The present invention is a method and apparatus for providing cryptographically secure algebraic key establishment protocols that use monoids and groups possessing certain algorithmic properties. Special fast algorithms associated with certain monoids and groups are used to optimize both key agreement and key transport protocols. The cryptographic security of the algorithms is based on the difficulty of solving the conjugacy problem in groups and other known hard algebraic problems. Braid groups and their associated algorithms are the basis for highly rapid key agreement and key transport protocols which employ modest computational resources.

1. Field of the Invention
The invention relates to algebraic key establishment protocols for cryptographic applications.
2. Description of the Prior Art
The concepts, terminology and framework for understanding cryptographic key establishment protocols is given in Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, xe2x80x9cHandbook of Applied Cryptography,xe2x80x9d CRC Press (1997), pages 490-491.
A xe2x80x98protocolxe2x80x99 is a multi-party algorithm, defined by a sequence of steps specifying the actions required of two or more parties in order to achieve a specified objective.
A xe2x80x98key establishmentxe2x80x99 protocol is a protocol whereby a shared secret becomes available to two or more parties, for subsequent cryptographic applications.
A xe2x80x98key transportxe2x80x99 protocol is a key establishment protocol where one party creates or obtains a secret value, and securely transfers it to the other participating parties.
A xe2x80x98key agreementxe2x80x99 protocol is a key establishment protocol in which a shared secret is derived by two (or more) parties as a function of information contributed by, or associated with, each of the participating parties such that no party can predetermine the resulting value.
A xe2x80x98key-distributionxe2x80x99 protocol is a key establishment protocol whereby the established keys are completely determined a priori by initial keying material.
A xe2x80x98dynamicxe2x80x99 key establishment protocol is one whereby the key established by a fixed pair (or subset) of the participating parties varies on subsequent executions. Dynamic key establishment protocols are also referred to as xe2x80x98sessionxe2x80x99 key establishment protocols, and it is usually intended that these protocols are immune from known-key attacks.
The Diffie-Hellman key agreement protocol (also called xe2x80x98exponential key exchangexe2x80x99) is a fundamental algebraic protocol. It is presented in W. Diffie and M. E. Hellman, xe2x80x9cNew Directions in Cryptography,xe2x80x9d IEEE Transaction on Information Theory vol. IT 22 (November 1976), pp. 644-654. The Diffie-Hellman key agreement protocol provided the first practical solution to the key distribution problem, allowing two parties, never having met in advance or sharing keying material, to establish a shared secret by exchanging messages over an open channel. The security rests on the intractability of the Diffie-Hellman problem and the related problem of computing discrete logarithms in the multiplicative group of the finite field GF(p) where p is a large prime, cf. Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, xe2x80x9cHandbook of Applied Cryptography,xe2x80x9d CRC Press (1997), page 113.
A key establishment protocol is said to have xe2x80x98perfect forward secrecyxe2x80x99 if compromise of long-term keys does not compromise past session keys. The idea of perfect forward security is that previous traffic is locked safely in the past. It may be provided by generating session keys by Diffie-Hellman key agreement, wherein the Diffie-Hellman exponentials are based on short term keys. If long-term secret keys are compromised, future sessions are nonetheless subject to impersonation by an active adversary (cf. Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, xe2x80x9cHandbook of Applied Cryptography,xe2x80x9d CRC Press (1997), page 496).
xe2x80x98Point-to-point key updatexe2x80x99 techniques based on symmetric encryption would make use of a long-term symmetric key K shared a priori by two parties A and B. The Diffie-Hellman key agreement protocol allows for the establishment of such a K. Thus, the Diffie-Hellman key agreement protocol together with the symmetric encryption system provide the primitives in specifying a key transport protocol (cf. Alfred J. Menezes, Paul C. van Oorschot, and Scott A. Vanstone, xe2x80x9cHandbook of Applied Cryptography,xe2x80x9d CRC Press (1997), page 497).
The definition of a monoid is given in Serge Lang, xe2x80x9cAlgebra,xe2x80x9d Third Edition, Addison-Wesley Publishing Company Inc. (1993), page 3.
Quote
Let S be a set. A mapping Sxc3x97Sxe2x86x92S is sometimes called a law of composition (of S into itself). If x, y are elements of S, the image of the pair (x, y) under the mapping is also called their product under the law of composition, and will be denoted xy . . . . Let S be a set with a law of composition. If x, y, z are elements of S, then we may form their product in two ways: (xy)z and x(yz). If (xy)z=x(yz) for all x, y, z in S then we say that the law of composition is associative.
An element e of S such that ex=x=xe for all x xcex5 S is called a unit element.
A unit element is unique, for if exe2x80x2 is another unit element, we have e=eexe2x80x2=exe2x80x2 by assumption. In most cases, the unit element is written simply 1 (instead of e) . . . .
A monoid is a set G, with a law of composition which is associative, and having a unit element (so that in particular, G is not empty).
Unquote
The definition of a group is given in Serge Lang, xe2x80x9cAlgebra,xe2x80x9d Third Edition, Addison-Wesley Publishing Company Inc. (1993), page 7.
Quote
A group G is a monoid, such that for every element x xcex5 G there exists an element y xcex5 G such that xy=yx=e. Such an element y is called an inverse for x. Such an inverse is unique. . . We denote this inverse by xxe2x88x921.
Unquote
The basic reference for concepts, terminology, and historical framework in combinatorial group theory is the monograph by Bruce Chandler and Wilhelm Magnus, xe2x80x9cThe history of combinatorial group theory: a case study in the history of ideas,xe2x80x9d Springer-Verlag (1982). We quote from page 3:
Quote
Combinatorial group theory may be characterized as the theory of groups which are given by generators and defining relations, or, as we would say today, by a presentation.
Unquote
The following problems were posed by M. Dehn in 1911. We quote from the monograph by Bruce Chandler and Wilhelm Magnus, xe2x80x9cThe history of combinatorial group theory: a case study in the history of ideas,xe2x80x9d Springer-Verlag (1982), page 19.
Quote
The Word Problem (called Identitaetsproblem by Dehn) Let an arbitrary element of the group be given through its buildup in terms of the generators. Find a method to decide in a finite number of steps whether this element equals the identity element or not.
The Conjugacy Problem (called Transformationsproblem by Dehn) Any two elements S and T of the group are given. Find a method to decide whether S and T are conjugate, i.e. whether there exists an element U of the group which satisfies the relation S=UTUxe2x88x921.
Unquote
The comparison form of the word problem can be stated as follows:
Comparison Form of the Word Problem Let u, v be any two elements of the group given. Find a method to decide in a finite number of steps whether u=v.
Assume that G is a group given by a presentation P(G). Let W(G) denote the set of all words in the generators and their inverses given in the presentation of G. The functional form of the word problem is to produce a mapping F from W(G) to W(G) such that for all u, v xcex5 W(G) it follows that F(u)=F(v) if and only if u, v define the same element of G with respect to the presentation P(G). For each element u xcex5 W(G) the element F(u) is termed the canonical form of u.
The functional form of the word problem requires an algorithm to produce canonical forms.
The Canonical Form Problem Let u be an arbitrary element of the given group. Specify a method to find, in a finite number of steps, a canonical form for u.
The functional form of the conjugacy problem requires, in addition, an algorithm to actually produce the conjugating element U.
Generalized Conjugacy Problem (functional form) Let S1, S2, . . . , Sn be elements of a group G. Assume that a xcex5G is secret and the set of n pairs of elements of the group G
{s1,axe2x88x921s1a},{s2,axe2x88x921s2a}, . . . {sn,axe2x88x921sna}
are publicly announced. Find an algorithm to actually produce such an element a.
It is self evident that this problem is harder than the original conjugacy problem. It has been known for some time that there exist groups with solvable word problem and unsolvable conjugacy problem. For example, in D. J. Collins and C. F. Miller III, xe2x80x9cThe conjugacy problem and subgroups of finite index,xe2x80x9d Proc. LMS Series 3, 34, (1977), p. 535-556) it is shown that there exist finitely presented groups G with solvable word problem which contain a subgroup H of index 2 with an unsolvable conjugacy problem. (Of course, the word problem for H is solvable.)
The discrete logarithm problem for a finite cyclic group of order p (a large prime) provides a bridge from combinatorial group theory to cryptographic protocols. A finite cyclic group of order p can be realized as the set of integers coprime to p modulo p, i.e., the finite set of integers {1, 2, . . . , pxe2x88x921} which forms a group under multiplication modulo p. Given fixed integers a, b xcex5{1, 2, . . . , pxe2x88x921}, where a is a primitive root modulo p, the discrete logarithm problem is to find an integer x (with 1xe2x89xa6xxe2x89xa6pxe2x88x921) such that
b=ax(mod p).
Another realization of a finite cyclic group of order p can be specified by a presentation with one generator a and one defining relation ap=1 where 1 denotes the identity element. Note that every element g of the group has a unique canonical form g=ax where x is an integer between one and p. It is clear that the discrete logarithm problem for a finite cyclic group of order p is thus identical to the canonical word problem for this group with respect to an arbitrary primitive element a.
The present invention employs the problems and algorithms of combinatorial group to create novel cryptographically secure algebraic key establishment protocols. More specifically, the cryptographic security of these protocols depend on the existence of groups with feasible word problem and hard conjugacy problem. Such an approach does not exist in the prior art.
It is the primary object of the present invention to provide novel cryptographically secure algebraic key establishment protocols based on a key establishment algebraic system KEAS.
Let (U, xcex8U) denote a monoid whose generating set {u1, u2, . . . } is enumerable and whose law of composition
xcex8UUxc3x97Uxe2x86x92U
is feasibly computable. Let (V, xcex8V) denote another such monoid. A KEAS is a five-tuple (U, V, xcex2, xcex31, xcex32) where
xcex2:Uxc3x97Uxe2x86x92V,xcex3i:Uxc3x97Vxe2x86x92V(i=1,2)
are feasibly computable functions satisfying the following properties.
(i) For all elements x, y1, y2xcex5U
xcex2(x,xcex8U(y1,y2))=xcex8V(xcex2(x,y1),xcex2(x,y2))
(ii) For all elements x, y xcex5 U
xcex31(x,xcex2(y,x))=xcex32(y,xcex2(x,y))
It is an object of the present invention to provide an apparatus which can perform monoid multiplication for KEAS.
It is an object of the present invention to provide a novel algebraic key agreement protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where U=V=G is a group.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key agreement protocol whose security is based on the existence of groups whose word problem can be solved in polynomial time while no polynomial time algorithm to solve the generalized conjugacy problem is known.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key agreement protocol which is based on the computation of a list of randomly rewritten conjugates in a group, thus reducing the steps and calculations in executing the protocol. This allows for easy implementation of the algorithms on low level computing devices with table driven modules.
It is an object of the present invention to provide an algebraic key agreement protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where U=V=G is the braid group.
It is an object of the present invention to provide an apparatus which randomly rewrites a word in the braid group in linear time in the word length.
A key transport protocol is an algorithm, initiated by an input, defined by a sequence of steps, which enables one party to securely transfer a key to another party. The key transport protocol is said to run in polynomial time if the number of steps required to transfer the key is a polynomial in the bit length of the input. If the polynomial is of the first degree, the key transport protocol is said to run in linear time.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key transport protocol based on KEAS which allows for a linear time secure transfer of an encrypted key and requires polynomial time decryption of said encrypted key.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key transport protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where U and V are monoids and U acts on a message space. The key transport protocol is a combination of the algebraic key agreement protocol based on KEAS, together with an apparatus which efficiently compares members of the message space. This allows for linear time secure transfer of an element of the message space and requires a polynomial time algorithm for comparison and retrieval of the message.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key transport protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where the message space=U=V is the braid group which acts on itself by multiplication. This allows for the linear time secure transfer of an element of the message space (randomly rewritten word in the braid group) and requires a polynomial time algorithm to obtain a canonical form and decrypt the message.
It is an object and feature of the present invention to provide a cryptographically secure algebraic key transport protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where the message space=U=V is the braid group which acts on itself by conjugation. This allows for the linear time secure transfer of an element of the message space (randomly rewritten word in the braid group) and requires a polynomial time algorithm to obtain a canonical form and decrypt the message.
It is an object of the present invention to provide a cryptographically secure algebraic key transport protocol based on KEAS=(U, V, xcex2, xcex31, xcex32) where U=V is the braid group and the message space is a free group.
The system according to the invention is particularly suited towards implementation using currently available digital technology, commercially popular microprocessor based systems, and other affordable digital components. Significant portions of the system may be implemented and significant portions of the method according to the invention may be performed by software in a microcomputer based system. Moreover the system is quite suitable for implementation on emerging computer technologies, e.g., quantum computers.

Method and apparatus for cryptographically secure algebraic key establishment protocols based on monoids


A method and apparatus for analyzing traffic arriving at and/or departing from a traffic aggregate defined as a given IP-related protocol, a given port associated with a given protocol, an IP address or subset of IP addresses, or by other traffic aggregation, during a given time interval, to determine whether there is a significant increase or decrease in traffic aggregate's traffic volume as compared to the traffic aggregate's expected traffic volume are disclosed. In one embodiment, the present method defines a traffic share ratio threshold associated with a given protocol or a given protocol port or a given IP address or a given subset of IP addresses or other traffic aggregation using said collected volumetric traffic data. The present method also defines a current traffic share, a baseline traffic share and a traffic share ratio to be evaluated for the said traffic aggregate. In turn, the present method raises an alarm if the traffic aggregate's traffic share ratio to be evaluated exceeds or falls below the traffic share ratio threshold defined for the traffic aggregate.

In order to detect excessively high traffic volumes that may be malicious, traffic thresholds for alarming on spikes in flow, packet or byte traffic arrivals at and/or departures from a given IP protocol, a given port associated with a protocol, a given IP address or subset of IP addresses, or other traffic aggregations, need to be properly defined and monitored. These thresholds are protocol-specific, specific to a port and protocol, IP address-specific, or specific to other traffic aggregations. For instance, if large volume of suspicious traffic that deviates from, whether the suspicious traffic is a significant increase or decrease when compared to the regular traffic pattern, the regular traffic pattern for a particular IP protocol, a particular port associated with a protocol, a particular IP address or subset of IP addresses, or other traffic aggregation is detected, the network needs to be able to raise an alarm to warn the network operator of the potential problem so that the appropriate actions can be taken to mitigate any potential risks.
Therefore, a need exists for a method and apparatus for volumetric thresholding and alarming in a packet network, e.g., an IP network.

Method and apparatus for volumetric thresholding and alarming on internet protocol traffic


One step of the present method involves making an across ante and a down ante and an optional five card poker bet. Other steps involve making an across bet or folding, making a down bet or folding, and making a middle bet or folding. All winning bets are paid out against a designated payout table for that bet. A winning middle bet is paid to the higher of the two five card poker hands formed by the players two dealt cards and either the three across community cards or the three down community cards. A winning five card bonus bet is paid to a winning five card poker hand formed by the five community cards forming the cross. The method may be played on criss cross poker layouts on actual or simulated casino card tables or on electronic devices.

Field of the Invention
The present invention relates to casino card games and particularly to a method of playing a criss cross poker casino card game with an additional middle bet and an optional five card bonus using the same board cards as the criss cross poker game without altering the play of the criss cross poker casino card game.
Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
Gamblers enjoy side betting in games to double the opportunity of winning and just to have another opportunity to gamble. But there is also a need to preserve the integrity of the game being played to maintain the original unadulterated use of cards and play so that the original card game is not altered by the optional side betting game and that players can play the original casino card game without the optional side betting if they choose. Prior art casino card games related to criss cross poker, which provide a number of community cards dealt face down on a playing table to be combined with cards dealt to each player often provide two possible five card poker hands comprised of two different sets of community cards in combination with a players dealt cards. But none of the prior art games provide an optional extra side bet on the community cards themselves forming a winning hand. Prior art casino card games based on a criss cross type of configuration generally provide betting opportunities on player cards combined with one or the other of two different sets of community cards, but not the option of a third bet on both sets of community cards combined with the player cards that pays if either of the two combinations provide a winning hand.
Poker games played against other players and/or against a dealer hand add a level of difficulty and human judgment which complicates winning rather than just winning on the value of the cards themselves against a payout table. The payout table game provides a faster game and more certainty on the part of the player that a hand will pay off, even if the player lacks competitive play skill, and also does not depend upon how good or how bad the hands of the other players or the dealer may be.
U.S. Patent Application #US20120149451, published Jun. 14, 2012 by Nicely et al, discloses a gaming device which provides a single player poker game including one or more opportunities for forming player hands. In one embodiment, for a play of the poker game, a player places a wager on each of a plurality of player hands. The gaming device provides the player with one or more opportunities to fold one or more of the player hands and withdraw the wager associated with the folded hand. A number of community cards are dealt. The gaining device determines and provides any awards associated with a ranking of each of the remaining player hands according to a paytable.
U.S. Patent #62/048,267, issued Apr. 11, 2000 to Wichinsky, indicates a multiple hand stud poker game wherein a player wagers on one or multiple hands and using a single standard fifty-two card deck of playing cards. Three cards are dealt face up to each of the player hands. Two cards are then dealt—one face up and one face down—to be used as cards that can be selected by the player for use in the player's hand. The player selects either the face up card or the face down card. The selected card is added to the player's first hand and is displayed face up. The unselected card is then discarded. Two more cards are dealt—one card face up and one card face down. The player again selects either the face up card or the face down card. The selected card is added to the player's second hand and is displayed face up with the unselected card being discarded. Two more cards are dealt—one card face up and one card face down. The player again selects either the face up card or the face down card. The selected card is added to the player's third hand and is displayed face up with the unselected card being discarded. The same procedure is used to add a fifth card to each of the player's hands. This results in the player having three complete five card hands. The amount won by the player is based on the amount wagered by the player and the poker ranking of the player's hand based on a payout schedule.
U.S. Patent #6/042,118 issued to Poitra, describes a method of playing a poker-type game wherein the game provides the players an opportunity to increase the amount wagered based upon two of three community cards shown. After each player places a bet, two cards are dealt face down to each player and three cards are dealt face down to the dealer that are "community cards". The dealer then turns over two of the three community cards so that they are facing up. Each player has the opportunity to "double-down". The dealer then turns over the remaining community card and then turns over each player's two cards. The bets are resolved by using the three community cards in combination with each player's two cards based upon a predetermined plurality of winning card combinations similar to poker. The card deck is a standard 52 card deck with one joker to make a 53 card deck. The joker is utilized only in certain combinations as a 'wild card.
U.S. Patent Applications #US20050242506, published Nov. 3, 2005 and #US20120225706, published Sep. 6, 2012 both Mississippi Stud variations by Yoseloff, claim a card game played against a pay table, Wherein the player receives a partial hand that is preferably completed by community cards (but may be completed by cards dealt directly to a hand or a combination of cards dealt directly to a hand and at least one community card or Wild card). After placement of an Ante Wager, each player Will have an opportunity to place a game Wager before receiving another card for the player's hand (Whether dealt directly to the player or as a community card revealed to all players). At least some or all game Wagers may be an amount within a range of multiples of the player (such as 1×, 2×, 3× 4× or 5× the amount of the Ante Wager). The range of Wagers may remain the same or vary with the number of dealt cards or community card revealed to the players.
U.S. Pat. Nos. 5,489,101 and 5,531,448, issued to Moody, describe poker games in which a player attempts to form a five card poker hand that has the highest poker hand ranking. In the house banked version, all players play against the house and not against each other. The game is played with a standard fifty-two card deck. The game is played by a dealer and from one to seven players. Each player makes a bet and a portion of each bet may be allocated to a progressive jackpot. The dealer deals five cards to each player. The dealer then deals six cards as the community cards which are arranged face down in three rows in a triangle pattern on the gaming table layout. The players may discard from none to five unwanted cards. The dealer turns up the community cards and pre-designated groups of cards from the community cards are used for each player to make a complete five card poker hand. The dealer determines the best hand each player has made according to poker hand rankings. All winning hands will be paid by the dealer according to the odds listed in the pay table. When the progressive jackpot payout is used, the dealer examines the six community cards to determine if one of the predetermined card arrangements has occurred. Any winning payouts from the progressive jackpot are distributed to the players at the table. The method may also be played as a player banked game or as a pot game. In one version of the present invention, the dealer deals three cards to each player. The dealer then deals eight cards as the community cards which are arranged in groups or pairs of two cards each on the gaming table layout. In the preferred embodiment of the present invention, the card layout is in the format of a directional compass with a pair of cards each at the North position, East position. South position and West position, respectively.
U.S. Pat. No. 5,657,993, issued to Merlino, describes a method of playing a poker-type wagering game on top of a table layout having first and second player locations, a plurality of betting areas associated with each of the player locations and a community card area. The method includes a first player placing a wager on top of each of the betting areas associated with the first player location. A second player places a wager on top of each of the betting areas associated with the second player location. Each player receives two playing cards. A number of community cards are dealt face down in the community card area in a predetermined pattern. The number of community cards corresponds to the number of betting areas in one of the player locations. The faces of community cards are exposed in succession. Each time a community card is exposed, each of the players can either fold wherein the folding player loses a number of wagers which corresponds to the number of community cards exposed or the players can leave all of the wagers on the corresponding betting areas until all of community cards are exposed. Once all of the community cards are exposed, each of the players combines his or her pair of cards with three of the community cards to form a completed stud poker hand. The player with the highest ranking hand wins all of the wagers.
U.S. Pat. No. 5,975,529, issued to de Keller, describes a poker game played on a blackjack style table with a single dealer. The player opening the betting is rotated for each game. The game is played with chips/counters of various denominations. At the start of each game all players place a bet of equal value in their respective pots. Players then place Bet 1 (the maximum and minimum value thereof being determined by the house) and each player is dealt two cards (this number may vary), face-down, and the dealer receives three cards (this number may vary) one face-up and two face-down. The three dealer's cards are community cards, referred to as the 'flop' and complete each player's hand. The players, at this stage know the identity of three cards and each player has the option of discarding their first or second card, or both, face down. Replacements, face-down, are received for discards. Players may at this stage, either 'stand' by making no further bets or 'raise' by wagering on Bet 2. The Bet 2 wager must be exactly equal in value to the amount wagered on Bet 1. When all wagers have been placed on Bet 2 the fourth card is revealed by the dealer. Players may again either stand at this stage or raise by wagering on Bet 3. Players are not permitted to make a third bet if they have not placed the second. The Bet 3 wager must be exactly equal in value to the amount wagered on Bet 1. When all third bets have been placed the dealer turns up the fifth card. Each player reveals his/her cards and provided they show a winning hand on the list of poker rankings hands are paid according to the total stake placed at the corresponding pay-offs/odds. The player with the highest poker hand is awarded all the Pot bets; in the event of players holding identical hands the Pot is shared. No matter how many cards constitute community cards or how many cards are dealt to each player, the players select five cards to make up their hands. There is no variation in wagering allowed, and competition includes wagers against the pot.
What is needed is a method of playing a criss cross poker casino card game combined with an additional middle card bet and an optional five card poker bonus bet wherein a player competes solely against posted payout tables and the additional and optional bets use the same cards as the criss cross poker casino card game without interfering with the regular play of the criss cross poker casino card game.

Criss cross poker casino card game with middle bet and five card bonus bet


A method and apparatus are disclosed for management of linked lists within a dynamic queue system. In a dynamic queue system where a central memory is shared amongst a set of queues, the method organizes the linked list structures of the queues. The linked list pointers of the queues are organized over a set of single port memories. Memory for the queue entries is allocated in an alternating fashion, which allows the method to provide per-cycle access to queues while reducing the footprint of the memory elements used for maintaining the linked list structures. The method disclosed reduces the overall memory requirements for the design and implementation of queue systems with multiple queues sharing a common pool of memory.

Typical queuing systems contain multiple queues, which a user can access by pushing data onto a queue or popping data from a queue. The more complex queuing systems typically have a common pool of memory shared amongst all or a group of queues. The common pool of memory is used for storing queue entries as they are pushed onto individual queues. One flexible approach is for the common pool of memory to be managed dynamically.
In a dynamic queue system, the common memory locations that are available for use by queues are tracked and managed. This tracking mechanism is sometimes referred to as the free list or free queue. Dynamic queue systems usually support two queue operations: push and pop. A push operation will add an entry to a queue, while a pop operation will remove an entry. A push operation will cause memory to be de-allocated from the empty list and allocated to the particular queue. The data which is being pushed onto the queue is then stored at the newly allocated memory location. A pop operation returns the data from the queue, and the common memory pool in which the data is stored is then de-allocated from the queue and re-allocated to the free list.
With dynamically allocated memory, individual queues are formed by a linked list. For every queue entry, there is a pointer to the next entry in the queue. Each queue typically has a read and write pointer for the start and end of the linked list. The locations in the common pool which are not allocated to a particular queue are maintained as part of a separate linked list, with its own write and read pointer, or a simple head of stack pointer. Either way this is usually called the free list. Another method is to use a separate dedicated first in first out (FIFO) memory where the addresses of the un-allocated common memory are stored within an array.
FIG. 1 depicts a classic singly linked list queue structure, indicating a typical relationship between queue data 10, queue entries 12 and pointers 14. As shown in FIG. 1, the reference numeral 14 is used generically refer to a number of different types of pointers, such as: a read pointer; pointer to next; and write pointer.
FIGS. 2 and 3 depict physical and logical views, respectively, of a typical dynamic queue system with a linked list memory 16, a common memory pool 18 and the queue pointers: read 20, read next 22, and write 24, with queue pointers of each type being provided for each queue. The linked list memory 16 and common memory pool 18 are typically implemented as a single port random access memory (RAM), while the queue pointers 20, 22 and 24 are either register-based or stored in a RAM. In this example, the linked list memory 16 and common memory 18 each have eight memory locations addressed: A0, A1 to A7. Because every entry in the common memory pool 18 must have a pointer to the next entry, the linked list memory 16 and common memory 18 are required to have equal number of locations.
When allocated to a particular queue, a common memory pool location contains a queue entry. FIGS. 2 and 3 illustrate two queues: Queue 1 26 and Queue 2 28. When un-allocated, a common memory pool memory location is part of the free list 32, shown in FIG. 3. In this example, the start address of the free list is held in a stack pointer register 30 shown in FIG. 2. The physical view of FIG. 2 shows the memory contents, and the logical view of FIG. 3 displays the links from one entry to the next with respect to Queue 1 26, Queue 2 28 and Free List 32.
FIGS. 4 and 5 show physical and logical views, respectively, of a push operation performed on the typical dynamic queue system of FIG. 2. In such a system, the following memory operations are needed for a queue push operation:
Step 34: A read of the queue read/write pointer memory 20, 22, 24 is needed to retrieve the read and write queue pointers of the queue being operated on. This step is sometimes not needed as the queue pointers can be stored in registers instead of RAMs.
Step 36: Write the new queue entry 38 into the common memory 18. The free list stack pointer value 30 is used as the address to the common memory where the queue entry is to be written. This is typically a 1 cycle write operation to the common memory. As the stack pointer is stored in a register, the address for common memory is immediately available.
Step 40: Update the free list 32 by removing the newly allocated common memory. This is done by reading the linked list memory to get the next item in the free list and updating the free list stack pointer 30. This is typically a 1 cycle read operation of the linked list memory 16. The stack free list stack pointer register is then updated on the next cycle.
Step 42: Update the queue write pointer 24 with the current contents of the vacant stack pointer register 30. This effectively moves the write pointer to the latest entry in the queue. This is typically a 1 cycle write operation to the queue read/write pointer memory.
Step 44: Update the queue linked list 16 with the pointer to new entry. This takes the last entry currently in the queue and creates a link to the newly pushed data, effectively increasing the linked list by one. This is typically a 1 cycle write operation to the linked list memory at the address pointed to by the current write pointer.
FIGS. 6 and 7 show physical and logical views, respectively, of a pop operation performed on the typical dynamic queue system of FIG. 2. The following memory operations are needed for a queue pop operation:
Step 46: A read of the queue read/write pointer memory 20, 22, 24 is needed to retrieve the read and write queue pointers of the queue being operated on. This is sometimes not needed as the queue pointers can be stored in registers instead of RAMs.
Step 48: Read the queue entry from the common memory pool 18 using the queue read pointer 20 for queue 1 as the address to the common memory. This is a 1 cycle read operation of the common memory.
Step 50: Update the read pointer 20 for queue 1. The next read pointer value is written into the current read pointer register. This is a 1 cycle write operation into the read pointer register.
Step 52: Update the next read pointer 22 for queue 1. The linked list memory 16 is read to retrieve address of the entry following the next read pointer. The next read pointer value is used as the address to the linked list memory and the data returned is written into the next read pointer register 22. This is a 1 cycle write operation into the next read pointer register, and a 1 cycle read operation of the linked list memory.
Step 54: Place the newly un-allocated memory at the top of the free list stack 32. The stack pointer 30 is updated with the current read pointer value. This is a 1 cycle write operation into the free list stack pointer register.
Step 56: The linked list value of the newly un-allocated memory is updated to point to the next entry in the free list. The read pointer value is used as the address to the linked list memory and the data written is the current value of free list stack pointer.
It is important to note that dynamic queue system implementations are usually pipelined. Therefore, many of the memory transactions previously described will occur concurrently. Because the memory transactions are pipelined, a push or pop operation will always encounter latency in completing. Regardless of latency, for maximum performance of a dynamic queue system, the system must complete a push or pop operation at every clock cycle.
Each push or pop queue operation requires one transaction to the common memory pool and two transactions to the linked list memory. Typical hardware implementations will use a single port RAM or a bank of single port RAMs for the common pool memory. The selection of RAM for the linked list memory is more critical as the two memory transactions are required. The least costly storage in terms of area utilization is to use a single port RAM for the linked list memory, but the performance impacts are such that the system would be limited to one push or pop operation every two clock cycles.
Alternatively some systems utilize register based storage for the linked list. This option is feasible for systems that provide only a small amount of queue storage. For larger dynamic queue systems, a register based approach does not provide the density when compared to RAMs.
One more approach is for the linked list memory to use a dual port RAM as these can perform both a read and write within the same clock. This meets the performance goals. However, again the hardware area of the linked list storage can quickly approach the footprint of common pool memory, making such a system very costly and effectively mitigating some of the advantages of a dynamic queue system. In these situations it can take more hardware resources to maintain the linked list storage then the actual queue entries themselves.
For ASIC (Application Specific Integrated Circuit) based implementation, queuing systems are required to be flexible and high performance while minimizing hardware resources. To maximize bandwidth, queues should be accessible for push and pop operations at every clock cycle.

Management of linked lists within a dynamic queue system


A health-promoting insole includes bamboo charcoal powder mixed with filament fibers. Via the bamboo charcoal powder added at the upper and bottom layers of the insole, the insole thereof is equipped with strong moisture absorbent capabilities as well as anti-bacteria and deodorization effects.

The present invention is related to a health-promoting insole, including an upper layer with hollow support rings densely arranged thereon, a bottom layer, and bamboo charcoal powder added at the upper and bottom layers therein respectively wherein the upper and bottom layers are mutually bound together via fastening agent and pressed into insoles of various sizes and shoe shapes; whereby, the insole thereof is equipped with strong absorbing and decomposing capabilities as well as anti-bacteria, humid-adjustment, and deodorization effects.
A conventional insole for shoes is not equipped with anti-bacteria or strong moisture absorbing and deodorizing capabilities. Though designed with an airy effect, the conventional insole is unable to adjust humidity and defeat bugs. Once shoes are taken off after a long time of wearing, the conventional insoles therein easily disperse a bad smell of feet. Therefore, such a conventional insole for shoes, which is rather poor in deodorization, is significantly reduced in the quality thereof.


An embedded multimedia card (eMMC) includes a clock channel receiving a clock from a host, a complementary clock channel receiving a complementary clock from the host, a command/response channel exchanging commands/responses with the host, a plurality of data channels exchanging data between the host and the eMMC, a return clock channel sending a return clock to the host synchronously with data, a complementary return clock channel sending a complementary return clock to the host, and a reference voltage channel that either receives a reference voltage from the host or communicates a reference voltage to the host.

The inventive concept relates to embedded multimedia card(s) (eMMC), and more particularly, to eMMC having structures and functionality that support a 200 MHz dual data rate (DDR) mode of operation. The inventive concept also relates to hosts controlling this type of eMMC, as well as eMMC systems.
The so-called multimedia card (MMC) is a flash memory card standard. The eMMC is an embedded MMC standard defined by the Joint Electron Devices Engineering Council (JEDEC). In general configuration and application eMMCs are designed to be inserted (or "embedded") in conjunction with a host within mobile communication devices such as smart phones. Conventionally, the eMMC communicates data signals, control signals, commands, clock(s) and/or power signals with the connected host in accordance with a standardize ten (10) signal line bus.

This patent is subject to a terminal disclaimer.

Embedded multimedia card (eMMC), host for controlling eMMC method operating eMMC system


A telecommunications assembly including: a connector housing; a bezel mounted on the connector housing, the bezel have a front face having an opening for receiving a plug, the opening having a recess for receiving a plug latch; a faceplate having a faceplate opening of a standard dimension; wherein the bezel is mountable in the faceplate opening in a flat orientation with the recess positioned downwards and the bezel is mountable in the faceplate opening in an angled orientation with the recess positioned upwards.

Telecommunications connectors come in a variety of mounting configurations. For example, telecommunications outlets may be of a flat-type, meaning the outlet opening is parallel to the face of the faceplate. Telecommunication outlets may also be of an angled-type, meaning the opening of the outlet is positioned at an oblique angle relative to the face of the faceplate. Also, there exists in the art a keystone-type outlet which mounts in a defined type of faceplate opening resulting in a flush mounted, clean look preferred by some consumers.
Supplying connectors in all the major mounting configurations is a complicated endeavor for a supplier. Existing connectors use substantially different housings for flat, angled and keystone connectors. As the housings vary from one type of connector to the next, the manufacturer must stock or wide variety of complete connectors. Existing connectors may be color-coded. As the color-code is dictated by the connector housing, the manufacturer must know the appropriate color-code early in the manufacturing process. Further, different colored plastics have different properties (e.g., conductance) and thus molding connector housings from different colored plastic resins can lead to performance variations.
Thus, there is a need in the art for improved mounting mechanisms for telecommunications connectors.

Telecommunications connectors and apparatus for mounting the same


A target power value determining unit determines target power values Pc1* and Pc2* such that a sum SPc* of target load powers as a sum of target load power Pc1* and target load power Pc2* does not exceed a sum SWin of allowable charging powers and a sum SWout of allowable discharging powers. In accordance with the generated target load power values Pc1* and Pc2*, switching commands PWM1 and PWM2 are generated. Consequently, an inverter executes a power conversion operation such that the powers exchanged between a main line ML and motor generators attain to the target load power values Pc1* and Pc2*, respectively.

Recently, in consideration of environmental issues, vehicles using electric motors as driving sources, such as electric vehicles, hybrid vehicles and fuel cell vehicles are attracting attention. Such a vehicle is provided with a rechargeable power storage unit for supplying power to the electric motor and for converting kinetic energy to electric energy and storing the same at the time of regenerative braking.
In the vehicle having an electric motor as the driving source as described above, power supply of larger capacity is desirable in order to improve running performance such as acceleration characteristic and mileage per charge. As a method of increasing power supply capacity, provision of a plurality of power storage units has been proposed.
By way of example, U.S. Pat. No. 6,608,396 discloses an electrical motor power management system providing a desired high DC voltage level in a high-voltage vehicle traction system. The electrical motor power managements system includes: a plurality of power stages for providing DC power to at least one inverter, each stage including a battery and boost/buck DC-DC converter, and wired in parallel; and a controller controlling the plurality of power stages such that the batteries of the plurality of power stages are uniformly charged/discharged whereby the battery voltage to the at least one inverter is maintained by the plurality of power stages.
The power storage unit storing electric energy utilizing electro-chemical reaction has a maximum allowable power that can be charged and discharged (hereinafter referred to as the allowable power) defined in accordance with its state of charge. The allowable power represents a limit value for protecting each electric storage unit against excessive degradation.
On the other hand, in determining a driving force required in accordance with the state of running of the vehicle, the allowable power as such is not considered, and main focus has been on the optimization among the plurality of power storage units for sharing the driving force determined in accordance with the state of running. For instance, in the electrical motor power managements system of U.S. Pat. No. 6,608,396 mentioned above, what is disclosed is only a structure for actively distributing predetermined load power source as a whole.
Therefore, if a target value of driving force is set exceeding the allowable range of power supply or power regeneration of the plurality of power storage units as a whole, excessive degradation possibly occurs in each of the power storage units, or drivability (driving characteristic) possibly lowers.

Driving force generation system, vehicle using the system, and method for controlling the system


A modular orthopaedic implant system has first, second and third implant components. Two of the components have bores and the third component has a post. The third component can be assembled with either the first or second components with the post received in the respective bore of the other component. When assembled, the length of the post received within the bore of one of the components is greater than the length of the post received within the bore of the other component. The fatigue strength of the assembly with a greater length of the post received within the bore is greater, and this assembly can be used where such greater fatigue strength is needed and the other assembly can be used where a lesser fatigue strength is needed. Since the third component that is used in both assemblies may be the same, inventory may be reduced.

The knee joint basically consists of the bone interface of the distal end of the femur and the proximal end of the tibia. Appearing to cover or at least partially protect this interface is the patella, which is a sesamoid bone within the tendon of the long muscle (quadriceps) on the front of the thigh. This tendon inserts into the tibial tuberosity and the posterior surface of the patella is smooth and glides over the femur.
The femur is configured with two knob like processes (the medial condyle and the lateral condyle) which are substantially smooth and which articulate with the medial plateau and the lateral plateau of the tibia, respectively. The plateaus of the tibia are substantially smooth and slightly cupped thereby providing a slight receptacle for receipt of the femoral condyles.
When the knee joint is damaged whether as a result of an accident or illness, a prosthetic replacement of the damaged joint may be necessary to relieve pain and to restore normal use to the joint. Typically the entire knee joint is replaced by means of a surgical procedure that involves removal of the surfaces of the corresponding damaged bones and replacement of these surfaces with prosthetic implants. This replacement of a native joint with a prosthetic joint is referred to as a primary total-knee arthroplasty.
On occasion, the primary knee prostheses fails. Failure can result from many causes, including wear, aseptic loosening, osteolysis, ligamentous instability, arthrofibrosis and patellofemoral complications. When the failure is debilitating, revision knee surgery may be necessary. In a revision, the primary knee prosthesis is removed and replaced with components of a revision prosthetic knee system.
Knee implant systems for both primary and revision applications are available from a variety of manufacturers, including DePuy Synthes Products, LLC of Warsaw, Ind. DePuy and others offer several different systems for both primary and revision applications. For example, DePuy Synthes Sales, Inc. offers the P.F.C. SIGMA® Knee System, the LCS® Total Knee System, and the S-ROM Modular Total Knee System. These orthopaedic knee systems includes several components, some appropriate for use in primary knee arthroplasty and some appropriate for use in revision surgery.
DePuy Synthes Sales, Inc. also offers other orthopaedic implant systems for other applications. One such system is the LPS System. The LPS System is provided for use in cases of severe trauma and disease. In such cases, the trauma or disease can lead to significant amounts of bone loss.
These systems include modular components, allowing the surgeon to construct an implant that meets the needs of the individual patient. Some combinations include modular stem extensions for use in conjunction with a distal femoral implant component, a proximal tibial implant component, or metaphyseal sleeves that may be used with such femoral and tibial implant components.
Although these prior knee implant systems have provided surgeons with great flexibility in meeting patient needs, and the modularity of these systems provides the opportunity to reduce the number of components needed in a surgical kit, these systems still require a substantial number of components.
In these assemblies of modular components, the fatigue strength of the components at their connections is important in ensuring the longevity of the assembly in use, and the characteristics of the connection components, and in particular, the dimensions of the connection components, are significant in ensuring that the assembly has an appropriate fatigue strength. However, the loading requirements for different assemblies may vary; for example, the loading requirements for the connection between a femoral stem connection may be greater than the loading requirements for a tibial stem connection. If the geometry of the connection of the tibial components satisfies the fatigue strength loading requirements for tibial loading, this same geometry may not satisfy the fatigue strength loading requirements for femoral loading. Moreover, if the connection includes a metaphyseal sleeve, the loading requirements may further differ. If the connections are optimized for the maximum anticipated loads, then the design may not meet other constraints; for example, design constraints for the tibial components may not allow for use of a connection that is optimum for the femoral components. Therefore, different components may be required for use on the femoral and tibial sides; for example, different stem configurations may need to be provided for use with the femoral and tibial components. Since multiple sizes of components are also required, duplicates of each size of stem may be required, substantially increasing the number of components in each set of implants provided to the surgeon.
Accordingly, a need exists for a modular prosthesis system that optimizes the fatigue strength of each modular connection while allowing for a more limited number of components required in each implant set provided to the surgeon.

Modular knee prosthesis system for use with different load requirements


In a vacuum housing (1), an inner duct (17) is disposed. Quadrupole magnets (superconducting coils) (4) is placed around the inner duct (17) is excited by a DC power supply (10). Quadrupole magnets (4) are cooled by liquid helium contained in a helium housing and outer tubes (2, 3) and is brought into a superconducting state. Pulverized coal X is ejected together with air Y from a header (11) through piping (12) and a valve (13) to a baffle plate (14). Pulverized coal is made to fall into the inner duct (3). Paramagnetic materials such as ash are attracted by magnetic force to the tube and are then collected by a collection tube (26). Combustible diamagnetic materials are collected by a combustible collecting tube (18) extending in the central axis. Intermediate materials are collected by an intermediate collection tube (23) and are put back to the head (11) through a bypass tube (25). There are no mechanical parts in the inner duct (3). Consequently, rotation loss and eddy-current heating are prevented.

1. Field of the Invention
The present invention relates to a magnetic separator (namely, a magnetic separation apparatus) used for coal cleaning and to a pulverized coal combustion (or firing or burning) apparatus using the magnetic separation apparatus (or system).
2. Description of the Related Art
FIG. 9 is a diagram illustrating the principle of magnetic separation, which shows the distribution of lines of magnetic force of quadrupole magnets and the magnetic field strength distribution in an inner duct thereof. In this figure, reference numeral 40 designates quadrupole magnets that have a quadrupole structure provided in a circle therein. The lines 41 of magnetic force are generated by this magnet 40. Here, let (dH/dZ), H, X and V denote magnetic field gradient, magnetic field strength, magnetic susceptibility and the volume of a fine particle, respectively. Magnetic force Fm given by the following equation (1) acts in the direction of the magnetic field gradient: EQU Fm=.chi..mu..sub.o VH(dH/dZ) . . . (1)
Incidentally, in the aforementioned equation (1), .mu..sub.o denotes an absolute permeamibility of vacuum. Magnetic separation is performed by utilizing a variation in this magnetic force, which is caused due to a change in the magnetic susceptibility of this fine particle. As illustrated in FIG. 9, the magnetic force Fm given by the aforementioned equation (1) acts upon a fine particle contained in the inner duct 42 of the four-pole magnet 40. Variation in this magnetic force results in a change in the position in the Z-direction of each fine particle, so that the magnetic separation is achieved.
FIG. 10 is a diagram conceptually illustrating a section of a conventional magnetic separator employing such a principle of magnetic separation and illustrates an apparatus 110 for separating a dry paramagnetic material from a dry diamagnetic fine-grain material. Hereinafter, this apparatus will be described in detail.
A wall 114 and an inner space 116 vertically extend in the axial direction of the apparatus and thus compose a cylinder 112. Rotary screw 118 is installed in the cylinder 112. The screw 118 consists of the shaft 120 and a helical blade 122. The helical blade 122 is angled downwardly in both of the radial and axial directions and is accommodated inside the wall 114. The screw 118 is connected to a motor 124 and is rotated by this motor 124, so that fine particles are carried from the top portion of the screw 118 downwardly. A vibration drive or exciter (namely, a shaker) 126 is connected to the screw 118. The screw 118 is shaken during the rotation thereof.
A magnet 128 is disposed around the wall of the cylinder 112. This magnet 128 acts the magnetic field in the inner space 116. Thus, there is constructed a four-pole magnet, by which the magnetic field gradient is given in the inner space 116. The magnetic field (strength) has a maximum value on the wall 114. Further, the magnetic field strength at a point decreases as the point approaches the shaft 120. This magnetic field is constant in a central zone 129. In an edge portion 132, the magnetic field decreases linearly in the upward direction from an edge 132 of the magnet 128.
To enhance the separation ability or performance, a pulverizer 134 is used. Pulverized coal is sent by an auger 136 to a movable coal feeder 138. Then, the pulverized coal is sent from the coal feeder 138 to the helical blade 122. Rotation of the screw 18 brings the pulverized coal into the apparatus 110.
Paramagnetic fine particles of kaolinite and ash undergo the magnetic force Fm illustrated in FIG. 9 and move toward the wall 14, while fine particles of combustible (organic) content contained in the coal, which are diamagnetic fine particles, move along the direction of the shaft 120.
A splitter 142 is provided in a lower portion of the apparatus 110 and is composed of three concentric cylinders or tubes 144, 146 and 148. The tube 144 collects fine particles (incidentally, major constituents thereof are diamagnetic fine particles), which approaches the shaft 120. The tube 148 collects fine particles (incidentally, major constituents thereof are paramagnetic fine particles), which approaches the wall 114. The tube 146 collects a mixture of antimagnetic and paramagnetic fine particles.
The aforementioned conventional magnetic separator 110 has the following problems:
(1) Mechanical drive parts such as the screw 118, the rotary shaft 120, the motor 124, the vibration exciter 126 and the helical blade 122 are provided in the inner duct of the quadrupole magnet, so that the clogging thereof owing to the fine particles and the abrasion thereof occur. PA1 (2) Residual magnetization occurs in machine parts with the result that the fine particles adhere to the blade and so forth. Consequently, the separation performance is degraded. PA1 (3) Leakage current occurring in the rotating parts results in the generation of heat and in the occurrence of rotation loss. PA1 (4) When using a superconducting magnet in the case that electric current is directly supplied to the quadrupole magnets from the power supply, losses occur in an electric lead and in a normal conducting part of the power supply. Further, in the case of using the normal conducting magnet, losses are produced in the entire system. PA1 (5) In the case that the aforementioned conventional magnetic separator 110 is applied top as an apparatus of separating combustible (organic) materials from incombustible materials (such as pearlite, kaolinite and ash), if this magnetic separator is provided separately from a combustion apparatus, there is the necessity of labor and space for the storage, retention and conveyance of separated materials. Consequently, the cost of the magnetic separator is increased. PA1 (1) Namely, there is provided a magnetic separator (hereunder sometimes referred to as a first magnetic separator of the present invention) which comprises a cylindrical inner duct disposed along the vertical direction; quadrupole magnets constituted by superconducting coils, which are placed around the aforesaid inner duct and are cooled by liquid helium and are excited by use of a DC power supply; fine-particle supply means for ejecting and dropping fine particles, which consist of a plurality of elements and compounds, from a top end of the aforesaid inner duct; and first and second collection tubes, which are provided at a bottom portion of the aforesaid inner duct, for separating and collecting a paramagnetic material and a non-magnetic material, which are included in the aforementioned fine particles, owing to a difference between magnetic forces respectively acted on the aforementioned fine particles, which are ejected from the aforementioned fine particle supply means and drop. PA1 (2) Further, in the case of an embodiment (hereunder sometimes referred to as a second magnetic separator of the present invention) of the magnetic separator described in the aforesaid first magnetic separator of the present invention, the aforesaid fine-particle supply means comprises an umbrella-like baffle plate disposed in the aforesaid top end portion, wherein fine particles are ejected upwardly toward the aforesaid baffle plate from a lower portion thereof, and then the fine particles having collided with the aforesaid baffle plate are caused to drop toward the aforesaid inner duct. PA1 (3) Further, in the case of an embodiment (hereunder sometimes referred to as a third magnetic separator of the present invention) of the magnetic separator described in the aforesaid first or second magnetic separator of the present invention), the aforesaid quadrupole magnets comprise normal conducting coils and are cooled with liquid helium. PA1 (4) Further, in the case of an embodiment (hereunder sometimes referred to as a fourth magnetic separator of the present invention) of the magnetic separator described in the aforesaid first or third magnetic separator of the present invention), a persistent current circuit switch is connected in parallel with the aforesaid quadrupole magnets. PA1 (5) Further, in the case of an embodiment (hereunder sometimes referred to as a fifth magnetic separator of the present invention) of the magnetic separator described in the aforesaid first or second magnetic separator of the present invention), an intermediate-material collection tube, which is operative to collect intermediate materials, and a bypass collection tube, which is operative to supply the material collected by the aforesaid intermediate- material collection tube, are provided between the aforesaid first and second collection tubes. PA1 (6) Furthermore, there is provided a pulverized coal combustion apparatus (hereunder sometimes referred to as a sixth apparatus of the present invention) that comprises:

Magnetic separator and pulverized coal combustion apparatus using the same


An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.

Semiconductor devices are widely used throughout the electronics industry. One factor driving their use is the ability to put more and more circuits on a silicon chip. For example, semiconductor memory manufacturers have steadily progressed from memories of the 16K type as shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, to memories of the 1M type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. Memories of the 4M type are now being produced, production plans for high density 16M memories having submicron technology now exist, and experimentation of 64M memories has begun. Other VLSI devices such as microprocessors are now produced that have more than one million transistors on chip.
In order to put more and more circuits on a silicon chip, without unduly increasing the size of the semiconductor chip, it is necessary to reduce the size of the individual semiconductor devices formed on the semiconductor chip. U.S. Pat. No. 4,240,092 to Kuo and U.S. Pat. No. 4,721,987 to Baglee et al, discuss scaling down the size of memory devices. U.S. Pat. No. 4,356,623 to Hunter, incorporated herein by reference, discusses scaling down the size of semiconductor transistors. Some encountered problems include parasitic capacitances, resistances, and punchthrough currents. Hunter's solution provides a Metal-Oxide-Semiconductor, MOS, transistor with a gate conductor within the range of about 0.1 microns to about 1 micron. A gate insulator is formed on top of a substrate and a gate conductor is formed on top of the gate insulator. The gate conductor has sidewall insulators. Ion implantation and subsequent drive-in anneal form the source/drain regions of the transistor. The source/drain regions extend underneath the sidewall insulators and underneath gate of the transistor.
Additional scaling of semiconductor devices is needed. By forming larger numbers of semiconductor devices in a semiconductor chip, the cost per device is greatly reduced. By increasing the density of semiconductor elements on a chip, the manufacturing costs can be decreased. This will allow further use and application of semiconductor devices throughout the electronics industry and benefit consumers.
The channel length scaling in MOS transistors is limited by the punchthrough voltage, i.e., the source to drain bias that produces current between the source and drain when the gate to source bias is at the "off" condition. The implanted source/drain regions to the typical planar self-aligned MOS transistor cannot be guaranteed to have a vertical doping profile before diffusion such that the highest doping concentration is at the silicon surface. Thus later diffusion, proportional to the concentration gradients, may be greater at some depth below the surface that is not adequately controlled by the gate. Very shallow voltage threshold, Vt, implants which counterdope the surface can contribute to this effect which results in sub-surface conduction at a source to drain voltage lower than that needed to produce current in the gate controlled surface channel at "off" bias.
It is an object of this invention to provide a method of manufacturing such small semiconductor device.
It is an additional object of this invention to arrange the surface channel and the source/drain diffusions such as to prevent the possibility of higher dopant concentrations in the substrate below the plane of the gate controlled channel, thereby preventing the sub-surface punchthrough and resulting lowering of the device punchthrough voltage.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.

Method of manufacturing a minimum scaled transistor


Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

1. Field of the Invention
The present invention is directed to technology for reading memory devices.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistors is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
Many EEPROMs and flash memories have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states. Such memory cells store one bit of data. Other EEPROMs and flash memory cells store multiple ranges of charge and, therefore, such memory cells can be programmed to multiple states. Such memory cells store multiple bits of data. The size and parameters of the threshold voltage window depends on the device characteristics, operating conditions and history.
Conventional EEPROMs and flash memories can experience endurance related stress each time the device goes through an erase and program cycle. The endurance of a flash memory is its ability to withstand a given number of program and erase cycles. With use, defects tend to build up in the memory device and may eventually render the device unreliable. One physical phenomenon limiting the endurance of prior flash memory devices is the trapping of electrons in the active dielectric between the floating gate and the substrate. During programming, electrons are injected from the substrate to the floating gate through the dielectric. Similarly, during erasing, electrons are extracted from the floating gate through the dielectric. In both cases, electrons can be trapped by the dielectric. The trapped electrons oppose the applied electric field and subsequent program/erase cycles, thereby causing the programmed threshold voltage to shift to a lower value and the erased threshold voltage to shift to a higher value. This can be seen in a gradual closure of the voltage window between the programmed and erased states. If program/erase cycling is continued, the device may eventually experience catastrophic failure. This problem is even more critical if multi-state memory is implemented, since more accurate placement of the threshold voltage is demanded.
A second problem pertains to charge retention on the floating gate. For example, negative charge on the floating gate tends to diminish somewhat through leakage over a period of time. This causes the threshold voltage to shift to a lower value over time. Over the lifetime of the device, the threshold voltage may shift as much as one volt or more. In a multi-state device, this could shift the memory cell by one or two states.
A third problem is that the program/erase cycles may not be performed evenly for the cells in the memory device. For example, it is not uncommon that a repetitive pattern may be programmed continuously into a set of memory cells. Therefore, some cells will constantly be programmed and erased while other cells will never or rarely be programmed. Such uneven programming and erasing causes non-uniform stress conditions for the cells in a particular sector. Non-uniformity of the program/erase cycling histories can result in a wider distribution of threshold voltages for any particular given state. In addition to widening the threshold distributions, certain cells may reach closure of the voltage window, device failure or charge retention issues earlier than others.


Disclosed is the structure of a persistent current switch and a control method for the same. In the switch structure, a portion of a superconducting wire to be used as a switch is formed with slits such that the flow of current is controlled by the switch, to facilitate a transition between the superconducting state and the normal state of the superconducting wire. The structure of the persistent current switch includes a first slit longitudinally extending from a first point on one end of a superconducting wire to a second point and from a third point to a fourth point, the second, third, and fourth points being arranged sequentially in a longitudinal line, and second and third slits provided at opposite sides of a region between the second point and the third point where no first slit exists.

Superconductivity is the phenomenon that the electric resistance of materials disappears when temperature of the substance is decreased lower than its critical transition temperature. Using superconductive materials can cause the flow of electric current without the generation of heat, and prevent the loss of electrical energy. The superconductive materials are called "superconductors". The superconductors can cause the flow of electric current without a resistance only below a superconducting transition temperature Tc and a critical magnetic field Hc. In this case, there exists a critical current density Jc as the maximum conducting current density for allowing the flow of electric current without a resistance.
As application examples of the superconductors, superconducting electromagnets have been widely used. The superconducting electromagnets are processed to have a wire or tape shape and serve to produce a high magnetic field. The electromagnets are fabricated by winding wires to form several geometrical shapes of coils. The coils produce a magnetic field when electric current flows through the wires. If the wires are superconductors, there is no loss of electric power due to a resistance.
The superconducting electromagnet is used for Magnetic Resonance Imaging (MRI) and Nuclear Magnetic Resonance (NMR) equipments, etc. These equipments require a uniform and stable magnetic field in order to exhibit desired characteristics thereof. To produce the uniform and stable magnetic field, it is necessary to achieve a superconductive bonding between ends of the superconducting coil, so as to form a closed-loop superconducting electromagnet having a persistent current operation mode. Under the assumption of an ideal superconductive bonding, conducting current can flow through the electromagnet or bonding points without the loss of energy due to an electrical resistance. Further, a uniform magnetic field can be produced from the electromagnet, and the superconducting magnet can operate in the persistent current mode to maintain a desired magnetic field in a uniform and stable state.
FIG. 1 illustrates a conventional superconducting magnet for the persistent current mode. More specifically, FIG. 1A illustrates a superconducting wire 10, which has a slit S to divide the superconducting wire 10 into a first wire 10a and a second wire 10b. Referring to FIG. 1B, the first wire 10a and the second wire 10b of the superconducting wire 10 are wound on bobbins 25, respectively, and one end of each wire 10a or 10b is connected to a power supply 40 by means of a current-inlet line 41 to receive current (i) supplied from the power supply 40. If the overall superconductive magnet is cooled, the superconducting wire 10 becomes a superconducting state. Then, as a portion of the superconducting wire 10, which is designated by reference numeral 60 in FIG. 1B, is heated by a heater 50, the portion 60 of the superconducting wire 10 is changed from the superconducting state to a normal conducting state. In this state, the current (i) being supplied from the power supply 40 flows through the first wire 10a and the second wire 10b, and magnetic field are produced around the bobbins 25. The portion 60 of the superconducting wire 10 is again changed from the normal conducting state to the superconducting state if the heater 50 is switched off, and the superconducting wire 10 constituting the two coils forms a closed loop. Since the superconducting wire 10, consisting of the two wires 10a and 10b, has no resistance, the superconducting wire 10 can be operated in the persistent current mode In the persistent current mode, the current (i) continuously flows even if no further current (i) is supplied from the external source, and the magnetic fields can be kept continuously.
FIG. 1C is a view illustrating the flow of current (i). If a portion of a superconducting wire, which is designated by symbol {circle around (g)} in FIG. 1C, is heated by a heater, the portion {circle around (g)} becomes the normal conducting state, but other portions {circle around (b)}, {circle around (c)}, {circle around (d)}, {circle around (e)} and {circle around (f)} of the superconducting wire remain in superconducting state. In this case, the current (i) flows in the course of {circle around (a)}→{circle around (b)}→{circle around (c)}→{circle around (d)}→{circle around (e)}→{circle around (f)}→{circle around (h)}. Then, the heating of the portion {circle around (g)} is stopped, the portion {circle around (g)} is changed to the superconducting state, to form a superconductive closed loop. In this state, the current (i) continuously flows in the course of {circle around (b)}→{circle around (c)}→{circle around (d)}→{circle around (e)}→{circle around (f)}→{circle around (g)}. When the overall superconducting wire being changed to the superconducting state, there is no resistance. Therefore, the current can flow continuously through the superconducting wire, even if the supply of current (i) is stopped and thereby maintaining a magnetic field in a stable state.
However, in the above described conventional art, one end of the superconducting wire 10 is wholly heated by the heater 50, and thus results in the loss of a refrigerant. Further, since the end of the superconducting wire 10 has no slit, the superconducting wire 10 has a difficulty in the connection of the power supply 40.
In the following description, the same reference numbers will be used to refer to the same parts as the conventional art.

Structure of persistent current switch and that of control method

Korea Polytechnic University Industry Academic Cooperation Foundation


A resilient metal contact brush for use in controlling an electric motor, comprises a strip-like metal member having at one end thereof a contact head protruding at an angle to the plane of the strip-like member and at the other end thereof a fixing means. The contact head is an integral portion of the strip-like member and is formed by the juxtaposition of two flat ear-like protrusions formed on the strip-like member adjacent the one end thereof. Each ear-like protrusion is initially located at a respective edge of, and in the plane of, the strip-like member adjacent the one end thereof. The contact head is formed by first bending each ear-like protrusion through an angle of 180.degree. to place it in close contact with a central portion of the strip-like member adjacent the one end, to produce a head portion having at least double the thickness of the strip-like member and then bending the head portion thus formed at an angle to the plane of the strip-like member along a line adjacent the head portion which extends at right angles to a longitudinal axis of the strip-like member. The contact head of the contact brush presents a narrow rectangular contact area for making contact with a contact strip of a control system for a windscreen wiper electric motor.

Windscreen wiper motors for motor vehicles are customarily provided with a control system built into a gear box portion of the windscreen wiper motor, the control system comprising a series of resilient metal contact brushes which engage a rotary contact member on one of the gears of the motor. These resilient contact brushes form part of the speed control system for the windscreen wiper motor as well as a parking brake system which becomes operable when the windscreen wiper motor is switched off to ensure that the windscreen wiper blades connected to the motor park in the correct position on the windscreen of a motor vehicle to which the windscreen wiper motor is attached. A resilient metal contact brush suitable for use in such a control system is disclosed and claimed in U.S. Pat. No. 4,445,746, issued May 1, 1984, and assigned to the assignee of the present invention. The present invention is an improvement to the resilient metal contact brush disclosed in such patent.


A method for improving the adsorption properties of a hydrocarbon adsorber involves contacting a molecular sieve hydrocarbon adsorber at ambient temperature with an agent for modifying the acid sites of the molecular sieve to impregnate the molecular sieve with the agent. The average pore diameter of the intracrystalline porosity of the molecular sieve is about 3 to 20 angstroms. The agent has an anionic portion which is retained within the structure of the molecular sieve. The modified molecular sieve has the ability to retain adsorbed hydrocarbons at higher temperatures than the unmodified molecular sieve. The acid-modified molecular sieve can be used to remove hydrocarbons from a hydrocarbon-containing stream. The hydrocarbon-containing stream is passed through the modified adsorber at atmospheric pressure at a temperature ranging from room temperature to about 150.degree. C. to cause adsorption and retention of the hydrocarbons. The adsorbed hydrocarbons can then be desorbed at a higher temperature than would otherwise occur with an unmodified adsorber.

Internal combustion engines emit a large amount of unburned hydrocarbons during cold engine start-up. In fact, a substantial fraction of the emitted hydrocarbons have been found to occur during the first ten seconds due to the rich fuel mixture.
Release of hydrocarbons immediately after starting an engine poses a special problem because at this point the temperature of the conventional catalytic reactor is not high enough for conversion to innocuous products. The catalysts utilized in catalytic converter systems are generally ineffective at ambient temperature and must reach high temperatures, often several hundred degrees e.g., 300-400.degree. C. before they are activated.
One method of reducing cold start emissions is to temporarily adsorb hydrocarbons on zeolites which desorb at engine operating temperature and are converted by the main body catalyst.
One disadvantage of this method is that specific zeolites do not adsorb with equal efficiency at the full temperature range of the exhaust gas at start-up, that is, from room temperature to about 300.degree. C. Additionally, the adsorbed hydrocarbons can prematurely desorb before the main conversion catalyst is up to operating temperature, thus emitting hydrocarbons to the atmosphere.
It would be desirable to have a way to efficiently adsorb hydrocarbons without premature desorption at engine start-up. It would also be desirable to maintain the adsorption activity over the age of the adsorber.
The present invention fills these needs.

Hydrocarbon adsorbers, method of making and use therefor


A negative photoresist composition is used for the formation of thick films and includes (A) a novolak resin, (B) a plasticizer, (C) a crosslinking agent and (D) an acid generator. The composition is applied onto a substrate and thereby yields a photoresist film 5 to 100 μm thick. Likewise, the composition is applied onto a substrate of an electronic part, is patterned, is plated and thereby yields a bump.

1. Field of the Invention
The present invention relates to a negative photoresist composition for use in the formation of thick films, as well as to a photoresist film and a method of forming bumps using the photoresist film. Specifically, the invention relates to an alkali-developable negative photoresist composition for the formation of thick films which is suitable for photofabrication such as bump formation, wiring, interlayer insulating film formation, circuit protective film formation and processing and manufacture of precision parts, carried out when circuit substrates are manufactured and semiconductors and electronic parts are packaged on the circuit substrates.
2. Description of the Related Art
The photofabrication is a generic term for techniques in which a photosensitive resin composition is coated on the surfaces of process articles and the coating films formed are patterned by photolithography, followed by chemical etching or electrolytic etching using the patterns as masks, or electroforming chiefly using electroplating, any of which are applied alone or in combination, to fabricate various precision parts. This is prevalent in the current high-precision microfabrication techniques.
With the downsizing of electronic equipment, there are a rapid progress toward higher integration of LSIs and toward ASICs (application specific integrated circuits), and a demand for multipin thin-film packaging for mounting LSIs on electronic equipment, where the bare chip packaging carried out by the TAB system or flip-chip system, has attracted notice. In such multipin packaging, protruded electrodes of 20 μm or more in height, called bumps serving as connecting terminals, must be highly precisely arranged on the substrate, and it has become more required to make the bumps higher in precision so as to be adaptable to any further miniaturization of LSIs in future. In addition to the formation of the connecting terminals, a rewiring process is performed to form wiring between the chip and the connecting terminals in many cases. In this procedure, the wiring is patterned with the use of a thick resist film about 5 to about 20 μm in thickness.
Photoresists for the formation of thick films are used as materials for the formation of such bumps or for rewiring. The term "photoresist for the formation of thick films" (hereinafter referred to as "thick-film photoresist") used herein means and includes resists that can form films having a thickness of at least about 5 μm on substrates. Using such a patterned thick film as a mask, bumps are formed by plating process.
For example, Japanese Patent Laid-Open Nos. 10-207057, 2000-39709 and 2000-66386 disclose thick-film photosensitive resin compositions which are used for the formation of bumps or for wiring. These conventional thick-film photosensitive resin compositions require large amounts of reaction initiators in order to sufficiently react overall of the resulting resist films each having a large thickness. However, large amounts of reaction initiators may deteriorate compatibility or stability in preservation. Demands have therefore been made on reaction initiators having higher sensitivity.
Chemically amplified resists containing acid generators have been used as photosensitive resist compositions having high sensitivity. In these chemically amplified resists, a protonic acid is generated from the constitutive acid generator upon irradiation of active light or radiant ray and then induces an acid catalytic reaction with a base resin in the resin composition due to heat treatment after exposure. Thus, the chemically amplified resists have significantly higher sensitivity than conventional resists each having a photoreaction efficiency (a reaction per photon) of less than 1. As an example of chemically amplified negative resists, L. E. Bogan et al. disclose a resist using polyvinylphenol and a melamine derivative in combination in Proceeding of SPIE, 1086, 34-47 (1989). However, when thick films are formed using these chemically amplified resists, the resulting thick films invite cracking and do not exhibit required plating resistance.

Negative photoresist compositions for the formation of thick films, photoresist films and methods of forming bumps using the same


A method for manufacturing a semiconductor device is provided. The method includes successively forming a first silicon film and a mask film above a semiconductor substrate through a gate insulating film, forming a plurality of trenches in the first silicon film and in the mask film to a depth to reach the semiconductor substrate, filling the plurality of trenches with the silicon oxide film, removing the mask film to expose the first silicon film existing between the silicon oxide films, selectively growing a second silicon film on the first silicon film, planarizing the second silicon film using an alkaline slurry exhibiting a pH of 13 or less and containing abrasive grains and a cationic surfactant, thereby obtaining a floating gate electrode film comprising the first and second silicon films, forming an interelectrode insulating film on the entire surface, and forming a control gate electrode film on the interelectrode insulating film.

1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device and, in particular, to a method for manufacturing a flash memory cell using a damascene working process.
2. Description of the Related Art
Because of the advantage of flash memory that it can retain data without necessitating the supply of power, the flash memory is widely employed as a storage element for multimedia cards. In recent years, there have been persistent demands for a flash memory having an increased capacity and hence it is now required to further enhance the integration degree of such a memory.
As one of the method for enhancing the integration degree of flash memory, there has been proposed a method of dividing the silicon layer of floating gate into two layers in fabricating a stacked gate structure. In this method, element isolation is performed after the formation of the first silicon layer, thereby enabling the second silicon layer to be deposited selectively and in a self-aligned manner only on the first silicon layer. According to this method, it is possible to make the floating gate larger than the width of tunnel insulating film and also to make the distance between neighboring floating gates smaller than the minimum line width.
It is however difficult to make uniform the surface area of the selectively grown silicon layer for every cells. As a result, the memories obtained tend to become non-uniform in characteristics due to the coupling ratio. Meanwhile, there has been proposed a damascene working process wherein the second silicon layer is non-selectively formed all over the surface of the first silicon layer and the surface of insulating layer for element isolation at first and then the second silicon layer is subjected to back etching or polishing so as to leave the second silicon layer only on the first silicon layer. Further, there has been proposed a slurry for polishing a polysilicon film that has been non-selectively grown by the ordinary LPCVD method. When a polysilicon film is mainly polished at a high polishing rate by this slurry, it is possible to inhibit the phenomena such as dishing and erosion that may be generated inside the pattern.
However, as the fineness of memory cells is further enhanced in future, it is feared that due to the existence of step portion between the first silicon layer and the insulating film for element isolation, a defective formation of the second silicon film may be generated to degrade the characteristics of the obtained device.

Method for manufacturing semiconductor device