Methods and articles are provided for frangible slugs. A method of manufacturing a frangible slug includes heating substantially spherical metallic powdered particles, where substantially all of the powdered particles have diameters larger than 125 microns and smaller than 250 microns, to form heated powdered particles. The method includes heating a microcrystalline wax to form a melted wax. The method also includes combining the heated powdered particles with the melted wax to form a liquid mixture. The method further includes filling a payload cavity of a slug container with the liquid mixture to form a liquid mixture payload, where the slug container is configured to retain a solidified frangible payload as the frangible slug until impact with a solid object.

In the field of ordnance, various types of cartridges are available for firearms. A cartridge is a piece of ammunition that contains primer, propellant, and a ballistic projectile, packaged together in a case. Cartridges are sometimes referred to as rounds or shells, with cartridges for shotguns referred to as shotgun shells.
Cartridges are available with several types of ballistic projectiles. One well-known type of ballistic projectile is a bullet, which is a solid projectile mounted in or on the front end of a cartridge. A bullet is sometimes referred to as a slug, as described below.
Shotgun shells are typically available with shot or slugs as ballistic projectiles. Shot are small solid round projectiles, which are packed into the front end of a shotgun shell. Shot are available in various sizes, from small birdshot (size 9 birdshot is 0.080″ in diameter) to large buckshot (size 000 buckshot is 0.36″ in diameter). A shotgun shell with shot typically includes a number of shot, with the number depending on the size of the shot and the size of the shotgun shell.
A slug is a projectile package mounted in or on the front end of a cartridge, such as a shotgun shell. A slug can be a solid projectile package, such as a bullet. Alternatively, a slug can be a composite projectile package formed from one or more component parts and/or materials, such as a container and a payload.
Various types of slugs are available for firearm applications. One firearm application is the disabling of door hardware. Sometimes, military and/or law enforcement personnel may use firearms to disable the hardware of a door in order to gain entrance into a building. In this application, a firearm can be used to fire a door slug at door hardware, such as a handle, lock, or hinge, to disable the door hardware. Throughout this document, a slug intended to disable door hardware is referred to as a door slug.
A door slug can effectively disable door hardware in several ways. One way in which a door slug can disable door hardware is by removing a portion of a door and/or door frame, to which the door hardware is connected. Another way in which a door slug can disable door hardware is by removing a portion or all of the door hardware from a door and/or door frame to which the door hardware is connected. Still another way in which a door slug can disable door hardware is by damaging it so that it no longer performs its intended function. Alternatively, a door slug can effectively disable door hardware by using a combination of these ways.
Some door slugs, when fired at door hardware, may fail to effectively disable the door hardware. A door slug may impact the door hardware but fail to effectively disable it. Alternatively, a door slug may pass through a portion of the door hardware but still fail to effectively disable it.
Some door slugs, when fired at door hardware, may perform poorly upon impact with door hardware, A portion or all of a door slug may pass through the door hardware, possibly harming a person behind the door. A portion or all of the door slug may ricochet off the door hardware, possibly harming a person who fired the door slug. The impact of the door slug may cause pieces of the door hardware to fragment and fly off at high speeds, possibly harming a person in the vicinity of the impact.

Method of manufacturing a frangible slug


A device for controlling a display screen has an actuating element which can be rotated about a longitudinal axis and moved in the direction of the longitudinal axis, enabling a point of a menu structure consisting of menu, partial menus, functions and/or function values to be selected, and which can be represented as an optically highlighted field in the display screen. The actuating element has an initial position and can describe with relation thereto an additional movement with two additional degrees of freedom. The additional movement of the actuating element enables a field arranged in a marginal region (2) of the display screen and Audio associated with a point of the menu structure to be selected. The rotary/longitudinal movement of the actuating element enables a subordinate field of the menu structure associated with the field arranged in the marginal region of the display screen to be selected in the central region (3) of the display screen enclosed by the marginal region.

This application is a National Stage of PCT/EP9/07571 filed Nov. 24, 1998 claims the priority of 19752056.1 and 19843421.9, filed Nov. 25, 1997 and Sep. 22, 1998, the disclosures of which are expressly incorporated by reference herein.
The invention relates to a device for controlling a display screen having a rotatable actuating element and moved to enable pointing to a menu structure.
A device of this type is known from European Patent Document EP 0 796 766 A2. In this case, the actuating element is used for increasing the number of planes within the menu structure. It is indicated for this purpose that the planes are to be arranged to be distributed along the circumference of the display screen. This type of a device represents an additional difficulty for the user because there is no clear assignment between the additional movement and the axial or rotational movement of the actuating element. The transition between the planes and within the menu structure also does not develop in a manner that is unclear and finally draws the user's attention away from the traffic situation.
It is an object of the invention to provide a device of the initially mentioned type in the case of which there is a clear assignment between the display screen and the various moving possibilities of the actuating element.
By means of the additional movement of the actuating element, an overriding point of the menu structure is now selected; by means of the rotary/longitudinal movement of the actuating element, a point of the menu structure is selected which is subordinate thereto. In concrete terms, this means, for example, that the possible menus are arranged in the marginal region, while the pertaining submenus or function or function values are situated in the central region. In this case, only the partial menus, the function and function values are arranged in the central region which are part of the one menu preferably selected by a preceding additional movement of the actuating element. Thus, the points which within the menu structure are disposed on the same step are situated in the marginal region, while the hierarchically lower points are located in the central region.
As known from European Patent Document EP 0 796 766 A, the actuating element can carry out a wobbling as well as a parallel displacement as the additional movement and can also be forcibly guided during this movement. The moving possibilities and limitations improve the handling of and the movement within the menu structure. Starting from the central position as the initial position of the actuating element, the additional movement is synonymous with a leaving of the plane of the menu structure indicated in the central region and the selecting of the next-higher plane. The return movement into the starting position, in turn, indicates the transition from the just found higher plane into the next plane situated underneath. As a result, the user is provided with a tactile sense as to how he is moving within the menu structure.
An improvement of the invention relates to the problem of an operating error which may occur in the case of a device of this type. Particularly if a plurality of points are arranged within the frame region of the display screen, the risk of accidentally not "hitting" the desired point is particularly high. Another factor is the special situation in which the selection of these points takes place. The turning to the display screen frequently competes with the traffic situation. The time available for this purpose, as a rule, is very brief.
If the points arranged in the frame area are optically highlighted during and/or after the additional movement and are selected only when the actuating element is at least approximately back in the starting position, the danger of a faulty selection is largely avoided.
Although, by means of the additional movement, it is possible to optically select the point of the menu structure arranged in the frame area, the selection will functionally only take place when the actuating element is back in the starting position. When the device is used in a vehicle for controlling different menus, such as the navigation system, the vehicle computer, the air conditioner, etc. and the assignment of the points arranged in the frame area to the individual menus, the term "functional selection" means the following:
As a result of the additional movement of the actuating element, the section of the marginal region assigned to the respective menu is optically stressed, for example, highlighted. The selection and therefore the controlling of the respective menu, for example, of the navigation, will, however, take place only when, after the optical highlighting of the corresponding marginal region section, the actuating element is returned back into the starting position. Only then will the navigation system be selected, for example, for the vehicle computer, instead of the menu previously shown on the display screen. If, in this case, the partial menus and/or functions and/or function values are displayed as points (for example, in the form of rectangular fields) within the interior surface of the display screen surrounded by the frame region, these points can now be activated preferably by means of the actuating element.
The transition to another menu again requires the preparatory selection of the respective marginal region section by means of the actuating element, in conjunction with the optical highlighting of this section and the subsequent functional selection by returning the actuating element into the starting position.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

Bayerische Motoren Werke Aktiengesellschaft


An output buffer circuit includes a first output buffer having a high output resistance determined by DC specifications, a second output buffer having an output resistance satisfying AC specifications when simultaneously driven with the first output buffer, and a control circuit for controlling an operation of the second output buffer. An input signal is supplied to the input node of the first output buffer, and the output node of the first output buffer is connected to an output terminal. The output node of the second output buffer is connected to the output terminal. The control circuit is responsive to the potential of the input signal or of the output terminal to control the operation of the second output buffer. The control circuit drives the second output buffer when the output from the first output buffer is changed, and sets the output from the second output buffer in the high impedance state when the output from the first output buffer is stationary.

1. Field of the Invention
The present invention relates to an output buffer circuit formed in a semiconductor integrated circuit device and, more particularly, to an output buffer circuit capable of suppressing power supply noise generated when an output is changed and suppressing leakage of the power supply noise to an output node.
2. Description of the Related Art
In a semiconductor integrated circuit device, when an output from an output buffer circuit is to be changed, an increase or decrease in power supply potential or ground potential is caused by an induced electromotive voltage determined by a product "L.times.di/dt" where L is an inductance of a power supply line or a ground line and di/dt is a rate of change in output current. These potential variations (power supply noise) are transmitted to an output node through a transistor constituting part of the output buffer circuit to cause output noise. Especially, when a plurality of output buffer circuits perform switching operations simultaneously, the output noise is increased to cause erroneous operations of other circuits in the semiconductor integrated circuit device or erroneous operations of input circuits of other semiconductor integrated circuits connected to the output node. Such noise is called simultaneous switching noise (SSN). The SSN tends to be increased as the micropatterning size of a semiconductor element is decreased and the operation speed is increased recently.
Conventionally, in order to minimize the potential variation in the power supply or the output as described above, efforts have been made to decrease the inductance L of the power supply line or the ground line or to decrease the rate of change di/dt in output current. The inductance L, however, is mainly determined by the length of the lead frame or the bonding wire, and it is not easy to shorten the lead frame or the bonding wire. Also, the speed of an output signal (a rise time tr or a fall time tf) and a propagation delay time tpd of a signal propagation line are normally defined as the design specifications. When di/dt is decreased, tr and tf, and thus tpd are increased, and the specified values cannot be satisfied. In other words, in order to increase the rate of change in output signal, the output current of the output buffer circuit must be increased. When the speed of the output signal is determined, the lower limit of the di/dt is determined. Hence, the di/dt cannot be simply decreased, and it is difficult to minimize the potential variation.
Generally, the specifications of the output current of an output buffer circuit include AC specifications (determined in accordance with the rate of change in output signal) and DC specifications (a source current I.sub.OH and a sink current I.sub.OL when the output is stationary). In an integrated circuit having high-speed specifications, when the output current is determined in accordance with the AC specifications, the DC specifications are often automatically satisfied. Since the out-put currents (I.sub.OH, I.sub.OL) of the DC specifications of the output buffer circuit are automatically determined from the AC specifications, the output resistance (an ON resistance R.sub.ON) when the output is stationary is also automatically determined.
Assume that the output buffer circuit is a CMOS inverter comprising a p-channel MOS transistor and an n-channel MOS transistor. When the input signal is at Vcc level (potential of the high potential-side power supply), the p-channel MOS transistor is turned off, and the n-channel MOS transistor is turned on. The 0N resistance R.sub.ON (=V.sub.OL /I.sub.OL) of the n-channel MOS transistor is determined by an output potential V.sub.OL at "L" level and the sink current I.sub.OL at this time. When the input signal is at Vss level (potential of the low potential-side power supply; ground potential), the n-channel MOS transistor is turned off, and the p-channel MOS transistor is turned on. The ON resistance R.sub.ON (={Vcc-V.sub.OH }/I.sub.OH) of the p-channel MOS transistor is determined by an output potential V.sub.OH at "H" level and the source current I.sub.OH at this time.
When an output from the output buffer circuit is changed, the level of the output noise appears as a bounce quantity .DELTA.E.sub.B of the power supply potential or the ground potential divided by a rate of the ON resistance R.sub.ON of the output buffer circuit to a load impedance Z of the output node. When the load impedance Z is a capacitive load (i.e., a capacitance C.sub.L), output noise V.sub.OLP when the output is at "L" level becomes substantially .DELTA.E.sub.B /(1+S.C.sub.L.R.sub.ON), and the higher R.sub.ON, the lower V.sub.OLP. The fact that the ON resistance R.sub.ON is automatically determined by the AC specifications of the output buffer circuit means that when the speed of the output signal is determined, the lower limit of the output noise V.sub.OLP is determined. This applies to output noise V.sub.OHV when the output is at "H" level.
As described above, in the conventional output buffer circuit, since the ON resistance R.sub.ON which is automatically determined by the AC specifications of the output buffer circuit, is low when compared to that determined only from the DC specifications, a variation in the power supply potential or the ground potential when the output is changed can easily adversely affect the output node, and the output noise V.sub.OLP or V.sub.OHV tends to be unpreferably increased.


Provided are an apparatus for filtering a fluid, the apparatus including a first flow channel and a second flow channel which are connected to each other in a fluid communicable manner via a filtration medium, and a method of isolating particles using the apparatus.

1. Field
The present disclosure relates to apparatus for filtering a fluid and methods of isolating a particle by using the same.
2. Description of the Related Art
Fluid isolation methods by filtering a fluid including particles using a filtration medium having a plurality of apertures have been well known in the art. In some cases, however, a layer is formed over time on a surface of a filtration medium by materials accumulated thereon, and thus, the flow of the materials through the apertures may become obstructed. Furthermore, air bubbles may be formed in the apertures, thereby further negatively affecting the flow of materials through the apertures.
Thus, there is a need to develop a method of preventing or removing clogging caused by air bubbles or other materials formed in the apertures of a filtration medium during isolation thereof.

Apparatus for filtering fluid and methods of isolating particle using the same


A computing device may receive multiple recordings or transmissions from one or more source devices. The recordings may include geo-tag information to relate the recordings to a specific event. The computing device may receive from a client device a request for the recordings. Responsive to the received request, the computing device may transmit the recordings to the client device. The computing device may receive from the client device an identification of which recording(s) are preferred over the course of the event, and may compile statistics related to the preferred selections over the course of the event as received from a plurality of client devices. The computing device may generate a “best-cut” recording or summary version of the event based on the most preferred recording at various points in time during the event, based on the compiled statistics.

Improvements in computing technologies have changed the way people accomplish various tasks. For example, some estimates indicate that between the years 1996 and 2007, the fraction of the world's population that uses the Internet grew from approximately 1% to approximately 22%. Irrespective of the actual percentages, trends suggest that the Internet will continue to grow.
Along with the growth of the Internet, users and service providers have developed numerous applications and corresponding interfaces to facilitate the exchange of information. For example, a politician may give a "victory speech" after he has been announced as the winner of an election, and just as he is getting ready to deliver the speech, those in the audience, which may include the media/press and supporters of his campaign, may each use a digital video camera to shoot footage of the speech as it unfolds. The audience members that shot the video footage may each upload the video footage to a respective user account or the like associated with a commercial server thereafter for purposes of saving the video footage, freeing up memory on the digital video camera for future use, and allowing friends, family, or more generally, other computing users to view the video.
More generally, recent success of media sharing services has increased the amount of media content available on the Internet, yet the media content remains largely disorganized and characterized by low/poor quality. Users often waste time and become frustrated when they are forced to consume low quality media content and when they must review multiple versions of the same event to determine which recording is the best.


The invention is intended to provide a downhill speed control system which employs a method of setting a target vehicle speed in advance, thereby improving controllability when a vehicle runs down a slope, and giving an operator improved operability in setting of the target vehicle speed. Brakes are controlled so that, when the vehicle runs down the slope, an actual vehicle speed is matched with a target speed set by a switch which can set the target speed by selectively or continuously changing plural preset speeds. Also, control constants for PID control are modified depending on settings of a downslope gradient setting switch and a load setting switch. When an acceleration computed from the actual vehicle speed is larger than a target acceleration, the strength of applied brake is increased.

A method of adjusting the strength of applied brake with an operator operating a foot brake or a brake lever has hitherto been practiced for the purpose of keeping a vehicle speed at a control target value when a vehicle runs down a slope. In mines or the likes where a downward slope continues over a long distance, however, it is troublesome for the operator to operate the brake whenever an occasion requires. In a downhill speed control system for releasing the operator from the troublesome braking operation in such a case, as disclosed in, e.g., JP-A-6-135260, a target vehicle speed is set depending on a road surface gradient angle detected by a road surface gradient sensor, and a retarder brake is controlled so that a vehicle speed detected by a vehicle speed sensor is held at the target vehicle speed. Further, the disclosed control system includes a loaded weight sensor, and the strength of the applied brake is controlled depending on the amount of earth and sand loaded in a vessel.

Hitachi Construction Machinery Co., Ltd.


An intermediary device configured to insert at least one of user interest categories or a client device location in the header portion of a message received from a client device is described herein. The insertion enables a server receiving the message from the intermediary device to target content to the client device based on the at least one of the user interest categories or the client device location.

The increase in distribution of media over the Internet has led to the desire for advertisers and other content providers to develop new ways of reaching potential consumers. Previously, an advertiser knew a general location of a person receiving the advertisement. For example, an advertiser in a geographically-based television market knew that the person viewing its add was in that television market. On the Internet, however, advertisers typically do not know the location of the person receiving the advertisements. Advertisers are able to take advantage of user activities monitored by servers, such as a history of search queries tracked by a search engine. These user activities may be used to formulate interests of consumers that are then used in determining appropriate advertisements. User activities, however, often depend on a current user location and are irrelevant when a user is no longer at that location. For example, if a user is visiting a certain town and searches for restaurants in that town, that search activity will be irrelevant to the user upon his or her departure and would thus be a poor determiner of which advertisements are appropriate.
Many user devices, such as telecommunication devices, have mechanisms for determining their locations. For example, many of these devices are equipped with Global Positioning System (GPS) components that enable a telecommunication device to locate itself. This location information is sometimes provided to remote servers, such as third party application servers. The downside of these mechanisms, however, is the amount of power and processing they consume. Typically, user devices have limited battery power and processing means that must be conserved. Thus, use of these user device-based location mechanisms for providing servers with user locations is problematic.

Insertion of user information into headers to enable targeted responses


A first field oxidation is performed by masking an element-isolating region formation-expected region on a substrate by a first oxidation preventing film (silicon nitride film) having therein a first opening to thereby form a first field oxide film, which is then masked by a second oxidation preventing film (silicon nitride film) having a second opening with a smaller width dimension than the first opening in a second field oxidation to thereby locally form a second field oxide film at the middle of the first field oxide film.

1. Field of the Invention
The invention relates to a semiconductor device in which an element isolating region is formed using LOCOS (LOCal Oxidation of Silicon) and a method for manufacturing the same.
The present application claims priority of Japanese Patent Application No.2000-236213 filed on Aug. 3, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
An LSI (Large Scale Integration) known as a representative of semiconductor devices includes desired circuit devices formed in each of a plurality of element regions which is dielectrically isolated from each other by an element isolating region on a semiconductor substrate. This element isolating region has conventionally been formed using LOCOS.
FIGS. 5A to 5C are flow diagrams for schematically showing an element isolating region forming method utilizing a LOCOS method.
As shown in FIG. 5A, first a silicon oxide (SiO2) film 52 is formed as a pad insulating film by thermal oxidation and then a silicon nitride (SiN) film 53 is formed as an oxidation preventing film by CVD (Chemical Vapor Deposition) on a silicon substrate 51. In this configuration, oxidation preventing film, silicon oxide film 52, is used as a buffer film to prevent a crystal defect from occurring in a surface of the silicon substrate 51 if the silicon nitride film 53 is formed directly formed on the silicon substrate 51. Next, by photolithography, the silicon nitride film 53 is selectively etched away only in an element-isolating region formation-expected region 54 on the silicon substrate 51 to thereby expose the silicon oxide film 52.
Next, as shown in FIG. 5B, by performing thermal oxidation (field oxidation) on the silicon substrate 51 in an oxidizing atmosphere, a field silicon oxide film (field oxide film 55) is formed at such a position in the element-isolating region formation-expected region 54 that is not masked by the silicon nitride film 53. As a result, an element isolating region is formed which is made up of the field oxide film 55. Also, the field oxide film 55 has a so-called bird""s beak 55A formed at its sides. Next, as shown in FIG. 5C, by removing the silicon nitride film 53 and the silicon oxide film 52, the silicon substrate 51 has, formed thereon, a plurality of element regions 56 which is dielectrically isolated from each other by the element isolating region made up of the field oxide film 55.
Afterwards, thus obtained silicon substrate 51 undergoes repeatedly such required process steps as impurity introduction and etching, so that desired circuit elements are formed in the element regions 56, thus completing a semiconductor device.
As mentioned above, the field oxide film 55 formed by LOCOS has the bird""s beak 55A at its sides, which bird""s beak 55A bites into the element region 56. Since a depth by which the bird""s beak 55A bites into the element region 56 is roughly proportional to film thickness of the field oxide film 55, if the field oxide film 55 is formed thick to increase isolation dielectric strength of a circuit element formed in the element region 56, bite-in depth of the bird""s beak 55A is also increased. As a result, a lateral dimension L of the element region 56 is decreased and will be more and more restricted as the LSIs will be demanded to have an even higher integration density in the future, thus leading to a major problem.
If the field oxide film 55 is formed thin to decrease the bite depth of the bird""s beak 55A, on the other hand, the isolation dielectric strength is also decreased, thus finding difficulty in application to such a circuit element that requires a higher isolation dielectric strength. Thus, with the conventional element isolating region forming method using a LOCOS step only once, the bird""s beak 55A cannot avoid biting deeply into the element region 56 particularly, when the element isolating region is formed rather thick.
Also, as the bird""s beak 55A bites into the element region 56 deeper, it becomes more difficult to flatten the surface of the element region 56, so that when a MOS (Metal Oxide Semiconductor) transistor is formed as the circuit element in the element region 56, a channel region is not flattened in shape, thus resulting in fluctuations in effective lateral dimension L, hence in transistor characteristics.
It should be noted that such a semiconductor LSI device including a flash memory, for example, is widely used in information equipment or a like that includes a first type of circuit element that requires a higher isolation dielectric strength (supply voltage: 15-18V) like a memory transistor and a second type of circuit element that requires only a lower isolation dielectric strength (supply voltage: 2.5-3.3V) like a logic transistor in a peripheral circuit which are mixed on the same substrate. In such a configuration, the first type of circuit element requires a thicker element isolating region and the second type of circuit element, only a thinner one.
In manufacturing of such a semiconductor device, however, performing the LOCOS step only once is not sufficient to form an element isolating region that meets requirements of both types of circuit elements described above.
In view of the above, such a semiconductor device manufacturing method has conventionally been provided that forms an element isolating region by performing the LOCOS processing in two steps. The following will describe this semiconductor device manufacturing method along its steps with reference to FIGS. 6A to 6H. Description is made with reference to the above-mentioned example where the first type of circuit element requiring a thicker element isolating region and the second type of circuit element requiring only a thinner element isolating region are formed in a mixed manner on the same substrate.
First, as shown in FIG. 6A, on a silicon substrate 61 is formed by thermal oxidation, a silicon oxide film 62 as the pad insulating film with a film thickness of 18-22 nm, on which is then formed by CVD a silicon nitride film 63 as the oxidation preventing film with a film thickness of 130-170 nm. And, on the silicon substrate 61 are defined a first element-isolating region formation-expected region 64A for a first circuit element requiring a thicker element isolating region and a second element-isolating region formation-expected region 64B for a second circuit element requiring only a thinner element isolating region.
Next, as shown in FIG. 6B, a photo-resist is applied by photolithography everywhere on the silicon substrate 61, which is then exposed and developed to form a photo-resist (PR) film 66 having such a pattern that has an opening 66A therein with a width dimension of 700-750 nm only on the above-mentioned first element-isolating region formation-expected region 64A. Next, as shown in FIG. 6C, the silicon nitride film 63 and the silicon oxide film 62 which are exposed are sequentially and selectively dry-etched and patterned using the photo-resist film 66 as a mask to thereby form an opening 67 with roughly a same dimension as the opening 66A, thus exposing the silicon substrate 61. Subsequently, the silicon substrate 61 is selectively dry-etched on its surface to thereby form a recess 68 with roughly a same width dimension of 700-750 nm as the opening 67 and a depth of 70-80 nm. Next, the photo-resist film 66 is removed.
Next, as shown in FIG. 6D, the silicon substrate 61 is heat treated, as exposed in an oxidizing atmosphere, at 1000-1100xc2x0 C. for 20-30 minutes as first field oxidation (thermal oxidation). This permits the silicon nitride film 63 having the opening 67 therein to be used as a mask to thereby form a first field oxide film 69 having a film thickness of 270-350 nm and a width of 1.0-1.3 xcexcm constituting part of the first element isolating region on the surface of the silicon substrate 61 in which the recess 68 of the first element-isolating region formation-expected region 64A is formed. This first field oxide film 69 has a bird""s beak 69A formed at its sides. When this first field is being formed, the second element-isolating region formation-expected region 64B is covered with the silicon nitride film 63, so that no field oxide film is formed. Note here that the silicon oxide film 62 is integrated with the first field oxide film 69.
Next, as shown in FIG. 6E, a photo-resist is applied by photolithography everywhere on the silicon substrate 61, which is then exposed and developed to thereby form a photo-resist film 71 having such a pattern that has an opening 71A with a width dimension of 330-390 nm only on the above-mentioned second element-isolating region formation-expected region 64B. Next, as shown in FIG. 6F, the exposed silicon nitride film 63 and the silicon oxide film 62 are selectively dry-etched and patterned in this order using the photo-resist film 71 as a mask to thereby form an opening 72 with roughly a same dimension as the opening 71A, thus exposing the silicon substrate 61. Subsequently, the surface of the silicon substrate 61 is selectively dry-etched to form a recess 73 having roughly a same width dimension of 330-390 nm as the opening 72 and a depth of 70-80 nm. Next, the photo-resist film 71 is removed.
Next, as shown in FIG. 6G, the silicon substrate 61 is heat treated, as exposed in an oxidizing atmosphere, at 1000-1100xc2x0 C. for 30-40 minutes as second field oxidation (thermal oxidation). This permits the silicon nitride film 63 having the opening 67 therein to be used as a mask to thereby form a second field oxide film 74 with a film thickness of 450-500 nm so as to overlap with the first field oxide film 69 in the first element-isolating region formation-expected region 64A. As a result, in the first element-isolating region formation-expected region 64A is formed a first element isolating region 76 comprised of the first field oxide film 69 and the second field oxide film 74. At the same time, using as a mask the silicon nitride film 63 having the opening 72 therein, a third field oxide film 75 having a film thickness of 330-380 nm and a width of 0.6-0.8 xcexcm is formed on the surface of the silicon substrate 61 in the recess 73 of the second element-isolating region formation-expected region 64B. This third field oxide film 75 provides a second element isolating region 78 and also has a bird""s beak 75A at its sides.
Next, as shown in FIG. 6H, the silicon oxide film 62 and the silicon nitride film 63 are removed to thereby form such a silicon substrate 61 that has, formed thereon, a plurality of first element isolating regions dielectrically isolated from each other by the first element isolating region 76 made up of the first field oxide film (thin film) 69 and the second field oxide film (thick film) 74 and a plurality of second element regions 79 dielectrically isolated from each other by the second element isolating region 78 made up of the third field oxide film (thick film) 75.
The above-mentioned semiconductor device manufacturing method forms the element isolating region using LOCOS in two steps and so can form the first element isolating region 76 and the second element isolating region 78 that respectively meet the requirements of the first circuit element requiring a thicker element isolating region and the second circuit element only requiring a thinner element isolating region.
By this semiconductor device manufacturing method, however, when forming the first element isolating region 76 requiring an especially thick element isolating region, the silicon nitride film 63 having the opening 67 therein is used as a mask commonly for the first field oxidation shown in FIG. 6D for forming the first field oxide film (thin film) 69 and the second field oxidation shown in FIG. 6G for forming the second field oxide film (thick film) 74, so that the first and second field oxide films 69 and 74 spread laterally by almost the same width. Therefore, both bird""s beaks 69A and 74A inevitably bite deep into a first element region 77.
The semiconductor device manufacturing method for forming the element isolating region using LOCOS in two steps is disclosed, for example, in Laid-open Japanese Patent Application No. Hei 9-330922. By this semiconductor device manufacturing method, as shown in FIG. 7A, first a pad oxide film 82 and a nitride film 83 are patterned and formed on a semiconductor substrate 81 and then, using the nitride film 83 as a mask, a first thermal oxidation is performed to form a thicker first field oxide film 84. Next, as shown in FIG. 7B, the nitride film 83 is etched using, for example, phosphoric acid to remove the pad oxide film 82 using, for example, BOE (Buffered Oxide Etchant) in order to reduce a size of both films 83 and 82, thus exposing the semiconductor substrate 81. Next, as shown in FIG. 7C, a second thermal oxidation is performed using thus small-sized nitride film 83 as a mask to thereby form a thinner second field oxide film 85 on the above-mentioned exposed surface. Next, as shown in FIG. 7D, the nitride film 83 and the pad oxide film 82 are removed to thereby obtain such the semiconductor substrate 81 that has, formed thereon, a plurality of element regions 86 dielectrically isolated from each other by an element isolating region made up of the thicker first field oxide film 84 and the thinner second field oxide film 85.
Another semiconductor device manufacturing method for likewise forming the element isolating region using LOCOS in two steps is disclosed, for example, in Japanese Laid-open Patent Application No. Hei9-330923.
By this semiconductor device manufacturing method, which employs a so-called fully recessed LOCOS method, as shown in FIG. 8A, first on a semiconductor substrate 91 is formed by patterning an oxidation preventing film pattern 93 which has therein an opening T2 formed by a pad oxide film 92 and a nitride film, which oxidation preventing film pattern 93 is then used as a mask to perform a first thermal oxidation to thereby form a first field oxide film 94 on the semiconductor substrate 91 at a lower part of the pad oxide film 92 exposed through the opening T2. At sides of this first field oxide film 94 is formed a bird""s beak 94A. Next, as shown in FIG. 8B, on a side wall of the oxidation preventing film pattern 93 is formed a spacer 95 made of a nitride film. And then, by using both oxidation preventing film pattern 93 and spacer 95 as a mask, in the first field oxide film 94 is formed a recess 96 which is shallower than thickness of the first field oxide film 94 as shown in FIG. 8C. Alternatively, this recess 96 may well be formed throughout on all thicknesses of the first field oxide film 94.
Next, as shown in FIG. 8D, a second thermal oxidation is performed using the oxidation preventing film pattern 93 and the spacer 95 to oxidize the first field oxide film 94 having the recess 96 formed therein in order to form a second field oxide film 97 thicker than the first field oxide film 94 at a position corresponding to an opening in the spacer 95. Next, as shown in FIG. 8E, the pad oxide film 92 and the oxidation preventing film pattern 93 are removed to obtain such the semiconductor substrate 91 that has, formed thereon, a plurality of element regions 98 dielectrically isolated from each other by an element isolating region made up of the thinner first field oxide film 94 and the thicker second field oxide film 97.
By the above-mentioned semiconductor device manufacturing method, especially, the spacer 95, which is formed on the side wall of the oxidation preventing film pattern 93, can suppress bite-in of the bird""s beak 94A when the second field oxide film 97 is formed by the second thermal oxidation, thus preventing the bird""s beak 94A from biting deep into the element region 98.
Also, still another semiconductor device manufacturing method forming the element isolating region using LOCOS in two steps is disclosed, for example, in Japanese Laid-open Patent Application No. Hei 10-284477.
By this semiconductor device manufacturing method, as shown in FIG. 9A, first on a semiconductor substrate 101 is formed by patterning a nitride film 103 having a pad oxide film 102 and an opening 103A, which nitride film 103 is then used as a mask to perform a first thermal oxidation to form a first field oxide film 104 on the semiconductor substrate 101 at a lower part of the pad oxide film 102 exposed through the opening 103A. Next, as shown in FIG. 9B, for example, RIE (Reactive In Etching) is performed using the nitride film 103 having the opening 103A therein as a mask to selectively etch the first field oxide film 104, thus forming an opening 105 penetrating through the first field oxide film 104. Alternatively, this opening 105 may not penetrate through the first field oxide film 104, thus forming a remaining film.
Next, as shown in FIG. 9C, a second thermal oxidation is performed using the nitride film 103 having the opening 103A therein as a mask to thereby oxidize the first field oxide film 104 having the opening 105 formed therein, thus forming a second field oxide film 106. Next, as shown in FIG. 9D, the nitride film 103 is removed to thereby obtain such the semiconductor substrate 101 that has, formed thereon, a plurality of element regions 108 dielectrically isolated from each other by an element isolating region made up of the first field oxide film 104 and the second field oxide film 106. By this semiconductor device manufacturing method, it is possible to form a thick element isolating region made up of the first field oxide film 104 and the second field oxide film 106, thus maintaining sufficiently good isolation between the element regions even with a small distance between the element isolating regions.
The prior art semiconductor device manufacturing methods disclosed in the above two publications for forming the element isolating region using LOCOS in two steps have such respective problems as follows.
First, by the semiconductor device manufacturing method disclosed in Japanese Laid-open Patent Application No. Hei 9-330922, as shown in FIGS. 7A to 7D, the nitride film 83 used as an oxidation preventing mask when forming the first field oxide film 84 is reduced in size by wet etching after the first field oxide film 84 is formed to thereby reserve the exposed surface of the semiconductor substrate 81, on which the second field oxide film 85 is then formed, so that the element isolating region has a width as much as the first field oxide film 84 plus the second field oxide film 85. Therefore, an inside region of the first field oxide film 84 which can be used as the element region 86 originally is occupied by the second field oxide film 85, thus resulting in a disadvantage of reduced lateral dimension of the element region 86.
By the next semiconductor device manufacturing method disclosed in Japanese Laid-open Patent Application No. Hei 9-330923, as shown in FIGS. 8A to 8E, the fully recessed LOCOS method is applied in a premise, so that the spacer 95 made of a nitride film is formed on the side wall of the oxidation preventing film pattern 93 used when forming the first field oxide film 94 prior to the second thermal oxidation. Then, this spacer 95 is used as part of the oxidation preventing film in the second thermal oxidation to thereby form the second field oxide film 97. To thus form the spacer 95 made of the nitride film on the side wall of the oxidation preventing film pattern 93, however, prior to the formation of the second field oxide film 97, such extra steps are required as forming an nitride film thoroughly and processing this nitride film into the spacer 95, thus resulting in a disadvantage of an increased number of steps required in manufacturing. Further, there also occur such a disadvantage that a bird""s beak 94A bites into the thick field oxide film and such another disadvantage that a photolithography process results in a small distance between a photo-resist film edge and a oxide film edge.
Next, by the semiconductor device manufacturing method disclosed in Japanese Laid-open Patent Application No. Hei 10-284477, as shown in FIGS. 9A to 9D, the nitride film 103 having the opening 103A therein is used as an oxidation preventing film commonly in both oxidation steps for formation of the first field oxide film 104 and the second field oxide film 106, so that as in the case of the prior art described with reference to FIGS. 6A to 6H, the first and second field oxide films 104 and 106 spread laterally by roughly the same width. Therefore, this method has a disadvantage that the bird""s beak of the first and second field oxide films inevitably bites deep into the element region 108. Further, it has a disadvantage that the bird""s beak bites deep into a thick field oxide film as well as another disadvantage that a photolithography process results in a small distance between a photo-resist film edge and an oxide film edge.
In view of the above, it is an object of the invention to provide a semiconductor device in which bite-in of a bird""s beak into an element region can be suppressed to flatten the surface of the element region when an element isolating region is formed using LOCOS in two steps and a method for manufacturing the same.
According to a first aspect of the present invention, there is provided a semiconductor device manufacturing method for selectively forming an element isolating region on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the element isolating region, including:
a first oxidation preventing film forming step of covering an element-isolating region formation-expected region on the semiconductor substrate with a first oxidation preventing film having a first opening therein;
a first field oxide film forming step of performing first field oxidation on the semiconductor substrate to thereby selectively form a first field oxide film at such a position in the element-isolating region formation-expected region that is not covered with the first oxidation preventing film;
a second oxidation preventing film forming step of removing the first oxidation preventing film to then cover the first field oxide film with a second oxidation preventing film having a second opening having a set width dimension smaller than the first opening; and
a second field oxide film forming step of performing second field oxidation on the semiconductor substrate to thereby selectively form a second field oxide film which overlaps partially with the first field oxide film and also which is located deeper in level than the first field oxide film at such a position in the element-isolating region formation-expected region that corresponds to the second opening in the second oxidation preventing film.
In the foregoing first aspect, a preferable mode is one that wherein further including a recess forming step of using the first oxidation preventing film as a mask to thereby form a recess in the first element-isolating region formation-expected region between the first oxidation preventing film forming step and the first field oxide film forming step.
Also, a preferable mode is one wherein the recess can be changed in formation arbitrarily in width and depth.
According to a second aspect of the present invention, there is provided a semiconductor device manufacturing method for selectively forming a first element isolating region with a larger film thickness and a second element isolating region with a smaller film thickness on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the first element isolating region and second element isolating region, including:
a first oxidation preventing film forming step of covering a first element-isolating region formation-expected region and a second element-isolating region formation-expected region on the semiconductor substrate with a first oxidation preventing film having a first opening therein in such a way that the first opening may be located above the first element-isolating region formation-expected region;
a first field oxide film forming step of performing first field oxidation on the semiconductor substrate to thereby selectively form a first field oxide film only at such a position in the first element-isolating region formation-expected region that is not covered with the first oxidation preventing film;
a second oxidation preventing film forming step of removing the first oxidation preventing film to then cover the semiconductor substrate with a second oxidation preventing film having a second opening and a third opening which have set width dimensions smaller than the first opening in such a way that the second opening may be located above the first field oxide film and also that the third opening may be located above the second element-isolating region formation-expected region; and
a second and third field oxide films forming step of performing second field oxidation on the semiconductor substrate to thereby selectively form a second field oxide film which overlaps partially with the first field oxide film and also which is located deeper in level than the first field oxide film only at such a position in the first element-isolating region formation-expected region that corresponds to the second opening in the second oxidation preventing film and, at the same time, selectively forms a third field oxide film only at such a position in the second element-isolating region formation-expected region that corresponds to the third opening.
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method for selectively forming an element isolating region on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the element isolating region, including:
a first oxidation preventing film forming step of covering an element-isolating region formation-expected region on the semiconductor substrate with a first oxidation preventing film having a first opening therein;
a first field oxide film forming step of performing first field oxidation on the semiconductor substrate to thereby selectively form a first field oxide film at such a position in the element-isolating region formation-expected region that is not covered with the first oxidation preventing film;
a second oxidation preventing film forming step of removing the first oxidation preventing film to then cover the first field oxide film with a second oxidation preventing film having a second opening therein which has a set width dimension larger than the first opening; and
a second field oxide film forming step of performing second field oxidation on the semiconductor substrate to thereby selectively form a second field oxide film which overlaps partially with the first field oxide film and also which is located shallower in level than the first field oxide film at such a position in the element-isolating region formation-expected region that corresponds to the second opening in the second oxidation preventing film.
According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method for selectively forming a first element isolating region with a larger film thickness and a second element isolating region with a smaller film thickness on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the first element isolating region and second element isolating region, including:
a first oxidation preventing film forming step of covering a first element-isolating region formation-expected region and a second element-isolating region formation-expected region on the semiconductor substrate with a first oxidation preventing film having a first opening therein in such a way that the first opening may be located above the first element-isolating region formation-expected region;
a first field oxide film forming step of performing first field oxidation on the semiconductor substrate to thereby selectively form a first field oxide film only at such a position in the first element-isolating region formation-expected region that is not covered with the first oxidation preventing film;
a second oxidation preventing film forming step of removing the first oxidation preventing film to then cover the semiconductor substrate with a second oxidation preventing film having a second opening and a third opening which have set width dimensions larger than the first opening in such a way that the second opening may be located above the first field oxide film and also that the third opening may be located above the second element-isolating region formation-expected region; and
a second and third field oxide films forming step of performing second field oxidation on the semiconductor substrate to thereby selectively form a second field oxide film which overlaps partially with the first field oxide film and also which is located shallower in level than the first field oxide film only at such a position in the first element-isolating region formation-expected region that corresponds to the second opening in the second oxidation preventing film and, at the same time, selectively form a third field oxide film only at such a position in the second element-isolating region formation-expected region that corresponds to the third opening.
In the foregoing second aspect, a preferable mode is one that wherein further including another recess forming step of using the second oxidation preventing film as a mask to thereby form another recess in the second element-isolating region formation-expected region between the second oxidation preventing film forming step and the second and third field oxide films forming step.
Also, a preferable mode is one wherein the recess can be changed in formation arbitrarily in width and depth.
According to a fifth aspect of the present invention, there is provided a semiconductor device in which a semiconductor substrate thereof is dielectrically isolated into a plurality of element regions by an element isolating region which is selectively formed on the semiconductor substrate, wherein the element isolating region includes:
a first field oxide film which is selectively formed at such a position in an element-isolating region formation-expected region that is not covered with a first oxidation preventing film having a first opening therein; and
a second field oxide film which is selectively formed at such a position in the element-isolating region formation-expected region that is not covered with a second opening of a second oxidation preventing film having the second opening with a smaller width dimension than the first opening and also which is locally formed so as to be thicker at around a middle of the first field oxide film.
According to a sixth aspect of the present invention, there is provided a semiconductor device in which a first element isolating region with a larger film thickness and a second element isolating region with a smaller film thickness are selectively formed on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the first element isolating region and second element isolating region, wherein:
the first element isolating region includes a first field oxide film which is selectively formed at such a position in a first element-isolating region formation-expected region that is not covered with a first oxidation preventing film having a first opening and a second field oxide film which is selectively formed at such a position in the first element-isolating region formation-expected region that is not covered with a second opening of a second oxidation preventing film having the second opening with a smaller width dimension than the first opening and also which is locally formed so as to be thicker at around a middle of the first field oxide film; and
the second element isolating region includes a third field oxide film which is selectively formed at such a position in a second element-isolating region formation-expected region that is not covered with the second oxidation preventing film having a third opening.
According to a seventh aspect of the present invention, there is provided a semiconductor device in which a semiconductor substrate thereof is dielectrically isolated into a plurality of element regions by an element isolating region which is selectively formed on the semiconductor substrate, wherein the element isolating region includes:
a first field oxide film which is selectively formed at such a position in an element-isolating region formation-expected region that is not covered with a first oxidation preventing film having a first opening therein; and
a second field oxide film which is selectively formed at such a position in the element-isolating region formation-expected region that is not covered with a second oxidation preventing film having therein a second opening with a larger width dimension than the first opening and which overlaps partially with the first field oxide film and also which is formed shallower in level than the first field oxide film.
Also, according to an eighth aspect of the present invention, there is provided a semiconductor device in which a first element isolating region with a larger film thickness and a second element isolating region with a smaller film thickness are selectively formed on a semiconductor substrate so that the semiconductor substrate may be dielectrically isolated into a plurality of element regions by the first element isolating region and second element isolating region, wherein:
the first element isolating region includes a first field oxide film which is selectively formed at such a position in a first element-isolating region formation-expected region that is not covered with a first oxidation preventing film having a first opening therein and a second field oxide film which is selectively formed at such a position in the first element-isolating region formation-expected region that is not covered with a second opening of the second oxidation preventing film having a second opening with a larger width dimension than the first opening; and
the second element isolating region includes a third field oxide film which is selectively formed at such a position in a second element-isolating region formation-expected region that is not covered with the second oxidation preventing film having a third opening.
With the above configurations drawn to the semiconductor device manufacturing method, on the substrate, an element-isolating region formation-expected region is masked by a first oxidation preventing film having a first opening therein in the first field oxidation to thereby form a first field oxide film, which is then masked by a second oxidation preventing film having a second opening therein having a set width dimension smaller than the first opening in the second field oxidation to thereby locally form a second field oxide film at around the middle of the first field oxide film, thus enabling arbitrarily controlling the film thickness of the element isolating region around the element region.
Also, with the above configurations drawn to the semiconductor device, a plurality of element regions is dielectrically isolated from each other by an element isolating region selectively formed on the silicon substrate, which element isolating region includes a first field oxide film which is selectively formed at a position not covered with a first oxidation preventing film having a first opening therein of an element-isolating region formation-expected region and a second field oxide film which is selectively formed at a position not covered with a second oxidation preventing film having a second opening therein with a smaller width dimension than the first opening of the element-isolating region formation-expected region and also which is locally formed so as to be thicker at around the middle of the first field oxide film, thus enabling formation the element isolating region having an arbitrary film thickness.
Thus, when the element isolating region is formed by LOCOS in two steps, the bird""s beak can be suppressed from biting deep into the element region, thus flattening the surface of that element region.

Semiconductor device and method for manufacturing the same that includes a dual oxidation


The present invention relates to estimating the Angle of Arrival (AoA) of a signal from a user equipment received at a base station of a wireless telecommunications network where the base station has a multi-beam antenna. A signal received from a user equipment is received by the each of the multiple beams of the antenna, and the two adjacent beams receiving the highest amplitude from the end user are selected. A ratio of functions of the amplitudes of the two selected beams, such as a ratio of the difference between the amplitudes of the two beams to the sum of the amplitudes is calculated and compared to a data store of ratios. The data store stores expected ratios corresponding to AoAs and the calculated ratio is compared to the pre-calculated expected ratios to extract an estimate of the AoA of the signal from the user equipment.

A typical cell of a wireless telecommunications network has a central base station transmitting and receiving radio frequency (rf) signals over a geographical area or cell bounded by a boundary of theoretical equal signal strength with adjacent cells. The network is made up of a plurality of such cells mosaiced over a wider geographical area, as is well known in the art. The cell may be divided into sectors with typically one or more single beam antenna of the base station covering each sector.
There is currently a requirement from end users of mobile user equipments for location aware services, in which the network is aware of the location of the end user. An example might be services for advising end users of traffic jams in their location or for advising end users of local services, such as restaurants in their location.
Several schemes have so far been utilised to determine position location of a user equipment within a telecommunications network. Cell ID and enhanced cell ID provide position location by identification of the cell within which the end user equipment is located. While this system requires no modifications to the user equipment, it cannot provide precise location positioning. Another alternative, Global Positioning System (GPS) is relatively expensive, although accurate. It suffers from the disadvantage that it can take some time for a user equipment to acquire and lock on to satellites, coverage is poor indoors, power consumption by the user equipment is high and a specially modified user equipment is required. Assisted GPS enables the user equipment to acquire and lock on to a satellite more quickly but still suffers from the other disadvantages of GPS. Enhanced-Observed Time Difference (E-OTD) provides relatively accurate position location, but again requires modified user equipments. In addition network wide synchronisation or additional timing measurement devices have to be deployed in the network. Finally, Cumulative Virtual Blanking (CVB) is a complex scheme which enables the deployment of E-OTD in Code Division Multiple Access (CDMA) networks. Again modified user equipments are required.
User equipment position location can be derived by triangulation between multiple base stations. However, this requires an array of antennas in each sector of each base station in the network. Algorithms which act directly on the outputs of the antennas (or antenna columns) of such an array are expensive to implement. This is because they require either a full receiver chain at each output, or a single receiver chain plus a complex and high speed switching module to commutate this single receiver across multiple antennas.
To maximise the capacity of the base station downlink, it has been proposed to use multi-beam or beamformed antenna arrays to cover each sector of the cell of the base station, for example, three beam per sector deep cusp antennas. It is envisaged that the additional equipment complexity of the multi-beam antenna arrays and associated signal processing will be compensated for by the enhanced downlink capacity achieved. The angular position of a user equipment within a cell sector is most likely to be aligned in some way with the beam through which the received signal power is the greatest however, estimating the Angle of Arrival (AoA) of a signal on the uplink simply by picking the beam with the strongest signal would not be accurate enough for practical purposes because in the three beam per sector case, with deep cusp beams, each beam has a width between crossovers of around 40°.

Angle of arrival estimation in a wireless telecommunications network


A light-emitting diode matrix comprises a substrate, first and second electrodes electrically insulated from each other formed in or on the substrate, and a first organic layer on the first electrode and a second organic layer on the second electrode. The first organic layer is separated from the second organic layer by separator means. Further, the light-emitting diode matrix comprises a cap electrode with an area disposed on the first organic layer and an area disposed on the second organic layer. The areas of the cap electrode are connected in an electrically conductive way via an area of the cap electrode disposed on the separator means.

Based on organic light-emitting diodes (OLED), new flat displays with many advantages can be realized. Part of theses advantages is wide-area deposition on different substrates, self-illuminating characteristics, allowing very thin displays, a high independence of the angle of view and the potentially high efficiency of such displays.
For realizing such displays, structuring into different emitting elements, so called pixels, is required. This applies particularly for full color displays, where those pixels have to be realized such that they emit in different colors. Structuring via shadow masking technology can no longer be applied in small pixels in mini or microdisplays.
The possibility of producing such structures depends heavily on the used materials. On the one hand, organic light-emitting diodes have been realized based on polymers, which are often disposed as solutions. In that case, it is possible to perform structuring the pixels by printing methods. For example, it could be shown that efficient pixeling is possible by ink jet printing. In this pixeling technology, the resolution limit of the pixels is at approximately 50 to 100 μm. Organic light-emitting diodes of polymers, however, also have their disadvantages, for example a lower life span compared to vapor-deposited organic light-emitting diodes.
These printing techniques are not available for light-emitting diodes based on vapor-deposited materials. Further, it is important for the quality of the produced LEDs, to perform all structuring in vacuum.
U.S. Pat. No. 5,701,055 describes a possibility for obtaining structuring with integrated disruption edges, called separators below, for monochrome passive matrix displays, i.e. displays without individual control circuit. Here, both an organic layer and a cap electrode are structured by an undercut edge between individual rows.
However, for color displays it is necessary to realize selectively different colors. Conventionally, this is obtained by a lateral separation of a pixel into three subpixels for red, green and blue. In order to obtain sufficient luminosity of the pixel, every subpixel has to illuminate with threefold luminosity according to the area proportion of maximum one third of the total pixel, to represent a corresponding light-emitting diode of the overall pixel for the viewer. In the real case, the area proportion of a subpixel is at fewer than 33%. Due to the increased control, a higher current intensity is required for every pixel. Thereby, at the same time, the life span of the pixel is reduced.
A standard approach for structuring the vapor-deposited organic light-emitting diodes in the subpixels is based on evaporating colorants through a shadow mask. Such vapor-deposition through a shadow mask has been basically shown in the laboratory scale. However, the same is limited to displays with relatively low dimensions, since larger masks tend to distort. Further, such shadow masks tend to clog and block with colorants. This requires that the masks be frequently cleaned, which is a significant disadvantage in an industrial production process. Displays with subpixel sizes in the demonstration scale of up to 50 μm have already been presented. However, with smaller pixel sizes, this method can no longer be applied. Already with pixel sizes for so called minidisplays with a diagonal of more than "1", only a little area of the pixel can be used for the actual OLED, since a distance between different colors has to be maintained due to the inaccuracies of the shadow masks, in order to avoid overlapping of the subpixels.
For even higher resolutions, approaches are known, which use a realization of white emitters that are correspondingly filtered by color filters. In light-emitting diodes, which emit through the substrate, so-called substrate emitters, the filters can be applied prior to depositing light-emitting diodes on the substrate. In top emitters, the filters can be applied after depositing the light-emitting diodes. A large advantage of this method is the usage of a full-area deposition of the organic layer without having to use shadow masks. A disadvantage of this method is an efficiency loss due to the color filters and an optical and/or electrical crosstalk of neighboring pixels due to the non-structuring of the organic layers.

Light-emitting diode matrix and method for producing a light-emitting diode matrix

Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.


The disclosure describes an active network interface device (NID) enclosure having a modular construction that provides flexibility to a vendor and permits independent access to technician-accessible connections and subscriber-accessible connections while promoting resistance to environmental and security threats. The active NID enclosure includes an electronics enclosure and an access enclosure. The electronics enclosure contains active electronic components for conversion of data carried on a network signal carrier into services for delivery to subscriber devices. The access enclosure includes two separate access compartments, having separate covers, for independent access to either network terminals or subscriber terminals.

Integrated networks transmit voice, video and data to subscribers via network signal carriers in the form of coaxial cable or optical fiber. An example of an integrated network is a passive optical network (PON), which can deliver voice, video and other data among multiple network nodes, often referred to as optical network terminations (ONTs), using a common optical fiber link. Passive optical splitters and combiners enable multiple ONTs to share the same optical fiber link. An optical line terminations (OLT) transmits information downstream to the ONTs, and receives information transmitted upstream from the ONTs. Each ONT terminates the optical fiber link for a residential or business subscriber, and is sometimes referred to as a subscriber premises node.
An ONT in a PON functions as an active network interface device (NID). An active NID converts information received on a network signal carrier into services suitable for use by various subscriber devices, such as telephone, video and data services. For example, an active NID in a PON converts optical signals received from the network on an optical fiber to electrical signals for transmission to a subscriber device. In addition, the active NID converts information received from the subscriber devices into integrated data for transmission over a network signal carrier, such as an optical fiber.
Some active NIDs have an enclosure with three different covers that serve to protect electronic circuitry and network terminals from environmental conditions and security threats. For example, the electronic circuitry in a NID is typically fabricated on a circuit card and enclosed in a first, inner protective cover to reduce electromagnetic interference (EMI) emissions and susceptibility to EMI. Shielding the circuit card from EMI improves the reliability of the electronic circuitry to convert the data into useful services for the subscriber.
A second, intermediate protective cover encloses both the circuit card and the first protective cover, as well as the connections to the integrated network, and is accessible only by a service technician via a security latch. In this manner, the NID and its protective cover create a demarcation point between integrated network terminals accessible only by the service technician, and subscriber network terminals accessible by the subscriber. The intermediate cover typically encloses network terminals which require training to handle, such as power inputs, safety ground, and the main signal input, which may be carried by coaxial cable, or fiber optic cable, so as to provide safety measures and prevent tampering by the subscriber or others.
The intermediate cover does not cover the subscriber connections. Instead, the subscriber is permitted to access subscriber terminals such as binding posts or jacks for plain old telephone service (POTS) wires, coaxial cables, and data connections in order to disconnect wiring leading into the subscriber's premise and test the outside line directly. For example, the subscriber can test outside phone lines by plugging a modular phone directly into a POTS connection, such as an RJ-11 phone jack in order to determine if there is a problem with the subscriber's wiring inside the subscriber premises or with the network. The subscriber also may have access to lightning protection for telephony, cable television, Ethernet and safety grounding. A third, outer cover encloses the circuit card, the inner cover, the intermediate cover, the network terminals, and the subscriber terminals, providing the NID with protection from moisture, debris, solar loading, animals and other adverse environmental conditions.


The disclosure relates to an organic electroluminescence element including an organic layer including multiple light-emitting layers. The light-emitting layers include a blue light-emitting layer including a blue light-emitting dopant. In a case where emission color of the organic electroluminescence element operated at an operation temperature for a stable state is represented in a CIE1931 chromaticity coordinate system, when coordinate point A of the emission color at an early stage of use and coordinate point B of the emission color deteriorated by use are represented by (x1, y1) and (x2, y2) respectively, a relation of y2≧y1 is satisfied. When amounts of changes in x and y values from coordinate point A to coordinate point B are represented by equations of Δx=x2−x1 and Δy=y2−y1 respectively, a relation of Δy≧Δx is satisfied. It can be made difficult to perceive change in emission color and lifetime can be prolonged

In the past, there has been known an organic electroluminescence element (hereinafter referred to as "organic EL element" if needed) which includes a stack in which a light-emitting layer including a light-emitting dopant is between a pair of electrodes, and causes light emission by recombination of electrons and holes in the light-emitting layer.

Organic electroluminsescence element and lighting device

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


There is disclosed a polycrystalline silicon solar cell, utilizing a continuous polycrystalline silicon film consisting of single crystals grown from a plurality of small nucleation surfaces provided on a non-nucleation surface. The semiconductor junction, providing the photoelectromotive force of the solar cell, is formed on the single crystals, avoiding the areas of grain boundaries formed by mutual contact of the single crystals, in order to eliminate the drawbacks resulting from such boundaries. The semiconductor junction is formed by masking the areas of the grain boundaries with a suitable masking material, such as photoresist.

1. Field of the Invention
The present invention relates to a solar cell adapted for use as a power source for various electronic equipment or as a power source for power generating facilities, and more particularly a large-grain polycrystalline solar cell with a high energy conversion efficiency and with satisfactory mass producibility, and a method for producing such solar cell.
2. Related Background Art
Solar cells have been utilized as power sources for various equipment. Such solar cells include a p-n junction as the functional part, and the semiconductor constituting such p-n junction is generally silicon. Monocrystalline silicon is preferable in terms of efficiency for converting the light energy into electric power, but amorphous silicon is considered more advantageous in formation of large-area devices and in cost reduction. In recent years, there has been investigated the use of polycrystalline silicon, for the purpose of attaining a low cost, as with amorphous silicon, and a high energy conversion efficiency as with monocrystalline silicon. However, in the conventionally proposed method, utilizing plate-shaped materials obtained by slicing a block of polycrystal, it has been difficult to reduce the thickness of the device below 0.3 mm. Consequently, the device becomes excessively thicker than required for sufficient light absorption, and the material has not effectively been utilized. Thus, for cost reduction, formation of a sufficiently thin structure is essential.
For this purpose, there has been investigated the formation of a thin film of polycrystalline silicon by thin film forming technologies such as chemical vapor deposition (CVD), but such methods have only provided crystals with a grain size less then 1/10 micron, so that the energy conversion efficiency is even lower than that obtained with the plate sliced from a polycrystalline silicon block.
Also, there has been reported a so-called "abnormal grain growing method" (Yasuo Wada and Shigeru Nishimatsu, Journal of Electrochemical Society, Solid-State Science and Technology, 125 (1978) 1499) for expanding the grain size even in excess of 10 times the film thickness, by introducing atoms of an impurity such as phosphorus by ion implantation to a supersaturated state into the above-mentioned polycrystalline thin silicon film, formed by CVD, and then annealing said film at a high temperature. However, such film cannot be used as the active layer for generating the photocurrent because of the excessively high impurity concentration. Also, there has been an attempt to irradiate a polycrystalline thin silicon film with a laser beam, thereby enlarging the crystal grain size by fusion and recrystallization, but such method cannot achieve sufficient cost reduction and stable manufacture.
The above described situation exists not only with silicon but also with compound semiconductors.
On the other hand, a solar cell as shown in FIG. 3 can be obtained by forming, on a substrate surface, a different material having a nucleation density sufficiently higher than that of the material constituting the substrate surface and having a size sufficiently small for growing a single nucleus, then forming a substantially monocrystalline semiconductor layer of a first conductivity type on said substrate surface, including a step of forming a nucleus by deposition on said different material and growing a crystal from said nucleus, and growing, on said monocrystalline layer, a substantially monocrystalline semiconductor layer of a second conductivity type. Such polycrystalline solar cell has been shown to have a small thickness, a sufficiently large crystal grain size, and a high energy conversion efficiency.
Such solar cell and the method for producing the same are disclosed, for example, in the European Patent Office Laid-Open Application No. 0276961.
In a polycrystalline semiconductor, however, a number of crystal grain boundaries (hereinafter simply written as grain boundaries) are formed by many monocrystalline grains of different crystal orientations, and defect energy levels are formed in the forbidden band because of the presence of atoms with dangling bonds at such boundaries. The characteristics of the semiconductor device are closely related to the defect density of the prepared semiconductor layer, and the grain boundaries not only have the above-mentioned defect levels but also tend to induce segregation of impurities, both of which give rise to deterioration of the characteristics of the device. Therefore, with a polycrystalline semiconductor, the characteristics of the obtained device are generally considered to be significantly affected by control of the grain boundaries. More specifically, in order to improve the characteristics of a semiconductor device utilizing a polycrystalline semiconductor layer, it is effective to reduce the number of grain boundaries present in the semiconductor layer. In the method for forming the device shown in FIG. 3, the number of grain boundaries can be reduced by increasing the grain size. In this method, the first substantially monocrystalline layer is immediately covered by the second substantially monocrystalline layer, so that the solar cell is composed, as shown in FIG. 3, of a substrate 301, a silicide layer 302, an insulating layer 303, continuously formed polycrystalline silicon films 304, 305, a transparent conductive layer 306, all in a stacked structure, and a current collecting electrode 307. In such configuration, though the number of grain boundaries is reduced in comparison with that in an ordinary polycrystalline semiconductor of smaller gain size, certain grain boundaries 308 are still included at the junction, as such boundaries are inevitably formed at the contact of single crystals, each grown from a single nucleus formed on the small-sized different material constituting the nucleation surface. For this reason, the open circuit voltage of such a device based on a polycrystalline semiconductor is lower than that based on a monocrystalline semiconductor. Therefore, the conventional configuration based on polycrystalline silicon tends to show a high level of dark current resulting from recombination and a relatively low level of photocurrent.
Also, the p-n junction is usually formed in the vicinity of a light-receiving surface of the semi-conductor layer. In the case of a polycrystalline semi-conductor, active grain boundaries 203 in an n (or p) area 201 and a p (or n) area 202 are included in the p-n junction as shown in FIG. 2, thus causing recombination. Therefore the dark current increases significantly in comparison with that of a monocrystalline semiconductor, eventually leading to the deterioration of electrical characteristics, particularly a decrease in the open circuit voltage. Also, the presence of many grain boundaries deteriorates the photosensitivity, thus decreasing the photocurrent. For these reasons, the open-circuit voltage of an ordinary solar cell based on polycrystalline silicon has not exceeded 0.5 V unless certain measures, such as hydrogen passivation, are adopted.

Solar cell and method for producing the same


A method of transmitting a spread spectrum signal in a single communication session between a transmitter and a receiver, stores a series of N unique waveform designs and a hopping sequence in a transmitter memory. A signal is transmitted to a receiver according to the hopping sequence using the plurality of N unique waveform designs. Preferably, each waveform design is characterized by a unique composite spreading code that is formed by at least some of a plurality of constituent code segments. Alternatively or additionally, the waveform designs may differ by any one or more of code length, symbol or chip timing or phase, frame or burst structure, chip offset, modulation, error control coding, encryption scheme, or scrambling code. A transmitter and receiver are also disclosed, as is the concept of appending chips between symbols to expand the universe of unique spreading codes without incurring an increase in processing gain.

In digital spread spectrum (DSS) communication, a wide band carrier signal is modulated by a narrow band message signal. The wide-band carrier is typically generated by modulating a single frequency carrier using a pseudo-random noise (P/N) code sequence. The data rate at which a message is communicated is usually much lower than the P/N code symbol or "chip" rate. The ability of DSS to suppress interference is proportional to a ratio of the chip rate to data rate. In many applications, there are thousands of code chips per data bit. There are two basic types of DSS systems: direct sequence spread spectrum systems (DSSS) and frequency hop spread spectrum systems (FHSS).
The DSSS systems spread the signal over a bandwidth fRF±Rc, where fRF represents the center bandpass carrier frequency and Rc represents the PN-code maximum chip rate, which in turn is an integer multiple of the symbol rate Rs. Multiple access systems employ DSSS techniques when transmitting multiple channels over the same frequency bandwidth to multiple receivers, each receiver having its own designated PN-code. Although each receiver receives the entire frequency bandwidth only the signal with the receiver's matching PN-code will appear intelligible, the rest appears as noise that is easily filtered. The DHSS system PN-code sequence spreads the data signal over the available bandwidth such that the carrier appears to be noise-like and random, but is deterministic to a receiver using the same PN-code. These systems are well known in the art and will not be discussed further.
FHSS systems employ a PN-code sequence generated at the modulator that is used in conjunction with an m-ary frequency shift keying (FSK) modulation to shift the carrier frequency fRF at a hopping rate Rh. A FHSS system divides the available bandwidth into N channels and hops between these channels according to the PN-code sequence. At each frequency hop time a PN generator feeds a frequency synthesizer a sequence of n chips that dictates one of 2 n frequency positions. The receiver follows the same frequency hop pattern. FHSS systems are also well known in the art and need not be discussed further.
At the receiver, a carrier replica is generated by reducing the DSS signal to baseband and multiplying it with a locally generated replica of the original narrow-band carrier using a local oscillator. If the frequency and phase of the carrier replica is the same as that of the received original narrow-band carrier, then the multiplier output signal will be the product of the bipolar P/N code and intended message. The P/N code is removed by multiplying the wide-band data stream with the locally generated replica of the P/N code that is time aligned with the received P/N code. The de-spreading process of generating the carrier replica with proper carrier frequency and phase and generating the P/N code replica at the proper rate and time offset is a complex problem. In many DSS communication systems, the necessary carrier frequency, carrier phase, and P/N code offset are not known a priori at the receiver, which tries different values until a large signal is observed at the data-filter output. This is termed the search or acquisition process, and a DSS signal is said to be acquired when the proper frequency, phase, and code offset have been determined.
The above cross-referenced patent applications also detail various concerns for security in DSS communication systems, along with exemplary wireless environments in which a secure DSS system is advantageously deployed. One such security concern is low probability of intercept (LPI) and low probability of detection (LPD) by adverse parties of messages sent over the secure DSS system. Once a secure spreading code is known to an unauthorized user, some or all of the messages over the system may be compromised, and the breach may not be known immediately to the authorized parties. Further, in some communication systems such as space-based satellite DSS systems that may or may not be a secure system, certain hardware systems must be hardened against ambient radiation such as alpha particles. Typically, the hardware of concern is made to resist some minimal level of radiation and the overall system employs triple redundancy to ensure against failure of any single or pair of like components. This is an expensive proposition, both in the radiation hardening, in the redundancy of components, and in the additional weight to be launched into space. By reloading often, some of this redundancy may be eliminated.
Frequency hopping is known in the art. Adaptive modulation is also known in the art of multiple-input/multiple output communication systems, but this is generally not considered a hopping technique as modulation is changed in response to channel conditions rather than according to a predetermined schedule or sequence. It is also known in the art to use code hopping as an encryption technique for securing communications in a DSS system. For example, U.S. Pat. No. 6,657,985 to Su-Won Park, entitled "Orthogonal Code Hopping Multiple Access Communication System", describes a system that divides channels according to hopping patterns of the orthogonal codes allotted to the respective channels. In an illustrated embodiment, a first orthogonal code OC hops three times for every bit stream duration, a second OC hops once per bit stream duration, and a third OC hops at multiples of the bit stream duration (n=2 in FIG. 4). The hopping code on each channel then repeats over the fraction or multiple of the bit stream duration. While advantageous in reducing probability of detection, this is seen to expose the secure communication system to compromise if an adverse party should gain access to a transmitter or receiver. This results in an increase to probability of interception, because each transmitter and receiver has a hopping controller or a memory that has the hopping pattern stored within. Interrupting the hopping repetition is not seen to resolve this security risk, as all hopping patterns and codes are seen to be stored and subject to breach if the hardware is compromised.
What is needed in the art is a cost-effective way to enhance security in a DSS communication system without inordinately spending bandwidth.

Waveform design hopping system and method


A heat sink can include a folded fin with a base portion, an offset portion extending away from the base portion, the offset portion having a width, a narrowing tapering portion having a maximum width equal to the width of the offset portion, and an extension portion extending away from the narrowing tapering portion, the extension portion having a width smaller than the width of the offset portion.

Receivers for solar concentrators are the focus for light which has intensity greater than sunlight. Some concentrators produce an intensity equivalent to two or three multiples of the intensity of sunlight, while other concentrators can produce light forty or fifty times as intense as sunlight. The focused light can be directed toward a receiver, which can be a thermal conversion device, such as a working fluid conduit or a Stirling engine, a photovoltaic cell, or a combination of the thermal conversion device with a photovoltaic cell.
For applications which direct concentrated sunlight on a photovoltaic cell, some heat is produced by the focused light impinging on the cell. As the heat experienced by the photovoltaic cell increases, its conversion efficiency decreases. Accordingly, it is desirable to conduct heat away from the photovoltaic cell.
One technique for conducting heat away from the photovoltaic cell is to thermally couple the cell to a heat sink. The shape and composition of the heat sink can determine its effectiveness at conducting heat away from the photovoltaic cell and consequently affect the efficiency of the cell.