The present invention is an adhesive suitable for use in the production of engineered wood products, said adhesive comprised of an aromatic diisocyanate (99.0-10.0 parts by mass) and an aromatic petroleum distillate (1.0-90.0 parts by mass) with low volatility. The adhesive composition may result in improved coverage or distribution on the outer surface of raw materials, such as strands, particles, flakes, fibers, or veneer.

Wooden strand-based composite products, such as oriented strandboard (OSB), flakeboard, waferboard or TimberStrand, are commonly used in residential home construction. They can be formed from raw materials, such as wooden elements, such as strands and flakes. These wood products are generally manufactured in seven major stages, which may include stranding, screening, drying, blending, forming, pressing, and finishing.
Stranding is a process in which logs are cut into discrete wooden strands (also known as flakes) that typically have an aspect ratio between 1 and 20. The long axis of the strands is predominantly aligned within about 0-30° of the grain of the wood. The strand thickness can range from about 0.015″ to about 0.060″ and the length can range from about 1″ to about 15″, or even longer. In most cases, the strands are cut from round wood that has a moisture content of about 50-150%. Thus, the stranding process typically yields wet strands that must be dried prior to further processing.
Drying is usually accomplished by passing the wet strands through long rotating drums or pipes in conjunction with hot, dry air. Alternatively, strands can be dried by conveying them in a chamber with hot, dry air passing through or around the conveyance system. The drying process commonly results in strands that have a moisture content of about 1-7%. The resulting dried strands exist as a mixture of relatively large and small elements, and it is frequently desirable to screen the material in order to separate the strands on the basis of size. In many cases the smallest wooden particles, known as fines, are diverted from the product stream and are transported to a burner where they are used as fuel.
The acceptable wooden strands are then metered into large rotating drums, known as blenders, and are sprayed or otherwise mixed with bonding resin and wax. This stage is known as blending. Many blenders rotate at a rate of about 4-20 rpm and are tilted (3-8°) in order to promote material flow. A single blender can have about six or more liquid application devices distributed within it. Such application devices are frequently rotary disk atomizers, but they can also be simple spray guns. In some cases, one or two of the application devices are devoted to wax and the remaining application devices are devoted to resin. Powdered bonding resins can also be introduced into the blender. It is common for large strands and small strands to be blended separately. Strands that have been treated with bonding resin and wax are then formed into a mat. In the case of OSB and TimberStrand, treated strands are formed into a mat by dispensing them at some controlled rate through mechanical partitions that tend to align the strands in a particular orientation. As the strands pass through the alignment devices they are collected onto a continuous conveyor belt. In the case of waferboard, the strand alignment devices are not used, and the mat that collects on the conveyor belt has an essentially random orientation within the plane of the mat, which is parallel to the conveyor belt. Frequently, the strands incorporated into the top and bottom layers of an OSB mat are larger than the strands incorporated into the core (or middle) layer of the mat. In many cases the bonding resin formulas and resin application levels used in the surface layers of an OSB mat are different than those used in the core layer of the mat. In a commercial manufacturing process the mat is generally continuous in length and has a width of between about 4′ and 16′. The thickness of the mat can be in the range of about 2″ to 20″. In some cases, the continuous mat of treated strands is transported directly into a continuous hot-press, but in most cases, the mat is cut into discrete sections, which can have a length of about 8′ to 24′. These mat sections are loaded into a multi-opening hot press, which can usually press between 12 and 20 mats simultaneously. In the case of TimberStrand, the mat is loaded into a single-opening, steam-injection press.
During the process of pressing, strands are forced together and intimate contact is achieved at the strand-to-strand interfaces. Subsequent to this consolidation process, bond formation occurs as the resin undergoes curing reactions and is converted from a liquid to a load-bearing solid. The press then opens and the relatively large "jumbo" panels are ejected onto a conveyor and transported to the finishing stages of the operation. Finishing steps commonly include cutting the jumbo panels into smaller panels, such as those having dimensions of 4″×8″. Other finishing activities can include sanding, edge profiling, marking with grade stamps, grading for quality, stacking into units, sealing, labeling, strapping and packaging.
Other engineered wood-based composite products, such as medium density fiberboard (MDF), particleboard, plywood, and laminated veneer lumber, are manufactured in processes that are generally similar to that of the wooden strand-based composites.
Adhesives, or binder resins, which are commonly utilized in the blending step of the production process for wooden strand-based composites include polymeric diphenylmethane diisocyanate (pMDI), such as Huntsman's Rubinate 1840, liquid phenol/formaldehyde resole resins, such as Georgia-Pacific's 70CR66 resin; and powdered phenol/formaldehyde resole resins, such as Hexion's W3154N resin. Binders are typically applied to strands at a level of about 1-8%. In general, these adhesive types have worked well for this application, but manufacturers are constantly searching for resins that will facilitate improved distribution on the strands at minimal application rates. It is well known in the industry that binder distribution (i.e. the percentage of strand surface area covered with adhesive) can be improved by increasing the resin application rate. Indeed, increasing the resin application rate results in improved resin distribution and increased strand-to-strand bond strength. Unfortunately, high resin application rates also increase production costs and increase the rate of "build-up" or fouling of the interior surface of the blender. Conversely, decreasing the resin application rate reduces production costs and reduces the rate of "build-up" on the inside of the blender, but it also has a detrimental effect on resin distribution and strand-to-strand bond strength. When resin distribution is sufficiently poor, a significant portion of the strand population will be essentially free of adhesive on at least one major side. If two untreated strand surfaces are in direct contact in the finished board, then there will be essentially no internal bond strength at the interface between these strands. Products with many of these weak interfaces would be expected to perform poorly in a structural application. Among conventional resins, powdered phenol/formaldehyde resole resins tend to yield very good distribution at low application rates. Unfortunately, these resins are relatively expensive compared to liquid phenol/formaldehyde resins, they are "dusty", and the application level of the powder is limited to about 3% of the strand mass, which might be insufficient to achieve a desired level of performance in the board. Higher resin loading levels can be achieved by use of pMDI or liquid phenol/formaldehyde resole resin. The extent of distribution for liquid binders is partially related to resin droplet size, which generally decreases as the resin viscosity decreases. Therefore, there is some tendency for lower viscosity liquid binders to yield improved distribution in a given application system. It is also known that there is a tendency for pMDI to absorb into a wooden strand faster and to a greater extent than that of a liquid phenol/formaldehyde resole resin. Thus, pMDI tends to yield better distribution than a liquid phenol/formaldehyde resole resin, even when they both have the same viscosity and are applied at the same level.
Accordingly, a need exists for a resin composition that can be applied to strands in a conventional blender at a given application rate wherein the resin yields improved distribution relative to that achieved with a conventional liquid resin.

Adhesive having aromatic diisocyanates and aromatic petroleum distillates with low volatility for use in engineered wood products


A flat, ribbon-like headphone cable having a unitary cable section, a splitter, and two split cable sections for connection to earpieces. The unitary and split cable sections each have substantially flat cross-sections wherein the width is substantially greater than the thickness. The split cable sections are oriented such that their widths are substantially perpendicular to the width of the unitary cable section.

Ear-bud type headphones as are known in the art typically have thin cables that are prone to tangling. This tangling causes difficulty and delay for the user, who must untangle the headphone cable prior to actual use of the headphone, or else risk damage to the headphone cable due to knots or sharp folding of the cable. Even so, such damage may occur during the process of untangling the headphone cable, if such untangling is not performed in a careful manner.
A flat ribbon-like cable provides advantages in that its structure is inherently more rigid and therefore less prone to tangling. Moreover, the larger cross-sectional area of a flat cable facilitates passage of multiple conductors in a side-by-side configuration, as shown in FIG. 2. This provides benefits in terms of lower overall cable impedance and faster transient response as compared to conventional headphone cabling. Moreover, the flat cable can accommodate added functionality such as conductors for a microphone.
Headphone cables typically have a unitary section, in which the left and right channel conductors are combined in a single cable segment, and split left and right sections that connect to each of the left and right ear pieces. During usage of a flat headphone cable, it is desirable to orient the headphone cable so that its unitary cable section lays flat against the user's body. However, it is also desirable to orient the left and right split sections of the cable so that they lay flat against the user's face. This requires that the widths of the unitary cable section and the split cable sections be oriented in a substantially perpendicular relationship. Therefore, there is a need for a flat headphone cable incorporating a splitter that facilitates orientation of the widths of the unitary and split portions of the headphone cable in a substantially perpendicular relationship.


The present invention relates to a topical cosmetic composition that has improved non-oily feel comprising: (a) a hybrid silicone composite powder having a spherical shape with particle diameter ranging from 2 to 10 μm, of which each particle has a composite structures consisting of two interpenetrating polymer networks of polydimethylsiloxane (PMS) and polymethylsilsesquioxane (PMSQ). These two interpenetrating polymer networks are joined together by physical entanglements instead of chemical bonds; (b) a volatile cosmetic fluid; (c) a silicone fluid with viscosity ranging from 2 to 350 cSt; (d) an oil base consisting of an oil, wax, oil gelling agent or the mixture thereof; (e) a surface active agent; (f) a cosmetic pigment; and (g) an optional aqueous gel containing glycerin, glycols and an aqueous thickening agent. The cosmetic composition provides an improved skin sensory feel and a superior matte finish, and is useful for skin treatment, makeup and personal hygiene products.

Cosmetic and skin care formulations involve the use of oils from animals, natural plants and organic synthesis to build a carrier for active ingredients and to set up a barrier against environmental influences such as dirt, chemicals and microorganisms and against the loss of endogenous substances such as natural fats and water. The oils could often cause an unpleasant oily, greasy feel on the skin. Consequently, a skilled cosmetic formulator often chooses to add powders of, for example, nylon, polymethylmethacrylate, polyurethane, silica and polymethylsilsesquioxane into cosmetic formulations to reduce the undesirable skin feel. While these powders provide a reasonable skin sensory and oil control benefit, they suffer the disadvantage of high cost and low efficacy. Their sensory feel is not obvious when they are used in liquid formulations at a level of about 10% or lower. But if their concentration in the formula is too high these powders lead to an undesirable texture and appearance.
Recently, silicone elastomer powder has found increased use in cosmetic formulations because it imparts a very smooth feel and absorbs a large amount of oil at a relative low concentration, resulting in a matte appearance. The preparation and cosmetic applications of silicone elastomer have been disclosed in Japanese Pat. JP 1190757, issued to Toru et al.; U.S. Pat. No. 4,987,169, issued to Kuwata et al.; U.S. Pat. No. 5,266,321, issued to Shukuzaki et al.; U.S. Pat. No. 5,919,468, issued to Bara; and U.S. Pat. No. 6,524,598, issued to Sunkel et al. While the silicone elastomer has advanced the approach to battle the oily, greasy feel, it still suffers from an unsatisfactory performance. A wet, draggy feel is often observed in the initial application to the skin when a high viscosity silicone fluid or a vegetable oil is used in formulations.
It remains desirable to further improve the sensory feel of the delivery system for cosmetic applications. It would be especially desirable to have new systems carrying modified silicone powder to provide an improved dry-smooth feel.

Topical cosmetic composition containing hybrid silicone composite powder


A method for controlling engine vacuum production is disclosed. In one example, one or more air sources to an engine intake manifold are closed so as to increase an amount of air drawn from another air source. The method may increase a rate of vacuum supplied to a vacuum actuated device so as to improve operation of the vacuum actuated device.

Engine and vehicle actuators may be operated via vacuum or electrical energy. Electrical energy may be suitable for operating actuators that require a moderated amount of force; however, vacuum may be more suitable for operating actuators that may require higher levels of force such as vehicle brakes. Vacuum for operating actuators may be supplied via an engine intake manifold or a vacuum pump. An engine may provide vacuum via an intake manifold positioned in the engine air intake path between engine cylinders and an engine throttle. The pumping of engine cylinders may lower pressure in the intake manifold with respect to atmospheric pressure, thereby producing vacuum. However, engine air sources supplying air to the engine may affect the way vacuum is produced by the engine. For example, the engine throttle, engine crankcase ventilation system, EGR, and fuel vapor control system may affect the rate of vacuum production by the engine since the engine throttle and fuel vapor control system supply air to the intake manifold. In addition, the engine throttle and the fuel vapor control system may affect the level of vacuum produced by the engine. Further, choosing between liquid and gaseous fuels in a bi-fuel engine can also affect engine vacuum production. Consequently, if larger diameter hoses are used between vacuum system components to improve vacuum recovery rate of a vacuum system, the engine may not be able to provide vacuum at a desired rate and level.
The inventors herein have recognized the above-mentioned disadvantages and have developed an engine operating method, comprising: closing air sources to an engine intake manifold in response to a vacuum level, the air sources including a throttle; evacuating air from an air source supplying air to the engine intake manifold that is not closed; and opening at least one of the closed air sources in response to engine combustion stability degrading below a threshold level.
By restricting air flow or other gases flowing into the engine via closing gas sources capable of providing gas to the engine, the engine can be operated as a vacuum pump to quickly resupply a vacuum system with vacuum. In one example, a throttle supplying air to the engine may be closed in response to a brake booster vacuum level. The throttle may be at least partially reopened in response to a combustion stability level of the engine so that the possibility of engine emission degradation may be reduced during the vacuum recovery period.
The present description may provide several advantages. For example, the approach may reduce the possibility of engine stalls while increasing a rate of engine vacuum production. In addition, some cylinders of a multi-cylinder engine may be operated without fuel to produce vacuum while other cylinders operate with fuel to produce engine torque. Further, the engine may provide higher vacuum levels since the engine throttle can be closed during vacuum production. Further still, engine air sources can be opened in a predetermined order after being closed so as to prioritize operation of vacuum consumers.
The above advantages and other advantages, and features of the present description will be readily apparent from the following Detailed Description when taken alone or in connection with the accompanying drawings.
It should be understood that the summary above is provided to introduce in simplified form a selection of concepts that are further described in the detailed description. It is not meant to identify key or essential features of the claimed subject matter, the scope of which is defined uniquely by the claims that follow the detailed description. Furthermore, the claimed subject matter is not limited to implementations that solve any disadvantages noted above or in any part of this disclosure.

Method and system for controlling engine vacuum production


A system and method for testing standby current of a semiconductor package is provided. The method includes testing semiconductor chips formed on a wafer having a predetermined wafer run number, collecting measured values of standby current of the semiconductor chips, and storing the measured values of standby current in a database, by using a wafer tester; recognizing a wafer run number of each of semiconductor packages to be tested; downloading measured values of standby current of semiconductor chips corresponding to the recognized wafer run number from the database to a semiconductor package tester; extracting a boundary value defining predetermined upper values of the downloaded measured values of standby current, by using the semiconductor package tester; setting the boundary value as a standby current limit of a program for testing the semiconductor packages by use of the semiconductor package tester; and testing the semiconductor packages based on the standby current limit.

1. Field of the Invention
The present invention relates to a method for testing standby current of a semiconductor package, and more particularly, to a method of automatically setting a standby current limit for a package testing process based on values measured during an electrical die sort (EDS) of a wafer.
2. Description of the Related Art
To realize a particular function, a circuit is designed and a plurality of parameters are set to measure the characteristics of the circuit. The circuit is manifested as a semiconductor chip fabricated on a wafer. To check whether the semiconductor chip was fabricated as it was originally designed, the predetermined parameters are measured while the chips are on the wafer. Thereafter, the semiconductor chip is packaged. To determine whether the characteristics of the semiconductor chip have been changed during the packaging, the parameters are measured again in a package testing process.
Among those parameters, standby current is a parameter for checking the amount of leakage current dissipated in a standby mode not an operation mode. Standby current is usually leakage current of a transistor, e.g., a memory cell transistor of a semiconductor memory device. The main cause of an increase in the leakage current of a memory cell transistor is a decrease in a gate poly critical dimension or an active critical dimension. In addition, when a threshold voltage decreases according to the thickness of a gate insulating layer and cleaning conditions for a memory cell transistor, the leakage current of the memory cell transistor increases.
In this situation, when high-voltage stress is applied to a semiconductor package in a package testing process, in order to skip a burn-in process, the median (central) and statistical spread or dispersion (distribution) of the standby current may shift because of a vulnerable process management standard. Besides, the standby current may change due to various factors in wafer fabrication processes. Particularly, in a low-power semiconductor apparatus, the range of fluctuation in medians and statistical dispersions of the standby currents increase during wafer fabrication and package testing.
The change in the median value and distribution of standby current does not necessarily cause faults during fabrication or problems in product quality. However, since the test limit set for the standby current at an initial characteristic evaluation is fixed, yield loss occurs during the package testing process.
To prevent yield loss from occurring during package testing attributable to the change in the characteristics of standby current, a conventional method includes measuring the standby current of each semiconductor chip formed on a wafer when yield loss occurs or inspecting the result of wafer fabrication processes and the result of an EDS, statistically estimating the level of standby current, manually adjusting the test limit for the standby current in a package testing process, and repeating the above operations.
As described above, when standby-current yield loss occurs during package testing, a standby current limit must be adjusted manually. The manual adjustment takes a large amount of time and requires a lot of labor.

Method for testing standby current of semiconductor package


A system and method is provided for exchanging data between at least one merchant site and at least one partner site across an interconnected computer network. The at least one merchant site enables a user to conduct a transaction on the merchant site, and employs a merchant database format. The at least one partner site has a link to the at least one merchant site and/or a display of transactional information from the at least one merchant site, and employs a partner database format different than the merchant database format. The display of transactional information of the at least one partner site enables a user to conduct a transaction with the at least one merchant site on the at least one partner site. A clearinghouse site is also provided in communication with the at least one merchant site and the at least one partner site. The clearinghouse site has at least one translator to convert data compliant with the merchant database format into data compliant with the partner database format, and is also capable of sending such converted data to the at least one partner site. In addition, the clearinghouse site may have at least one further translator to convert data complaint with the partner database format into data compliant with the merchant database format, and may also be capable of sending such converted data to the at least one merchant site.

In recent years, businesses have been making increased efforts to sell products and services through computers linked by interconnected computer networks. Many of these businesses have utilized the largest network today, the Internet, for such sales efforts. As known in the art, the Internet is a combination of large computer networks joined together over a high-speed backbone and data links. The Internet provides access to information stored on individual sites managed by various providers. As the Internet grows in its complexity, a greater part of population becomes more familiar with the skills required to access and communicate using the Internet.
Therefore, it is not surprising that many businesses use the Internet, especially a subset of the Internet known as the World Wide Web (the "Web"), as a significant sales channel and commerce forum. Web servers typically employ the HyperText Transfer Protocol ("HTTP") to enable users to communicate over a number of hyperlinks that interconnect numerous web sites to each other. The web sites are usually created using the HyperText Markup Language ("HTML"), which is a set of "markup" symbols or codes inserted in a file intended for displaying on a web browser. The markup symbols typically direct the Web browser how to display a web page's words and images for the user. For more information on HTTP and HTML, see Internet Engineering Task Force ("IETF") Request For Comments ("RFC") 1945 and RFC 2616, and RFCs 1866 and 2854, respectively, all of which are specifically incorporated in their entirety herein by reference.
Its graphical environment makes the web ideal for supporting a wide variety of a "online marketing". A few years ago, "online marketing" meant ensuring a good placement with web search engines. As the search engines and placements proliferated, businesses using this type of the marketing technique became increasingly undifferentiated. To solve this problem and, further, to expand many businesses' reach across the web, the businesses have adopted a marketing technique commonly referred to as "affiliate marketing" for advertising their products and/or services without incurring fixed costs.
E-commerce companies, such as Amazon.com and CDNow.com, pioneered the affiliate marketing. These companies created a system in which web publishers ("affiliates") could build mini storefronts on their web sites and, thus, effectively push many merchant's brands to a broader base of potential customers. These storefronts have been typically developed in a form of promotions, such as banner ads, combining graphics and text into an appealing display of merchants' products. By placing the banner adds for products that are targeted to the kinds of people who traffic the affiliate web site, the merchants and the affiliates are able to conduct e-commerce "in context." Thus, the merchants may place banner ads for travel books on travel web sites, and parenting books on sites for new parents, for instance. Typically, merchants pay no initial fee for placing banner ads on affiliate sites but, instead, the merchant pays a "per-action" commission to the affiliate sites. The "actions" may be a click-through, a membership sign-up, an actual product purchase, or a fulfillment relationship.
Affiliate marketing is popular among many merchants because it is predictable, measurable and profitable. By pushing different customer promotions to different affiliates, the merchant may recognize how well each affiliate is performing. Further, such arrangement enables merchants to continually adjust their marketing, merchandising and a mixture of affiliates to optimize the merchants' overall performance.
Despite its attractiveness, the conventional affiliate marketing is perhaps the least efficient and effective way to develop high-performance based marketing that results in positive returns on investments. First of all, the conventional affiliate marketing is built on an implicit assumption that all affiliates are good partners for all merchants. Typically, the vast majority of a merchant's affiliate sales come from a relatively small number of affiliate sites associated with the merchant site. As more affiliate sites learn to effectively influence the affiliate marketing channel, this small number of revenue partners may grow. However, it will never reach the scale of the hundreds of thousands of good partner sites that traditional affiliate marketing providers seek to draw to their networks, and, in the long run, these networks are obstacles to an effective affiliate channel performance. To recruit real revenue partners, merchants must either analyze a vast pool of affiliates, or they must commit to paying the ongoing costs of servicing and supporting tens of thousands of affiliate sites, of which, only a few thousand may actually create value for the merchants.
Furthermore, as affiliate sites grow in complexity to display an increasing number of merchants' products and/or services, many affiliate sites resort to building proprietary databases both to keep track of such products and/or services and also to enable visitors to search these databases in order to locate advertised products. As a merchant changes its product line, pricing or availability, the affiliates' databases must be updated to reflect these changes so consumers continue to see current information on affiliate sites. Therefore, the affiliate sites need to receive and store the most current product (or service) data from a variety of merchants, each of which may make independent decision about how to store and transmit data internally.
Currently, if a merchant site wishes to send product data to its affiliate sites, the merchant has to convert the product data into formats that its affiliate sites are able to process. If the merchant site has hundreds of affiliate sites, this process becomes so time consuming that many merchant sites choose to leave it up to the affiliate sites to convert the product data format into their proprietary database formats. However, many of the affiliate sites do not have resources available to do this, which, in turn, leaves them with unreadable product data that can not be processed.
Additionally, as many of the affiliate sites generate sales on a merchant's behalf, transaction data must be reported back to the merchant site to fulfill the sales and to ensure that the affiliate site receives an appropriate commission for the sales from the merchant. Because a single affiliate site may represent multiple merchants, the affiliate site may be forced to go through lengthy conversion processes to report the transaction data back to each merchant so the transaction data is in each merchant's preferred database format.
The complexity of this problem grows as a number of interconnected merchants and affiliates increases. In an exemplary system including two affiliate sites representing two merchant sites, a total of eight data conversions must take place if each affiliate site and each merchant site employs a different database format. In such a system, each affiliate site must convert, for instance, transaction data to the database formats of the two merchant sites, and each merchant site must convert, for instance, product data to the database formats of the two affiliate sites. Thus, for a system with ten affiliates representing ten merchants, two hundred conversions would be necessary if each merchant site and each affiliate site employ unique database formats.
Furthermore, as networked commerce grows increasingly sophisticated, merchants and affiliates recognize a need to share new kinds of information in addition to basic product data. For instance, this information includes tracking purchases of individual users on the Internet, as well as informing customers of up-to-date product availability.
Therefore, a need exists for a method and system that solves all of the above inefficiencies of the existing methods and systems.

Method and system for exchanging data between affiliated sites


A substrate treatment method in accordance with an exemplary embodiment includes: heating a substrate, for a substrate treatment process, so that a temperature of the substrate reaches a target temperature; calculating the temperature of the substrate using a sensor located facing the substrate while heating the substrate; and controlling an operation of a heating part configured to heat the substrate according to the temperature calculated from the calculating the temperature, wherein the calculating the temperature comprises: measuring a total radiant energy (Et) radiated from the substrate using the sensor; calculating a corrected total emissivity (εt0) by applying a correction value for correcting the total emissivity (εt) which is the emissivity of the radiant energy (Et); and calculating the temperature (Ts) of the substrate using the total radiant energy (Et) and the corrected total emissivity (εt0).

The present disclosure relates to a substrate treatment method and a substrate treatment apparatus, and more particularly, to a substrate treatment method and a substrate treatment apparatus which are capable of improving reliability of temperature detection.
Apparatuses for performing various heat treatment processes include furnaces and a rapid thermal process (RTP) apparatuses. Among these, the rapid thermal process apparatus treats a substrate with high-temperature heat in a short time, can thereby achieve target effects, and therefore has a merit in that side effects of causing impurities during heat treatment process can be reduced to minimum.
The rapid thermal process apparatus includes: a chamber having a heat treatment space for a substrate; a substrate support which is positioned inside the chamber and on which a substrate to be treated is supported; a plurality of lamps which are positioned to face the substrate support and provide a heat source for heat treating the substrate; a window which is positioned between the plurality of lamps and the substrate support and transmits thermal energy generated from the plurality of lamps so that the thermal energy is transferred to the substrate; a base positioned under the substrate support and having, on the upper portion thereof, a reflective member that reflects light; and a temperature detection unit mounted on the base and provided with a pyrometer that detects the temperature of the substrate. The temperature detection unit includes a temperature control unit which calculates a temperature using data measured from the pyrometer.
The pyrometer detects or measures radiant light radiated from the substrate s, reflected light provided such that the radiant light radiated from the substrate s is reflected by a reflective member at least once, and reflected light which is emitted to the substrate s from a light source and is reflected by the substrate s. In addition, the temperature control unit uses the amounts of radiant light and reflected light, which are measured by the pyrometer, to convert the amounts into the radiant intensity and emissivity of light, and calculates a temperature using these.
Here, the temperature control unit calculates the temperature of the substrate by applying the radiant energy and emissivity to an equation expressing Planck's law about black body radiation. In addition, according to the calculated temperature of the substrate, whether to operate or the power of each of the plurality of lamps are adjusted to adjust the substrate to a target temperature.
Meanwhile, referring to FIG. 2, the moving path of the reflective light incident on the pyrometer includes a case (A) in which among the reflected light, light emitted from the pyrometer is reflected from the substrate and is directly incident on the pyrometer, and a case (B and C) in which radiant light radiated from the substrate is reflected from the reflective member at least once and is then incident on the pyrometer. Thus, in calculating the temperature by applying the emissivity in the temperature control unit, the total emissivity εt including the emissivity (hereinafter substrate emissivity) when light emitted from the pyrometer is reflected from the substrate and is directly incident on the pyrometer, and the emissivity enhanced when the radiant light emitted from the substrate is reflected from the reflective member at least once and is then incident on the pyrometer. The total emissivity εt varies according to the substrate emissivity.
When a substrate at room temperature is heated, the phenomenon in which the substrate is deflected downward occurs, and at this point, according to the degree of deflection of the substrate, the substrate emissivity value calculated from the temperature detection unit varies. That is, there is a tendency that the closer to the pyrometer the defection degree of the substrate, the lower the substrate emissivity. In particular, in the process of raising the temperature of a substrate at room temperature to the process temperature, the degree of variation in the substrate emissivity is great, and at this point, it is sometimes detected that the substrate emissivity εs instantaneously drops to "0", and when the substrate emissivity εs is "0", according to the equation for calculating the total emissivity εt, the total emissivity εt becomes "0". However, practically, there can be no object having the emissivity of "0". Thus, when the total emissivity εt
In addition, as described above, according to the decrease in the substrate emissivity εs, the total emissivity ET decreases. According to the conventional calculation equation, in the interval in which the substrate emissivity εs is no greater than approximately 0.5, more specifically, no greater than approximately 0.3, the degree of variation in the total emissivity ET according to the variation in the substrate emissivity εs is great. Describing this in other words, in the interval in which the substrate emissivity εs is no greater than approximately 0.5, more specifically, no greater than approximately 0.3, the sensitivity of the total emissivity ET is great.
This becomes a cause for increasing the temperature deviation between the calculated temperature and the actually measured value of temperature of the substrate when the substrate emissivity εs is calculated to fall within a low temperature range (no greater than approximately 0.5, more specifically, no greater than approximately 0.3).
Thus, since the error of the calculated temperature is great, upon controlling the plurality of lamps according to the temperature calculated from the temperature control unit, the temperature of the substrate is not easily controlled to a target temperature, and this causes degradation in product quality and causes a problem of unstable process. In particular, while raising the temperature of the substrate at room temperature to the process temperature, it is difficult to control the temperature of the substrate, and process stability cannot be secured.

Substrate treatment method and substrate treatment apparatus


A radio receiver includes a down-converter 110 for receiving a radio multiplexed signal containing a first signal and a second signal, multiplying the first signal and the second signal by a mixer 104 to thereby down-convert the radio multiplexed signal and generate an intermediate frequency signal 5e. The mixer 104 has a control section for controlling an operating bias of the mixer 104 in response to a signal strength of at least either one of the first signal or the second signal. Thus, the dynamic range of the mixer can be widened so that stable image characteristics can be obtained over a wide range of transmission distance.

The present invention relates to a radio receiver, for example, to a microwave band radio receiver for receiving signals derived from broadcast waves which have been radio-transmitted in the microwave band.
Generally, a radio receiver includes a mixer which generates an intermediate frequency signal (hereinafter, referred to as IF signal) from a received radio modulation signal (hereinafter, referred to as RF signal) and a local oscillation signal (hereinafter, referred to as LO signal) generated in the receiver.
As for electric power of an LO signal to be inputted to the mixer and operating bias of the mixer, appropriate values points are chosen so that successful IF signal can be obtained by demodulation in terms of conversion gain, noise characteristics, low distortion or the like. The electric power of the LO signal is constant and, generally, large enough as compared with the electric power of the RF signal. Accordingly, the operating bias current of the mixer has a value dependent on the power of the LO signal, and hardly not on the power of the received RF signal, thus being a generally constant value.
In recent years, there have been energetically developed radio receivers using frequency bands of 10 GHz or higher microwave and milli-wave bands, and such radio receiver and radio reception method as shown below have been proposed (see, e.g., JP 2003-258655 A).
FIG. 10 shows the construction and frequency arrangement of a proposed radio receiver 900. The radio receiver 900 receives a radio multiplexed signal 930 transmitted from transmitter with an antenna 901. This radio multiplexed signal is formed from combination of a first local oscillation signal 930c (frequency: fLO1) and a first radio modulation signal 930a. This first radio modulation signal 930a, in which a first local oscillation signal 930c and a first intermediate frequency signal 932a (IF1 signal, frequency: fIF1) are multiplied, has a frequency of fLO1+fIF1.
The received radio multiplexed signal 930 has its unwanted waves eliminated by a filter 902, and amplified by an amplifier 903. Then, with the use of a mixer 905, the amplified radio signal and a second local oscillation signal (frequency: fLO2) generated from a local oscillator 904 inside the receiver are multiplied and down-converted, by which a first-local-oscillation-signal component signal 931c (frequency: fLO1−fLO2) and a first-radio-modulation-signal component signal 931a (frequency: fLO1+fIF1−fLO2) are generated.
Next, the signals, after the amplification by an amplifier 906, are divided by a divider 907, one being amplified by an amplifier 910 via a filter 908 allowing only the first-local-oscillation-signal component signal 931c and then inputted to a mixer 911, and the other being inputted to the mixer 911 via a filter 909 that allows only the first-radio-modulation-signal component signal 931a to pass through.
In the mixer 911, the first-local-oscillation-signal component signal 931c and the first-radio-modulation-signal component signal 931a are multiplied and down-converted, by which the IF1 signal 932a is demodulated. This is expressed by the following equation:(fLO1+fIF1−fLO2)−(fLO1−fLO2)=fIF1
In this method, it is described that since frequency fluctuations and phase noise of the first local oscillation signal and the second local oscillation signal are canceled during the demodulation of the IF1 signal, there is no need for any high-performance oscillator so that the manufacturing cost can be reduced. Further, it is also described that since the first-local-oscillation-signal component signal 931c is amplified by the amplifier 910, a signal of sufficiently high level as an LO power can be fed to the mixer 911, so that the demodulation sensitivity can be enhanced.
However, with the above-described radio system, the LO power to be inputted to the mixer changes in proportion to the received power of the radio multiplexed signal 930. The LO power is small when the received power is small, while conversely the LO power is large when the received power is large. Therefore, with the use of a conventional mixer, the operating bias current of the mixer would largely change due to the received power of the radio multiplexed signal 930. As a result, in the case of transmission of digital terrestrial broadcasting or BS/CS television broadcasting waves, when the transmission distance is shortened so that the received power is enlarged, there would be some cases where the operating state of the mixer (operating bias) is changed, causing the reception C/N (carrier to noise ratio) to deteriorate or the mixer to be broken due to occurrence of a large current.
Moreover, when the operating bias of the mixer is so set as to prevent occurrence of the such troubles as described above even with a large received power, it would occur that the mixer does not operate when the received power is small, resulting in a small output of the mixer. In this case, the reception C/N could not be ensured and the transmission distance could not be elongated.
Consequently, with such a radio system, the dynamic range of the mixer would be narrowed so that stable reception C/N characteristics or image characteristics could not be obtained over a wide range of transmission distance in the radio system.


An imaging device includes a solid-state imaging device configured to include a plurality of pixels, the solid-state imaging device outputting subject data according to a pixel signal output by the pixel of an image region on which subject light is incident and optical black (OB) data according to the pixel signal output by the pixel of a constantly shielded OB region of a plurality of columns or rows located on an end of the image region as image data, and an imaging processing unit configured to output pre-processed image data obtained by performing black level correction on partial subject data included in the image data using the same OB data included in the image data output by the solid-state imaging device.

Field of the Invention
The present invention relates to an imaging device. Priority is claimed on Japanese Patent Application No. 2013-186472, filed Sep. 9, 2013, the content of which is incorporated herein by reference.
Description of Related Art
Recently, the number of pixels of a solid-state imaging device in an imaging device such as a digital camera has increased year by year according to an increase in resolution of images to be captured. In general, the solid-state imaging device performs raster scanning and sequentially outputs signals (hereinafter referred to as "pixel signals") of pixels in a horizontal direction (lateral direction) for an image. Because of this, in the image processing device provided in the imaging device and configured to process an image output by the solid-state imaging device, a storage capacity of the line memory for temporarily storing pixel signals of the horizontal direction output by the solid-state imaging device in a number of rows necessary for image processing also increases. An increase in the storage capacity of the line memory in the image processing device is a factor which increases a circuit scale of the imaging device.
For example, as in the publication of Japanese Patent No. 4179701, technology of the image processing device for performing image processing on one image through a plurality of separate operations is disclosed. In the technology disclosed in the publication of Japanese Patent No. 4179701, a pixel signal output from the solid-state imaging device is temporarily stored in a frame memory provided outside the image processing device and then one image is generated through a plurality of image processing operations while pixel signals necessary for the processing are read from the frame memory. For example, in the technology disclosed in the publication of Japanese Patent No. 4179701, as shown in FIG. 14A, the entire region of one image is divided into two regions, image processing is performed on one (left) half region in first image processing, and image processing is performed on the other (right) half region in the second image processing.
In the technology disclosed in the publication of Japanese Patent No. 4179701, one image is divided into a plurality of blocks and image processing is performed through operations equal in number to the division blocks, so that one image can be generated in the storage capacity of the line memory which is less than the number of pixels of the horizontal direction in which the solid-state imaging device performs an output operation.
In a pixel unit of a solid-state imaging device provided in an imaging device, there is an optical black region (hereinafter referred to as an "OB region") of a plurality of columns or rows arranged on an end of an image region and constantly shielded. In photographing in the imaging device, image processing (hereinafter referred to as "black level correction") for correcting a change in a black level represented by a pixel signal output by each pixel within the image region is performed based on a signal (hereinafter referred to as an "OB pixel signal") of a pixel of the OB region. In general, in the pixel unit of the solid-state imaging device, the OB region includes a sub OB region of a horizontal direction (hereinafter referred to as an "HOB region") and a sub OB region of a vertical direction (hereinafter referred to as a "VOB region"). The HOB region refers to a sub region in which a pixel located on either of the left and right of the image region and configured to output an OB pixel signal to be used for the black level correction of the horizontal direction of the image is arranged. The VOB region refers to a sub region in which in which a pixel located on either end of the top and bottom of the image region and configured to output an OB pixel signal to be used for the black level correction of the vertical direction (longitudinal direction) of the image is arranged. In FIG. 14B, an example of an image including an OB pixel signal output by a solid-state imaging device in which the HOB region is arranged on the left end of the image region and the VOB region is arranged on the upper end of the image region is shown.
The case in which the technology disclosed in the publication of Japanese Patent No. 4179701 is applied to the image and black level correction is performed by dividing the entire region of one image into two regions is considered. In this case, as shown in FIG. 14B, the HOB region is included in a left half region on which the black level correction is performed through a first operation, but no HOB region is included in a right half region on which the black level correction is performed in a second operation.
In addition, as disclosed in the publication of Japanese Unexamined Patent Application, First Publication No. 2009-094675, a solid-state imaging device with two HOB regions that are a HOB region corresponding to the image region of the left half and another HOB region corresponding to the image region of the right half is also implemented. In the solid-state imaging device of a configuration disclosed in the publication of Japanese Unexamined Patent Application, First Publication No. 2009-094675, it is possible to perform black level correction on each of the left and right regions even when the entire region of one image is divided into two regions.


According to one embodiment, an antenna device includes a first antenna, a second antenna, a third antenna, a capacitor element, a high-frequency cable, and a base member. The first antenna includes a folded-type monopole element. The second antenna includes a monopole element. The third antenna includes a passive element. The capacitor element is between a feeding point and a stub in a backward-path portion of the first antenna. The high-frequency cable is connected to the feeding point. The base member is formed of a dielectric material and has first, second, and third surfaces located to extend in different directions. The first, second, and third antenna are located at the first, second, and third surfaces.

In recent years, portable electronic devices such as smart phones, personal digital assistant (PDAs), tablet terminals and notebook personal computers have been required to have a lighter, thinner and smaller housing in order to decrease their sizes and weights. Accordingly, antenna devices for the portable electronic devices have also been required to be made more compact. Also, in recent years, the portable electronic device have been required capable of performing communication in a wider frequency band, in order that they can each communicate with a plurality of wireless systems having different frequency bands.
In view of the above, antenna devices have been proposed in which in addition to a folded-type monopole element, a second monopole element and a passive element are added in order to widen a resonant band. Also, antenna devices have been proposed in which a capacitor element is provided close to a feeding point of a folded-type monopole element provided with a stub in order to widen an operation frequency band.

This patent is subject to a terminal disclaimer.


One embodiment of the present invention provides a system which facilitates selective prefetching based on resource availability. During operation, the system executes instructions in a processor. While executing the instructions, the system monitors the availability of one or more system resources and dynamically adjusts an availability indicator for each system resource based on the current availability of the system resource. Upon encountering a prefetch instruction which involves the system resource, the system checks the availability indicator. If the availability indicator indicates that the system resource is not sufficiently available, the system terminates the execution of the prefetch instruction, whereby terminating execution prevents prefetch instructions from overwhelming the system resource.

1. Field of the Invention
The present invention relates to techniques for improving computer system performance. More specifically, the present invention relates to a method and apparatus for selectively prefetching based on resource availability.
2. Related Art
Hardware prefetching ("automatic prefetching") and software prefetching ("explicit prefetching") are two well known techniques for enhancing the performance of the caches in computer systems (where "caches" include hardware structures such as data caches, instruction caches and Translation Lookaside Buffers (TLBs)).
In a computer system that uses hardware prefetching, system hardware monitors runtime data access patterns and uses the access patterns to make predictions about future loads and stores. Based on these predictions, the system hardware issues automatic prefetch requests in anticipation of accesses.
In a computer system that uses software prefetching, software applications are tuned by inserting explicit prefetch instructions into the executable code in order to minimize the number of cache misses by subsequent load and store operations. These prefetch instructions can be placed so that they complement the automatic (hardware) prefetch behavior of the processor on which the software is executing.
Using these two techniques should result in significant performance improvement. In practice, however, the techniques have several limitations which significantly reduce the expected performance improvement. In fact, these limitations are so significant that they have impeded the widespread adoption of these techniques.
One such limitation is "processor implementation sensitivity," which occurs because the use of prefetches is highly dependent on the implementation details of the processor on which a software application is running. For example, the sizes of the caches, the number of ways in each cache, the load-to-use latency of a main memory access, and the clock frequency of the processor are processor implementation details that can affect the use of prefetches.
Processor implementation sensitivity is apparent in many commercially available software applications. Because software designers typically deliver only a single executable binary which is designed to be executed on a variety of different processors from the same processor family, the prefetch requests are not optimized for each possible processor implementation. The suppliers (1) choose the most popular variant within the processor family and optimize for that variant, or (2) deliver a binary that is suboptimal for any particular processor variant, but maximizes the average performance gain across the whole family.
A second limitation is "workload insensitivity," which occurs in computer systems where more than one virtual or physical processor is sending prefetch requests to a shared cache. For a single application (or a single execution thread), aggressive prefetching can produce considerable performance gains—because the cache is dedicated to the single application. Unfortunately, in a multi-application system, two or more executables time-share a processor and that processor's caches. In this case, aggressive prefetching by one application can displace the data in the shared cache that another application is actively using. In fact, multiple executables, each performing self-interested prefetching, can cause so much interference in the cache that the resulting performance is significantly worse than if each executable was run sequentially—a phenomenon known as "thrashing in the cache."
A third limitation is "shared resource insensitivity," which occurs because modern processors contain multiple processor cores which share system resources in a complex arrangement. Caches are one example of a system resource that is particularly vulnerable to shared resource complications. Because of the technical difficulties involved with one processor assessing the cache footprints taken up by the other processor cores, each processor core may operate without knowing how much space is available in the cache. Therefore, the processor cores typically restrict the use of aggressive prefetching or risk overloading and thrashing in the cache.
Although cache performance is affected by shared resource insensitivity, caches are not the only system resource affected by this condition. The processor cores also share other resources, such as the system bus. Aggressive speculative prefetching may load these system resources with counterproductive or unnecessary work, hampering the efficient operation of the computer system.
A fourth limitation is "competitive prefetching interference," which occurs in systems that combine hardware and software prefetching. In pathological cases, hardware and software prefetching can actually interfere with each other. Competitive prefetching interference occurs when the software issues prefetch requests which hardware has already issued, or when the false miss rate of the hardware and software prefetching combined exceeds the threshold at which actively used cache lines begin to be evicted, thereby causing cache thrashing.
Hence, what is needed is a method and apparatus which allows prefetching to be used aggressively without causing system-level performance degradation.

Method and apparatus for selectively prefetching based on resource availability


A lower arm assembly comprises a lower arm, a front fluid-filled bushing, a rear fluid-filled bushing, and a fluid transferring pipe extending between the bushings. Each of the front and rear bushings has an outer pipe, an inner pipe, and a shock absorbing member. A fluid chamber is formed within the shock absorbing member. The fluid transferring pipe connects the fluid chambers of the front and rear bushings together such that the fluid can transfer between the fluid chambers. Therefore, with the lower arm assembly according to the embodiment of the present invention, riding comfort and cornering stability can be simultaneously improved.

A suspension system of a vehicle is a device for absorbing shocks transmitted from a road. The suspension system typically includes, for each wheel, a knuckle that receives the wheel with the knuckle being supported from below by a lower trailing arm and from above by a shock absorber cooperating with a coil spring.
The lower arm is coupled to the sub frame of the vehicle through front and rear bushings. When the vehicle is running in a straight line, shape of the front bushing and the rear bushing are oppositely distorted. That is, when a shock is transferred to a vehicle body in a rearward direction, as shown in FIG. 3A, the front bushing is outwardly distorted and the rear bushing is inwardly distorted. To improve riding comfort, distortions of the front and rear bushings must be maximnized.
When the vehicle is cornering, lateral force is transmitted to the lower arm, so that in the case of cornering to the right the front and rear bushings are inwardly distorted at the same time. Under these conditions, for a cornering stability, distortions of the rear and front bushings must be minimized. However, the conventional lower arm cannot satisfy the opposite requirements for straight line and cornering operation at the same time.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.


A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.

1. Technical Field
Various implementations relate to a nonvolatile memory device, and more particularly, to a variable resistance memory device and a method of manufacturing the same.
2. Related Art
In recent years, with demands on semiconductor devices with high performance and low power, next generation semiconductor memory devices with non-volatility and no refresh have been researched. As one of the next-generation semiconductor memory devices, variable resistance memory devices have been suggested. Such and there are phase-change random access memory devices (PCRAMs), resistive RAMs (ReRAMs), magnetic RAMs (MRAMs), spin-transfer torque magnetoresistive RAMs (STTMRAMs), and polymer RAMs (PoRAMs) as the variable resistance memory devices.
The variable resistance memory devices perform a memory operation to have a set state or a reset state by controlling a phase-change material, which constitutes a data storage unit, to a crystalline state or an amorphous state.
Here, since more current is required in switching to the reset state of the variable resistance memory device than in switching to the set state, the current for switching to the reset state, that is, a reset current has to be lowered to obtain a high degree of integration.
In recent years, variable resistance memory devices having a confined structure are suggested to obtain a high degree of integration. There is a need for improving reliability of the variable resistance memory devices by improving stability of a process in a method of fabricating the variable resistance memory devices having the confined structure.

Variable resistance memory device and method of manufacturing the same


A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer.

1. Field of the Invention
The present invention generally relates to package substrates and methods for fabricating the same, and more specifically, to a package substrate with a wire bonding metal layer formed on wire bonding pads and a method for fabricating the same.
2. Description of Related Art
Owing to the flourishing development of the electronics industry, the research and development of electronic products have a trend toward multi-function, high-performance products. To satisfy the packaging requirements of high integration and miniaturization for semiconductor packages, package substrates for carrying semiconductor chips have been evolving from single-layer into multi-layer boards. Therefore, given a limited space, circuit area available to a package substrate is expandable by interlayer connection technology in order to cope with the application demands for high-density integrated circuits.
At present, package substrates for carrying semiconductor chips include wire bond package substrates, chip scale package (CSP) substrates, flip chip ball grid array (FCBGA) substrates, and others. To meet the operational requirements for microprocessors, chipsets, and graphic chips, improvements have to be made in delivery of chip signals, bandwidth, impedance control, etc. of circuit-laden circuit boards with a view to answering to the development trends of high I/O number packages. However, to fit in with the developing trend of semiconductor package towards light weight, small size, multi functions, high speed, and high frequency, circuit boards for packaging semiconductor chips have been trending towards fine lines and small apertures; size of circuit lines of circuit board, including line width, spaces between lines, aspect ratio, etc., has been reduced from the traditional 100 μm to below 25 μm presently, and the development trend is continuously towards smaller lines with great precision.
Please refer to FIGS. 1A and 1B, which are cross-sectional views of a fabrication method of a known package substrate that has wire bonding metal layer formed on its wire bonding pads; wherein as shown in FIG. 1A, provide first a substrate body 10, and then form a plurality of wire bonding pads 101 on at least a surface of the substrate body 10, and the wire bonding pads 101 have plating lines 102, also form an insulating passivation layer 11 on the substrate body 10 and the wire bonding pads 101, and then form a plurality of apertures of insulating passivation layer 110 in the insulating passivation layer 11 to correspondingly expose each of the wire bonding pads 101 and part surface of the substrate body 10; as shown in FIG. 1B, form a wire bonding metal layer 12 of, e.g. nickel/gold (Ni/Au), on the wire bonding pads 101 by using the plating lines 102 as an electrical conduction path.
However, the wire bonding metal layer 12 is formed on the wire bonding pads 101 by means of electroplating via the plating lines 102; and since the plating lines 102 must be laid on the substrate body 10, a great deal of area of the substrate body 10 is taken, thereby being unable to reach objectives of high density wiring and fine spacing between wire bonding pads.
Please refer to FIGS. 2A and 2B, which are cross-sectional views of another fabrication method of a known package substrate that has wire bonding metal layer formed on its wire bonding pads; as shown in FIG. 2A, provide a substrate body 20, and form a plurality of wire bonding pads 201 on at least one surface of the substrate body 20, and then form an insulating passivation layer 21 on the substrate body 20 and the wire bonding pads 201, and subsequently form a plurality of apertures of insulating passivation layer 210 in the insulating passivation layer 21 to correspondingly expose each of the wire bonding pads 201 and part surface of the substrate body 20; next, as shown in FIG. 2B, form a wire bonding metal layer 22 on the wire bonding pads by means of chemical deposition.
As stated above, chemical deposition is applicable to forming wire bonding metal layer 22 on the wire bonding pads 201, however, a sufficient thickness of wire bonding metal layer 22 costs highly, also wire bonding metal layer 22 formed by means of chemical deposition has softer texture and has poor bonding capability with wire of subsequent wire bonding process, thereby being disadvantageous to application demands of high number of pins.
Please refer to FIGS. 3A through 3H, which are cross-sectional views illustrating a fabrication method of wire bonding metal layer formed on wire bonding pads by means of non plating lines (NPL) electroplating; wherein a substrate body 30 with a plurality of wire bonding pads 301 thereon is provided, and as shown in FIG. 3B, form an electroconductive layer 32 on the wire bonding pad 301 and part surface of the substrate body 30; as shown in FIG. 3C, form a first photoresist layer 33a on the electroconductive layer 32, and also form a plurality of first openings 330a in the first photoresist layer 33a to correspondingly expose the electroconductive layer 32 on area of each of the wire bonding pads 301; as shown in FIG. 3D, remove the electroconductive layer 32 inside the first openings 330a; as shown in FIG. 3E, form a second photoresist layer 33b on the first photoresist layer 33a and inside the first openings 330a, and then form a plurality of second openings 330b in the second photoresist layer 33b to expose each of the wire bonding pads 301 but cover the electroconductive layer 32 not covered by the first photoresist layer 33a inside the first openings 330a; since the electroconductive layer 32 is electrically connecting to the wire bonding pads 301, as shown in FIG. 3F, a wire bonding metal layer 34 is formed on the wire bonding pads 301 inside the second openings 330b by electroplating via the electroconductive layer 32; as shown in FIG. 3G, remove the second photoresist layer 33b, the first photoresist layer 33a, and the electroconductive layer 32 covered thereunder to expose the wire bonding pads 301 and the wire bonding metal layer 34 there above; and as shown in FIG. 3H, form an insulating passivation layer 35 on the substrate body 30 and the wire bonding metal layer 34, and then form a plurality of apertures of insulating passivation layer 350 to expose the wire bonding metal layer 34 on the wire bonding pads 301.
According to the abovementioned NPL method, sufficient thickness of wire bonding metal layer 34 can be obtained by electroplating and has cost lower than by chemical deposition, and the wire bonding metal layer 34 formed by electroplating has firmer texture, thereby having better bonding capability with wire of subsequent wire bonding process. However, the fabrication method is complicated and the cost is still high. Besides, the insulating passivation layer 35, which is formed after the wire bonding metal layer 34 has been formed, causes contamination to the wire bonding metal layer 34 readily, thereby resulting in unstable quality of the subsequent wire bonding.
Hence, it is a highly urgent issue in the industry for how to provide a package substrate that has wire bonding metal layer formed on its wire bonding pads and a method for fabricating the same, which are capable of providing high density wiring and fine spacing between wire bonding pads as well as enhancing bonding capability and being advantageous to application demands of high number of pins.

Package substrate and method for fabricating the same

Phoenix Precision Technology Corporation


A method for fabricating a light-emitting device is provided. The method includes: providing a substrate; forming a sacrificial dielectric layer on the substrate, wherein the sacrificial dielectric layer is a structure containing voids; forming a buffer layer on the sacrificial dielectric layer; forming an epitaxial light-emitting structure on the buffer layer; forming a metal bonding layer on the epitaxial light-emitting structure; bonding the metal bonding layer to a thermally conductive substrate; and wet etching the sacrificial dielectric layer for to remove the substrate.

Field of the Invention
The invention relates in general to a method for fabricating a light-emitting diode (LED) device, and more particularly to a method for the fabricating LED device, wherein the sacrificial dielectric layer is wet etched to remove a substrate.
Description of the Related Art
Light-emitting diode (LED) has a P/N junction and emits a light when a voltage is applied to the P/N junction. LED elements can be widely used in various fields, such as indicators, sign boards, illumination, and other illuminating elements. Due to the advantages of small sizes, long lifespan, low power consumption, and high luminosity, LED has gradually replaced conventional lamps and become a most important light-emitting element.
In general, the LED device may include a substrate, a buffer layer formed on the substrate, and an epitaxial light-emitting structure formed on the buffer layer. When emitting a light, the LED generates heat, and the light-emitting performance of the LED will deteriorate if the heat cannot be dissipated. The use of a thermally conductive substrate helps to dissipate the heat generated by the LED device. Some commonly used LED substrates, such as a sapphire substrate, despite being excellent epitaxy growth substrates, have low heat transfer coefficients and cannot produce satisfactory thermal transfer effects. A commonly used method for resolving the above problem includes: removing the substrate by a laser lift-off process; and then bonding a part of the LED removed from the substrate to a thermally conductive substrate. A vertical type GaN LED device is taken for example. Firstly, an undoped GaN layer is grown on a sapphire substrate. Next, an n-type GaN layer, a multiple quantum well, a p-type GaN layer, and a metal layer are sequentially formed on the undoped GaN layer, wherein the position of the n-type GaN layer and the position of the p-type GaN layer are exchangeable. Then, the sapphire substrate is removed by laser lift-off technology, and the above-mentioned structure having the undoped GaN layer, the n-type GaN layer, the multiple quantum well, the p-type GaN layer, and the metal layer is bonded to a metal substrate such as a copper substrate via a metal layer. Thus, the LED device has a thermally conductive metal substrate. However, the method for fabricating a LED device by using a laser lift-off process results in a poor yield, and the yield is even worse for large-size substrates (such as ≧3″). Therefore, a substrate removal process which produces better yields than the conventional laser lift-off process does is needed to replace the conventional laser lift-off process.

Light-emitting semiconductor structure and method for fabricating light-emitting diode device


The present invention relates to a thin film transistor array panel, a liquid crystal display, and a method capable of reducing an effect on neighboring pixels in a process of repairing a pixel defect. The thin film transistor array panel may include: a thin film transistor connected to a gate line and a data line to define a pixel area; a pixel electrode formed in the pixel area and connected to the thin film transistor; and a storage electrode including a first portion overlapping the data line between two adjacent gate lines. The storage electrode may also include a second portion connected to the first portion and enclosing an edge of the pixel area except for a region where the first portion is formed. The storage electrode may be branched between pixel electrodes respectively formed in two adjacent pixel areas.

1. Field of the Invention
Exemplary embodiments of the present invention relate to a thin film transistor array panel, a liquid crystal display, and a repairing method capable of reducing an influence generated between adjacent pixels in a process of repairing deteriorations.
2. Discussion of the Background
A liquid crystal display (LCD) is a widely-used flat panel display that includes two electrode-containing substrates and a liquid crystal layer interposed therebetween. By applying a signal to the electrodes, the amount of light transmitted by rearranging liquid crystal molecules of the liquid crystal layer can be controlled.
At least one of the substrates may include a thin film transistor (TFT) array panel used as a circuit board to independently drive each pixel in the liquid crystal display or an organic light emitting device.
The TFT array panel may include a gate line transmitting a gate signal; a data line transmitting a data signal and intersecting the gate line; a thin film transistor connected to the gate line and the data line; and a pixel electrode connected to the thin film transistor.
When signal lines of the liquid crystal display are disconnected or shorted, a corresponding pixel may need to be repaired. After being repaired, however, the repaired pixel and a pixel neighboring the repaired pixel may have a higher or lower luminance than that of a normal pixel.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Thin film transistor array panel, liquid crystal display, and method to repair the same


A method for forming at least one quantum dot at at least one predetermined location on a substrate is disclosed. In one aspect, the method comprises providing a layer of semiconductor material on an insulating layer on the substrate. The layer of semiconductor material is patterned so as to provide at least one line of semiconductor material having a width (wL) and having a local width variation at at least one predetermined location where the at least one quantum dot has to be formed. The local width variation has an amplitude (A) of between about 20 nm and 35 nm higher than the width wL of the at least one line. The at least one line is patterned to form at least one quantum dot. A design for a lithographic mask for use with the method and a method for making such a design are also disclosed.

1. Field of the Invention
The present invention relates to quantum dots. More particularly, the present invention relates to a method for forming at least one quantum dot at a predetermined location on a substrate, to a design for a lithographic mask for use with this method according to embodiments of the invention and to a method for making such a design as well as to semiconductor devices made with the at least one quantum dot.
2. Description of the Related Technology
Quantum dots are semiconductor nanostructures that confine the motion of conduction band electrons, valence band holes, or excitons (bound pairs of conduction band electrons and valence band holes) in all three spatial directions. Confinement can be due to electrostatic potentials (generated by external electrodes, doping, strain, impurities), the presence of an interface between different semiconductor materials (e.g. in core-shell nano-crystal systems), the presence of the semiconductor surface (e.g. semiconductor nano-crystal), or a combination of these.
Quantum dots have a discrete quantized energy spectrum. The corresponding wave functions are spatially localized within the quantum dot, but extend over many periods of the crystal lattice. Quantum dots contain a small finite number in the order of about 1-100 of elementary electric charges, i.e. a finite number of conduction band electrons, valence band holes, or excitons. The usefulness of quantum dots comes from their peak emission frequency's extreme sensitivity to both the dot's size and composition. This remarkable sensitivity is quantum mechanical in nature. Quantum dots offer the unnatural ability to tune the bandgap and hence the emission wavelength.
Electrons in quantum dots have a range of energies. The concepts of energy levels, bandgap, conduction band and valence band which apply to bulk semiconductors also apply to quantum dots. However, there is a major difference. Excitons have an average physical separation between the electron and hole, referred to as the exciton Bohr radius. This is a physical distance which is different for each material. The dimensions of semiconductor crystals are much larger in bulk semiconductors than the exciton Bohr radius, allowing the exciton to extend to its natural limit. When the size (diameter) of a semiconductor crystal becomes small enough that it approaches the size of the material's exciton Bohr radius, then the electron energy levels can no longer be treated as continuous. In this case, the electron energy levels must be treated as discrete. This means that there is a small and finite separation between energy levels. This situation of discrete energy levels is called quantum confinement. Under these conditions, the semiconductor material ceases to resemble bulk and instead is called a quantum dot. This has large repercussions on the absorptive and emissive behavior of the semiconductor material and thus on the applications quantum dots can be used for. With quantum dots, the size of the bandgap of the material may be controlled simply by adjusting the size of the dot. Because the emission frequency of a dot is dependent on the bandgap, it is therefore possible to control the output wavelength of a dot with extreme precision.
Although quantum dots have many promising applications, such as their use in lasers, single electron transistors or others, it is not always easy to control the size of quantum dots and/or their precise location on the substrate. Up till now, quantum dots are formed by using electron beam (e-beam) lithography techniques. These lithography techniques use a focused beam of electrons to expose a resist. In these techniques no mask is used as the pattern is "written" directly into the resist by very fast scanning of the electron beam. With this technique a pattern transfer resolution of below 100 nm may be obtained. However, the resolution is limited by the proximity effect, i.e. by scattering of electrons in the irradiated resist. This proximity effect may be responsible for the size of the exposed resist area being larger than the diameter of the incident electron beam which thus limits the resolution of e-beam lithography. This may be a disadvantage when using e-beam lithography for forming quantum dots as the size of the quantum dot determines its properties. Another disadvantage of using e-beam lithography for making quantum dots is that it is not suitable for being used for mass production of devices comprising quantum dots because of this proximity effect.


An electrical connector for a flat conductive member include a housing; a first terminal including a first fixing arm portion, a first movable arm portion, and a first connecting portion; a second terminal including a second fixing arm portion, a second movable arm portion, and a second connecting portion; and a pressing member for pressing a first pressure receiving portion and a second pressure receiving portion so that the first pressing portion and the second pressing portion press the flat conductive member. The pressing member includes a cam portion having a small radius cam portion and a large radius cam portion. The small radius cam portion contacts with the first pressure receiving portion when the pressing member is situated at the open position. The large radius cam portion presses the first pressure receiving portion and the second pressure receiving portion when the pressing member is situated at the closed position.

The present invention relates to an electrical connector for a flat conductor.
A Flexible Printed Circuit (FPC), a flat cable, and the likes are known as flat conductors. A connector disclosed in Patent Reference is known as an electrical connector that connects the flat conductor to a connection object member, for example, other circuit board.
Patent Reference: Japanese Patent Publication No. 11-031561
FIG. 6 is a perspective sectional view showing a conventional electrical connector. FIG. 7 is a partial perspective sectional view showing the conventional electrical connector.
In the connector disclosed in Patent Reference, as shown in FIGS. 6 and 7, a plurality of the terminals 51 is held in a housing 52 in a direction perpendicular to a plate surface thereof. The terminal 51 is made to maintain a plate surface of a metal sheet.
The terminal 51 has an approximate transverse H-shape. Further, each upper arm and lower arm of the terminal 51 is connected at a middle portion thereof in a longitudinal direction thereof. The upper arm elastically inclines and is displaceable as a lever with a connection portion thereof as a fulcrum. The upper arm is provided with a supporting arm 54A on a right side of a fulcrum portion 53.
Further, the upper arm is provided with a contact arm 54B having a contact portion 54C with a protrusion shape on a left side thereof. The lower arm is provided with a supporting arm 55A having a connection portion 55B on a distal end thereof on a right side of the fulcrum portion 53. Further, the lower arm is provided with a fixed arm 55D having a protrusion portion 55C on a left side.
The housing 52 is provided with grooves 56 corresponding to the terminals 51, so that the terminals 51 are inserted into the grooves 56. The terminals 51 can be inserted from a right side in FIG. 6. All of the grooves 56 communicate at a left opening 57 of the housing 52. Further, the grooves 56 communicate at a right opening 58 of the housing 52. A flat conductor is inserted between the contact arms 54B and the fixed arms 55D from the left opening 57. Further, the right opening portion 58 is provided with a pressing member 59 to be freely rotatable.
The pressing member 59 is made of an electrical insulation material similar to that of the housing 52. As shown in FIGS. 6 and 7, the pressing member 59 has an operation portion 59A, a rotation guided portion 59B, a pressing portion 59C that functions as a cam, and a shaft portion 59D.
The operation portion 59A protrudes from the right opening 58 of the housing 52 to be in a lever shape. The rotation guided portion 59B has a section having a circular arc shape and is rotated to guide in a recessed portion. The recessed portion is provided to correspond to the supporting arm 55A of the lower arm of the terminal 51. When the pressing member 59 is rotated to be at a close position in a clockwise direction in the operation portion 59A, the pressing portion 59C presses the supporting arm 54A of the upper arm of the terminal 51 upwardly.
The shaft portion 59D is provided to protrude from both ends of a width direction of the pressing member 59. The shaft portion 59D has a pivot on an extension of a centerline of the circular arc of the rotation guided portion 59B. The shaft portion 59D is supported to be movable and guided along with the rotation guided portion 59B when the pressing member 59 is rotated.
A taper groove portion 61 and a step groove portion 62 are provided inside of a sidewall 60 of the housing. The taper groove portion 61 and the step groove portion 62 are adjacent to each other. Further, a slit 64 is provided in each border portion of the sidewalls 60 and a top wall 63 of the housing. The slit 64 enables the sidewall 60 to elastically bend outwardly. The pressing member 59 is incorporated into the housing 52 from a right side in FIG. 6 and from an upper right side in FIG. 7.
At that time, the shaft portion 59D elastically deforms to bend the sidewall 60 outwardly to be accommodated in the step groove portion 62 while moving the taper groove portion 61 of the sidewall 60. When the shaft portion 59D is accommodated in the step groove portion 62, the elastic deformation to bend is released. Accordingly, the shaft portion 59D engages with the step groove portion 62 and becomes hard to disengage upon receiving an external force.
As described above, in the connector disclosed in Patent Reference, the shaft portion provided on both side edges of the pressing member engages with the step groove portion of the housing in an arrangement direction of the terminals, so that the pressing member does not come off.
When the number of the terminals increases, a width dimension between both side edges of the pressing member increases and becomes easier to bend. In a range between the both side edges, the recessed portion provided in the supporting arm of the terminal prevents the pressing member from coming off to some extent.
However, when the pressing member is bent as described above due to an external force, the rotation guided portion of the pressing member easily protrudes from the recessed portion. Accordingly, solely the shaft portion has to be depended on to prevent the pressing member from coming off. As a result, the shaft portion may be overloaded; an engagement depth with the step groove portion of the shaft portion may become small due to the bend described above; or the sidewall may open due to a large force from the shaft portion, thereby further decreasing the engagement depth.
When one of the situations described above occurs, the shaft portion may break or the pressing member may come off. That is, when the pressing member is opened and closed, or when an inadvertent external force is applied to the pressing member, the pressing member may come off. Accordingly, the flat conductor can lose contact with the terminal; and therefore, a function as the connector can be lost.
In view of the problems described above, an object of the present invention is to provide an electrical connector for a flat conductor, in which it is possible surely prevent a pressing member from coming off without enlarging a size of the electrical connector. Another object of the present invention is to provide an electrical connector that prevents a pressing member from coming off even though the number of terminals increases.
Further objects and advantages of the invention will be apparent from the following description of the invention.


A pattern forming method comprising forming a coating of a radiation-sensitive resin composition, which contains an acid-dissociable group-containing polysiloxane, alkali-insoluble or scarcely alkali-soluble but becoming alkali-soluble when the acid-dissociable group dissociates, on a film containing a polymer with a carbon content of 80 wt % or more and a polystyrene-reduced weight average molecular weight of 500–100,000, an applying radiation to the coating is provided. The method can form minute patterns with a high aspect ratio by suitably selecting a specific etching gas in the dry etching process, without being affected by standing waves.

1. Field of the Invention
The present invention relates to a pattern forming method suitable for a lithography process and a bilayer film for forming patterns. The pattern forming method comprises a process of forming a coating, which comprises a radiation-sensitive resin composition containing an acid-dissociable group-containing polysiloxane, onto a film with a high carbon content and irradiating the coating with light such as deep ultraviolet rays, electron beams, and X-rays.
2. Description of the Background Art
A recent strong demand for high density and highly integrated LSIs accelerates miniaturization of wiring patterns.
Using short wave rays in a lithographic process is one method for miniaturizing wiring patterns. In recent years, deep ultraviolet rays typified by a KrF excimer laser (wavelength: 248 nm) or an ArF excimer laser (wavelength: 193 nm), electron beams, Xrays, and the like are being used in place of ultraviolet rays such as g-line (wavelength: 436 nm) and i-line (wavelength: 365 nm).
Novolac resins, poly(vinylphenol), and the like have been used as resin components for conventional resist compositions. However, since these resins exhibit strong absorbance at a wavelength of 193 nm due to inclusion of aromatic rings in the structure, a lithographic process by an ArF excimer laser using these resins cannot provide high accuracy corresponding to high photosensitivity, high resolution, and a high aspect ratio.
Therefore, a resin for use in a resist, transparent to a wavelength of 193 nm or less, particularly to a wavelength of 193 nm and 157 nm, and exhibiting excellent dry etching resistance equivalent to or better than aromatic rings has been desired. A polysiloxane is one such a polymer. R. R. Kunz et al. of the MIT have reported their research results showing excellent transparency of a polysiloxane at a wavelength of 193 nm or less, particularly at 157 nm, describing superiority of this polymer as a resist in a lithographic process using radiation with a wavelength of 193 nmor less (J. Photopolym. Sci. Technol., Vol. 12, No. 4, 1999). Moreover, polysiloxanes are known to exhibit excellent dry etching resistance. In particular, a resist containing polyorganosilsesquioxane having a ladder structure is known to possess high plasma resistance.
Several resist materials using a siloxane polymer have also been reported. For example, Japanese Patent Publication Laid-open No. 323611/1993 discloses a radiation-sensitive resin composition comprising a polysiloxane having an acid-dissociable group such as a carboxylic acid ester group, phenol ether group, etc., on the side chain, bonded to a silicon atom via one or more carbon atoms. Since this polysiloxane is a homopolymer, resolution cannot be increased if the acid-dissociable carboxylic acid ester group on the side chain does not efficiently dissociate. If a large number of acid-dissociable groups dissociate, on the other hand, the curing shrinkage stress of the resist film increases, causing cracks and peels in the resist film.
Japanese Patent Application Laid-open No. 160623/1996 discloses a positive tone resist using a polymer in which the carboxyl group of poly(2-carboxyethylsiloxane) is protected with an acid-dissociable group such as a t-butyl group. Since this resist protects the carboxyl groups only insufficiently, it is difficult to develop the resist containing a large amount of carboxylic acid components remaining in the non-exposed area using a common alkaline developing solution.
Japanese Patent Application Laid-open No. 60733/1999 discloses a resist resin composition containing a polyorganosilsesquioxane having an acid-dissociable ester group. This polyorganosilsesquioxane is prepared by the addition reaction of an acid-dissociable group-containing (meth)acryl monomer to a condensation product of vinyl trialkoxysilane, γ-methacryloxypropyltrialkoxysilane, or the like. The resin has a problem of insufficient transparency to light with a wavelength of 193 nm or less due to unsaturated groups remaining on the polymer side chains. The patent specification also describes a resist resin composition containing a polymer made by the esterification of polyhydroxycarbonylethylsilsesquioxane with t-butyl alcohol. This polymer also has the same problem as a resist as encountered by the polymer disclosed in Japanese Patent Application Laid-open No. 160623/1996 due to a low degree of carboxyl group protection.
In view of this situation, the inventors of the present invention have conducted extensive studies on resist materials containing a siloxane polymer exhibiting high transparency to light with a wavelength of 193 nm or less. However, the effect of standing waves that are considered to be caused by high transparency of this type of resists to light with a short wavelength cannot be ignored. The high transparency to short wavelength light was found to hinder formation of fine patterns.
One way of controlling the effect of standing waves is to provide an under layer film which can not only lessen the effect of standing waves, but also exhibits sufficient dry etching resistance.
To provide the under layer film with dry etching resistance, it is necessary to reduce the content of elements with high reactivity to the etching gas, such as a hydrogen atom and nitrogen atom, in the polymer composing the under layer film and to increase the content of carbon atom having relatively low reactivity to the etching gas. Conventionally, i-line resists made from a novolac resin have been mainly used for this purpose.
However, i-line resists do not necessarily possess satisfactory dry etching resistance. The resist is significantly eroded when the under layer film for silicon-type oxide films is processed. Reduction of film thickness has been unavoidable. For this reason, a thicker under layer film is used at present. However, since the pattern size is very small in the process with a minute silicon-type oxide film using a KrF excimer laser, an ArF excimer laser, or an F2 excimer laser (wavelength: 157 nm), this method of increasing the thickness of the under layer film inevitably increases the aspect ratio of patterns. As a result, the pattern is easily eroded from the sidewall by etching gas, dwindling away or collapsing. Precise pattern transfer is difficult.
An object of the present invention is to provide a pattern forming method capable of forming minute patterns without being affected by standing waves comprising the combined use of an under layer film with excellent dry etching resistance available as a thin film and a specific polysiloxane-type radiation-sensitive resin composition exhibiting high transparency to light with a wavelength of 193 nm or less, particularly, wavelength of 193 nm and 157 nm, and also capable of forming resist patterns with a high aspect ratio by suitably selecting a specific etching gas in the dry etching process, and also to provide a bilayer film.