An object is to obtain a step-up potential supply circuit which can supply a suitable step-up potential with suppressed power consumption even with a power-supply potential varying in a relatively large range. A 2Vcc charge pump circuit (1) is always kept in an active state. A power-supply potential detecting circuit (4) detects a power-supply potential Vcc. When the power-supply potential Vcc is under a first comparison potential, a switching signal SS at "L" is outputted to turn on a switch portion (3). Then a 2Vcc charge pump circuit (2) enters an active state and a step-up potential Vpp is supplied with a relatively large first charge supply capability. When the power-supply potential Vcc is above the first comparison potential, the switching signal SS is outputted at "H" to turn off the switch portion (3). Then the 2Vcc charge pump circuit enters an inactive state and the step-up potential Vpp is supplied with a relatively small second charge supply capability.

1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a step-up potential supply circuit for use in a semiconductor storage device such as a dynamic random access memory.
2. Description of the Background Art
FIG. 13 is a block diagram showing the overall circuit structure of a conventional DRAM. As shown in this diagram, an address signal inputted from an external address pin P1 passes the address buffer 21 and is time-divided; the row address is inputted to the row decoder 22 and the column address to the column decoder 23. The row decoder 22 decodes the row address, according to which result the word driver 24 selectively activates a word line WL in the memory cell array 25. The memory array 25 includes DRAM memory cells arranged in a matrix, where each row is connected to a common word line WL and each column is connected to a common bit line BL.
The column decoder 23 decodes the column address, according to which result a bit line, or a column selecting line, is selected. Then, when reading, data in the memory cell connected to both of the selected word line and bit line is amplified in the sense amplifier 26 and then outputted from the output pin P0 through a preamplifier (not shown) and the output buffer 27.
FIG. 14 shows the structure of a memory cell of the DRAM in detail. A memory cell of the DRAM is formed of one NMOS transistor 215 and one capacitor 217. The NMOS transistor 215 has its gate connected to the word line WL, one of its source/drain connected to the bit line BL and the other connected to one electrode of the capacitor 217. The substrate potential of the semiconductor substrate in which this NMOS transistor 215 is formed is (when a p-type substrate is used) usually at a negative, back gate potential (Vbb). The other electrode of the capacitor is set at a cell-plate potential Vcp.
The operation of writing "H" data (a Vcc level) into the memory cell is explained referring to FIG. 15. A Vcc level is transferred to the bit line BL by the sense amplifier 26 (refer to FIG. 13). Then, the word line WL is caused to rise to write Vcc into the storage node SN of the capacitor.
FIG. 16 shows the conditions of the voltage applied to the NMOS transistor at this time. When the bit line BL (source) attains the Vcc level, a large back gate potential Vbs (Vbb-Vcc) is applied to it due to the substrate potential Vbb. Originally, the NMOS transistor 215 of the memory cell has a higher threshold (Vth) than usual peripheral NMOS transistors to reduce the sub-threshold leakage current and to improve the refresh characteristics.
Then, when the source potential on the bit line BL rises to the Vcc level and the back gate voltage Vbs increases, the threshold of the NMOS transistor 215 of the memory cell further increases. FIG. 17 is a graph showing the increase of the threshold of the transistor of the memory cell due to the substrate effect. As shown in this diagram, while the threshold of the NMOS transistor 215 is Vt1 with Vbs=Vbb, it becomes as high as Vt2 when the Vcc level is written into the capacitor 217.
The "H" level of the word line WL must strongly turn on the NMOS transistor 215 to certainly transfer the Vcc level to the memory cell. The "H" level of the word line therefore requires the level of Vcc+Vth plus operation margin .alpha.; (Vcc+Vth+.alpha.).
FIG. 18 shows the relation between the word line WL and the power-supply potential Vcc. Since the threshold of the memory cell does not fall in proportion to the Vcc level, that is, since it takes almost the same value, the potential on the word line WL is proportional to Vcc. Nowadays, a power-supply for the step-up potential Vpp is usually used to set the potential on the word line WL. FIG. 19 and FIG. 20 show examples of circuit structure of a word driver.
In FIG. 19, the NAND gate 33 receives the row address and outputs the decoded result (select with "L" and unselect with "H") to the word driver 24. The word driver 24 is formed of PMOS transistors 34 and 35 and an NMOS transistor 36. The sources of the PMOS transistors 34 and 35 receive the step-up potential Vpp, and the PMOS transistor 35 and the NMOS transistor 36 form a CMOS inverter. The output portion of this CMOS inverter is connected to the word line WL and to the gate of the PMOS transistor 34. The input portion of the CMOS inverter and the drain of the PMOS transistor 34 receive the output of the NAND gate 33.
With this structure, when the output of the NAND gate 33 is "L", the PMOS transistor 35 turns on and the NMOS transistor 36 turns off, and therefore the word line WL is provided with the step-up potential Vpp. On the other hand, when the output of the NAND gate 33 is "H", the PMOS transistor 35 turns off and the NMOS transistor 36 turns on, and then the word line WL is set at an "L" level (the ground level). Furthermore, the PMOS transistor 34 turns on and the step-up potential Vpp is applied to the input portion of the CMOS inverter, and then the PMOS transistor 35 certainly turns off.
In FIG. 20, the inverter 37 receives the output from the NAND gate 33 and the output of the inverter 37 (the "H" level is the step-up potential Vpp) is applied to the gate of the NMOS transistor 39 through the NMOS transistor 38. The NMOS transistors 39 and 40 are connected in series between the signal RX and the ground level, the signal RX supplying the step-up potential Vpp.
With this structure, when the output of the NAND gate 33 is "L", the output of the inverter 37 is "H" (the step-up potential Vpp), and then the NMOS transistor 39 turns on and the NMOS transistor 40 turns off. Then, the word line WL is provided with the step-up potential Vpp. On the other hand, when the NAND gate 33 is "H", the NMOS transistor 39 turns off and the NMOS transistor 40 turns on, and then the word line WL is set at the "L" level (the ground level).
FIG. 21 is a circuit diagram showing the basic principle of a conventional Vpp generating circuit. The precharge circuit 41 (shown as a power-supply and a diode in FIG. 21) precharges the node NA to the Vcc level. The pump capacitor 42 is connected to the node NA, one electrode of which is thus charged. After the precharging, the oscillator 44 applies an oscillation signal (amplitude of GND and Vcc) to the other electrode of the capacitor 42. Then, the node NA is stepped up from the Vcc level to the doubled Vcc level, which potential is transferred to the step-up potential node Npp. FIG. 21 shows the diode 43 as a switch element for passing the potential to the step-up potential node Npp.
FIG. 22 shows an example of a charge pump circuit. A pulse-like clock signal CLK is inputted. The signal CLK is applied to one electrode of the capacitor 65 and one electrode of the capacitor 66. The node NA on the other electrode side of the capacitor 67 is connected to the drain of the NMOS transistor 73 and the node NB on the other electrode side of the capacitor 65 is connected to the gate of the NMOS transistor 73. The NMOS transistor 69, having common drain and gate, is interposed between the power-supply potential Vcc and the node NA, and the NMOS transistor 71, having common drain and gate, is interposed between the power-supply potential Vcc and the node NB.
With this structure, before starting operation, the nodes NA and NB are precharged by the NMOS transistors 69 and 71 to the power-supply potential Vcc, or to a potential at a level lower than the power-supply potential Vcc by the threshold voltage. When starting operation, the clock signal CLK is inputted to the capacitors 65 and 67. Then, as the clock signal CLK rises from the ground level (0V) to the power-supply potential Vcc, the potentials at the nodes NA and NB rise from the power-supply potential Vcc level to the doubled, 2Vcc level because of the capacitive coupling of the capacitors 67 and 65. The potential at the 2Vcc level at the node NA is supplied to the step-up potential node Npp as the step-up potential Vpp through the NMOS transistor 73. However, supplied to the step-up potential node Npp is a potential lower than 2Vcc by the threshold voltage of the NMOS transistor 73, because the last driver of the charge pump circuit is the NMOS transistor 73.
Next, FIG. 23 shows a circuit using a triple-well structure. As shown in FIG. 23, a pulse-like clock signal CLK is inputted. The signal CLK is applied to one electrode of the capacitor 45 and to one electrode of the capacitor 46. The node NA on the other electrode side of the capacitor 45 is connected to the drain of the NMOS transistor 47 and the node NB on the other electrode side of the capacitor 46 is connected to the gate of the NMOS transistor 47.
As shown in the section in FIG. 24, since the drain of the NMOS transistor 47 is electrically connected to the P-well region 231, the island in which the NMOS transistor 47 is formed, a potential is transferred by the PN junction from the P-well region 231 to the N.sup.+ region 232, or the source of the NMOS transistor 47.
While it is hence possible to cause the step-up potential Vpp to be outputted from the step-up potential node Npp with operation similar to that of the charge pump circuit shown in FIG. 22, the step-up potential Vpp is lower than the doubled Vcc level by the PN junction voltage Vv. However, as the PN junction voltage Vv is lower than the threshold of the NMOS transistor, the charge pump circuit shown in FIG. 23 can generate the step-up potential Vpp at a higher level than the charge pump circuit shown in FIG. 22.
FIG. 25 is a circuit diagram showing an example of a charge pump circuit in detail. As shown in this diagram, the charge pump circuit is formed of capacitors 75 and 77, a level converting circuit 79, and an NMOS transistor 81.
The capacitor 75 is interposed between the node to which the clock signal CLK is inputted and the node NA. The level converting circuit 79 enlarges the amplitude of the clock signal CLK and outputs it to the capacitor 77. The capacitor 77 is interposed between the level converting circuit 79 and the node NB. The NMOS transistor 81 is interposed between the node NA and the step-up potential node Npp, the gate of the NMOS transistor 81 serving as the node NB.
This structure, that is, providing the gate of the NMOS transistor 81 with a potential level higher than the potential level (2Vcc level) inputted to the gate of the NMOS transistor 73 of FIG. 22 prevents the potential supplied from the node NA to the step-up potential node Npp from being lowered from 2Vcc by the threshold voltage of the NMOS transistor 81.
FIG. 26 is a circuit diagram showing the level converting circuit 79 of FIG. 25 in detail. The same parts as those in FIG. 25 are shown at the same reference characters and not fully described again.
Referring to FIG. 26, the level converting circuit 79 is formed of NMOS transistors 83, 85, PMOS transistors 87, 89 and an inverter 91. The PMOS transistor 87 and the NMOS transistor 83 are connected in series between the step-up potential Vpp and the ground level. The PMOS transistor 89 and the NMOS transistor 85 are connected in series between the step-up potential Vpp and the ground level. The clock signal CLK as an input signal IN is applied to the gate of the NMOS transistor 83. The clock signal CLK is inverted by the inverter 91 and inputted to the gate of the NMOS transistor 85. The PMOS transistor 89 has its gate connected to the drain of the NMOS transistor 83 and the PMOS transistor 87 has its gate connected to the drain of the NMOS transistor 85. An output signal OUT is outputted from the drain of the NMOS transistor 85 to the capacitor 77 of FIG. 25.
Referring to FIG. 25 and FIG. 26, operation of the charge pump circuit will be explained. When the clock signal CLK at the ground level is inputted to the level converting circuit 79, the level converting circuit 79 outputs the signal OUT on the ground level to the capacitor 77. Next, when the clock signal CLK goes from the ground potential GND level to the power-supply potential Vcc, the level converting circuit 79 outputs the signal OUT at the step-up potential Vpp level to the capacitor 77. That is to say, the capacitor 77 is provided with the step-up potential Vpp, and then the potential at the node NB becomes higher than 2Vcc because of the capacitive coupling. This allows the potential at the 2Vcc level at the node NA to be transferred to the step-up potential node Npp as the step-up potential Vpp without affected by the threshold voltage of the NMOS transistor 81. That is to say, the potential transferred to the step-up potential node Npp is not lowered from 2Vcc by the threshold voltage of the NMOS transistor 81.
FIG. 27 is a circuit diagram showing another example of a charge pump circuit in detail. Referring to FIG. 27, the charge pump circuit is formed of an inverter 93, diodes 95 and 97, NMOS transistors 99, 101, a PMOS transistor 103 and capacitors 105, 107 and 109.
The capacitor 107 is connected between the node to which the clock signal CLK is inputted and the node NC. The NMOS transistor 101 is connected between the node NC and the step-up potential node Npp, whose gate is connected to the node NB. The input node of the inverter 93 is connected to the input node for the clock signal CLK and its output node is connected to the gate of the PMOS transistor 103 and the gate of the NMOS transistor 99. The diode 95, the PMOS transistor 103 and the NMOS transistor 99 are connected in series between the power-supply potential Vcc and the ground level. The capacitor 105 is interposed between the input node for the clock signal CLK and the node NA. The capacitor 109 is interposed between the drain of the NMOS transistor 99 and the node NB. The diode 97 is interposed between the power-supply potential Vcc and the node NB.
FIG. 28 is a timing diagram for describing operation of the charge pump circuit of FIG. 27. Referring to FIG. 27 and FIG. 28, the operation of the charge pump circuit will be explained. The node NA is charged to the power-supply potential Vcc by the diode 95 as a precharge circuit. When the clock signal CLK goes from 0V to the power-supply potential Vcc, the capacitive coupling causes the potential at the node NA to become the 2Vcc level twice as large as the power-supply potential Vcc. On the other hand, a potential of 0V is applied to the gate of the PMOS transistor 103 and it turns on. Accordingly, the potential at the 2Vcc level is provided to the capacitor 109 from the node NA. The operation explained so far corresponds to the operation of enlarging the amplitude of the clock signal CLK from between the ground level (0V) and the power-supply potential Vcc to between the ground level (0V) and 2Vcc. Since the capacitor 109 is thus provided with a potential at the 2Vcc level, the potential at the node NB is stepped up from the power-supply potential Vcc level to the triple, 3Vcc level. Accordingly, the potential at the 2Vcc level at the node NC produced by the capacitor 107 is intactly transferred to the step-up potential node Npp by the NMOS transistor 101 receiving the 3Vcc potential at its gate without being decreased the threshold voltage of the NMOS transistor 101.
FIG. 29 shows an example of utilization of the Vpp power-supply. The step-up potential Vpp produced by the charge pump circuit explained above is used as an operation power-supply for circuits requiring the step-up potential Vpp, such as the word driver 24, the RX driver 18, etc. When the DRAM enters a running state, the step-up potential Vpp generated from the charge pump circuit is consumed and its potential decreases. When the step-up potential Vpp remains decreased, the potential on a word line WL in an active state will not rise sufficiently, or it will take long before attaining a desired potential, leading to deterioration of performance or malfunction of the DRAM.
If the charge pump circuit is always kept operating to maintain the step-up potential Vpp at a desired level, however, the power consumption increases. Then, the circuit shown in FIG. 30 is suggested. As shown in FIG. 30, a detecting circuit 19 is provided to detect whether the step-up potential Vpp is maintaining a certain level. When the step-up potential Vpp falls below the certain level, it provides a pump active signal OE at "L" to cause the ring oscillator 20 to operate. Then the charge pump circuit 28 generates the step-up potential Vpp at the step-up potential node Npp in response to the clock signal CLK from the ring oscillator 20. On the other hand, when the potential level at the step-up potential node Npp attains or exceeds the certain level, the detecting circuit 19 provides the pump active signal OE at "H" to stop the operation of the ring oscillator 20. The charge pump circuit 28 then stops generating the step-up potential Vpp to the step-up potential node Npp.
FIG. 31 and FIG. 32 are circuit diagrams showing examples of structure of the detecting circuit 19. In FIG. 31, an NMOS transistor 111 and a resistor 115 are connected in series between the step-up potential node Npp and the ground level and the power-supply potential Vcc is applied to the gate of the NMOS transistor 111. The NMOS transistor 111 has a channel length larger than usual to realize a threshold Vth similar to that of the transistor forming a memory cell (the NMOS transistor 215 in FIG. 13). The signal obtained from the node NO between the NMOS transistor 111 and the resistor 115 becomes the pump active signal OE.
Accordingly, in the circuit in FIG. 31, the pump active signal OE goes "H" when the step-up potential Vpp exceeds (Vcc+Vth) and goes "L" when it falls below it.
In FIG. 32, the detecting circuit 19 is formed of PMOS transistors 117, 119 and a resistor 121. The PMOS transistor 117, the PMOS transistor 119 and the resistor 121 are connected in series between the step-up potential node Npp and the ground level. The PMOS transistor 117 is diode-connected and the gate of the PMOS transistor 119 is provided with the power-supply potential Vcc. The threshold voltage of the PMOS transistors 117 and 119 is taken to be Vthp. The signal obtained from the node NO between the drain of the PMOS transistor 119 and the resistor 121 becomes the pump active signal OE.
Hence, in the circuit shown in FIG. 32, the pump active signal OE goes "H" when the step-up potential Vpp exceeds (Vcc+2Vthp) and goes "L" when it falls below it.
Thus, in the detecting circuits 19 having the structures shown in FIG. 31 and FIG. 32, when the charge is consumed from the step-up potential node Npp and the step-up potential Vpp drops, the transistor 111 (119) turns off and the pump active signal OE goes "L" to cause the charge pump circuit to operate to maintain the step-up potential Vpp above a set value.
Consider DRAM operation at a power-supply potential Vcc as low as 2V, or lower. When the step-up potential Vpp is generated by using the charge pump circuit having the structure described above, the capability (the maximum attainable level) of the charge pump circuit can, even if an ideal circuit, attain only the doubled power-supply potential Vcc. That is to say, the step-up potential Vpp has an inclination twice that of a change in the power-supply potential Vcc. However, the threshold (Vth) of the memory cells can not be lowered in proportion to Vcc, since the refresh characteristics must be maintained.
In FIG. 33, the line Ld shows a change of the power-supply potential Vcc. That is to say, the vertical axis in FIG. 33 shows the power-supply potential Vcc for the line Ld. The threshold voltage Vth of the NMOS transistor 215 (FIG. 2) of a memory cell can not be lowered at the same inclination as the power-supply potential Vcc. That is to say, the threshold voltage Vth has almost the same value irrespective of the power-supply potential Vcc. Accordingly, the minimum potential level required for the step-up potential Vpp has approximately the same inclination as the power-supply potential Vcc. The line Lc shows the minimum potential level required for the step-up potential Vpp.
In practice, the minimum potential level required for the step-up potential Vpp further includes, in addition to the value (Vcc+Vth), the operation margin m2 (hundreds of millivolts) and the control margin m1 (hundreds of millivolts) for controlling the detecting circuit 19 (FIG. 30). The line Lb shows the minimum potential level actually required for the step-up potential Vpp. The threshold voltage Vth of the NMOS transistor forming a memory cell can not be lowered at approximately the same inclination as the power-supply potential Vcc because it is necessary to maintain the refresh characteristics and the control margin m1 is required to prevent the charge pump circuit 28 (FIG. 30) from operating too frequently to increase the power consumption. In summary, the actually required minimum potential level for the step-up potential Vpp is (Vcc+Vth+m1+m2; the line Lb in FIG. 33).
The maximum step-up potential Vpp that a step-up potential generating circuit can generate rapidly decreases as the power-supply potential Vcc decreases. The line La in FIG. 33 shows the potential level of the maximum step-up potential Vpp that the step-up potential generating circuit can generate.
This rapid decrease is due to the fact that the maximum step-up potential Vpp that the step-up potential generating circuit can generate has an inclination twice that of the power-supply potential Vcc, since the maximum step-up potential Vpp that the step-up potential generating circuit can generate is at the 2Vcc level.
In FIG. 33, when the power-supply potential Vcc is Vb (about 3.3 V), that is, when the power-supply potential Vcc is relatively large, there is no problem because the maximum step-up potential Vpp (the line La) that the step-up potential generating circuit can generate sufficiently exceeds the actually required step-up potential Vpp (the line Lb).
A problem arises, however, when the power-supply potential Vcc is Va (about 1.5V) or lower, that is, when the power-supply potential Vcc is as small as 2V, or smaller. That is to say, when the power-supply potential Vcc is Va, the maximum step-up potential Vpp (the line La) that the step-up potential generating circuit can generate is almost equal to the actually required minimum step-up potential Vpp (the line Lb). When the power-supply potential Vcc is lower than Va, the maximum step-up potential Vpp that the step-up potential generating circuit can generate becomes smaller than the actually required minimum step-up potential Vpp. Thus there is the problem that the conventional step-up potential generating circuit can not supply the actually required step-up potential Vpp if the power-supply potential Vcc is small.
FIG. 34 is a circuit diagram showing a power-supply for supplying the step-up potential Vpp, which is used to explain another problem of the conventional DRAM. The same parts as those in FIG. 21 are shown at the same reference characters and not fully explained. The switch 49 in FIG. 34 corresponds to the diode 43 in FIG. 21.
Referring to FIG. 34, when the capacitance value of the negative side capacitor 48 is taken as Cv, the capacitor 48 accumulates a charge of (Cv.multidot.Vpp). In this sense, the step-up potential node Npp to which the capacitor 48 is connected can be regarded as a power-supply for supplying the step-up potential Vpp.
In one operating period (in one cycle), the power-supply Npp consumes a certain fixed amount of charge, that is, (Cv.multidot.Vpp). Hence, if the consumed charge is not compensated for in one cycle in the direction of the arrow `a` from the step-up potential generating circuit, the step-up potential Vpp may fall below the certain potential when the next cycle starts, which may lead to a malfunction.
When the capacitor (pump capacitor) 42 has a capacitance of Cp, the amount of charge which can be supplied from the step-up potential generating circuit is Cp.multidot.(2Vcc-Vpp). If the (2Vcc-Vpp) has a small value, that it, if the difference between the maximum step-up potential that the step-up potential generating circuit can generate and the minimum required potential for the step-up potential is small, it is necessary to set a large value for the capacitor (pump capacitor) 42. This causes the problem of an increase in chip size.
Since a charge pump circuit for the step-up potential Vpp having an attainable level of doubled Vcc is not sufficient when operating with a low power-supply potential, use of a pump circuit providing a value larger than the twice will be one of the solutions. Such a pump circuit structure is described in detail in Japanese Patent Laying-Open No. 7-46825. For the object of realizing a DRAM with a wide range of power-supply potential, generating a Vpp larger than the doubled Vcc works with a low power-supply potential Vcc. However, with a high Vcc, in addition to the fact that the level larger than the doubled Vcc is unnecessary, the large capacitance of the pump capacitor in the charge pump circuit will supply excessive charge to excessively raise the step-up potential Vpp, bringing about new problems like deterioration of reliability and increase in the power consumption.

Step-up potential supply circuit and semiconductor storage device


A lens barrel includes: an image pickup optical system including a plurality of lenses. The plurality of lenses includes an adjusting lens for a shift adjustment in a direction perpendicular to an optical axis of the image pickup optical system. The lens barrel further includes a lens frame holding the adjusting lens; and a housing holding the lens frame and including a wall portion. The lens frame comprises a plurality of protrusions coming contact with the wall portion and each of the plurality of protrusions has a protruding amount which differs from the other for correcting a tilt of an optical axis of the adjusting lens.

A camera equipped with a zoom lens has been commercially available. In the zoom lens, a plurality of lens groups are moved in the direction of an optical axis to change a focal length of the zoom lens by changing spaces of the plural lens groups.
Further, there is known a camera wherein its optical axis is bent by 90° by arranging a prism in an optical system of a zoom lens. The camera of this kind has a merit that a lens barrel does not protrude in the course of photographing.
A zoom lens is composed of many single lenses and lens groups. Therefore, when the zoom lens is incorporated in a lens barrel, the property of the zoom lens is adversely affected by errors in respective lenses and by assembly errors.
Under the aforesaid background, there are provided patent publications about lens barrels. For example, Unexamined Japanese Patent Application Publication (JP-A) No. 2007-271648 discloses a lens barrel including a zoom lens whose optical system includes an adjusting lens for shift-adjustment in the direction perpendicular to an optical axis of the optical system for correcting errors in respective lenses and assembly errors.
In JP-A No. 2007-271648, the adjusting lens is fixed on a lens frame, and the lens frame is held on a housing together with other lenses to be shiftable in the direction perpendicular to the optical axis. This lens barrel is composed of two housings, and one housing holds a front optical system of a zoom lens, and the other housing holds a rear optical system of the zoom lens. Then, the lens frame that holds the adjusting lens is arranged at a position where the two housings are connected.
Unitizing a lens barrel by constituting it with two housings improves efficiency in terms of assembly and repairing, but it increases errors when securing lens property.
Therefore, it is considered to arrange the entire optical system of the zoom lens in one housing, which reduces errors compared with employing a lens barrel constituting with two housings. However, there still remain errors in respective lenses and assembly errors even when employing a single housing, because a zoom lens is composed of many lenses. It also requires an adjusting lens for a shift-adjustment.
In the lens barrel, an inside of the housing is formed variously in terms of shapes and dimensions depending on a lens to be held. The housing is generally molded with resin. Therefore, the housing is formed to have a cross section in a substantially square shape and to have one surface extending in parallel with the optical axis being open. A metal mold for forming the inside of the housing is drawn out in the direction that the housing opens. In other words, the housing is formed to have a cross section in a U-shape obtained when cutting the housing in the direction perpendicular to the optical axis, and a metal mold that forms the inside of the housing is drawn out in the direction of the opening of this U-shape.
However, when the metal mold for forming the inside of the housing is drawn out in this way, a draft angle in a certain degree is needed. A lens frame that holds an adjusting lens is held on a wall portion provided inside the housing extending in the direction that is almost perpendicular to the optical axis. Thus, the wall portion has a draft angle because the wall portion is formed by drawing out of the metal mold in the same way as described above.
As a result, the lens frame that holds the adjusting lens is tilted by the draft angle of the wall portion, resulting in a problem that the adjusting lens is also tilted away from the optical axis, which adversely affects lens property.
The housing may be molded without a draft angle on the wall portion. However, when deformation and shrinking is caused after molding in this case because of characteristics of resin, a surface of the wall portion that holds the adjusting lens would be tilted in the opposite direction to the tilt of the draft angle, in some cases. As a result, there is also caused a problem in a tilt of the adjusting lens in the same way as in the above description.
Further, even in the case where the housing is molded without a draft angle of the wall portion, and the wall portion does not tilt after being molded, the lens barrel would not provide sufficient lens property in some cases, due to a balance with a lens frame that holds other lenses. In this case, it is sometimes possible to obtain better lens property by tilting the adjusting lens intentionally.
In the meantime, when the lens barrel is formed by two housings and a lens frame that holds an adjusting lens is arranged at a position where the two housing are connected as shown in JP-A No. 2007-271648, the wall portion that is in contact with the lens frame can be formed by drawing the mold in the optical axis direction. Therefore, a draft angle is not needed and the aforesaid problem is not caused. Therefore, JP-A No. 2007-271648 discloses neither problems nor an embodiment about correction of the tilt of the adjusting lens.


A cue point data structure is maintained independent of a recorded time-varying content file. Embodiments of the present invention enable cue point data structures to be defined and then saved and independently recalled for application to any recorded time-varying content file. An authoring tool includes an interface to enable an author to, once having defined one or more cue points for a first recorded time-varying content file, save data structure(s) defining such one or more cue points independent of the first recorded time-varying content file. The authoring tool may further include an interface that enables an author to recall previously-saved cue point data structures. In this manner, the author may save and reuse cue point data structures. Further, a plurality of cue points may be saved together as a cue point scenario. Additionally, the data structure may be in a non-proprietary format, such as an extensible mark-up language (XML) format.

Recorded time-varying content is an ever-increasingly popular form of content. Various types of recorded time-varying content are known, including as examples video (e.g., movies, films, etc., which may comprise audiovisual content), audio (e.g., music, songs, audio-books, etc.), animation (e.g., cartoons, video games, etc.), multimedia content, and other forms of recorded content whose output vary over time. During the playback of such recorded time-varying content, the output changes (e.g., the images being displayed in a video change during the playing of the video, the audio output during playing of a song changes over the course of the song, etc). Thus, recorded time-varying content, as used herein, generally refers to any type of content (e.g., video, audio, etc.) whose output varies over the time of the recording.
Such recorded time-varying content is often stored in electronic form (e.g., as an electronic file) to a computer-readable data storage medium, such as a hard disk, magnetic data storage, optical data storage, memory, etc., and may be accessed by a playback application (referred to as a player) to output (or "playback") the recorded time-varying content (e.g., output the video, audio, etc.). As an example, the content of recorded time-varying content files may be presented to users via a media player application executing on a processor-based device, such as a personal computer (PC), laptop computer, mobile telephone, portable media player devices (e.g., iPod, etc.). Various media player applications are well known for reading recorded time-varying content files (e.g., multimedia files) and presenting their content to a user, including as examples ADOBE SYSTEMS INCORPORATED'S FLASH PLAYER™ (e.g., ADOBE® FLASH PLAYER 9), MICROSOFT WINDOWS MEDIA PLAYER™ developed by Microsoft Corporation, QUICKTIME™ developed by Apple computer, and REAL PLAYER™ developed by Real Networks. Also, various file formats have been developed for recorded time-varying content (such as multimedia file formats), including as examples such well-known video compression formats as MPEG (Moving Picture Experts Group, including MPEG-1, MPEG-2, and/or MPEG-4, as examples), H.261. H.262, H.263, H.264, AVS, Bink, Dirac, Indeo, MJPEG, Real Network's RealVideo format, Theora, VC-1, VP6, VP7, WMV (Windows Media Video), and QUICKTIME'S MOV format; and including as examples such well-known audio compression formats as MPEG-1 Layer 3 (MP3), MPEG-1 Layer 2, AAC, HE-AAC, G.711, G.722, G.722.1, G.722.2, G.723, G.723.1, G.726, G.728, G.729, G.729.1, G.729a, AC3, Apple Lossless, ATRAC, FLAC, iLBC, Monkey's Audio, μ-law, Musepack, Nellymoser, Real Network's RealAudio format, SHN, Speex, Vorbis, Way Pack, WMA, and TAK. Further, in some instances, a recorded time-varying content file may be implemented using a media container format such as one of the well-known media container formats of 3GP, ASF, AVI (Audio Video Interleave), DMF, DPX, FLV, Matroska, MP4, MXF, NUT, Ogg, Ogg Media, QuickTime, RealMedia, VOB, AIFF, AU, and WAV.
Various authoring tools are known for use in aiding an author in creating, editing, and/or otherwise authoring recorded time-varying content. Such authoring tools typically comprise a computer-executable software program that comprises computer-executable instructions (or code) stored to a computer-readable medium, which when executed by a processor-based device ("computer") causes the computer to perform operations described herein for such authoring tools. For instance, the authoring tools often present a user interface to a display with which a user (e.g., "an author") can interact to author (e.g., create, edit, etc.) a recorded time-varying content file. Examples of such authoring tools known in the art include ADOBE FLASH™, ADOBE FLASH MEDIA ENCODER, ADOBE AFTER EFFECTS™, ADOBE AUDITION™, ADOBE PHOTOSHOP™, ADOBE PREMIERE™, ADOBE VISUAL COMMUNICATOR™, and MACROMEDIA DIRECTOR® MX 2004.
Certain authoring tools may aid an author in editing the actual content of a recorded time-varying content file, such as by cutting out portions of the content (e.g., removing frames of a video), rearranging frames in the content, generating portions of the content (e.g., recording video and/or audio, performing computer-generated animation, etc), and/or performing other editing of the content. In addition, certain authoring tools may aid an author in editing certain characteristics of the recorded time-varying content file, such as the file format in which the content is stored, the resolution of the content, the bit rate for encoding and/or playback of the content, the codec used for encoding the content to a particular type of recorded time-varying content file, etc. Other types of authoring operations may be supported by various authoring tools, as are well known in the art.
One popular type of authoring operation that many authoring tools support is the insertion of cue points into a recorded time-varying content file. In general, a cue point is a defined point or marker that can be employed to trigger some event, such as an event that may be external to the recorded time-varying content. Thus, cue points provide invisible markers within a recorded time-varying content file which may be used to trigger such events as synchronization (e.g., synchronizing graphics, subtitles, etc., relative to particular points within the recorded time-varying content), providing navigation options (e.g., marking designated "chapters" or other sections within the recorded time-varying content to enable easy jumping to those marked chapters or sections), and/or loading other content (e.g., loading other video files, etc). As one example, an author may insert a cue point at a point within a video file to trigger subtitle text to be presented to a display at that point of playback of the video. As another example, when authoring video for a television program, an author may insert a cue point within such video file to designate when the video is to break to commercial (e.g., to trigger loading of another video file that presents the commercial content). Thus, authoring tools allow an author to insert a cue point at any point along a recorded time-varying content's reference playback timeline and/or at any given frame of the recorded time-varying content.
As an example, video cue points are supported in ADOBE's FLASH Professional 8, where an author can use cue points in conjunction with the FLASH FLVPlayback component to coordinate the playback of a video clip with accompanying interactive content. For instance, an author can use FLASH Professional 8 to create a FLASH presentation that has video playing in one area of the screen, wherein the author can insert cue points within the video to tigger other actions such as presentation of descriptive text and/or graphics in other areas of the screen at designated points during the playback of the video. Thus, such use of cue points enables the author to create richer and/or more interactive content.
Cue points can be inserted directly into a FLASH Video (FLV) file, for example, using either the FLASH Video Encoder or the Video Import Wizard of FLASH Professional 8. An author can also add and remove cue points with ActionScript using the addCuePoint and removeCuePoint methods.
Cue points are implemented as some type of data structure that defines the cue point properties. For instance, generally each cue point has a name and time value that designates the respective point in time within the recorded time-varying, content (e.g., video) file at which the cue point occurs. The cue point reference time may be specified in hour:minute:second:millisecond format. In some instances, the cue point reference time may be designated based on a corresponding frame of the recorded time-varying content, rather than or in addition to the reference time at which such frame occurs within the recorded time-varying content. For instance, an author may, in some instances view a video frame-by-frame, and insert a cue point at the occurrence of a specific frame.
The cue point data structure may further comprise data indicating a corresponding "type" of the cue point. As discussed further herein, different types of cue points may be defined, such as navigation cue points, event cue points and ActionScript cue points.
Further, a cue point data structure may comprise parameter data that specifies an action to be triggered upon the cue point being encountered. As examples, the parameter data may specify the subtitle text that is to be presented upon the corresponding cue point being encountered, or the parameter data may specify the name of another file (e.g., another video or audio file) to be launched upon the corresponding cue point being encountered.
FIGS. 1A-1B show an exemplary system 10 of the prior art in which a user interface of an authoring application 12 is provided to enable a user to insert a cue point into a video. As shown in FIG. 1A, system 10 comprises a processor-based computer 11, such as a personal computer (PC), laptop computer, server computer, workstation computer, etc. In this example, an authoring tool (or "application") 12 is executing on such a computer 11 with which a user may interact to author recorded time-varying content, such as the exemplary video being output to a preview display 101. Authoring tool 12 comprises computer-executable software code stored to a computer-readable medium that is readable by a processor of computer 11 and, when executed by such processor, causes computer 11 to perform the various operations described further herein for such authoring tool 12. Examples of such, an authoring tool 12 known in the art include the ADOBE FLASH™, ADOBE FLASH MEDIA ENCODER, ADOBE AFTER EFFECTS™, ADOBE AUDITION™, ADOBE PHOTOSHOP™, ADOBE PREMIERE™, ADOBE VISUAL COMMUNICATOR™, and MACROMEDIA DIRECTOR® MX 2004 authoring applications. The exemplary interface shown as being provided by authoring tool 12 in FIGS. 1A-1B corresponds to that provided by the Flash Video Import Wizard in FLASH Professional 8, with which an author may interact to define cue points for a video as described further hereafter.
In me example of FIGS. 1A-1B, an author interacts with authoring tool 12 to perform authoring operations for a video, such as those operations mentioned above. In particular, in this illustrative example the author interacts with authoring tool 12 to insert a cue point in the video. The exemplary interface of authoring tool 12 provides a content preview display 101 which allows the author to view portions of the content. For instance, the author can "scrub" (or move) along the video's reference timeline 102 to view corresponding parts of the video content. The user may view the video frame-by-frame, in slow-motion playback, etc.
Additionally, certain characteristics of the video file may be defined by the author, such as by defining via input box 106 the quality (e.g., video data rate), video codec, audio codec, audio data rate, etc. Thus, these characteristics of the video file may be modified in addition to or instead of modifying the actual content (e.g., frames) of the video.
A cue point insertion interface 107 is also provided. In FLASH Professional 8, such cue point insertion interface 107 may be accessed by clicking the "Show Advanced Settings" from the Encoding panel of the Video Import Wizard. The author can then select the cue points tab to be presented the cue points interface 107, as shown. On the reference timeline 102, a playback, head indicator 105 is shown, which may be used to locate a specific frame in the video in which the author wants to embed a cue point. For greater precision, the author may select the playback head 105 and use the left and right arrow keys on a keyboard to locate specific points within the video's content. Thus, the video preview window 101 enables an author to visually identify points in the video at which to insert a cue point. The author can also use the elapsed time counter (as indicated by elapsed time indicators 103 and 104 that are located beneath the video preview window 101) to locate specific points in time at which to embed cue points.
When the playback head 105 is positioned on the desired frame, the author can activate (e.g., click with a mouse) the Add Cue Point button 108. FLASH then embeds a cue point on that frame of the video. As shown in FIG. 1B, responsive to the user activating the add cue point button 108, a new cue point 110 is identified in the cue point list 120. The new cue point 110 is defined by certain data, such as a name 111 (e.g., "New Cue Point" in this example), time 112 (e.g., 00:00:17.796 in this example), and type 113 (e.g., an event or navigation type of cue point).
Time 112 identifies the time during playback of the video (e.g., the time on the videos reference timeline 102) when the corresponding event will be triggered by the cue point 110. The types 113 of the cue point may be event or navigation, as examples. Event cue points may be used to trigger ActionScript methods when the cue point is reached. Event cue points enable the author to synchronize the video playback to other events within the FLASH presentation. Navigation cue points may be used for navigation and seeking, and can also trigger ActionScript methods when the cue point is reached. Embedding a navigation cue point may insert a keyframe at that point in the video clip.
In this example, a cue point marker 109 is displayed on the slider control (of reference timeline 102) at the point where the cue point 110 was embedded. The author can use the cue point marker 109 to adjust the placement of the cue point. That is, the author may adjust the placement of the cue point 110 within the video by dragging the corresponding cue point marker 109 to the desired point on timeline 102.
Additionally, the cue point data structure typically comprises parameter data that defines an action to be triggered. As examples, the parameter data may specify the subtitle text that is to be presented upon the corresponding cue point being encountered, or the parameter data may specify the name of another file (e.g., another video or audio file) to be launched upon the corresponding cue point being encountered. Thus, for cue point 110, the author may add one or more parameters into parameter interface 114 by activating insert parameter button 115. For any such parameter, the author may define a corresponding name (in name field 116) and value (in value field 117). For instance, a parameter named "End Subtitle" may be defined whose value specifies the text "The End" to be presented at a corresponding point near the end of the video at which cue point marker 109 may be placed. The parameters may be passed to the cue point event handler as members of the single parameter object.
Traditionally, the cue point data structure defining such information as the cue point's name, time, type, and parameters is embedded within an encoding of a recorded time-varying content file (e.g., video file) in a proprietary (e.g., binary) format. Because the cue point data structure is embedded in the encoded time-varying content file, reuse of a cue point data structure when authoring (e.g., editing) other time-varying content files has traditionally not been available. As a result, inefficiency arises in many instances because the author is required to re-define cue points for each recorded time-varying content file that is being authored on a case-by-case basis. Further, because the cue point data structure has traditionally been in a proprietary format, access to such cue point data structure (e.g., for editing it, etc.) has been limited to an authoring tool that is coded to recognize such proprietary format.
FIG. 2 shows a block diagram of an exemplary system 20 in which an authoring tool 12 may be used to embed a cue point at a desired point in a video, such as described above with FIGS. 1A-1B. In this example, suppose an author uses authoring tool 12 to edit a first recorded time-varying content file 22, including inserting cue points at one or more points in the recorded time-varying content file 22. The cue point data structure 201, including the cue point's name, time, type, and parameters 202, is embedded (in a proprietary format of authoring tool 12) within the encoded time-varying content file 22 that is created. Now, further suppose that the author uses authoring tool 12 to edit a second recorded time-varying content file 23, including inserting cue points at one or more points in the recorded, time-varying content file 23. The cue point data structure 203, including the cue point's name, time, type, and parameters 204, is embedded (in a proprietary format of authoring tool 12) within the encoded time-varying content file 23 that is created. The cue point data structures 201 that were previously defined for recorded time-varying content file 22 are not available for reuse in authoring recorded time-varying content file 23. For instance, when working with a given recorded time-varying content file, authoring tool 12 does not allow an author to recall previously-defined cue point data structures that may have been defined previously for a different recorded time-varying content file. Such lack of reusability leads to inefficiencies by author, as discussed further below.
Suppose, as an example, that an author uses authoring tool 12 to edit a first video 22, and the author interacts with authoring tool 12 in the manner discussed above with FIGS. 1A-1B to specify cue points at various points within the first video 22. Those cue points are defined by corresponding cue point data structures 201 that are embedded in the first video file 22. So, the user creates/edits video 22, inserts the cue points, and then encodes the video to a desired encoded file type, resulting, in encoded video 22. Once encoded, the cue point data structures 201 are not reusable in authoring other videos.
For example, suppose the author then desires a new version of the video. For instance, the first video file 22 may be too long, or its quality may be too poor, or it may be too big in size and/or uses up too much bandwidth to play back, etc. The author may create a new version of the video, such as video 23, to correct these problems. While the cue points 201 previously defined for the first video 22 may be again desired for the new video 23, such cue points are not reusable structures, and thus the author is required to again perform the actions discussed above with FIGS. 1A-1B to re-define the desired cue points for the new video 23, resulting in cue point data structures 203 that are embedded in such video 23.
As another example, in many cases recorded time-varying content is desired to follow a definite structure or format. For instance, television shows follow a designated structure in which they have an opening section, which is everything that plays before the opening credits, and there is typically a break to commercial right after the opening credits, then there will be a first segment of the show followed by another commercial break at some point (e.g., at approximately 15 minutes) into the show, followed by another segment of the show, etc. Thus, the cue points inserted for such a television show follow a similar pattern for each episode of the show, but may need to be adjusted slightly from one episode to the next (e.g., the exact cue point for breaking for commercial at the end of a first segment of the show may not be at an identical time point for every episode of a show). However, traditionally an author using authoring tool 12 is required to repeat the actions for defining/inserting the cue points for each episode of a show (e.g., for a first episode of a show 22, and a second episode of the show 23), as the cue points defined for a first episode are not reusable in authoring a second episode 23.
Accordingly, a desire exists for improved technique for managing cue point data structures.

System and method for maintaining cue point data structure independent of recorded time-varying content


An organic EL device having a red light emitting area and a green light emitting area is provided. Each of the red light emitting area and the green light emitting area has a structure such that a first electrode having a light transmitting characteristic and an organic layer formed on the first electrode are stacked, and a second electrode having a light reflecting characteristic is disposed on the organic layers of the red and green light emitting areas. Reflectance of green light by the second electrode in the red light emitting area is smaller than reflectance of green light in the second electrode of the green light emitting area. Reflectance of red light by the second electrode of the red light emitting area is larger than reflectance of red light by the second electrode of the green light emitting area.

1. Field
Embodiments relate to an organic electroluminescence (hereinafter, referred to as EL) device.
2. Description of the Related Art
An organic EL device receives attention as a light emitting device. The organic EL device is a self-emissive device in which an organic layer including a light emitting layer, disposed between an anode electrode and a cathode electrode, emits light when holes and electrons, generated when voltages are supplied to the anode and cathode electrodes, are combined.
In the organic EL element, a technique is proposed which makes a characteristic of each of R, G and B pixels become uniform when an image is displayed using pixels emitting red (R), green (G) and blue (B), e.g., in which a thickness of an organic layer of a red pixel increases, thus increasing the fabrication cost and the driving voltage.


A system, method and computer program product for utilizing a person's voting status as a factor in segmenting a population, and in various aspects of selling, underwriting, or rating insurance. Voting status may include voter registration, eligibility for voter registration, an instance of recent voting, voting frequency, or other voting history in elections. In defining voting status, an instance of recent voting, voting frequency, or other voting history may optionally take into account the type of election or the turnout for the election, or both. Voting status may be used together with other factors such as age, gender, driving distance to place of employment, or residence location. A risk model for insurance purposes is provided, including segmentation of a population into groups based factors including voting status; and determining risk parameters of each group. A rate structure corresponding to the segmented groups may be calculated, and insurance coverage limits and a premium proposed to a customer based on a group assignment. Persons to receive insurance sales solicitations may be identified based on voting status.

Actuaries develop risk models by segmenting large populations of policies into predictable risk groups, each with its own risk characteristics. Actuarial pricing methods often use predictive variables derived from various internal insurance company and external data sources to compute expected loss and loss ratio at the individual policy level.
The traditional method used by actuaries to construct risk models involves first segmenting the overall population of policyholders into a collection of risk groups based on a set of factors, such as age, gender, driving distance to place of employment, etc. The risk parameters of each group are then estimated from historical policy and claims data. Actuaries may employ a combination of intuition and trial-and-error hypothesis testing to identify suitable factors.
However, some partly automated approaches use a predictive modeling class library to discover risk characterization rules by analyzing large sets of insurance data. The values of particular risk factors that apply to a particular individual or business are given weight in such analyses based on predictive modeling. Risk groups and their associated risk characteristics can be expressed in the form of actuarial rules, each rule defining a distinct risk group and its level of risk, such as: male drivers under age 25 who drive sports cars have a claim frequency of 25% and an average claim amount of $3200. To be able to discover such rules from historical claims and policy data, predictive modeling based on rule induction can be utilized.
Examples of external data sources for such data include the C.L.U.E. database of historical homeowners' claims; the MVR (Motor Vehicle Records) database of historical motor claims and various databases of both personal and commercial financial stability (or "credit") information.
As described above, using predictive modeling, key variables that one must try to predict are claim frequency and claim severity, and thereby pure premium. Approaches to predictive modeling are described in C. Apte, et al., "Research Report: Insurance Risk Modeling Using Data Mining Technology," IBM Research Division (31 Mar. 1998); U.S. Pat. No. 4,975,840 issued Dec. 4, 1990, to DeTore et al.; and U.S. Patent Publication 20060136273, Jun. 22, 2006, each of which is incorporated herein by reference in its entirety. Apte, et al., note that P&C companies continually refine both the delineations they make among risk groups and the premiums they charge.
Thus, insurance companies generally seek to improve the accuracy of their risk analysis. They collect many data fields for each policy they underwrite. From time to time, the use of certain consumer data for underwriting (for example credit scores or neighborhood boundaries) comes under attack for philosophical or political reasons. Thus, there is a need to identify factors for use in classifying prospective insureds.

System, program product and method for segmenting and underwriting using voting status


The present invention provides a pyrido five-element aromatic ring compound, and a preparation method therefor and a use thereof. The compound provided in the present invention has an inhibitory effect on wild-type and/or mutant EZH2, and is well positioned to become a novel anti-tumor drug or a drug for the treatment of autoimmune diseases.

Epigenetics means that expression of a gene has undergone heritable changes while the nucleotide sequence of the gene keep unchanged, which play an important role in regulating cell proliferation, differentiation, survival and apoptosis. An important mechanism of epigenetic regulation is histone covalent modification. In eukaryotic cells, DNA surrounds the histones to form nucleosomes, which is the basic structure of chromatin. In each nucleosome, two molecules of H2A, H2B, H3 and H4 form a histone octamer. A variety of covalent modifications occur at the N-terminal amino acid end of each histone, such as methylation, acetylation, phosphorylation, ubiquitination, etc., so as to control gene expression. Enzymes which catalyze the methylation of histones are called histone methyltransferases (HMTs).
The polycomb protein PRC2 is a multiprotein complex that functions to catalyze the methylation of lysine (H3K27) at position 27 of histone H3, thus causing silencing of related genes. The catalytic subunit of PRC2 is EZH1 or EZH2. EZH1 or EZH2 alone has no catalytic function and must be combined with EED and SUZ12 before it can exert methyltransfertion. EZH2 is highly expressed in cells of various tumors (such as breast cancer, colorectal cancer, endometrioma, gastric cancer, liver cancer, kidney cancer, lung cancer, melanoma, ovarian cancer, pancreatic cancer, prostate cancer and bladder cancer), and is closely related to a process of tumor cells, such as proliferation, invasion, drug resistance and migration.
In recent years, EZH2 has been found to have mutated in 8-24% of non-Hodgkin's lymphomas, such as Y641F, Y641N, Y641S, Y641H, A677G and A687V. These mutants have enhanced dimethylation and trimethylation catalytic functions to histone H3 at position 27 of lysine compared with wild-type EZH2. Excessive expression or mutation of EZH2 causes an increase in the level of 27 lysine trimethylation products (H3K27me3) of H3, and high levels of H3K27me3 plays an important role in tumor cell proliferation and survival. Abnormal EZH2 activity leads to the development of tumors. The multiple target genes regulated by EZH2 are tumor suppressor genes, and the silencing of tumor suppressor genes may be an important mechanism. Down-regulation of EZH2 by siRNA or shRNA or indirect inhibition of EZH2 by SAH hydrolase inhibitor 3-deazaneplanocin A (3-DZNep) can significantly reduce the proliferation and invasion of tumor cells in vitro and the growth of tumors in vivo.
EZH2 also plays an important role in the differentiation of T cells. EZH2 reduces the expression of Th1/Th2 cytokines (such as IFN-γ, IL-4, IL-5, etc.), inhibits Th1/Th2-dependent T cell migration, and activates regulatory T cells. In the tumor microenvironment, EZH2 inhibits Th1 chemokines such as CXCL9 and CXCL10, which is an important mechanism for tumor immune escape.
In summary, there is an urgent need in the art to develop effective drugs capable of inhibiting wild-type and/or mutant EZH2.

Pyrido five-element aromatic ring compound, preparation method therefor and use thereof

SHANGHAI INSTITUTE OF MATERIA MEDICA, CHINESE ACADEMY OF SCIENCES


A method of manufacturing a field effect transistor according to the present invention is disclosed including the steps of preparing a semiconductor substrate; forming an insulating film for use as high concentration on the semiconductor substrate; forming an insulating film for use as low concentration on the insulating film for use as high concentration; performing a heat treatment on the insulating films to thereby diffuse impurities; forming high concentration regions and low concentration region in the surface of the semiconductor substrate; forming mesa and electrodes on the upper surface and side of the semiconductor substrate; and selectively etching the insulating film for use as low concentration so as to expose a predetermined portion of the upper surface of the semiconductor substrate, to thereby form a gate electrode so as to be in contact with the low concentration region of the predetermined portion.

The present invention relates to a field effect transistor, and more particularly, to a method of manufacturing a field effect transistor.
In general, a field effect transistor is composed of source and drain electrodes supplied with currents, an active layer formed therebetween and supplied with a current, and a gate electrode controlling the active layer with a voltage to thereby control the current flow.
In a metal semiconductor field effect transistor (MESFET) having such general structure, the characteristics of the current and voltage is determined by the following equations (1) and (2). ##EQU1## where x is the distance from the source electrode; y is the distance from the surface of the active layer;
Id is the drain current; PA1 z is the gate width; PA1 q is the electron charge quantity; PA1 t is the thickness of an active layer; PA1 v(x) is the movement velocity of the electron at the depth y; PA1 N(y) is the impurity concentration of the electron at the depth y; PA1 h(x) is the depth which is scarce of the electron concentration by the gate voltage within the active layer; and PA1 .di-elect cons.s is the dielectric constant of the active layer.
At this time, when the gate voltage V(h(x)) is applied, the value of the drain current Id can be obtained by finding the depth h(x) being scarce of the electron concentration from the equation (2) and substituting it for the equation (1).
As the field effect transistor having such current-voltage characteristics, there are a depletion mode field effect transistor (DFET) and an enhancement mode field effect transistor.
Here, the DFET is a device in which the lack of the electron concentration cannot fully isolate the active layer when the voltage of 0V is applied to the gate, so that the drain current flows.
Meantime, the EFET is a device in which the drain current cannot flow because the active layer is fully isolated.
The important difference between these devices is that the depths of the active layers are different from each other.
Particularly, in the EFET, it is difficult to obtain the active layer through the general method of forming the active layer, because the active layer is as thin as 500 .ANG., approximately.
Accordingly, the general method of forming the active layer will be described with reference to a conventional method.
FIG. 1 is a cross-sectional view showing the structure of a conventional field effect transistor.
Referring to FIG. 1, in the conventional field effect transistor, a buffer layer 2 of mesa shape is formed on a semiconductor substrate 1. Active layers 3, 4 and 5 are formed on buffer layer 2, sequentially.
Further, a gate electrode 7 is formed within a V-groove 6 formed in the center of active layers 3, 4 and 5.
Moreover, a source electrode 8 and a drain electrode 9 are formed on the active layers 4 and 5 of the high concentration region and on the both sides of mesa.
A method of forming the active layer in the conventional field effect transistor structure composed as described above will be explained, as follows.
The active layer is formed hitherto by using the chemical vapor deposition (CVD) method or the ion implantation method.
Here, according to the CVD method, it is relatively easy to manufacture the polymeric compound. Further, the metal organic vapor deposition method facilitating the mass production is used.
Here, the MOCVD method is a deposition method where the organic metal compound of the 3-group atom and the hydrogen compound of the 5-group atom are used as the raw material, using the hydrogen as the carrier gas. That is, the chemical reaction is made while the above raw materials are pyrolyzed on the heated substrate within the reaction chamber, so that an epitaxial layer of the solid state grows.
According to the MOCVD method, it is easy to manufacture the polymeric compound, and it is possible to mass-produce. However, the thickness and concentration of the deposited epitaxial layer is not formed uniformly over the entire of the layer.
Therefore, in case that a digital integrated circuit (IC) is manufactured by using such epitaxial growth method, the threshold voltage which is the important characteristics of the integrated circuit is not uniform. Thus, the entire yield of the circuit manufacture is reduced.
Further, there is a disadvantage that the manufacturing apparatus used for growing the epitaxial layer is expensive.
Meantime, the ion implantation method is a method that an atomic ion is implanted into a target, having so high energy as to penetrate the surface of the target.
According to the ion implantation method, a silicon is used as an n-type, a barium (Be) as a p-type, in the GaAs semiconductor. Further, using the energy of about 30.about.500 keV, the ion is implanted to the depth of 100.about.10000 .ANG. below the surface of GaAs, thereby forming the active layer.
At this time, the depth where the ion is implanted is controlled according to the magnitude of the ion energy. Thus, it is possible to select the suitable depth according to the use purpose.
Therefore, the ion implantation method is better than the MOCVD method in the uniformity aspect of the active layer, and have the good characteristics in the mass-production aspect.
However, according to the ion implantation method, it is necessary to precisely control the ion implantation. Further, the unit cost of production is increased because the manufacturing apparatus is expensive.
In addition, in the device used recently, the manufacture of the enhancement mode field effect transistor (EFET) having the thin active layer is required. Thus, there is a problem that the limit of the minimum energy appears during the ion implantation.
Meantime, as another method of forming the active layer, there is a diffusion method.
According to the diffusion method, the impurity can be doped with the thin thickness, as compared with the CVD method or the ion implantation method. Further, the steep of the impurity becomes high, thereby improving the current ratio of Ion/Ioff.
The diffusion method having such characteristics was used hitherto in a silicon, but scarcely used in a compound semiconductor. This is because the compound semiconductor has a low degree of heat tolerance.
Accordingly, in the present invention, an oxide film and a nitride film are used in order to solve the characteristics of the compound semiconductor having a low degree of heat tolerance. Further, a method of improving the characteristics having the steep impurity distribution will be used.

Method of manufacturing field effect transistor


A cyclic peptide analog of somatostatin wherein a disulfide bond links the N-terminus residue and the C-terminus residue.

Native somatostatin is comprised of both a 14-amino acid isoform (somatostatin-14) and a 18-amino acid isoform (somatostatin-28). Heiman, et al., Neuroendocrinology, 45:429-436 (1987). Because of the short half-life of the native somatostatin, various somatostatin analogs have been developed, e.g., for the treatment of acromegaly. Raynor, et al., Molecular Pharmacol. 43:838 (1993). Five distinct somatostatin receptors have been identified and characterized. Hoyer, et al., Naunyn-Schmiedeberg's Arch. Pharmacol., 350:441 (1994). Somatostatin produces a variety of effects, including modulation of hormone release, e.g., growth hormone, glucagon, insulin, amylin, and neurotransmitter release. Some of these effects have been associated with its binding to a specific somatostatin receptor. For example, the inhibition of growth hormone has been attributed to the somatostatin type-2 receptor ("SSTR-2") (Raynor, et al., Molecular Pharmacol. 43:838 (1993); Lloyd, et al., Am. J. Physiol. 268:G102 (1995)) while the inhibition of insulin has been attributed to the somatostatin type-5 receptor ("SSTR-5") (Coy, et al. 197:366-371 (1993)). It is preferred to have an analog which is selective for the specific somatostatin receptor subtype responsible for the desired biological response, thus, reducing interaction with other receptor subtypes which could lead to undesirable side effects.


The meso-azacyclic aromatic acid amides and esters of the present invention are useful in the treatment of the central nervous system and gastrointestinal motility disorders such as gastroesophageal reflux, non-ulcer dyspepsia, delayed gastric emptying, ileus, irritable bowel syndrome, and the like. Additionally, the compounds of the present invention find utility as antagonists of serotonin 5-HT.sub.3 receptors. As such they are useful for the treatment of humans and animals wherein antagonism of 5-HT.sub.3 receptors is beneficial. Therapy is indicated for, but not limited to, the treatment of anxiety, psychoses, depression (especially depression accompanied by anxiety), cognitive disorders, substance abuse dependence and/or withdrawal, irritable bowel syndrome, emesis caused by chemotherapeutic agents, and visceral pain. Additionally, the compounds of the present invention may find utility as enhancers of nasal absorption of bioactive compounds.

The invention herein is directed to compounds and a method of treating gastrointestinal motility disorders of a mammal by administering to the mammal in need thereof a therapeutically effective amount of a compound disclosed herein or a pharmaceutically acceptable salt thereof. The method can be practiced to treat gastrointestinal motility disorders such as gastroesophageal reflux, diseases characterized by delayed gastric emptying, ileus, irritable bowel syndrome, and the like. The compounds of the invention are serotonergic 5-HT.sub.3 antagonists and as such are useful for the treatment of conditions, for example, such as anxiety, psychoses and depression.
There are classes of compounds known for the treatment of such disorders. For example, azatetracycle compounds are disclosed in co-pending U.S. patent application Ser. No. 07/515,391 filed Apr. 27, 1990, and N-Azabicyclo [3.3.0] octane amides of aromatic acids are disclosed in copending application serial no. 07/406,205 filed Sep. 11, 1989.
Aza-adamantyl compounds are disclosed in U.S. Pat. No. 4,816,453 and are mentioned generically in U.K. Patent 2,152,049A and European application 0189002A2.
Azabicyclic nonanes are disclosed in European Patent application 0094742A2. Additional azabicyclic compounds are disclosed in U.S. Pat. Nos. 4,797,387 and 4,797,406.
Benzamides have been known as 5-HT.sub.3 antagonists and as compounds possessing gastrointestinal motility-enhancing properties. Benzamides of the following formula: ##STR1## compounds wherein X can be an azabicycloalkane moiety and which exhibit gastrointestinal motility enhancing and/or 5-HT.sub.3 antagonist properties are disclosed in EP 0094742A2 and in U.S. Pat. No. 4,797,406. In addition, UK Patent 2,152,049 discloses that certain benzamide derivatives exhibit serotonin M antagonistic activity.
Indoleamides of the following formula have also been described as possessing gastrointestinal motility-enhancing and/or 5-HT.sub.3 antagonist properties: ##STR2## Compounds wherein X contains an aminergic side chain or an azabicycloalkane moiety are described in U.S. Pat. No. 4,797,406.
European patent publication number 0,230,718 discloses certain substituted benzamide derivatives, substituted with piperidinyl analogues as having gastrointestinal motility-enhancing and/or antiemetic activity and/or 5-HT receptor antagonist activity. J. Heterocyclic Chemistry (1987) 24: 47 describes the preparation of the following compound: No substitution is shown in the phenyl ring and no utility is described. ##STR3## J. Pharmaceutical Sciences (1987) 76: 416 describes compounds of generic scope. Utility as anti-arrhythmic agents is described. ##STR4## n=1 or 2 R.sub.1 =H, 2-Me, 4-NH.sub.2, 4-OMe, 4-NHCO.sub.2 Et, 2-OEt, 4-OEt, 3- or 4-NMe.sub.2, 3- or 4-NO.sub.2 ; R.sub.2 =H or 6-Me.
JP Patent 58083694 A2 and JP 0027355B describe anti-arrhythmic agents of the following formula wherein n=1 or 2; R.sub.1 or R.sub.2 are both Me or R.sub.1 is H while R.sub.2 is nitro, di-lower alkylamino, lower alkoxycarbonylamino, or ethoxy. ##STR5##
EP Patent 39,903 and U.S. Pat. No. 4,617,401 describe compounds of the following formula wherein R is H, OMe, OH, or NH.sub.2 ; X is NH or O; and Z is a lone electron pair or optionally substituted alkyl group. The compounds are described as spasmolytic, antiarrhythmic, and neuromuscular-blocking agents. ##STR6##

New meso-azacyclic aromatic acid amides and esters as novel serotonergic agents


A robot (1) is provided which includes a situated behaviors layer (SBL) (58). This SBL (58) is formed in the form of a tree structure in which a plurality of schemata (behavior modules) is connected hierarchically in such a matter that the schemata are highly independent of each other for each of them to behave uniquely. A patent schema can define a pattern in which child schemata are connected, such as an OR type pattern in which the child schemata are caused to behave uniquely, AND type pattern in which the plurality of child schemata are caused to behave simultaneously or a SEQUENCE type pattern indicating a sequence in which the plurality of child schemata should behave, thereby permitting to select a behavior pattern of the robot (1). Also, a new child schema can additionally be included in the SBL (58) without having to rewrite the schemata connection in the tree structure, whereby a new behavior or function can be added to the robot (1). Namely, the plurality of behavior modules permits to enable the robot (1) to show a complicated behavior and have units thereof recombined.

1. Field of the Invention
The present invention generally relates to a robot apparatus which can behave autonomously to have realistic communications with the user and a method of controlling the behavior of the robot apparatus, and more particularly to an autonomous robot apparatus which can recognize surroundings thereof including images and sounds and behave itself in response to such conditions, and a behavior control method for the robot apparatus.
This application claims the priority of the Japanese Patent Application No. 2002-257097 filed on Sep. 2, 2002, the entirety of which is incorporated by reference herein.
2. Description of the Related Art
A machine or device capable of performing like a human being (animal) by electrical or magnetic operations is called "robot". In Japan, the robots had started prevailing in the late 1960s. Many of the robots were industrial robots such as manipulators, transport robots and the like intended for automation, unmanning, etc. of the factory production lines.
Recently, there have been developed utility robots which support the human life as a partner of the human being, that is, support the human activities in the residential environment and other daily living situations. Different from the industrial robots, the utility robots have abilities of autonomically learning how to adapt themselves to human beings different in personality from each other in various aspects of the human beings' living environments or to various environments or to various environments. There are being put to practical use the "pet" robots simulating the physical mechanism and behaviors (motions or actions) of a quadrupedal walking animal such as a dog or cat and the "humanoid" robots designed based on the physical mechanism and behaviors of the human being or the like walking on two feet, for example.
Since the above "pet" and "humanoid" robots can perform various behaviors designed with major consideration to the entertainment as compared with the industrial robots, they are often called "entertainment robots". Some of the entertainment robots autonomously behave adaptively to external information and internal status.
Generally, the robot of such an autonomous type selects a sequence of behaviors correspondingly to change in environments including images and sounds. Also, some of the autonomous robots have other behavior selection mechanisms which models emotions such as instinct and feeling for managing the internal status of the system and selecting a behavior correspondingly to a change of the internal status. It should be noted that the system internal status is changed as the environment changes and also when the robot does the selected behavior.
Since a robot has to be designed with considerations given to resources such as a hardware and software and required behavior of the robot, many of behavior modules are implemented on demand.
Actually, a behavior as a whole can be implemented monolithically, that is, by one software module. To implement a more complicated behavior, however, a behavior may be modularized, namely, it may be decomposed into a plurality of modules to implement the behavior by interactions among the modules.
However, when any one of the modules is used to implement another behavior, the procedure of interaction between the modules and the modules themselves have to radically be rewritten for that purpose in some cases. The modules are difficult to recombine.

Robot apparatus, and behavior controlling method for robot apparatus


This disclosure provides a method of controlling an electric drive powertrain system. The method includes providing an electric motor capable of running between a motor minimum speed and a motor maximum speed such that the electric motor can produce different amounts of torque between a first region defined between the motor minimum speed and a motor base speed and a second region defined between the motor base speed and the motor maximum speed. The method includes receiving a signal from operator inputs and determining a desired transmission output torque based on the signal received from the operator inputs. The method also includes determining a desired motor torque based on the desired transmission output torque, operating the electric motor at a current corresponding to the desired motor torque and producing a greater amount of torque at the motor base speed than at the motor minimum speed.

Different work machines, particularly in the construction and forestry industries, can be designed with different power and torque requirements. This can also be the case with machines having electric drive powertrains. In some instances, the electric drive powertrain includes a transmission powered by an electric motor. The amount of torque provided by the motor can control the machine during operation. In addition, the power and torque ratio can change for different sized machines. As a result, the design of the powertrain system for larger machines can require an increase of costs due to the additional power and different performance requirements.

Method and system for controlling torque in an electric drive powertrain


A hookswitch actuator including an activating mechanism which maintains the hookswitch circuit of a telephone in an "on hook" state when the activating mechanism is in a first position, or in an "off hook" state when the activating mechanism is in the second position. The movement of the activating mechanism between the two positions is accomplished through the use of a shape memory alloy mechanism. The shape memory alloy mechanism is coupled to the activating mechanism in such a way that heating or cooling of the shape memory alloy mechanism moves the activating mechanism between its two positions. Control of the heating and cooling of the shape memory alloy mechanism is effectuated by controlling the amount of electric current passing through it.

1. Field of the Invention
This invention relates to the field of actuators, and more particularly to a device which utilizes a shape memory alloy mechanism to change the state of a telephone hookswitch circuit.
2. Description of the Related Art
Telephone headsets are well-known and widely used in business settings. Headsets allow a person to hold a conversation while still having both hands free to operate other devices, take notes, and the like. There are many situations in which a person talking on a telephone would want to be able to move around or away from the telephone in addition to having his or her hands free. For example, a headset user whose telephone base is at his or her desk might be working elsewhere at a table or a filing cabinet while holding a telephone conversation. A cordless headset allows a user to roam further from the telephone base than does a corded headset.
In order to answer or initiate a telephone call with a standard handset telephone, a user simply lifts the handset. This action changes the state of a hookswitch circuit in the telephone base. When the handset is "on hook," the hookswitch circuit is open, and the telephone is not active. When the handset is "off hook," the hookswitch circuit is closed, and the telephone is active and available to make or receive a call. In most handset telephones the state of the hookswitch circuit is changed through the position of a hookswitch in one or more of the wells where the handset rests. In many telephones, the hookswitch is a lever which is pushed out of a slot in the well of a telephone by a spring. When the handset is placed on the telephone base with a portion of the handset in the hookswitch well, the hookswitch is depressed, opening the hookswitch circuit. When the handset is lifted the hookswitch is allowed to spring forward, closing the hookswitch circuit and activating the telephone. In some telephones, the hookswitch is not mechanically activated by a spring, but rather is activated by a magnetic induction circuit in response to the presence or absence of the handset in the telephone base.
Without a special device to control the hookswitch circuit, a headset user must lift the handset off the telephone base in order to put the hookswitch circuit in the "off hook" state before answering or initiating a call. The handset must be kept off the hookswitch for the duration of the call. Headset users may find this annoying since some place other than the telephone base must be found for the handset to rest. Headset users also find the need to remove the handset particularly troublesome since they are required to return to the telephone base to answer or initiate a telephone call. This undermines the utility of a headset, particularly cordless headsets, since the user is not able to answer or initiate calls remotely or in a hands-free manner.
Mechanisms have been devised to displace the handset from the telephone base for headset users. Mechanical lifters have been employed to lift and hold the handset above the hookswitch. Such lifters typically have a lever which is moved or rotated by the user to raise and lower the handset. However, these systems still require users of either corded or cordless headsets to return to the telephone base each time a call is to be answered or initiated. Thus, these devices do not adequately serve the needs of many headset users.
Electro-mechanical lifters use electric motors and gears to effect the lifting of the handset (or other weight placed on the hookswitch). Because this kind of lifter is controlled electrically, it is possible to design an electromechanical lifter system to respond to a remote signal. Such an electromechanical lifter may allow headset users to answer or initiate telephone calls without returning to the telephone base. Electro-mechanical lifters, however, are typically complex and expensive. Their complexity generally results in their being bulky objects which take up desk space next to the telephone base. The expense of electromechanical lifters prohibits their wide acceptance and use, for example in call centers with hundreds or even thousands of users, or by ordinary consumers.
Accordingly, it is desirable to provide an apparatus for operating the hookswitch of a telephone base that overcomes the limitations of conventional products by providing an inexpensive, easy to use apparatus for activating the hookswitch, and that is amenable to remote operation.


The present invention relates to a computer-aided process for carrying out the structural design of a stiffened panel (9) made of a composite material, optimizing a target variable, comprising a first preparation phase (21) in which a Simulation Model (25) of the stiffened panel (9) with all the relevant information for the structural analysis thereof is obtained from a General Finite Element Model (23) and the modifiable variables and the restrictions (27) are defined, and a second simulation phase (51) in which the design variables are iteratively modified for the purpose of optimizing the target variable, taking into account in each iteration the load distribution changes resulting from the previous iteration, and verifying that the restrictive conditions and the safety margins associated to the pre-established failure modes are met using for that purpose simulation expert modules (55) of families of failure modes.

The use of composite materials in the design of aeronautical structures began timidly after the Second World War. The first materials, basically glass fibers embedded in polyester resins, were used in the design of secondary structure elements, such as radomes, protection of antennae and hulls. The constant evolution of the developments of new materials has led to the progressive use thereof in more components of the airplane.
Twenty-five years of accelerated evolution, both of the properties of the material and the knowledge of their behavior, have passed since the milestone of the certification of the first primary structure element of a passenger airplane completely designed with composite material was achieved in the 80s decade until today, when the launch of the design of the greater part of the structure of an airplane in composite material is studied.
The composite materials that are most used in the aeronautical industry consist of fibers or fiber bundles embedded in a matrix of thermosetting or thermoplastic resin, in the form of a preimpregnated or "prepreg" material.
Without the intention of being thorough, the advantages of composite materials can be specified in three essential aspects:                Their high specific strength with respect to metallic materials. It is the strength/weight equation.        Their excellent behavior before fatigue loads.        The possibilities of structural optimization hidden in the anisotropy of the material and the possibility of combining fibers with different orientations, allowing the design of the elements with different mechanical properties adjusted to the different needs in terms of applied loads.
Processes for designing aeronautical structures taking advantage of said optimization possibilities are not known in the prior art and the present invention intends to solve this shortage.

Process for optimizing the structural design of a stiffened composite material panel


An image pickup unit (2) mounted on a vehicle shoots an image in front thereof to attain image information. An edge pixel extraction section (40202 to 40206) scans the obtained image information for each line and then checks boundaries between a particular color and the other colors to extract pixels having the particular color as edge pixels. Moreover, a candidate line extraction section (40208 to 40212) references position coordinates of the extracted edge pixels such that assuming the edge pixels to be classified to configure straight lines, the edge pixels are coupled with each other to configure straight lines according to the classification so as to obtain the straight lines as candidate lines.. Thereafter, a line selection section (40212) selects a left line and a right line in front of the vehicle from the plural candidate lines, thereby attaining the left and right lines.

An apparatus for recognizing a running route or lane area according to image information obtained through an image pickup operation by an onboard camera has been described, for example, in the JP-A-4-134503 (article (1)).
The apparatus above includes scan means for extracting a running route edge from image information inputted via image input means and scanning upward an image associated with the extracted running route edge beginning at a particular reference point in a horizontal direction and means for setting a center of the scanned area to a particular reference point in the horizontal direction for the subsequent scanning operation such that the running route zone according to the area scanned by the scan means.
In other words, a color corresponding to pixels which constitute the image information and which are at the lower portion of the screen is assumed as a particular color (color of the road surface) to examine an area including a set of pixels having color information equivalent to the particular color, thereby determining a zone or an area enclosed with the particular color as a road area in front of the vehicle.
However, in accordance with the prior art described in article (1), although the zone enclosed with the particular color is assumed as a road area in front of the vehicle, there still remains a problem, for example, occurrence of an event in which the road zone enclosed with road edges (corresponding to lines of the vehicle) cannot be exactly extracted only by the technology.
For example, in a case in which the contour of the road area in front of the vehicle is complicated due to presence of wheel tracks, it is determined that there exist edges of the running route in addition to the line in the road. Resultantly, the edge cannot be appropriately recognized. In addition, there have frequently occurred a case in which the road zone cannot be correctly recognized.
On the other hand, for such a vehicle which runs on a road, it is necessary for the driver to appropriately drive the vehicle so that the vehicle runs along a predetermined running lane.
Consequently, the driver is required to continuously monitor the running road surface to pay attention to the state of the road surface and presence of other vehicles and obstacles. Therefore, a heavy psychological and physical load is imposed on the driver.
As a result, if the driver loses concentration or the driver's attention is distracted in a driving state in which the vehicle exceeds its own running lane at random, there may possibly occur a grave accident.
In particular, on a general road including opposing traffic lanes in which vehicles run mutually in the opposite directions, if a vehicle exceeds a central line of the road into the opposing traffic lane, there will possibly occur quite a serious accident.
To solve the problem, the JP-A-62-221800 (article (2)) has disclosed an apparatus in which an image of a road surface in front of the pertinent vehicle is obtained by a color image pickup device. According to the obtained color image signal, a line of the vehicle is decided according to the difference in color between the line and the road surface to thereby issue an alarm message to the driver of the vehicle.
In the conventional technology described in article (2), the existence of the line is determined according to a color representing the line, namely, yellow or white.
Since the road surface is grey and hence it is guaranteed to discriminate the road surface from the yellow line. However, the discrimination is impossible by the color difference between the white line and the grey road surface and it is therefore necessary to achieve the discrimination according to luminance.
Consequently, in a case in which the state around the road, namely, the road environment is altered, for example, luminance varies in a tunnel (an obtained image is yellow due to the yellow illumination) or due to illumination at night, it is difficult to recognize the line of vehicle according to the change in the state.
On the other hand, in the apparatus in which the line of vehicle is recognized according to image data obtained by the onboard camera, there has been generally used a method in which the state in front of the vehicle is shot by one camera. However, such an apparatus is attended with the following problems. To recognize the state in a wide range, when there is disposed a wide-angle lens, it is difficult to recognize the line in the faraway place. On the other hand, to recognize the line in the faraway place, when there is adopted a zoom mechanism of the optical system, the recognizable field of vision is restricted.
To improve the apparatus, there has been disclosed an apparatus described, for example, in the JP-A-06-229760 (article (3)).
The apparatus includes a solid-state image pickup block including an optical system having a low zoom rate and a solid-state image pickup block including an optical system having a high zoom rate. Comparing image data attained by the block of low zoom rate with that obtained by the block of high zoom rate, it is recognized that the running route in a relatively faraway place in front of the vehicle has a contour of a curved route or that the vehicle is in a state to enter a curved route.
However, according to the prior art of article (3) described above, the configuration includes a solid-state image pickup block including an optical system having a high zoom rate to recognize the contour of the line in a relatively faraway place. Therefore, there are required two optical systems for the high and low zoom rates and two solid-state image pickup blocks for the respective optical systems. This leads to a problem, namely, the size of the apparatus is increased and hence the apparatus is not necessarily suitable as a device to be mounted on a vehicle; moreover, the production cost thereof is inevitably soared.
Additionally, in consideration of the environment related to the mounting of the apparatus, namely, in the environment of a high temperature and a large amplitude of vibration, it is strongly desired that the number of optical systems is to be possibly reduced in the configuration of the apparatus.
It is therefore a first object of the present invention in relation to the problem of the prior art of article (1) to provide an apparatus in which when recognizing a line of vehicle for a running lane of the vehicle according to image information obtained by a camera mounted thereon, the line of vehicle can be correctly recognized even there exists such an edge other than the line as a noise in the road area in front of the vehicle.
A second object of the present invention in relation to the problem of the prior art of article (2) is to provide a road surface monitor apparatus employing an image process in which changes in luminance and color of the road surface just in front of the vehicle are determined to discriminate the road surface from the line of vehicle according to the luminance and color, thereby appropriately recognizing the line.
A third object of the present invention in relation to the problem of the prior art of article (3) is to provide a road surface monitor apparatus employing an image process in which when recognizing a line of vehicle for a running lane of the vehicle according to image information obtained by a camera mounted thereon, the configuration of the apparatus is not required to include a plurality of optical systems and the line can be correctly recognized in a running lane in a relatively faraway place while retaining a wide field of vision.