An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a spacer structure formed on its sidewalls. Yet more in particular, the present disclosure relates to an integrated circuit wherein at least two transistors are present having spacer structures with different thicknesses. This situation normally occurs when one of the transistors is an N-channel transistor and the other transistor is a P-channel transistor with a silicon/germanium (SiGe) alloy embedded in the source/drain regions and overfilling the trenches in which it is embedded.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
One of the most widespread technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs (PFETs) and N-channel FETs (NFETs), are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Active regions are to be understood as a portion of the semiconductor layer within which and on top of which a transistor or a semiconductor device may be formed. Presently, the semiconductor layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer.
A MOS transistor, or generally a FET, irrespective of whether an NFET or a PFET is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
However, reduction of transistor channel length may not be pushed to extreme limits without incurring other problems. For example, the capacitance between the gate electrode and the channel decreases with decreasing channel length. This effect must then be compensated for by reducing the thickness of the insulating layer between the gate and the channel. Extremely small thicknesses of the insulating layer might, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in order to increase the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors.
When fabricating transistors with typical gate dimensions below 50 nm, a so-called "high-k/metal gate" (HKMG) technology is well known and frequently employed. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. On the other hand, it is also well established to use an oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices.
Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges. For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level. Thus, in the HKMG technology, a thin metal layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). A work function metal, such as aluminum (Al) or lanthanum (La), may be present in a predetermined percentage in the metal layer or may form a separate layer between the metal layer and the high-k dielectric.
One promising strategy for improving speed and performance of a FET consists in the generation of a certain type of strain in the FET channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, it has been found that, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors.
Therefore, attempts have been made in the past decades to improve transistor performance by introducing a stress-inducing material in or near the channel region of silicon-based transistors. Stress can be brought about by the difference in lattice constant between the stress-inducing material and silicon. For instance, in order to induce a compressive stress in the channel region of a P-channel transistor, a material with a slightly larger lattice constant than silicon, such as a silicon/germanium (SiGe) semiconductor alloy, may be epitaxially grown in the transistor active region next to or on top of the channel region.
Thus, trenches may be formed in portions of the source and drain regions of a FET adjacent to the channel region. An SiGe alloy, or a semiconductor alloy in general, may subsequently be epitaxially grown in the trenches. This semiconductor alloy is also commonly referred to as an "embedded semiconductor alloy" or, in the particular case of an SiGe alloy, "embedded SiGe". The embedded semiconductor alloy is then included in the source or drain region of the FET.
According to the gate-first HKMG approach, the gate structure is formed by depositing a stack of layers, which is subsequently appropriately patterned so as to obtain a gate structure of the desired size and dimensions. The gate-first HKMG approach requires the gate electrode stack to withstand the high temperatures reached during the annealing steps performed in order to, e.g., activate the dopant species implanted in the source and drain regions or induce the silicidation process.
Thus, in order to protect the sensitive gate materials during the subsequent fabrication stages, the gate stack is encapsulated into a dielectric casing formed on its sidewall. This protective layer, also known as a "spacer" or "spacer structure," besides protecting the sensitive gate materials, is advantageously used as a mask when implanting dopants of a desired type into the semiconductor layer in which the transistor is formed. In this respect, the spacer structure may be formed in subsequent stages so as to have the appropriate shape and thickness during each implantation step.
In particular, a first spacer portion having a first thickness is formed next to the encapsulating portion. This first portion is usually called "spacer-0". A first series of implantations may be performed using the spacer-0 as a mask. This first series may include implantations carried out in order to define halo regions in the transistor channel region and extension regions in the source and drain regions. Subsequently, the spacer structure may be broadened by forming a second portion above the spacer-0 previously formed. This second portion is usually referred to as "spacer-1". A second series of implantations may then be performed in the presence of both spacer-0 and spacer-1, for example in order to define the deep regions of the source and drain regions.
When forming an array of FETs including NFET and PFET structures, according to the HKMG conventional manufacturing flow, but also if the conventional SiON/polysilicon gate structures are used, problems are incurred if embedded SiGe is used in the source/drain area of PFETs. In both of these cases, spacer structures of different thicknesses are formed on the sidewalls of NFETs and PFETs. This is illustrated in an exemplary manner for an HKMG structure in FIGS. 1a-1e, which show subsequent stages during a conventional HKMG manufacturing flow.
FIG. 1a shows a cross-sectional view of a portion of an integrated circuit 100 in a relatively advanced manufacturing stage. Transistors 151-154 have been partially formed partly in and partly on top of a semiconductor layer 110. Transistors 151-154 are, for example, FETs.
The semiconductor layer 110 is typically supported by a substrate, which may be represented by any suitable carrier for an integrated circuit. The semiconductor layer 110 may comprise, for example, silicon, germanium or also a III-V semiconductor. The semiconductor layer 110 is divided into active zones, which are to be understood as areas of the semiconductor layer 110 in which and upon which one or more FETs may be formed. FIG. 1a shows a first active region 112 housing FETs 151 and 152, and a second active region 114 housing FETs 153 and 154. FETs 151 and 152 may conveniently have an opposite polarity with respect to FETs 153 and 154. For example, FETs 151 and 152 may be N-channel FETS, whereas FETs 153 and 154 may be P-channel FETs.
Active regions 112 and 114 are separated by an isolation region 116, typically comprising an insulating material such as, for example, an oxide. For example, the isolation region 116 may comprise silicon dioxide (SiO2) and may have been formed by means of the shallow trench isolation (STI) technique.
Transistors 151-154 each comprise a respective gate structure 151g-154g. The gate structures 151g-154g shown in FIG. 1a have been formed according to the HKMG technology. Thus, the gate structures 151g-154g are each made up of a stack comprising an insulation layer 161 formed on the surface of the semiconductor layer 110, a gate metal layer 163 and a gate material layer 165.
The insulation layer 161, formed on the surface of active regions 112 or 114, comprises a high-k material. The gate metal layer 163 is formed between the insulation layer 161 and the gate material 165 so as to adjust the transistor threshold voltage. The gate material layer 165, formed directly on the upper surface of the gate metal layer 163, typically comprises a semiconductor such as polysilicon.
Each transistor 151-154 comprises a respective spacer structure 171-174 formed on the sidewall of the respective gate structure 151g-154g. The spacer structures 171-174 comprise a dielectric material which is negligibly affected by the standard wet etching process performed for cleaning purposes on the surface of the integrated circuit. Furthermore, the dielectric material constituting spacer structures 171-174 hinders transport of oxygen or other gases through its thickness. Typically, the spacer structures 171-174 are comprised of silicon nitride (Si3N4).
In the fabrication stage shown in FIG. 1a, spacer structures 171-174 comprise an inner portion 171sp0-174sp0, respectively, known as spacer-0. The spacer-0 structures 171sp0-174sp0 typically comprise Si3N4. As further shown in FIG. 1a, the spacer structures 171-174 may conveniently comprise one or more liner layers 167, used as stop-etch layers when forming the spacer structures 171-174. The liner layer 167 typically comprises an oxide. For example, the liner layer 167 may be comprised of silicon dioxide (SiO2).
The spacer structures 171-174 may be formed by depositing a first liner layer 167i, included in liner layers 167, onto the surface of the integrated circuit 100 after forming the gate structures 151g-154g. Thus, the first liner layer 167i is formed adjacent to the gate structures 151g-154g. Subsequently, a dielectric layer, such as an Si3N4 layer, may be deposited onto the first liner layer 167i and appropriately patterned in order to obtain spacer-0 structures 171sp0-174sp0. Patterning is conveniently achieved by an anisotropic etching selective to the liner layer 167i. The spacer-0 structures 171sp0-174sp0 are, thus, formed adjacent to the gate structures 171g-174g, respectively, and separated therefrom by the first liner layer 167i.
After forming the spacer-0 structures 171sp0-174sp0, a First Series of Implantations may be performed, for example, in order to form halo regions and extension regions (not shown) of transistors 151-154 in the semiconductor layer 110. Subsequently, a second liner layer 167o, also included in liner layer 167, is deposited onto the surface of the integrated circuit 100. Deposition of the second liner layer 167o is then followed by the deposition of a second dielectric layer 173, e.g., an Si3N4 layer, onto the second liner layer 167o. The dielectric layer 173 is generally deposited by using a highly conformal deposition technique, such as, for example, chemical vapor deposition (CVD). The dielectric layer 173 is subsequently patterned in order to form an outer portion of the spacer structures 171-174 called spacer-1, as will be described in the following.
FIG. 1a shows that semiconductor alloy layers 122-124 are embedded in the second active region 114, next to the gate structures 153g and 154g. The semiconductor alloy layers 122-124 typically comprise embedded SiGe (eSiGe) with a variable Ge concentration. The semiconductor alloy layers 122-124 are obtained by forming trenches in predetermined positions of the active region 114 adjacent to the gate structures 153g and 154g. The trenches are then epitaxially filled with a semiconductor alloy. If FETs 153 and 154 are P-channel FETs, the semiconductor alloy layers 122-124 may be conveniently doped with a P-type doping agent, which may include, for example, boron (B). Doping of the semiconductor alloy layers 122-124 is conveniently performed in situ while epitaxially depositing the semiconductor alloy layers 122-124 in the trenches. Furthermore, if FETs 153 and 154 have a P-channel, the semiconductor alloy in layers 122-124 is typically SiGe. As said above, since SiGe has a larger lattice constant than Si, SiGe layers 122-124 exert a compressive strain onto the areas of the active region 114 directly underneath the gate structures 153g and 154g, which are to be included in the channel regions of FETs 153 and 154, respectively. This is beneficial to the mobility of holes in the channel region of a P-channel FET.
FIG. 1a also shows that, in the case in which semiconductor alloy layers 122-124 comprise SiGe, layers 122-124 each comprise a bottom portion 122a-124a, a middle portion 122b-124b and a top portion 122c-124c. The three portions of the SiGe alloy layers 122-124 differ from each other for the concentration of Ge.
More specifically, bottom portions 122a-124a have a lower Ge concentration than middle portions 122b-124b. For example, the concentration of Ge in bottom portions 122a-124a could be of approximately 25%, whereas the concentration of Ge in middle portions 122b-124b could be of approximately 35%. Thus, bottom portions 122a-124a formed adjacent to the surface of active regions 114 have a smaller lattice constant than middle portions 122b-124b formed above bottom portions 122a-124a, respectively. Since the lattice mismatch with silicon is smaller, bottom portions 122a-124a are affected by a lower degree of internal strain than middle portions 122b-124b, which favors a pseudomorphic epitaxial growth of SiGe layers 122-124 onto the semiconductor layer 110, typically including silicon.
Top portions 122c-124c of SiGe alloy layers 122-124 are then formed above middle portions 122b-124b, respectively. Top portions 122c-124c contain a substantially null concentration of Ge and are exclusively comprised of Si. The presence of top portions 122c-124c is necessary in order to favor the silicidation process subsequently performed on the surface of the integrated circuit 100 in order to form electrical connections to the electrodes of the FETs formed therein. Metal silicide formation is indeed known to be much more easily and reliably achieved in Si than in an SiGe alloy.
The structure of the semiconductor alloy layers 122-124 discussed above results in the trenches being significantly overfilled by the semiconductor alloy material. The semiconductor alloy material of layers 122-124, typically SiGe, can in some cases protrude outwards, for instance, by a height of approximately 15 nm from the plane identified by the surface of the semiconductor layer 110. In general, the semiconductor alloy material of layers 122-124 protrudes typically more than 10 nm, often more than 20 nm from the plane identified by the surface of the semiconductor layer 110.
In FIG. 1b a cross-sectional view is shown of the integrated circuit 100 in a subsequent manufacturing stage to that shown in FIG. 1a. After forming the dielectric layer 173 shown in FIG. 1a, this is patterned in order to give rise to outer portions 171sp1-174sp1 of spacer structures 171-174, respectively, shown in FIG. 1b. Outer portions 171sp1-174sp1 are also known as spacer-1 structures. Patterning is usually achieved by means of a dry etching selective to liner layer 167, in such a way that the second liner layer 167o acts as a stop-etch layer. The dry etching process is preferably highly anisotropic. Patterning of the dielectric layer 173 is usually performed without the presence of a mask, thus affecting the whole surface of the integrated circuit 100.
As shown in FIG. 1b, spacer-1 structures 171sp1-174sp1 have different thicknesses from each other. More specifically, spacer-1 structures 171sp1 and 172sp1 of FETs 151 and 152 are considerably thicker than spacer-1 structures 173sp1 and 174sp1 of FETs 153 and 154. This is due to the fact that the semiconductor alloy material 122-124 overfilling the trenches between and around FETs 153 and 154 causes the thickness of the portion of conformal nitride layer 173 lying above FETs 153 and 154 to decrease with respect to the thickness of the portion of conformal nitride layer 173 lying above FETs 151 and 152.
While FIGS. 1a and 1b show the process flow for an HKMG structure, the skilled person will understand that the same thickness constraints for the spacer-1 structures will result in a SiON/polysilicon gate structure process due to the raised surface portion of the eSiGe in the trench between FETs 153 and 154.
The large thickness of spacer-1 structures 171sp1 and 172sp1 results in a high aspect ratio of the gap between FETs 151 and 152. In general, the aspect ratio of an aperture is defined as the ratio of the length (dimension along the vertical axis in the figures) to the width (dimension along the horizontal axis in the figures) of the aperture.
As a result of the patterning process of conformal nitride layer 173, the distance between spacer-1 structures 171sp1 and 172sp1 shown in FIG. 1b is considerably less than the distance between spacer-1 structures 173sp1 and 174sp1. Therefore, the portion of the surface of the semiconductor layer 110 included between FETs 151 and 152 is much smaller than that included between FETs 153 and 154.
FIG. 1c shows a cross-sectional view of the integrated circuit 100 in a subsequent manufacturing stage to that shown in FIG. 1b. After forming spacer-1 structures 171sp1-174sp1 as described above, a further series of ion implantations may be performed. For example, during this series of implantations, doping agents may be implanted in active region 112 in order to form deep regions (not shown) of source and drain regions of FETs 151 and 152. Thereafter, an annealing step is performed in order to activate the implanted ions and to let the semiconductor layer 110 recover from implantation damage.
After the annealing step, a further etching is performed on the surface of the integrated circuit 100 in order to remove the exposed portion of the oxide liner layer 167, i.e., the portion of the oxide liner layer 167 not lying underneath one of the gate structures 151g-154g or of the spacer structures 171-174. FIG. 1c shows the integrated circuit 100 after this oxide liner removal process. After removing the exposed portion of the oxide liner layer 167, the gate material 165 is exposed in the gate structures 151g-154g. Furthermore, portions of the surfaces of the active regions 112 and 114 are left exposed between and around FETs 151-154. It should be noted that, after the exposed portions of the oxide liner layer 167 have been removed, the aspect ratio of the gap between FETs 151 and 152 is increased.
FIG. 1d shows that a silicidation process 181 is carried out on the integrated circuit 100 after removing the exposed liner layer 167. The silicidation process 181 is carried out in order to decrease the contact resistance to the electrodes of FETs 151-154. Silicidation 181 is performed according to a well-established procedure.
Salicidation (i.e., self-aligned silicidation) 181 is typically performed by depositing a refractory metal layer onto the exposed face of the integrated circuit 100. The refractory metal layer may comprise, for example, a metal such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer comprises nickel. The refractory metal layer may also comprise platinum, which, in some cases, may promote a more homogeneous formation of nickel monosilicide.
A heat treatment is then applied to the semiconductor structure 100 in order to promote a chemical reaction between the metal atoms of the deposited layer and the silicon atoms of the exposed surface of the semiconductor structure 100.
FIG. 1d shows that, as a result of the heat treatment, metal silicide layers 151gs-154gs have formed partly in and partly on top of the gate material 165 of the gate structures of FETs 151-154. Furthermore, metal silicide layers 140 and 141 have formed partly in and partly on top of the first active region 112, so as to provide electrical contacts with a low contact resistance to the source and drain regions of transistors 151 and 152. Analogously, metal silicide layers 142-144 have formed partly in and partly on top of the semiconductor alloy layers 122-124, respectively, so as to provide electrical contacts with a low contact resistance to the source and drain regions of transistors 153 and 154. More specifically, metal silicide layers 142-144 have formed in top portions 122c-124c of the semiconductor alloy layers 122-124, respectively. Typically, metal silicide layers 151gs-154gs and 140-144 comprise nickel silicide.
Due to the proximity of spacer-1 structure 171sp1 to spacer-1 structure 172sp1, metal silicide layer 140 formed between FETs 151 and 152 is much smaller than metal silicide layer 143 formed between FETs 153 and 154. In particular, the width (dimension along the horizontal direction in FIG. 1d) of metal silicide layer 140 is much less than the width of metal silicide layer 143. This results in a significantly higher contact resistance of metal silicide 140 as compared to metal silicide layer 143. For example, the contact resistance to the source and drain regions of FETs 151 and 152 has been measured to be up to 50% greater than the contact resistance to the source and drain regions of FETs 153 and 154.
After the silicidation process 181, an internally stressed layer (not shown) is normally deposited on the surface of the integrated circuit 100 in order to improve the device performance. The stressed layer is to fill all void spaces and gaps between neighboring FETs 151-154. However, due to the high aspect ratio of the gap between FETs 151 and 152, the stressed layer cannot easily be deposited between FETs 151 and 152.
In order to favor the deposition of the stressed layer, a further dry etching process 182 is required, which is shown in FIG. 1e. Dry etching 182 is performed on the surface of the integrated circuit 100 after performing the silicidation process 181 and is preferably selective to oxide liner layer 167. FIG. 1e shows the integrated circuit 100 after dry etching 182 has been carried out. Etching 182 causes the width of spacer-1 structures 171sp1-174sp1 to shrink. In particular, the purpose of etching 182 is decreasing the thickness of spacer-1 structures 171sp1 and 172sp1, thereby increasing the aspect ratio of the gap between FETs 151 and 152. In this manner, the stressed layer may be more effectively deposited on the surface of the integrated circuit 100.
Etching 182 is normally performed without the presence of a mask and, consequently, affects the entire exposed surface of the integrated circuit 100, not only spacer structures 171-174. In particular, etching 182 removes a surface layer of metal silicide layers 151gs-154gs and 140-144. The thickness of the removed metal silicide layer ranges between approximately 2 nm and 5 nm. This results in a further increase of the contact resistance of metal silicide layers 151gs-154gs and 140-144.
Etching 182, although rendered necessary by the traditional manufacturing flow, is desirably omitted. Besides introducing a further step in the fabrication flow, etching 182 undesirably erodes metal silicide layers 151gs-154gs and 140-144. Furthermore, etching 182 is unduly performed on the entire surface of the integrated circuit 100, whereas the effect of spacer structure thinning is only required on FETs 151 and 152, which can be, for example, N-channel FETs. The reader is here reminded that the spacer structures of FETs 153 and 154, which may be P-channel FETs, have a satisfactory thickness also before performing etching 182.
The limitations and problems outlined above become more critical the more the distance between neighboring FETs decreases in an integrated circuit. This situation calls for an improved manufacturing flow, capable of compensating for the thickness imbalance between spacer structures of, for example, N-channel FETs and P-channel FETs.


The invention relates to an integrated tubular reaction device, which comprises a reaction vessel, a reaction vessel including at least two tubular chambers, a channel connecting at least two tubular chambers and an opening; a cover body, which can be worked with the opening, and a cover body including a through hole; a seal, which includes a sealing plug which can be worked with the through hole. The integrated tubular reaction device solves the problem of contamination of reaction products in the process of multiple or multi-step biological enzyme reaction, and can realize multiple or multi-step biological enzyme reactions in the same device.

With the development of biotechnology, modern molecular biology technology or genetic engineering technology is increasingly widely used in various biotechnology industries, especially in medical diagnosis. The application of these techniques often involves multiple or continuous multi-step enzymatic reactions. For example, when it is necessary to detect RNA virus, the first step is to purify the RNA from the virus, then reverse the RNA into cDNA, and finally carry out the cDNA amplification reaction. A typical DNA (or cDNA) amplification reaction is polymerase chain reaction, or PCR. In the similar multi-step enzyme reaction, the existing technology needs to carry out each step of reaction separately. Specifically, each reaction is carried out in a separate test tube and operated by hand or robot.
However, when a separate tube is used for the multi-step reaction in the process, the reaction product is transported from one tube to another, the product molecules will be exposed to the environment outside the tube, which is easy to contaminate the working environment and lead to false positive reaction in the sample test in the future. In addition, the use of separate test tube for multi-step reaction takes up a lot of space time-consuming, and using more materials, thus increasing the cost.
In order to carry out multi-step or continuous multi-step enzyme reaction more conveniently, the existing technology also provides a new technical scheme. Different steps are integrated with microfluidic technology to achieve the purpose of automated operation. Products created by microfluidic technology are often called integrated biochips. The use of integrated biochip can avoid the molecular contaminationcontamination of the product, but its structure is complex and the production cost is high. In addition, the integrated biochip has a small volume structure and does not match the volume requirement of general biological samples. Therefore, the practical value of integrated biochip is limited.

This patent is subject to a terminal disclaimer.


An angle adjustable grip mounting device including a cylindrical connector fastened to either end of a tubular bicycle handlebar by a short tube and a screw nut by means of the control of an adjusting screw to hold a grip by means of two arched symmetrical clamping plates. The grip has a round head held between two arched clamping plates received inside the cylindrical connector, and retained in position by the two arched clamping plates, which are spaced by an opening on the peripheral wall of the cylindrical connector, are fastened together. The screw nut and the short tube become biased on two opposite sides and firmly retained in the tubular bicycle handlebar as the adjusting screw is turned clockwise to move the screw nut toward the short tube.

The present invention relates bicycle handlebars, and more particularly to an angle-adjustable grip mounting device for mounting a grip to a bicycle handlebar.
FIG. 1 illustrates a bicycle handlebar according to the prior art which comprises two curved grips B connected to two opposite ends A1 of a transverse tube A. Each grip B has one end terminated to an eye mounted around either end A1 of the transverse tube and then fixed in place by a respective tightening up screw C. If the angular position of either grip B is to be changed, the tightening up screw C is loosened and then screwed tight again after the respective grip B has been turned to the desired angle. The thread of the tightening up screw C may be damaged easily when repeatedly loosening the tightening up screw C and then screwing it tight again. Therefore this grip mounting structure is not durable in use.


A fiber optic connector cabinet is provided that has at least one adapter panel rotatably mounted to the cabinet and that carries at least one fiber optic connector adapter. The angular position of the adapters relative to a front plane of the cabinet is readily adjustable.

Fiber distribution frames are used in the fiber optic industry to provide a point of interconnection between an array of incoming optical fiber cables and an array of outgoing optical fibers. Optimally, the fiber distribution frame allows reconfiguration of the incoming fibers relative to the outgoing fibers to provide flexibility in the optical fiber network. To achieve such flexibility, fiber distribution frames typically are designed to receive different types of cabinets on the frame that can be arranged depending on the requirements of the specific network being constructed. Such cabinets can include splice cabinets where fibers are joined by a splicing technique and the splices are organized and stored in trays in the splice cabinet. Another cabinet is storage cabinets that organize and store excess cable slack so as to prevent bending of the fiber cable beyond its minimum bend radius.
Another commonly used cabinet is the coupler cabinet that has an array of couplers for coupling a pair of optical fiber connectors that are terminated on the ends of a respective pair of optical fibers. One side of the array of couplers typically receives connector-terminated incoming fiber cables and the other side of the array of couplers will receive connector-terminated jumper cables or outgoing fiber cables, or vice versa.
It is preferred that the array of couplers in the cabinet provide for the following features: (1) ease of installation of connectors on both sides of couplers, (2) insurance against exceeding minimum bend radius of optical fiber cables, (3) accommodating a variety of reconfigurations of the connectors on the array of couplers, and (4) minimizing space required at the front of the coupler cabinet for the optical fiber extending from the front of the array of couplers.
In existing coupler cabinets for fiber distribution frames the couplers are typically mounted in the cabinet and fixed relative to the cabinet. For example, the couplers may be arrayed in a plane parallel to the front face of the cabinet with each coupler oriented perpendicular to the plane of the array. In such an arrangement, the optical fiber extending from the front of the array must be routed through a 90 degree turn to the coupler. In another example, the coupler cabinet shown in FIG. 9 of U.S. Pat. No. Re 34,955 has a front panel with the left half of the panel having an array of adapters that hold couplers at a 45 degree angle to the left, and the right half of the panel having an array of adapters that hold couplers at a 45 degree angle to the right. In such an arrangement, an optical fiber coming from the right side of the frame cannot be routed to a coupler in an adapter in the left half of the panel without the optical fiber having to be routed through a sharp turn. Such arrangement is limited on its accommodation of reconfigurations of connectors on the array of couplers.
Therefore a need exists for a coupler cabinet that allows the angle of the couplers relative to the array of couplers to be readily adjusted facilitate installation and reconfiguration of connectors to the array of couplers without exceeding the minimum bend radius of the optical fiber.

Fiber optic connector cabinet with rotatably mounted adapter panels


A system and method for realizing vector Kerr magnetometry are disclosed. The system enables simultaneous longitudinal and transverse Kerr effect measurements at each point on a sample surface. An optional component includes a sample platform for achieving precise linear and rotational relocation. The repositionable platform enables complete, 360 degree characterization about a single point. Additionally, the platform control mechanism may be utilized in obtaining longitudinal and transverse Kerr effect measurements at succeeding points on the surface of a sample. Rapid sample characterization is thus achieved.

N/A
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This invention pertains to Kerr effect magnetometry in general, and in particular to a system and method for realizing multi-dimensional or vector Kerr effect magnetometry.
The Magneto-optic Kerr effect (MOKE), or more simply referred to as the Kerr effect, corresponds to a change in the intensity or polarization state of light reflected from a magnetic material. Since the amount of change in the polarization state or intensity is proportional to the magnetization in the material, it is possible to use this effect to examine magnetic properties of a material sample.
The prior art has provided three discrete geometries for characterizing a material sample: longitudinal MOKE; transverse MOKE; and polar MOKE. With a longitudinal MOKE geometry, a magnetic field is applied parallel to the plane of the film and the plane of incidence of the light. With a transverse MOKE geometry, the magnetic field is applied perpendicular to the plane of incidence of the light. With a polar MOKE geometry, the magnetic field is applied orthogonal to the surface of the sample. In all cases, a polarization rotation in the detected light provides an indication of the relative magnetization of the sample under test.
Another prior art approach employed for characterizing light transmissive materials is a polar Faraday effect system. A magnetic field is applied parallel to the surface of the material under test. Light is emitted through a point in the material under test and is received on the opposite side of the material. Intensity or polarization changes in the received light are used to characterize the response of the material to the applied field. Practically speaking, the detector can be located in any location as long as the appropriate optics are employed for relaying the received light.
Systems employing the longitudinal, transverse or polar geometries may be referred to as scalar systems. Scalar analysis has to-date provided the only non-contact, non-destructive approach for detecting magnetic response.
Certain magnetic materials are described as being anisotropic, in that the magnetic response to an applied magnetic field at a point on the surface of the material varies in theta about the point, theta being defined in the plane of the material sample. In general, anisotropic materials exhibit a variation on magnetic behavior in one or multiple directions some of which may or may not be in the plane of the sample. Thus, in the presence of a magnetic field applied in the x direction, a material sample may exhibit one characteristic response in light reflected off the sample in a plane parallel to the x direction, while exhibiting a different characteristic response in light reflected off the sample in a plane parallel to the y direction.
In order to measure the degree of anisotropy of a sample using scalar Kerr effect systems of the prior art, it has been necessary to obtain measurements from two separate devices, one longitudinal and one transverse. Proper alignment between instruments becomes difficult, as is the ability to gauge the relative strength of the discrete applied fields.
The easy axis of a material is the axis along which the material is most readily magnetized in the presence of an externally applied magnetic field. Certain materials exhibit easy axis dispersion, where the easy axis varies from point to point across the surface of the sample. Scalar detection systems have consequently provided incomplete characterization of anisotropic materials.
A system and method for realizing vector Kerr magnetometry is disclosed. The system enables simultaneous longitudinal and transverse Kerr effect measurements at a single point on a sample surface. Consequently, anisotropic materials may be more completely, rapidly and accurately characterized. The system may be used with a variety of materials to be tested, including but not limited to magnetic media (e.g. hard drive platters), thin film heads, magnetic random access memory (MRAM) and permanent magnetic wafers.
An optional component of the presently disclosed system includes a sample platform with motive elements and an associated controller for achieving precise relocation of the sample under test in x, y, and theta. Thus, even though the present system enables two-dimensional hysteresis loop characterization at a sample location without sample movement, the repositionable platform as disclosed enables complete, 360 degree characterization about a single point, if desired. Alternatively, the highly precise control mechanisms may be utilized in obtaining longitudinal and transverse Kerr effect measurements at succeeding points on the surface of a sample. Rapid sample characterization is thus achieved, including easy axis dispersion measurement with a much higher accuracy as compared to prior art measurement systems.
A further embodiment of the presently disclosed system includes the integration of a polar Faraday effect emitter/detector pair in conjunction with the vector Kerr magnetometry system disclosed above, either with or without the x, y, and theta translatable sample platform. More accurate and rapid sample characterizations are thereby achieved.


A centrifugal compressor has a plurality of seals arranged at the back of an impeller for sealing the impeller outlet and form an annular space defined at the back of the impeller. The annular space is fed with a cold gas under a higher pressure than that of the air discharged at the impeller outlet. Thus, the back of the impeller is cooled down.

1. Field of the Invention
The present invention relates to a centrifugal compressor to be applied, for example, as a supercharger of an engine.
2. Description of the Prior Art
FIG. 3 shows a longitudinal section of a centrifugal compressor of the prior art, and FIG. 4 illustrates the operation of the same. A labyrinth packing 5 is sandwiched between the back of an impeller 1 of the centrifugal compressor and a casing 12. The labyrinth packing 5 seals a space 7 by being located between the outlet and back of the impeller 1. The space 7 is vented to the outside through a ventilation hole 8 for releasing a slight amount of air, which comes into the space 7 along the labyrinth packing 5, to the outside to thereby decrease the pressure in the space 7. As a result, the pressurized air leaking from the outlet of the impeller 1 to the back of the impeller 1 is prevented from establishing a thrust pushing a rotor shaft 2 in a direction toward the inlet of the impeller 1. Thus, the facial pressure on a main thrust bearing 3 is lowered to lighten the load upon the main thrust bearing 3. Reference numerals 11 and 4 designate a thrust collar and a thrust bearing, respectively.
In the existing centrifugal compressor described above, the air temperature at the outlet of the impeller 1 becomes higher with a higher pressure ratio of the centrifugal compressor. Even when air at the room temperature is aspirated, for example, its temperature reaches 200.degree. C. or more at the outlet of the impeller 1 if the pressure ratio is about 4.0. This hot air is additionally heated, while passing through the labyrinth packing 5, by the heat of friction which is produced by the rotations of the fins of the labyrinth packing 5. Thus, the back of the impeller 1 is heated. The centrifugal compressor of this single stage type intaking the atmospheric air usually has its impeller made of an aluminum alloy, and the impeller 1 is degraded due to its temperature rise when heated by the air at its back. This makes it difficult to retain a high pressure ratio if the impeller is made of an aluminum alloy. The temperature rise of the impeller 1 in turn leads to a rise in the air temperature, thus causing an efficiency drop of the compressor.


This invention relates to humanized antibodies and antibody preparations produced from transgenic non-human animals. The non-human animals are genetically engineered to contain one or more humanized immunoglobulin loci which are capable of undergoing gene rearrangement and gene conversion in the transgenic non-human animals to produce diversified humanized immunoglobulins. The present invention further relates to novel sequences, recombination vectors and transgenic vectors useful for making these transgenic animals. The humanized antibodies of the present invention have minimal immunogenicity to humans and are appropriate for use in the therapeutic treatment of human subjects.

The therapy of infectious diseases caused by bacteria, fungi, virus and parasites is largely based on chemotherapy. However, the emergence of drug-resistant organisms requires the continuous development of new antibiotics. Therapies of patients with malignancies and cancer are also based on chemotherapy. However, many of these therapies are ineffective and the mortality of diseased patients is high. For both infectious diseases and cancer, improved and innovative therapies are needed. Therapy of steroid resistant rejection of transplanted organs requires the use of biological reagents (monoclonal or polyclonal antibody preparations) that reverse the ongoing alloimmune response in the transplant recipient. The major problem of antibody preparations obtained from animals is the intrinsic immunogenicity of non-human immunoglobulins in human patients. In order to reduce the immunogenicity of non-human antibodies, genetic engineering of individual antibody genes in animals has been proposed. In particular, it has been shown that by fusing animal variable (V) region exons with human constant (C) region exons, a chimeric antibody gene can be obtained. However, this approach may only eliminate the immunogenicity caused by the non-human Fc region, while the remaining non-human Fab sequences may still be immunogenic. In another approach, human immunoglobulin genes for both, heavy and light chain immunoglobulins have been introduced into the genome of mice. While this genetic engineering approach resulted in the expression of human immunoglobulin polypeptides in genetically engineered mice, the level of human immunoglobulin expression is low. This may be due to species-specific regulatory elements in the immunoglobulin loci that are necessary for efficient expression of immunoglobulins. As demonstrated in transfected cell lines, regulatory elements present in human immunoglobulin genes may not function properly in non-human animals.
Several regulatory elements in immunoglobulin genes have been described. Of particular importance are enhancers downstream (3′) of heavy chain constant regions and intronic enhancers in light chain genes. In addition, other, yet to be identified, control elements may be present in immunoglobulin genes. Studies in mice have shown that the membrane and cytoplasmic tail of the membrane form of immunoglobulin molecules play an important role in expression levels of human-mouse chimeric antibodies in the serum of mice homozygous for the human Cγ1 gene. Therefore, for the expression of heterologous immunoglobulin genes in animals it is desirable to replace sequences that contain enhancer elements and exons encoding transmembrane (M1 exon) and cytoplasmic tail (M2 exon) with sequences that are normally found in the animal in similar positions.
The introduction of human immunoglobulin genes into the genome of mice resulted in expression of a diversified human antibody repertoire in genetically engineered mice. In both mice and humans, antibody diversity is generated by gene rearrangement. This process results in the generation of many different recombined V(D)J segments encoding a large number of antibody molecules with different antigen binding sites. However, in other animals, like rabbits, pigs, cows and birds, antibody diversity is generated by a substantially different mechanism called gene conversion. For example, it is well established that in rabbit and chicken, VDJ rearrangement is very limited (almost 90% of immunoglobulin is generated with the 3′proximal VH1 element) and antibody diversity is generated by gene conversion and hypermutation. In contrast, mouse and human gene conversion occurs very rarely, if at all. Therefore, it is expected that in animals that diversify antibodies by gene conversion a genetic engineering approach based on gene rearrangement will result in animals with low antibody titers and limited antibody diversity. Thus, the genetic engineering of large animals for the production of non-immunogenic antibody preparations for human therapy requires alternative genetic engineering strategies.

Production of humanized antibodies in transgenic animals


Methods of confidential data sharing and mutual authentication between a sensor node and a router are established, and data in the sensor node is protected from a physical attack. Sensor node issuing processing is performed on a sensor node having a tamper resistant device. The sensor node issuing processing is processing in which data and a function that are deactivated are loaded in the tamper resistant device of the sensor node from the time of manufacture of the sensor node to the time the sensor node reaches a system that runs the sensor node. Activation data is used to activate the deactivated data and function. The activation data is shared between stages of the issuing processing with the use of a data management system.

This invention relates to a communication technique using sensor nodes. In particular, the invention relates to a technique of sharing confidential data and functions between a sensor node and a router, as well as protecting data in the sensor node.
Sensor nets in which many sensor nodes are connected through short-distance wireless communications have gained popularity in recent years. Using wireless communications to broadcast data, sensor nets contain such security risks as interception, tampering, and impersonation. Also, sensor nodes in sensor nets are often placed in unmanned sites, which gives rise to another set of problems including theft of data from a sensor node by physical means.
"Security Services Specification Revision 13, Version 1.00" (ZigBee Alliance, Dec. 14, 2004) proposes to use confidential data such as encryption keys given to sensor nodes in protecting wireless communications between sensor nodes against security risks.
In JP 2003-87242 A, JP 2004-318881 A, and JP 2004-241976 A, protection against security risks is accomplished by loading of confidential data and sensor node authentication performed by routers with the use of the confidential data.

Method for protection of sensor node's data, a systems for secure transportation of a sensor node and a sensor node that achieves these


An image signal processing apparatus and method perform appropriate correction of image blurring in accordance with an image characteristic. In the apparatus, a user interface designates a blurring parameter, and a control signal generating unit generates a control signal corresponding to the designated parameter. An image characteristic detecting unit determines directions in which pixels in an input image have flat levels and directions in which pixels in the input image have levels corresponding to edges. Based on the determination, an address calculating unit reads coefficients from a coefficient ROM and supplies the coefficients to a product-sum calculating unit. The product-sum calculating unit generates a blurring-eliminated image by performing product-sum calculation using the coefficients. A post-processing unit produces an output image based on the input image and the result of product-sum calculation.

1. Field of the Invention
The present invention relates to image signal processing apparatuses and methods, and programs and recording media used therewith, and in particular, to an image signal processing apparatus and method that perform appropriate correction of image blurring in accordance with a characteristic of an image, and a program and recording medium used therewith.
2. Discussion of the Background
In recent years, many digital still cameras each having an automatic focusing function have come into widespread use. The automatic focusing function detects an appropriate focus and performs automatic focusing without user's manual focusing. Although the automatic focusing function enables the user to easily capture images, image capturing may be performed in a state in which, not the original subject whose image to be captured by the user, but the background of the subject is brought into focus. This may consequently cause the image of the original subject to blur.
To correct a picture having a blurred subject image as described above, a technology (see, for example, Japanese Unexamined Patent Application Publication No. 6-68252) in which the image is cleared by performing edge-enhancement sharpening in a blurred portion has been proposed.
In addition, as a method for correcting a picture when considering a blurring model, a technology (see, for example, Japanese Unexamined Patent Application Publication No. 8-272995) in which, when assuming that the pixel levels (observed values) of a captured image are such that the pixel levels (true values) of an image free from blurring are spatially diffused, by writing a model expression between the true values and the observed values and solving the model expression, the true values are estimated from the observed values for image correction.
In the technology disclosed in Japanese Unexamined Patent Application Publication No. 6-68252, a model of blurring caused by shifting in focusing is not considered. Accordingly, information of image details lost due to blurring cannot be reproduced with high fidelity.
In the technology in Japanese Unexamined Patent Application Publication No. 8-272995, the model expression is solved by uniformly setting coefficients concerning portions far from the center of diffusion to be zeroes. When the degree of diffusion is small, the range of diffusion is narrow, and pieces of true-value information concentrates around the center of diffusion. Accordingly, in relation to the uniform setting of the coefficients concerning the portions positioned away from the center of diffusion to be zeroes, no inconsistency occurs. When the degree of blurring is large, even in portions positioned away from the center of diffusion, pieces of true-value information sufficiently exist. Accordingly, by setting the coefficients to be zeroes, inconsistency occurs. In addition, since characteristics of the image are not considered in the case of solving the model expression, in the case of a picture including noise such as JPEG (Joint Photographic Experts Group) noise, there is a possibility that noise may be enhanced to result in deterioration in image. This causes a problem of an inability to appropriately correct the image.

Image signal processing apparatus and method, and program and recording medium used therewith


A process for producing a frozen confectionery product is provided, the process comprising: supplying a frozen confection to a nozzle which has an orifice having a non-circular cross-section; dispensing a filling comprising sauce and/or inclusions into the frozen confection inside the nozzle; extruding the frozen confection and filling from the nozzle through the orifice until the extruded frozen confection makes contact with a receiving surface; wherein the longest axis of the product is parallel to the direction of extrusion; and then cutting the extruded frozen confection with an iris cutter.

Stick products are one example of an individual frozen confectionery product that has been known for many years. They are usually produced by an "extrude and cut" process, as follows. Ice cream from the freezer is extruded vertically downwards though a nozzle onto a conveyor. Sticks are inserted as the ice cream comes out of the nozzle and a heated wire cuts it horizontally into uniform portions of the required thickness. Consumers have come to expect that ice cream stick products generally have a certain shape, typically 70-100 mm long×30-60 mm wide×15-35 mm thick with rounded corners and/or edges. This shape is produced by extruding ice cream through an orifice which has the required cross-sectional shape (the cross-section contains the two longest axes of the product).
There is a continual need to provide new and improved products in order to maintain consumers' interest. Whereas in the past products often simply consisted of ice cream with a coating such as chocolate, there is now a demand for more exciting and indulgent products, for example products wherein sauce and/or inclusions are located within the ice cream. Such products can be produced by co-extrusion of ice cream and sauce/inclusions. However, the standard "extrude and cut" process is unsatisfactory when the ice cream contains significant amounts of sauce and/or inclusions. This is because the wire cutter can hit an inclusion during the cutting step. This can cause the inclusion to be dragged by the cutter to the edge of the frozen confection resulting in deformation of the frozen confection and an uneven surface. Moreover, sauce can leak out from the ice cream at the cut surface, and stick to the conveyor or cold plate onto which it lands. Also, the cutter can be damaged by repeated contacts with hard inclusion particles, in particular if they are large in size.
WO 2010/043493 discloses a process which addresses the problem of encapsulating sauce and/or inclusions. The frozen confection is co-extruded with a filling and then cut with an iris cutter. The cross-sectional shape of the extrudate is typically circular, and the resulting product is typically approximately spherical or cylindrical. However, while this process works well for producing products in the shape of balls or rounded bars, we have found that difficulties arise in producing other products, in particular stick products having the expected shape. The iris cutter forms a peak on the cut surface, which should be flat to match the standard stick product shape. Furthermore, having an orifice with a non-circular cross-section can result in the extrudate being twisted by the blades of the iris cutter during cutting. This has the effect that when the cut extrudate lands on a receiving surface beneath the iris cutter (typically a conveyor belt), it does not land on one of its large flat surfaces. This in turn can result in misshapen products and may also cause problems for subsequent handling of the product, for example when a stick is inserted.
Therefore there remains a need for an improved method for producing stick products having the desired shape and containing a fully encapsulated filling of sauces and/or inclusions.

Process for producing frozen confectionery products


A method of forming a sufficiently thin, highly amorphous and homogeneous glass-like carbon film on the surface of a titanium metal with high efficiency. In this method, the surface of a titanium metal is polished by e.g. buffing with emery paper and alumina or chromium suspension as polishing agents to form a mirror surface. A dense and rigid titanium oxide film layer is formed on the mirror surface. The surface of the titanium oxide film is then subjected to plasma heating in an atmosphere containing a hydrocarbon gas under a gas pressure of 0.1-30 Torr at 400-1100.degree. C. to form a glass-like carbon film thereon.

This invention relates to a method of forming a coating of glass-like carbon on titanium metal.
Titanium metal is heat-resistant and high in specific strength. In the air, an oxide film is formed on its surface, making titanium metal corrosion-resistant. Pure titanium can be alloyed with any metal, especially copper, tin, iron, aluminum, vanadium, chromium, cobalt, molybdenum and nickel. By alloying, it is possible to improve its workability, mechanical strength and other properties.
Titanium metals, i.e. pure titanium and titanium alloys are active metals, so that their surfaces are oxidized soon in the air, forming a film of titanium oxide thereon. Protected by such titanium oxide films, the titanium metals show high corrosion resistance even under corrosive environments. Thus, titanium oxide films formed on titanium metals are called passivated films.
The present inventors developed a material useful as sliding members and tightening members such as bolts and nuts obtained by cleaning the surface of a titanium metal to remove an oxide film, followed by carburizing to reduce friction and wear coefficients. A method for manufacturing such a material is disclosed in unexamined Japanese patent publication 7-90542.
Glass-like carbon is a nondirectional aggregation of hexagonal structure with a side of several nanometers, which are basic units of a graphite material. It is a kind of carbon having a nearly amorphous structure with its graphite units never growing even when heated to around 3000.degree. C. (hard-to-graphitize carbon). Such highly amorphous glass-like carbon has various industrially desirable properties including high corrosion resistance, wear resistance, lubricity (low friction coefficient), releasability, and gas impermeability.
In a conventional method for forming a glass-like carbon article, a thermosetting resin such as phenol is molded into a desired shape, polymerized, thermally set, machined, and heated very slowly while strictly controlling temperature for carbonization.
It would be possible to form a glass-like carbon film on the surface of a metal using this conventional method, i.e. by forming a thermosetting resin coating on the metal surface and heating it for a long time while controlling the temperature.
But with this method, it is difficult to form a homogeneous glass-like carbon film on the surface of a titanium metal due to the formation of a layer in which substrate metal and glass-like carbon are mixed together or the formation of a carbide of substrate metal. It is also difficult to form a sufficiently thin glass-like carbon film on the metal surface with high efficiency.
An object of this invention is to form a highly amorphous and homogeneous glass-like carbon film on the surface of a titanium metal with high efficiency and desired thinness.
Another object is to provide a method of forming a coating of glass-like carbon on a titanium metal article with high efficiency to improve the corrosion resistance, wear resistance (friction coefficient), releasability, gas impermeability and bio-affinity of titanium metal, thereby providing a surface treatment method that can increase the industrial value of titanium metals.

Method of forming a coating of glass-like carbon on titanium metal


A cooking appliance includes a controller which calculates a desired percentage of hot air convection and microwave energy needed to perform a cooking operation based on selections made by a user through a menu driven display. The display prompts a user for a programming inputs, while also displaying operational information to the user as needed. The programming options enable the user to select between various different cooking operations and also provides for appealing cooking sequences to be stored as cooking recipes. As needed, certain pre-cooking functions are automatically performed, such as heating or cooling of the oven cavity, as needed.

1. Field of the Invention
The present invention pertains to the art of cooking appliances and, more particularly, to a menu driven electronic interface system used in controlling the operation of a cooking appliance.
2. Discussion of the Prior Art
Cooking appliances have evolved in the fairly recent past to incorporate electronic controls. In fact, many ovens, ranges and the like available on the market today incorporate, to certain degrees, programmable features intended to aid a consumer in performing cooking operations. Actually, most electronic control systems for cooking appliances only enable a consumer to input certain cooking information, such as cooking modes, times and temperatures, with the inputted information generally being presented in a viewable display area and used to establish a cooking operation.
With the introduction of the microwave oven, additional electronic programming features became available. For instance, some microwave ovens available in the marketplace provide for the user input of a desired cooking or defrosting operation which can be carried out based on information concerning the category of food, e.g., meats, leftovers, canned goods, frozen dinners etc. When cooking meat in such known appliances, the approximate weight of the meat is also a common input parameter. With this information, the appliance performs a programmed cooking operation.
In any event, there have been developments in the art of cooking appliances directed to aiding a consumer in performing certain cooking operations effectively. However, there still exists a need for a more user friendly system for controlling the operation of a cooking appliance. More specifically, there exists a need for an electronic control system which functions to prompt a user, as needed, to input certain cooking information in a convenient and clear manner, and then automatically controls the cooking appliance to perform the desired operation. Furthermore, there is a need for an electronic cooking appliance control system which can itself be programmed to perform various operations in a desired manner, such as following a personal recipe stored in the system by the user.
The present invention pertains to a system for programming and operating a cooking appliance, preferably a cooking appliance which calculates a desired percentage of hot air convection and microwave energy need to perform a cooking operation in an efficient manner, based on selections made by a user. Most preferably, a menu driven display, such as a touch screen, is used to prompt a user for programming inputs, ranging from the type of cooking to be performed, relevant food groups, times, temperatures and the like. In addition to prompting the user for necessary programming information, the cooking appliance can pause the programming sequence to automatically perform preheating or cooling functions for the oven cavity as needed, preferably while displaying a control screen to the user concerning the function being performed.
Following the completion of a cooking operation performed based on the programming input by the user, the user can still provide for additional cooking to satisfy personal preferences. In addition, a favorite cooking sequence can be selectively saved as a recipe to be followed in subsequent cooking operations. Most preferably, the recipes are saved in an alpha format. In addition, pre-stored recipes can be executed as well.
Additional objects, features and advantages of the present invention will become more readily apparent from the following detailed description of a preferred embodiment thereof when taken in conjunction with the drawings wherein like reference numerals refer to corresponding parts in the several view.

Menu driven control system for a cooking appliance


A method and a device for determining wheel slip information of an electrically driven wheel of a motor vehicle, according to which during travel, the speed (nE-motor) of an electric motor driving the wheel is detected and the detected speed (nE-motor) of the electric motor is used to determine the wheel slip information.

To ensure vehicle stability or steerability of a motor vehicle even on slippery surfaces, information regarding the slip on the wheel is necessary. Today's ABS/ESC systems use wheel speed information to ascertain which wheel is slipping and by how much.
Currently, if one or more wheel speed sensors fail, this is indicated to the driver (warning by ABS/ESC light) and the driver is responsible for safely driving or parking the vehicle. In terms of the functioning of piloted or (partially) autonomous driving in particular, this would have the consequence that the piloted or (partially) autonomous driving function would have to be deactivated for a short time, because the lack of information about the wheel slip could place the vehicle in a safety-critical driving situation that can no longer be mastered by the system.

Method and device for determining wheel slip information of an electrically driven wheel of a motor vehicle


A knowledge-based driver is provided for powering a solid-state light source with a constant current, including a memory that stores lumens per amp and volts per amp performance characterizations of the light source over time, and a controller that operates in a test mode to estimate the light source degradation based on voltage feedback obtained at a predetermined test current value, and to adjust the drive current in normal operating mode according to the estimated device degradation to implement constant lumens control without external optical feedback components.

The disclosed embodiments relate to solid-state light source drivers and driver controls for maintaining constant lumen output and end-of-life (EOL) adaptation. Lighting devices are employed in a variety of applications for illuminating buildings, roads, and in other area lighting applications, as well as in a variety of signage and optical display applications. These applications are generally driven by a need for controlled illumination levels that may vary according to customer adaptation of dimming levels and the like. Many solid-state light sources suffer from lumen output depreciation, where the illumination provided by the device diminishes over time, even if driven at a constant current level. These devices also suffer degraded performance as the light source nears its end-of-life. Previous techniques for addressing these problems include direct optical feedback using a photosensor to detect the light output of the device, with closed-loop controls modifying the drive current to attempt to maintain a constant lumen output. However, such optical feedback systems increase the package size and add cost to the system, and the mechanical location of the optical sensor is critical to provide accurate light output measurement while avoiding stray light and other ancillary problems. Thus, there remains a need for improved solid-state light source drivers and driver controls for maintaining constant lumen output and end-of-life (EOL) adaptation.

Knowledge-based driver apparatus for high lumen maintenance and end-of-life adaptation


A base of a metallurgical vessel having a direct-current arc device whose cathode projects into the vessel and in whose fire-resistant lining on the base at least one anode is arranged, one end of which, passing through the vessel wall, touches metallic melt located in the vessel, and the other end of which can be connected to cooling fluid supply sources and is attached in an electrically insulated manner to the vessel wall via holding elements. A sleeve is provided which does not conduct electric current, sheaths that part of the anode which projects into the metallurgical vessel and, in the process of forming an outlet channel, is arranged at a distance sufficiently far away from the anode that low-melting-point metals, mainly lead, can flow out of the vessel without being impeded.

This is a U.S. national stage of application No. PCT/DE99/00631, filed on Mar. 3, 1999. Priority is claimed on that application and on the following application:
Country: Germany, Application No.: 198 15 154.3, Filed: Mar. 27, 1998.
1. Field of the Invention
The invention relates to a base of a metallurgical vessel having a direct-current arc device whose cathode projects into the vessel and in whose fire-resistant lining on the base at least one anode is arranged, one end of which, passing through the vessel wall, touches metallic melt located in the vessel, and the other end of which can be connected to cooling fluid supply sources and is attached in an electrically insulated manner to the vessel wall via holding elements.
2. Discussion of the Prior Art
DE 40 26 897 A1 discloses a metallurgical vessel having a vessel base which has a fire-resistant lining in which the base electrode of a direct-current arc furnace is arranged. A holding device is detachably attached to the casing of the vessel, isolated by insulation. The holding device in this case comprises a flanged tube which is arranged coaxially with respect to the electrode center and can be screwed to the metallurgical vessel.
The electrode, which passes through the furnace wall, makes contact with the melt located in the vessel. During operation, the head area of the electrode is melted. Since this is the lowest point in the furnace vessel, at which the melt is located, the thinner liquid and heavier melt components also gather here. Defects in the fire-resistant material can lead to connections of the liquid thread between the electrode and the metal casing of the vessel. This causes damage or destruction to the furnace vessel in the region of the base electrode, due to electrical flashovers.
The invention is based on the aim of providing a base of a metallurgical vessel having a direct-current arc device, in which the occurrence of electrical flashovers in the vessel base is prevented by simple design means.
According to the invention, the passage of the anode through the metallic base of the furnace vessel is designed as an outlet channel. For this purpose, a sleeve is provided which sheaths that part of the anode which projects into the vessel and in the process is placed at a distance sufficiently far away from the anode that low melting-point metals can flow out of the vessel without being impeded. The sleeve is in this case formed from a material which does not conduct electric current, preferably from ceramic.
The head of the sleeve, which faces the vessel interior, is designed as a collecting screen, and in this case has a conically diverging shape. In one advantageous refinement, the sleeve comprises at least two parts, with the first part having a cylindrical shape and the second part having a conically opening funnel shape away from a separation point in the direction of the vessel interior.
In a further advantageous embodiment, a sleeve which is composed of a fire-resistant ramming mass and extends in an extension of the funnel-shaped second part of the sleeve is provided in the fire-resistant lining. The sleeve formed from the ramming mass in this case provides the function of drainage and ensures that all the thin-liquid metal is passed to the sleeve even when the wear of the anode is relatively severe.
The distance xcex94r of the outlet channel between the anode and the tubular holding element of the anode and the sleeve is 0.5 to 2 mm. This distance is sufficient to prevent the normal melt from flowing out of the vessel base.
A collecting apparatus is arranged underneath the base, in order to collect the thin-liquid metal, such as lead, flowing out via the outlet channel.
In one particularly simple construction in design terms, the anode is held by a clamping ring which is separated via insulation and is arranged underneath the furnace base. The insulation is held in a positively locking manner as a simple ring by the furnace base and, in the process, is at a distance from the anode forming an outlet channel.

Bottom for a metallurgical vessel with a direct current electric arc device


The band-pass filter has first terminals, second terminals, a first decoupled stacked bulk acoustic resonator (DSBAR), a second DSBAR, and an electrical circuit connecting the first DSBAR and the second DSBAR in series between the first terminals and the second terminals. Each DSBAR has a first film bulk acoustic resonator (FBAR), a second FBAR and an acoustic decoupler between the FBARs. Each FBAR has opposed planar electrodes and a piezoelectric element between the electrodes.

Band-pass filters are used in an ever-widening variety of electronic products, especially wireless products. An ideal band-pass filter provides little or no attenuation of signals at frequencies in the pass band, has a flat frequency response in the pass band, and provides a large attenuation of signals at frequencies outside the pass-band. Additionally, in an ideal band-pass filter, the slope of the transition between the pass band and the stop band is steep.
Band-pass filters that incorporate one or more film bulk acoustic resonators (FBARs) have characteristics that approximate the above-described ideal characteristics yet are small in size and are relatively inexpensive. For example, modern cellular telephones incorporate a duplexer composed of two band-pass filters. Each of the band-pass filters includes a ladder circuit in which each element of the ladder circuit is an FBAR. A duplexer incorporating FBARs is disclosed by Bradley et al. in U. S. Pat. No. 6,262,637 entitled Duplexer Incorporating Thin-film Bulk Acoustic Resonators (FBARs), assigned to the assignee of this disclosure and incorporated by reference. Such duplexer is composed of a transmitter band-pass filter connected between the output of the transmitter and the antenna and a receiver band-pass filter and a 90° phase-shifter connected in series between the antenna and the input of the receiver. The center frequencies of the pass-bands of the transmitter band-pass filter and the receiver band-pass filter are offset from one another. Band-pass filters incorporating ladder filters based on FBARs are also used in other applications.
FIG. 1 shows an exemplary embodiment of an FBAR-based band-pass filter 10 suitable for use as the transmitter band-pass filter of a duplexer. The transmitter band-pass filter is composed of series FBARs 12 and shunt FBARs 14 connected in a ladder circuit. Series FBARs 12 have a higher resonant frequency than shunt FBARs 14. FBAR-based ladder filters are widely used in the duplexers of CDMA mobile telephones where their small physical size, large power handling capability, low cost, low insertion loss and frequency response characteristics are advantageous.
FIG. 2 is a graph showing the frequency response of FBAR-based band-pass filter 10. The frequency response exhibits a flat response in the pass band and an initial steep fall in the response in the transition between the pass band and the stop band. However, the characteristics of the band-pass filter 10 deviate from the above-described ideal characteristics because, after the initial fall, the subsequent rise in the frequency response in the stop band may result in insufficient stop band attenuation for some applications.
FIG. 3 shows an exemplary embodiment 30 of an FBAR. FBAR 30 is composed a pair of electrodes 32 and 34 and a piezoelectric element 36 between the electrodes. FIG. 3 also shows a substrate 40 that supports FBAR 30 in a way that mechanically decouples the FBAR from the substrate. Mechanically decoupling FBAR 30 from substrate 40 allows the FBAR to resonate mechanically in response to an electrical signal applied between electrodes 32 and 34. In the example shown, FBAR 30 is mechanically decoupled from substrate 40 by suspending the FBAR over a cavity 42 defined in the substrate. Other ways of mechanically decoupling the FBAR from the substrate are known.
FIG. 4 shows an exemplary embodiment 50 of a band-pass filter that incorporates a decoupled stacked bulk acoustic resonator (DSBAR) as described in above-mentioned U.S. patent application Ser. No. 10/699,289 and above-mentioned U.S. patent application Ser. No. 10/965,541. Band-pass filter 50 is based on a DSBAR 52 composed of a lower FBAR 54, an upper FBAR 56 stacked on lower FBAR 54 and an acoustic decoupler 58 between the FBARs. Each of the FBARs is similar in structure to FBAR 30 described above with reference to FIG. 3. DSBAR 52 is shown suspended over cavity 42 in substrate 40 in a manner similar to that described above. When an electrical input signal is applied between the electrodes of lower FBAR 54, upper FBAR 56 provides a band-pass filtered electrical output signal between its electrodes. The pass bandwidth of band-pass filter 50 is determined by the coupling of acoustic energy between lower FBAR 54 and upper FBAR 56. The coupling is controlled by acoustic decoupler 58. The electrical input signal may alternatively be applied between the electrodes of the upper FBAR, in which case, the electrical output signal is taken from the electrodes of the lower FBAR.
FIG. 5 is a graph showing the frequency response of DSBAR-based band-pass filter 50. The frequency response exhibits a flat response in the pass-band and a fall in the response at frequencies above and below the pass band. However, the characteristics of the DSBAR-based band-pass filter deviate from the above-described ideal characteristics in that the transition between the pass band and the stop band is less steep than some applications require. The response falls less steeply than the initial fall in the response shown in FIG. 2 of the FBAR-based ladder filter described above with reference to FIG. 1.
Accordingly, what is needed is a band-pass filter whose characteristics more closely approximate the above-described ideal characteristics. In particular, what is needed is a band-pass filter having the advantages of the above-described band-pass filters but whose frequency response in the transition between the pass band and the stop band falls more steeply than that of DSBAR-based band-pass filter 50 and that provides a greater attenuation in the stop band than FBAR-based band-pass filter 10.

Decoupled stacked bulk acoustic resonator-based band-pass filter

Avago Technologies Wireless IP (Singapore) Pte. Ltd.


A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks. Each of the plurality of reception blocks receives an input signal among the input signals and the strobe signal, and controls a phase of any one of the input signal and the strobe signal.

1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a semiconductor apparatus which controls the phases of signals transmitted.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of memory chips are stacked and packaged, has been developed. In the 3D semiconductor apparatus, since two or more memory chips are vertically stacked, a maximum degree of integration may be achieved in the same area.
Various methods may be applied to realize the 3D semiconductor apparatus. In one of the methods, a plurality of memory chips having the same structure are stacked and are then electrically coupled with one another using wires such as metal lines to operate as one semiconductor apparatus.
Recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which through-silicon vias are formed to pass through a plurality of stacked memory chips so that all the memory chips are electrically coupled with one another. In the TSV type semiconductor apparatus, because the through-silicon vias vertically pass through the respective memory chips to electrically couple them with one another, the area of a package may be efficiently reduced when compared to a semiconductor apparatus in which respective memory chips are electrically coupled with one another through peripheral wiring using wires.
Respective memory chips may receive a data signal, a command signal and various control signals. Signals to be transmitted may need to be controlled in their phases due to various factors. For example, since a signal to be transmitted through a long distance from a transmission unit to a reception unit may be received by being delayed more than a signal to be transmitted through a short distance, the phase of the signal with the long transmission distance may be controlled. For another example, since a signal may be received by being delayed due to a variation in process, voltage or temperature, the phase of the signal may be controlled.

Semiconductor apparatus for controlling phase difference between input signal and strobe signal


In a semiconductor device, rewirings 3 for connecting a semiconductor chip 1a, a semiconductor chip 1b and external connecting terminals 4 with each other are formed on the semiconductor chip 1a. An insulating resin 6 having opening portions in regions for forming the external connecting terminals 4 at peripheral portion of the semiconductor chip 1a and another opening portions in another region for mounting the semiconductor chip 1b at the central of the semiconductor chip 1a is overlaid on the rewirings 3. The external connecting terminals 4 consisting of BGA are formed in the opening portions of the regions for forming the external connecting terminals 4 through lands 5. The semiconductor chip 1b is connected to another opening portions of another region for mounting the semiconductor chip 1b by flip-chip structure through electrodes 11 and bumps 8. A junction surface of the bumps 8 is sealed by a sealing resin 7. The semiconductor chip 1b is mounted on the same surface as that the external connecting terminals 4 are formed. The under surface of the semiconductor chip 1b is ground in order that the semiconductor chip 1b may be shorter than the external connecting terminals 4. The semiconductor chip 1b is thereby mounted with high density.

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, in particular to the semiconductor device and the method of manufacturing the semiconductor device in which a plurality of semiconductor chips are stacked with high density.
As regards mounting of a semiconductor package and a semiconductor chip, it is important that the semiconductor package and the semiconductor chip are mounted in small area and capacity, but with high density, and at a low cost. For this purpose, semiconductor chips are progressively miniaturized, and Multi-Chip Module (hereunder called "MCM") method, as will later be described more in detail, is used as a method of mounting those semiconductor chips. In the MCM method, a plurality of semiconductor chips are mounted on a ceramic wiring substrate, silicon wiring substrate, and a printed wiring substrate by wire bonding or flip-chip mounting. Moreover, Multi-Chip Package (MCP) method is used as another conventional method of mounting a plurality of semiconductor chips, also as will later be described more in detail. In the MCP method, a plurality of semiconductor chips having different sizes from each other are stacked three-dimensionally and electrically connected to each other by wire bonding.
It is difficult for some different function devices, of which manufacturing processes are different from each other, to be integrated in a semiconductor chip, because of cost and technical problems. A package capable of compositing different function devices into a system, such as MCM, MCP or the like is used therefor. However, the package such as MCM or MCP has, for example, the following problems.
Namely, it becomes difficult to make the MCM package small in size and with high density. Further, manufacturing cost of the MCM package becomes high. Further, delay of electric signals is inevitably caused to occur, since wiring length becomes long in the MCM package. It is therefore difficult to obtain a desirable characteristic of high-speed operation.
On the other hand, the MCP package becomes large in thickness. As a result, the MCP package is not always suitable to be manufactured with high density. In addition, total bonding wires become so long. As a result, delay of operation speed is inevitably caused to occur due to parasitic capacitance or wiring resistance.

Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same


In an embodiment, a method provides for receiving commands within a mobile communications application running on a mobile communication device. The method includes monitoring text entered into a text input region of a touchscreen keyboard module within a user interface on the mobile communication device for an interrupt code, and detecting an interrupt code. The method also includes determining a command from a plurality of commands, based on user inputs following the interrupt code, identifying an action from a plurality of actions corresponding to the plurality of commands, and initiating the action corresponding to the command.

Mobile communication devices allow users to communicate with each other using a wide variety of different communication modes, such as email, text, speech, video, or the like. Typically a user has at least one mobile communication application for each of these different communication modes.
When a user wishes to switch communication modes or applications, typically the user must first exit whatever application they are currently using, find the icon or command for the application providing their desired communication mode, and execute that application.
Overview
Embodiments disclosed herein provide systems and methods for receiving commands within a mobile communications application running on a mobile communication device. In an embodiment, a method provides for receiving commands within a mobile communications application running on a mobile communication device. The method includes monitoring text entered into a text input region of a touchscreen keyboard module within a user interface on the mobile communication device for an interrupt code, and detecting an interrupt code. The method also includes determining a command from a plurality of commands, based on user inputs following the interrupt code, identifying an action from a plurality of actions corresponding to the plurality of commands, and initiating the action corresponding to the command.
In another embodiment, one or more non-transitory computer readable storage media having program instructions stored thereon for receiving commands within a mobile communications application running on a mobile communication device is provided. When executed by a computing system, the program instructions direct the computing system to at least monitor text entered into a text input region of a touchscreen keyboard module within a user interface on the mobile communication device for an interrupt code, and to detect an interrupt code.
The program instructions also direct the computing system to determine a command from a plurality of commands, based on user inputs following the interrupt code, to identify an action from a plurality of actions corresponding to the plurality of commands, and to initiate the action corresponding to the command.
In another embodiment a mobile communication device configured for receiving commands within a mobile communications application is provided. The device includes a memory configured to store an action database comprising a plurality of commands and a plurality of actions corresponding to the plurality of commands, and a processor coupled with the memory. The processor is configured to monitor text entered into a text input region of a touchscreen keyboard module within a user interface on the mobile communication device for an interrupt code, and to detect an interrupt code.
The processor is also configured to determine a command from the plurality of commands corresponding to the one or more interrupt codes stored within the interrupt code database, based on user inputs following the interrupt code, to identify an action from the plurality of actions corresponding to the plurality of commands stored within the action database, and to initiate the action corresponding to the command.

Systems, methods, and software for receiving commands within a mobile communications application