A power line communication (PLC) apparatus wherein transmission mode information is encoded into each data packet while maintaining immunity from single bit errors. In the present invention, a power line communication system includes a transmitter/receiver (i.e. transceiver) which is coupled to a power distribution network. Data is transmitted through the power line by the transceiver in packets. The transceiver includes a preamble generator which creates a preamble for each of the data packets and a preamble decoder that decodes the preamble of a data packet and determines word sync for the packet. The preamble generated by the preamble generator consists of a carrier detect interval, a carrier sync interval, a bit sync interval, and a word sync pattern. The transceiver may select either BPSK or QPSK transmission modes on a data packet by data packet basis by encoding information into the packet preamble. Transmission mode information is encoded into the preamble using one of two seven-bit cross compatible word sync patterns for each data packet. Thus, one word sync pattern is used to define a BPSK transmission while the other word sync pattern is used to define a QPSK transmission. The transmitter may send data packets using either BPSK or QPSK on a packet by packet basis by generating the appropriate word sync pattern for each packet. The receiver uses the word sync pattern to determine the receive mode for each packet.

Prior art data communications systems use a variety of methods for coding data into an analog medium. Such well known methods include amplitude modulation, frequency modulation and phase modulation. Two forms of phase modulation are commonly used: BPSK (Binary Phase Shift Keyed) and QPSK (Quadrature Phase Shift Keyed). In a BPSK system, there are two phases: an in-phase signal and a 180.degree. out of phase signal. During each baud (i.e. digital symbol transmission cycle), the transmitter sends one of the two signals. The phase sent determines the value of the bit transmitted (zero or one). A single binary bit per baud is conveyed from transmitter to receiver during each baud time in a BPSK system.
In a QPSK system, there are four phases: an in-phase signal, a 180.degree. out of phase signal, a +90.degree. phase signal, and a -90.degree. phase signal. During each baud, the transmitter sends one of four baud signals. The phase sent determines the value of each of two transmitter bits. Two binary bits per baud are thus conveyed from transmitter to receiver during each baud time.
Both BPSK and QPSK systems have a distinct set of characteristics that make one form of coding better in some circumstances while the other method is better for other situations. QPSK has the advantage of getting more data into less bandwidth. At the same time, separation between phases in a QPSK system is half that of BPSK phases (phases are only 90 degrees apart in QPSK instead of 180 degrees for BPSK). Thus, some noise immunity is lost in QPSK. If there is any kind of impairment on a communication channel which could modulate the phase of the carrier, BPSK would be more reliable than QPSK. Therefore, QPSK is more efficient in getting more data into a limited bandwidth while BPSK is more robust.
BPSK and QPSK phase modulation techniques may be employed in a variety of adverse communication environments. One such adverse environment is a power distribution network. Although a power line may be used as a data communication medium, the level of noise present on the power line makes effective communication very difficult. A typical AC power line network is used for power distribution to a number of electric devices connected thereto. Such devices cover a wide range of applications including hair dryers, television sets, computers and specialized factory tooling. Each type of device conducts a significant level of noise back onto the power lines. Different devices produce a different type and degree of noise. This diverse power line noise problem severely impairs the efficient and reliable operation of any power line communication system.
Another problem hindering any power line communication system is signal attenuation. Due in part to the diverse impedance levels of the electric devices being used with a power line network, transmitted communication signals may suffer greater than 40 dB attenuation before being captured by a receiver. The significant signal attenuation problem in combination with the noise problem renders effective signal line communication difficult.
Time varying conditions on a typical AC power line have been observed to cause sudden, periodic shifts in the carrier phase of received data communication signals. Phase shifts up to 45 degrees in the carrier frequency range of 50 KHz to 150 KHz are relatively common. In the carrier frequency range of 100 KHz to 150 KHz, a phase modulation of 22 degrees is relatively common, while 45 degree shifts occur only when certain electrical devices are powered on. These phase shifts severely impair the capability of any QPSK receiver during the time the interference is present. At other times, for example when certain electrical devices which produce large phase variation are powered off, power line interference is reduced to a level at which QPSK operation is not a reliability risk. It will be apparent to those skilled in the art that other adverse data communication environments other than power line distribution networks present impairments to the faster QPSK method.
It is therefore desirable to support both BPSK (for robustness) and QPSK (for speed) modes in a single data communication system. The QPSK mode can be enabled when low levels of interference allow fast transmission; BPSK mode may be enabled when greater reliability is necessary in a noisy environment. It is also desirable to provide a means for switching between BPSK and QPSK modes that is tolerant of bit errors occurring during transmission of the mode information.

Transmission mode detection in a modulated communication system


A method and apparatus are provided for selecting an optimal communication path between an IB computer and a non-IB computer. All gateways that join the network multicast their presence on the network. The data associated with the multicast transmission are retained by each member of the network in the associated cache. The retained multicast data is leveraged to select an optimal transmission protocol between the host and target computers, and a gateway configured to support the selected transmission protocol.

1. Technical Field
This invention relates to selecting an optimal communication path over a computer network. More specifically, the invention relates to a computer network configured with a computer operating in an InfiniBand network and a computer operating in a non-InfiniBand network, and a set of protocols to determine an optimal gateway for transmitting messages between the computers.
2. Description of the Prior Art
Input/Output (I/O) networks, such as system buses, are used by a processor to communicate with peripherals, such as network adapters. However, constraints in the architectures of common I/O networks, such as the Peripheral Component Interface (PCI) bus, limit the overall performance of computers. As a result, new types of I/O networks have been introduced.
One type of I/O network is known and referred to as the InfiniBand network, hereinafter IB. InfiniBand is an I/O architecture and specification for transmission of data between processors and I/O devices. Instead of sending data in parallel, which is the structure for sending data in PCI, IB send data in serial and can carry multiple channels of data at the same time in a multiplexing signal. The IB network replaces the PCI or other bus currently found in computers with a packet-switched network, complete with zero or more routers. FIG. 1 is a prior art block diagram (100) of a system area network based on the IB architecture. The IB network is broken up into separate autonomous management units, each containing multiple IB nodes, called subnets. As shown, there are six nodes, node0 (102), node1 (104), node2 (106), node3 (108), node4 (110), and node5 (112) interconnected by a fabric (120) consisting of three switches, switch0 (122), switch1 (124), and switch2 (126). Each node connects to the fabric (120) through a channel adapter. The IB specification classifies the channel adapters into two categories, host channel adapters (HCA) and target channel adapters (TCA). The HCA is an interface that is used to integrate the IB with the operating system. The TCA is present on I/O devices, such as a RAID subsystem. As shown in FIG. 1, node2 (106), node3 (108), and node5 (112) represent peripherals and include TCAs (136), (138), and (142), respectively. Similarly, node0 (102), node1 (104), and node4 (110) represent operating systems and include HCAs (132), (134), and (140), respectively. Furthermore, in the example shown herein, each channel adapter may have one or more ports. A channel adapter with more than one port may be connected to multiple switch ports. For example, channel adapter (140) has at least two ports, with a first port connected to switch0 (122) and a second port connected to switch1 (124). Accordingly, as shown multiple paths between a source and a destination are available in the IB architecture, resulting in performance and reliability benefits.
IB components are assigned a global identifier (GID) during initialization. The GID is used to uniquely identify the target component both within and across IB subnets. A router may be provided to interconnect two or more subnets to form a larger system area network. IB Routers, like IB switches, forward packets between their ports. The difference between routers and switches is that a router is used to interconnect two or more subnets to form a larger multi-domain system area network. Within a subnet, each port is assigned a unique identifier called the local identifier (LID). Switches make use of the LIDs for routing packets from the source to the destination, whereas routers make use of the GIDs for routing packets across domains.
In order for an application to communicate with another application over the IB architecture, it must first create a work queue that consists of a queue pair, which is a pair of queues—one queue for send requests and one queue for receive requests. In order for the application to execute an operation it must place a work queue element (WQE) in the work queue. Thereafter, the operation is picked up for execution by the channel adapter. Accordingly, the work queue forms the communication medium between applications and the channel adapter.
By having multiple paths available for transmitting data between nodes, the fabric is able to achieve transfer rates at the full capacity of the communication channel, avoiding congestion issues that may arise in shared bus architecture.
Remote direct memory access (RDMA) is a communications technique used in IB that allows data to be transmitted from the memory of one computer to the memory of another computer without passing through either device's CPU, without needing extensive buffering, and without calling to an operating system kernel. Through RDMA, data can be transferred faster since it does not have to pass through the CPU. Although RDMA is supported in the IB architecture, it is not universally supported across all networks. There are circumstances where a computer on a non-IB network is in communication with a computer on an IB network and data transfer and communication between the two computers is warranted. Such communication utilizes gateways between the IB and non-IB network to transfer data packets between the two networks. A gateway is a node that serves as an entrance to another network. It is known in the art that a gateway can support RDMA data transfer between an IB network and a non-IB network. However, the prior art solutions available for determining an optimal path for data transfer in such a circumstance are complex and costly. Accordingly, there is a need for a solution that efficiently determines an optimal communication path and data transfer technique between an RDMA configured gateway and a generic gateway, such as IPoIB, that are in communication with the IB network.

Communication paths from an InfiniBand host

International Business Machines Corporation


Methods and compositions are provided for detection of analytes, such as cell surface moieties, preferably in multiplexed assays, such that multiple analytes can be assayed simultaneously. The methods employ analyte binding agents which are linked to oligonucleotide labels, which labels are then used for formation of cleavage structures and generation of detectable molecular tags. Preferably, multiple tags are generated per analyte binding event.

Biochemical species targeted in therapy or diagnosis frequently include cell surface antigens, which, upon recognition by natural or synthetic binding molecules, trigger a network of signal transduction and gene regulation events inside the cell that result in cellular responses important in the initiation or maintenance of a disease. Target antigens may also differentially reside on the surface of different cells and signify a unique state of physiology or disease progress in the tissue or organ.
Monoclonal antibodies directed against tumor-associated antigens expressed on the tumor cell surface have found application in the immunotherapy of human tumors. The interaction of certain monoclonal antibodies directed against tumor cells with cell surface antigens is well documented. See, e.g., Herlyn et al. (1987), Koprowski et al. (1985), Grob et al. (1985), and Murthy et al. (1987). Monoclonal antibodies targeted to the epidermal growth factor receptor (EGFR) are of great interest, due to the high level of expression of this receptor in patients with solid tumors. MAB have also been developed which target molecules implicated in other diseases, such as autoimmune diseases, AIDS, asthma, psoraisis, and other inflammatory disorders.
Target-specific binders such as antibodies are also widely employed in detection of such biological markers, particularly in differential assays of markers in different cell or tissue types, e.g. in immunohistochemical assays. Immunohistochemistry (IHC), which broadly includes techniques of screening for target analytes in multiple tissue or cell samples, such as tissue libraries, by application of known binding molecules followed by detection, can be used for detection of the presence or absence of molecular markers, typically proteins, involved in various stages of diseases, such as cancer. Methods have been developed for carrying out such assays on surface antigens in whole cells, as opposed to soluble antigens (see e.g. Bishop & Hwang, 1992; Bator & Reading, 1989). Over the last few years, the role of immunohistochemical analysis has been changing from that of an ancillary diagnostic technique to that of a stand-alone diagnostic method (O'Leary 2001). IHC studies play an increasingly important role in surgical pathology, and can be used, for example, in classifying tumors, predicting the origin of a carcinoma, demonstrating micrometastases and microorganisms, providing prognostic information, or rendering a diagnosis in a damaged specimen (Chan 2000).
In standard IHC assays, markers are generally detected by immunostaining of the specific binding molecules (e.g. antibodies) added to the sample. Consistency of interpretation of staining results, especially from one clinical setting to another, can be problematic. This technique also limits the number of different markers which can be detected simultaneously.
Many receptors are normally expressed on the cell surface to only a small extent, i.e. a few hundred to a few thousand receptors/cell. These include many receptors types of great medical interest, including, for example, receptors for granulocyte-macrophage colony-stimulating factor (GM-CSF), many interleukins, erythropoietin, and tumor necrosis factor (TNF). In addition, assays must often be carried out on tissue samples which are small, rare, unique, or otherwise limited in quantity. Accordingly, there is a need for methods of detecting such markers, often present at low levels, in limited tissue samples, where the method is quantitative, reproducible, and high sensitivity; that is, it gives a readily detectable signal from a small amount of analyte.

Multiplexed immunohistochemical assays using molecular tags


Optimal allocation of a number of sub carriers to applications having diverse QoS requirements and executing on terminal devices (e.g., mobile stations). A base station (BS) considers the QoS requirements and the observed QoS for each of the applications in computing the number of sub carriers allocated to each terminal device in the forward link direction in a given time slot. For allocation in the reverse link direction, the terminal device transmits a first bit indicating whether the aggregate queue lengths (of all applications) exceeds a pre-specified threshold and a second bit indicating whether a delay bound requirement is likely to be violated in the absence of sub carrier allocation. The BS computes the number of sub carriers to be allocated in the reverse link direction based on the respective two bits received from the terminal devices.

1. Field of the Invention
The present invention relates to wireless communications, and more specifically to a method and apparatus for providing optimal allocation of resources in a wireless communication system.
2. Related Art
A wireless communication system may be viewed as containing a wireless network which connects various mobile devices (or, in general, any terminal device). Mobile network represents an example wireless network providing wireless communication between mobile devices. In general, mobile networks contain systems such as base stations which communicate over air with individual mobile devices.
Wireless networks generally operate over an allocated frequency spectrum. The allocated frequency spectrum is divided into a number of sub carriers used for transferring information of interest. In general, a sender (base station or mobile station, depending on the direction) transfers the information to a receiver on one or more of the allocated sub carriers. OFDMA represents a technology which operates according to such an approach, and a base station often allocates the sub carriers to the individual mobile stations (for sending or receiving, in general transferring).
In general, time is logically divided into a number of slots ("time slots"), and a sub carrier may be allocated for a transfer in each time slot. Accordingly, it may be appreciated that the quality of services (QoS) provided to applications depend on respective number of sub carriers allocated in the corresponding time slots. Accordingly, the sub carriers and the time slots may be viewed as resources.
The allocation of resources is of particular importance when multi-media applications are supported in the mobile network and in mobile stations, since different applications require different QoS (hereafter "required QoS"). For example, delay sensitive applications such as VoIP, video conferencing have QoS specifications in terms of delay bound, delay jitter and throughout. Applications such as web browsing (over TCP) have QoS specifications in terms of their average delay and throughout. On the other hand, file transfer (e.g. FTP) applications have QOS specifications in terms of throughout. The QoS requirements can be either qualitative (high/low data throughput) or quantitative (CBR of 128 Kbps), can be user specified or understood from the nature/type of the application.
Accordingly, there is a general need for optimal allocation of sub carriers to devices supporting multimedia application in a wireless communication system or providing different QOS to different applications.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Optimal allocation of resources in a wireless communication system


The present invention discloses a portable digital graphic processing device having the required graphic processing capability by adopting the advanced multi-chip packaging technology and intelligent stick memory card packaging technology to integrate the graphic processing function into an intelligent stick for the portable purpose and integrate a portable device such as a PDA or a smart phone to enhance the digital graphic processing capability of portable devices.

Portable devices generally focus on a light, thin, short, and compact design; such design cannot provide a high-speed processing capability for graphic processing. Unlike personal computers, the graphic processing capability such as the 3D animation for portable devices cannot be enhanced to a high-speed data processing capability for users.
Therefore, the way of overcoming the foregoing shortcomings by providing digital data processing equipments compatible to the existing computer interface to make its application more convenient and comply with user's operating habits is an important subject that deserves our attention.
In view of the description above, the inventor of this invention based on years of experience in the research and development and marketing of related computer products to conduct researches and perform experiments to overcome the foregoing shortcomings, and finally invented the "portable digital graphic processing device" in accordance with the present invention.

Portable digital graphic processing device


A barrier laminate packaging material comprising from its outermost surface to the innermost surface contacting the contents of the container to be prepared therefrom, a first exterior layer of a low density polyethylene polymer, a paperboard substrate, a first interior layer laminate coating of nylon with a tie resin layer, a blown film layer comprising a first low density polyethylene polymer layer, a tie layer, a first interior layer of EVOH, a second tie layer, a second interior layer of EVOH, a third tie layer and a second interior layer of low density polyethylene polymer, and an innermost product contacting layer of low density polyethylene.

The present invention relates to paperboard laminates, and more particularly to a non-foil paperboard laminate useful for making containers for products such as alcoholic beverages, including wine, sake and the like as well as other beverages wherein the laminate has good oxygen barrier characteristics as well as the ability to protect the products therein against humidity.
In Asia, alcoholic beverages, such as wine, sake and the like, are packaged in a wide variety of materials, including paperboard based containers. In order to protect the product from oxygen and eventual spoilage, the container construction usually consists of a multilayer structure comprised of aluminum foil, polyethylene terephthalate, metallized polyethylene terephthalate, or a combination of at least two of these in a multilayer structure. Foil has proved to be the best oxygen barrier, but it is relatively expensive and difficult to convert into a carton without cracking or developing pin holes.
The object of the present invention is to produce an improved alcoholic beverage packaging heat-sealable material for wine, sake, or other alcoholic beverage cartons, which does not transmit oxygen and humidity or moisture and exhibits a good heat-seal structure for product shelf lives of six months or longer.

This patent is subject to a terminal disclaimer.

Barrier laminate structure for packaging beverages


A method for recommending a download resource includes: obtaining a download record of a target user, obtaining a target user group associated with the target user according to the download record; obtaining download records of the target user group and download records of a global user group; processing the downloading records of the target user group and the download records of the global user group to generate, for a download resource in the download records of the target user group, a differentiation degree between the download resource in the download records of the target user group and the download resource in the download records of the global user group; and sorting download resources in the download records of the target user group according to the differentiation degree, and recommending the top-ranking predetermined number of download resources to the target user.

With the development of telecommunications techniques, network bandwidth is increased dramatically. Therefore, a large amount of websites and client software providing download resources emerge. These websites and client software classify the download resources into different categories and present them to users. Users may download a download resource according to their requirements. The download resources may include software, video, audio, picture, text, etc. In order to facilitate the selection of the user, besides allowing the user to submit downloading request initiatively, the websites and client software also provide a download resource recommendation function, i.e., push some high quality download resources, such as hot films, hot games, frequently-used software, to a webpage or a client, so as to present the recommended download resources to the user.
In a conventional download resource recommendation method, the hot degree of a download resource is determined according to a download record of the download resource (the more times that the download resource is downloaded, the higher the hot degree). Then the download resources are sorted. Top N download resources (top N download resources whose hot degrees rank in first N, N may be determined according to a practical requirement) are recommended to the user. However, the download record merely statistically reflects interests of all users. Therefore, the user may be not interested in the download resource recommended to the user.
In a conventional improved downloading recommendation method, a score table (score matrix) is created first according to a score of each download resource given by each user. Then, according to a similarity degree between scores of different download resources, a target user group similar to a target user (a user that the download resource is to be recommended to) is determined. According to a whole interest of the group (e.g., scores of the download resources provided by users in the target user group), a download resource is recommended to the user.
Although this improved download resource recommendation method increases the correlation degree between the download resource and the user, it is hard to obtain the score of the download resource provided by the user (most users do not give a score after downloading the resource). In addition, the interest of the target user on the download resource is determined merely according to the overall interest of the target user group, which makes the target user and the download resource less correlated. Thus, the accuracy ratio of the download resource recommendation method is not high.

Download resource recommendation method, system and storage medium

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


After satisfaction of an overrun condition that a tentative torque Tm1tmp of a motor overruns a torque limit Tlim1, a torque command Tm1* of the motor is set by limiting the tentative torque Tm1tmp with the torque limit Tlim1. With respect to an engine, the greater between a converted power Pesh and a value 0is set to a second correction power Pemo2. A requested power Pe* of the engine is recalculated by subtracting a first correction power Pemo1 and the second correction power Pemo2from the requested power Pe*. The engine is controlled using the recalculated requested power Pe*, while the motor is controlled using the torque command Tm1*.

In a proposed configuration of a hybrid vehicle having: an engine: a generator: a planetary gear unit having a carrier, a sun gear and a ring gear connected with an output shaft of the engine, a rotating shaft of the generator and an output shaft linked to drive wheels; a drive motor having a rotating shaft connected with the ring gear of the planetary gear unit; and a battery capable of transmitting electric power to and from the generator and the drive motor, a torque of the generator is decreased with an increase in temperature of the generator, and a torque of the engine is accordingly decreased with an increase in rotation speed of the generator (for example, Patent Literature 1). In this hybrid vehicle, such control causes the torque of the engine to be sufficiently supported by the torque of the generator and suppresses an excessive increase in rotation speed of the generator.


A motor vehicle seat with a seat back hinge including a lower hinge arm associated with a seat carrier and an upper hinge arm associated with a seat back. A locking mechanism prevents the seat back tilting forward in a locked position and allows tilting of the seat back in a released position. The locking mechanism includes a handle, and a blocking lever hinged to the seat back that includes a blocking side. The upper hinge arm cooperates with the blocking side and a retaining catch stop. A retaining lever on the seat back forms a retaining lug which abuts the retaining catch stop in the tilted position of the seat back and retains the seat back in position. The blocking lever pivots upon actuation of the handle to abut the retaining lever, which is pivoted as a result, releasing the retaining lug from engagement with the retaining catch stop.

The invention relates to a motor vehicle seat with a seat carrier, with a seat back and with a seat back hinge that is disposed between seat carrier and seat back and is comprised of a lower hinge arm associated with said seat carrier as well as of an upper hinge arm associated with said seat back.
Motor vehicle seats are known in which the seat back can be pivoted to substantially a horizontal plane through an additional pivot hinge member provided above the pivot axis of the normal seat back hinge. The pivot hinge member, which is located higher, permits to sufficiently tilt the seat when it is adjusted in the forward direction. The forward tilted seat may be used as a table, this feature being termed the "table function". The decisive feature is that the seat back be folded down as far as possible so that the seat occupies little space and that the vehicle in which the motor vehicle seat is mounted can be advantageously loaded and can for example carry a bulky load.
A motor vehicle seat with a table function is known from DE 197 41 996 A.
In view of the motor vehicle seat of the type mentioned herein above, it is the object of the invention to indicate a motor vehicle seat with table function that is simple in construction and is built from a few component parts, is reliable in function and easy to operate.

Motor vehicle seat with a seat back hinge


A test on a desired internal voltage is easily and accurately conducted without increasing current dissipation or the number of pads. A driving circuit receiving a reference voltage from a reference voltage generating circuit has a high input impedance and low output impedance, and generates a voltage substantially at the same voltage level as the reference voltage received, and transmits the generated voltage to a pad with a current driving capability larger than the driving current capability of the reference voltage generating circuit.

1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a semiconductor integrated circuit device having at least a test mode for externally monitoring an internal voltage. Specifically, this invention relates to a semiconductor integrated circuit device having an internal power supply voltage generating circuit for generating an internal power supply voltage according to a reference voltage, and more specifically to a configuration permitting externally monitoring or externally changing the reference voltage.
2. Description of the Background Art
Now, as an example of the semiconductor integrated circuit device, a semiconductor memory device is considered. The semiconductor memory device has been made with higher integration and higher density to obtain an increased storage capacity, and accordingly, the elements or the components of the device have been miniaturized. To ensure the reliability of these miniaturized elements such as a MOS transistor insulated gate type field effect transistor), the operating power supply voltage should be made low. Such a lowering of the operating power supply voltage can reduce the power dissipation which is proportional to the square of the operating power supply voltage. External logics and processors, however, have not been miniaturized to the degree of the semiconductor memory device. Therefore, the power supply voltage for those devices cannot be made as low as that for the semiconductor memory device, because their high-speed operation will not be ensured. In addition, the miniaturized memory devices must retain compatibility with previous-generation semiconductor memory devices.
Therefore, the power supply voltage provided from an outside of the semiconductor memory device, such as a system power supply voltage, is down converted within the device to generate an internal power supply voltage at a required voltage level.
FIG. 19 is a diagram showing an example of the configuration of a conventional internal power supply circuit. Referring to FIG. 19, the internal power supply circuit includes a reference voltage generating circuit RFG which generates reference voltage Vref at a prescribed voltage level, and an internal voltage down converter VDC which compares reference voltage Vref from the reference voltage generating circuit RFG with the voltage on an internal power supply line IVL, and according to the result of comparison, supplies current from an external power supply node EX onto internal power supply line IVL to adjust the voltage level on the internal power supply line IVL to generate an internal power supply voltage intVcc.
The internal voltage down converter VDC includes a comparator CMP for comparing reference voltage Vref with internal power supply voltage intvcc on internal power supply line IVL, and a drive transistor DR formed of a p channel MOS transistor and for supplying current from external power supply node EX onto internal power supply line IVL according to the output signal from the comparator CMP. Comparator CMP has a positive input receiving internal power supply voltage intVcc on internal power supply line IVL and a negative input receiving reference voltage Vref.
When internal power supply voltage intvcc is higher than reference voltage Vref, the internal voltage down converter VDC pulls up the output signal from comparator CMP to a high level for rendering drive transistor DR nonconductive to stop current supply from external power supply node EX to internal power supply line IVL. On the other hand, if internal power supply voltage intvcc on internal power supply line IVL is lower than reference voltage Vref, the comparator CMP outputs a signal at a low level, increasing the conductance of drive transistor DR, and thus the current in proportion to the difference between the internal power supply voltage intvcc and the reference voltage Vref from external power supply node EX is supplied to internal power supply line IVL through drive transistor DR. As a result, the voltage level of internal power supply voltage intVcc is maintained substantially at the same level as reference voltage Vref.
FIG. 20 is a diagram showing an example of the configuration of reference voltage generating circuit RFG shown in FIG. 19, which is described, for example, in Japanese Patent Laying-Open No. 7-37381.
Referring to FIG. 20, the reference voltage generating circuit RFG includes: a p channel MOS transistor P1 connected between external power supply node EX and a node M1 and having a gate receiving a ground voltage; an n channel MOS transistor N1 connected between node M1 and a ground node and having its gate connected to node M1; a p channel MOS transistor P2 connected between external power supply node EX and a node M2 and having its gate connected to node M2; an n channel MOS transistor N2 connected between node M2 and a ground node and having its gate connected to node M1; a p channel MOS transistor P3 connected between external power supply node EX and a node M4 and having its gate connected to node M2; a p channel MOS transistor P4 connected between node M4 and node M3 and having its gate connected to node M3; and an n channel MOS transistor N3 connected between node M3 and a ground node and having its gate connected to node M1.
The two p channel MOS transistors P2 and P3 constitute a current mirror circuit, and their size ratio (size being a ratio of gate width to gate length) is set to 1:1. Meanwhile, each of the n channel MOS transistors N2 and N3 constitutes a current mirror circuit with n channel MOS transistor N1. The gate width to gate length ratio of n channel MOS transistor N2 is set to one half (xc2xd) that of n channel MOS transistor N3.
The reference voltage generating circuit RFG further includes a p channel MOS transistor P5 connected between external power supply node EX and node M3 and having its gate connected to node M3, a p channel MOS transistor P6 connected between external power supply node EX and a node MS and having its gate connected to node M4, and diode-connected channel MOS transistors P7, P8 and P9 connected in series to one another between node M5 and a ground node.
The absolute value of threshold voltage of p channel MOS transistor P5 is set higher than that of p channel MOS transistor P4. The ratio of gate width to gate length of p channel MOS transistor P6 is set at the same value as that of each of p channel MOS transistors P7-P9. Now, the operation of reference voltage generating circuit RFG shown in FIG. 20 will be described in brief.
P channel MOS transistor P1 having its gate connected to the ground node serves as a current source and generates a reference current, which in turn is supplied to n channel MOS transistor N1. N channel MOS transistors N1 and N2 constituting a current mirror circuit have the same size with each other, so that current flowing through n channel MOS transistor N2 is the same in amount as the current flowing through n channel MOS transistor N1. N channel MOS transistor N2 is supplied with current from p channel MOS transistor P2, and the mirror current of the current flowing through p channel MOS transistor P2 flows through p channel MOS transistor P3. As p channel MOS transistors P2 and P3 have the same size with each other, the same amount of current flows therethrough. The current i from p channel MOS transistor P3 flows through p channel MOS transistor P4 and n channel MOS transistor N3 to the ground node.
The ratio of gate width to gate length of n channel MOS transistor N3 is set twice that of n channel MOS transistor N2, and thus the current 2i, twice the magnitude of current i flowing through p channel MOS transistors P3 and P4, flows through n channel MOS transistor N3. The remaining current i is supplied from p channel MOS transistor P5 to n channel MOS transistor N3. The absolute value of threshold voltage of p channel MOS transistor P5 is set greater than that of p channel MOS transistor P4. Now, assume that the absolute value of threshold voltage of p channel MOS transistor P4 is represented by Vthp4, and the absolute value of threshold voltage of p channel MOS transistor P5 is represented by Vthp5. In this situation, as p channel MOS transistor P5 is operating in a diode mode, the voltage V(M3) of node M3 is represented by the following expression:
V(M3)=extVccxe2x88x92Vthp5.
Meanwhile, as p channel MOS transistor P4 is also operating in a diode mode, the voltage of node M4, V(M4) is expressed as follows:
V(M4)=V(M3)+Vthp4=extVccxe2x88x92(Vthp5xe2x88x92Vthp4).
Node M4 is connected to the gate of p channel MOS transistor P6, and thus p channel MOS transistor P6 supplies a constant current ir according to the constant voltage on nodes M4. Each of p channel MOS transistors P7-P9 has the same size as the p channel MOS transistor P6, and therefore each of these p channel MOS transistors P7-P9 generates the same gate-to-source voltage as p channel MOS transistor P6 does. That is, the source-to-gate voltage of p channel MOS transistor P6 is Vthp5-Vthp4, and each of p channel MOS transistors P7-P9 causes a voltage drop at the same voltage level as Vthp5-Vthp4. Therefore, the reference voltage Vref from node M5 is expressed by the following equation:
Vref=3(Vthp5xe2x88x92Vthp4).
This reference voltage Vref is determined based on the difference between the absolute values of threshold voltages of p channel MOS transistors P4 and P5, and becomes a constant voltage independent of external power supply voltage extVcc, provided that the external power supply voltage extVcc is higher than a predetermined voltage level and that all the p channel MOS transistors P7-P9 are conductive. Internal power supply voltage intVcc is set essentially at the same voltage level as reference voltage Vref. Therefore, the voltage level of internal power supply voltage intVcc, used as the operating power supply voltage for internal circuitry, attains a constant voltage level independent of the voltage level of external power supply voltage extVcc.
Reference voltage generating circuit RFG shown in FIG. 20 has reference current ir made considerably small in value in order to keep power dissipation sufficiently small. In the reference voltage generating circuit RFG configured as shown in FIG. 20, current ir supplied from p channel MOS transistor P6 flows through p channel MOS transistors P7-P9, causing a constant voltage drop at each of p channel MOS transistors P7-P9, and thus reference voltage Vref at a constant voltage level is generated. Accordingly, reference voltage generating circuit RFG shown in FIG. 20 has no current supplying capability for an external load. If current ir supplied from p channel MOS transistor P6 flows into an external load, the current value flowing through p channel MOS transistors P7-P9 will change, and the voltage level of reference voltage Vref will change consequently. Therefore, in the case a noise occurs on node M5, it will not be absorbed (because of the absence of current supply), making the configuration extremely susceptible to noise.
If noise is not absorbed, the voltage level of reference voltage Vref will vary, and accordingly the voltage level of internal power supply voltage intVcc will vary.
In the configuration of reference voltage generating circuit RFG as illustrated in FIG. 20, a resistance element can be connected between node M5 and a ground node. In this case, reference voltage Vref is determined by both reference current ir and the resistance value of the resistance element. In this case, the resistance value of the resistance element is made extremely high in order to make current consumption sufficiently small. Therefore, the configuration that utilizes the resistance element in order to generate the reference voltage also has considerably small current supplying capability, and thus has a disadvantage that it is susceptible to noise at the output node. Several tests are conducted for semiconductor memory devices. The reference voltage Vref is externally monitored in a test mode for tuning the voltage level of internal power supply voltage intVcc. Further, a test for measuring an estimation parameter (such as operating margin) of the semiconductor memory device is performed. In these test modes, the following problems arise in the conventional reference voltage generation circuit.
FIG. 21 is a diagram schematically showing an arrangement for externally monitoring the voltage level of reference voltage Vref generated by reference voltage generating circuit RFG. Referring to FIG. 21, on the semiconductor chip CH where the semiconductor memory device is formed, a pad PD is arranged in the vicinity of reference voltage generating circuit RFG. The pad PD is connected through an interconnection line SG to the output node of reference voltage generating circuit RFG. Pad PD is a test-dedicated pad, and is not connected to a lead terminal after packaging. A test probe PB from a tester TU is contacted to the pad formed on the semiconductor chip CH, and the voltage level on pad PD is monitored.
When the tester TU has a voltmeter connected to the test probe PB, reference voltage generating circuit RFG having no current supplying capability cannot sufficiently charge the path from pad PD through test probe PB to the voltmeter in tester TU, and therefore, the voltage level of reference voltage Vref cannot be measured in tester TU accurately.
There is another way of measuring the voltage level of reference voltage Vref generated from reference voltage generating circuit RFG, in which pad PD is provided with current from test probe PB using the tester TU, and the voltage level is measured dependent on whether or not current flows through the test probe PB. In this case, the current supplied from tester TU through test probe PB will be transmitted through pad PD and interconnection line SG to the output node of reference voltage generating circuit RFG. Reference voltage generating circuit RFG is essentially a voltage follower circuit with a small output impedance. Therefore, the current supplied by test probe PB flows into the output node and causes the voltage level of reference voltage Vref to change, thereby making it difficult to measure the level of reference voltage Vref accurately.
Further, this test is carried out on a semiconductor chip CH present on a wafer, with test probe PB from tester TU connected to pad PD. When testing, a jig called a test card is employed to allow test probes to contact with all the pads formed on a semiconductor chip CH. Therefore, noise from these test probes, such as a cross-talk is transmitted to pad PD, causing the voltage level of reference voltage Vref of reference voltage generating circuit RFG to change, thereby making it difficult to measure the voltage level with accuracy.
FIG. 22 is a diagram schematically showing the overall configuration of a semiconductor memory device. Referring to FIG. 22, the semiconductor memory device includes a memory cell array MA having a plurality of memory cells arranged in a matrix of rows and columns, a sense amplifier band SAB having a plurality of sense amplifier circuits provided corresponding to respective columns of memory cell array MA, to sense, amplify and latch the data of the memory cells read out on the corresponding columns when activated, a peripheral circuit PC for making an access to memory cell array MA, and a sense amplifier control circuit SAC for controlling the sense amplifier circuits in sense amplifier band SAB. The peripheral circuit PC may include a row decoder for selecting a row and an internal write/read circuit for writing/reading data. It may also include circuits for generating various control signals.
A peripheral circuit dedicated internal power supply circuit IGP is provided for peripheral circuit PC, and a sense amplifier dedicated internal power supply circuit IGS is provided for sense amplifier control circuit SAC. In the vicinity of the peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS, pads PDP and PDS are disposed respectively. Peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS each include both reference voltage generating circuit RFG and internal voltage down converter VDC shown in FIG. 19. However, the level of the internal power supply voltage output from peripheral circuit dedicated internal power supply circuit IGP is set slightly higher in order to permit peripheral circuit PC to operate at high speed.
The internal power supply voltage fed by sense amplifier control circuit SAC for driving sense amplifier band SAB (sense amplifier power supply voltage) is set lower than that supplied to peripheral circuit PC in order to ensure the reliability of the memory cell transistors in memory cell array MA. As a result, the internal power supply voltage output from sense amplifier dedicated internal power supply circuit IGS is set at a voltage level lower than the internal power supply voltage output from peripheral circuit dedicated internal power supply circuit IGP. In memory cell array MA, the voltage transmitted onto a selected word line is (normally 1.5 times) higher than the operating power supply voltage, and accordingly, the voltage level to be transmitted into memory cell array MA is set low in order to prevent the gate insulating film of each memory cell transistor (MOS transistor) from suffering a dielectric breakdown when the boosted voltage is applied.
As illustrated i n FIG. 22, pads for monitoring the reference voltage, PDP and PDS, are arranged respectively for peripheral circuit dedicated internal power supply circuit IGP and sense amplifier dedicated internal power supply circuit IGS. These pads PDP and PDS are for use in a wafer level test, and not used after packaging. Therefore, a problem arises with respect to the semiconductor memory device that the chip area cannot be reduced because of the large area occupied by pads PDP and PDS. In addition, if the number of the required pads increases, it will become more complicated to align the pads with test probes in testing, and will consequently lower the efficiency of the testing operation.
The problem that the number of pads increases will be encountered not only where monitoring the reference voltage for generating an internal power supply voltage, but also where externally monitoring the voltage levels of internal voltages generated in the semiconductor memory device, such as a bit line precharge voltage, a cell plate voltage, a substrate bias voltage, an internal power supply voltage, and a word line driving voltage.
Moreover, the problem associated with externally monitoring an internal voltage is experienced not only in the semiconductor memory device, but also in other semiconductor integrated circuit devices including logics.
Furthermore, the problem with the pad number will also arise when the xe2x80x9cforcexe2x80x9d test is conducted for measuring the operating margin and others of an internal circuit by externally setting the level of a desired internal voltage to a desirable voltage level.
It is an object of the present invention to provide a semiconductor integrated circuit device capable of easily conducting a test on a desired internal voltage with accuracy.
It is another object of this invention to provide a semiconductor integrated circuit device capable of externally monitoring as well as externally setting the internal voltage accurately.
It is still another object of the present invention to provide a semiconductor integrated circuit device capable of easily conducting a test on a plurality of internal voltages without increasing the chip area.
It is a further object of the present invention to provide a semiconductor integrated circuit device capable of easily and accurately conducting a test on a reference voltage used for generating an internal power supply voltage without increasing the chip occupation area.
The semiconductor integrated circuit device according to an aspect of the present invention includes at least one reference voltage generating circuitry, internal power supply voltage generating circuitry for comparing a voltage corresponding to the reference voltage generated by the at least one reference voltage generating circuitry with a voltage on an internal power supply line to adjust the voltage level on the internal power supply line according to the result of comparison, a pad, and driving circuitry provided between the pad and an output of the at least one reference voltage generating circuitry for receiving the reference voltage output from the at least one reference voltage generating circuitry to generate a voltage substantially at the same level as the received reference voltage for transmission to the pad.
The semiconductor integrated circuit device according to another aspect of the invention includes a plurality of voltage transmitting lines each having an internal voltage at a predetermined voltage level transmitted thereon, a pad, and connecting circuitry provided between the pad and each of the plurality of voltage transmitting lines, and responsive to a select signal for electrically connecting the pad to a voltage transmitting line designated by the select signal.
The semiconductor integrated circuit device according to a further aspect of the invention includes a plurality of voltage transmitting lines each having an internal voltage at a predetermined voltage level transmitted thereon, a pad, connecting circuitry provided between each of the plurality of voltage transmitting lines and a first internal node, and responsive to a select signal for electrically connecting the pad to a voltage transmitting line designated by the select signal, and driving circuitry provided between the first internal node and the pad, and for receiving the voltage on the voltage transmitting line selected by the connecting circuitry to generate a voltage substantially at the same level as the received voltage for transmission to the pad.
By providing driving circuitry between the pad and the output of the reference voltage generating circuit having an extremely small current supplying capability, influence of the noise at the pad on the reference voltage generating circuit can be prevented. Also, by driving the pad by driving circuitry, the pad can be driven with a relatively large current supplying capability, and thus the level of the reference voltage can be externally monitored reliably.
Furthermore, by providing a plurality of internal voltage transmitting lines with connecting circuitry for selective connection with the pad, a test on a plurality of internal voltages can be conducted using a single pad. Accordingly, increase in the number of pads is suppressed to restrict an increase in a chip occupation area, and also the contact of the test probes of the test card with the pad will be made easier, and therefore the operation upon the testing can be simplified.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor integrated circuit device capable of externally monitoring internal voltage


This invention discloses improvements to a damper of the type used in industrial applications to open and close ducts carrying noxious or corrosive materials, such as combustion by-products. The improvements include a linear rack and wheeled pinion system to raise and lower a damper blade plate and improvements to the seal cartridge to prolong the life of the seal membrane and to prevent galling between the blade plate and the seal cartridge or damper frame.

The devices of the type disclosed herein are used principally in industrial settings having exhaust duct systems with large cross sectional dimensions wherein exhaust gases must be processed by scrubbers and/or precipitators before they can be released to the air through a smokestack. An example of use for the damper of the present system would be in a power plant where combustion by-products must be released. Such combustion by-products may contain sulfur dioxide, carbon monoxide, carbon dioxide and other noxious and corrosive compounds. In addition to corrosive compounds present in the exhaust gases, temperatures within the ducts may reach highs in the range of 300° to 700° F.
It is desirable in such settings that the flow of combustion by-products through individual ducts be interrupted at various times for the purpose of performing maintenance on the scrubbers and precipitators within the exhaust system. Therefore, a typical application of the damper of the present invention would be within a duct in an exhaust system from an industrial plant to isolate a scrubber and/or a precipitator from the normal flow of combustion by-products. Because the ducts carrying the combustion by-products may be relatively large, for example, on the order of twenty-five to four hundred square feet in cross sectional area, it is possible that maintenance workers may be required to physically enter the duct to perform maintenance operations. It is therefore necessary that a seal be provided such that combustion by-products do not leak past the damper and into the area where maintenance workers may be present.
Typical prior art dampers of the type for which improvements are shown by this invention consist of a frame which is secured inline in a duct carrying combustion by-products. A blade typically slides into the cross sectional area of the duct from an area outside of the duct to close the duct, thereby interrupting the flow of the combustion by-products past the damper. In addition, to better seal the duct against leaks of the combustion by-products past the damper blade, a seal within the damper contacts the blade and is forced against the blade by an inflation pressure provided by compressed air which may be inserted into a hollow area of the seal. To open the damper it is known in the art to evacuate the air from within the seal to cause the seal to collapse away from the blade, thereby allowing the blade to be retracted to open the duct.
Such a damper is shown in U.S. Pat. No. 4,561,472 (Dryer et al.). The damper of the '472 patent is typical of those shown in the many patents of the prior art and improvements thereto are disclosed by this invention. Other similar dampers are also shown in U.S. Pat. No. 4,235,256 (Crawshay), U.S. Pat. No. 4,163,458 (Bachmann) and U.S. Pat. No. 4,022,241 (Fox).
One problem with the damper disclosed by Dryer et al. is that a failure of the seal may be precipitated by a failure of the compressed air system, which may allow the seal to deflate, thereby allowing combustion by-products to leak around the blade. A further problem with the prior art dampers of the type disclosed by Dryer et al. is that the blade, which may be subjected to differential pressure gradients and be relatively heavy, on the order of 4 plus tons, may contact the seal cartridge frame during retraction and engagement, causing galling to develop between the blade and the seal cartridge frame. This is particularly troublesome in corrosive environments where alloy materials must be utilized. Further, the mechanism for raising and lowering the blade in the prior art systems is prone to fouling by the collection of dust and dirt and through corrosion of the mechanism by continued exposure to the corrosive elements present in the combustion by-products. Lastly, the flexible seals of the prior art are typically permanently affixed to the frame of the damper, making it difficult to repair or replace the seal when necessary. These and other problems with the prior art are addressed by the current invention.

Rack and pinion wheel drive for an industrial sliding blade damper


Multiple embodiments relate to a method for detecting a fault on a data line in a bus system in a two-line data network having at least two control units. A data signal is emitted by a transmitter-receiver unit on the two data lines as a differential voltage signal that includes a defined quiescent current. The data lines are mutually connected through a resistance bridge for detecting the middle voltage. The middle voltage is detected directly by a microcontroller after a low-pass filter or as a digital value after an analog-to-digital conversion. The result is displayed and/or stored. A circuit arrangement for implementing the method is also provided.

1. Technical Field
The multiple embodiments disclosed herein relate to a method for detecting a fault on a data line in a bus system in a two-conductor data network having at least two control units.
2. Background Art
In the case of such two-wire data buses, such as a CAN-Bus (derived from Control Area Network), for which the properties are specified in ISO 11898, individual data bits are transmitted differentially on the two lines of the bus. In a quiescent state, both lines of the bus have about the same potential, since the two lines are coupled to one another through a terminating resistor. A dominant bit is actively transmitted from a transmitter on the bus by enabling a driver current. This transmission occurs differentially, which means that the potential of one line of the bus is raised and the potential of the other line of the bus is lowered. A recessive bit is transmitted by a transmitter by turning off the driver current. In the following discussion, we assume that the two bus lines remain at approximately the same potential.
Different kinds of errors can occur in data buses of this type. Short circuits can arise in the individual conductors with respect to a reference potential and also with respect to one another. DE 100 59 769 A1 discloses that known circuit arrangements analyze the potentials of the conductors and attempt to infer whether such short circuits are present.
In a circuit element known from U.S. Pat. No. 5,488,306, the difference in potentials of the two bus lines is also evaluated. A concrete example of a circuit is presented in this publication that allows for definite error recognition to occur without reacting to ground offsets of the bus conductors resulting from error recognition by differential current measurement and not by voltage measurement.
A method for detecting the ground offsets of portions of a network system is disclosed in DE 102 25 556 A1, in particular for testing the ground contact between networked control units, wherein data are sent and received through at least one bus system. Thus, in the quiescent state of at least one bus conductor provided for receiving the data or at least one receiver line, the voltage is sampled after the passage of a specifiable first time interval and is compared with at least one specifiable threshold or reference potential value. If the threshold value is exceeded, it then produces a ground fault signal by which the quiescent state of the at least one bus conductor is evaluated. The circuit is relatively complex and complicated, and thus expensive.
An important requirement for high-speed CAN systems in motor vehicles is the diagnosis of the conductor lines, which also results from the previously mentioned documents. The prevalent solutions consist in that a diagnosis is carried out in integrated circuits, namely in central interface modules. Such interface modules are relatively expensive. The high speed TJA1041A and TJA1040-CAN-transceivers are cited for example. It is obvious from the specification sheets for these integrated circuits that two resistors (each 60Ω) are connected between the data lines such that their connection point to ground is switched through a condenser and connected with an input of the transceiver. Stabilization is to be achieved in this manner.

Method for detecting a fault on a data line


A method, an apparatus, and a system for establishing a data connection are disclosed that relate to the field of communications network technologies, and can implement automatic determination of a transmission function by an electronic device and reduce operation steps of enabling a transmission function by a user. A receiver device obtains connection information sent by a transmitter device, and enables a target transmission function according to transmission function priorities obtained in advance, transmission functions of the transmitter device, and transmission functions of the receiver device; and then the receiver device sends an authentication message to the transmitter device through the target transmission function, and establishes a connection of the target transmission function with the transmitter device. Solutions provided are applicable to data transmission.

A near field wireless communication technology (NFC), also known as near field wireless communication, is a non-contact identification and interconnection technology, which can implement near field wireless communication between a mobile device, a consumer electronic product, a personal computer (PC), and an intelligent control tool. An electronic device can implement file transmission by using the NFC technology.
When two electronic devices transmit a file by using an NFC function, a transmission rate thereof is low, and a transmission distance ranges from 0 centimeter (cm) to 10 cm. The NFC technology is generally used for a file less than 7 kilobytes (KB). Considering limitations on the rate and the transmission distance, in the prior art, a certain association is established through contact of the electronic devices, and both the electronic devices enable, through a contact protocol, the same transmission function such as wireless network direct transmission (e.g., Wireless Fidelity (Wi-Fi) Direct), wireless network (e.g., Wi-Fi), or Bluetooth (BT) to perform pairing and establish a connection, so that the electronic devices can automatically enable the transmission function, and that a user reduces operation steps.
However, after passing NFC authentication, the electronic devices enable the transmission function through a certain protocol, where the protocol enables the same transmission function, and when either one of the electronic devices does not have the transmission function specified by the protocol, data transmission fails.

Method, apparatus, and system for establishing data connection


The present invention provides methods for limiting or preventing a decrease in the level of RyR2-bound FKBP12.6 in a subject. The present invention further provides methods for treating and preventing atrial and ventricular cardiac arrhythmias, heart failure, and exercise-induced sudden cardiac death in a subject. Additionally, the present invention provides use of JTV-519 in a method for limiting or preventing a decrease in the level of RyR2-bound FKBP12.6 in a subject who has, or is a candidate for, atrial fibrillation. Also provided are uses of 1,4-benzothiazepine derivatives in methods for treating and preventing atrial and ventricular cardiac arrhythmias and heart failure in a subject, and for preventing exercise-induced sudden cardiac death. The present invention also provides methods for identifying agents for use in treating and preventing atrial fibrillation and heart failure, and agents identified by these methods.

Despite advances in treatment, congestive heart failure remains an important cause of mortality in Western countries. Heart failure affects 5 million individuals in the United States alone, and is characterized by a 5-year mortality rate of ˜50% (Levy et al., Long-term trends in the incidence of and survival with heart failure. N. Engl. J. Med., 347:1397-402, 2002).
An important hallmark of heart failure is reduced myocardial contractility (Gwathmey et al., Abnormal intracellular calcium handling in myocardium from patients with end-stage heart failure. Circ. Res., 61:70-76, 1987). In healthy heart muscle, and in other striated muscle, calcium-release channels on the sarcoplasmic reticulum (SR), including ryanodine receptors (RyRs), facilitate coupling of an action potential to a muscle cell's contraction (i.e., excitation-contraction (EC) coupling). Contraction is initiated when calcium (Ca2+) is released from the SR into the surrounding cytoplasm. In heart failure, contractile abnormalities result, in part, from alterations in the signaling cascade that allows the cardiac action potential (AP) to trigger contraction. In particular, in failing hearts, the amplitude of the whole-cell Ca2+ transient is decreased (Beuckelmann et al., Intracellular calcium handling in isolated ventricular myocytes from patients with terminal heart failure. Circ., 85:1046-55, 1992; Gomez et al., Defective excitation-contraction coupling in experimental cardiac hypertrophy and heart failure. Science, 276:800-06, 1997), and the duration is prolonged (Beuckelmann et al., Intracellular calcium handling in isolated ventricular myocytes from patients with terminal heart failure. Circ., 85:1046-55, 1992).
Cardiac arrhythmia, a common feature of heart failure, is known to be associated with SR Ca2+ leaks in structurally-normal hearts. In these cases, the most common mechanism for induction and maintenance of ventricular tachycardia is abnormal automaticity. One form of abnormal automaticity, known as triggered arrhythmia, is associated with aberrant release of SR Ca2+, which initiates delayed after-depolarizations, or DADs (Fozzard, H. A., After depolarizations and triggered activity. Basic Res. Cardiol., 87:105-13, 1992; Wit and Rosen, Pathophysiologic mechanisms of cardiac arrhythmias. Am. Heart J., 106:798-811, 1983). DADs are abnormal depolarizations in cardiomyocytes that occur after repolarization of a cardiac action potential. The molecular basis for the abnormal SR Ca2+ release that results in DADs has not been fully elucidated. However, DADs are known to be blocked by ryanodine, providing evidence that RyR2 may play a key role in the pathogenesis of this aberrant Ca2+ release (Marban et al., Mechanisms of arrhythmogenic delayed and early afterdepolarizations in ferret ventricular muscle. J. Clin. Invest., 78:1185-92, 1986; Song and Belardinelli, ATP promotes development of afterdepolarizations and triggered activity in cardiac myocytes. Am. J. Physiol., 267:H2005-11, 1994).
The most common cardiac arrhythmia in humans is atrial fibrillation (AF). It represents a major cause of morbidity and mortality (Chugh et al., Epidemiology and natural history of atrial fibrillation: clinical implications. J. Am. Coll. Cardiol., 37:371-78, 2001; Falk, R. H., Atrial fibrillation. N. Engl. J. Med., 344:1067-78, 2001). Despite its clinical importance, however, treatment options for AF have been limited—due, in part, to the fact that its underlying molecular mechanisms are poorly understood.
Approximately 50% of all patients with heart disease die from fatal cardiac arrhythmias. Such fatal cardiac arrhythmias are often ventricular in nature. In some cases, a ventricular arrhythmia in the heart may be rapidly fatal—a phenomenon referred to as "sudden cardiac death" (SCD). Fatal ventricular arrhythmias (and SCD) may also occur in young, otherwise-healthy individuals who are not known to have structural heart disease. In fact, ventricular arrhythmia is the most common cause of sudden death in otherwise-healthy individuals.
Catecholaminergic polymorphic ventricular tachycardia (CPVT) is an inherited disorder in individuals with structurally-normal hearts. It is characterized by stress-induced ventricular tachycardia—a lethal arrhythmia that may cause SCD. In subjects with CPVT, physical exertion and/or stress induce bidirectional and/or polymorphic ventricular tachycardias that lead to SCD in the absence of detectable structural heart disease (Laitinen et al., Mutations of the cardiac ryanodine receptor (RyR2) gene in familial polymorphic ventricular tachycardia. Circulation, 103:485-90, 2001; Leenhardt et al., Catecholaminergic polymorphic ventricular tachycardia in children: a 7-year follow-up of 21 patients. Circulation, 91:1512-19, 1995; Priori et al., Clinical and molecular characterization of patients with catecholaminergic polymorphic ventricular tachycardia. Circulation, 106:69-74, 2002; Priori et al., Mutations in the cardiac ryanodine receptor gene (hRyR2) underlie catecholaminergic polymorphic ventricular tachycardia. Circulation, 103:196-200, 2001; Swan et al., Arrhythmic disorder mapped to chromosome 1q42-q43 causes malignant polymorphic ventricular tachycardia in structurally normal hearts. J. Am. Coll. Cardiol., 34:2035-42, 1999).
CPVT is predominantly inherited in an autosomal-dominant fashion. Individuals with CPVT have ventricular arrhythmias when subjected to exercise, but do not develop arrhythmias at rest. Linkage studies and direct sequencing have identified mutations in the human RyR2 gene, on chromosome 1q42-q43, in individuals with CPVT (Laitinen et al., Mutations of the cardiac ryanodine receptor (RyR2) gene in familial polymorphic ventricular tachycardia. Circulation, 103:485-90, 2001; Priori et al., Mutations in the cardiac ryanodine receptor gene (hRyR2) underlie catecholaminergic polymorphic ventricular tachycardia. Circulation, 103:196-200, 2001; Swan et al., Arrhythmic disorder mapped to chromosome 1q42-q43 causes malignant polymorphic ventricular tachycardia in structurally normal hearts. J. Am. Coll. Cardiol., 34:2035-42, 1999).
There are three types of ryanodine receptors, all of which are highly-related Ca2+ channels. RyR1 is found in skeletal muscle, RyR2 is found in the heart, and RyR3 is located in the brain. The type 2 ryanodine receptor (RyR2) is the major Ca2+-release channel required for EC coupling and muscle contraction in cardiac striated muscle.
RyR2 channels are packed into dense arrays in specialized regions of the SR that release intracellular stores of Ca2+, and thereby trigger muscle contraction (Marx et al., Coupled gating between individual skeletal muscle Ca2+ release channels (ryanodine receptors). Science, 281:818-21, 1998). During EC coupling, depolarization of the cardiac-muscle cell membrane, in phase zero of the AP, activates voltage-gated Ca2+ channels. In turn, Ca2+ influx through these channels initiates Ca2+ release from the SR via RyR2, in a process known as Ca2+-induced Ca2+ release (Fabiato, A., Calcium-induced release of calcium from the cardiac sarcoplasmic reticulum. Am. J. Physiol., 245:C1-C14, 1983; Nabauer et al., Regulation of calcium release is gated by calcium current, not gating charge, in cardiac myocytes. Science, 244:800-03, 1989). The RyR2-mediated, Ca2+-induced Ca2+ release then activates the contractile proteins which are responsible for cardiac muscle contraction.
RyR2 is a protein complex comprising four 565,000-dalton RyR2 polypeptides in association with four 12,000-dalton FK506 binding proteins (FKBPs), specifically FKBP12.6 (calstabin). FKBPs are cis-trans peptidyl-prolyl isomerases that are widely expressed, and serve a variety of cellular functions (Marks, A. R., Cellular functions of immunophilins. Physiol. Rev., 76:631-49, 1996). FKBP12 proteins are tightly bound to, and regulate the function of, the skeletal ryanodine receptor, RyR1 (Brillantes et al., Stabilization of calcium release channel (ryanodine receptor) function by FK506-binding protein. Cell, 77:513-23, 1994; Jayaraman et al., FK506 binding protein associated with the calcium release channel (ryanodine receptor). J. Biol. Chem., 267:9474-77, 1992); the cardiac ryanodine receptor, RyR2 (Kaftan et al., Effects of rapamycin on ryanodine receptor/Ca(2+)-release channels from cardiac muscle. Circ. Res., 78:990-97, 1996); a related intracellular Ca2+-release channel, known as the type 1 inositol 1,4,5-triphosphate receptor (IP3R1) (Cameron et al., FKBP12 binds the inositol 1,4,5-trisphosphate receptor at leucine-proline (1400-1401) and anchors calcineurin to this FK506-like domain. J. Biol. Chem., 272:27582-88, 1997); and the type I transforming growth factor β (TGFβ) receptor (TβRI) (Chen et al., Mechanism of TGFbeta receptor inhibition by FKBP12. EMBO J., 16:3866-76, 1997). FKBP12.6 binds to the RyR2 channel (one molecule per RyR2 subunit), stabilizes RyR2-channel function (Brillantes et al., Stabilization of calcium release channel (ryanodine receptor) function by FK506-binding protein. Cell, 77:513-23, 1994), and facilitates coupled gating between neighboring RyR2 channels (Marx et al., Coupled gating between individual skeletal muscle Ca2+ release channels (ryanodine receptors). Science, 281:818-21, 1998), thereby preventing aberrant activation of the channel during the resting phase of the cardiac cycle.
It is clear that leaks in RyR2 channels are associated with a number of pathological states—in both diseased hearts and structurally-normal hearts. Accordingly, methods to repair the leaks in RyR2 could treat or prevent heart failure, cardiac arrhythmias, and sudden cardiac death in millions of patients.
The 1,4-benzothiazepine derivative, JTV-519, or 4-[3-(4-benzylpiperidin-1-yl)propionyl]-7-methoxy-2,3,4,5-tetrahydro-1,4-benzothiazepine monohydrochloride (also known as k201 or ICP-Calstan 100), is a new modulator of calcium-ion channels. In addition to regulating Ca2+ levels in myocardial cells, JTV-519 also modulates the Na+ current and the inward-rectifier K+ current in guinea pig ventricular cells, and inhibits the delayed-rectifier K+ current in guinea pig atrial cells. Studies have shown that JTV-519 has a strong cardioprotective effect against catecholamine-induced myocardial injury, myocardial-injury-induced myofibrillar overcontraction, and ischemia/reperfusion injury. In experimental myofibrillar overcontraction models, JTV-519 demonstrated greater cardioprotective effects than propranolol, verapamil, and diltiazem. Experimental data have also suggested that JTV-519 effectively prevents ventricular ischemia/reperfusion by reducing the level of intracellular Ca2+ overload in animal models.

Anti-arrhythmic and heart failure drugs that target the leak in the ryanodine receptor (RyR2) and uses thereof

The Trustees of Columbia University in the City of New York


Disclosed a process for purifying dimethyl carbonate which comprises distillating a mixture of dimethyl carbonate and methanol in the presence of dimethyl oxalate to separate and remove methanol.

This invention relates to a process for purifying dimethyl carbonate which is useful as a synthesis starting material for an aromatic polycarbonate and various chemical products and as a solvent. More particularly, it relates to a process for purifying dimethyl carbonate which comprises distillating and separating methanol to purify dimethyl carbonate by co-presenting dimethyl oxalate in order to prevent reacting carbon monoxide and an ester of nitrous acid in the presence of a specific catalyst with high yield.
As a process for preparing dimethyl carbonate, there have been practiced by, for example, the method of reacting carbon monoxide, methanol and an acid by using copper chloride (Japanese Patent Publications No. 11129/1970 and No. 45655/1980), the method of interesterifying a cyclic carbonate such as ethylene carbonate with methanol in the presence of a catalyst (U.S. Pat. Nos. 3,642,858 and 3,803,201, and Japanese Patent Publication No. 27658/1985), and the method of subjecting to vapor reaction of carbon monoxide and nitrite in the presence of a catalyst (Japanese Unexamined Patent Publications No. 274816/1989 and No. 201146/1990). However, in either of the methods, dimethyl carbonate can be obtained as a mixture with methanol so that separation from methanol is indispensable for purifying dimethyl methyl carbonate. Dimethyl carbonate and methanol constitute azeotropic mixture in a composition ratio of 30:70 (weight ratio), and thus, it is difficult to separate the mixture by distillation under normal pressure.
Thus, many investigations have been carried out about the method for purifying dimethyl carbonate from the mixture of the both components, and various proposals have been made. For example, there has been proposed the method of obtaining crystalline product enriched in dimethyl carbonate by cooling as disclosed in U.S. Pat. No. 3,803,201, the method of subjecting to separation of the mixture by distillation by breaking azeotrope with pressurization as disclosed in Japanese Patent Publication No. 3463/1984, and the method of subjecting to separation by distillation by adding a hydrocarbon such as hexane and heptane as disclosed in Japanese Unexamined Patent Publication No. 41820/1979. However, these methods cannot be said to be industrially satisfied. That is, the method of using extraction and distillation with water is not economical since dimethyl carbonate dissolves well in water and easily saponified so that causing many loss. An apparatus to be used in the method of distillation under pressure becomes extremely high cost and operations thereof are difficult. Also, the method of adding hydrocarbon is complicated in operations and disadvantageous in energy. Further, the method of precipitation by cooling is industrially not practical.

Process for purifying dimethyl carbonate


Provision of two or more powder coatings different in hue, lightness and/or saturation as base colors makes it possible to mix the base color powder coatings in accordance with a desired color and hence to conduct color matching upon performing powder coating. It is therefore no longer necessary to stock a large number of powder coatings, in other words, it is therefore possible to systematically produce fewer powder coatings in greater quantities. This can achieve rationalization in production, storage, physical distribution, management and the like and also a cost reduction in each of these stages. For example, coatings of desired color tones, especially coatings excellent in artistry can be formed in accordance with a fluidized-bed, electrostatic coating process making use of a powder-fluidizing container by preparing in advance only three primary colors of yellow, red and blue or optionally five primary colors additionally including black color and white color. The present invention provides these powder coatings, powder coating process and powder-coated article.

a) Field of the Invention
This invention relates to a powder coating, a powder coating process and a powder-coated article, and more specifically to a powder coating useful in an electrostatic coating process making use of a powder-fluidizing container, a powder coating process for the powder coating and a powder-coated article obtained by using the powder coating.
b) Description of the Related Art
Processes for coating an article with a powder coating conventionally include electrostatic coating processes and fluidized bed coating processes. In an electrostatic coating process, use of a powder coating the average particle size of which is 30 .mu.m or smaller is generally prone to cohesion of particles of the powder coating, resulting in a baked coating of reduced smoothness due to inclusion of cohered particles. Moreover, the flowability of the powder coating as powder is reduced and an object under coating cannot therefore be coated evenly, leading to the formation of a coating with lowered smoothness. An average particle size greater than 30 .mu.m, on the other hand provides a coating of reduced cohesion tendency but, after baking, results in the formation of large interparticle voids. When coated thinly (about 50 .mu.m or less), a coating is obtained with reduced smoothness after baking.
A fluidized-bed coating process, the other coating process, uses a powder coating, particles of which are generally coarser than those employed in an electrostatic coating process so that a coating lower in smoothness than that available by the electrostatic coating process is obtained after baking.
With a view to providing a coating with improved smoothness by relying upon a coating process, a great deal of research has been conducted in recent years on electrostatic fluidized-bed coating processes, resulting in the proposal of such a process as illustrated in FIG. 1.
The process illustrated in FIG. 1 is a powder coating process. Described specifically, a powder coating 2 which has been pneumatically brought into a fluidized state in a powder-fluidizing container 1 is lifted toward an object 4, which is to be coated and is suspended from a ground electrode 7, while applying positive (or negative) charges thereto from a powder-feeding lower electrode 3. Opposite, namely, negative (or positive) charges are next applied from a powder-feeding upper electrode 5, whereby the powder coating is lifted further while its charges are being neutralized. A pair or plural pairs of side electrodes 6 are arranged above the powder-feeding upper electrode 5 so that the object 4 suspended from the ground electrode 7 is conveyed between the paired side electrodes 6 in parallel with the paired side electrodes 6. Negative (or positive) charges are then applied from the pair or plural pairs of side electrodes 6, whereby powder coating is applied to a surface of the object passing between the side electrodes 6.
According to this process, the powder coating 2 is fluidized in the powder-fluidizing container 1. Charges are applied to the cohered powder coating 2 from the lower electrode 3. Individual particles of the powder coating are hence charged so that they repel each other. The cohered particles are therefore lifted while separating from each other. They are lifted further while their charges are once neutralized by the upper electrode 5. Subsequently, charges are applied from the side electrodes 6 so that the powder coating is applied.
The above-described electrostatic coating process making use of the powder-fluidizing container (electrostatic fluidized-bed coating process) has an excellent advantage that a thinner coating can be formed compared with conventional power coating processes. This process is however accompanied by a problem that powder coatings of different colors or different resins have to be prepared in advance, in other words, an extremely wide variety of powder coatings have to be prepared beforehand because only one kind of powder coating is used upon each application.

Powder coating, powder coating process and powder-coated article

Dainichiseika Color & Chemicals Mfg. Co., Ltd.


A catheter retaining clip (100) including first and second generally straight body portions (104,106), each of which extends along a longitudinal axis parallel to the other and includes a retention section. The generally straight body portions are connected by an extension piece (116 or 240) that extends generally from one generally straight body portion to the other generally straight body portion. The extension piece (116) may extend around a 180° curve that defines the curve of the catheter to be inserted into the clip, and a U-shaped channel (120) extends through the first and second generally straight body portions and the extension piece; the clip is installed onto a catheter (50) so that the catheter lies in the U-shaped channel and is retained therein by two or three retention sections or locking clasps (130). The present invention also provides methods of installing a catheter within the clip and methods of removing a catheter from within the clip.

In the manufacture of certain catheters, it is desirable to provide a curved shape thereto between the proximal and distal ends. When a stylet is installed into such a catheter assembly during manufacture to later assist in the insertion of the catheter into a patient, the stylet is sufficiently stiff that it tends to try to straighten the curvature of the catheter assembly that is desired. Therefore, it is desired to provide for maintaining the curvature of the catheter assembly during sterilization, packaging and shipping.


A dual interlayer dielectric material structure is located on a passivation dielectric material liner and entirely fills a gap located between each memory device stack of a plurality of memory device stacks. The dual interlayer dielectric material structure includes, from bottom to top, a first void free low-k interlayer dielectric (ILD) material and a second void free low-k ILD material.

The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a plurality of memory device stacks located in the back-end-of the-line (BEOL) and contained within a dual interlayer dielectric (ILD) material structure that is devoid of voids (i.e., void free). The present application also relates to a method of forming such a semiconductor structure.
Non-damascene memory device stacks in the BEOL is challenging for ILD material gap fill. Encapsulation (i.e., passivation) is required to protect each memory device stack prior to ILD material deposition. Gap filling of high incoming topography is an issue using existing ILD materials having a low dielectric constant (i.e., dielectric constant of less than 4.0). Thick encapsulation can reduce topography. However, thick encapsulation can increase parasitic capacitance of such structures.
There is thus a need for providing a semiconductor structure including a plurality of memory device stacks that are located in the back-end-of the-line (BEOL) that can eliminate the aforementioned concerns and achieve good gap filling.

ILD gap fill for memory device stack array


A novel water-soluble enzyme protein being composed of three heterogeneous subunits and having nitrile hydratase activity was separated and purified from the bacterium of genus Rhizobium. The nucleotide sequence of the gene encoding the protein was determined; using the transformant transformed with the expression vector having the nucleotide sequence, the protein was expressed; by reacting the transformant with a nitrile in a culture broth, the corresponding amide was produced.. Via the use of a culture broth containing the transformant described above or the protein itself, a nitrile can be efficiently converted into the corresponding amide.

The present invention relates to a novel protein having nitrile hydratase activity, the gene encoding the same, and a method for producing an amide from a nitrile via a transformant containing the gene. More specifically, the present invention relates to a novel protein having the activity of generating from a nitrile the corresponding amide; the gene encoding the same; a transformant transformed with an expression vector having a promoter sequence required at least for the expression of the protein; the DNA sequence encoding the protein and a terminator sequence; a method for expressing the protein via the culture of the transformant; a method for producing an amide by treating a nitrile with a culture broth containing the transformant or protein itself; an isolated microorganism; a treated microorganism; and protein or the immobilized products thereof.
For the technique to convert the nitrile groups of nitriles into amide groups by hydration, thereby producing the corresponding amides, there have been known a heating process using an acid or an alkali as a reaction catalyst and a heating process using copper catalysts. In recent years, however, a method has been adopted using a bacterial catalyst containing a water-soluble enzyme protein, namely nitrile hydratase, catalyzing the hydration reaction, (see Japanese Patent Applications Laid-open Publication Nos. 2693/1984 and 86889/1989; European Patent Applications Publication Nos. 188,316, 204,555, 444,639, and 93,782; U.S. Pat. Nos. 5,130,235 and 4,001,081; U.K. Patent Applications Publication Nos. 2,018,240, 2,076,820, and 2,076,821). It is believed that the method using the bacterial catalyst is superior to other methods, in that the hydration reaction can be carried out at ambient temperature and a higher conversion ratio can be achieved according to the method.
In using a bacterial catalyst, however, numerous considerations are required in preparing the bacterial catalyst, depending on the biological features of the bacterial catalyst to be used, such as the safety assessment of the bacterium, the optimum culture condition, and the like. Therefore, the activity as a biological catalyst is not necessarily readily increased to a level industrially applicable from the respect of cost.
As a method for improving such bacterial catalyst processes, a process is under investigation, comprising preparing a bacterial catalyst, namely an enzyme nitrile hydratase per se, via genetic engineering and converting nitriles into the corresponding amides. For example, Japanese Patent Application Laid-open No. 137688/1988 describes at an enzyme level a type of nitrile hydratase composed of two heterogeneous subunits and derived from genus Rhodococcus; Japanese Patent Application Laid-open No. 119778/1990 discloses a nitrile hydratase gene composed of two heterogeneous subunits and derived from genus Rhodococcus; and European Patent Application Publication No. 444,639 discloses a nitrile hydratase gene composed of two heterogeneous subunits and derived from genus Pseudomonas; and European Patent application Publication No. 455,646 discloses a nitrile hydratase gene composed of two heterogeneous subunits and derived from Rhodococcus rhodochrous.
For the purpose of preparing a bacterial catalyst with a higher catalytic activity, the present inventors have made investigations so as to produce a large quantity of a protein having an extremely high hydration activity of nitriles, namely nitrile hydratase activity, in a transformant via recombinant DNA technology. Consequently, the inventors have isolated and purified for the first time a novel protein useful for such an objective (often referred to as "nitrile hydratase protein", "nitrile hydratase AM24 protein", or "AM 24 protein" hereinbelow). Furthermore, the present inventors have separated and isolated the gene encoding the protein. Additionally, they have integrated the gene into an expression vector to generate a transformant, and have successfully achieved the large scale production of the nitrile hydratase protein via the transformant. Thus, the inventors have accomplished the present invention.

Protein having nitrile hydratase activity obtained from rhizobium, gene encoding the same, and a method for producing amides from nitriles via a transformant containing the gene


An interior cover mount assembly includes a base member and an interior cover including a clip and the clip includes an arm section and a head section having a width greater than that of the arm section. The base member has an insertion stopper hole through which the head section is inserted and a projection projecting from the base member toward the interior cover and disposed near the holding section. The insertion stopper hole includes an insertion section through which the head section is inserted and a holding section having a width smaller than that of the head section and greater than that of the arm section and where the arm section is arranged. In the interior cover that is mounted on the base member, the clip is fit in the insertion stopper hole such that the head section overlaps the holding section and the projection in the mounting direction.

An interior cover may be attached to a vehicle interior component such as a door trim as a separate component from the vehicle interior component to improve design of the vehicular interior component. The interior cover may be fit on the vehicle interior component from a vehicular interior side. One example of such an interior cover may be a grip cover of a door grip and such a grip cover is attached to a grip base member. The interior cover may be detached from the grip base member due to a holding force of a passenger or shock caused by a collision.


A gel formulation is combined with a fungicidal concentrate which is a liquid mixture of about 1.2 to 16 ml parts by volume of ultra pure water having an electrical resistance of 16–26 megohms, total dissolved solids of less than 0.04 parts per million and a specific conductance of less than 0.10 mho with about 1.2 to 16 parts by volume of Willard Water as prepared in accordance with U.S. Pat. No. 3,893,943, together with one liter of a gel formulation ingredient containing 10% by weight urea, based on the weight of the gel formulation. The fungicidal liquid concentrate is applied directly to a fungal nail to soften the fungal nail and control the growth of fungi.

Willard Water is set forth in U.S. Pat. No. 3,893,943 as a novel catalyst and its preparation is therein described. Willard Water has a poor shelf life insofar as its use in a fungicidal solution. A concentrate is needed that will provide an extended shelf life and will be useful to treat a nail bed that is contaminated with fungi.

Fungicidal gel and method for controlling nail fungi