A method for operating a measuring point for determining at least one measured variable of a medium is disclosed. The measuring point includes a base unit, which is connected releasably with a sensor unit, and which is provided for communication of a signal representing the value of the measured variable to a process monitoring facility. The following steps are included: at least one-time registering and storing in the base unit a value of a diagnostic parameter stored in the sensor unit or produced by the sensor unit; on the basis of this value conforming a prognosis value or prognosis interval stored in the base unit, and storing the conformed prognosis value or prognosis interval in the base unit in place of the previously stored prognosis value or prognosis interval.

Measuring points of this type include, for example, pH measuring points or other measuring points of analytical measurements technology. In this category belong, especially, other potentiometric, amperometric, coulometric, colorimetric, photometric, turbidimetric and spectrometric units.
The problem to which the invention is directed will be explained on the basis of an example of pH measuring points. It is not intended, however, that the invention be limited to a method for operating pH measuring points.
A sensor unit includes at least one transducer, which outputs an electrical signal dependent on the value of the measured variable. Frequently, the transmit function of the transducer is variable. This is true in special measure for pH sensors. Therefore, pH sensors, or pH electrodes, must, at suitable points in time, be subjected to maintenance, especially, it must be calibrated anew. The length of time intervals between the maintenance procedures, or calibration intervals, depends strongly on the environmental influences, to which the sensor is exposed during its lifetime. Also, the total lifetime of the sensor is strongly influenced by these environmental conditions.
The term, "calibrating", has frequently a somewhat different meaning in pH measuring than usual. In general, one means with "calibrating" the checking of the display of a measuring device against a standard; the deviation between true value and display value is detected. The conforming of the display value to the true value is referred to as adjusting. "Calibrating" in the case of a pH sensor is strictly an adjusting. Since the term, "calibrating", is widely used in electrochemistry, it is also used here.
In the guidelines VDI/VDE 2650 and NAMUR NE107, recently, future market developments in the area of sensor diagnostics are emphasized.
The state of the art contains attempts to equip sensors with intelligent self-diagnosis. Thus, there are first publications with reference to analysis of individual sensor characteristics for ascertaining the period of time until the entering of a defined sensor state in the future, e.g. the end of the sensor lifetime or a point in time, at which a new calibrating is necessary. Cited by way of example are DE 10141408, JP 05-209858, JP 2002-228495, DE 10 2004 012420 and DE 10239610.
The described methods in the named publications operate on the assumption that the behavior of a sensor in a medium with essentially known ingredients and in the case of known environmental conditions can be sufficiently well described by a model. Actually, however, the relationships are a number of times more complex, so that a mapping via a model of the processes, which influence the transmit function of a sensor, especially, a pH electrode, is not, or, at most, only with large effort, possible.
pH glass electrodes embodied as single-rod, measuring chains are subject to wear, which depends, in large part, on pH value and temperature of the environment. Besides the glass membrane, also the reference half-cell of a glass electrode is strongly loaded. While, at the glass membrane, due to media influences, a gradual deterioration takes place and thereby the probability for a sensor failure increases, diaphragm changes, poisoning and deterioration of the reference electrolyte of the reference half-cell can also degrade the functionality of the sensor.
Due to the large number of parameters, which determine the lifetime, or service life, of a sensor, prediction is difficult, the more so, since also a considerable scatter from sensor instance to sensor instance of the same type occurs.

ENDRESS + HAUSER CONDUCTA GESELLSCHAFT FUR MESS—UND REGELTECHNIK MBH + CO. KG


Disclosed is an apparatus for holding a bin-liner on a barbecue grill assembly. The apparatus includes a supporting unit and two frames. The supporting unit is connected to the barbecue grill assembly. The first frame is pivotally connected to the barbecue grill assembly. An upper portion of the bin-liner can be flipped and placed on the first frame. The second frame is pivotally connected to the first frame. The first frame is kept in a horizontal position as the second frame is supported on the supporting unit.

1. Field of Invention
The present invention relates to a barbecue grill assembly and, more particularly, to an apparatus for holding a bin-liner on a barbecue grill assembly.
2. Related Prior Art
In a barbecue party, people enjoy cooperating with one another to cook food and enjoy the cooked food. A barbecue party that often takes place in an outdoor environment is more relaxing than a feast that often takes place in a restaurant. Hence, barbecue parties are very popular in close friends and families. Therefore have been devised many barbecue grill apparatuses.
After a barbecue party, there are often leftovers and garbage such as used brushes, sticks and paper napkin, disposable plates, bowls and cups, and empty bottles. Such garbage is often placed in a bin-liner. As mentioned above, a barbecue party often takes place in an outdoor environment, and in an outdoor environment, there is often wind strong enough to blow away the bin-liner, throw the garbage out of the bin-liner, and cause a mass.
Therefore, the present invention is intended to obviate or at least alleviate the problems encountered in prior art.

Apparatus for holding a bin-liner on a barbecue grill assembly


A suction device includes a suction cup having a peg extending therefrom and a transverse shaft extending in opposite directions from the peg, an inner cap positioned on the suction cup and retaining a spring that applies a restoring force to the suction cup, and an outer cap positioned on the inner cap and defining inclined slots in which the opposite ends of the shaft are movably received, respectively. By rotating the outer cap with respect to the inner cap causes camming action between each inclined slot and the respective end of the shaft, which in turn imposes a driving force on the peg to deform the suction cup thereby inducing a suction force. An elongate flexible member has a first end coupled to the inner cap and an opposite second end rotatably supporting an article receptacle in which an article, such as mobile phone and a personal digital assistant can be received and retained.

1. Field of the Invention
The present invention generally relates to a manually-operated suction device, and in particular to a suction device that attaches/separates an article, such as a mobile phone and a personal digital assistant (PDA), to/from a smooth flat surface by rotating a rotatable cap to cause/release deformation of a suction cup, which induces a suction force between the cup and the surface due to pressure difference.
2. The Related Art
It is common to retain a mobile phone or a PDA on a designated sites, such as inside a car or on a office table, by a mobile phone holder, to allow a mobile phone user to take an incoming call or make an outgoing call without hand holding the phone, whereby the user is allowed to proceed with what is being done without interference caused by operating the phone.
A conventional mobile phone holder employs fasteners, such as bolts, to fix the holder to the designated site. Using bolts to fix the mobile phone holder usually causes damage to the surface to which the holder is attached. Further, the holder is not allowed to readily move to other sites. Another way to fix the mobile phone holder to a fixed surface is employing adhesives to adhesively attach the holder to the surface. Similarly, fixing the holder with adhesives does not allow the holder to be readily moved. In addition, an adhesive mark is often left on the fixed surface once the holder is removed from the fixed surface. Such a mark is difficult to clean off.
Another conventional device for fixing a mobile phone holder to a fixed surface is a suction cup, which comprises a deformable cup that deforms to induce pressure difference by which a suction force is caused to fix the holder. The suction force is generally dependent upon the projected area of the cup. A small cup usually leads to a small and insufficient suction force that cannot firmly and stably supports a mobile phone or other objects. However, a large cup requires a large footprint on the fixed surface, which causes inconvenience in operating the suction cup. In addition, the large cup often deteriorates overall surface aesthetics, due to occupation of large space.
Thus, it is desired to have a suction device that overcomes the problems discussed above.


A substrate includes adjacent first and second pixel regions defined by first and second gate lines extending in a first direction and a data line extending in a second direction that crosses the gate lines. First and second driving thin film transistors formed in the first and second pixel regions, respectively, are connected to the data line. A first synchronization adjusting thin film transistor formed in the first pixel region and is connected to the second gate line. A first connection line is connected to the first driving thin film transistor and the first synchronization adjusting thin film transistor. The first connection line overlaps a conductive line along a direction of extension of the conductive line. First and second pixel electrodes are connected to the first synchronization adjusting thin film transistor and the second driving thin film transistor, respectively.

1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for a liquid crystal display (LCD) device and a manufacturing method of the same.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) device utilizes the optical anisotropy and birefringence properties of liquid crystal molecules to display images. The liquid crystal display (LCD) device usually has first and second substrates spaced apart from and opposing each other. The first and second substrates respectively have electrodes for forming an electric field between the electrodes. That is, if voltage is applied to the electrodes of the liquid crystal display (LCD) device, an electric field is formed between the electrodes and the electric field changes alignments of the liquid crystal molecules. The changed alignments of the liquid crystal molecules control a light transmittance through the liquid crystal and thus images can be displayed by controlling the light transmittance through the liquid crystal.
FIG. 1 is an exploded perspective view of a related art liquid crystal display (LCD) device. In FIG. 1, a liquid crystal display (LCD) device 11 has an upper substrate 5 having a black matrix 6, a color filter layer 8, and a common electrode 18 on the color filter layer 8, and a lower substrate 22 having a switching element T and a pixel electrode 17 at each pixel region P defined on the lower substrate 22. A liquid crystal layer 14 is interposed between the upper substrate 5 and the lower substrate 22.
Array lines are formed around the pixel region P. The lower substrate 22 may be commonly referred to as an array substrate. Thin film transistors T are arranged in a matrix form as the switching element, and are disposed crossing portions of gate and data lines 13 and 15. The gate and data lines 13 and 15 define the pixel region P by crossing each other, and in the pixel region P, the transparent pixel electrode 17 is formed. The pixel electrode 17 is formed of transparent conductive metal material such as indium tin oxide (ITO) that relatively reflects light well.
A storage capacitor C connected to the pixel electrode 17 in parallel is formed over the gate line 13. A portion of the gate line 13 serves as a first storage electrode and a metal layer 30 formed of the same material as source and drain electrodes serves as a second storage electrode. The metal layer 30 is connected to the pixel electrode 17, and receives signals of the pixel electrode 17.
The number of array lines and driving integrated circuits of the LCD device having the above structure increase as the size of the device increases or the resolution of the device increases.
To reduce the number of driving integrated circuits, a method for driving two pixels by using one data line and one gate line has been researched.
In this method, time variation is generated in two pixels commonly connected to one data line by switching a thin film transistor on and off, and thus sequential data signals are applied to the two pixels.
However, the method needs more thin film transistors at each pixel as compared with a general structure. This decreases an aperture ratio of the device. In addition, the numbers of thin film transistors are asymmetric in adjacent pixels with respect to the data line commonly contacted by the adjacent pixels.
FIG. 2 is a plan view showing an array substrate for a liquid crystal display device having a data line sharing structure according to a first embodiment of the related art.
As shown in FIG. 2, gate lines 31 are formed on a substrate 30 in a first direction and a data line 46 is formed in a second direction. The gate lines 31 and the data line 46 perpendicularly cross each other to define a first pixel region P1 and a second pixel region P2. Transparent pixel electrodes 52 and 54 are formed in the first and second pixel regions P1 and P2, respectively.
A driving thin film transistor (TFT) Ts is formed in each pixel region P1 and P2. A synchronization adjusting thin film transistor (TFT) Tc is formed in the first pixel region P1, and inputs signals from the driving TFT Ts to the pixel electrode 52. The synchronization adjusting TFT Tc can be formed in one of two pixel regions, which are referred to as an odd pixel region or an even pixel region, adjoining each other with respect to a particular data line 46.
The driving TFTs Ts formed in the adjacent pixel regions P1 and P2 are connected to the same data line 46. Different signals are transmitted through the data line 46. The synchronization adjusting TFT Tc is formed to sequentially transmit the different signals.
Each driving TFT Ts includes a gate electrode 32a, an active layer 38a, a source electrode 42a, and a drain electrode 44a. The synchronization adjusting TFT Tc includes a gate electrode 32b, an active layer 38b, a source electrode 42b, and a drain electrode 44b.
A common line 36 is formed parallel to and spaced apart from the gate lines 31, and traverses the first and second pixel regions P1 and P2. A metal pattern 45 is formed over the common line 36 in each pixel region P1 and P2. The metal pattern 45 is connected to each pixel electrode 52 and 54. Thus, a storage capacitor Cst is formed in each pixel region P1 and P2. The common line 36 functions as a first electrode and the metal pattern 45 acts as a second electrode of the storage capacitor Cst.
In the pixel region P1 where the driving TFT Ts and the synchronization adjusting TFT Tc are formed, the driving TFT Ts and the synchronization adjusting TFT Tc are connected to adjacent gate lines 31, respectively, and thus are spaced apart from each other.
Accordingly, in the first pixel region P1, the first drain electrode 44a of the driving TFT Ts and the second source electrode 42b of the synchronization adjusting TFT Tc are connected to each other through a connection line 48.
Since the additional connection line 48 is formed, the aperture ratio of the pixel region containing the additional connection line 48 and synchronization adjusting TFT Tc is decreased.
FIGS. 3 and 4 show cross-sections of an array substrate for a liquid crystal display device according to the first embodiment of the related art. FIG. 3 is a cross-sectional view along the line III—III of FIG. 2 and FIG. 4 is a cross-sectional view along the line IV—IV of FIG. 2.
As shown in FIGS. 3 and 4, first and second pixel regions P1 and P2 are defined on a substrate 30. A driving TFT Ts is formed in each pixel region P1 and P2, and a synchronization adjusting TFT Tc is formed in the first pixel region P1. The synchronization adjusting TFT Tc is connected to the driving TFT Ts in the first pixel region P1. The driving TFT Ts and the synchronization adjusting TFT Tc are simultaneously formed through the same process.
More particularly, a gate electrode 32a for the driving TFT Ts and a gate electrode 32b for the synchronization adjusting TFT Tc are formed on the substrate 30. Although not shown in the figures, gate lines are formed of the same material in the same layer as the gate electrodes 32a and 32b. The gate lines are spaced apart from each other, and are connected to the gate electrodes 32a and 32b, respectively.
A gate insulating layer 33 is formed on the gate electrodes 32a and 32b, and active layers 38a and 38b and ohmic contact layers 40a and 40b are formed by sequentially depositing intrinsic amorphous silicon and impurity-doped amorphous silicon and then patterning these layers.
Source electrodes 42a and 42b and drain electrodes 44a and 44b are formed on the ohmic contact layers 40a and 40b. The source electrodes 42a and 42b are near by and spaced apart from the drain electrodes 44a and 44b, respectively. At the same time, a connection line 48 is formed to connect the drain electrode 44a of the driving TFT Ts with the source electrode 42b of the synchronization adjusting TFT Tc in the first pixel region P1.
Next, a passivation layer 50 is formed by depositing an inorganic insulating material such as silicon nitride (SiNx) and silicon oxide (SiO2) on an entire surface of the substrate 30 including the source electrodes 42a and 42b and the drain electrodes 44a and 44b of the driving TFT Ts and the synchronization adjusting TFT Tc thereon.
Pixel electrodes 52 and 54 are formed on the passivation layer 50 in respective pixel regions P1 and P2. The pixel electrode 52 of the first pixel region P1 is connected to the driving TFT Ts and the synchronization adjusting TFT Tc and the pixel electrode 54 of the second pixel region P2 is connected to the driving TFT Ts.
As stated above, the connection line 48 connecting the driving TFT Ts and the synchronization adjusting TFT Tc occupies a portion of the first pixel region P1 and thus both substantially reduces the aperture ratio of the LCD device and causes non-uniform brightness in adjacent pixels with respect to the data line 46. Thus, the quality of the images produced is lowered.
FIG. 5 is a plan view showing an array substrate for a liquid crystal display device according to a second embodiment of the related art. The array substrate of the second embodiment also has the above-mentioned problems.
As shown in FIG. 5, gate lines 61 are formed in a first direction on a substrate 60, and data lines 76 are formed in a second direction crossing the first direction. The gate lines 61 and the data lines 76 perpendicularly cross each other to define a plurality of pixel regions P.
In each pixel region P, a driving TFT Ts and a synchronization adjusting TFT Tc are formed. The driving TFT Ts includes a gate electrode 62a, an active layer 66a over the gate electrode 62a, and source and drain electrodes 70a and 72a spaced apart from each other over the active layer 66a. The synchronization adjusting TFT Tc includes a gate electrode 62b, an active layer 66b over the gate electrode 62b, and source and drain electrodes 70b and 72b spaced apart from each other over the active layer 66b. Additionally, a transparent pixel electrode 80 is formed in each pixel region P.
The drain electrode 72a of the driving TFT Ts is connected to the source electrode 70b of the synchronization adjusting TFT Tc through a connection line 74, and the drain electrode 72b of the synchronization adjusting TFT Tc is connected to the pixel electrode 80.
In this embodiment, adjacent pixel regions up and down in the context of the figure are commonly connected to a single gate line 61 and receive signals. Therefore, to sequentially apply the signals to the pixels, the driving TFT Ts and the synchronization adjusting TFT Tc are formed in one pixel region P. The driving TFT Ts and the synchronization adjusting TFT Tc in the same pixel region P are connected to different gate lines 61.
A common line CL is also formed in the pixel region P and is spaced apart from and parallel to the gate line 61.
A storage capacitor Cst is formed over the common line CL. A part of the common line CL functions as a first electrode and an extension part 75 extending from the drain electrode 72b of the synchronization adjusting TFT Tc acts as a second electrode of the storage capacitor Cst.
The aperture ratio of the LCD device according to this embodiment is also reduced due to the connection line 74 for connecting the driving TFT Ts and the synchronization adjusting TFT Tc.
FIGS. 6 and 7 show cross-sections of an array substrate for a liquid crystal display device according to the second embodiment of the related art. FIG. 6 is a cross-sectional view along the line VI—VI of FIG. 5 and FIG. 7 is a cross-sectional view along the line VII—VII of FIG. 5.
As shown in the figures, a driving TFT Ts and a synchronization adjusting TFT Tc are formed in each pixel region P, which is defined on a substrate 60.
A gate electrode 62a of the driving TFT Ts and a gate electrode 62b of the synchronization adjusting TFT Tc are formed on the transparent insulating substrate 60. A gate insulating layer 64 is formed on the gate electrodes 62a and 62b, and active layers 66a and 66b and ohmic contact layers 68a and 68b are formed on the gate insulating layer 64 by sequentially depositing amorphous silicon (a-Si:H) and doped amorphous silicon (n+ or p+ a-Si:H) and then patterning them.
Source electrodes 70a and 70b and drain electrodes 72a and 72b are formed on the ohmic contact layers 68a and 68b. The source electrodes 70a and 70b are spaced apart from the drain electrodes 72a and 72b, respectively. At the same time, a connection line 74 is formed to connect the drain electrode 72a of the driving TFT Ts with the source electrode 70b of the synchronization adjusting TFT Tc. A data line 76 is also formed of the same material as the source electrodes 70a and 70b and the drain electrodes 72a and 72b and is connected to the source electrode 70a of the driving TFT Ts.
A passivation layer 78 is formed on an entire surface of the substrate 60 including the source electrodes 70a and 70b and the drain electrodes 72a and 72b, and exposes the drain electrode 72b of the synchronization adjusting TFT Tc. A pixel electrode 80 is formed on the passivation layer 78 and is connected to the exposed drain electrode 72b.
In the above structure, the aperture ratio is reduced because the connection line 74 for connecting the driving TFT Ts and the synchronization adjusting TFT Tc still occupies a part of the aperture area.
Thus, in each of the related art substrates above, the pixel electrodes do not cover substantially all of the pixel regions. Although not drawn to scale, between about 5–10% of the aperture area is lost due to the connection line being formed in the pixel region.
A vertical electric field mode LCD device is described in the first and second embodiments of the related art, and an in-plane switching (IPS) mode LCD device will be explained hereinafter with reference to FIGS. 8 to 10.
The IPS mode LCD device has a wider viewing angle than the vertical electric field mode LCD device of the first and second embodiments. However, since a common electrode and a pixel electrode are formed in one pixel, the IPS mode LCD device has a reduced aperture ratio.
FIG. 8 is a plan view showing an array substrate for an IPS mode LCD device of the related art.
As shown in FIG. 8, gate lines 94 are formed on a substrate 90 in a first direction and a data line 110 is formed in a second direction. The gate lines 94 and the data line 110 perpendicularly cross each other to define a first pixel region P1 and a second pixel region P2. A common line 96 is formed parallel to the gate lines 94, and traverses the first and second pixel regions P1 and P2.
A driving TFT Ts is formed in each pixel region P1 and P2 and a synchronization adjusting TFT Tc is formed in the first pixel region P1. The synchronization adjusting TFT Tc can be formed in one of the two pixel regions (the odd pixel region and the even pixel region, above) adjoining each other with respect to a single data line 110.
Pixel electrodes 114a and 114b are formed in the pixel regions P1 and P2, respectively. The pixel electrode 114a of the first pixel region P1 is connected to the synchronization adjusting TFT Tc and the pixel electrode 114b of the second pixel region P2 is connected to the driving TFT Ts. The pixel electrodes 11 4a and 11 4b are parallel to the data line 110. Additionally, a common electrode 98 is formed in each pixel region P1 and P2. The common electrode 98 includes a plurality of patterns, which are parallel to the pixel electrodes 114a and 114b and alternate with the pixel electrodes 114a and 114b in respective pixel regions P1 and P2.
A storage capacitor Cst is formed over the common line 96 in each pixel region P1 and P2. A part of the common line 96 functions as a first electrode and an extension part DL extending from each pixel electrode 114a and 114b acts as a second electrode of the storage capacitor Cst.
The adjacent pixel regions P1 and P2, left and right in the context of the figure, receive signals from the same data line 110. To sequentially transmit the signals, the synchronization adjusting TFT Tc is formed in one of the pixel regions P1 and P2 as stated above.
Therefore, a connection line 112 is formed in the first pixel region P1 to connect a drain electrode 108a of the driving TFT Ts with a source electrode 106b of the synchronization adjusting TFT Tc, and the aperture ratio is accordingly decreased.
FIGS. 9 and 10 show cross-sections of an array substrate for an IPS mode LCD device of the related art. FIG. 9 is a cross-sectional view along the line IX—IX of FIG. 8 and FIG. 10 is a cross-sectional view along the line X—X of FIG. 8.
As shown in FIGS. 9 and 10, pixel regions P1 and P2 are defined on a substrate 90. A synchronization adjusting TFT Tc is formed in one of the pixel regions P1 and P2, for example, in the pixel region P1.
More particularly, a gate electrode 92a for the driving TFT Ts and a gate electrode 92b for the synchronization adjusting TFT Tc are formed on the substrate 90. Although not shown in the figures, gate lines, a common line 96 and common electrodes 98 are formed of the same material in the same layer as the gate electrodes 92a and 92b. The gate lines are spaced apart from each other, and are connected to the gate electrodes 92a and 92b, respectively. The common line 96 is parallel to and spaced apart from the gate lines. As shown in FIG.8, the common electrodes 98 vertically extend from the common line 96.
A gate insulating layer 100 is formed on the gate electrodes 92a and 92b, and active layers 102a and 102b and ohmic contact layers 104a and 104b are sequentially formed on the gate insulating layer 100 over the gate electrodes 92a and 92b.
Source electrodes 106a and 106b and drain electrodes 108a and 108b are formed on the ohmic contact layers 104a and 104b. The source electrodes 106a and 106b are spaced apart from the drain electrodes 108a and 108b, respectively. A data line 110 and a connection line 112 are formed of the same material in the same layer as the source electrodes 106a and 106b and the drain electrodes 108a and 108b. The data line 110 is connected to the source electrodes 106a and 106b and the connection line 112 is connected to the drain electrode 108a of the driving TFT Ts and the source electrode 106b of the synchronization adjusting TFT Tc in the pixel region P1.
Meanwhile, pixel electrodes 114a and 114b are formed in the pixel regions P1 and P2. Although not shown in FIGS. 9 and 10, the pixel electrode 114a of the pixel region P1 is connected to the synchronization adjusting TFT Tc and the pixel electrode 114b of the pixel region P2 is connected to the driving TFT Ts. The pixel electrodes 114a and 114b are parallel to and alternate the common electrodes 98.
However, as stated above, the connection line 112 is formed in the pixel region P1, thereby reducing the aperture ratio of the device.

Array substrate with driving TFT and synchronization adjustment TFT


An efficient technique for storing, updating, locating, and retrieving data is provided. In particular, data may be stored in a persistent, user-defined, shareable in-memory database table. Once this in-memory database table is created and loaded with data, data may be located in the table. When a search request specifying a number of results to be retrieved from a desired starting point is received, the data is located in an in-memory database table. Then, the specified number of results from a desired starting point are returned. Furthermore, data that is accessed via an in-memory database table is updated upon receiving an update request. The data that is updated may either be data in a data area of the in-memory database table or may be relational data. When data is updated, a high speed index used to access the in-memory database table is also updated.

Databases are computerized information storage and retrieval systems. A Relational Database Management System (RDBMS) is a database management system (DBMS) which uses relational techniques for storing and retrieving data. Relational databases are organized into physical tables which consist of rows and columns of data. The rows are formally called tuples. A database will typically have many physical tables and each physical table will typically have multiple tuples and multiple columns. The physical tables are typically stored on random access storage devices (RASD) such as magnetic or optical disk drives for semi-permanent storage. Additionally, logical tables or "views" can be generated based on the physical tables and provide a particular way of looking at the database. A view arranges rows in some order, without affecting the physical organization of the database.
RDBMS software using a Structured Query Language (SQL) interface is well known in the art. The SQL interface has evolved into a standard language for RDBMS software and has been adopted as such by both the American National Standards Institute (ANSI) and the International Standards Organization (ISO).
The SQL interface allows users to formulate relational operations on the tables either interactively, in batch files, or embedded in host languages, such as C and COBOL. SQL allows the user to manipulate the data. The definitions for SQL provide that a RDBMS should respond to a particular query with a particular set of data given a specified database content, but the method that the RDBMS uses to actually find the required information in the tables on the disk drives is left up to the RDBMS. Typically, there will be more than one method that can be used by the RDBMS to access the required data. The RDBMS will optimize the method used to find the data requested in a query in order to minimize the computer time used and, therefore, the cost of performing the query.
One way to optimize retrieval of data is to use an index. An index is an ordered set of references to the records or rows in a database file or table. The index is used to access each record in the file using a key (i.e., one of the fields of the record or attributes of the row). When data is to be retrieved, an index is used to locate records. Then, the data is sorted into a user-specified order and returned to the user. Additionally, if a join operation is involved, the join operation is performed prior to retrieving data and sorting. Although conventional indexes are useful, they are only useful in locating data. Next, the data must be retrieved from a data store (e.g., a database or file system).
It is typically very time consuming to retrieve data. The amount of time required to access data stored within databases and/or file systems is adversely affected by I/O (i.e., input/output) sub-system performance and cache designs. A cache is a high speed data storage mechanism that may be implemented as a portion of memory in a computer. Data that may be used more than once may be retrieved from a data store and stored in a cache for easy and quick access. Current cache designs do not guarantee that desired data will be present in memory when needed. When desired data is not in a cache, additional time is required to retrieve data from I/O sub-systems. This causes delays and fluctuations in access times needed to retrieve desired data.
FIG. 1 is a diagram illustrating a basic data store design using a non-persistent cache area. A user submits search requests 100, which are forwarded to a search engine 102. A search request 100 is, for example, a SQL query. The search engine 102 attempts to locate the data in the relational non-persistent cache 104. The term "non-persistent" indicates that the cache 104 in this example is non-persistent (i.e., the data is stored temporarily). If the search engine 102 locates the data in the relational non-persistent cache 104, the search engine 102 retrieves the data and returns search results 112. If the search engine 102 does not locate the data in the relational non-persistent cache 104, the search engine 102 uses the relational index 106 to retrieve relational data 110 from a data store and return search results 112. Therefore, some of the search results 112 may be provided from relational non-persistent cache memory, but this is not guaranteed. The relational non-persistent cache 104 is limited in size. Also, the relational index 106 and relational data 110 are located on magnetic media, and so I/O resources are needed to access this data. The relational data 110 may be in the form of a file.
There are many disadvantages to using this technique. In particular, the relational non-persistent cache typically contains data that has been received in response to prior requests for data. In many cases, users submit requests for data that was not recently received. In these cases, the data is retrieved from the basic data store. Accessing data from this basic data store typically uses up system resources for I/O. This conventional system has performance, capacity and cost issues as data stores and user load increase in size.
Thus, there is a need in the art for an improved technique of storing, updating, locating, and retrieving data.

International Business Machines Corporation


The present invention discloses an apparatus for suppressing stimulated Brillouin scattering and the method thereof that a threshold fiber input power is raised in order to prevent loss of an inputted light by stimulated Brillouin scattering being generated in a case that a signal having a strong intensity is inputted to the optical fiber and so a light signal having more strong intensity can be inputted to the optical fiber. The apparatus for suppressing the SBS includes a plurality of first transmission unit, each of which has a wavelength separation, for transmitting information signals through a signal channel; and a second transmission unit for generating and transmitting a supervisory signal of which a modulation frequency and an intensity generates a phase modulation to the plurality of information signals, through a supervisory channel. The modulation frequency and the intensity of the supervisory signal are modulated in phase to the information signals by a cross phase modulation effect, thereby broadening a line width of the information signal.

Methods for suppressing stimulated Brillouin scattering (SBS) in a conventional art will be described as follows.
In a SBS suppression method, a separate phase modulator is used for generating a frequency chirp of signal, thereby extending a width of spectrum.
However, in the conventional method using such a phase modulator, there is a disadvantage that besides an intensity modulator used for modulating signal, an additional phase modulator must be used.
In a second SBS suppression method, in a wavelength division multiplexing (WDM) link, a width of spectrum is extended by a phase modulation through a cross phase modulation (XPM) between signal channels.
An example of the second SBS suppression method is described in a paper, Y. Horiuchi et al., "SBS suppression effects induced by XPM in high power WDM repeaterless transmission," Electronics Letters, vol.34, no.4, p390–391, 1998.
In the above example, the SBS generated in a wavelength division multiplexing (WDM) link of 2.5 Gb/s×8 channels is suppressed by using a cross phase modulation (XPM). As a result, although a power of +18 dBm per a channel is inputted, the SBS is not generated, thereby transmitting a signal through pure silica core fibers (SMF) of 423 km without using a repeater.
However, in the wavelength division multiplexing (WDM) link, the use of the conventional method using a phase modulation effect by cross phase modulation between the signal channels is limited, because conditions generating a phase modulation effect are determined by a transmission speed and a light intensity between each signal channel within the wavelength division multiplexing WDM channel, in a case that the transmission speed and a light intensity are changed, the phase modulation effect is also changed.
In a third method, a low frequency and a modulated amplitude are applied to a semiconductor laser, thereby extending a width of a spectrum.
The above example is described in U.S. Pat. No. 5,329,396 filed by D. A. Fishman, entitled as "Reduction of stimulated Brillouin scattering in a fiber having reduced Brillouin scattering", and issued on Jul. 12, 1994.
In such an example, as a method that a critical value of stimulated Brillouin scattering (SBS) being generated in an optical fiber is raised up, a waveform of a low frequency is applied to a general laser diode (LD) and modulated it and so a valid line width of the laser diode (LD) is extended, thereby raising up the critical intensity of stimulated Brillouin scattering.
However, although the conventional method for applying a low frequency and a modulated amplitude to the semiconductor laser is widely used, in a case that a direct modulation can not apply, like an optical fiber laser, it is impossible to adapt.
In a fourth method, a duobinary method is used as a modulation method.
The above example is described in U.S. Pat. No. 5,917,638 filed by F. Thorkild et al., entitled as "Duo-binary signal encoding", and issued on Jun. 29, 1999.
In the above example, in order to raise up the threshold of stimulated Brillouin scattering (SBS) phenomenon, a duobinary modulation method is used as a modulation method of a transmission light, thereby raising up the threshold of stimulated Brillouin scatting SBS. By using this method, when comparing it to the conventional binary modulation method, the threshold of stimulated Brillouin scattering (SBS) is increased by 12.6 dB at a transmission speed of 10 Gb/s and at this time, power penalty is less than 1 dB.
However, in the conventional method using the duobinary modulation method, a new method, unlike the conventional modulation method, must be used, the implementation method is complicate and its technology is not yet completed until now.
In a fifth method, there is a method that an optical fiber in which stimulated Brillouin scattering dose not well generated is used.
The above example is described in U.S. Pat. No. 5,851,259 filed by J. B. Clayton et al., entitled as "Method for making Ge-doped optical fibers having reduced Brillouin scattering", and issued on Dec. 22, 1998.
In the above example, when making an optical fiber being added germanium Ge, in case that a properly modulated tension is applied, stimulated brillouin scattering can be suppressed without a loss of the optical fiber and a large change of a value of dispersion. At this time, the used tension is modulated by 10–50 g in a low case and 150–200 g in a high case.
However, in the conventional method using an optical fiber in which stimulated brillouin scattering SBS does not generated in well, there are several disadvantages that a conventional optical fiber can not be used and all optical fibers must be embedded in new.

Apparatus and method for stimulated Brillouin scattering suppression using supervisory channel

Electronics and Telecommunications Research Institute


A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.

1. Field of the Invention
The invention relates to the phase change memory, and more particularly to the reference memory unit of the phase change memory.
2. Description of the Related Art
With the growth in the use of portable electronic devices, demand for non-volatile memory has increased. Among all kinds of emerging non-volatile memories, phase change memory is the most promising candidate for the next generation non-volatile memory due to its higher speed, lower power consumption, higher capacity, reliability, easier process integration and lower cost.
Phase change memory is based on the fast and reversible phase transitions of chalcogenide alloy which result in a highly resistive amorphous state and low resistive crystalline state, i.e. the logic data of 1 and 0. Thus, an adequate read circuit is desirable for correctly and reliably sensing the programmed data of the phase change memory. Typically a memory system comprises a reference memory array and a primary memory array. The unit cells in the reference memory array generate reference signals which are different from the signals generated by the programmed bits in the primary memory array. The read circuit is thus used to compare the reference signals with the signals from the primary memory array such that the programmed data in the primary memory array can be identified. To avoid a wrong sensing of the programmed state due to the reference signal error, it is important to develop an ideal reference memory array.
The ideal reference memory array must have the characteristics: (1) easy implementation without additional processes or complicated circuit design; (2) high reliability and stability, i.e. the reference memory array has a high tolerance to the memory state variation of the phase change memory; (3) flexibility and compatibility with memory array.
FIG. 1 is a schematic diagram of a conventional memory array with a parallel-connected reference memory array announced by Ovonyx Inc. in 2001. The phase change memory 100 comprises a primary memory array, columns C1 to C4, a reference memory array 130, columns C5 and C6, and a comparison circuit 140. The primary memory array 120 comprises a plurality of the memory units 121 and the reference memory array 130 comprises a plurality of reference memory units 131, wherein the memory units 121 and the reference memory unit 131 have the same structure. When the phase change memory 100 is accessed, the primary memory array 120 provides sensing signals SSE1 to SSE4 corresponding to the memory states and the reference memory array 130 provides a reference signal SRE. The comparison circuit 140 then compares the signals SSE1 to SSE4 with the signal SRE to identify the data stored in the phase change memory 100. In the conventional memory architecture, the reference memory array 130 is implemented by two columns, C5 and C6, parallel connected to the primary memory array 120. The memory units 121 of the primary memory array 120 and the reference memory unit 131 of the reference memory array 130 have the same structure. According to this architecture, however, the reference signal SRE generated by the conventional reference memory array 130 is nest easily adjustable and the reference signal SRE may drift due to process variation. In other words, the reference signal SRE may mix with the sensing signal SSE corresponding to a specific memory state, thus easily leading to a sensing deviation.
Assuming that the memory unite in the primary memory array 120 have two memory states, i.e., high resistance reset state and low resistance set state, the voltage difference between the sensing signal SSE and the reference signal SRE can be respectively given as follows:ΔVreset≡Vsense−Vreference=Iread1×Rreset−Iread2×(Rreset∥Rset)  (1),ΔVset≡Vsense−Vreference=Iread1×Rset−Iread2×(Rreset∥Rset)  (2),
wherein Iread1 is the read current applied to the primary memory array, Iread2 is the read current applied to the reference memory array, Rset is the resistance when the memory unit is in the set stste, and Rreset is the resistance when the memory unit is in the reset state. In order to make sure that the reference signal is approximate to the average of two sensing signals of reset state and set atate, the magnitude of the read current Iread2 is usually twice the magnitude of the read current Iread1. Thus, the equations (1) and (2) can be written as follows:|ΔVreset|=|Vsense−Vreference|=Iread1×[Rreset−2(Rreset∥Rset)]  (3),|ΔVset|=|Vsense−Vreference|=Iread1×[2(Rreset∥Rset)−Rset]  (4).
Since the resistance Rreset is much larger than the resistance Rset, the |ΔVreset| is large enough to be determined. However, the |ΔVset| is relatively small such that the reference signal is more unreliable and a sensing error may occur.


One aspect of the invention provides dietary fiber compositions comprising effective amounts of glucomannan, xanthan gum, and alginate to produce a desired viscosity. The invention also provides food products comprising an effective amount of a dietary fiber composition. In other aspects, the invention provides methods for preparing a dietary fiber composition or a food product comprising a dietary fiber composition, and methods for promoting satiety, promoting weight loss, lowering blood glucose levels, or lowering blood cholesterol levels in a mammal.

Diabetes and hypoglycemia, a condition that may lead to the development of Type 2 diabetes, have become more and more common. It has been found that such conditions are due to increasing insulin resistance of the cells. Diabetic conditions are traditionally managed with insulin injections and various pharmaceuticals to regulate blood sugars. However, diet and weight-loss plays a major role in correcting many metabolic abnormalities associated with diabetes (Yip et al. (2001) Obesity Res. 9:341S-347S). Intake of foods high with high glycemic index is known to lead to overeating and obesity (Ludwig et al. (1999) Pediatrics 103(3):E26). Therefore, it is preferable that any agent used in the management of diabetic conditions as well as weight-loss be low in glycemic index. It is most preferable if such agents reduce the glycemic index of foods.
A reduction in carbohydrate intake is also required in successful management of diabetic conditions. Diet counseling is helpful, but diabetics experience more food cravings as they experience more frequent states of hypoglycemia (Strachan et al. (2004) Physiol. Behav. 80(5):675-82). Additionally, therapies lowering blood glucose levels in diabetic patients are often associated with the undesirable side effect of body weight gain (Schultes et al. (2003) J. Clin. Endocrinol. Metabol. 88(3):1133-41). It has been reported that diets high in soluble fiber may reduce the risk of diabetes through increased insulin sensitivity (Ylonen et al. (2003) Diabetes Care 26:1979-85). This may result from the possible role of dietary fiber in blood sugar regulation. It has also been reported that high viscosity meals produce a greater sense of fullness compared to low viscosity meals (Marciani et al. (2001) Am. J. Physiol. Gastrointest. Liver Physiol. 280:G1227-33).
Thus, there is a need for dietary fiber compositions that assist in the management of diabetic conditions by lowering blood sugar levels and promoting satiety. The present invention addresses this need and others.


An electrophotographic photoconductor contains at least a furan derivate or a thiophene derivate as the charge transport agent in a photoconductive layer thereof.

The present invention relates to a photoconductive layer of the electrophotographic photoconductors used in devices such as printers and copying machines that employ electrophotographic processes. More specifically, the present invention relates to constituent materials of the photoconductive layer.
The photosensitive materials of a conventional electrophotographic photoconductor (hereinafter simply referred to as a "photoconductor") used for devices such as printers, facsimiles, digital copying machines and analog copying machines, that employ electrophotographic processes, include inorganic photoconductive materials such as selenium and selenium alloys, inorganic photoconductive materials such as zinc oxide and cadmium oxide dispersed into a resin binder, organic photoconductive materials such as poly-N-vinylcarbazole and poly(vinyl anthracene), and other organic photoconductive materials such as phthalocyanine compounds and bisazo compounds dispersed into a resin binder or deposited by vacuum deposition.
It is required for the photoconductor to exhibit the functions for retaining surface charges in the dark, for generating electric charges in response to the received light, and for transporting the electric charges in response to the received light. The photoconductor may be classified into two types: 1) the mono-layered-type that exhibits the above described functions by one single photoconductive layer and 2) the so-called laminate-type consists of a layer mainly for charge generation, and a second layer for charge retention in the dark and charge transport in response to the received light.
For image formation by the electrophotographic techniques and with these types of photoconductors, Carlson's process can be applied as an example. The Carlson's process for image formation includes the steps of 1) charging of the photoconductor by corona discharge in the dark, 2) formation of electrostatic latent images of the letters and figures in a manuscript on the charged surface of the photoconductor, 3) development of the electrostatic latent images with toner, and 4) fixing of the developed toner images on a paper and such carriers. The photoconductor is reused after removal of the charge, removal of the residual toner, and removal of the optical charge.
Various image formation steps are employed in the Carlson's process. The corotron method or the scrotron method that uses metal wire and the contact charging method that uses the charging brush or charging roller are adopted for charging the photoconductor. Methods such as the two-components development method, nonmagnetic-single-component development method and magnetic-single-component development method are used in the development step.
Recently, the organic photoconductors have been developed by virtue of the flexibility, thermal stability and ease of film formation thereof. U.S. Pat. No. 3,484,237 discloses a photoconductor that includes poly-N-vinyl carbazole and 2,4,7-trinitrofluorenone. Japanese Unexamined Laid Open Patent Application No. S47-37543 discloses a photoconductor that includes an organic pigment as the main component thereof. Japanese Unexamined Laid Open Patent Application No. S47-10785 discloses a photoconductor that includes an eutectic complex consisting of a dye and resin as the main component thereof. At present, the function-separation-type organic photoconductors, which include a charge generation layer and a charge transport layer, are mainly used. The charge generation layer comprises metal-free phthalocyanine, metal phthalocyanine such as titanyl phthalocyanine or azo compound and a resin binder. The charge transport layer comprises a hydrazone compound, styryl compound, diamine compound or butadiene compound and a resin binder.
Among the function-separation-type photoconductors which laminate a charge generation layer on a conductive substrate and a charge transport layer on to the charge generation layer, negative-charging photoconductors exhibit sensitivity when the photoconductor surface is charged negatively, because the hole contributes to charge transport due to the nature of the charge transport material that functions as the electron donor. However, the corona discharge for negative-charging is unstable compared with the corona discharge for positive-charging. The corona discharge for negative-charging generates ozone and nitrogen oxide. The photoconductor surface is deteriorated physically and chemically by the ozone and nitrogen oxide absorbed thereto. Ozone and nitrogen oxide are very hazardous for the environmental safety. Accordingly, positive-charging photoconductors can be in practice more freely used and more widely used than negative-charging photoconductors.
Various positive-charging photoconductors have been proposed. Some positive-charging photoconductors, which include a single-layered photoconductive layer comprising a charge generation agent and a charge transport agent, both dispersed into a resin binder, have been put into practical use. However, the sensitivity of these positive-charging photoconductors of the single-layered type is not so high enough to be applicable to the high speed machines. More improvements are necessary for repeatedly using the positive-charging photoconductors of the single-layered type.
Laminate-type positive-charging photoconductors for high-speed use may be constructed by laminating a charge generation layer on a charge transport layer. However, corona discharge, light irradiation and mechanical wear pose problems of stability for repeated use of the photoconductor, since the charge generation layer is exposed on the surface of the photoconductor. The protection layer, disposed on the charge generation layer to avoid the mechanical wear of the charge generation layer, is problematic for improving the sensitivity and electrical properties of the photoconductor.
Laminate-type positive-charging photoconductors which include a charge transport layer on a charge generation layer have been proposed. The charge transport materials including 2,4,7-trinitrofluorenone may be used. However, 2,4,7-trinitro-9-fluorenone is a carcinogen. The Japanese Unexamined Laid Open Patent Applications No. S50-131941, No. H06-59483 and No. H06-123986 disclose cyano compounds and quinone compounds as the charge transport agent. Nonetheless, no charge transport agent that can be satisfactorily used for the laminate-type positive-charging photoconductor has yet been obtained.
Although the organic photoconductive materials have many merits which the inorganic photoconductive materials do not have, the conventional organic photoconductive materials do not exhibit all the properties required for electrophotographic photoconductors. It is required to fabricate a highly sensitive photoconductor that exhibits little change in the properties thereof after the photoconductor is continuously used in the electrophotographic apparatus continuous for a long time. Especially, the customer's demands are increasing for photoconductors, which can endure long continuous use in various electrophotographic apparatuses provided the foregoing with various imaging processes. The photosensitivity of the conventional laminate-type photoconductors is insufficient. Practical long use of the conventional laminate-type photoconductors causes charge potential lowering, residual potential rise, sensitivity lowering and such problems to be solved. Thus, a technology that facilitates realizing all the favorable properties for the electrophotographic photoconductor has not been established so far.


Apparatus and method for determining characteristics of a bit stream of binary pulses. The apparatus has control apparatus for defining a window comparator and logic apparatus for accumulating and mapping numbers derived from a count of the number of times the bit stream pulses fall at points inside the window comparator and drawing an eye diagram defining characteristics of the bit stream.

High-speed communication systems typically communicate with each other by sending serial bit streams of data between transmitters and receivers. These bit streams are usually binary coded pulse signals represented by zeros and ones which may be electrical voltages or optical signals derived from the signals created by the transmitters and which pulse coded signals are applied to a transmission facility connecting the transmitters with the receivers. The receivers decode the received pulse code signal data to obtain the information therein.
If a receiver receives pulse code signals that have been deformed by errors occurring in the transmission facility or if the receiver improperly decodes the received pulse coded signals, the effect is that bit errors may occur in the communications thereby resulting in wrong information being received by the receiver. Thus, designers, engineers, installers and maintenance personal need to evaluate the stream of pulse coded signals, oftentimes called binary pulse bit streams, to monitor system performance and to help in diagnosing system problems. It is typical to monitor the quality of such bit streams by using a sampling oscilloscope.
In the monitoring operation, the binary pulse bit stream and a trigger input in the form of a clock signal having a repetition rate identical to the repetition rate of the binary pulses in the bit stream and synchronous therewith are applied to the inputs of the sampling oscilloscope. Samples of the voltage levels of the binary pulses of the bit stream are taken at various time offsets from the repetitive trigger input and are plotted as sample points on the display of the oscilloscope. Voltage samples are continuously taken of the bit stream and added to the sampling oscilloscope in combination with the older sample points which continue to exist on the sampling oscilloscope display. Over a relatively short period of time, hundreds or thousands of the sample points on the sampling oscilloscope display plot the possible voltage distributions at each time offset from the trigger input. By sweeping all time offsets in the range of interest, a diagram appears on the sampling oscilloscope display which reveals the quality or characteristics of the measured high-speed bit stream. This type of diagram, oftentimes called an "eye" diagram, is often used to view high speed binary pulse bit streams during the various development, installation and maintenance phases of high-speed communications systems.
A problem exists in using sampling oscilloscopes in this manner to measure the quality of high-speed communication systems. As the bit stream data rate increases, the bandwidth of the sampling oscilloscopes needed to create the eye diagrams increases proportionally thereby resulting in a higher cost. Another problem arises in that as the cost of the sampling oscilloscopes increases and due to the design issues of super high-speed systems, the present sampling methods takes samples at a relatively few of all the possible edges of the bit stream pulses thereby limiting the current effective sampling rate to the range of one hundred to two hundred thousand samples per second.
Another type of apparatus has been developed to create an eye diagram for statistically measuring the quality of high speed binary pulse bit streams. A problem exists with this apparatus in that it requires that multiple histrograms be created and combined to establish an eye diagram and that two histograms are required to be created to make an eye diagram. Subtractions from neighboring vertical elements in the first histrogram are required to make the second histrogram which is what is used to make the eye diagram. If the data count of the user signal passing through the device under test changes drastically between the times the two vertical elements are taken, noise can be added to the subtracted results causing noise in the eye diagram. Accordingly, a need exists in the art for apparatus and a method for creating a noise free single histrogram actively determining an eye diagram for measuring the characteristics of high-speed binary pulse bit streams used to transfer information and data between communications systems.

Apparatus and method for sampling eye diagrams with window comparators


The rate based end system may provide feasible transmission rates for end source stations. As an extension to the rate based end to end system, there is disclosed a hybrid link by link flow control system. The link by link control system is built upon the end to end, rate based traffic control system. The link by link system utilizes bandwidth un accounted for by the end to end system. The link by link system uses feasible transmission rates obtained by the end to end system to determine the size of the buffers required for overbooking and for updating credit information to sustain the calculated rate.

As computer networks become increasingly more complex, more and more end stations communicate through more and more intermediate links. An intermediate link is typically a section of network cable with nodes or network switches at each end of the cable. A link can carry only a predetermined amount of network traffic, usually expressed as a bit per second limit. Network traffic is typically referred to as packets or cells, and each packet or cell requires a number of bits to be transmitted over the network.
For example, an intermediate link may carry traffic originating at numerous source end stations. And each source end station may be capable of generating network traffic at a rate in excess of what the intermediate link can handle without dropping packets. That is, each individual end station may be capable of driving an intermediate link into congestion. Accordingly, when a plurality of end stations are creating network traffic, and all of that traffic passes through a particular intermediate link, it is clear that a mechanism must be installed to limit the traffic created by the source end stations. Flow control is the generic term used to describe a mechanism to limit traffic created by source end stations.
Fairness in allocation of link capacity to various source end stations is another consideration which flow control must address. If one source end station uses the entire capacity of an intermediate link, then no other source end station can transmit. Congestion management systems provide each source end station with an opportunity to transmit, even though transmissions are at a rate reduced from what the source end station desires.
In many networks, particularly connection oriented networks, substantially stable routes are established for transfer of packets from a selected source end station to a selected destination end station. Typically, such stable routes are referred to as sessions or as virtual circuits. A virtual circuit is a path through intermediate links and nodes between a designated source end station and a designated destination end station. Each packet carries a designation of the virtual circuit, and each intermediate node maintains state information so that it can examine the virtual circuit designation in a received packet and accordingly forward the packet onto an appropriate downstream link.
Two common types of flow control typically utilized in networks having stable routes such as virtual circuits are, firstly, end-to-end flow control, and secondly, hop-by-hop flow control.
End-to-end flow control typically has a destination end station detect that congestion is occurring in the network. A destination end station may detect congestion by an intermediate node inserting a flag into a forwarded packet, where the flag informs the destination end station that the intermediate node's buffers are filling or that the intermediate node is otherwise experiencing congestion. The destination end station then places congestion information in an acknowledgement packet returned to the source end station, and the source end station reacts to the congestion information by reducing the rate which the source end station transmits packets onto the network.
A further refinement of end-to-end flow control is to transfer control packets along a virtual circuit from a source station, through the network to a destination station, and in response the destination station returns the control packet to the source station along the virtual circuit. As the control packet passes through the network, link capacity information is written into the control packet as it passes through each link of the virtual circuit. Each node at each link along the virtual circuit then maintains a table giving transmission rate information pertaining to each virtual circuit passing through that node.
Problems with a method of computing a transmission rate for each virtual circuit is that each intermediate node must keep a table containing state information for each virtual circuit passing through. Further, when a change occurs in the network, such as a new virtual circuit is established or an old virtual circuit is dropped, the network must respond rapidly to the change. Response to a change, in past attempts to apply end-to-end flow control, require a convergence time which is too long. For example, the worst case convergence time in many past systems is proportional to the number of virtual circuits, in addition to the dominant (or maximum) round trip time. Such long convergence times are not acceptable for efficient congestion management.
Secondly, hop-by-hop flow control is next discussed. In hop-by-hop flow control a downstream node uses a mechanism to inform an immediate upstream node to limit the rate at which the upstream node transmits packets to the downstream node. A typical mechanism used by the downstream node to limit the rate at which packets are transmitted by the upstream node, is the issuance of credits. Credits issued by the downstream node reflect the number of buffers in the downstream node. Credit information is sent in a control packet to the upstream node. The upstream node is permitted to send only the number of packets for which it has credits, and the upstream node decrements its credit count as it sends a packet. When the downstream node receives a packet the packet is stored in a buffer, and later the buffer is drained by the downstream node further processing the packet. As packets are forwarded by the downstream node, the downstream node sends credit information to the upstream node. Accordingly, the upstream node receives and uses credits to control the rate at which it transmits packets (or cells) to the downstream node. All of the nodes in the network use the hop-by-hop credit based flow control, and so permit their source stations to send only the number of packets which each node can handle.
Hop-by-hop flow control has been implemented by using either static buffering or dynamic buffering. In static buffering, sufficient buffers for each virtual circuit to fully occupy each link must be provided. Each individual virtual circuit may be capable of fully using the capacity of an intermediate link. Accordingly, each virtual circuit must have enough buffers assigned for it to fully use the capacity of the link. When many virtual circuits are established, the number of buffers needed becomes excessive. For example, in a transmission protocol referred to as Asynchronous Transfer Mode, or ATM, there are 24 bits assigned to designate a virtual circuit. Accordingly the number of possible virtual circuits is 2.sup.24. It is not practical to provide buffering at full link capacity for so many virtual circuits. And one never knows which of these virtual circuits will require buffering at full link capacity.
Secondly, when dynamic buffering is used, in a particular intermediate node, a pool of buffers is assigned for all of the virtual circuits passing through that node. Some of the buffers are allocated to each virtual circuit as they are needed. A problem is that when the network changes by adding or subtracting a virtual circuit, the system is very slow in responding to the change. For example, when a new virtual circuit is added, there may be no buffers available to be assigned to the new virtual circuit, as they may already be full from their previous assignment. The buffers drain slowly. Accordingly, the new virtual circuit must wait for a long time before it can begin transmission. Such long waits are unacceptable in efficient network management.
There is needed a flow control system capable of scaling to a large number of virtual circuits, capable of responding quickly to a change in the number of established virtual circuits, capable of responding to the different requirements of many different source end stations, and capable establishing a fair allocation of network resources to all of the source end stations.

Traffic control system having distributed rate calculation and link by link flow control


In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

1. Technical Field
The present application is related to co-pending application entitled "METHOD FOR INDIRECT ACCESS TO A SUPPORT TNTERFACE FOR MEMORY-MAPPED RESOURCES TO REDUCE SYSTEM CONNECTIVITY FROM OUT-OF-BAND SUPPORT PROCESSOR", Ser. No. 11/055,404, and application entitled "METHOD FOR PROVIDING LOW-LEVEL HARDWARE ACCESS TO IN-BAND AND OUT-OF-BAND FIRMWARE", Ser. No. 11/055,675, all filed on even date herewith. The present invention generally relates to computer systems, and more specifically to an improved method of allowing firmware to access system status and configuration registers in a multiprocessor system.
2. Description of Related Art
The basic structure of a conventional symmetric multi-processor computer system 10 is shown in FIG. 1. Computer system 10 has one or more processing units arranged in one or more processor groups; in the depicted system, there are four processing units 12a, 12b, 12c and 12d in processor group 14. The processing units communicate with other components of system 10 via a system or fabric bus 16. Fabric bus 16 is connected to one or more service processors 18a, 18b, a system memory device 20, and various peripheral devices 22. A processor bridge 24 can optionally be used to interconnect additional processor groups. System 10 may also include firmware (not shown) which stores the system's basic input/output logic, and seeks out and loads an operating system from one of the peripherals whenever the computer system is first turned on (booted).
System memory device 20 (random access memory or RAM) stores program instructions and operand data used by the processing units, in a volatile (temporary) state. Peripherals 22 may be connected to fabric bus 16 via, e.g., a peripheral component interconnect (PCI) local bus using a PCI host bridge. A PCI bridge provides a low latency path through which processing units 12a, 12b, 12c and 12d may access PCI devices mapped anywhere within bus memory or I/O address spaces. PCI host bridge 22 also provides a high bandwidth path to allow the PCI devices to access RAM 20. Such PCI devices may include a network adapter, a small computer system interface (SCSI) adapter providing interconnection to a permanent storage device (i.e., a hard disk), and an expansion bus bridge such as an industry standard architecture (ISA) expansion bus for connection to input/output (I/O) devices including a keyboard, a graphics adapter connected to a display device, and a graphical pointing device (mouse) for use with the display device.
In a symmetric multi-processor (SMP) computer, all of the processing units 12a, 12b, 12c and 12d are generally identical, that is, they all use a common set or subset of instructions and protocols to operate, and generally have the same architecture. As shown with processing unit 12a, each processing unit may include one or more processor cores 26a, 26b which carry out program instructions in order to operate the computer. An exemplary processor core includes the PowerPC™ processor marketed by International Business Machines Corp. which comprises a single integrated circuit superscalar microprocessor having various execution units, registers, buffers, memories, and other functional units, which are all formed by integrated circuitry. The processor cores may operate according to reduced instruction set computing (RISC) techniques, and may employ both pipelining and out-of-order execution of instructions to further improve the performance of the superscalar architecture.
Each processor core 12a, 12b includes an on-board (L1) cache (actually, separate instruction cache and data caches) implemented using high speed memory devices. Caches are commonly used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from system memory 20. A processing unit can include another cache, such as a second level (L2) cache 28 which, along with a memory controller 30, supports both of the L1 caches that are respectively part of cores 26a and 26b. Additional cache levels may be provided, such as an L3 cache 32 which is accessible via fabric bus 16. Each cache level, from highest (L1) to lowest (L3) can successively store more information, but at a longer access penalty. For example, the on-board L1 caches in the processor cores might have a storage capacity of 128 kilobytes of memory, L2 cache 28 might have a storage capacity of 512 kilobytes, and L3 cache 32 might have a storage capacity of 2 megabytes. To facilitate repair/replacement of defective processing unit components, each processing unit 12a, 12b, 12c, 12d may be constructed in the form of a replaceable circuit board, pluggable module, or similar field replaceable unit (FRU), which can be easily swapped installed in or swapped out of system 10 in a modular fashion. A command unit is a generic term that includes, among others, processor cores, and the service processors (which may also be called flexible service processor).
A prior art architecture shown in published US patent application US 2004/0215929 "Cross-chip communication mechanism in distributed node topology", discloses a predecessor external scan communications command XSCOM. Therein was shown an alternative method to provide supervisory commands to core processors through the use of a ring connected set of registers within a chip and extending between chips. The disclosed method had the advantage that commands circulated by way of the old XSCOM didn't have to interrupt fabric bus transported commands.
However, the old XSCOM method, because it used a relatively low bandwidth medium, required significant overhead to place locks on the so called 'mode ring'. Such locks could be placed by the service processor, or by individual threads operating on the cores of a chip.
In addition, the old XSCOM method had the drawback that once a XSCOM operation was initiated, the thread that owned that operation had to poll for status in order to receive the result. As can be seen, the old XSCOM required several instruction cycles to complete, which further required that the processor core had to gate off interrupts to avoid being interrupted during these cycles.
The architecture described above typically used a logical partition debugger and maintenance program known as the 'hypervisor', that allows, among other things, multiple computing environments on the same platform. The Hypervisor in a typical configuration would operate on one processor core. In order to coordinate functions on other chips, i.e. inter-chip commands, the Hypervisor needed to activate functions on a third command unit. This activity had the attendant drawback that in order to do this, many machine language instructions were needed, including a software lock on the resources of the target command unit. This meant that collisions of multiple processor cores needed to be avoided during the many machine instructions, as well as preventing the one or more service processors from trying to access the same facility at the same time.

Method to operate cache-inhibited memory mapped commands to access registers


In a docking apparatus for docking a note-type personal computer including a release lever, an ejecting structure for ejecting the note-type personal computer when the release lever is opened, and a solenoid-type eject stopper for stopping an operation of the ejecting structure, a detecting element is provided for detecting whether the release lever is closed or opened. A solenoid of the solenoid-type eject stopper is energized to stop the operation of the ejecting structure only when the docking apparatus receives an eject stopping signal from the note-type personal computer and the detecting element detects that the release lever is opened.

1. Field of the Invention
The present invention relates to a docking apparatus for a note-type personal computer.
2. Description of the Related Art
A note-type personal computer has often been docked to an extended station such as a port replicator.
In a prior art docking apparatus for docking a note-type personal computer, a release lever is provided, and an ejecting structure is provided for ejecting the note-type personal computer when the release lever is opened. Also, a solenoid-type eject stopper is provided for stopping an operation of the ejecting structure. Thus, a solenoid of the solenoid-type eject stopper is always energized to stop the operation of the ejecting structure when the docking apparatus receives an eject stopping signal from the note-type personal computer.
In the above-described prior art docking apparatus, however, since the eject stopper solenoid is always energized when an eject stopping signal is generated, the solenoid would be in an inoperative state by its magnetization. For example, the solenoid is overheated and overoperated. As a result, the eject stopper would erroneously operate. Also, the power consumption is remarkably increased.
It is an object of the present invention to provide a docking apparatus for a note-type personal computer having an improved release function capable of suppressing the erroneous operation and reducing unnecessary power consumption.
According to the present invention, in a docking apparatus for docking a note-type personal computer including a release lever, an ejecting structure for ejecting the note-type personal computer when the release lever is opened, and a solenoid-type eject stopper for stopping an operation of the ejecting structure, a detecting element is provided for detecting whether the release lever is closed or opened. A solenoid of the solenoid-type eject stopper is energized to stop the operation of the ejecting structure only when the docking apparatus receives an eject stopping signal from the note-type personal computer and the detecting element detects that the release lever is opened.
Thus, the operation duration of the eject stopper solenoid is decreased.

Docking apparatus for note-type personal computer having improved releasing function


A synthetic aperture ultrasonic imaging system for imaging a target with a resolution limited by a designated aperture. A phased array of nonuniformly spaced ultrasound transducers having an average inter-transducer spacing which is greater than a .lambda./2 Nyquist spacing for the transducers is used for imaging in a manner so as to either obtain a desired point spread function which is unattainable by a single image taken by the nonuniformly spaced transducers or to provide coarray equivalence to a phased array of transducers which are uniformly spaced at the .lambda./2 Nyquist spacing for the designated aperture. Coarray equivalence makes possible the technique of applying amplitude weightings to each of the nonuniformly spaced ultrasound transducers during transmit and receive modes and by forming a number of component images which when added together form a sum image substantially equivalent to a single image formed by a scan beam of the uniformly spaced transducers with the designated aperture. The complex values of the resulting component images are then added on a point by point basis, preserving phase, such that a point spread function of the sum image is substantially equivalent to the desired point spread function of the single image formed by the uniformly spaced transducers with the designated ape. STATEMENT OF GOVERNMENT INTEREST. This invention was made with government support under contract N00014-89-J-1538 awarded by the Department of the Navy. The government has certain rights in the invention.

1. Field of the Invention
The present invention relates to ultrasonic imaging systems, and more particularly, to ultrasonic imaging systems and methods which create the effect of imaging with a filled linear array while making use of a reduced or minimum number of linear array elements or processing channels.
2. Description of the Prior Art
In the imaging of coherent scenes composed of distributions of reflectors, active (transmit/receive) imaging arrays have been used in the prior art. In such imaging systems, the imaging array is often composed of linear arrays of elements which can function as both transmitters and receivers for, e.g., far-field, active imaging using narrowband radiation. As known to those skilled in the art, an image may be obtained with such a system by forming transmit and receiving beams and scanning them together across the scene Such beams are typically characterized by their beam patterns, where the beam pattern of the array is defined as its complex gain as a function of direction of arrival of incident radiation. Examples of imaging systems making use of such arrays may be found in the fields of medical ultrasound and underwater acoustic imaging.
As known by those skilled in the art, ultrasonic imaging is a technique used to form an image of the interior of a solid, opaque object by use of high-frequency, low amplitude mechanical vibrations (ultrasound). As just noted, this technique has applications in medical and underwater acoustic imaging. In medical imaging, images of small parts of the body (valves of the heart, for example) are formed and displayed. Such applications put a premium on high image resolution and overall image quality. For such reasons, it has been proposed to use phased arrays of transducer elements and signal processing techniques in order to obtain higher quality images from a given ultrasound transducer and instrument than would ordinarily be obtainable from that equipment. However, to date, sufficient techniques have not been developed.
Many prior art ultrasonic imaging instruments make use of single-element, mechanically scanned transducers, where the transducer element is a source of ultrasound which may also function as a receiver. In a mechanically scanned system, this element is pointed in a direction of interest by mechanical means and then is excited by a high-voltage pulse which causes it to emit ultrasound. Because the aperture is typically large compared to the wavelength of the emitted sound, the strongly insonified region is limited to a small volume of space directly in front of the transducer. This region is known as the afore-mentioned "beam". The echoes from the transmission are, in turn, sensed by the transducer element and recorded. Then, when the beam has been scanned over all the directions of interest, the recorded echoes may be combined to create an image which is displayed on a display device such as a CRT. In a phased array ultrasound instrument, multiple elements of this type are used. In many such systems, these elements are deployed side-by-side in a line to form a linear array, while in other systems the elements are made in the shape of continuous rings of annuli of varying radius.
As noted above, a beam may be formed in an array imaging system by transmitting (or receiving) with all of the elements at once. When a linear phased array is used, scanning of the beam is accomplished by varying time delays imposed on the measured echoes of the different elements, while the annular phased array is mechanically scanned and is usually focused by imposition of the delays on the transducer elements In the case of the linear phased array, the standard method of image formation is thus beam forming and scanning.
There are several known applications of phased arrays in medical ultrasound at the present time. In abdominal imaging (pre-natal, for example), large phased arrays are sometimes used, although the most common mode of operation is that of the large, unsteered linear array which translates the path of the sound through the body by subarray selection. Phased arrays are also used in cardiac imaging, but they are restricted in their physical size by the requirement that imaging be done through the spaces between the ribs. Phased arrays are also used in most color flow mappers, which image moving blood using a Doppler shift to project motion, because, unlike moving transducers, phased arrays can illuminate the same volume over and over again. Annular arrays are also widely used; however, their primary value lies in the fact that they can be dynamically focused when receiving an ultrasound echo.
Active imaging systems of the type to which the present invention is directed may be characterized by their point spread functions (PSF). The PSF is simply the image produced by the system for a point target or point reflector, and since any linear imaging system can be characterized by its response to a point reflector, the PSF is the key determinant of image quality. In other words, the quality of the final image is determined by the PSF. Because of this feature of active imaging systems, a method is desired for synthesizing a desired PSF in an image obtained with a given array used for active imaging. The desired PSF must belong to the set of realizable PSFs associated with the aperture, for the set of realizable PSFs for a given aperture may be larger than the set of PSFs which can be obtained by the standard method of transmit/receive beam forming and scanning. As will be described herein, images with these PSFs can be synthesized by the use of image addition, which is referred to herein as image synthesis or aperture synthesis. Such synthetic aperture active imaging systems using arrays have been a topic of investigation for some time, and various schemes have been proposed which are motivated by the desire to create the effect of a large array without using a large number of array elements. However, most of the schemes in the prior art, such as those described by W. H. Wells in "Acoustical Imaging With Linear Transducer Arrays," Acoustical Holography, Vol. 2, pp. 87-103 (1969), and by P. N. Keating et al. in "Holographic Aperture Synthesis Via a Transmitter Array," Acoustic Holography, Vol. 6, pp. 485-523 (1975), were devised on an ad hoc basis and do not allow for specification of a desired PSF. Additionally, such schemes typically deal with planar arrays, and the applicability of the idea of redundancy to linear active imaging arrays has not been explicitly recognized and exploited in the prior art.
Accordingly, the present invention has been designed to specifically apply the idea of redundancy to linear active imaging arrays so as to allow for improved imaging efficiency, and as will be described herein, this application has led to a significant advancement in the acoustical imaging art.

Synthetic aperture ultrasonic imaging system using a minimum or reduced redundancy phased array

The Trustees of The University of Pennsylvania


A portable computer having a standby power mode of operation has a bay for receiving a portable removable disk drive. The drive has a pair of slots engageable with parallel guide rails in the receiver, and a notch engageable with a retractable latch normally biased in the direction of the notch. A switch adjacent one of the rails generates a standby signal for the computer whenever the drive is inserted into the bay or moved in the ejection direction after installation. An ejector mechanism retracts the latch and an auxiliary locking pivot to release the drive for removal. The ejector also provides an ejection force which moves the drive a sufficient distance externally of the bay to permit the drive to be grasped by the user for complete removal. A grounding contact engageable with a similar contact on the drive provides a static discharge path for the drive prior to electrical interconnection with the computer.

This invention relates to the field of portable computers, and in particular to portable computers employing disk drives.
Portable computers are known which incorporate disk drives used for mass storage of data used by the computer for processing. In the past, such disk drives have been incorporated into the housing of the personal computer as a permanent structural component and thus not removable. Some of the disk drives are designed for use with so-called floppy disks, while others are designed for use with rigid disks. The floppy disks are insertable and removable from the drives; while the rigid disks are not usually fixed within the drive.
The advantage of the floppy disk is its portability: i.e., data stored on the floppy disk can be removed from the drive (and thus the computer) and either physically stored elsewhere or transferred into the internal or mass storage memory of some other computer. Rigid disk drives incorporated into the physical structure of the portable computer housing do not offer this portability advantage.
In order to try to provide some portability to disk drives using rigid disks, portable drives have been designed which are removably connectable to the computer system incorporated inside the portable computer housing, the connection usually being made by a cable. In addition, rigid disk drives have been designed which are incorporated onto printed circuit cards which are removably attachable in the extra bus slots within a personal computer. Due to size requirements, however, such arrangements have not been found to be physically compatible with the extremely small portable computers which are currently available.
As portable computers have evolved into more sophisticated computer systems with smaller dimensions and lighter weight, efforts have been directed toward providing increasing amounts of portable data storage with smaller weight and physical dimensions. With reduced physical size, however, it has been found difficult if not impossible to provide appropriate and reliable mechanical latching mechanisms which provide reliable mechanical retaining forces when the disk drive is installed in the portable computer while at the same time affording easy removal of the disk drive. For example, with space at an extreme premium there is little room available for mechanical latching mechanisms ordinarily used to retain a rectangular module in an opening formed in a housing. In addition to these mechanical constraints, portable computers operate on battery power which has limited electrical storage capacity. Consequently, normal power operated latching and unlatching mechanisms are not suitable for adaptation into a portable computer environment. Also, the electronic components of a computer system incorporated into a portable computer are sensitive to static charges: consequently, some protective mechanism must be provided to guard against static discharge into the computer system electronic components when an object is inserted into a portable computer housing and electrically connected to the computer system components. In addition, to ensure proper system operation, some provision must be made to signal the computer that electrical interconnection or disconnection between the disk drive and the computer is imminent.

Disk drive ejector mechanism with latch and ejector and standby switch


A scheduling apparatus flexibly integrates guaranteed-bandwidth (GB) and best-effort (BE) flows and comprises a combination of a primary weighted-round-robin (WRR) scheduler (PWS) and a secondary WRR scheduler (SWS). The PWS distributes service to the individual GB flows and determines the amount of service that the BE flow aggregate should receive during each frame. The SWS takes care of fairly distributing the service share of the BE aggregate over the individual BE flows. The scheduling apparatus divides the service frame in two subframes. In the first subframe, the PWS fulfills the bandwidth requirements of the GB flows. In the second subframe, the SWS distributes fair service to the BE flows. For each frame, the duration depends on the amount of bandwidth allocated to the GB flows and on the number of GB flows that are backlogged at the beginning of the frame. The amount of bandwidth globally available to BE flows (i.e., the duration of the second subframe) is dynamically adapted to the backlog state of the GB flows, increasing when the GB-flow activity is low, and decreasing when the GB-flow activity intensifies.

The increasing popularity of elaborate Quality-of-Service (QoS) frameworks such as Integrated Services and Differentiated Services puts emphasis on packet schedulers that allow flexible bandwidth management. Because of the heavy implementation cost of packet schedulers that feature optimal delay performance and because worst-case delay performance is actually rather secondary to robust bandwidth performance in IP networks, the industry is showing strong interest in Weighted Round Robin (WRR) schedulers [see references 1, 2, 3 listed in the attached Appendix], which have very low complexity and can provide robust bandwidth guarantees and fairness, but do not necessarily achieve tight delay bounds. A WRR scheduler can provide strict bandwidth guarantees to guaranteed-bandwidth (GB) flows (i.e., flows with specified bandwidth requirements) and service fairness to best-effort flows (i.e., flows with no specified bandwidth requirements) when it handles flows of either type in isolation (i.e., without flows of the other type). Typically, the aggregation of GB and BE flows in a single WRR scheduler compromises the efficiency of the server in allocating bandwidth resources. In existing WRR schedulers, a BE flow can be serviced only if it is allocated a service share. The selection of the service share is always arbitrary, and intrinsically compromises the flexibility that should instead characterize the distribution of bandwidth to BE flows. Furthermore, the service shares allocated to the BE flows are subtracted from a bandwidth pool that is shared with the GB flows, which implies a reduction in the amount of GB flows that the scheduler can support.
What is desired is an improved WRR scheduler that can efficiently integrate GB and BE flows.

Method and apparatus for integrating guaranteed-bandwidth and best-effort traffic in a packet network