A stacked semiconductor device includes a plurality of stacked chips, each having a plurality of elements to receive a signal. At least one first ladder main signal line for receiving the signal is arranged to pass through the chips. At least one second ladder main signal line is arranged to pass through the chips. A plurality of ladder buffers buffer the signal applied from the first ladder main signal line to the second ladder main signal line. The signal is uniformly distributed to the stacked chips using a ladder type circuit network technique.

A conventional semiconductor device may use many signals. The signals used in the semiconductor device may be externally applied or internally generated. Additionally, signals may be used in a region of the semiconductor device or distributed and used throughout the semiconductor device.
For example, a clock signal is a signal that may be distributed and used throughout the semiconductor device. The clock signal may be applied to various circuits implemented inside the semiconductor device. The circuits to which the clock signal is applied, may operate in synchronization with the clock signal such that the semiconductor device is operable at a proper rate in response to the clock signal. The semiconductor device or the circuits inside the semiconductor device and the external device may mutually input and output various signals at proper timings. Accordingly, the clock signal may be used as a timing reference signal for adjusting an operating rate or an input/output timing of the semiconductor device.
Since the clock signal may be used as the timing reference signal, an ideal clock signal may have the same slew rate and the same duty rate throughout the semiconductor device. Furthermore any skew or delay time difference may be eliminated. However, various signals, including the clock signal, may be transmitted through transmission lines such as metal lines and the like in the semiconductor device. In such a transmission process, the same signal may not be applied throughout the semiconductor device at the same timing because the signal may be delayed or distorted. When the clock signal is not uniformly applied throughout the semiconductor device, a timing margin of the semiconductor device may be reduced. The reduced timing margin may lead to an abnormal operation. Since the timing margin is important, equal distribution of the clock signal throughout the semiconductor device may be considered when designing the semiconductor device.
FIG. 1 illustrates an example of a single chip package (SCP) semiconductor device in which transmission lines may be arranged in an H-tree circuit network technique. In FIG. 1, the transmission lines may be arranged such that an externally applied clock signal may be uniformly distributed throughout the semiconductor device.
The SCP semiconductor device may have a single chip 10 within a package. A clock signal CLK may be uniformly distributed in all regions on the single chip 10. A transmission line (HL) arrangement illustrated in FIG. 1 is based on a signal distribution method known as an H-tree circuit network technique.
In the H-tree circuit network technique, a reference transmission line ML is arranged such that the clock signal CLK may be applied to a middle position of the chip 10. A first H transmission line HL1, may be coupled to the reference transmission line ML and transmit the clock signal CLK to the middle position of each of four regions into which the chip 10 is uniformly divided. First H transmission line HL1 may serve as a highest layer transmission line. For example, the reference transmission line ML may be coupled to the H transmission line HL1 and a center of H transmission line HL1. The H transmission line HL1 may have four end points. Each of the four end points of the H transmission line HL1 may be coupled to a corresponding middle position of each of the four regions of the chip 10.
Second H transmission lines HL2 may serve as lower layer transmission lines than the first H transmission line HL1. The middle of each second H transmission line HL2 may be coupled to a corresponding end of the first H transmission line HL1. For example, the middle of H transmission line HL2 may be coupled to the corresponding end of first H transmission line HL1. The second H transmission line HL2 may transmit the clock signal CLK to a middle position of each of four sub-divided regions of each of the four regions of the chip 10. A region where the clock signal CLK may be distributed in the chip 10 may be further sub-divided by third H transmission lines HL3 and fourth H transmission lines HL4 serving as lower layer transmission lines. For example, H transmission lines HL1, HL2, HL3 and HL4 may serve as first, second, third and fourth layer H transmission lines, respectively.
An input buffer 20 may accurately detect a signal level of the externally applied clock signal CLK, and may drive the clock signal CLK such that the clock signal CLK is accurately transmitted to the last H transmission line HL4 of the H-tree. The input buffer 20 may include a first buffer bf and a driving buffer drvbf. The first buffer bf may receive the externally applied clock signal CLK, and may detect the level of the clock signal CLK. The driving buffer drvbf may have high drive capability and may increase a swing width of the clock signal CLK output from the first buffer bf.
In FIG. 1, the fourth H transmission lines HL4, or the lowest layer should there be more than four layers of H transmission lines, may be coupled to various elements 11 implemented on the chip 10. Since the clock signals CLK applied to the elements 11 may be applied via the H transmission lines HL1-HL4, the signals may be applied via similar paths. Consequently, the clock signal CLK may be applied to each element 11 at the same timing and in the same phase throughout the chip 10.
In FIG. 1, H transmission line layers may include four layers, the first, second, third and fourth H transmission lines HL1, HL2, HL3 and HL4. However, it should be noted that the number of H transmission line layers may be decreased or increased.
FIG. 2 is a diagram illustrating a method for distributing a signal throughout a semiconductor device using a ladder type circuit network technique in the SCP semiconductor device.
The ladder type circuit network technique is a device using a phase interpolation that is disclosed in Korean Patent No. 10-0366629 (Yeong-don CHOI et al.) published on Dec. 17, 2002, the entire contents of which are incorporated herein by reference. In phase interpolation, a plurality of signals that has a small phase difference and is coupled via transmission lines may be combined to obtain one signal. For the sake of brevity, a more detailed description will be not be provided.
The ladder type circuit network technique shown in FIG. 2 may include an input buffer 21, two or more ladder transmission lines LL1 and LL2 extending side-by-side and a plurality of buffers b11-b2n. The buffers b11-b1n may be coupled in parallel between the adjacent ladder transmission lines LL1 and LL2. The input buffer 21 may operate in a similar or substantially similar manner as the input buffer 20. Thus, for the sake of brevity, the input buffer 21 will not be discussed in further detail. The plurality of buffers b11-b2n may have the same signal delay time.
A clock signal CLK applied to the first ladder transmission line LL1 through the input buffer 21 may be transmitted to the second ladder transmission line LL2 through the buffers b11-b1n provided between the first ladder transmission line LL1 and the second ladder transmission line LL2. The buffers b11-b1n may have the same signal delay time as one another. Therefore, time delay differences from a plurality of clock signals CLK applied to the second ladder transmission line LL2 through the buffers b11-b1n may have delay time differences due to distances through the first and second ladder transmission lines LL1 and LL2. Hence, the delay time difference between the clock signal CLK applied to the second ladder transmission line LL2 through the buffer b11 and the clock signal CLK applied to the second ladder transmission line LL2 through the buffer b1n may be small. Thus, the plurality of clock signals CLK applied to the second ladder transmission line LL2 may be phase-interpolated and merged into one clock signal CLK.
While only two rows of buffers and transmission lines are shown in FIG. 2, it should be understood that more than two rows may be used. When the ladder type circuit network technique is applied to the SCP semiconductor device, a plurality of ladder transmission lines of all regions on the chip may be arranged on the chip side-by-side, and a plurality of buffers may be provided between the adjacent ladder transmission lines. The plurality of ladder transmission lines LL1-LL2 may be arranged in a zigzag form or a vortex form. It should be noted that lines may be arranged in any form throughout the chip such that they do not overlap.
The conventional signal distribution methods in the SCP semiconductor device have been described with reference to FIGS. 1 and 2. However, highly integrated and multi-functional semiconductor devices may be required for miniaturized and multi-functional electronic products. A multi-chip package (MCP) semiconductor device in which a plurality of chips is packaged into a single semiconductor device has been introduced. The MCP semiconductor device may be a single layer type MCP semiconductor device or a multi-layer type MCP semiconductor device. The single layer type MCP semiconductor device is a semiconductor device in which a plurality of chips may be arranged side-by-side and packaged. The multi-layer type MCP semiconductor device (e.g., a stacked semiconductor device) is a semiconductor device in which a plurality of chips may be stacked and packaged.
FIG. 3 illustrates a signal distribution path in a conventional stacked semiconductor device.
In contrast to the SCP semiconductor device and the single layer type MCP semiconductor device, the stacked semiconductor device may have a three dimensional structure including a plurality of stacked chips Cp1-Cp5, as shown in FIG. 3. Similar to the SCP semiconductor device and the MCP semiconductor device, a clock signal may be distributed throughout the semiconductor device.
The stacked semiconductor device shown in FIG. 3 has the plurality of stacked chips Cp1-Cp5 oriented in a stacked vertical fashion. A main signal line MLM may pass through the plurality of stacked chips Cp1-Cp5, so that a signal is distributed to each of the plurality of stacked chips Cp1-Cp5. A host chip Host, serving as an internal or external device of the stacked semiconductor device, may have a reference transmission line ML and an input buffer 120. Additionally, the host chip Host may supply a clock signal CLK to the stacked semiconductor device. The input buffer 120 may be similar to the input buffers 20 and 21 of FIGS. 1 and 2, respectively. The input buffer 120 may drive and output the clock signal CLK such that the clock signal CLK is smoothly distributed to the plurality of chips Cp1-Cp5. An example in which the host chip Host is additionally provided is illustrated in FIG. 3. However, it should be understood that the host chip Host may not need to be additionally provided when one of the plurality of stacked chips Cp1-Cp5 is configured to have the reference transmission line ML and the input buffer 120 in order to receive an external clock signal CLK.
The plurality of chips Cp1-Cp5 may uniformly transmit the clock signal CLK to all regions on the plurality of stacked chips Cp1-Cp5 using the H-tree circuit network technique or the ladder type circuit network technique. As shown in FIG. 3, the main signal line MLM is arranged in a node NodeA such that the clock signal CLK can be transmitted from the middle of the plurality of chips Cp1-Cp5 as in FIG. 1.
The plurality of stacked chips Cp1-Cp5 may be the same as one another or may be different from one another. When the plurality of stacked chips Cp1-Cp5 is the same as one another, a timing margin for transmitting an inter-chip signal or a signal level may be easily set since chip characteristics may be similar. However, when the plurality of stacked chips Cp1-Cp5 of the stacked semiconductor device is different from one another, it is relatively difficult to set a timing margin for transmitting an inter-chip signal or a signal level since characteristics may differ according to a difference in a chip structure, a manufacturing process, or the like.
In order to distribute a signal throughout the semiconductor device in the above-described stacked semiconductor device, it is important to uniformly distribute the clock signal CLK to the plurality of stacked chips Cp1-Cp5. If the clock signal CLK to be applied to the plurality of stacked chips Cp1-Cp5 is not uniformly distributed, the clock signal CLK may be different among the plurality of stacked chips Cp1-Cp5 even when the clock signal CLK is uniformly distributed from the chips Cp1-Cp5.
However, as shown in FIG. 3, the conventional stacked semiconductor device is configured to smoothly distribute a signal using the H-tree circuit network technique or the ladder type circuit network technique for an internal signal distribution of each of the plurality of stacked chips Cp1-Cp5. The conventional stacked semiconductor device may use a simple signal transmission technique through the main signal line MLM for a signal distribution to the plurality of stacked chips Cp1-Cp5. However, when one of the plurality of stacked chips Cp1-Cp5 is far away from the host chip Host, the far away chip has a larger delay than another of the plurality of stacked chips Cp1-Cp5 that is closer to the host chip Host. Therefore, there is a high possibility that the applied clock signal may be distorted. That is, the signal applied to the plurality of stacked chips Cp1-Cp5 may be skewed.

Stacked semiconductor devices and signal distribution methods thereof


Embodiments of process shield for use in process chambers are provided herein. In some embodiments, a process shield for use in a process chamber includes: an annular body having an upper portion and a lower portion extending downward and radially inward from the upper portion, wherein the upper portion includes a plurality of annular trenches on an upper surface thereof and having a plurality of slots disposed therebetween to fluidly couple the plurality of annular trenches, wherein one or more inlets extend from an outer surface of the annular body to an outermost trench of the plurality of annular trenches.

Plasma process chambers typically include a substrate support to support a substrate and a target disposed opposite the substrate support. The target provides a source of material for sputtering onto the substrate during processing. RF power is provided to the plasma process chamber to create a plasma in a processing volume disposed between the target and the substrate support. Plasma process chambers typically include process kits for protecting chamber walls from unwanted deposition and to confine the plasma. Process kits generally include a process shield. A space between the target and the process shield is referred to as a dark space. During processing of the substrate for high pressure processes (>100 mTorr), contaminants, such as outgassing particles, may flow into the dark space, causing unwanted arcing.
Therefore, the inventors have provided improved process kits for use in plasma process chambers.

Gas injection process kit to eliminate arcing and improve uniform gas distribution for a PVD process


The present application relates to an operating appliance for interacting with a user, including a transparent cover device, a support device with a sensor cutout, and a pressure switch, wherein the transparent cover device forms an operating area and a lower side lying opposite to the operating area and the support device is arranged on or at the lower side and the pressure switch is located and aligned within the sensor cutout in such a way that a user input by means of a finger of the user on the operating area is detectable by the pressure switch, wherein a finger indentation is provided on the operating area and arranged above the pressure switch.

To be able to better clean operating surfaces of medical apparatuses, such as light sources, insufflators, or pumps, it is desirable for operating elements to be located behind a glass panel. This means that, e.g., a touch-sensitive screen for display and input purposes and, possibly, a further screen and an on/off switch should be arranged behind a glass panel. By way of example, the on/off switch of the apparatus can be embodied as a piezo switch in this case.
The space on the operating surface can be restricted, especially in the case of compact apparatuses. In this case, the switch can be located quite tightly next to the touch-sensitive screen and the adjacent touch-sensitive screen might (also) be operated when the switch is actuated.
By way of example, DE 10 2004 048 463 A1 has disclosed an operating field for a glass cooktop, in which a plurality of proximity sensors are arranged below a glass panel. Furthermore, the operating field has switching mechanisms to counter an operating error.
US 2020/0057467 A1 describes a cellular telephone, in which a biometric sensor is arranged behind the cover glass on the front side of the cellular telephone.


A bowel cleansing composition includes as a first cleansing ingredient, a specific sugar alcohol such as xylitol, sorbitol, etc., as a second cleansing ingredient glycerol, erythritol, threitol, arabitol, ribitol, mannitol, galactitol, fucitol, iditol, inositol, volemitol, isomalt, maltitol, lactitol, maltotriitol, maltotetraitol, and polyglycitol, as a second cleansing ingredient ascorbic acid or a mixture of ascorbic acid and a salt of ascorbic acid, as a third cleansing ingredient picosulfate, and an aqueous solvent, wherein the concentration of the first cleansing ingredient is 10 g/L to 500 g/L based on the total composition, the concentration of the second cleansing ingredient is 15 g/L to 500 g/L based on the total composition, the concentration of the third cleansing ingredient is 1 mg/L to 100 mg/L based on the total composition, and the volume of the aqueous solvent is 0.1 L to 1.0 L.

According to the reports from the World Cancer Research Fund International, colon cancer is the third most common cancer worldwide with incidences of colon cancer during the year 2012 estimated to be 1.4 million worldwide and expected to be 2.4 million in the year 2035. For the diagnosis of colon cancer, colonoscopy is essential. Moreover, colonoscopy is very important because colon cancer can be prevented if colon polyps, which are considered to be the precursor of colon cancer, are detected during colonoscopy and removed.
For accurate colonoscopy examination, bowel cleansing prior to the procedure is essential; since stool may be retained inside the colon even after fasting for days, it is necessary to cleanse the colon thoroughly by artificial methods prior to the examination. For this purpose, methods have been developed where cleansing liquids comprised of laxative agents are ingested to empty the colon. An ideal bowel cleansing agent should have high cleansing power, ease of administration, as well as safety.
Firstly, high cleansing power is an essential requirement for an accurate colonoscopy procedure. If too much residue remains after bowel cleansing, it is difficult to perform an accurate examination, and the poor visualization increases the risk of complications such as perforation, and sometimes the painful bowel procedure has to be repeated, which might result in the patient's refusal or avoidance of the examination. Thus, reliable cleansing efficacy is the most important requirement.
Secondly, the ease of administration is determined by the volume of the bowel cleansing agent to be ingested, the taste of the agent, and the occurrence of discomforts such as nausea, vomiting, and abdominal pain following the ingestion of the agent. Even if a bowel cleansing agent has excellent cleansing power, if its administration is difficult, one cannot successfully complete the intake process in accordance with the dosing regimen, resulting in inadequate bowel cleansing. In addition, the unpleasant experience with bowel cleansing often leads to the refusal of repeat examination, and rumors about the difficulties of administration may impede the popularization of colonoscopies harming public health.
Thirdly, as a safety requirement, bowel cleansing should minimize temporary disorders and should not cause irreversible chronic disorders.
Early regimens involved ingesting a large volume of up to 7-12 L of solutions like saline solutions as bowel cleansing agents. However, administration of such cleansing preparations was accompanied by a great deal of pain and difficulties.
Later, bowel cleansing preparations using 2 L of 10% mannitol, a sugar alcohol, was introduced and garnered much expectation. However, colonic gas explosions during colonic surgery or therapeutic colonoscopy after mannitol preparation have been reported and the use of mannitol is now avoided. Bowel cleansing preparations with sorbitol have also been considered to be inappropriate in most advanced countries including the U.S. and Europe due to similar risks.
In the 1980s, bowel cleansing preparations comprising the ingestion of polyethylene glycol (PEG) formulated into a 4 L solution were developed. PEG formulations are still the most commonly used bowel cleansing agents worldwide.
The most serious problems with PEG preparations were their very large volume amounting to 4 L and difficulties of ingestion due to their disgusting taste. Such difficulty of ingestion gave rise to the wide-spread negative perception of bowel preparation, which has led people to fear or avoid colonoscopies.
Thus, various attempts have been made to reduce the volume of the PEG preparations to be ingested. For example, the required volume of the diluted PEG solution may be reduced to 3 L by including a stimulant laxative such as bisacodyl tablets in the regimen such that it is administered 6-12 hours prior to the ingestion of the PEG solution, or using a magnesium citrate (Trade name Citromag®) solution in combination, or adding ascorbic acid (Trade name MoviPrep®). In the case of MoviPrep® type bowel cleansing preparations, ascorbic acid and sodium ascorbate are added to make up for the anticipated reduction in cleansing efficacy. However, as the total amount of PEG contained in these bowel cleansing preparations is 200 g, the PEG content has decreased by only 15.3%, compared to the 236 g contained in the COLYTE powder which is to be administered in a 4 L volume. Thus, despite the decrease in the total volume of the diluted solution to be ingested, complaints of patient discomfort are more common than in the case of the COLYTE powder 4 L regimen because PEG is concentrated 1.7-fold.
In addition to such difficulties of ingestion, PEG preparations have not achieved satisfactory bowel cleansing power. Various studies show that the percentage of bowel cleansing with a PEG formulation achieving a cleansed level adequate for colonoscopy is approximately 70%. Such insufficient cleansing by PEG formulations has been demonstrated by a number of published studies. For instance, a study has reported that colonoscopy was hindered by the residual solid stool in the colon in 47.1% of patients who had their bowel cleansed with the PEG formulation "Colyte" <"Comparison between Conventional 4 L Polyethylene Glycol and Combination of 2 L Polyethylene Glycol and Sodium Phosphate Solution as a Colonoscopy Preparation", Seoul National University Bundang Hospital, Department of Internal Medicine, Seoul National University College of Medicine and Liver Research Institute, Jung Won Lee et al., Korean J Gastroenterology, 56, 299-306, 2010>.
In order to resolve such ingestion problems with the PEG preparations, picosulfate preparations comprising magnesium citrate were developed as bowel cleansing preparations. A big advantage with picosulfate preparations is that they have greatly improved taste and thus, unlike PEG preparations, their consumption causes little discomfort due to unpleasant taste. For that reason, picosulfate preparations are most commonly used in Europe, but their relatively poor bowel cleansing power is the biggest problem with these preparations. The recommended regimen for Ferring's Prepopik® (sodium picosulfate, magenisum oxide, and anhydrous citric acid) approved by the U.S. FDA indicates the total volume of ingestion amounting to 2.22 L, and according to actual use of this preparation it has been found to be problematic due to its relatively poor cleansing power compared to PEG solutions.
For such reasons, Picolight®, which has the same composition as Prepopik®, is often used in a total volume of 3.5 L in clinical settings, which is 1.5-fold higher than its recommended dose.
Moreover, picosulfate-containing bowel cleansing agents do not contain electrolytes and thus they rarely cause hyponatremia or hypopotassemia due to overdose, but severe side effects such as spasm, etc., have been reported. Due to the incorporation of magnesium into this preparation, hypermagenesemia may occur, and thus patients with renal disorders are banned from using the preparation.
Thus, picosulfate-containing bowel cleansing agents developed for solving the ingestion difficulties with PEG preparations have improved compliance but show poor bowel cleansing efficacy. Consequently, patients still have to ingest large amounts ranging from 2.3 L to 3.5 L, and there exist problems of electrolyte abnormalities and hypermagenesemia.
Attempts to overcome the above limitations of known bowel cleansing preparations have not been successful and, consequently, there is a strong need for the development of a novel bowel cleansing composition that has reliable cleansing powder, ease of administration, minimal side effects, and is safe.


A semiconductor random access memory device has stacked capacitor electrodes and test conductive pieces laid on the same pattern as the stacked capacitor electrodes, and the test conductive pieces are alternately isolated from and connected to a ground line, wherein the test conductive pieces are scanned with an electron beam to see whether or not any one of the conductive pieces generates secondary electrons different in intensity from those radiated from the other conductive pieces for detecting a short-circuit, whereby an analyst investigates the stacked capacitor electrodes for a possible short-circuit.

This invention relates to a diagnosing technology for a semiconductor device and, more particularly, to a semiconductor device and a method for testing a semiconductor device for short-circuits.
A short-circuit is fatal to semiconductor devices, and lowers the production yield. When the short-circuit is detected in a semiconductor device, it is important for the manufacturer to investigate the cause of the short-circuit. One of the approaches to the cause of the short-circuit is a direct observation on the short-circuit. Conventionally, an optical microscope was used in the direct observation. The design rule has been severe, and the conductive lines are presently arranged at high dense on a semiconductor chip. In this situation, it is hard to observe the conductive lines directly with the optical microscope. Moreover, a possible portion of the short-circuit is merely detected through the direct observation with the optical microscope. The short-circuit is to be confirmed through an electric test. This results in a large amount of time and labor consumed for the diagnosis.
In order to make the test simple, it is proposed to test a semiconductor device with a scanning electron beam microscopy. A typical example of the testing method using the scanning electron beam microscopy is disclosed in Japanese Patent Publication of Unexamined Application No. 4-314032. FIG. 1 shows a substrate 106 for an array of thin film transistors. Gate lines 107 and source lines 108 are laid on a lattice pattern, and the gate lines 107 are electrically isolated from the source lines 108.
The prior art testing method is based on the charge-up phenomenon in the insulating during the observation with the scanning electron beam microscopy, and the array of thin film transistors is tested as follows. First, the substrate 106 is fixed to the sample table of the scanning electron beam microscopy, and is electrically isolated. Conductive tapes 103 and 109 are adhered to the substrate 106. The conductive tape 109 extends over the gate lines 107, and the gate lines 107 are short-circuited. On the other hand, the conductive tape 103 extends over the source lines 108, and the source lines 108 are short-circuited. A switching unit 101 is connected between the conductive tape 109 and a ground line 102 for the gate lines 107, and another switching unit 104 is connected between the conductive tape 103 and a ground line 105 for the source lines 108.
An analyst checks the array of thin film transistors to see whether or not any gate line 107 is short-circuited with the source lines 108 at the overlapped portions therebetween as follows. First, the analyst turns on the switching unit 101, and turns off the other switching unit 104. The gate lines 107 are grounded through the conductive tape 109 and the switching unit 101, and the source lines 108 are electrically isolated from the ground line 105. Subsequently, the source lines 108 are charged. The source lines 107 are designed to be electrically isolated from the gate lines 108. Therefore, if the source lines 107 are surely isolated from the gate lines 107, the charge-up phenomenon takes place at all the overlapped portions. However, if a source line 108 is short-circuited with the gate line 107, the overlapped portion is never charged. The short-circuit is detectable on the basis of the difference between the charge-up portions and non-charged portion.
FIG. 2 shows a test pattern formed in a semiconductor device to be tested through another prior art method. The prior art method is disclosed in IEEE TRANSACTION ON SEMICONDUCTOR MANUFACTURING, pages 384-389, 1997. Conductive pads 201 are arranged on a semiconductor substrate, and a test pattern 202 is formed among the conductive pads 201. The test pattern 202 is connected through a conductive buried-layer and a diffused region (not shown) to the semiconductor substrate or the ground 203. The semiconductor substrate is placed in vacuum, and is scanned with an electron beam. When the conductive pads 201 are radiated with the electron beam, secondary electrons are generated. The amount of secondary electrons is measured. If a conductive pad 201 is short-circuited with the test pattern due to an improper pattern transfer, the amount of secondary electrons is reduced. Thus, the analyst checks the dispersion of the secondary electrons to see whether or not a short-circuit takes place.
A semiconductor dynamic random access memory device is designed under the most severe design rules. The semiconductor dynamic random access memory cell is implemented by a series combination of an access transistor and a storage capacitor. In case where a stacked storage capacitor is employed in the dynamic random access memory device, miniature capacitor electrodes are arrayed on an inter-layered insulating layer at high dense, and a short-circuit is liable to take place between the adjacent miniature capacitor electrodes. The stacked storage capacitor is so small that a miniature short-circuit affects the data holding characteristics of the dynamic random access memory cell. However, such a miniature short-circuit is hardly observed with the scanning electron beam microscopy, because the image of miniature short-circuit is affected by noise due to fluctuation of the device pattern.
The above-described prior art detecting technologies have the following problems. Only the short-circuit between the conductive lines connected through the conductive tapes 103/109 is detectable through the first prior art testing method shown in FIG. 1. Even if a short-circuit takes place between the conductive line 107/108 and an isolated conductive piece, the analyst can not specify the short-circuit through the first prior art testing method shown in FIG. 1. When the analyst checks the array of stacked capacitor electrodes for a short-circuit, he or she needs to prepare a lot of miniature conductive tapes and micro-switches, and adheres the miniature conductive tapes between the stacked capacitor electrodes of all the combinations. It is not feasible. Therefore, the first prior art method is not applicable to the array of stacked capacitor electrodes.
On the other hand, the test pattern 202 consisting of conductive lines is required for the second prior art testing method shown in FIG. 2. The test pattern 202 is formed on the semiconductor chip for the testing use only, and the test pattern 202 render the layout between the conductive pads 201 and the test pattern 202 different from the actual layout of the conductive pads 201. When the second prior art testing method is applied to the array of stacked capacitor electrodes, a test pattern is to be formed in the array of stacked capacitor electrodes. However, the stacked capacitor electrodes are patterned under the most severe design rules. Therefore, it is impossible to form the test pattern in the array of stacked capacitor electrodes. In other words, the second testing method is available for an array of conductive pieces not patterned under the most severe design rules.
It is therefore an important object of the present invention to provide a method for testing a semiconductor device for a short-circuit in an array of miniature conductive pieces.
It is another important object of the present invention to provide a semiconductor device, which is to be tested through the testing method.
To accomplish the object, the present invention proposes to form a miniature test pattern same as a conductive pattern to be test.
In accordance with one aspect of the present invention, there is provided a semiconductor device fabricated on a substrate comprising an insulating layer formed over a major surface of the substrate, conductive strips laid on a pattern on the insulating layer and incorporated in an electric circuit, and test conductive strips laid on at least a part of the pattern on the insulating layer concurrently with the patter of conductive strips, and broken down into a first group consisting of certain test conductive strips electrically isolated and a second group consisting of remaining test conductive strips alternated with the certain test conductive strips and connected to another conductive strip.
In accordance with another aspect of the present invention, there is provided a method of testing conductive strips for a short-circuit comprising the steps of a) preparing test conductive strips alternately isolated and laid on a part of a pattern of the conductive strips formed over a substrate, b) scanning the test conductive strips with an electron beam for measuring the intensity of secondary electron and c) checking a dispersion of the intensity of the secondary electron to see whether or not the amount of secondary electron radiated from any one of the test conductive strips is different from the amount of secondary electron radiated from others of the test conductive strips for determining a short-circuit.

Semiconductor device having a test pattern same as conductive pattern to be tested and method for testing semiconductor device for short-circuit


This invention provides a seed-sorting apparatus that includes an alignment trough having a plurality of grooves into which the seeds are distributed, a line sensor camera for inspecting the seeds, a nozzle device having a number of nozzles that is the same as the number of grooves on the upper surface of the alignment trough, and a control unit. The control unit, through a series of calculations, is capable of differentiating between different types of seeds and can direct a seed sorting and sucking device to suck the seed.

1. Field of the Invention
The present invention relates to a sorting apparatus and a sorting method for sorting a desired article from a plurality of articles to be sorted, and an alignment apparatus for transporting a plurality of articles to be sorted.
2. Description of the Background Art
It is required that articles which belong to a desired category be sorted from a plurality of articles having various colors, sizes, etc. Conventionally, desired articles have been sorted based on the color, size, etc., of the articles to be sorted through the human eyesight. In recent years, sorting apparatuses have been proposed which sort desired articles using CCD (charge-coupled device) cameras (refer to, for example, JP-A-04-346877).
In the sorting apparatus according to the above-described JP-A-04-346877, the seeds are transported at intervals by a transport apparatus with a vibration generator, and the image of each of the seeds is obtained by a CCD camera. The color or size of the seed is determined based on the image of the seed obtained by the CCD camera, and the seeds determined to be rejected are sucked and extracted by an extraction device, so that the seeds are classified into accepted seeds and rejected seeds.
In the sorting apparatus according to the above-described patent document, however, the seeds are transported by the vibrations by the vibration generator in the transport apparatus, and therefore, the seed-transporting speed is low. As a result, it requires a great deal of time to sort the seeds. Moreover, since the color or size of the vibrating seeds is determined, it is difficult to accurately sort the seeds.
On the other hand, as a seed sorting apparatus for sorting seeds according to the genetic traits, an apparatus has been provided which sorts seeds by measuring the condition of the surface design of a seed and binarizing the measured result to compare this binarized image with a value of reference distribution of a seed stored in a storage in advance(refer to, for example, JP-B-3334003).
In the above-described seed sorting apparatus, however, the seeds are sorted by converting the image of the surface design of a seed into a binarized monochrome image, and therefore, it has been difficult to sort the seeds having the same surface condition with different colors.
Further, a seed sorting apparatus has been also provided which sorts the seeds according to color by a color sensor. It has been difficult, however, to accurately sort the identical seeds when some of them have non-uniformity in color. It has also been difficult to accurately sort the seeds according to color when some of them have white parts, that is, no color at their peripheries or string parts inside.

Sorting apparatus, sorting method and alignment apparatus


The SOC of a battery is calculated based on the voltage Vb and current Ib of a battery, and a battery electromotive voltage Vbo is calculated based on the SOC of the battery. Based on the battery electromotive voltage Vbo and the voltage Vc of a capacitor connected on the output side of the DC/DC converter, a duty ratio D(=Vbo/2Vc) achieving the maximum battery power is set as the lower limit value DL of the optimum duty range DR, so that the lower limit value DL is varied according to the SOC of the battery. The duty ratio D is limited so as to fall within the optimum duty range DR, and the DC/DC converter is controlled to be driven using the limited duty ratio D.

As a conventional driving system having a voltage conversion apparatus, there is proposed a system comprising, for example, a battery which serves as a power source of the driving system, a DC/DC converter for performing DC/DC conversion to an input voltage from the battery, a load comprising an inverter circuit for converting an output from the DC/DC converter into multi-phase AC electrical power and a motor for rotation driving while receiving the multi-phase AC electrical power from the inverter circuit, and a capacitor arranged between the DC/DC converter and the load and connected to the positive and negative bus bars (lines) of the inverter circuit (for example, Japanese Patent Laid-open Publication No. 2004-112904).
In this system, an input voltage from the battery is subjected to DC/DC conversion by the DC/DC converter, and thereafter stored in the capacitor, so that a load is driven using the power-storing capacitor which is then considered as a DC power source. Also, the voltage conversion ratio of the DC/DC converter can be controlled by adjusting the duty ratio of a switching control signal to be output to a switching element within the DC/DC converter.
Also, International Publication No. 03/61104 discloses a control apparatus of a voltage conversion apparatus.
For the reasons described below, such a system requires control to limit the voltage conversion ratio of the DC/DC converter by limiting the duty ratio of a switching control signal. Generally, a typical battery is designed capable of supplying electrical power of an amount corresponding to load requiring power. Depending on the condition of a battery, however, a battery may not be able to output electrical power of an amount corresponding to the load requiring power, for example, when the internal resistance of a battery increases due to drop of temperature.
In this case, should a DC/DC converter be simply controlled to be driven such that electrical power of an amount corresponding to the load requiring power is fed to the load, an increased amount of electrical power may be consumed due to the inner resistance of the battery and, consequently, only a reduced amount of electrical power can be supplied to the load. In order to suppress drop in the electrical power supplied to the load, the duty ratio of a switching control signal requires limitation.
According to the international publication No. 03/61104, the control apparatus of the voltage conversion apparatus sets the duty ratio which leads to the maximum battery power as a lower limit of the optimum duty range, based on the electromotive voltage (which is set as a constant) of a battery and an output voltage of a DC/DC converter, and the duty ratio of a switching control signal to be supplied to the switching element is limited so as to remain within the optimum duty range. That is, the related control apparatus of the voltage conversion apparatus limits the duty ratio to thereby suppress drop of electrical power supplied to the load.
In this related art, however, as the electromotive voltage of a battery is set as a constant, when an electromotive voltage varies due to variation in the state of charge (SOC) of the battery, the lower limit of the optimum duty range may also undesirably vary due to variation in the state of charge (SOC) of the battery. This makes it difficult to perform optimum control to limit the voltage conversion ratio of the DC/DC converter.
The present invention can advantageously provide a control apparatus and a control method for a voltage conversion apparatus capable of performing more appropriate control to limit the voltage conversion ratio of the voltage conversion apparatus.

This patent is subject to a terminal disclaimer.

Control apparatus and control method for voltage conversion apparatus


A device for assembling sections of wind-turbine blades provided with casings, including at least one tie including a first portion and a second portion, the first portion being a portion for assembly with a casing of a first section and the second portion being a portion for mounting with a complementary tie supported by a casing of a second section, wherein the first portion includes at least one composite/metal shear link provided with a continuous fitting element on at least one surface of the casing which receives one end of the aformentioned surface of the casing, provided with attachment pins passing through the fitting and the end of the surface. According to a preferred embodiment, the composite/metal link has at least double shear and is additionally provided with a back-fitting element, the end of the aforementioned surface of the casing being received between the fitting and the back fitting, the attachment pins passing through the fitting, the end of the surface and the back fitting, the link also being provided with a means for attaching the back fitting to the fitting.

The mechanical links, unlike for example with bonded or welded links, are links that can be disconnected.
One method generally used to produce mechanical links between panels or structures made from composite materials involves using several metallic interface parts, each attached to the composite material in a discontinuous manner and using mechanical attachment means such as screws, pins, bolts or others.
Although these solutions appear optimised, this is actually not the case, as they do not provide for the homogenous passage of forces over the entire wall of the composite structure.
This generates local overflows creating the risk of a progressive breakage appearing on the zones subjected to higher stresses known as the peel-off phenomenon.
Furthermore, with regard to mechanical analysis, these local overflows are difficult to quantify, which is detrimental to the reliability and optimisation of the structure, with the link produced therefore being difficult to guarantee.
Today, wind turbines are designed with blades measuring several tens of meters in length. Such blades clearly create many technical problems in addition to logistics problems. The transportation of such structures, and more particularly over land, is not easy.
Wind turbine blades are made from composite materials, which enable these moving parts to keep a reduced weight, which in turn reduces the attachment forces to be transferred.
These blades are generally made from several sections so as to simplify their transport and in particular their transport by lorry.
A problem therefore arises involving the mechanical assembly of composite parts within the perspective of a mechanically optimised solution in terms of mass, in particular in the event where the forces to be passed by the link are significant and complex, the link being required to resist significant mechanical, fatigue and environmental stresses with very high reliability.
Documents EP 1 584 817, EP 1 878 915 and WO 01/48378 describe links for sections of wind turbine blades made by several metallic parts.
With regard to document EP 1 878 915, the link uses metallic rods inserted into the walls of the central casing and bonded in place.
In document WO 01/48378, the links are distributed along the skin of the blade and in document EP 1 584 817, separate ties connected to the central casing of the sections are attached together and supported by elements covering the gap between the blades.
These examples of embodiment use discontinuous mechanical attachment means.
Furthermore, known methods exist for the calculation of metal/composite pinned links, even if such a calculation is fairly complex due to the number of phenomena that must be taken into account and in particular: the transfer of forces between the composite material and the pins, the shear within the pins, the peening of the composite material, the tensile strength of the composite material and/or of the metal, and the scribing axis.
It should be noted that the known methods for calculating force transfers are very approximate, as they simplify the assembly geometry by representing the latter in the form of a single shear which enables the use of the shear calculation method known as the Huth method.
Due to this approximation, classic methods do not allow for the exhaustive parameterisation of the links.
In particular, the Huth model does not allow for geometrically non-symmetrical links to be studied, which limits its field of use.
Moreover, the calculation formulae associated with this model, in particular for calculating shear within pins, brings about generalisation difficulties for multi-shear, with this model not at all being adapted to suit the latter.
Document FR 2 675 563 describes a method for linking a tube made from composite material with a tubular metallic part.
In this method, the metallic part is attached to the composite material both by bonding and by mechanical attachments, which results in the possibility of passing very high mechanical flows. This method, for which optimisation of the pin link depends on the orientation of the winding wires, is however specific to wound tubes and therefore to a specific method of manufacturing the composite material.
This concept does not directly apply to composite parts such as sections of wind turbine blades, which are not generally manufactured by winding, and therefore the fibre orientation of which is set by the conditions for use of these blades.

Device for assembling sections of wind-turbine blades and method for linking sections of wind-turbine blades


A continuous method for preparing a granular molding material for abrasive articles has been developed. The method includes the step of continuously blending an abrasive material with a curing agent and measured portions of phenol-novolac resins, at least one of which has a phenol-formaldehyde molar ratio in the range of about 1:0.2 to 1:0.35. The resulting product is a flowable, granular material homogeneously coated with the phenol-novolac resins. The product can be directly molded, i.e., without an aging step, into various improved abrasive articles, such as grinding wheels, comprising a homogeneous distribution of abrasive grain and having a low volatile organic chemical content.

Resin-bonded abrasive articles such as grinding wheels are typically produced by blending discrete abrasive particles with a liquid binder material and a powdered resin, and then pressing the mixture under appropriate thermal conditions. Other constituents can be included in the mixtures, e.g., fillers, curing agents, wetting agents, and various metal powders. An aging period which allows for salvation of the dry portion of the mixture with the liquid resin is usually required before pressing.
As noted in U.S. Pat. No. 4,918,116 (Gardziella et al), novolac resins have often been used as solutions in solvent-based systems for binding abrasive articles. A disadvantage of such a system is the easy ignitability of the solvents at high temperatures. While solvent-free modified novolacs have been developed, these materials are quite expensive, and their commercial use may often not be economical.
In addition to the difficulties involved will using certain novolac binders for making abrasive articles, manufacturers are sometimes faced with other production problems as well. For example, as pointed out in Gardziella, the use of liquid grain wetting agents such as furfural when preparing molding materials for abrasive discs may result in an unstable molding mixture. Furthermore, the use of such a mixture may generate a large amount of dust--often a drawback on the manufacturing floor.
The dust and stability problems associated with using novolac binders appears to have been somewhat alleviated by the teachings set forth in Gardziella. This reference discloses the preparation of various molding materials, using specific phenol-novolacs having a phenol-formaldehyde molar ratio of 1:0.2 to 1:0.35. As an example, abrasive discs are prepared by using heated corundum grains wetted with a not melt of the specified phenol-novolacs. After being blended at 140.degree. C. in a high-power mixer, the composition is cooled to 90.degree. C. and then further blended with a second novolac resin and a curing agent.
The type of novolac resins discussed in Gardziella may be used in a multi-step process for preparing a precursor molding material for abrasive articles. This process involves applying a heated, liquid novolac resin to abrasive particles by a mixing technique, followed by the application of a dry bonding material. The dry material usually includes another novolac resin, fillers, and one or more curing agents. The sequence of applying liquid resin and dry binding material is repeated in two or more discrete steps to eventually obtain dry, flowable, homogeneously-coated abrasive grains.
From this brief discussion, it should be apparent that there are advantages and disadvantages involved in using various novolac resins to prepare articles like abrasive discs. A process which does not require high-power mixers and temperatures as high as 140.degree. C. is commercially attractive. Additional economic benefits result from a continuous process which does not require multiple applications of liquid binder and dry binder, and which does not call for the heating and cooling cycles described in Gardziella. Moreover, elimination of the time-consuming aging step before pressing is another major improvement.
Ideally, these process improvements would not occur at the expense of material properties. For example, the attainment of flowable, homogeneously-coated abrasive grains (which are also substantially dust-free) as a molding material for abrasive wheels is an important objective in a manufacturing setting.
The homogeneous surface coating on the abrasive grain of the molding material of this invention causes substantially all abrasive grain to be uniformly distributed through the abrasive article prepared from the molding material. The abrasive article, both in its green and its cured state, is substantially free of bond rich regions, providing a uniform distribution of abrasive grains throughout the cross-section of the abrasive article. Because the abrasive grain is uniformly distributed, an abrasive wheel made from the molding mix is balanced. In traditional manufacturing processes, the abrasive wheel must be balanced by removing out a portion or the side or the wheel so that the wheel is true and spins in a balanced fashion during grinding operation. Many wheels which are out of balance are rejected, causing production losses. The elimination of all or some of the balancing steps from the manufacturing process is a significant improvement. In addition, the uniform distribution of abrasive grain provides better grinding performance and longer wheel life during use.
Finally, the characteristics of the abrasive article should remain very attractive. In the case of an abrasive wheel, the desirable properties include grindability and long working life.

Abrasive articles and method for preparing them


The invention relates to a common mode choke coil and a method of manufacturing the same and provides a compact, low-profile, and low-cost common mode choke coil and a method of manufacturing the same. A common mode choke coil has a general outline in the form of a rectangular parallelepiped provided by forming an insulation layer, a first helical coil unit, a second helical coil unit, and a closed magnetic path on a silicon substrate made of a single-crystal using thin film forming techniques. The first and second helical coil units are formed such that their axes of spiral extend substantially parallel to a substrate surface of the silicon substrate.

1. Field of the Invention
The present invention relates to a common mode choke coil and a method of manufacturing the same.
2. Description of the Related Art
Known coil components mounted on internal circuits of electronic apparatus such as personal computers and portable telephones include wire-wound types provided by winding a copper wire around a ferrite core, multi-layer types provided by forming a coil conductor pattern on a magnetic sheet made of ferrite etc. and stacking such magnetic sheets one over another, and thin-film types provided by alternately forming insulation films and metal thin-film coil conductors using a thin film forming technique. Recently, there is a rapid trend toward electronic apparatus having smaller sizes and higher performance, which has resulted in strong demand for coil components having smaller sizes and higher performance. Referring to thin-film type coil components, coil components of a chip size of 1 mm or less are supplied to the market by providing coil conductors having smaller thickness.
Coil components include common mode choke coils for suppressing a common mode current which can cause electromagnetic interference in a balanced transmission system and inductors which are combined with a capacitor to provide a low-pass filter (LPF). Patent Document 1 discloses a thin-film type common mode choke coil having an insulation layer and a spiral coil conductor formed using a thin film forming technique between a pair of magnetic substrates disposed opposite to each other. Patent Documents 2 and 3 disclose thin-film type inductors and methods of manufacturing the same. Patent Document 4 discloses a thin-film type micro-coil having a core and a method of manufacturing the same.
Patent Document 1: Japanese Patent No. 3601619
Patent Document 2: U.S. Pat. No. 6,008,102
Patent Document 3: U.S. Pat. No. 5,372,967
Patent Document 4: U.S. Pat. No. 6,876,285
Further size reduction of common mode choke coils is still required. However, in the case of the common mode choke coil according to the related art disclosed in Patent Document 1, it is required to increase the number of turns of the coil conductor to improve electrical characteristics such as impedance characteristics, for example. As a result, the coil conductor must be formed in a larger area, and a problem arises in that it will be difficult to reduce the size of the common mode choke coil.
Further, since the common mode choke coil according to the related art has a pair of magnetic substrates disposed opposite to each other, there is a problem in that it is difficult to provide the choke coil with a low profile.
The common mode choke coil according to the related art is completed through a thin film forming step for forming an insulation layer and a coil conductor (coil layer) on a magnetic substrate in the form of a wafer using a thin film forming technique such as a photo-process, a substrate combining step for combining the substrate with another magnetic substrate by bonding them using a bonding layer formed on the insulation layer, a cutting step for cutting the wafer to divide it into chips, and an external electrode forming step for forming an external electrode. As thus described, the manufacture of a common mode choke coil involves a plurality of manufacturing steps and therefore requires a high manufacturing cost, which results in a problem in that the cost of the common mode choke coil is increased.

Common mode choke coil and method of manufacturing the same


A method and computerized apparatus for assigning frequencies to a plurality of cells in a cellular network. Each cell requires a predetermined number of frequencies. The method includes generating a difficulty factor for each cell, wherein each cell's difficulty factor is based on an adjustment factor for that cell, and wherein, following a first unsuccessful assignment attempt, each cell's adjustment factor is indicative of a relative level of difficulty in selecting frequencies for that cell during the first unsuccessful assignment attempt. The method further includes the steps of selecting a cell from the plurality of cells based on each cell's difficulty factor; selecting a frequency from the available frequencies for the selected cell; when at least one of the plurality of cells requires at least one more frequency and there is at least one frequency available for use by that cell, repeating the steps of generating a difficulty factor, selecting a cell and selecting a frequency; and when at least one of the plurality of cells requires at least one more frequency and there are no frequencies available for use by that cell, updating each cell's adjustment factor, unselecting all of the selected cells and all of the selected frequencies for the selected cells, and re-performing the steps of generating a difficulty factor, selecting a cell, selecting a frequency, as a second assignment attempt.

1. Field of the Invention
The present invention relates to cellular telecommunications and, more particularly, to methods and apparatus for assigning frequencies in a cellular network.
2. Description of the Related Art
Cellular telephone providers supply cellular telephone service to callers within cellular telephone networks. Each network covers a geographic area that is divided into several smaller regions, generally referred to as cells. When a caller within a cell makes a cellular telephone call, the caller's cellular telephone establishes a connection with transmission/reception hardware within that cell. This hardware is generally referred to as a base station. The connection requires a pair of frequencies, one frequency to carry a first signal from the base station to the caller's telephone, and another frequency to carry a second signal from the caller's telephone to the base station.
A provider is typically allocated a pool of frequencies for use within a network. The provider controls the assignment of the frequencies of the pool to various cells in the network. To handle the demand for cellular telephone connections in a typical network, the provider must often reuse frequencies, i.e., assign the same frequency to more than one cell in the network.
Reuse of frequencies within a network may cause problems. In particular, use of a particular frequency in one cell may increase radio interference at that frequency in other cells. In some circumstances, a frequency becomes unusable in a cell because the combined interference from use of that frequency in other cells is too great. Usually when a caller attempts to use a frequency having excessive interference, the caller's connection fails. If frequencies are reused in cells that are too close together, a signal from one caller's connection in one cell may be overheard by another caller in another cell.
The problem of assigning frequencies within a cellular network, such that frequencies are reused and the above-described interference problems are avoided, is commonly referred to as the frequency assignment problem, and has been studied extensively. However, it appears that only a few approaches to the frequency assignment problem have been implemented in real cellular networks.
One such approach is a manual approach. In particular, sets of frequencies are assigned manually to cells. This approach is commonly used in practice.
Another approach is more automated and involves treating the frequency assignment problem as a graph coloring problem. In this approach, a nodal map of the network is developed, with each cell of the network plotted as a node. Frequencies are grouped into sets, with each set assigned a particular color. Then, each node on the map is assigned a color such that the number of colors is minimized, and such that no two adjacent nodes have the same color.
Attempts at implementing the graph coloring algorithm have been well documented. In particular, an article entitled "On Frequency Assignment in Mobile Automatic Telephone Systems," by Andreas Gamst and Werner Rave, IEEE (1982) B3.1.1, pp. 309-315, discusses several variations of the graph coloring method. Further variations of the graph coloring method are provided in an article entitled "Channel Assignment in Cellular Radio," by Kumar Sivarajan and Robert McEliece, IEEE (1989) Ch. 2379, pp. 846-850.
There are several drawbacks to the graph coloring method. First, the graph coloring method does not adequately represent real world situations, because it attempts to minimize the number of frequencies used in the network. Since cellular providers are typically allocated pools of frequencies, the number of frequencies is fixed, and there is no need to minimize the number of frequencies. Second, minimizing the number of frequencies may result in some frequencies of the pool being under-utilized and other frequencies being over-utilized. Over-utilization of frequencies typically produces unnecessarily high amounts of interference. Third, the graph coloring method does not take into account varying amounts of interference between cells. For example, the graph coloring method treats the interference for 10 frequencies the same as the interference for 50 frequencies.
Another approach to the frequency assignment problem is called applied frequency planning. In the applied frequency planning method, each cell has a "rest-capacity" that is a function of the maximum number of frequencies that can be assigned to the cell. The lower rest-capacity cells receive assignments before the higher rest-capacity cells. The applied frequency planning method is described in an article entitled "Applied Frequency Assignment," by J. Plehn, IEEE (1994) 0-7803-1927, pp. 853-857.
There are several drawbacks to the applied frequency planning method. First, the applied frequency planning method gives priority to the lower rest-capacity cells, assuming that it is harder to assign frequencies to those cells than to the higher rest-capacity cells. However, the higher rest-capacity cells may also have higher constraints with other cells, thus making it more difficult to assign frequencies to the higher rest-capacity cells than the lower rest-capacity cells. Another drawback is that the applied frequency planning method considers carrier-to-interference ratios only when two cells have the same rest-capacity. Accordingly, a cell could be considered a high rest-capacity cell although most of the available frequencies have inadequate carrier-to-interference ratios. Furthermore, the applied frequency planning method requires a significant amount of time to compute the rest-capacity for each cell prior to each assignment.
It is therefore desirable to provide methods and apparatus for assigning frequencies in a cellular network that avoid the drawbacks of the conventional approaches. It is also desirable to provide methods and apparatus for improving the number of assignments, average carrier-to-interference ratios, carrier-to-interference variability and worst-case carrier-to-interference ratios in a cellular network.

Methods and apparatus for assigning frequencies in a cellular network


A method, system, and program product comprising, assigning addressable elements of storage devices of a data storage system to groups and subgroups, each subgroup being a member of a respective group of the groups, associating a value with a first group of the groups, wherein the value is derived from attributes of access requests to addressable elements of only a subset of the subgroups that are members of the first group, and based on the value, migrating data of the first group.

1. Technical Field
This application relates to facilitating data migration between tiers.
2. Description of Related Art
A traditional storage array (herein also referred to as a "disk storage array", "disk array", or simply "array") is a collection of hard disk drives operating together logically as a unified storage device. Storage arrays are designed to store large quantities of data. Storage arrays typically include one or more storage array processors (SPs), for handling both requests for allocation and input/output (I/O) requests. An SP is the controller for and primary interface to the storage array.
Performance of a storage array may be characterized by the array's total capacity, response time, and throughput. The capacity of a storage array is the maximum total amount of data that can be stored on the array. The response time of an array is the amount of time that it takes to read data from or write data to the array. The throughput of an array is a measure of the amount of data that can be transferred into or out of (i.e., written to or read from) the array over a given period of time.
The administrator of a storage array may desire to operate the array in a manner that maximizes throughput and minimizes response time. In general, performance of a storage array may be constrained by both physical and temporal constraints. Examples of physical constraints include bus occupancy and availability, excessive disk arm movement, and uneven distribution of load across disks. Examples of temporal constraints include bus bandwidth, bus speed, spindle rotational speed, serial versus parallel access to multiple read/write heads, and the size of data transfer buffers.
One factor that may limit the performance of a storage array is the performance of each individual storage component. For example, the read access time of a disk storage array is constrained by the access time of the disk drive from which the data is being read. Read access time may be affected by physical characteristics of the disk drive, such as the number of revolutions per minute of the spindle: the faster the spin, the less time it takes for the sector being read to come around to the read/write head. The placement of the data on the platter also affects access time, because it takes time for the arm to move to, detect, and properly orient itself over the proper track (or cylinder, for multihead/multiplatter drives). Reducing the read/write arm swing reduces the access time. Finally, the type of drive interface may have a significant impact on overall disk array storage. For example, a multihead drive that supports reads or writes on all heads in parallel will have a much greater throughput than a multihead drive that allows only one head at a time to read or write data.
Furthermore, even if a disk storage array uses the fastest disks available, the performance of the array may be unnecessarily limited if only one of those disks may be accessed at a time. In other words, performance of a storage array, whether it is an array of disks, tapes, flash drives, or other storage entities, may also be limited by system constraints, such the number of data transfer buses available in the system and the density of traffic on each bus.
Storage arrays are typically used to provide storage space for one or more computer file systems, databases, applications, and the like. For this and other reasons, it is common for storage arrays to be logically partitioned into chunks of storage space, called logical units, or LUs. This allows a unified storage array to appear as a collection of separate file systems, network drives, and/or Logical Units.
The Storage Array keeps track of the logical unit to physical unit associate in a map. The map associates a host logical unit address with a physical device address. The size of the elements in the map is the coarseness of the map. A map that only has a few entries of large extents is a course grain map. A map that has many entries with small extents is a fine grain map. Fine grain map allow more flexibility but generally are to large for all of it to be contained in memory at once. It is possible to use different mapping granularities for different data to achieve a variety of space/performance trade offs.

Facilitating data migration between tiers


A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.

Typical semiconductor devices include metal conductors or traces and vias for electrically coupling portions of the semiconductor devices. One method for creating these metal conductors uses a damascene fill process. The process includes forming fine pitch lines by laser structuring a dielectric layer, overfilling the structured dielectric layer by a copper electroplating process, and back etching the excess copper to expose the structured dielectric layer and the trace structures.
This damascene fill process requires a uniform, planar copper plating process. As such, the deposited copper layer must be very flat and uniform to enable etchback and singulation of the metal traces. The uniform deposition process, however, only works for very fine structures. Due to the electroplating process characteristics with copper deposition on the sidewalls of the fine structures, the copper growth is such that the copper surface above the fine structures is almost flat. This does not work for larger structures, however, therefore a dent is visible in the area of larger structures. When the copper is etched back to expose the underlying structures, the copper in the large structures will be etched out completely. Therefore, this process is not capable of creating relatively large structure elements, such as land pads for solder balls.
For these and other reasons, there is a need for the present invention.

Semiconductor device including conductive element


Wafer carrier arranged to hold a plurality wafers and to inject a fill gas into gaps between the wafers and the wafer carrier for enhanced heat transfer and to promote uniform temperature of the wafers. The apparatus is arranged to vary the composition, flow rate, or both of the fill gas so as to counteract undesired patterns of temperature non-uniformity of the wafers. In various embodiments, the wafer carrier utilizes at least one plenum structure contained within the wafer carrier to source a plurality of weep holes for passing a fill gas into the wafer retention pockets of the wafer carrier. The plenum(s) promote the uniformity of the flow, thus providing efficient heat transfer and enhanced uniformity of wafer temperatures.

Many semiconductor devices are formed by processes performed on a substrate. For example, in the fabrication of light-emitting diodes (LEDs) and other high-performance devices such as laser diodes, optical detectors, and field effect transistors, a chemical vapor deposition (CVD) process is typically used to grow a thin film stack structure using materials such as gallium nitride over a sapphire or silicon substrate. The substrate typically is slab of a crystalline material, commonly referred to as a "wafer," typically in the form of a disc.
One common process is epitaxial growth. For example, devices formed from compound semiconductors such as III-V semiconductors typically are formed by growing successive layers of the compound semiconductor using metal organic chemical vapor deposition or "MOCVD." In this process, the wafers are exposed to a combination of gases, typically including a metal organic compound as a source of a group III metal, and also including a source of a group V element which flow over the surface of the wafer while the wafer is maintained at an elevated temperature. Typically, the metal organic compound and group V source are combined with a carrier gas which does not participate appreciably in the reaction as, for example, nitrogen. One example of a III-V semiconductor is gallium nitride, which can be formed by reaction of an organo gallium compound and ammonia on a substrate having a suitable crystal lattice spacing, as for example, a sapphire wafer. Typically, the wafer is maintained at a temperature on the order of 1000-1100° C. during deposition of gallium nitride and related compounds.
Composite devices can be fabricated by depositing numerous layers in succession on the surface of the wafer under slightly different reaction conditions, as for example, additions of other group III or group V elements to vary the crystal structure and band gap of the semiconductor. For example, in a gallium nitride based semiconductor, indium, aluminum or both can be used in varying proportion to vary the band gap of the semiconductor. Also, p-type or n-type dopants can be added to control the conductivity of each layer. After all of the semiconductor layers have been formed and, typically, after appropriate electric contacts have been applied, the wafer is cut into individual devices. Devices such as light-emitting diodes ("LEDs"), lasers, and other optoelectronic devices can be fabricated in this way.
The epitaxial growth process can be carried out in a CVD tool that includes a process or reaction chamber, which provides a sealed environment that allows infused gases to be deposited upon the substrate to grow the thin film layers.
One type of CVD tool which has been widely accepted in the industry uses a device commonly referred to as a "wafer carrier." Wafer carriers typically comprise a large disc with numerous wafer retaining regions or "pockets," each pocket adapted to hold one wafer. The wafer retaining pockets are typically comprise a recess or cavity formed on the top surface dimensioned to receive a wafer, and are characterized as having an upwardly-facing floor and a radially inward-facing perimeter wall.
Typically, the wafers are supported by protrusions that extend from the floor and the perimeter wall the wafer retaining pocket to suspend the wafer above the surface of the floor of the wafer retaining pocket. The wafer can bow downward (concave) in different process layers. Suspension above the pocket floor at a predetermined distance prevents wafer from unevenly sitting bottomed out in the pocket due to this shape, which can cause wafer toss and large temperature non-uniformities. Maintaining a certain distance between the wafer and the pocket floor also reduces the wafer temperature non-uniformity that results from an uneven wafer-pocket gap due to the bowing of the wafer. The suspension of the wafer also promotes uniformity of the temperature of the wafer by eliminating random contact points that would otherwise result between the wafer and the pocket floor. Moreover, certain wafer carriers implement pocket floors that are appropriately bowed or shaped to help with uniformity at certain process layers. If the wafer rests on the floor directly, layers that the floors were not designed for can incur large non-uniformities due to bottoming out.
The wafer carrier is supported on a spindle within the reaction chamber so that the top surface of the wafer carrier with exposed surfaces of the wafers is oriented to face upwards, toward a gas distribution element of the CVD tool. While the spindle is rotated, the gas is directed downwardly onto the top surface of the wafer carrier and flows across the top surface toward the periphery of the wafer carrier. The wafer carrier is maintained at the desired elevated temperature by heating elements, typically electrical resistive heating elements disposed below the bottom surface of the wafer carrier. These heating elements are maintained at a temperature above the desired temperature of the wafer surfaces, whereas the gas distribution element typically is maintained at a temperature well below the desired reaction temperature so as to prevent premature reaction of the gases. Therefore, heat is transferred from the heating elements to the bottom surface of the wafer carrier and flows upwardly through the wafer carrier to the individual wafers.
The importance of maintaining uniform conditions at all points on the top surfaces of the various wafers during the CVD process has long been recognized. Minor variations in composition of the reactive gases and in the temperature of the wafer surfaces cause undesired variations in the properties of the resulting semiconductor device. For example, if a gallium and indium nitride layer is deposited, variations in wafer surface temperature will cause variations in the composition and band gap of the deposited layer. Because indium has a relatively high vapor pressure, the deposited layer will have a lower proportion of indium and a greater band gap in those regions of the wafer where the surface temperature is higher. If the deposited layer is an active, light-emitting layer of an LED structure, the emission wavelength of the LEDs formed from the wafer will also vary. Thus, considerable effort has been devoted in the art heretofore towards maintaining uniform conditions.
While considerable effort has been devoted to design an optimization of such systems, further improvement would be desirable. In particular, it is desirable to provide better uniformity of temperature across the surface of each wafer.

Wafer carrier with temperature distribution control


A butterfly valve disc has a circular cross-section bore for receiving the end of a drive shaft which engages with a member non-rotatably located in the bore. The member is polygonal and preferably formed with twelve sides and edges, the edges biting into the internal surface of the bore to prevent rotation. The member preferably is of harder alloy than the disc to resist wearing and is formed with a slot extending perpendicularly to the plane of the disc to receive a corresponding tongue formed at the end of the shaft. This arrangement allows a small degree of play so that if the disc is subjected to pressure on one side and therefore bends, the torque required to open the valve is not increased. Alternatively wherein the disc (or another component) is not subject to such pressure the member may be integrally formed with the shaft.

This invention relates to a valve disc and drive shaft assembly, particularly for a butterfly valve.
In a known form of butterfly valve, the disc is cast to its general shape and then a diametrically arranged bore is formed by drilling. This bore extends across the whole diameter of the disc, and receives the drive shaft by means of which the disc is rotated to open or close the valve. To prevent the shaft rotating in the bore, one or more pins are provided radially with respect to the shaft axis and inserted through holes in the disc into blind apertures formed in the shaft.
However, it has been found that sometimes the joint between a pin and a disc is not properly formed or becomes damaged and leakage occurs, either through the disc from one side to the other or from the interior to the exterior of the valve, along a leakage path alongside the drive shaft.
One way of avoiding piercing the disc is to use a shaft of non-circular cross-section e.g. square cross-section, in a correspondingly shaped bore. However such bore shapes are relatively difficult and expensive to provide in practice to the required degree of accuracy by relatively simple machining techniques.


A camera executes a photographing operation with multiple flashes. The camera includes a photometering unit and a control unit. The control unit controls light emission at a first electronic flash unit which is either built into or externally mounted at the camera and transmits a light signal constituting a preliminary light emission command to a second electronic flash unit provided separately from the camera by engaging the first electronic flash unit in light emission. The photometering unit photometers a subject when the second electronic flash unit executes a preliminary light emission. The control unit allows a photographing operation to be executed if a photometered value detected at the photometering unit is equal to or greater than a predetermined threshold value.

1. Field of the Invention
The present invention relates to a camera system used to photograph a subject under flash light by utilizing a camera-side master strobe and a separately provided slave strobe.
2. Description of the Related Art
There are camera systems known in the related art in which a subject is photographed with multiple flashes by using an electronic flash unit (referred to as a "strobe" in this specification) mounted at the accessory shoe of the camera and a separate strobe for photographing with multiple flashes (for instance, see Japanese Laid Open Patent Publication No. H11-212148).
In such a camera system, the quantity of light emitted from the camera-side master strobe is monitored on a separately provided slave strobe side, a light emission at the slave strobe is started synchronously with the start of light emission at the master strobe and the light emission at the slave strobe is synchronously stopped as the light emission at the master strobe stops. In other words, the light emission at the slave strobe is controlled through optical communication between the master strobe and the slave strobe achieved via the flash light emitted from the master strobe.


This invention pertains to equipment used in the custom fitting of golf clubs and in particular to a dustfree workbench for use by a golfsmith for customizing golf clubs having shafts manufactured from graphite, titanium or beryllium. The workbench includes a filtration system particularly designed for removal of the extremely fine particles generated in the cutting of golf club shafts, and characterized by the use of a series of high efficiency filters that the dust-laden air is passed through before being returned to the room. Grates placed within the upper surface of the workbench prevent larger items from passing therethrough and include dampeners for purposes of flow regulation. The filter assembly comprises a plurality of filter elements with various micron rating filters, referred to as coarse and fine, and assembled in order of decreasing porosity and placed in series and upstream of the blower.

Golf club construction has evolved over the years to a highly specialized art wherein specialty materials such as titanium, beryllium and graphite are now commonly used in the construction of golf clubs. The use of graphite for golf shaft construction has become an instantaneous success. Graphite, known for its high strength and low weight, permits faster club head speeds which result in longer distance drives for the golfer.
To allow for optimum success, golf clubs can be built so as to be custom tailored to the individual golfer. With a conventional steel shaft golf club, a golfsmith typically employs a workbench having specialized vises to build or customize the club. In many golf shops, this work is performed in front of the customer. One of the problems associated with the machining of these specialty material shafts, particularly graphite, is the amount of specialty material dust, particularly graphite dust that is produced during the building or customizing process. For instance, when a club is tailored to meet the height requirements of an individual, the shaft of the club may need to be cut to fit the particular individual. This cutting process results in a fine dust that is distributed throughout the room and may have possible carcinogenic or other health side effects that the individual and customers are being subjected to. For these reasons, I have improved upon known prior art workbenches to provide the golfsmith with a self-contained workbench to permit continued golf club manufacturing while eliminating the problem of harmful dust fibers, e.g. graphite fiber dust, in the workplace.
For instance, U.S. Pat. No. 3,470,679 disclosed a workbench having a filtered laminar flow of clean air through a filtration system to absorb contaminated air. The platform has a recessed grate for drawing air from around items placed upon the platform.
U.S. Pat. No. 3,518,814 disclosed a workbench having a top working surface and an enclosure which defines an air passageway for movement of air upward through a filter and onto the work area.
U.S. Pat. No. 3,686,836 discloses a workbench having recirculated air drawn across the top of a workbench.
U.S. Pat. No. 4,333,745 discloses a workbench filtering station having HEPA-filters.
U.S. Pat. No. 5,582,225 discloses a simplified workbench that operates via the use of a conventional wet/dry vacuum cleaner for drawing air from a modified workbench.
A common problem with all of the known prior art is that the workbenches are not specifically designed for a golfsmith. To this end, the use of an enclosure over the bench can make it difficult to work on a long club. In addition, most grated workbenches are designed for removal of particulate dust, such as saw dust, and do not possess the air volume necessary to draw the extremely fine fibrous dust, e.g. graphite dust, from the working area. Thus, what is needed is a dustfree workbench having a specific design for removal of graphite fiber dust, or equivalent fine fibrous dust produced from alternative specialty shaft materials, while remaining aesthetically pleasing for use before the golfsmiths' customers.

Dustfree workbench for golf club shafts including underlying air filtration system


Aspects of the invention can provide an image display device for modulating light from a light source on the basis of display image data to display an image. The image display device can include a first optically modulating device for modulating light from the light source, a second optically modulating device for modulating light from the first optically modulating device, a relay lens system provided between the first optically modulating device and the second optically modulating device for forming an optical image of the first optically modulating device on a light-receiving surface of the second optically modulating device, and at least one reflecting optical device provided between plural lenses forming the relay lens system.

Aspects of the invention can relate to an image display device and a projector.
Improvements in picture quality of a related art electronic display device, such as an LCD (liquid crystal display), an EL (electro-luminescence) display, a plasma display, a CRT (cathode ray tube) and a projector have been remarkable and a device having a property such that resolution and the color gamut are almost equal to a visual characteristic of a human being has been almost put into practice. As for an intensity dynamic range, however, a reproduction range is generally at most around from 1 to 102 [nits] while a gradation number is 8 bits. On the other hand, as for human eyesight, it is said that an intensity dynamic range capable of perception at one time is around from 102 to 104 [nits] while intensity distinction ability is 0.2 [nits], which can be converted into 12 bits in gradation number. When a display image of a current display device is considered from a viewpoint of such a visual characteristic, narrowness of the intensity dynamic range is conspicuous in addition to lack of gradation of a shadow part or a highlighted part, so that the display image is not satisfied in reality and power.
In CG (computer graphics) used in movie films, games and the like, there has almost been a mainstream of the tendency to pursue reality in drawing with image data having an intensity dynamic range and a gradation characteristic, which are close to human eyesight, (refer to as HDR (high dynamic range) image data, hereinafter). A display device, however, lacks the performance for displaying the above. This causes a problem that expression ability, which is inherent in CG contents, cannot be sufficiently shown.
Further, in the next-generation OS (operating system), 16 bits of color space is planned to be adopted. This causes a dynamic range and a gradation number to be greatly increased, comparing with a case of using the current 8-bits color space. Accordingly, it is expected that a need for an electronic display device, which is capable of making the best use of the 16-bits color space and which has a high dynamic range and a high gradation, will be increased.
Among display devices, a projecting type of display device, such as a liquid crystal projector and a DLP (digital light processing, a registered trademark of the TI company) projector is a display device capable of large-screen display and effective for reproducing reality and power of a display image. In such a field of art, the following proposal has been made for the purpose of solving the above problems.
For a related or display device having a high dynamic range, there is a technique disclosed in, for example, Japanese Patent Application Publication 2001-100689. In the technique, a display device can include a light source, a second optically modulating device for modulating intensity of a whole wavelength range of light and a first optically modulating device for modulating intensity of respective wavelength ranges of the three primary colors RGB in the wavelength region of light and, in the display device, the light from the light source is modulated by technique of the second optically modulating device to form desired distribution of intensity, an optical image so formed is formed on a display surface of the first optically modulating device to be color-modulated and the secondarily modulated light is projected. Respective pixels of the second optically modulating device and the first optically modulating device are individually controlled on the basis of a first controlling value and a second controlling value, respectively, the first and second controlling values being determined on the basis of HDR display data. For the optically modulating device, used is a transmission type of modulating device, which has a pixel structure or a segment structure capable of individually controlling transmittance and which can control two-dimensional distribution of transmittance. As a typical example of the above, a liquid crystal light valve can be named. Moreover, a reflecting type of modulating device may be used instead of the transmission type of modulating device. A DMD (digital micro-mirror device) can be named as a typical example of the reflecting type of modulating device.
Here, considered is a case of using an optically modulating device in which transmittance in dark display is 0.2% while transmittance in bright display is 60%. An intensity dynamic range of a single optically modulating device is 60/0.2=300. Such a display device is equivalent to optically modulating devices, which have the intensity dynamic range of 300 and which are optically arranged in series. Accordingly, it is possible to obtain the intensity dynamic range of 300×300=90000. The same idea can be applied to a gradation number. Arranging optically in series optically modulating devices, which have an 8-bits gradation, allows a gradation number more than 8 bits to be obtained.
In the above description, Japanese Patent Application Publication 2001-100689 is an example of related art.


A physical encryption key system binds an encryption key to a physical key and denies decryption of secured information if the physical key is not present to a particular computing device. In one implementation, the physical key comprises a convenient removable pen drive on which a .NET isolated storage space is created to store the encryption key. The .NET isolated storage space can only be accessed by concurrence of the same user, domain, computing device, application, and physical key that participated in creating the isolated storage space. The user enjoys the security of knowing that protected information cannot be decrypted without the physical key; cannot be decrypted without the user's credentials even if the physical key is stolen; and cannot be decrypted if the protected information is pirated to a different computing device.

Security and privacy are becoming paramount issues in personal computing. It is now a common occurrence for security flaws to be uncovered in the bulletproof security of computing and Internet systems. This puts private and personal data at risk.
Several schemata are conventionally used to keep a user's files secure. Requiring a username and password for access to files and websites is now in widespread use. However, a typical user has many types of personal data files associated with many types of computing applications, each requiring a different password. Since it is unwise to use the same password for many different secured resources, the typical user ends up with a multitude of passwords—too many too remember. Thus, a user may record the many passwords, putting the resources they protect at risk if an unintended person finds the cache of passwords. Passwords can also be guessed, there are even legendary hackers known for this ability. Further, malicious background processes that read keystrokes as passwords are being entered by the user are relatively common.
Encryption per se is another technique for protecting private data resources. In a sense, encryption and password protection are very closely related. Often the only difference is that part of a password may contain a word familiar to the human, providing a human memory device, while an encryption key is often purely random, consisting of random numbers and symbols. Password protection is often a front-end for encryption, that is, the encryption key is often derived from a form of the input password. Guessing an encryption key can be automated, so that if the password or encryption key is too simple, then it is at risk.
One of the problems with security key infrastructures is that the "combination to the safe," i.e., private keys, must be stored somewhere. For most computing systems, but especially for typical end-users with limited resources, the storage place for security keys is usually on the same hardware that stores the personal data being protected. Although encryption algorithms can be very strong, even the a remote possibility that an encryption key could be discovered and exploited to open private information on the same machine as the key disturbs the security-minded user's peace of mind.
The more sensitive the private data, the greater looms the apprehension that someone with enough time could garnish resources to break into the private data. In other words, a feeling of perfect security is difficult to obtain when the user does not know the current state of decryption arts or the sophistication of deciphering tools available to hackers, government agencies, and manufacturers of the user's equipment and software.
Hardware security solutions have been tried, but these are usually either awkward or easily worked around. Removing the media that contains the sensitive information from the host computing device, for instance, can provide a greater vulnerability than the pitfalls of password and encryption schemes. Physical locks that lock out, e.g., the keyboard, are easily circumvented and are no longer even offered as options when purchasing a computer.
Hence, although there is always a need for stronger data security, there is especially a long felt need for a device or technique that provides a user with a higher degree of peace of mind—a feeling of certain security, wherein the user can know more absolutely that personal data is secure even if the private information is stored far away from the user and even if the computing device that stores the private information has been confiscated, stolen, or inadvertently given to charity.