A memory device is described which includes memory cells, access lines, and support electronics for facilitating access to information stored in the memory cells via the access lines. Both the memory cells and the support electronics comprise multi-layer thin film structures exhibiting giant magnetoresistance.

The present invention relates to memory technology employing the property of giant magnetoresistance (GMR). More specifically, a memory architecture is described herein in which the memory cells and the control electronics are all implemented using multi-layer thin film elements exhibiting GMR. According to further embodiments, a unified memory architecture is provided in which multiple types of conventional memories are replaced by the memories of the present invention.
Semiconductor memory technology, and specifically silicon random access memories (RAMs), are an important part of the foundation of all data processing systems. The device density of silicon technology has increased steadily in the decades since its introduction and, until recently, roughly conformed to Moore""s law which states that the device density of silicon chips doubles every eighteen months. That is, in recent years, the rate at which the bit density of silicon memories has improved has increasingly fallen short of the rate predicted by Moore""s law. The limitations of semiconductor technology are readily apparent in the widening gap between its future potential and its past performance. There are a number of reasons for this.
First, the limitations of semiconductor technology with regard to device size have not, and in many cases cannot, keep up with advances in lithography techniques. For example, as the feature size of silicon devices shrinks, undesirable effects occur including the loss of information through charge leakage, high oxide breakdown, and power consumption problems. Inherent limitations such as the non-scalability of p-n junctions and charge pumps also translates into an inability to take full advantage of advances in lithography.
Memory systems which include mechanical elements, e.g., disk drives, are also facing technological obstacles relating to storage density such as, for example, the difficulty of mechanically aligning a read head with increasingly smaller storage locations on a magnetic storage medium. Access times for such memories are also typically orders of magnitude greater than that of the semiconductor memories which they complement. Such memories are also vulnerable to a variety of environmental stresses including, for example, shock, vibration, temperature extremes, radiation, etc. In combination, such limitations impede the dual objectives of greater information density and faster information access.
The evolution of memory technologies such as FLASH and EEPROM have addressed some of these limitations in that they have much faster access time than conventional magnetic memories and are more resistant to some environmental stresses, e.g., mechanical shock. However, these xe2x80x9chardcardxe2x80x9d technologies do not have sufficient storage density or capacity to support the average stand-alone or networked computer system. Indeed, with one-tenth the capacity of standard disks, FLASH and EEPROM provide only supplemental storage capacity and have the added disadvantage of a limited number of access cycles. Moreover, although FLASH and EEPROM access times are better than those of conventional mechanical systems, they are clearly inferior as compared to DRAM or SRAM access times. In addition, the high power consumption per megabyte associated with FLASH and EEPROM necessitates larger power supplies, obviating the hardcard technologies"" advantage in size and weight. Therefore, although FLASH and EEPROM provide advantages with regard to speed and reliability, these memory technologies cannot achieve the capacity or power efficiency of conventional magnetic disk drives.
More recently, there has been a significant shift in industry-wide memory development aimed at replacing both solid-state semiconductor memories and mechanical storage by magnetic RAM. Most of this activity has focused on hybrid magnetic RAMs, known generically as MRAM, in which a magnetic memory array is combined with semiconductor electronics.
It is therefore desirable to develop memory technologies which can take advantage of advances in lithography techniques without suffering from the limitations inherent in semiconductor memories, and which can take full advantage of recent developments in GMR electronics. It is also desirable to that such technologies overcome the limitations of mechanical memory systems.
According to the present invention, a memory technology is provided which is based on structures which exhibit the property of giant magnetoresistance (GMR), and which overcomes the limitations of conventional memories described above. The memory arrays of the present invention include individual memory cells comprising GMR thin film structures which store one or more bits of information in their magnetic layers. Memory access lines are configured to provide random access to each cell in an array. Selection matrices, control electronics, preamplifiers, and sense amplifiers are all implemented with an all metal device referred to herein as a xe2x80x9ctranspinnor.xe2x80x9d The transpinnor is a network of GMR thin film structures which has characteristics like both a transistor and a transformer.
The performance of GMR structures improves as the feature size decreases. In addition, production costs associated with the all metal memories described herein will be dramatically lower than those associated with semiconductor memories for a number of reasons.
First, because the GMR structures of the invention are relatively simple, the number of fabrication steps is significantly reduced as compared to the typical semiconductor process for a similar device (e.g., fewer than 10 versus greater than 30). Second, the process steps for the all metal architecture of the present invention are carried out at relatively low temperatures (e.g., 200xc2x0 C.) as compared to the high temperature processing by which semiconductor techniques are characterized (e.g., 800xc2x0 C.). Furthermore, hybrid magnetic RAMs involve both processing methods, with subsequent bonding of the semiconductor support electronics with the magnetic memory array. In contrast, an all-metal magnetic RAM may be fabricated as a single monolithic integrated circuit using a single mask set because the GMR electronics and the GMR memory array are made of the same materials.
In addition, implementation of the memory electronics using transpinnors is advantageous because they can be deposited and patterned at the same time as the memory elements rather than sequentially as with semiconductor process, thereby further reducing the number of process steps required. The all metal architecture of the present invention will also be more immune to radiation than semiconductor or hybrid magnetic RAM memories. Moreover, transpinnor circuits tend to take up less area than equivalent semiconductor circuits (the transpinnor-based differential sense amplifier is a good example).
Additionally and according to various specific embodiments, an all-metal magnetic RAM can be a low-power device, in part because of the inherently low power of GMR circuitry, in part because a single transpinnor can perform multiple digital functions, and in part because of the ability of GMR circuits to turn off those subsystems that are not in use.
Finally, because the memory technology of the present invention is persistent, i.e., no refresh or standby power is required to retain stored information, it may be used not only to replace RAM, but mechanical storage systems as well.
According to a specific embodiment, a unified memory architecture is provided in which each of a plurality of memory types in the architecture are implemented using a specific embodiment of the memory arrays of the present invention. A specific example of such an architecture is described in the context of a computer memory architecture in which both system memory and long term storage are implemented according to the present invention.
Thus, the present invention provides methods and apparatus relating to a memory device comprising memory cells, access lines, and support electronics for facilitating access to information stored in the memory cells via the access lines. Both the memory cells and the support electronics comprise multi-layer thin film structures exhibiting giant magnetoresistance.
The present invention also provides methods and apparatus relating to a memory architecture comprising system memory for facilitating execution of computer program instructions by a processor, and mass memory for storing information which may be accessed by the processor. The system memory and the mass memory include first and second random access memories, respectively, which include first and second arrays of memory cells, respectively. Each memory cell in the first and second arrays comprises a multi-layer thin film structure exhibiting giant magnetoresistance.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.


An encoding/decoding method for predicting appearance probability of an information source symbol, while learning, and for dividing a valid section on a numerical straight line into both a first partial section to which an approximate value of the above-mentioned prediction appearance probability is applied and a second partial section remained in the valid section, to which such an arithmetic code is applied, the arithmetic code setting a partial section corresponding to an appearing symbol as a new valid section, is operated by storing thereinto such a fact that the prediction appearance probability is a specific value; by judging that the prediction appearance probability is equal to the specific value by referring to the relevant specific value; and by correcting an allocation between the first partial section and the second partial section when the judgement operation judges that the prediction appearance probability is equal to the specific value.

1. Field of the Invention
The present invention is related to an encoding method, an encoding apparatus, a decoding method, and also a decoding apparatus, capable of compressing/decompressing data.
2. Description of the Related Art
As an example of known encoding systems, a description will be made of an arithmetic encoding operation capable of achieving a high compression rate. Before describing a concrete operation, a conceptional idea of a binary arithmetic encoding operation is explained with reference to FIG. 16. An arithmetic encoding operation is realized in such a manner that a coordinate system value of a binary decimal number on a numerical straight line defined larger than, or equal to 0.0 and smaller than 1.0 becomes a code C. In a process stage, a range defined on the above-explained numerical straight line is divided as a valid section (effective section) width A in direct proportion to an appearance probability of a binary symbol, and a partial section corresponding to an actually appearing symbol is divided as a new valid section, which is repeatedly carried out. MPS (More Probable Symbol) corresponds to a superior symbol which indicates a data value of higher appearance probability. LPS (Less Probable Symbol) corresponds to an inferior symbol which indicates a data value of lower appearance probability. One coordinate value which is updated by a final symbol within a valid section is outputted as a code. During process operation, the code C is calculated as a lower bound value of a valid section, and this code C is updated as well as a width of a valid section, which is equal to a difference between an upper bound value and a lower bound value in this drawing. As the final code, it is also possible to select a coordinate value where a significant digit number is minimum within a valid section where 0 subsequent to a tail of a coordinate system is cut off.
In general, to practically execute the arithmetic encoding operation, a subtraction type arithmetic encoding operation is employed which is adaptive to cope with an increase in a significant digit number when a code calculation is carried out. It is assumed in the below-mentioned description that an arithmetic code indicates a subtraction type arithmetic code. FIG. 17 is a diagram for representing a conceptional idea of a subtraction type arithmetic encoding operation and a conceptional idea of a renormalizing process operation. A symbol LSZ corresponds to a partial section allocated to LPS, and an approximate value is selected from a previously prepared table based upon appearance probability of the symbols. In this step, when the valid section becomes smaller than xc2xd, such a renormalizing process operation is carried out that the valid section is multiplied by power of 2 so as to be enlarged larger than, or equal to xc2xd. As a consequence, a digit number of a decimal portion is kept constant during a calculation. At this time, in an integer portion, these digits which constitutes xe2x80x981xe2x80x99 subsequent to a decimal point and xe2x80x980xe2x80x99 of an upper digit of this xe2x80x981xe2x80x99, may be changed by a carry-up propagation in a coordinate calculation which will be performed later. Thus, the values are not defined. Since digits upper than these values do not contain the carry-up propagation, these upper digits can be sent out from an encoder.
Both the most typical encoder (Encoder) of the subtraction type arithmetic encoding operation and also the most typical decoder (Decoder) thereof may be realized by employing the table and the process flow, which are described in the International Standard Recommendation T. 82 of ITU-T. Here, this arithmetic encoding operation will the be referred to as a QM coder, and while data to be encoded is used as a binary image, the calculation process operations of both the encoding operation and the decoding operation defined in the above-explained preceding technical publication will now be described. In this case, when the encoding calculation process operation and the decoding calculation process operation of the QM coder are carried out, the correcting techniques for partial sections corresponding to the symbols disclosed in Japanese Patent No. 2128115 (U.S. Pat. Nos. 5,307,062, 5,404,140) are employed. This correcting technique will be explained with reference to FIG. 18, in which numeral values are expressed by the decimal system. In FIG. 18(a), while the valid section is 0.6, 0.2 is selected as LSZ which may occupy ⅓ of the entire section. Since this LSZ is not larger than xc2xd, LSZ is allocated to LPS, and the remaining section is allocated to MPS. However, as shown in FIG. 18(b), when LSZ may occupy ⅔ of the entire section, which exceeds xc2xd thereof, since the symbol correspondences between the appearance probability rate and the actual occupation rate are inversed, the correction is performed by simply exchanging the sections by both MPS and LPS so as to suppress deterioration of the encoding performance. This is referred to as an xe2x80x9cconditional MPS/LPS exchangexe2x80x9d.
FIG. 19 and FIG. 20 respectively represent block structural diagrams of an encoder 1A and a decoder 1B of QM coder, which are provided to explain operations with respect to both the encoding calculation process operation and the decoding calculation process operation. In this prior art, both an image memories 5A and 5B are assumed to be arranged inside the encoder 1A and the decoder 1B, respectively.
In FIG. 19 and FIG. 20, reference numeral 2 shows a context (Context), reference numeral 3 indicates a pixel (Pixel) which should be encoded, reference numeral 4 represents a code, and reference numerals 5A and 5B are image memories. Reference numeral 7 shows a prediction value table MPS, reference numeral 8 indicates a state table ST, reference numeral 9 represents an LPS section width table LSZ, reference numeral 10 shows an MPS state transition destination table NMPS, reference numeral 11 denotes an LPS state transition destination table NLPS, reference numeral 12 shows a prediction value inversion judgement table SWTCH, reference numerals 13A and 13B show arithmetic encoders, reference numeral 14 represents a symbol, and also reference numerals 15A and 15B represent pixel symbol converters.
Operations of the QM coder will now be explained. The image memory 5A employed in the QM encoder 1A stores thereinto an entered image 6, and refers to a predetermined encoded pixel by a model template with respect to the pixel 3 which should be encoded, and outputs the pixel 3 which should be encoded and the context 2 equal to a pattern produced from the pixel at the same time.
On the other hand, the image memory 5B employed in the QM decoder 1B stores therein the decode pixel 3 which has already been decoded, produces the context 2 with respect to such a pixel that should be decoded later from this stored pixel 3, and then outputs the produced context 2. The image memory 5B obtains such a pixel that should be decoded and is decoded by using this context to store thereinto this pixel which should be decoded, and then, outputs an image 6.
In the QM coder, prediction coincident probability of a pixel value is predicted in every context with respect to the pixel which should be encoded/decoded, and the encoding/decoding operations are executed, while the QM coder erans in connection with this variation. Learning is carried out by rewriting two variable tables 7 and 8 in which the context 2 is used as an index. One of these variable tables corresponds to a prediction value table MPS7 of each 1 bit (will be referred to as xe2x80x9cMPS table 7xe2x80x9d hereinafter) which stores thereinto as a prediction value in a state in which a pixel value MPS whose appearance probability is high. The other corresponds to a state table ST8 of each 7-bit (will be referred to as an xe2x80x9cST table 8xe2x80x9d hereinafter) which stores thereinto state numbers (0 to 112). The state numbers are produced by classifying a degree of prediction coincidence probability of a prediction value into 113 pieces of states (State) in total.
Other than the variable tables 7 and 8, there are constant tables (probability prediction table) 9 to 12, while referring to state numbers (State) as an index when the encoding/decoding operations are carried out. In other words, these constant tables are an LPS section width table LSZ9 in which an LPS section width is expressed by 16 bits (will be referred to as an LSZ table 9 hereinafter), an MPS state transition destination table NMP10 in which an MPS transition destination is expressed by 7 bits (will be referred to as an NMPS table 10 hereinafter); an LPS state transition destination table NLPS11 in which an LPS transition destination is-expressed by 7 bits (will be referred to an NLPS table 11 hereinafter), and also a prediction value inversion judgement table SWTCH12 in which a prediction value inversion judgement is expressed by 1 bit (will be referred to as an SWTCH table 12 hereinafter). It is now assumed that the names of the alphabetical variable/constant tables indicated in this explanation are arrangement names employed in process flow operations (will be explained later).
The calculating units employed in the arithmetic encoder 13A/arithmetic decoder 13B refer to the LSZ table 9, and this LSZ table 9 is not directly related to learning of adaptive prediction. Inside the arithmetic encoder 13A/arithmetic decoder 13B, the calculation is carried out by employing the LSZ value, and when the calculation precision is lowered, the renormalizing process operation (Renormalization) is carried out. When this renormalizing process operation is carried out, learning is performed at the same time.
If the encoding/decoding symbol 14 when the renormalizing process operation is executed corresponds to a superior symbol, the NMPS value is written into the ST table 8, whereas if the encoding/decoding symbol 14 when the renormalizing process operation is executed corresponds to the inferior symbol, then the NLPS value is written in the ST table 8, and the state is updated. The superior symbol indicates that the pixels 3 to be encoded/decoded are equal to the prediction value MPS7, whereas the inferior symbol indicates that the pixels 3 to be encoded/decoded are not equal to the prediction value MPS7. When the encoding operation is carried out, the pixel symbol converter 15A outputs the symbol 14 to the arithmetic encoder 13A, whereas when the decoding operation is performed, the decoder 13B outputs the symbol 14 to the symbol pixel converter 15B.
Also, when the renormalizing process operation is caused by the inferior symbol, if the prediction coincidence probability thereof is substantially equal to xc2xd, the MPS value 7 is inversed (calculation 1-MPS) and the inversed MPS value 7 is written into the MPS table 7. It can be judged as to whether or not the coincidence probability is equal to xc2xd by using the SWTCH value 12 as a flag.
As explained above, the updating process operation is carried out with respect to each of the two variable tables ST8 and MPS7, and these variable tables ST8/MPS7 must be separately managed.
In FIG. 21, there is shown an example of a constant table. While the constant table of the actual QM coder is constituted by 113 states, a description will now be made of a simple model. In this example, the constant table is constituted by 10 pieces of states, and it is assumed that the appearance probability of LPS between a state 0 to a state 9, is decreased by steps defined from 0.5 to 0.05. Under state i, when the renormalizing process operation is executed during the MPS process operation, the NMPS value is referred, and also the state number stored under the context is updated to (i+1). If i=9, this state cannot be further transferred to such a state having lower appearance probability than that of the own state 9, and therefore this state remains. Also, when the LPS process operation is carried out under state i, the NLPS value is referred, and the state number stored under the context is updated to (ixe2x88x921). If i=0, this state cannot be further transferred to such a state having higher appearance probability than that of the own state xe2x80x9c0xe2x80x9d, and therefore this state remains. At this time, since SWTCH=1, the prediction value MPS stored under the context is updated to an inversed value (1-MPS). In this case, it is ideal that LSZ is set to a probability value. However, since the valid section width is present between 0.5 and 1.0, LSZ is determined in such a manner that the errors caused by these aspects should be reduced as being permitted as possible. The constant table does not always contain the actual probability. In this drawing, an average value of the probability as to both the state i and the state (i+1) is simply described in this constant table.
FIG. 22 represents a bit arrangement of an encoding register C 30A, a bit arrangement of a decoding register C 30B, and a bit arrangement of a section width register A 31, which are used in both the encoding calculation process operation and the decoding calculation process operation. In the encoding register C 30A, a decimal point is set between a bit 15 and bit 16, a decimal part xe2x80x9cxxe2x80x9d (16 bits) corresponds to a calculating unit Cx32 based upon LSZ9, and when a carry is performed, this decimal part is propagated to an upper integer part. In the integral part, symbol xe2x80x9cbxe2x80x9d (8 bits) corresponds to a byte output unit Cb33, and symbol xe2x80x9ccxe2x80x9d (1 bit) corresponds to a carry-up judging unit Cc34. The carry-up is propagated to a code byte outputted just before the carry-up, and may be propagated up to an output byte before this code byte, if necessary. In the encoding process stage, the C register value is updated in such a manner that this C register value becomes as a code 4 a lower bound value of a section corresponding to the coded symbol.
In the decoding register C 30B, both a lower digit register CLOW 36 and a high digit register CHIGH 37 set a decimal point between a bit 23 and a bit 24; symbol xe2x80x9cbxe2x80x9d (8 bits) corresponds to Cb36 identical to a byte input unit (CLOW register 35); and symbol xe2x80x9cxxe2x80x9d (17 bits) corresponds to a calculating unit Cx (CHIGH register 37) 38 based upon LSZ9. In the decoding process stage, the C register value is updated in such a manner that this C register value becomes an offset value to a code 4 from a lower bound value of a section corresponding to the decoded symbol. This code 4 is a coordinate value within this section.
The input/output operations of the code byte in Cb are carried out when shift numbers of the C registers 30A, 30B, and the A register 31 by the renormalizing process operation are counted by CT50 equal to an auxiliary variable other than a register, and the counted value becomes 0. Both an initial value and a re-setting value of CT50 are equal to 8. As the encoding register defined in the preceding technical publication (recommendation T.82), there is a Cs between Cx and Cb, but is omitted for the sake of a simple explanation. If Cs is provided, a digit number thereof must be added to an initial value of a variable CT. Also, an integer part bit 24 of the encoding register is not defined, but is not required in this prior art. While the CLOW register 36 is defined by 16 bits, since lower-digit 8 bits lower than Cb are not used, the lower-digit 8 bits are omitted. The above-explained changes in the description never give any adverse influence to the encoding performance.
In the section width register A 31 which is commonly used in both the encoding operation and the decoding operation, in correspondence with the decimal points of the encoding/decoding registers 30A/30B, xe2x80x9caxe2x80x9d (16 bits) is arranged as a decimal part in conformity with an xe2x80x9cxxe2x80x9d register unit, and an integer part (bit 16) becomes xe2x80x9c1xe2x80x9d only by the value of an initial state. A section width (or, section size) is updated to either A-LSZ (lower section width) or LSZ (upper section width), and this section width is renormalized in such a manner that a bit 15 indicative of a xc2xd weight becomes xe2x80x9c1xe2x80x9d except for the initial value (integer part=xe2x80x9c1xe2x80x9d). Since the section width is kept larger than, or equal xc2xd, even when any LSZ9 is selected as the upper section width, securing of the lower section is guaranteed. In the renormalizing process operation, the A register 31, and the C register 30A, or 30B are enlarged at the same time.
In the QM coder, normally, the upper section LSZ9 which constitutes the fixed size with respect to the state is allocated to LPS. When the lower section becomes smaller than the upper section, xe2x80x9cconditional MPS/LPS exchangexe2x80x9d in which the upper section LSZ9 is allocated to MPS is carried out. The renormalizing process operation is necessarily carried out when LPS is encoded/decoded, and also MPS is encoded/decoded by applying xe2x80x9cconditional MPS/LPS exchangexe2x80x9d.
First, the encoding calculation process operation will now be explained with reference to a concrete process flow operation.
When the encoding calculation process operation is commenced, an initial value of the C register 30A (see FIG. 22) is 0; an initial value of the A register 31 is 0x10000; and an initial value of an auxiliary variable CT50 becomes 8 based upon the specification of the above-explained C register. Also, both a prediction value MPS[CX]7 with respect to all of contexts (reference patterns) CX2 (FIG. 19), and an initial value of a state ST[CX]8 are assumed as 0. Then, when the coding calculation process operation is ended, a process operation of a definition for sweeping out the content of the encoding register 30A as a final code 4 is performed.
FIG. 23 is an encoding process (ENCODE) flow operation for switching a process operation called from coincidence/incoincidence between the pixel value 3 to be encoded and the prediction value 7. At a step S111, a judgement is made as to whether or not the pixel value PIX3 is made coincident with the prediction value MPS[CX]7. If the pixel value PIX3 is made coincident with the prediction value MPS[CX]7, then MPS is encoded, whereas if the pixel value PIX3 is not made coincident with the prediction value MPS[CX]7, LPS is encoded. At a step S112, while CODELPS (LPS encoding) is called, LPS is encoded. At a step S113, while CODEMPS (MPS encoding) is called, MPS is encoded.
FIG. 24 shows a CODELPS process flow operation called in such a case that the pixel value 3 to be encoded is not made coincident with the prediction value 7, namely, LPS is encoded. First, at a step S120, LSZ is assumed as LSZ [ST[CX]]. At a step S121, the value of the A register 31 is temporarily updated to the lower section width. When such a judgement is made at a step S122 that the LSZ value (upper section width) is larger than the A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the xe2x80x9cconditional MPS/LPS exchangexe2x80x9d is applied, and while both the value of the A register 31 and the value of the C register 30A remain, the valid section is updated to a smaller lower section. When, the LSZ (upper section width) is smaller than, or equal to the A value (lower section width) (namely the answer is xe2x80x9cNOxe2x80x9d), the lower section width (present A register 31) is added to the C register 30A at a step S123, and thereafter, while the A register 31 is set as LSZ, the valid section is updated to a smaller upper section at a step S124. If it is judged at a step S125 that the constant SWTCH value 12 is equal to 1, then the prediction value 7 (MPS table) is inversed/updated at a step S126. While LPS is encoded, a state transition is performed with reference to the NLPS table 11 at a step S127, and RENORME is called to execute the renormalizing process operation at a step S128.
FIG. 25 represents a CODEMPS process flow operation called in such a case that the pixel value 3 to be encoded is made coincident with the prediction value 7, namely called when MPS is coded. First, at a step S130, LSZ is assumed as LSZ [ST [CX]]. At a step S131, the value of the A register 31 is temporarily updated to the lower section width. If it is judged at a step S132 that the value of the A register 31 is larger than, or equal to 0x8000 (namely, the answer is xe2x80x9cNOxe2x80x9d), then this CODEMPS process flow operation is ended. To the contrary, when the value of the A register 31 is smaller than 0x8000 (namely, the answer is xe2x80x9cYESxe2x80x9d), if it is so judged at a step S133 that the LSZ value (upper section width) is smaller than the A value (lower section width) (namely the answer is xe2x80x9cYESxe2x80x9d), then the xe2x80x9cconditional MPS/LPS exchangexe2x80x9d is applied. The lower section width (present A register 31) is added to the C register 30A at a step S134, and thereafter, while the A register 31 is set as LSZ, the valid section is updated to a larger upper section at a step S135. On the other hand, when it is judged at the step S133 that LSZ (upper section width) is larger than, or equal to the A value (low section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), while both the value of the A register 31 and the value of the C register 30A remain, the valid section is updated to a larger lower section. While MPS is encoded, a state transition is performed with reference to the NMPS table 10 at a step S136, and RENORME is called to execute the renormalizing process operation at a step S137.
FIG. 26 indicates a RENORME process flow operation for performing the renormalizing process operation. At a step S141, the value of the A register 31 is shifted to a 1-bit upper digit, and at a step S142, the value of the C register 30A is shifted to a 1-bit upper digit, so that such a calculation is carried out that is equivalent to a multiplication by 2. At a step S143, 1 is subtracted from the variable CT50, and a judgment is made as to whether or not the variable CT50 is equal to 0 at a step S144. When the judgment result is xe2x80x9cYESxe2x80x9d, the 1-byte code 4 is outputted from the C register 30A (Cb), and 8 is again set to the variable CT50 at a step S145. At a step S146, a judgment is made as to whether or not the renormalizing process operation is ended. If the value of the A register 31 is smaller than 0x8000, then the process operations defined from the step S141 to the step S145 are repeatedly carried out. If the value of the A register 31 is larger than, or equal to 0x8000, then the section becomes larger than, or equal to xc2xd, and the process operation is ended.
When the 1-byte code 4 is outputted from the Cb register 33 at the step S145, the carry is judged by the Cc register 34, and the carry is propagated to the code byte which has already been outputted. Then, after the carry is propagated and the code byte is outputted, both the values of the Cb register 33 and the Cc register 34 are cleared.
Next, the decoding calculation process operation will now be described with reference to a concrete process flow operation.
When the decoding calculation process operation is commenced, the C register 30B inputs thereinto a 3-byte code from a decimal part bit 0 to bit 23 as an initial value, and an initial value of the A register 31 is equal to 0x10000. Also, while an initial value of the auxiliary variable CT50 is assumed as 8, both an initial value of the prediction value MPS [CX]7 and an initial value of the state ST[CX]8 with respect to all of the contexts (reference patterns) CX2 are assumed as 0.
FIG. 27 indicates a decoding process (DECODE) operation flow for decoding a pixel which should be decoded. First, at a step S220, LSZ is set to LSZ [ST [CX]]. At a step S221, the value of the A register 31 is temporarily updated to the lower section width. When it is so judged at a step S222 that the value of the code CHIGH register 37 is smaller than the value of the A register 31 (namely, the answer is xe2x80x9cYESxe2x80x9d), the lower section is decoded. Next, when it is so judged at a step S223 that the value of the A register 31 is smaller than 0x8000 (namely, the answer is the answer is xe2x80x9cYESxe2x80x9d), xe2x80x9cMPS_EXCHANGExe2x80x9d is called at a step S224, and RENORMD is called at a step S225, so that the renormalizing process operation is carried out. On the other hand, when it is so judged at the step S223 that the value of the A register 31 is larger than, or equal to 0x8000 (namely, the answer is xe2x80x9cNOxe2x80x9d), MPS is decoded without executing the renormalizing process operation. At a step S226, the pixel value 3 is set to the prediction value 7, so that while both the value of the A register 31 and the value of the C register 30B remain, the valid section is updated to a larger lower section. Also, when it is so judged at the step S222 that the value of the code CHIGH register 37 is larger than, or equal to the value of the A register 31 (namely the answer is xe2x80x9cNOxe2x80x9d), the upper section is decoded. At a step S227, xe2x80x9cLPS_EXCHANGExe2x80x9d is called, and also RENORMD is called at a step S228, so that the renormalizing process operation is carried out. In such a process path for calling both xe2x80x9cMPS_EXCHANGExe2x80x9d and xe2x80x9cLPS_EXCHANGExe2x80x9d, even when the sections to be decoded are determined respectively, if the sections are not compared with each other, then it is not possible to judge as to whether the section to be decoded corresponds to MPS, or LPS. In the called process flow, the pixel value 3 to be decoded is determined.
FIG. 28 shows an LPS_EXCHANGE process flow operation for decoding an upper section. When it is so judged at a step S231 that an LSZ value (upper section width) is smaller than and A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the conditional MPS/LPS exchange is applied. At a step S232, a lower section width (present A register 31) is subtracted from the CHIGH register 37, and thereafter, the A register 31 is set to LSZ at a step S233. At this time, since the upper section is larger than the lower section, MPS is decoded. At a step S234, the pixel value 3 is set as the prediction value 7. At a step S235, a state transition is carried out by referring to the NMPS table 10. When LSZ (upper section width) is larger than, or equal to the A value (lower section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), a lower section width (present A register 31) is subtracted from the CHIGH register 37 at a step S236, and thereafter, the A register 31 is set to LSZ at a step S237. At this time, since the upper section is smaller than the lower section, LPS is decoded. At a step S238, the pixel value 3 is set as a non-prediction value (1-prediction value 7). When it is so judged at a step S239 that the constant SWTCH value 12 is equal to 1, the prediction value (MPS table) 7 is inversed/updated at a step S240. At a step S241, a state transition is carried out with reference to the NLPS table 11.
FIG. 29 shows an MPS_EXCHANGE process flow operation for decoding a lower section. When it is so judged at a step S251 that an LSZ value (upper section width) is smaller than an A value (lower section width) (namely, the answer is xe2x80x9cYESxe2x80x9d), the conditional MPS/LPS exchange is applied, and LPS is decoded. At a step S252, since the pixel value 3 is set to the non-prediction value (1-prediction value 7), while both the value of the A register 31 and the value of the C register 30B remain, the valid section is updated to a smaller lower section. Next, when it is so judged at a step S253 that the constant SWTCH value 12 is equal to 1, the prediction value (MPS table) 7 is inversed/updated at a step S254. At a step S255, a state transition is carried out with reference to the NLPS table 11. On the other hand, when it is judged at a step S251 that LSZ (upper section width) is larger than, or equal to the A value (lower section width) (namely, the answer is xe2x80x9cNOxe2x80x9d), MPS is decoded. At a step S256, the pixel value 3 is set to the prediction value 7. At a step S257, a state transition is carried out with reference to the NMPS table 10.
FIG. 30 indicates a RENORMD process operation for executing the renormalizing process operation. At a step S261, a check is made as to whether or not the variable CT50 is equal to 0. If the judgment result is xe2x80x9cYESxe2x80x9d, then at a step s262 a 1-byte code 4 is inputted to the C register 30B (Cb), and 8 is again set to the variable CT50. At a step S263, the value of the A register 31 is shifted to a 1-bit upper digit, and at a step S264, the value of the C register 30B is shifted to a 1-bit upper digit, so that such a calculation is carried out which is equivalent to a multiplication by 2. At a step S265, 1 is subtracted from the variable CT50. At a step S266, a judgment is made as to whether or not the renormalizing process operation is ended. If the value of the A register 31 is smaller than 0x8000, then the process operations defined from the step S261 to the step S265 are repeatedly carried out. A judgment is made as to whether or not the variable CT50 is equal to 0 at a step S267. When the judgment result is xe2x80x9cYESxe2x80x9d, the 1-byte code 4 is inputted to the C register 30B (Cb), and 8 is again set to the variable CT50 at a step S268.
It should be understood that in the above-described encoding calculation process operation and decoding calculation process operation, in accordance with the preceding technical publication (recommendation T.82) cited as the prior art, the above-mentioned steps S120, S130, and S220 are not described, but are directly described in the respective calculation formulae in the reference format of the LSZ table 9. In this case, for the sake of the below-mentioned descriptions according to the present invention, it is clearly indicated that an index ST [CX] may be consulted as a variable LSZ which is not indicated (namely, not table reference format) in a process flow operation.
In the known encoding method, encoding apparatus, decoding method, and also decoding apparatus, in such a case that the valid section is divided in the arithmetic encoding step and also the arithmetic decoding step, the fixed approximate value is allocated to the partial section irrespective of the valid section width. As a result, since the error contained in the occupation rate and the error contained in the predicted appearance probability of the symbol are increased, there is such a problem that the encoding efficiency is lowered.
The present invention has been made to solve this problem of the prior art, and has an object to provide a data encoding method, a data encoding apparatus, a data encoding method, and a data encoding apparatus, capable of improving an encoding efficiency by employing such a way that in a symbol of a probability for power of xc2xd, while a correction is made in such a manner that an occupation rate of a valid section becomes a probability value, partial sections are allocated.
With the above objects in view, the encoding apparatus of the present invention for predicting appearance probability of an information source symbol, while learning, and for dividing a valid section on a numerical straight line into both a first partial section to which an approximate value of the prediction appearance probability is applied and a second partial section remained in the valid section, to which such an arithmetic code is applied, the arithmetic code setting a partial section corresponding to an appearing symbol as a new valid section, comprises storage means for storing thereinto such a fact that the prediction appearance probability is a specific value, judgement means for judging that the prediction appearance probability is equal to the specific value by referring to the specific value of the storage means, and correction means for correcting an allocation between the first partial section and the second partial section when the judgement means judges that the prediction appearance probability is equal to the specific value.
Also, one of the specific values stored in the storage means may be selected to be xc2xd, and a series of calculation process operations executed in combination with updating of a predicable symbol value of the prediction appearance probability with respect to the relevant symbol may be independently constituted from a calculation process operation of an irrespective symbol.
In encoding operation applied to the relevant symbol, the correction means corrects the allocation, while assuming that both the first partial section and the second partial section are made equal to the valid section. The correction means is comprised of renormalizing means by which only a code is enlarged by executing either a 1-digit shifting process operation or a multiplication by 2 without changing the valid section, and thereafter, representation precision of the valid section is kept maximum by a procedure for calculating a code value, and code outputting means for outputting such a code which can be outputted after the code has been updated by the renormalizing means.

Data encoding method, data encoding apparatus, data decoding method, and data decoding apparatus


An annealing method of a zinc oxide thin film, comprises loading a substrate coated with a zinc oxide thin film into a chamber, allowing a hydrogen gas to be flowed into the chamber, fixing pressure in the chamber and annealing the zinc oxide thin film using the hydrogen gas in the chamber.

1. Field
This embodiment relates to an annealing method of a zinc oxide thin film.
2. Description of the Related Art
Zinc oxide (ZnO) is used for a transparent conducting oxide (TCO), an emitter, nano quantum dot array, a nanorod, a nanobelt and the like in photoelectric devices such as a thin film solar cell, a thin film transistor liquid crystal display (TFT LCD), an organic electro luminescence device (OELD), a blue light emitting diode (LED) and a laser diode (LD).
The zinc oxide is a material which has n-type conduction by electrons because the Fermi level of the zinc oxide is located near the conduction band even though the zinc oxide is a nominally undoped thin film.
In a process of manufacturing a zinc oxide thin film used in a thin film solar cell, a TFT LCD, an OELD, an LED or the like, a wet cleansing process is frequently performed to protect the zinc oxide thin film from impurities.
Accordingly, moisture may remain in the zinc oxide thin film after the wet cleansing process. In this case, the remaining moisture (H2O) may be easily absorbed on a grain boundary or surface of the zinc oxide thin film.
Moreover, when the zinc oxide thin film is formed using a chemical vapor deposition (CVD) process, H2O is used as a raw material gas. Therefore, H2O which is not reacted during the formation of the zinc oxide thin film may remain on the grain boundary or surface of the zinc oxide thin film.
As described above, H2O may remain in the zinc oxide thin film during the formation of the zinc oxide thin film or the wet cleansing process. In this case, when another thin film is deposited on the zinc oxide thin film, adhesion between the zinc oxide thin film and the another thin film is lowered, and therefore, the another thin film may be peeled off from the zinc oxide thin film.
Particularly, in a thin film solar cell, if moisture (H2O) remaining in a transparent electrode formed of a zinc oxide thin film is diffused in a silicon layer, an open-circuit voltage is lowered, and therefore, conversion efficiency of the thin film solar cell may be degraded. Accordingly, it is very important to remove the moisture (H2O) contained in the zinc oxide thin film for the purpose of manufacturing a thin film solar cell with high efficiency and high yield.
In an OELD, an organic film layer constituting a light emitting layer is deteriorated due to moisture (H2O) remaining in a zinc oxide thin film, so that the lifetime of the OELD may be reduced or light emitting efficiency may be degraded. Therefore, it is very important to remove the moisture (H2O) remaining in the zinc oxide thin film of the OELD for the purposed of improving characteristics of the OELD.
To remove moisture remaining in a zinc oxide thin film, a glass substrate on which a zinc oxide thin film is formed is loaded into a vacuum chamber, and the zinc oxide thin film is then annealed under a high vacuum state or an atmosphere of an inert gas such as nitrogen (N2) or argon (Ar), thereby removing moisture (H2O). However, the inert gas such as nitrogen (N2) or argon (Ar) is not diffused at a relatively high speed in the vacuum chamber, and therefore, processing time may be delayed.
Further, the inert gas such as nitrogen (N2) or argon (Ar) has a large molecular weight, and hence, it is not easy for the inert gas to be diffused through a grain boundary of the zinc oxide thin film. Therefore, the inert gas may not be effective to remove moisture absorbed on the grain boundary of the zinc oxide thin film.
Furthermore, the inert gas such as nitrogen (N2) or argon (Ar) does not serve as a dopant of the zinc oxide thin film, and therefore, electrical characteristics of the zinc oxide thin film may not be improved.

Annealing method of zinc oxide thin film


A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably xe2x80x9cshortxe2x80x9d wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.

1. Technical Field
The present invention relates to a method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving system resistance and characteristic impedance requirements.
2. Related Art
Semiconductor chip size continues to decrease, with an attendant increase in component density. The electrical signals which provide communication between chips, via electrically conductive wires or lines, are characterized by increasing operational frequencies. Semiconductor chips mounted on a printed circuit board (xe2x80x9cPCBxe2x80x9d) are subjected to detrimental effects caused by the inherent resistance of the PCB wiring which interconnects the semiconductor chips. A typical high performance printed circuit board has traditionally not been able to use wiring densities beyond a certain point due to limitations imposed by the DC resistance maximum in interchip wiring networks. Similarly, higher frequency signals also demand wide lines as a means to minimize xe2x80x9cskin effectxe2x80x9d losses in long lines. Unfortunately, it is problematic to generate dense wiring between a plurality of semiconductor chips on a PCB or chip carrier.
The usual solution is to use the typical geometry of wide wire lines and appropriate dielectric layer thicknesses to produce a 50 ohm transmission line characteristic impedance (Z0), and achieve a wiring network with a single wiring layer pair that uses only lower capacitance buried vias and a limited number of higher capacitance plated through hole vias. The result of this approach is that more wiring layers are required, and with a correspondingly thicker printed circuit board structure resulting. Future projections of component input/output (I/O) counts (e.g., approaching 4000 I/O counts with an I/O pitch of 0.8 mm) require a solution other than this usual practice.
An alternative is to use fine wire lines that widen when sufficient space is available. However, these wire lines do not maintain the necessary transmission line characteristic impedance (Z0) in all areas. These wire lines also have circuitization yield implications that make them unattractive in most printed circuit board applications.
Thus, there is a need for a method and structure that implements dense wiring, in printed circuit board or chip carrier applications, and which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements.
The present invention discloses a structure and associated method of implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements.
In addition, the present invention provides reduced thickness printed circuit boards by providing selective dense wiring layers, and enables dense designs that were heretofore difficult to wire.
The present invention provides a multilayered circuit board assembly comprising: a first wiring layer having at least one first conductor, each first conductor having a first cross-sectional area; a second wiring layer having at least one second conductor, the second conductor having a cross-sectional area smaller than a cross-sectional area of said first conductor; said multilayered circuit board assembly having a first area of high component density and a second area of lower component density; said first area of high component density connected to said at least one second conductor.
The present invention further provides a method of increasing circuit wiring density in a printed circuit board while maintaining an impedance level and reducing electrical noise, said method comprising: providing a first wiring layer containing at least one first wire type having a first impedance, said first wiring layer having a first conductor; providing a second wiring layer containing at least one second wire type having a second impedance, said second wiring layer having a second conductor; wherein the impedance of said first wire type is equal to the impedance of said second wire type; and wherein said first wire type is used to produce said first conductor, and said second wire type is used to produce said second conductor.
The present invention also provides a multilayered circuit board assembly having a plurality of networks, said multilayered circuit board comprising: a first wiring layer having at least one first conductor, the first conductor having a first cross-sectional area; a second wiring layer having at least one second conductor, the second conductor having a second cross-sectional area, said second cross-sectional area being smaller than said first cross-sectional area; said multilayered circuit board having a maximum wire resistance limit; and said second wiring layer having electrical connections to networks such that the total resistance of the network connections remains within a maximum wire resistance limit.
The present invention additionally provides a method of maintaining a characteristic impedance level in wires of a printed circuit board, said method comprising: providing a first wiring layer containing at least one first wire of a first type, wherein said first wire has a first cross-sectional area; providing a second wiring layer containing at least one second wire of a second type, wherein said second wire has a second cross-sectional area; wherein said first cross-sectional sectional area is not equivalent to said second cross-sectional area; and wherein said first wire and said second wire have the same electrical characteristic impedance.
The present invention therefore provides a method and structure that implements dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics, while preserving the system resistance and characteristic impedance requirements.

High performance dense wire for printed circuit board

International Business Machines Corporation


A system is provided for engine and generator control. The system includes a compound AC generator, a generator control unit (GCU) module and an engine electronic controller (EEC) module. The compound AC generator includes a shaft, and a permanent magnet generator (PMG) configured to be driven by the shaft to generate an AC power signal. The GCU module is configured to control the compound AC generator. The PMG is coupled to the GCU module and the EEC module such that it is configured to simultaneously supply the AC power signal to the GCU module and to the EEC module.

An aircraft includes an engine and an electric power generator that is the primary power supply for the aircraft when the engine is running. An Engine Electronic Controller (EEC) is a processor that monitors and controls parameters (e.g., fuel flow, pressures, temperatures, rpm, etc.) needed to make an aircraft's engine run as required. The EEC has a dedicated, independent power supply, called a Permanent Magnet Alternator (PMA). The PMA can be mounted on the engine gearbox, and serves as the primary electric power source for the EEC when the engine is running (e.g., rotating). When the engine is not running or when electrical power is not available from the PMA, electrical power from the aircraft is used to power the EEC.
A Generator Control Unit (GCU) is controller that monitors and controls electric power generated by the generator. The generator includes a small Permanent Magnet Generator (PMG) built into it for powering the GCU. The PMG has a similar power output as the independent PMA that powers the EEC.
It would be desirable to provide improved systems for controlling the generator and engine(s) of the aircraft. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

Apparatus and systems for engine and generator control within an aircraft


The food container has a top edge formed with a slot. The slot allows a ladle having a hooked rear end to be hung thereto when the ladle is placed on the inside of the food container, thereby preventing the ladle from dipping into the stew in the food container.

1. Field of the Invention
This invention relates to a food container which is provided with a ladle holding structure that can hold a ladle firmly in position inside the food container.
2. Description of Related Art
Pots are a kitchen utensil used to cook stews or soups. A pot is usually used with a ladle, which is a long-handled spoon with a deep bowl-like front end, for conveying the stew or soup in the pot into a dish for serving to the diner. By careless handling, a short-handled ladle might fall out of hand and dip into the stew. Since the handle is usually held by hand, the ladle submerged in the stew could cause contamination to the stew.
These problems of the conventional stew pot will be depicted illustratively in the following with reference to FIGS. 1 and 2.
FIGS. 1 and 2 show a conventional stew pot which has the disadvantages mentioned above. This stew pot includes a container 1 for containing the stew and a lid 5 for covering on the top of the container 1. On the top edge of the container 1, a groove 2 is formned circumferentially on the top edge of the container 1 for receiving the edge of the lid 5 when the lid 5 covers on the top of the container 1. A ladle 4 is used to convey the stew in the container 1 to, for example, a bowl for serving the stew to the diner.
If the ladle 4 has a short handle, as illustrated in FIG. 1, the ladle 4 would usually slip and thus dip into the stew after the diner puts the ladle 4 back into the container 1. It is very inconvenient to get the ladle 4 out of the stew and use it again for making servings.
On the other hand, if the ladle 4 has a long handle, as illustrated in FIG. 2, the rear part of the ladle 4 will be exposed to the outside of the container 1 when the bowl part of the ladle 4 is placed on the inside of the container 1. This will cause the lid 5 unable to cover the container 1 tightly, such that houseflies, dust, or any foreign objects could gain access to the stew.

Food container with ladle holding structure


Cold finished seamless steel tubes are made such that the residual stress F to be generated at the stage of the correction process after cold working is controlled to be 30 MPa or more and the scattering thereof is 30 MPa or less, when measured by Crampton method. Further, by adjusting the average grain size of spheroidized carbides, the dimensional change which emerges in lathe turning of the outside and inside diameter of relevant steel tubes due to the residual strain can be suppressed, and the strict roundness as well as the excellent machinability can be secured at the final processing stage of the work pieces for bearing parts. Consequently, steel tubes with high dimensional accuracy and less dimensional change at the final steps such as lathe turning, heat treatment and the like, can be made for use as bearing parts.

1. Field of the Invention
The present invention relates to the cold finished seamless steel tubes for use of bearing parts such as the retainer ring and the like, more particularly to the same, wherein the dimensional change emerged due to the residual strain at the stage of lathe turning of the outside and inside diameter of the relevant steel tubes is significantly small, and the excellent roundness as well as the superior machinability at the final processing stage of bearing parts are reliably secured.
2. Description of the Related Art
Normally, the seamless steel tubes which require high dimensional accuracy undergo cold working process for precise finish to the targeted outside diameter and wall thickness by either drawing through dies or pilger rolling, subsequent to hot working process by either Mannesmann method, Extrusion method or others being followed on by softening treatment such as spheroidizing anneal and the like.
Accordingly, in-process seamless steel tubes after cold working process are softened by annealing and the like, then subjected to correction process for straightening and securing highly round shape of cross section thereof, and subsequently undergo the inspection for final tube products to be shipped out. The correction process after cold working process is applied to straighten the bend generated in annealing and to rectify the oval-like cross section caused by annealing into round one, by usually utilizing multi-roller straightener or by 2-roll straightener.
The cold finished seamless steel tubes thus shipped out are cut into ring-like work pieces, then are subjected to lathe turning and polishing for the predetermined dimension to be widely used for bearing parts of various equipment, of which the representative examples in use are the retainer ring and the like of the bearing.
When the work pieces for bearing parts are produced by aforementioned cold finishing, the common processing steps from billets to final bearing products are exemplified by the following: hot working process→spheroidizing annealing→cold working process→softening anneal→correction process→mill inspection for shipping→cutting of tubes→lathe turning→quench and temper (heat treatment)→polishing→assembling.
Meanwhile, the steel tubes made by said processing steps generally entail the residual stress due to correction process after cold working and intrinsically come to hold the residual strain in themselves. Accordingly, the thin wall steel tubes that the outside diameter is 70 mm or more and the ratio of the wall thickness to the outside diameter is 10% or less, at the stage of the machining process such as cutting and lathe turning as well as at the stage of quenching as for final heat treatment, are likely to lose the roundness owing to said residual stress, consequently resulting in the dimensional nonconformance.
In case the marked residual stress should exist, the large deformation due to the relevant residual strain is generated, which causes the frequency of polishing operation for dimensional correction to increase significantly, and or arouse the problem of failing in dimensional correction by polishing because of excessive deformation.
In order to cope with these problems, various proposals are made up to this time. For instance, the Japanese Patent Application (Laid-open) Publication No. 10-137850 describes the correction process of seamless steel tubes made by Ugine-Sejournet method for leaving low residual strain by applying an optimal condition such that the electric current of the load onto the upper and lower roll in 2-roll line contact type straightening machine is controlled.
Further, the Japanese Patent Application (Laid-open) Publication No. 2001-329316 discloses that, in order to remove the residual stress built up by the correction process, the annealing is carried out at 520° C. to 630° C. and the marginal correction process by using 2-roll air bend type straightener is applied such that the offset and the crush are controlled at 5 mm or less, and 1.5 mm to 5 mm respectively, which enables to obtain the hot finished seamless steel tubes with less dimensional change at the stage of machining.
Whist, as the high demand for cost reduction in manufacturing bearing parts is recently increased, it is required to reduce the margin of machining in the step of finishing of the work pieces and to secure much more round tubes than ever. And then, the problem arises that the previous proposals above are not adequate to meet these requirements.


An optical sensor can be multiplexed for different clients/features including estimating information or characteristics of a user's physiological signals. Additionally, the clients/features can include estimating information or characteristics independent from a user's physiological signals. As the number of clients increase and/or as the requirements for the clients increase, flexibility can be provided to accommodate the various clients. Parallelization of the optical sensor can be used to improve performance as the number of clients increase. For example, the hardware and software architecture can assemble patterns of time slots that measure all desired light paths for the multiple clients and distribute the corresponding measurements to each client according to the client requests. In some examples, the scanning sequence can be represented by frames including slots associated with multiple clients to compress the representation for larger or more complex scan sequences.

Optical sensors can be used to implement various features. The features can include estimating information or characteristics of a user's physiological signals. For example, the information or characteristics can include various measures of heart rate and/or arterial oxygen saturation, among other possibilities. Additionally, the features can include estimating information or characteristics independent from a user's physiological signals. For example, an optical sensor in a wearable device such as a watch can be used to detect contact with a user's wrist, termination of contact with the user's wrist, and/or contact with a non-wrist surface (e.g., a table, pocket, etc.)

System and method for multiplexing an optical sensor


To test the processing of a data frame processing unit (FPU) which, in a normal working mode, processes input data frames applied to a data frame input (FI) thereof, the data frame processing unit (FPU) is brought in a test mode. Therefore, an active test signal is applied to a test mode control input (TCI) of this data frame processing unit (FPU). When brought in the test mode, the frame counters of the data frame processing unit (FPU) have lower limits and test data frames with smaller dimensions than the input data frames applied to the data frame input (FI).

Such a data frame processing unit and such a line termination module are already known in the art, e.g. from the article `A broadband ISDN line termination chip set for 1.2 Gbit/s`, written by P. Meylemans, L. Cloetens, K. Adriaensen and D. Sallaerts and published in 1993 in the USA by IEEE. Therein, a set of line termination chips performing external transmission termination functions, external transfer mode termination functions, conversion between external transfer mode and internal transfer mode, and switch fabric termination functions is described. These chips are in fact line termination modules including data frame processing units.
Standardized data frames, processed by such a data frame processing unit however are often very lengthy. STM-1 frames for example, as described in the CCITT Recommendation G.709, published in 1991, have a total length of 2430 bytes. Processing such data frames is very time consuming and consequently test simulations, for testing the functionality of individual samples of the above mentioned line termination chips, require time periods to the extent of several hours. Solutions to speed up the testing of a data frame processing unit or a line termination module are usually searched in the use of faster computers controlling this module or unit, but such computers are very expensive.

Frame processing unit with test mode, line termination module including such a frame processing unit, and method for testing such a frame processing unit


A predistortion linearizer may include a digital signal processor (DSP) for modeling a nonlinear characteristic of a high power amplifier (HPA) on a real time basis; a distortion signal generator for generating a distortion signal by using the signal modeled by the DSP; and a main path unit for combining the output signal of the HPA and the distortion signal of the distortion signal generator and transmitting an input signal without a distortion component. Since the nonlinear characteristic of the power amplifier is modeled on a real time basis to remove the distortion component contained in the output signal of the power amplifier, the nonlinear characteristic of the power amplifier is improved, and thus, an efficiency of the power amplifier can be maximized.

1. Field of the Invention
The present invention relates to a power amplifier, and more particularly, to a predistortion linearizer that is capable of improving a nonlinear characteristic, and its method.
2. Description of the Background Art
Generally, a power amplifier is used to increase power of a radio frequency (RF). An ideal power amplifier would increase only the magnitude without distorting an input RF signal.
However, since the power amplifier typically includes an active device having a nonlinear characteristic, an output of the power amplifier inevitably includes a distortion component. Thus, in order to improve the nonlinear characteristic of the power amplifier, various linearization techniques and algorithms are proposed. Typical linearization methods include a predistortion method, an envelope feedback method and a feedforward method or the like.
FIG. 1 shows the construction of a linearizer of a power amplifier adopting the feedforward method in a base station transmitting apparatus in accordance with a conventional art.
As shown in FIG. 1, a linearizer of a conventional power amplifier includes a main path unit 100 and a distortion signal detecting unit 200.
The main path unit 100 includes a modem 110 for generating a source signal; an analog baseband unit 120 for converting the generated source signal to a baseband analog signal; an up converter 130 for up-converting the converted analog signal; a gain and phase controller 140 for controlling a gain and a phase of the up-converted signal; a high power amplifier (HPA) 150 for amplifying the output signal of the gain and phase controller 140; a delay unit 160 for delaying the output signal of the HPA 150; a combiner 170 for combining the output signal of the delay unit 160 and the distortion signal generated from the distortion signal detecting unit 200 and removing a distortion component contained in the output signal of the HPA 150; a filter 180 for filtering the output signal of the combiner 170; and a transmission unit 190 for transmitting the filtered signal.
The distortion signal detecting unit 200 includes a delay unit 210 for delaying the output signal of the up-converter 130; a combiner 220 for combining the output signals of the delay unit 210 and the HPA 150 and detecting a distortion component contained in the output signal of the HPA 150; a gain and phase controller 230 for controlling a gain and a phase of the distortion signal detected by the combiner 220; and a distortion amplifier 240 for amplifying the output signal of the gain and phase controller 230 and outputting it to the combiner 170 of the main path unit 100.
The operation of the linearizer of the power amplifier adopting the feedforward method of the conventional art will now be described with reference to FIG. 1.
The source signal generated by the modem 110 is converted into a baseband analog signal by the analog baseband unit 120 and then converted into a radio frequency signal 130a. The converted radio frequency signal 130a is gain and phase-controlled by the gain and phase controller 140 and amplified to a predetermined level by the HPA 150.
At this time, the combiner 220 of the distortion signal detector 200 combines the output signals 130a and 150a of the up-converter 130 and the HPA150 which have been delayed by the delay unit 210, detects a distortion signal 220a contained in the output signal 150a of the HPA 150, and inputs the detected distortion signal 220a through the gain and phase controller 230 and the distortion amplifier 240 to the combiner 170 of the main path unit 100.
The combiner 170 combines the output signal 150a of the HPA 240 which has been delayed by the delay unit 150 and the distortion signal 220a amplified by the distortion amplifier 240, and outputs only an input signal 130b without the distortion component.
A spurious component of the output signal 130b of the combiner 170 is removed by the filter 180 and then the output signal without the spurious component is transmitted through the transmission unit 190.
However, as for the linearizer of the conventional power amplifier, if the input signal provided as an input of the power amplifier is distorted, an output signal of the power amplifier inevitably contains a distortion component no matter how excellent the performance of the power amplifier is.
Thus, in the linearizer of the conventional power amplifier, when the up-converter performs a frequency up converting, an output signal of the up-converter may contain the distortion component, which becomes an obstacle to improvement of the nonlinear characteristic of the power amplifier.
In order to improve the nonlinear characteristic of the conventional power amplifier, the final output of the power amplifier is lowly backed off so that the power amplifier can be linearly operated for the whole change interval of an input signal. In such a case, however, an efficiency of the power amplifier is much degraded.
In addition, the linearizer adopting the feedforward method exhibits a low efficiency compared to other linearization methods.

Predistortion linearizer and method thereof


A snap-hook that has a hook, forming a portion of an eye loop, and a lever that is pivotally movable relative to the hook. The lever forms a remaining portion of said eye loop with respect to the hook. A thumb tab is connected to the lever, and is positioned in a slot defined in the hook. The thumb tab is slidable in the slot relative to the hook, forming a release mechanism, such that the sliding movement of the thumb tab in the slot causes the lever to pivot relative to the hook to open said eye loop. The snap-hook has essentially broad, opposing, front and back sides, and relatively narrower edges, such that the back side of the snap-hook can be placed into the palm of a user's hand to hold the snap. The thumb tab is located on the front side of the snap-hook to allow simpler holding of the snap-hook and operation of the release mechanism with one hand while essentially eliminating swiveling of the snap-hook in the hand.

Snap hooks are used for a variety of purposes. Typically a snap-hook includes a hook and a lever that opens/closes the hook. Bolt snap-hooks provide a thumb operated spring-loaded plunger, with an up and down motion. To open the bolt snap-hook, pressure is applied to a thumb tab to push down the plunger. However, it can be difficult to depress/open that snap as the pressure to push the thumb tab down (to open) will cause the snap to swivel in the hand. This is due to the tab's location on the narrow width/edge of the snap. Also, the thumb tab must be depressed to attach the snap to an object.
Bull snap-hooks employ a swivel tab that pulls forward to open the snap-hook. However, this requires the use of two hands; one to hold the snap-hook and another to pull the tab outward. The "two handed" operation presents problems to users such as in the equestrian industry. For example, to attach or disconnect this snap-hook to a horse halter (when the snap-hook is used on a lead rope), the user must first let go of the halter to free both hands (momentarily losing control of the horse) in order to open the snap-hook for either attachment or disconnection of the snap-hook to/from the halter.
Marine snap-hooks incorporate a spring loaded tab, folding inward to open, to hook an object. However, disconnecting/opening this snap-hook from an object with one hand requires great dexterity, and can force the finger(s), used to push/fold back the tab, between the tab and the body of the snap-hook; a potentially hazardous operation. For most users, two hands are required to unhook this snap-hook.
There is, therefore, a need for an improved snap-hook that provides one-hand, easy, operation.


A sheet is produced by curing an energy ray curable composition which includes a urethane acrylate oligomer and a compound having a thiol group in the molecule. The sheet has heat resistance to prevent outgassing.

As for the substrates for adhesive sheets, resin films produced by polymerizing and curing photopolymerizable urethane acrylate oligomers have been used. Urethane acrylate oligomers are obtained by reacting a polyether polyol or polyester polyol compound and a polyisocyanate compound, as described in Patent Literature 1 (Japanese Patent No. 3739570). With respect to urethane acrylate oligomers from a polyester polyol compound, Patent Literature 2 (Japanese Patent No. 3177149) describes urethane acrylate oligomers that have structural units derived from polyester diol.
However, materials for the production of urethane acrylate oligomers having structural units from polyester diol are limited in variety and tend to be expensive. Urethane acrylate oligomers having structural units from polyether diol cause problems when cured resin films thereof are used in semiconductor-processing sheets such as surface protective tapes, dicing tapes and die-bonding tapes. In detail, because the semiconductor processing sometimes involves high temperatures, the weight of substrates reduce as a result of the outgassing through heat decomposing and are deteriorated to fail to achieve expected performance. Further, the outgassing fail to contaminate surrounding devices and the like.


A method and apparatus for manufacturing a rubber sheet containing short fibers. The method includes the steps of: mixing short fibers in a flowable rubber matrix; forming the flowable rubber matrix with the fibers therein into a cylindrical shape with a circumferential extent; separating a portion of the circumferential extent from the cylindrical shape, and forming the cylindrical shape with the portion separated into a sheet form.

1. Field of the Invention
This invention relates to rubber sheets, as used in the manufacture of power transmission belts and, more particularly, to rubber sheets containing short reinforcing fibers. The invention is directed to both a method and an apparatus for manufacturing such rubber sheets.
2. Background Art
It is known to form one or more layers of a power transmission belt from rubber with short reinforcing fibers embedded therein. It is known to mix short fibers with an unvulcanized rubber and to place the unvulcanized rubber with the fibers therein between a pair of calendar rolls operating at different rotational speeds. Through this mechanism, the lengths of the fibers orient substantially in the direction of advancement of the rubber through the cooperating rolls. The resulting sheet is then cut to a width, dictated by the particular belt configuration into which it is to be incorporated, and placed in a roll form. The sheet and one or more like sheets and/or other components are laminated to produce a desired thickness. The fibers in the sheets are oriented so that their lengths extend widthwise of a belt into which the sheets are incorporated, to increase the lateral stability thereof.
The components/layers of the belts are conventionally serially wrapped upon a drum during the manufacturing process. More particularly, a conventional manufacturing process for a V-ribbed power transmission belt, or a raw-edge V-belt, is carried out as follows. One or more sheets of a covering canvas and cushion ruber layer are wrapped onto the outer surface of a cylindrical molding drum. Load carrying cords are spirally wrapped around the cushion rubber layers. One or more compression rubber layers are wrapped in turn to complete a belt sleeve preform, which is vulcanized. The compression section of the belt may typically have a thickness defined by three to four such laminated layers. One or more layers of the sheets with the fibers embedded therein may be wound around the molding drum to produce a desired thickness in the compression section, or elsewhere.
As a practical matter, in order to consistently orient the short fibers using the process described above, the sheets must be relatively thin. This may ultimately require the superimposition of numerous sheets to produce the desired thickness for a particular sheet/layer. As a result, the manufacturing process may be complicated by having to laminate multiple sheets/layers of the rubber material having the short fibers embedded therein.
To avoid this problem, it is known to form rubber sheets of substantially greater thickness with consistently oriented short fibers using an extruding process employing an expansion die. An exemplary expansion die is shown in Japanese Examined Patent Application Publication No. 9847/1994. The expansion die therein has an annular expansion space with a diameter that increases between inlet and discharge locations. The width of the space also varies between the inlet and discharge locations. More particularly, the width at the entry location is narrower than at an intermediate location. The width at the discharge location is less than the width at the intermediate location and greater than the width at the entry location.
Japanese Unexamined Patent Application Publication No. 106602/1994 discloses an apparatus in which a cutter severs a cylindrical elastomer shape containing short fibers oriented in the circumferential direction continuously as the cylindrical shape discharges from a die. With this mechanism, an axial cut is continuously formed so as to allow the cylindrical shape to be formed into a flat sheet. Air is blown at the cylindrical shape between the die and the cutter so as to effect cooling thereof. This cooling inhibits shrinkage of the cylindrical shape in a circumferential direction as might disturb the orientation of the fibers that may occur as a result of non-uniform shrinkage. The problem of flaring is avoided by maintaining equal distances between the cut ends of the sheet and the center thereof.
In this conventional expansion die arrangement, the orientation ratio is three-dimensionally adjusted by a) controlling the space width ratios between the entry location and intermediate location and the intermediate location and discharge location, b) the radii of the entry and discharge locations, and c) the sectional areas. Because the orientation ratio is controlled by flow pressure, as dictated by the shape of the die, the orientation ratio can be changed only by changing the dies.
In the above-described prior art structure, flow of rubber is diverted from horizontal to vertical between a feeding cylinder and the expansion die. By reason of the orientation of the axis of the expansion die in a vertical direction, internal strain, such as deflection, can be made relatively small. Resultingly, the thickness of the cylindrical shape that is extruded in the expansion die can be consistently maintained. However, the construction described above has some drawbacks.
The prior art uses a cross head design which splits the incoming flow to the expansion die to effect uniform circumferential distribution of the material. Accordingly, a weld line is formed at the point of diversion. The split flow converges at a second weld line at a diametrically opposite location. The converging flows at the second weld line produce a random orientation of the fibers thereat and potentially a non-uniform thickness.
Preferably, the discharging cylindrical shape will be axially cut at the weld lines and thereafter reshaped into a sheet which is wrapped around a roll A, as shown in FIG. 5. The edges B, B′ in FIG. 5, bounding the cut produced at C, expand at an angle a, a′ to vertical, between the point of incision at C and the location where the roll A is located. Accordingly, portions of the cylindrical shape are significantly stretched vertically to facilitate the rolling shown in FIG. 5, whereas other portions, such as those diametrically opposite to the incision location, are not vertically stretched to any significant extent. It has been found that when the lengths D, D′ of the edges B, B′, between the incision location and the locations E, E′ at which the edges B, B′ engage the roll A, exceed a certain value, the elongation of the cylindrical shape may remain as a permanent strain, thus causing a flaring phenomenon upon the finished sheet.

Method and apparatus for manufacturing a rubber sheet containing short fibers


A method of calibrating a polar amplification stage including a main signal path and a magnitude signal path, the method comprising: generating signals (108, 142) for the main signal path and the magnitude signal path for operating an amplifier (102) between a linear mode of operation and a saturated mode of operation; detecting (114) first and second peaks in a signal at the output of the amplifier (102) representing transitions between the linear and saturated modes of operation; and adjusting (124) the timing in one of the main signal path and the amplitude signal path in dependence on a relative difference between the size of the detected first and second peaks.

1. Field of the Invention
The present invention relates to a polar amplification stage which is suitable for, but not limited to, a transmitter. The invention is particularly but not exclusively concerned with an amplification stage in which an envelope tracking (ET) modulator is utilised to provide a power supply to an RF amplifier.
2. Description of the Related Art
Polar amplification stages, also known as polar modulators, are well-known in the art, and comprise an arrangement in which separate magnitude and main signal paths are utilised in order to amplify a signal for transmission. Polar amplification stages are typically used in transmitters, such as transmitters for RF (radio frequency) applications. A mobile communication system RF implementation may use a polar amplification stage.
Known polar amplifiers utilise, for example, envelope tracking (ET) techniques or envelope elimination and restoration (EER) techniques. In an envelope tracking amplification stage a modulated power supply is generated for an amplifier in dependence on the envelope (magnitude) of the input signal to be amplified by the amplifier, and the input signal to be amplified is provided as the input of the amplifier.
It is an objective in such amplification stages to minimise the distortion in the transmitted signal. It is known that one cause of distortion is a result of the total delay suffered by the main signal (in a main signal path) and the total delay suffered by the magnitude signal (in a magnitude signal path) not being equal to each other. In order to meet system specification requirements, it is necessary to align the signal in the main signal path and the magnitude signal path to ensure that any timing misalignment between those signals falls within a permitted range. Any misalignment of the timing signals in the paths results in distortion of the transmitted signal, and can reduce transmitter efficiency.
With reference to FIG. 1 there is illustrated components of an exemplary known RF amplification architecture in which an envelope tracking (ET) modulator is used to provide a power supply to a radio frequency (RF) power amplifier.
As illustrated in FIG. 1, an RF power amplifier 102 receives an RF input signal to be amplified on an input line 136, and receives a modulated power supply voltage Vsupply on line 138. The RF power amplifier 102 generates an RF output signal on line 140. An example implementation of such an RF power amplifier is in mobile communication systems, with the RF output on line 140 connected to the front end of radio transmission equipment.
A signal generation block 122 receives a baseband signal (not shown) to be amplified by the amplifier 102. The signal generation block generates a signal on line 125a representing the envelope of the input signal to be amplified. The signal generation block 122 additionally generates I and Q components of the input signal to be amplified on lines 125b and 125c.
The generation of the envelope signal and the I and Q components of the baseband input signal is known to one skilled in the art. Various techniques for the generation of such signals may be implemented.
As illustrated in FIG. 1, the envelope signal on line 125a representing the envelope of the input signal to be amplified is converted by a digital-to-analogue converter 126a into an analogue signal, filtered by an optional envelope filter 128a, and then provided as an input to an ET modulator 108. The ET modulator 108 may be implemented using a variety of techniques. For example, the ET modulator 108 may incorporate a switched mode power supply for selecting between one of a plurality of supply voltages in dependence on the magnitude of the envelope signal, and a correction or adjustment stage for adjusting the selected supply voltage in dependence on an error determined between the selected supply voltage and a reference signal based on the envelope signal. An exemplary envelope tracking modulator is described in U.S. Pat. No. 7,482,869. The output of the ET modulator 108 forms an input to an output filter 106, and a modulated supply voltage is then provided through a supply feed 104 to provide the supply voltage on line 138.
The baseband I and Q components of the input signal on lines 125b and 125c are converted into analogue signals via respective digital-to-analogue converters 126b and 126c, and optionally filtered through respective I and Q filters 128b and 128c. The filtered I and Q components of the input signal are provided as inputs to a vector modulator, illustrated as respective multipliers 130a and 130b and a combiner 132. The combined output of the combiner 132 forms an input to a variable gain amplifier 134, the output of which forms an input to an optional inter-stage surface acoustic wave (SAW) filter 112. The output of the filter 112 provides the RF input signal to be amplified on input line 136 to the RF power amplifier 102.
As known in the art, the envelope path which the envelope signal follows from the digital-to-analogue converter 126a to generation of the supply voltage on line 138 to the power amplifier 102 suffers from delays which vary on a unit-by-unit basis within a production tolerance. As also known in the art the input or RF path which the baseband signal follows from the digital-to-analogue converters 126b and 126c to generation of the RF input signal to be amplified on line 136 suffers from delays.
In general, such delays need to be controlled so as to ensure that they fall within certain tolerances, usually smaller than the production tolerances, to ensure maximum operating efficiency of the power amplifier and to ensure certain spectral emissions requirements are met (such as a minimum distortion of the amplified output signal).
In the envelope path delays may be introduced by several stages, such as the filter 128a, the output filter 106, and the supply feed 104. In addition delays may arise in the ET modulator 108 itself.
In the input or RF path delays may also be introduced by several stages, such as the respective I and Q filters 128b and 128c, and in the inter-stage SAW filter 112.
It is an aim of the present invention to provide an improved technique for a polar modulator in which distortion in an amplified signal is reduced by controlling the relative delay between the main signal path and the magnitude signal path.
It is also an aim of the present invention to provide an improved technique for an envelope tracking power supply for an RF amplifier, in which distortion in an amplified signal is reduced by controlling the relative delay between in the RF signal path and the envelope signal path.

Time alignment for an amplification stage


A dynamic run-length encoding scheme compresses data streams more effectively than conventional run-length encoding, which uses a fixed group length for encoding. With dynamic compression according to the invention, the group length is dynamically modified by the bitstream itself. This allows for greater efficiency in compression. As with run-length encoding, the actual compression ratio is a function of the particular bitstream. However, for identical bitstreams, the invention achieves greater compression than run-length encoding. The invention has applications in compressing data that is used to program a programmable logic device, thereby effectively increasing the capacity of storage, such as Serial EPROM's, used for PLD programming files.

This application claims benefit of priority from provisional patent application 60/022,121, filed Jul. 17, 1996 and incorporated herein by reference.
The present invention relates to the field of data processing. In particular, it relates to the use of data compression in programming programmable logic devices.
Coassigned U.S. Pat. No. 5,563,592, entitled, PROGRAMMABLE LOGIC DEVICE HAVING A COMPRESSED CONFIGURATION FILE AND ASSOCIATED DECOMPRESSION and incorporated herein by reference to the extent necessary to understand the invention, discusses the desirability of using run-length encoding and decoding schemes for compressing the amount of configuration data that must be stored in order to program a programmable logic device. Run-length encoding has many applications. In programmable logic devices, however, one application for run length encoding allows the encoding to be done in a computationally intensive way in software, while the decoding is performed in a simple way on circuitry connected to the programmable logic device.
As the complexity of the programmable logic devices grows, so does the number of programmable elements used requiring configuration files with a greater number of "1s" and "0s" to program the programmable memory devices. As the size of the configuration files increases, so does the size of the EPROMs needed to store them. Large EPROMs are expensive and require large silicon area to be manufactured. The size of the silicon area is more important when the EPROM is manufactured on the same substrate as the programmable logic device. The size of the EPROMs limit the complexity of the programmable logic device.
What is needed is an apparatus and method for further reducing the size of the configuration files used in a programmable logic device before they are stored in memory. Such techniques have applications in other areas where run-length encoding is desirable.


A current sensor device includes a bus bar that is to be connected to a plate-shaped terminal of a semiconductor device, a magnetoelectric conversion element that is configured to detect a current flowing through the bus bar, and a resin portion that integrally holds the magnetoelectric conversion element and the bus bar. The bus bar has one end protruding from the resin portion, and the one end of the bus bar includes a penetration portion defined by wall surfaces. The wall surfaces includes a pair of opposing wall surfaces opposing to each other. At least one of the opposing wall surfaces is configured to be connected to the terminal.

It has been known a current sensor device arranged on a semiconductor device including a switching element and a plate-shape terminal. The current sensor device includes a bus bar having one end connected to the terminal of the semiconductor device, a current sensor for detecting a current flowing in the bus bar, and a resin portion integrally holding the bus bar and the current sensor.