Provided is a task allocation optimizing system that, for a development target system which has a plurality of states and which is provided with multi-cores, makes an allocation of tasks to the cores such that a performance of the target system does not significantly degrade in a specific one of the states.

In response to a recent growing demand for a higher performance and lower power consumption of digital devices, a multi-core configuration in which a plurality of processor cores (hereinafter, each referred to as just a "core") is mounted in a large scale integration (LSI) has been drawing attention. A development of such a multi-core configuration based LSI has also become an important technology in real-time systems or the like aiming at system control.
Methods for this multi-core system are roughly classified into a symmetric multi-processing (SMP) method and an asymmetric multi-processing (AMP) method.
In the SMP method, task switching is performed in accordance with a situation of an available capability of each of cores, a priority of each of tasks currently being executed, and the like, and each of tasks can be executed on any one of the cores. For this reason, it becomes possible to implement an automatic load distribution, so that a performance of the whole system is enhanced. Nevertheless, such an automatic load distribution makes it difficult to grasp a real-time performance beforehand, and thus, it is difficult to apply the SMP method to a real-time system.
Meanwhile, the AMP method is based on a function distribution type configuration in which each of tasks is executed on its specific core. For this reason, the AMP method is suitable for a system, such as a real-time system for which it is important to be able to grasp behaviors of the system beforehand, or an embedded system in which there are restrictions on cores each connected to specific hardware.
In a multi-core system employing such an AMP method, its performance differs depending on to which of cores each of tasks is allocated. For this reason, in such a multi-core system employing the AMP method, it is necessary to search various task allocations and determine an optimum task allocation so that the multi-core system can be placed in an optimum operation state.
Hereinbefore, description has been made by providing a multi-core system employing the AMP method as an example. The above description is generally applicable to not only a multi-core system employing the AMP method but also a multi-core system employing a function distribution type method in which tasks are allocated to individual tasks on a fixed basis.
In Japanese Unexamined Patent Application Publication No. 2007-264734 (hereinafter, referred to as "patent literature 1 (PTL 1)", there has been disclosed a technology for a tuning support device which enables efficient software tuning for a multi-core processor provided with a plurality of cores. FIG. 21 illustrates a configuration of a tuning support device disclosed in PTL 1.
In the tuning support device, first, a granularity information acquiring unit 201 acquires information related to granularity allocated to each of cores (hereinafter, this information being referred to "granularity information"). This "granularity" is a unit of processing performed by, for example, a processor, and is a generic term representing a scale of a task, a function, or further, processes constituting a function.
A structure information generating unit 204 calculates a total appearance number for each of tasks or for each of functions included in tasks on the basis of the acquired granularity information, and generates information related to the calculated total appearance number (hereinafter, this information being referred to as "structure information").
A dependency information generating unit 206 generates information related to dependencies on other tasks or other functions (hereinafter, this information being referred to as "dependency information") for each of tasks or for each of functions included in tasks, on the basis of the acquired granularity information. An output unit 203 outputs these kinds of information.
Through this configuration, the tuning support device can efficiently analyze and manage the structure information for use in a load distribution. Though the use of information resulting from this analysis, for a multi-core processor, tasks are allocated to individual cores such that a processing performance of the multi-core system is enhanced.

This patent is subject to a terminal disclaimer.

Task allocation optimizing system, task allocation optimizing method and task allocation optimizing program

Abstract: The task allocation optimizing system according to the present invention performs optimization by calculating, for each of the states, a state-evaluating-function value, which represents the preferability of an allocation to the cores, through using a task set operating in the state, and further calculating a consolidated evaluating-function value as a whole of operation of the target system, through consolidating the state-evaluating-function values for all states targeted for an evaluation.


Greenhouse comprised of a ridge beam extending some distance above its roof defining two elongated side zones at either side of the ridge beam. The ridge beam is comprised of one or more elongated hollow spaces and with one or more closable openings in both side zones. The openings fluidly connect the exterior of the greenhouse with its interior and may be closed at one side and opened at its other side depending on the direction of the wind.

The invention is directed to a greenhouse comprised of transparent walls and a structure comprising of one or more ridge beams as part of a roof of the greenhouse. The invention is also directed to a novel ridge beam. The invention is also directed to a method to condition the air within a greenhouse.
DE8426219 describes a building with a ventilating ridge beam. The beam construction is provide with two elongated flaps which can simultaneously open and close thereby providing a ventilation opening.
DE1454648 describes a greenhouse provided with a window near the ridge beam allowing air to escape the greenhouse.
Such a greenhouse is described in WO17176114. In FIGS. 1 and 2 a schematic representation of a greenhouse with a saddle roof is shown. In the roof ventilating windows are present to discharge excess air from the interior of the greenhouse to the exterior of the greenhouse. Such ventilating windows are typically present in every saddle roof at a regular interval. A disadvantage of such ventilating windows is that the frames and controls to operate the window take away light and thus negatively affect the efficiency of the greenhouse to grow plants. Furthermore, local pressure differences and temperature differences may result from the internal gas flows towards these windows.

Van der Hoeven Horticultural Projects B.V.


A socket, adapted for electrically connecting a printed circuit board to an IC package, comprises a housing and a plurality of contacts arranged in an angular fashion within the passageways. The housing defines a mating face and a mounting face opposed to the mating face and a number of angular passageways extending from the mating face to the mounting face. Each contact includes a bend portion, a first leg and a second leg extending from two opposed ends of the bend portion. The second leg has an arc contacting portion extending out of the mating face for contacting with the IC package. Firstly a solder ball is disposed on a bottom surface of the bend portion and soldered to the printed circuit board to mount the contact to the printed circuit board. Or secondly the contacts (Mounting end) have no solder balls and solder paste is applied to PCB then connector is placed onto PCB and reflow soldered into place without use of solder balls.

1. Field of the Invention
The present invention relates to the art of electrical connector, and more specifically to a socket for electrically interconnecting two electrical interfaces, such as an IC (Integrated Circuit) package and a printed circuit board.
2. Description of the Prior Art
Generally speaking, a connector to which this invention is applicable is interposed between first and second electronic parts or components having contact pads, respectively, to achieve electrical connection between the first and the second electronic components. In the following description, the first and the second electronic components are a printed circuit board and an IC Package, respectively.
A conventional connector, referring to Korsunsky U.S. Pat. No. 6,447,304 issued to Huang et al. on Sep. 12, 2002, comprises a housing, and a plurality of contacts received in the housing. Each contact is formed by punching and bending an elastic metal plate, so that each contact comprises a generally U-shaped portion comprising a first leg portion, a second leg portion, a bridge portion connecting top ends of the first and the second leg portions and an extension portion obliquely and downwardly extending from a bottom end of the first leg portion. The extension portion has a curved end portion as a lower end portion and a first contact point formed on the curved end portion to be brought into contact with the contact pad of the printed circuit board. The bridge portion has a second contact point on its top portion to be brought into contact with the contact pad of the IC package. The contact is inserted into corresponding contact receptacle hole defined on the housing and held at a predetermined position.

Socket with contact for being soldered to printed circuit board


An object-oriented framework comprises system services, objects, and integration interfaces which unify retrieval and browsing of data among multiple different application programs, document formats, and local and remote data storage sites. The framework provides a hyperlink object which encapsulates general hyperlink navigation functions. The hyperlink object has a moniker which references a hyperlink's target, and a location string which designates a location in the target. The hyperlink object uses the moniker to retrieve the target as an object in the framework, and causes the object to display a view of the target at the location. The framework also provides a browse context object which maintains a navigation stack of navigated hyperlink targets, and allows passing of window and navigation tool bar position information to a frame in which the target is displayed to effect the appearance of window reuse when navigating between frames. The framework also includes a cache and table of running objects to speed return navigation to recently navigated targets.

Previous techniques and mechanisms for navigating to and retrieving data in a computer system have had significant drawbacks which pose obstacles to providing unified tools for browsing data seamlessly and transparently from all sources (including local storage, local networks, and remote networks).
An example of a previous system for navigating to and retrieving data is the user interface of the Microsoft Windows® 95 operating system. This interface displays "folder views" which show the contents (e.g., files and sub-directories) of file system directories (also referred to as "folders") on the computer's local storage (e.g., hard or floppy disk drive) or a connected local area network ("LAN"). The folder views show files in a folder using one of four display modes: large icon, small icon, list, and details. A user navigates to a document by opening successive folder views beginning with a "my computer" or "network neighborhood" folder view (which are a top or "root" folder in the file systems of the local storage and LAN, respectively), and then selecting a particular file represented in the folder view. In response, the operating system loads an application program associated with the file, and causes the application program to "open" the file. This results in the application program displaying the contents of the file in a window (i.e., rectangular display area on the computer monitor's screen).
These folder views provide a unified and consistent way of navigating to data stored as files in a computer's local storage or on a connected LAN. But, navigation using the folder views also is limited in many respects. The folder views do not permit equivalent navigation to data stored remotely, such as on the Internet or on-line services. The folder views also do not retain any navigation "state" information, which would allow retracing or returning to data which has been previously navigated. The only state remaining after navigation with a folder view is that the folder view in which a file is selected remains open as a separate window in the Windows® 95 user interface.
Another example of a previous navigation system is an Internet browser, such as the Netscape Navigator or the Microsoft® Internet Explorer. Internet browsers have generally supported navigation using hyperlinks between hypertext documents residing on the World-Wide Web. The Internet is a global network of cooperatively interconnected computer networks, consisting of millions of individual computers. A portion of the Internet referred to as the "World-Wide Web" consists of computers, also referred to as "sites," which make multi-media documents in hyper-text mark-up language (HTML) format generally available for downloading or retrieval by individuals having a computer with Internet access.
The HTML documents can contain "hyperlinks," which are references (e.g., in the form of a uniform resource locator or URL) to another HTML document on the World-Wide Web or to another part of the same document. Generally, the hyperlinks are displayed as underlined or otherwise highlighted text, or a graphic within the document which the user can activate by "clicking" using a mouse or other input device. When a hyperlink is activated, the Internet browser navigates to the document that the hyperlink references by retrieving and displaying the referenced document in place of a currently displayed document.
Internet browsers typically maintain navigation state information in the form of a navigation log or "history" of previously navigated documents. The Browser uses the history to provide "go back" and "go forward" controls with which the user can backtrack and retrace a path between previously navigated documents. Some browsers also provide a "favorites" or "bookmark" feature with which the user creates a list of user-selected HTML documents for future reference. The user can later return to the document by selecting it from the favorites list.
However, previous Internet browsers also have failed to provide unified browsing of different varieties of data from different sources. The typical previous Internet browser is an HTML document viewer application which can display an HTML document within an application window, and supports hyperlink navigation which replaces one HTML document with another in the same application window. (An application window is the display area under control of the application in a graphical user interface (GUI) of an operating system.) This typical browser cannot display other varieties of documents (e.g., a Microsoft® Word application document), and doesn't allow hyperlink navigation to such documents. In short, such typical browsers allow hyperlink navigation between only HTML documents and only within a single application window.
One browser, the Microsoft® Internet Explorer, version 2.0 (hereafter the IE 2.0 browser), supports hyperlink navigation to a non-HTML document in a separate application window. More specifically, if the destination document of a hyperlink is a non-HTML document, the IE 2.0 browser determines the application associated with the document (such as by looking up the document's file name extension in the Windows® operating system registry) and causes that application to be launched with the document opened in a separate application window (e.g., through a shell execute command of the Windows® operating system). For example, if the user activates a hyperlink to a Microsoft® Word document at a URL on the Internet, the IE 2.0 browser causes the Microsoft® Word application to be loaded (if the application is installed on that computer) and to open the document in its window.
However, the IE 2.0 browser still fails to provide unified navigation. When a hyperlink is navigated to a separate application window of a non-HTML document with the IE 2.0 browser, hyperlink navigation is effectively "dead-ended." To continue hyperlink navigation, the user must switch windows back to the IE 2.0 browser window. There also is no "go back" hyperlink control or command available to return from the non-HTML document in the separate application window back to the HTML document in the IE 2.0 browser window. Instead, the user must switch windows using operating system mechanisms, such as the "control+escape" or "control+tab" hot key combinations of the Microsoft Windows® operating system. Thus, hyperlink navigation in the IE 2.0 browser is still limited to a single application window since the separate application window of a non-HTML document cannot fully participate in hyperlink navigation.
Further, the hyperlink navigation of the IE 2.0 browser to a non-HTML document in a separate application window does not have the same effect as typical hyperlink navigation. In typical hyperlink navigation, navigating a hyperlink replaces the document which contains the hyperlink with another document that is the destination or target of the hyperlink. Conversely, when navigating to a non-HTML document, the IE 2.0 browser causes an application associated with the non-HTML document to be launched in a separate window. This separate application window can be nearly anywhere on the computer screen, and may be either windowed or full screen (typical application windows retain the size and position settings from when they were last open). Meanwhile, the HTML document that contains the hyperlink remains open in the IE 2.0 browser window. As a result, unless both the IE 2.0 browser window and the separate application window both happen to be full-sized, the document displayed in the separate application window does not replace the HTML document in the IE 2.0 browser window and may not overlap any part of the IE 2.0 browser window.
A unified browsing environment based on the hyperlink navigation browsing model is provided in the present invention by an object-oriented framework and system having objects, programming interfaces, object integration interfaces, and methods for supporting unified navigation among different varieties of documents, data, and application programs. The invention overcomes the limitation in previous Internet browsers of navigating within a single application window, and provides seamless navigation between multiple document types and applications.
According to one aspect of the invention, the object-oriented framework includes a hyperlink object which encapsulates information needed to navigate a hyperlink, and the action of navigating the hyperlink. In the illustrated embodiment of the invention, the hyperlink object is a system-defined object which supports an integration interface that allows other programs to use the hyperlink object for navigating the hyperlink. The hyperlink object contains a moniker to a target of the hyperlink, a character string designating a destination location within the target, a descriptive name for the hyperlink ("friendly name"), and other parameters.
According to another aspect of the invention, the object-oriented framework further includes a browse context object and integration interfaces for a hyperlink container object, a hyperlink target object and a hyperlink frame object. The browse context object maintains a history of navigated hyperlinks, and other context information for hyperlink navigation including window size and position. The integration interfaces of these objects allow multiple different applications to interact with the browse context so as to participate fully in hyperlink navigation. With the browse context and integration interfaces, the applications can provide "go back" and "go forward" controls which retrace prior hyperlink navigation activity between the applications. The applications also can use the browse context to position and size the destination application window of the hyperlink so as to create the appearance of replacing the originating application window of the hyperlink. The system thereby allows seamless hyperlink navigation between different document types and applications.
According to a further aspect of the invention, the system also includes a set of programming interfaces which allow applications to participate in unified browsing without implementing objects to support the integration interfaces.
Additional features and advantages of the invention will be made apparent from the following detailed description of an illustrated embodiment which proceeds with reference to the accompanying drawings.

Object-oriented framework for hyperlink navigation


A rectifier circuit includes a MOSFET (M1), and a first Zener diode (D1) or a first Zener-emulator (E1) that emulates the D1. The circuit conducts current in a forward direction from an input to an output, and substantially blocks current in a reverse direction. The M1 is characterized by an on-resistance. A cathode of the D1 or a cathode-contact of the E1 is connected to the input, and the anode of the D1 or an anode-contact of the E1 are connected to the source. The E1 includes a first small-Zener-diode (D11), a first resistor (R11) and a first transistor (M11) interconnected such that the E1 emulates the D1, and is characterized by a Zener-voltage. The Zener-voltage and the on-resistance are selected such that a stored-charge in the body-diode is less than a forward-charge-threshold when current flows in the forward direction, whereby the reverse recover time of the body-diode is reduced.

It is known to use a diode to conduct current in a forward direction and substantially block current in reverse direction. However, in some instances, the circuit in which a diode function is needed either cannot tolerate or suffers performance degradation due the reverse recovery time of the diode when the biasing of the diode transitions from forward biased to reverse biased. What is needed is a rectifier circuit that provides a diode like function with reduced reverse recovery time.

Rectifier circuit with reduced reverse recovery time


A robust method for addressing each of the participants of a bus system comprising a control unit, and a bus and a plurality of addressable participants connected to the bus, comprising the steps of a) pre-selecting a first number of participants, b) selecting from the pre-selected participants a second number of participants, and c) assigning one or more addresses to them, and repeating the steps a) to c). The selection and pre-selection is based on current sources, specific threshold values, and measurement error. The bus system and addressable device (are also claimed.

For minimizing the wiring complexities, for example in vehicles, it is common practice to transmit control signals for driving actuator devices via a bus to which, besides a control unit, the drive units for the actuator devices of the individual participants are connected. Combined to form a bus system are, for example, the actuator devices of a vehicle air conditioner, the window lift or the front seats of a vehicle. To enable the control unit to selectively drive one or a plurality of actuators, addresses are assigned to said actuators.
In older systems the addresses have been assigned to the participants in that they have been stored by programming, assigned via daisy chain, plug or PIN coding, or by sequential connection of the participant and allocation of the addresses after connection of a participant.
While programming is relatively easy during the manufacture of a vehicle, this is more complicated when the overall participant, i.e. the combination of the actuator device plus the drive unit, is, for example, replaced in a repair shop. Further, with regard to the logistics it is necessary that defined placement sequences are adhered to, which involves service inconvenience and the supply of pre-programmed (pre-addressed) components, which runs counter to the "identical-part principle" used in the automotive industry. The plug coding involves high costs due to the mechanical expenditure, and with regard to the stored address or the pin coding the logistics is complex since in this case no longer identical parts are involved such that these parts are no longer easily interchangeable. In the case of a daisy chain it is possible to realize the self-addressing of the participants of a bus system via switches for serially separating the bus connections between the participants. The drawbacks encountered in this regard are in particular the electrical disconnection of the bus line via active components and the large space requirement for bus systems which comprise a lot of participants.
Automated address allocation methods for bus systems are known in the art. A first group of bus systems, as e.g. described in U.S. Pat. No. 6,397,280B1, uses a circuit breaker (switch) for decoupling part of the chain from the master (also called "control unit"). So, at start-up, the master only "sees" the first slave (also called "participant"), and assigns a first address. Then the first slave closes its switch, and the master "sees" the second slave, etc. In this way each slave on the bus can be allocated a unique address, starting from the slave closest to the master.
A second group of bus systems uses the principle of sensing currents. In such a bus system, addresses are sequentially assigned to each slave, starting from the slave most distant from the master.
U.S. Pat. No. 7,091,876B2 describes such a bus system, (see also FIG. 1 of the present invention, which is a replica of FIG. 1 and FIG. 7 of U.S. Pat. No. 7,091,876B2). The functioning of this bus system will be described in detail here, in order to allow a good understanding of the present invention. FIG. 1 shows the setup of a serial bus system 10 (e.g. LIN-bus). The bus system 10 comprises a control unit 12 (master) to which a bus 14 is connected. Along the bus 14 a plurality of addressable participants (slaves) 16.1, 16.2, . . . , 16.n−1, 16.n (in general denoted 16.i below) are connected to said bus 14. All participants 16.i and the control unit 12 are connected to a supply voltage VDD and a ground voltage GND and can, at option, apply said potentials to the bus 14. The control unit 12 comprises a control circuit shown at 18 which applies control and addressing signals to the bus 14 and/or receives signals from the participants 16.i via the bus 14. The control circuit 18 drives a switch 22 with the aid of which the bus 14 is connectable via the control unit 12 with GND. Between VDD and the bus 14 a pull-up resistor 24 is located. All participants 16.i of the bus system 10 shown in FIG. 1 are equipped with an addressing logic 26 which is connected with a detector 28 and a control circuit 30. The control circuit 30 is connected with the bus 14, and the detector 28 measures, via a shunt resistor 32 located in the bus 14, the current flowing through the bus 14, in the area of the participant concerned, as a voltage drop which is amplified via an amplifier 34. Other variants of the detector 28 are also possible, provided that the detector 28 is in a position to measure the current flowing through the bus 14 in the area of the connecting node 36 of a participant 16.i. The control circuit 30 further controls a switch 38 in each participant 16.i, while the switches 40, 42 of each participant 16.i are controlled by the participant's addressing logic 26. The switch 38 connects, at option, the bus 14 with GND, while the switch 40 places the bus 14 via a pull-up resistor 44 to VDD, and the switch 42 connects the bus 14 with a current source 46 which feeds into the bus 14 an identifying current required for identifying a participant 16.i. Instead of a current source 46 a second pull-up resistor (not shown) may be arranged, provided that the VDD-potential is stable. In this embodiment the participants 16.i drive respective actuating members 48 assigned to the participants 16.i, said actuating members 48 being connected via an interface 50 with the control circuit 30 of the participant 16.i concerned. With the aid of the pull-up resistors and the switch 40 (in the closed state) the bus 14 is placed to VDD-potential in the area of each participant 16. When the switch 40 is closed, a quiescent current IR, is fed into the bus 14. The connection of the bus 14 with VDD via the pull-up resistors 44 results, inter alia, in an interference-immunity of the bus 14, which is known for bus applications of the kind discussed here. For the sake of completeness it should be said that in all connecting lines of the control unit 12 and the participants 16.i comprising the aforementioned switches inverse-polarity protection diodes are provided which, however, like the switches 38 of the participants 16.i, are of no importance for the automatic addressing process described below. The initial situation for addressing the participants 16.i is shown in FIG. 1. The switch 22 of the control unit 12 and the switches 40 of the participants 16.i are closed, while the switches 38 of the participants 16.i remain open all the time. In this situation, the participants 16.i, which are designated in the drawing 16.1, 16.2, 16.n−1 and 16.n to allow better distinction between the participants (wherein n is the total of all participants), feed quiescent currents IR1, . . . , IRn. It should be noted here that feeding of quiescent current during the addressing process is not absolutely necessary. If no quiescent current is fed, merely the switch 22 of the control unit 12 is closed at the beginning of the addressing process, while all other switches of the control unit 12 and the participants 16.i are open. When quiescent current is fed, currents of different magnitudes flow at the level of the different participants 16.i through the bus 14, said currents being detected with the aid of the detectors 28. The quiescent currents flow from the connecting nodes 36 of the participants 16.i to the control unit 12 where the quiescent currents flow off to GND. Due to arrangement of the detectors 28 behind the connecting nodes 36 (when looking at the bus 14 from the control unit 12), the detector 28 of the participant 16.n connected to the bus 14 at a location farthest away, as seen from the control unit 12, does not detect any quiescent current, the detector 28 of the participant 16.n−1 detects the quiescent current IRn, the detector 28 of the participant 16.2 detects a quiescent current which is equal to the sum of the quiescent currents IR3 to IRn of the participants 16.3 (not shown) to 16.n, and finally the detector 28 of the participant 16.1 detects a quiescent current which is equal to the sum of the quiescent currents IR2 to IRn. The respective currents detected by the participants 16.1 to 16.n during this phase are stored in the addressing logic 26. After a defined period of time the participants 16 not addressed so far close their switches 42. As described above in conjunction with feeding of the quiescent currents, currents with different magnitudes occur after feeding of the addressing currents IA1 to IAn in the individual sections of the bus 14, which currents are detected by the detectors 28. Apart from the detector 28 of the last participant 16.n, all other participants 16.1 to 16.n−1 now detect a current on the bus 14, said current exceeding the value previously measured and stored in the addressing logic 26 by the magnitude of an identifying current (the identifying currents of all participants have the same magnitude). In other words: the participant 16.n is identifiable. If in the next step the control unit 12 applies an addressing signal to the bus 14, this signal is accepted only by the participant 16.n and placed into the addressing logic 26 of this participant. The participant 16.n addressed in this manner does not take part in the further addressing process. As already explained above, the addressing process does not require measurement of the quiescent current. Thus in the addressing logic 26 of the participants 16 no current values are stored when feeding of the identifying current begins. The participant to be addressed during the first addressing cycle can then be identified by its detector 28 not detecting any current flow despite the fact that an identifying current is being fed. When the current detection in each participant 16 is carried out before its connecting node 36 (when looking at the bus 14 from the control unit 12), identification of a participant to be identified in an addressing cycle is effected by the detector 28 of this participant detecting a current equal to the identifying current, while the other participants detect a current which is at least twice as large as the identifying current. In this manner, a participant can be identified. Above, the first addressing cycle of the automatic addressing process has been described for a case in which the control unit 12 applies, after identification of a participant, an addressing signal to the bus 14. Alternatively, it is also possible to apply the addressing signal to the bus prior to the identification, and to store said signal in the addressing logic 26 of all participants 16.i. In this case, only the identified participant accepts the previously received addressing signal as its own address, while this addressing signal is deleted in the addressing logics 26 of the other participants. After termination of the first addressing cycle the addressed participant 16.n does no longer take part in the further process, i.e. the switch 42 of the participant 16.n remains open. In the manner described above, the participant 16.n−1 can be identified and thus addressed. The process described above is continued until all participants are identified, one by one.
U.S. Pat. No. 7,091,876B2 also describes a second embodiment of a bus-system, identical with the setup of the bus system 10 shown in FIG. 1, whereby the addressing process takes into account that the current flowing on the bus 14 does not exceed a predetermined maximum value. This boundary condition exists, for example, in LIN-bus applications. The initial situation for addressing according to this alternative process is shown again in FIG. 1. All participants 16.i feed their quiescent currents. In a first phase, each participant 16.i detects the respective current flowing through the bus 14. If this current detected by at least one participant exceeds a predetermined threshold value, this fact is interpreted to the effect that participants not addressed so far are connected behind this participant, when looking at the bus 14 from the control unit 12, such that the said participant and all participants connected to the bus 14 between this participant and the control unit 12 do no longer take part in the further addressing process. It is assumed that, as shown in FIG. 1, the participant 16.2 has detected in the bus 14 a current exceeding a threshold value. Therefore the participants 16.1 and 16.2 do not take part in the subsequent feeding of identifying current, such that identifying currents from the participants 16.3 (not shown) to 16.n are fed. The identification within this group of participants feeding identifying currents is then carried out in the manner described above, wherein in the first addressing cycle the participant 16.n is identified and an address can be assigned to this participant. During the next identifying cycle the switch 42 of the participant 16.n remains open all the time. Again, at the beginning of the next identifying cycle all participants 16.1 to 16.n−1 not addressed so far feed their quiescent currents. It should be assumed that during this addressing phase, too, the participant 16.2 detects a current exceeding a threshold value, such that, as has already been described in conjunction with the first addressing cycle, the participants 16.2 and 16.1 do not take part in the further addressing process in the second addressing cycle. The identification and addressing during this second cycle are then carried out in the manner described above and result in identification and/or addressing of the participant 16.n−1. The process described above is continued until a situation occurs in which the participant 16.2 does no longer detect a current value exceeding the threshold value while quiescent current is being fed. If this situation occurs for the first time during the addressing process, the participant 16.1, instead of the participant 16.2, detects a current still exceeding the threshold value while all participants feed their quiescent current. The participant 16.2 then takes part in the identifying and addressing cycle like the participants connected to the bus 14 behind the participant 16 when looking at the bus 14 from the control unit 12. The participant 16.1, however, does not take part in this process step.
U.S. Pat. No. 7,091,876B2 also describes a third embodiment of a bus-system, similar to the setup of the bus system 10 shown in FIG. 1, but whereby besides addressable participants, also non-addressable participants are connected to the bus. These devices already have a fixed address, and do not take part in the addressing cycle described above. They can, however, feed a quiescent current into the bus, which is measured first.
A disadvantage of the bus systems described in U.S. Pat. No. 7,091,876B2 is that it is difficult, and sometimes even impossible, to find suitable threshold values for guaranteeing that each slave is assigned exactly one address. This is especially true in an automotive environment, where devices from multiple vendors are used, and where the parameters of the devices may vary considerably (e.g. due to process variations and varying supply voltage), and where the number of devices may change even after production (e.g. during after-sales service).

Method for addressing the participants of a bus system


A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations.. A method of executing a succession of instructions in a computer system is also described.

Common operations by a processor in a computer system require identification of one or more sources of data to form an input to the processor as well as a destination for receiving the result of operating the processor. Conventional reduced instruction set computers (RISC devices) have used instructions all of a common bit length and format defining both the operation to be carried out by the processor as well as identification of two sources of data for use in the operation, and a destination for the result of the operation. Such instructions have been used to manipulate data that is found in addressable store locations such as registers or memory. When using a processor in a pipelined operation to execute a sequence of instructions it may be necessary to hold a plurality of live data items which are accessible by subsequent instructions. This requires sufficient number of addressable locations to be identified by an instruction that it either imposes a limit on the shortness of the instructions that can be used or a limit on the number of address locations that can be covered by an instruction set.
Other systems are known with complex instructions, (CISC devices) and such long instructions have provided the facility for identifying the addresses of more data stores used for holding live data during the pipelined processing of an instruction sequence. However such long instructions have required greater access time in obtaining the instructions from memory and may involve more extensive decoding needing more cycles of operation to achieve decoding of each instruction.
It is an object of the present invention to provide a computer system with instructions having a reduction in the number of address bits relative to the number of data items that may be held during instruction execution.

System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis


In a switched mode inductive DCDC converter having a first mode that conducts a first current path through an inductor and through a first switch, and a second mode that conducts a second current path through the inductor and through a second switch, a detecting component detects a parameter. The detecting component outputs a biasing signal extend the turn OFF time of one of the switches in order to decrease a voltage build up on the other switch.

The present invention is generally drawn to a switched mode inductive circuit.
FIG. 1 illustrates a conventional switched mode inductive DCDC converter 100.
As shown in the figure, switched mode inductive DCDC converter 100 includes an input node 102, an inductor 104, a controlling component 106, a power stage 108, a capacitor 110 and an output node 112. Controlling component 106 includes a driving component 114, a driving component 116 and a controller 118. Driving component 114 includes a switch 120 and a switch 122. Driving component 116 includes a switch 124 and a switch 126. Power stage 108 includes a switch 128 and a switch 130. Also shown in switched mode inductive DCDC converter 100, are parasitic inductances 132, 134 and 136.
In the example switched mode inductive DCDC converter 100, switch 120 is a p-channel field effect transistor (p-FET), switch 122 is an n-channel field effect transistor (n-FET), switch 124 is a p-FET, switch 126 is an n-FET, switch 128 is a p-FET and switch 130 is an n-FET.
Inductor 104 is disposed between input node 102 and power stage 108. P-FET 128 is disposed between inductor 104 and output node 112. N-FET 130 is disposed between inductor 104 and ground. Inductor 104, n-FET 130 and p-FET 128 are connected at a node 158. Capacitor 110 is disposed between output node 112 and ground. P-FET 120 and n-FET 122 are disposed between input node 102 and ground, wherein the source of p-FET 120 is connect to input node 102 and wherein the source of n-FET 122 is connected to ground. The drain of p-FET 120 and the drain of n-FET 122 are connected to the gate of n-FET 130 of power stage 108 via a line 138. The gate of p-FET 120 and the gate of n-FET 122 are connected to controller 118 via a line 140. P-FET 124 and n-FET 126 are disposed between input node 102 and ground, wherein the source of p-FET 124 is connect to input node 102 and wherein the source of n-FET 126 is connected to ground. The drain of p-FET 124 and the drain of n-FET 126 are connected to the gate of p-FET 128 of power stage 108 via a line 142. The gate of p-FET 124 and the gate of n-FET 126 are connected to controller 118 via a line 144.
Input node 102 is operable to receive an input voltage, Vin. Inductor 104 is operable to output a first voltage, V1, in a first state and a second voltage, V2, in a second state.
Controlling component 106 is operable to control power stage 108. In particular, controller 118 is operable to control driving component 114 via a control signal 146 on line 140, and is further operable to control driving component 116 via a control signal 148 on line 144. Control signal 146 alternately actuates p-FET 120 and n-FET 122, which in turn provides a bias signal 150 to control n-FET 130 of power stage 108 via line 138. Similarly, control signal 148 alternately actuates p-FET 124 and n-FET 126, which in turn provides a bias signal 152 to control p-FET 128 of power static 108 via line 142.
Power stage 108 operates in a first mode, wherein a current path indicated by arrow 154 travels through inductor 104, through n-FET 130 and to ground. Power stage 108 operates in a second mode, wherein a current path indicated by arrow 156 travels through inductor 104, through p-FET 128 and to output node 112.
Capacitor 110 acts as a low pass filter.
In operation, for purposes of discussion, let conventional switched mode inductive DCDC converter 100 be operating in a first mode, wherein current travels along current path 154. In this mode, controlling component 106 first control power stage 108 such that p-FET 128 is OFF and n-FET 130 is ON. In this case, input node 102 receives Vin, which creates a current along current path 154, through inductor 104, through n-FET 130, through parasitic inductor 136 and finally to ground.
Now, let conventional switched mode inductive DCDC converter 100 switch from the first mode to the second mode, wherein during the switch, there is no current path. While switching between modes, controlling component 106 controls power stage 108 such that, while p-FET 128 remains OFF, n-FET 130 is turned OFF. There should be some time with which p-FET 128 and n-FET 130 are both OFF, to avoid the situation where both switches may be ON, which would short output node 112 to ground.
Then, let controlling component 106 control power stage 108 such that p-FET 128 is turned ON and n-FET 130 remains OFF. In this case, input node 102 receives Vin, which creates a current along current path 156, through inductor 104, through p-FET 128, through parasitic inductor 132 and finally to output node 112.
Conventional switched mode inductive DCDC converter 100 may continue to switch back and forth between the two modes as discussed above, wherein there is a period during the switching when both of p-FET 128 and n-FET 130 are OFF.
At any switching event, the current through inductor 104 needs to change from current path 154 to current path 156, or vice versa. This produces switching loses and therefore reduces the efficiency of the voltage conversion from Vin to Vo. As such, it would be beneficial to switch as quickly as possible. The problem with quickly switching modes is that there are parasitic inductances coming, from bonds wires, PCB and passive components, for example as shown as parasitic inductances 132, 134 and 136. The parasitic inductances do not allow the current to quickly change from current path 154 to current path 156, or vice versa, in zero time. When the dI/dt in the parasitic components reaches high levels that are too high, the parasitic inductors cause voltage ringing. Further, the parasitic components may cause a voltage build up at the drain of one of p-FET 128 or n-FET 130 that could destroy these components. This voltage ringing and voltage build up will now be further described with additional reference to FIGS. 2-4.
FIG. 2 illustrates the voltage at node 158, between the n-FET 130 and p-FET 128, when conventional switched mode inductive DCDC converter 100 switches modes.
The figure includes a graph 200 and a graph 202. Graph 200 includes a y-axis 204, an x-axis 206, a pulse 208 and a pulse 210. Graph 202 includes a y-axis 212, an x-axis 214, a function 216 and a threshold voltage, Vth, indicated by a dotted line 217.
Y-axis 204 has a scale of zero, corresponding to when a FET is OFF, or 1 unit, corresponding to when a FET is ON. X-axis 206 is time and is in units of microseconds. Pulse 208 corresponds to n-FET 130 being ON until a time t1. Line 220 corresponds to n-FET 130 turning OFF, until it is fully OFF at time t2. Therefore, in this case, n-FET 130 takes a period Δt1 to turn OFF. At some time later, p-FET 128 turns ON. Line 221 corresponds to p-FET 128 turning ON, until p-FET 128 is fully ON as shown by line 210.
Y-axis 212 corresponds to a voltage at the drain of n-FET 130 and is measured in volts. X-axis 214 is time and is in units of microseconds. Function 216 corresponds to a voltage at the drain of n-FET 130 as a function of time. Function 216 includes a rising portion 218, a maximum portion 220 and a small ringing portion 222. Dotted line 217 corresponds to Vth, wherein n-FET 130 risks being damaged.
As shown in graph 200, n-FET 130 does not immediately turn OFF. It starts to turn OFF at time t1, and finishes turning OFF at time t2, after Δt1. During that period turning OFF, the current changes from current path 154 to current path 156, creating a parasitic voltage Vpar:Vpar=L*dI/dt,   (1)wherein L s the inductance of parasitic inductors 132 and 136 and dI/dt is the current change. This Vpar builds at the drain of n-FET 130. The voltage reaches a maximum as shown by maximum portion 220. The slope of rising portion 218 is a function of the rate at which n-FET 130 turns OFF, i.e., Δt1. Parasitic capacitances in n-FET 130 resonate with the parasitic inductors within the circuit to generate ringing portion 222. The generation of ringing portion 222 will now be described in greater detail with reference to FIG. 3.
FIG. 3 illustrates parasitic capacitances and inductances associated with n-FET 130 of FIG. 1.
As shown in FIG. 3, a parasitic capacitance 302 is disposed at node 158. Further, in addition to parasitic inductance 136, there exists a parasitic diode 304 in parallel with p-FET 128 not shown), wherein the anode of parasitic diode 304 is disposed toward node 158.
FIG. 3 shows the situation at the moment when n-FET 130 is turned OFF. In this situation, the inductor current, at the moment when n-FET 130 could no longer conduct it, needs to go through parasitic inductance 136 and parasitic diode 304. However an inductor cannot have such a jump in current. This means that physical inductance continues to drive current while it takes a while until parasitic inductance 136 to build up the current. Until the full current can be conducted by parasitic inductance 136, the remaining current is flowing into parasitic capacitance 302, which keeps increasing the voltage at node 158. Parasitic inductance 136 builds up current with a change in the current, i.e.,dI/dt=Vpi/Lpi   (2)wherein Vpi is the voltage across parasitic inductance 136 and wherein Lpi is the inductance of parasitic inductance 136.
Returning to FIG. 2, if maximum portion 220 were to be greater than Vth, then there is a possibility that n-FET 130 may be damaged. This may happen under many circumstances, non-limiting examples of which include operating conventional switched mode inductive DCDC converter 100 at extreme temperatures, and individual component degradation resulting from age or use.
For example, for purposes of discussion, let the period that it takes n-FET 130 to turn OFF increase as a result of operation of conventional switched mode inductive DCDC converter 100 under an extreme temperature. The resulting effect of ringing and voltage build up will be described in greater detail with reference to FIG. 4.
FIG. 4 illustrates the voltage at node 158, between the n-FET 130 and p-FET 128, when conventional switched mode inductive DCDC converter 100, operating in a less than optimum manner, switches modes.
FIG. 4 includes a graph 400 and a graph 402. Graph 400 includes a y-axis 404, an x-axis 406, a pulse 408 and pulse 210. Pulse 208 of FIG. 2 is additionally shown as dotted lines for comparison purposes. Graph 402 includes a y-axis 412, an x-axis 414, a function 416 and threshold voltage, Vth, indicated by dotted line 217. Function 216 of FIG. 2 is additionally shown as a dashed line for comparison purposes.
Y-axis 404 has a scale of zero, corresponding to when a FET is OFF, or 1 unit, corresponding to when a FET is ON. X-axis 406 is time and is in units of microseconds. Pulse 408 corresponds to n-FET 130 being ON until time t1. Line 410 corresponds to n-FET 130 turning OFF, until it is fully OFF at time t3, wherein t3 is less than t2 discussed above with reference to FIG. 2. Therefore, in this case, n-FET 130 takes a period of Δt2 to turn OFF. At some time later, p-FET 128 turns ON.
Y-axis 412 corresponds to a voltage at the drain of n-FET 130 and is measured in volts. X-axis 414 is time and is in units of microseconds. Function 416 corresponds to a voltage at the drain of n-FET 130 as a function of time. Function 416 includes a rising portion 418, a maximum portion 420 and a ringing portion 422.
As shown in graph 400, n-FET 130 does not immediately turn OFF. It starts to turn OFF at time t1, and finishes turning OFF at time t3, after Δt2. During that period of turning OFF, just as discussed above, the current changes from current path 154 to current path 156, creating a parasitic voltage Vpar. In this case, the current change is more drastic than that discussed above with reference to FIG. 2. This is because the period, Δt2, for n-FET 130 to totally turn OFF in this case, is much smaller than the period, Δt1, discussed above with reference to FIG. 2. This can easily be seen by comparing pulse 208 with pulse 408 in FIG. 4.
Just as in the previous example discussed with reference to FIG. 2, in this example Vpar builds at the drain of n-FET 130. The slope of rising portion 418 is a function of the rate at which n-FET 130 turns OFF, i.e., in this case, Δt2. In this case, the slope of rising portion 418 is much greater than the slope of rising portion 218 of function 216. The increased slope translates into a greater voltage build up, which can be seen by comparing maximum portion 420 to maximum portion 220 of function 216. In fact, in this case, maximum portion 420 is greater than Vth, thus risking damage to n-FET 130.
Finally, similar to the situation discussed above with reference to FIG. 2, in this case, parasitic capacitances in n-FET 130 resonate with the parasitic inductors within the circuit to generate ringing portion 422.
What is needed is needed is a switched mode inductive DCDC converter that decreases the likelihood of damage to its components, decreases ringing, and maximizes the overall speed of the circuit

Switched mode DCDC converter efficiency improvement by adaptive driver stage


The composite elastic yarn may be made from a wide, stretchable textile fabric or stretchable knitted fabric. A composite elastic yarn is obtained by drawing an elastic yarn 11 at a first draft rate to prepare a precursor composite elastic yarn with an inelastic yarn 31 and further drawing the precursor composite elastic yarn at a second draft rate of a value smaller than that of the first draft rate to make a composite with the removable inelastic yarn 31; and stretchable textile fabric and stretchable knitted fabric fabricated using this composite elastic yarn.

1. Field of the Invention
The present invention relates to a composite elastic yarn, stretchable textile fabric and stretchable knitted fabric using the same.
2. Description of Related Art
Conventionally, regarding a stretchable textile fabric or a stretchable knitted fabric using polyurethane elastic composite yarn, its maximum extension width is restricted by a reed space of a weaving machine or a shuttle diameter of a knitting machine, so that special equipment is required in order to obtain a wider cloth-like structure.
For example, in the case where a general weaving machine with a reed space of 190 cm is used, a finishing width of 127 cm is produced whereby the finished textile fabric has a stretch rate of 30% to 40%. It has been difficult to obtain a cloth-like structure with a double width (150 cm). In order to obtain a cloth-like structure with a double width, a special wide weaving machine with a reed space of 220 cm has been required. This double width is extremely advantageous and a high market need exists for such a product.

Composite elastic yarn and manufacturing method thereof, stretchable textile fabric, and stretchable knitted fabric


The present invention provides electric charge controlling resin formed with the use of a polymer which has a polar group for imparting an electrostatic charge and of which flow rate Rf as measured by a thin-layer chromatography using silica gel as an adsorbent and ethyl acetate as a developing solvent, is in a range from 0.5 to 1.0. Toner may be prepared by mixing and dispersing the electric charge controlling resin in a binding resin, or by suspension-polymerizing a polymerizable composition under the condition where the electric charge controlling resin is contained in the composition to obtain a binding resin. The toner thus prepared is excellent in the electrostatic chargeability, humidity resistance, coloring properties and reproducibility.

In the field of electrophotographic copying or electrostatic printing, it is a common practice to use, for developing an electrostatic latent image, toner in the form of colored resin particles containing coloring agents and electric charge controlling agents dispersed in a resin medium.
Generally, the toner is composed of resin particles containing coloring agents, electric charge controlling agents and the like as mixed and dispersed in binding resin. To provide the toner with desired color and electrostatic chargeability, it is a common practice to suitably change the types and blending amounts of the binding resin, coloring agents, electric charge controlling agents and the like to be used.
As a toner manufacturing method, there is generally adopted a so-called pulverization method by which a resin medium and coloring agents are molten and kneaded to prepare toner in the form of particles having a predetermined range of particle size. However, the toner thus produced by the pulverization method contains particles having irregular shapes and presents a poor fluidity. Further, the individual irregular particles of the toner are electrically, charged in considerably different manners, causing the distribution of electrostatic charge to become broad. Further, the pulverization method requires facilities of great size, resulting in increased production cost.
It is also proposed to manufacture toner by a suspension polymerization method. According to this method, a polymeric composition in the form of a mixture of an initiator of polymerization with toner characteristic imparting agents such as polymeric monomers, coloring agents, electric charge controlling agents and the like, is suspended, under stirring at a high speed, in an aqueous solution containing a dispersion stabilizer. Then, this mixture is polymerized to directly produce toner. This toner manufacturing method using suspension polymerization may directly produce toner in the form of particles of which sizes are in a practical range, at the resin polymerization step. This results in decrease in production cost. Further, this method presents the advantage that the resultant toner is excellent in fluidity and stability of electrostatic charge.
Such a toner manufacturing method using pulverization or suspension polymerization uses an electric charge controlling agent for adjusting the characteristics of toner electrostatic charge. As the electric charge controlling agent, a variety of dyes are generally used. Since the electric charge controlling agent controls the developing properties of the toner, it is important to properly select the electric charge controlling agent.
More specifically, the demands for an image forming apparatus are recently versatile according to applications and are extended to a variety of performances such as smaller-size, lower-energy, higher-speed, multi-colors, maintenance-free and the like. Accordingly, to accomodate to the developing system or inside environmental conditions of the apparatus, the toner is required to have different characteristics according to the apparatus types and colors used. Therefore, a great number of types of toner are apt to be produced in a small amount. It is therefore required to manufacture, with good reproducibility, toners of which characteristics are subtly different. In view of the foregoing, the selection of the electric charge controlling agent is important.
However, the dyes are hardly compatible with resin and a polymeric monomer. Accordingly, a great amount of dyes should be added to obtain a sufficient electrostatic charge. Further, since the dyes are present in the form of particles in resin and a polymeric monomer, the electrostatic chargeability of the resultant toner considerably vary with the quality of dispersion of the dyes. Such variations may cause image fog, toner scattering and uneveness of an image quality. Further, when the dyes are used for color toner requiring light permeability, the dyes dispersed in the form of particles inhibits such light permeability, failing to form a clear color image. In addition, the dyes are generally expensive, leading to increase in production cost.
In view of the foregoing, to uniformly stabilize the characteristics of toner electrostatic charge, in particular to improve the starting electrostatic chargeability, it is proposed to mix and uniformly disperse binding resin and a copolymer, serving as electric charge controlling resin, composed of (i) a monomer having a polar group and (ii) an oil-soluble monomer compatible with the binding resin or a monomer capable of forming the binding resin, so that the electrostatic charges of individual toner particles are made uniform. For example, Japanese Unexamined Patent Publication No. 88564/1988 discloses toner containing a polymer (copolymer) having a sulfonate group connected to an aromatic ring.
It is found that the sulfonate group disclosed in this Publication is excellent in electric charge imparting properties and that the use thereof for toner improves the electrostatic chargeability such as starting and stabilization of the electrostatic charge, and the like.
However, the inventors of the present invention have found the following facts. That is, even though the monomer having a polar group (sulfonate group or the like) and the oil-soluble monomer in the electric charge controlling resin are substantially the same in monomer composition ratio, the dispersibility of the electric charge controlling resin in the binding resin considerably depends on the polymer structure or molecular weight of the electric charge controlling resin which varies with change in production conditions, difference in raw materials used between lots, and the like. This presents the problems that the electrostatic chargeability undergo a change, that the water vapor resisting properties are lowered, and that the hue varies, failing to repeatedly produce the toner having desired characteristics with good reproducibility.
Consideration is then made on the use of the electric charge controlling resin for manufacturing toner by the suspension polymerization method. The polar group for controlling the electric charge of the electric charge controlling resin is also water-soluble. Accordingly, when the electric charge controlling resin as mixed in a polymeric composition is subjected to suspension polymerization, the electric charge controlling resin is eluted from the suspension oil drops into water. Further, the emulsification by the water-soluble polar group of the electric charge controlling resin thus eluted, causes a by-product in the form of particles with 1 .mu.m or less to be produced. This may not only reduce the productivity, but also deteriorate the electrostatic chargeability, durability and water vapor resistance of the toner.
It is a main object of the present invention to provide electric charge controlling resin excellent in electric charge imparting properties and dispersion in binding resin.
It is another object of the present invention to provide electric charge controlling resin which is adapted not to be eluted in an aqueous phase in a suspension polymerization step while being maintained in suspension oil drops until the polymerization is complete, and which may be uniformly and evenly dispersed in the oil drops.
It is a further object of the present invention to provide a toner producing method capable of manufacturing toner having improved durability with good productivity and without production of a by-product in the form of particules at a suspension polymerization step.
It is still another object of the present invention to provide electric charge controlling resin capable of imparting uniform and highly reproducible electrostatic chargeability.
It is a still further object of the present invention to provide toner having desired characteristics and a method of producing such toner in a system of producing a great number of types of toner in a small amount.
It is yet another object of the present invention to provide toner which may be economically produced with increased productivity, and a method of economically producing such toner with increased productivity.
It is a yet further object of the present invention to provide toner which is excellent in starting and stability of electrostatic charge and light permeability, and which is also excellent in coloring properties and water vapor resistance, and to provide a method of producing such toner.

Electric charge controlling resin, toner made with the use of the same and method of producing the toner


Compounds of the general formula I are provided:

The invention relates to acyclic sulfamides and bis-sulfamides useful as inhibitors of proteolytic enzymes. The invention further relates to general templates for use in designing combinatorial libraries, screening and identification of biologically active, peptidomimetic protease inhibitors. There are four classes of proteases: serine, cysteine, aspartic and metalloproteases.
Degenerative diseases associated with serine proteases such as human leukocyte elastase (HLE) include cystic fibrosis, chronic obstructive pulmonary disease (e.g., emphysema and asthma), adult respiratory distress syndrome (ARDS), inflammatory bowel disease, chronic bronchitis, psoriasis, rheumatoid arthritis, pancreatitis, periodontal disease, and other inflammatory diseases
A variety of cyclic mechanism-based inhibitors of serine proteases are known. Exemplary protease inhibitors include sulfonyloxy derivatives of isothiazolidin-3-one 1,1-dioxides (Groutas et al., Biochemical and Biophysical Research Communications 1997(2):730 (December, 1993)), 1,2,5-thiadiazolidin-3-one 1,1-dioxides (Kuang et al., J. Am. Chem. Soc. 121:8128 (September 1999)) and 3-alkyl-N-hydroxysuccinimides (Groutas et al., J. Med. Chem. 32:1607 (1989)). These compounds react irreversibly with a variety of serine proteases via a sequence of steps involving binding of the inhibitor molecule to the active site of the enzyme, nucleophilic ring opening of the cyclic inhibitor, rearrangement of the ring-opened structure to provide a reactive intermediate, followed by irreversible reaction of the compound with a second site on the enzyme, resulting in enzyme deactivation.
Diseases associated with cysteine proteases include cancer metastasis, osteoporosis and osteoarthritis (McGrath et al. Nature: Structural Biology 4(2):105 (1997)), bone resorption, muscular dystrophy, parasitic diseases (leishmaniasis, malaria) (Li et al. Bioorg. Med. Chem. 4(9):1421 (1996); Rosenthal et al. J. Clin. Invest. 91:1052 (1993)), inflammation, common cold (Webber et al. J. Med. Chem. 39:5072 (1996)), and hepatitis A (Malcolm et al. Biochemistry 34:8172 (1996)). Many known cysteine protease inhibitors are peptidyl aldehydes, halomethylketones and Michael acceptors (xcex1,xcex2-unsaturated groups).
Matrix metalloproteinases (MMPs), such as collagenase, stromelysin and gelatinase, are involved in connective tissue breakdown. Metalloproteinase (MMP) inhibitors are of potential value in the treatment of neuroinflammatory disorders, including those involving myelin degradation, for example, multiple sclerosis, as well as management of angiogenesis-dependent diseases, proliferative retinopathies, neovascular glaucoma, ocular tumors, angiofibromas and hemangiomas. See, WO 95/35275, entitled xe2x80x9cMetalloproteinase Inhibitorsxe2x80x9d. Many known metalloproteinases are characterized by the presence in the structure of a zinc(II) ion at the active site, and thus, most known MMP inhibitors typically include hydroxamic acid or carboxylic acid to bind zinc. For example, arylsulfonamide-substituted hydroxamic acids have been reported as matrix metalloproteinase inhibitors. See, U.S. Pat. No. 5,455,258 to MacPherson et al.
The present invention makes available a new class of compounds useful as protease inhibitors. The open sulfamide structure is anticipated to be more stable chemically than related closed ring structures, e.g., 1,2,5-thiadiazolidin-3-one 1,1-dioxides, yet show high inhibition of proteolytic activity.
The invention features a compound having the general formula I
and pharmaceutically acceptable salts thereof, wherein,
Z is a chemical species or R1 capable of binding at a primary specificity site of a protease;
Y is a chemical species reactive to a specific class of protease;
each of R2, R3, R5 and R7 is independently selected from the group consisting hydrogen, alkyls, aryls, substituted aryls, alkylaryls and arylalkyls;
R4 and R6 are independently selected from the group consisting of:
(a) H, alkyl, aryl, arylalkyl, alkylaryl, substituted derivatives thereof, and Ri;
(b) xe2x80x94C(O)OH and derivatives thereof, said derivatives selected from the group consisting of xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94C(O)[NHCHRi(q)C(O)]qNRYRZ; and
(c) xe2x80x94CHRiNH2 and derivatives thereof, said derivatives selected from the group consisting of xe2x80x94CHRiNHW, xe2x80x94CHRiNHC(O)OQ, xe2x80x94CHRiNHC(O)R, xe2x80x94CHRiNHC(O)NRYRZ, xe2x80x94CHRiNHC(O)[NHCHRi(q)C(O)]qOQ, xe2x80x94CHRiNHSO2R, and xe2x80x94CHRiNH[C(O)CHRi(r)NH]rW,
where q and r independently are integers from 1 to 10 inclusive;
where J is a carboxyl protecting group;
where G is an amino protecting group;
where Q is H, R or J;
where W is H, R or G;
where each Ri is independently selected from naturally or non-naturally occurring amino acid side chains;
where R is alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical; and
where each RY and RZ is independently H, alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical.
In another aspect of the invention, a compound of the general formula III, is provided, and pharmaceutically acceptable salts thereof,
wherein
Z is a chemical species or Ri capable of binding at a primary specificity site of a protease;
Y is a chemical species reactive to a specific class of protease;
R30 is selected from the group consisting of hydrogen, alkyls, aryls, substituted aryls, alkylaryls or arylalkyls;
R31 is selected from the group consisting of alkyl, aryl, arylalkyl, alkylaryl, substituted derivatives thereof, Ri, xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)R, xe2x80x94SO2R xe2x80x94[C(O)CHRi(r)NH]rW, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94C(O)[NHCHRi(q)C(O)]qNRYRZ; and
R32 is selected from the group consisting of alkyl, aryl, substituted aryl, arylalkyl, alkylaryl, Ri; xe2x80x94CHRiC(O)O, xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94[C(O)CHRi(r)NH]rW;
where q and r independently are integers from 1 to 10 inclusive,
where Q is H, R or J, and J is a carboxyl protecting group,
where W is H, R or GI and G is an amino protecting group;
where each Ri is independently selected from naturally or non-naturally occurring amino acid side chains,
where R is alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical, and
where each RY and RZ is independently H, alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical.
In another aspect of the invention, a compound of the general formula IV is provided, and pharmaceutically acceptable salts thereof,
wherein
Z is a chemical species or Ri capable of binding at a primary specificity site of a protease;
Y is a chemical species reactive to a specific class of protease;
R30 is selected from the group consisting of hydrogen, alkyls, aryls, alkylaryls or arylalkyls;
R34 is aryloxy, arylalkyl, xe2x80x94CHRiNHW or xe2x80x94NHCHRiC(O)OQ; and
R35 is alkyl, aryl, alkylaryl, arylalkyl or amino acid side group, Ri,
where Q is H, R or a carboxyl protecting group;
where W is H, R or an amino protecting group; and
where R is H, alkyl, aryl, substituted aryl, alkaryl, aralkyl, or heterocyclic radical.
In another aspect of the invention, a compound of the general formula V is provided and pharmaceutically acceptable salts thereof,
wherein
Z is a chemical species or Ri capable of binding at a primary specificity site of a protease;
Y is a chemical species reactive to a specific class of protease;
R30 is selected from the group consisting of hydrogen, alkyls, aryls, alkylaryls or arylalkyls;
R36 is alkyl, aryl, alkylaryl, arylalkyl or amino acid side group, Ri.;
R34 is aryloxy, arylalkyl, xe2x80x94CHRiNHW or xe2x80x94NHCHRiC(O)OQ,
where Q is H, R or a carboxyl protecting group;
where W is H, R or an amino protecting group; and
where R is H, alkyl, aryl, substituted aryl, alkaryl, aralkyl, or heterocyclic radical.
In still another aspect of the invention, a compound having the general formula II, and pharmaceutically acceptable salts thereof, is provided,
wherein
Z is a chemical species or Ri capable of binding at a primary specificity site of a protease inhibitor;
Y is a chemical species reactive to a specific class of protease inhibitor;
each of R2, R3, R5, R7 and R8 is independently selected from the group consisting of hydrogen, and saturated, unsaturated and aromatic hydrocarbons, and more particularly, hydrogen, alkyls, aryls, alkylaryls or arylalkyls; and
R4 and R6 are independently selected from the group consisting of:
(a) H, alkyl, aryl, arylalkyl, alkylaryl, substituted derivatives thereof, and Ri;
(b) xe2x80x94C(O)OH and derivatives thereof, said derivatives selected from the group consisting of xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94C(O)[NHCHRi(q)C(O)]qNRYRZ; and
(c) xe2x80x94CHRiNH2 and derivatives thereof, said derivatives selected from the group consisting of xe2x80x94CHRiNHW, xe2x80x94CHRiNHC(O)OQ, xe2x80x94CHRiNHC(O)R, xe2x80x94CHRiNHC(O)NRYRZ, xe2x80x94CHRiNHC(O)[NHCHRi(q)C(O)]qOQ, xe2x80x94CHRiNHSO2R, and xe2x80x94CHRiNH[C(O)CHRi(r)NH]rW,
where q and r independently are integers from 1 to 10 inclusive;
where J is a carboxyl protecting group;
where G is an amino protecting group;
where Q is H, R or J;
where W is H, R or G;
where each Ri is independently selected from naturally or non-naturally occurring amino acid side chains;
where R is alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical; and
where each RY and RZ is independently H, alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical.
In yet another aspect of the invention, a compound of the general formula VI, and pharmaceutically acceptable salts thereof, is provided,
wherein
Z is a chemical species or Ri capable of binding at a primary specificity site of a protease;
Y is a chemical species reactive to a specific class of protease;
R30 is selected from the group consisting of hydrogen, alkyls, aryls, alkylaryls or arylalkyls;
R31 is selected from the group consisting of alkyl, aryl, arylalkyl, alkylaryl, substituted derivatives thereof, Ri, xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)R, xe2x80x94SO2R xe2x80x94[C(O)CHRi(r)NH]rW, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94C(O)[NHCHRi(q)C(O)]qNRYRZ; and
R32 is selected from the group consisting of alkyl, aryl, substituted aryl, arylalkyl, alkylaryl, Ri; xe2x80x94CHRiC(O)O, xe2x80x94C(O)OQ, xe2x80x94C(O)NRYRZ, xe2x80x94C(O)[NHCHRi(q)C(O)]qOQ, and xe2x80x94[C(O)CHRi(r)NH]rW;
where q and r independently are integers from 1 to 10 inclusive,
where Q is H, R or J, and J is a carboxyl protecting group,
where W is H, R or G, and G is an amino protecting group;
where each Ri is independently selected from naturally or non-naturally occurring amino acid side chains,
where R is alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical, and
where each RY and RZ is independently H, alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical.
The invention features a universal template for creating biologically active, peptidomimetic compounds, such as those of formulae I-VI, above. The chemical stability, side chain orientation, and polarity characteristics of the disclosed core template combine to provide numerous inhibitors of a variety of enzymes, including serine and cysteine proteases and matrix metalloproteases (MMPs) and aspartic proteases and others. The disclosed compounds are designed to have inhibitory activity, including selectivity and improved subsite interactions, by varying the pendant groups of the template compounds.
The disclosed inhibitors are useful in methods of treating a protease-related condition, such as a degenerative disease, wherein a pharmaceutically effective amount of a composition including one or more disclosed inhibitors is administered to a patient. The invention therefore further includes methods of reducing or inhibiting protease activity by contacting a protease with one of the compounds I-VI above. The protease may be from any protease source, including human and non-human mammals, and tissues, cells or membranes isolated therefrom which include the protease, or an isolated enzyme which has a binding affinity for the compounds of the invention. Binding affinity is defined as having a Ki on the order of at least micromolar (xcexcM) and preferably nanomolar (nM).
Other features and advantages of the invention will be apparent from the detailed description and examples below.

Sulfamide and bis-sulfamide amino acid derivatives as inhibitors of proteolytic enzymes

Abstract: (c) xe2x80x94CHRiNH2 and derivatives thereof, said derivatives selected from the group consisting of xe2x80x94CHRiNHW, xe2x80x94CHRiNHC(O)OQ, xe2x80x94CHRiNHC(O)R, xe2x80x94CHRiNHC(O)NRYRZ, xe2x80x94CHRiNHC(O)[NHCHRi(q)C(O)]qOQ, xe2x80x94CHRiNHSO2R, and xe2x80x94CHRiNH[C(O)CHRi(r)NH]rW, where q and r independently are integers from 1 to 10 inclusive; J is a carboxyl protecting group; G is an amino protecting group; Q is H, R or J; W is H, R or G; each Ri is independently selected from naturally or non-naturally occurring amino acid side chains; R is alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical; and each RY and RZ is independently H, alkyl, aryl, substituted aryl, alkylaryl, arylalkyl, or heterocyclic radical.


A touch panel has an upper substrate, a lower substrate, an elastic layer, plural conducting wires, and a gel layer. An upper conductive layer is formed at a lower surface of the upper substrate, a lower conductive layer that faces the upper conductive layer with a gap in between is formed at a top surface of the lower substrate, and the elastic layer is formed at a top surface of the lower conductive layer. The conductive wires are partially buried in the elastic layer and are disposed in a manner vertically oriented with a gap from the upper conductive layer. The gel layer is formed between the upper conductive layer and the elastic layer. With this construction, the touch panel is obtainable that suffers less wrong operation and allows reliable operation.

1. Field of the Invention
The present invention relates to touch panels to be used for operation of various types of electronic equipments and manufacturing method for the same.
2. Background Art
In recent years, optically transparent touch panels are installed on the front surface of display devices such as liquid crystal display in a variety of electronic equipment such as mobile phones and car navigation systems. Through touch panels, visual identification of characters and symbols displayed on the screen can be made. Also, through touch panels, selection of the characters and the symbols can be made. Furthermore, touch panels are operated by depressing them with a finger or a thing such as a dedicated pen. With this operation, each function of electronic equipment can be switched. Accordingly, touch panels that suffer less wrong operation and are easy to operate are required.
A description of such a conventional touch panel will be given referring to FIG. 4.
FIG. 4 is a cross-sectional view of a conventional touch panel. In FIG. 4, optically transparent upper substrate 101 is in the form of a film. Optically transparent lower substrate 102 is formed of glass and the like. Optically transparent upper conductive layer 103 made of indium tin oxide and the like is formed at the lower surface of upper substrate 101. Optically transparent lower conductive layer 104 made of indium tin oxide and the like is formed at a top surface of lower substrate 102.
In addition, optically transparent elastic layer 105 made of silicone rubber, urethane rubber and the like is formed at a space between upper conductive layer 103 and lower conductive layer 104. Two or more conductive wires 106 made of nickel, stainless steel or the like are disposed in a manner vertically oriented and buried inside elastic layer 105. Bottom ends of conductive wires 106 are in contact with lower conductive layer 104. A predetermined space is provided between top ends of conductive wires 106 and upper conductive layer 103.
Furthermore, a pair of upper electrodes (not shown) is formed at both ends of upper conductive layer 103. A pair of lower electrodes (not shown) is formed at both ends of lower conductive layer 104 in a direction orthogonal to the upper electrodes. Touch panel 100 is constructed in this way.
Electronic equipment (not shown) is constructed by disposing touch panel 100 constructed in this way on the front surface of a liquid crystal display device (not shown), for example. At the same time, the pair of upper electrodes and the pair of lower electrodes are connected to an electronic circuit (not shown) of the electronic equipment, respectively.
In the above configuration, a top surface of upper substrate 101 is depressed with a finger or a thing such as pen in the direction of arrow X while visually confirming what is displayed on the liquid crystal display device, for example, on a back of touch panel 100. With this operation, upper substrate 101 and elastic layer 105 are bent, and that part of upper conductive layer 103 which is depressed and the top ends of conductive wires 106 come into contact together. When upper substrate 101 is further depressed, conductive wires 106 are bent. At this result, upper conductive layer 103 and lower conductive layer 104 are electrically connected via conductive wires 106.
And, an electrical power supplied from the electronic circuit is sequentially fed to the upper electrodes and the lower electrodes. The electronic circuit detects a location of depression based on a voltage ratio detected by the upper electrodes and a voltage ratio detected by the lower electrodes. With this, switching of various functions of the electronic equipment is performed.
Also, when depressing force on upper substrate 101 is released, upper substrate 101 returns to an original form by elastic restoring forces of upper substrate 101 and elastic layer 105. With this, upper conductive layer 103 is detached from the top ends of conductive wires 106.
Such a conventional touch panel 100 as above described is disclosed in Unexamined Japanese Patent Publication No. 1984-188726, for example.

Touch panel and manufacturing method for the same

Matsushita Electric Industrial Co., Ltd.


An alphanumeric data entry system for chordic keyboards permits the entry of vowels with the thumb and digits of the left hand and the entry of consonants with the thumb and digits of the right hand in combination with vowel chords from the left hand. Only the thumb, index, middle and ring digits of the left and right hands, respectively, are necessary for manipulation of 2 four-key sets. The keyboard can either be a conventional side-by-side keyboard or, alternatively, an 8 dot braille keyboard in which the two sets are arranged in two rows in a substantially parallel relationship to each other. The number mode is initiated by depressing all four digits of the right hand and then entering numbers beginning with the ring digit of the left hand as the lowest integer and proceeding in a reverse binary fashion from left to right with the numbers 0 through 9 entered by the left hand. The system can switch functions by depressing the index, middle and ring digits of the right hand and then entering the desired function code with the digits of the left hand. Some of the other functions possible are common math operators, containment chords, movement chords, operating chords, monetary and graphic chords, foreign language chords, etc. Because of the left to right nature of the data entry, the system is relatively easy to learn and fast to use. It is especially suited for handicapped and sight disabled individuals as a substitute for braille.

This application is a re-filed application Ser. No. 07/829,987, filed Feb. 3, 1992 which was abandoned after being rejected. Two corrections were made in the code part of the re-filed application and amended to better help those skilled in the art to understand and use the invention.
1. Field of the Invention
This invention relates to an eight bit binary computer data code used as an eight dot braille arrangement and a system and method for entering or producing a space, letters, numbers, data, symbols, control, etc. on an eight key or sensor binary chordic keyboard manipulated by four digits of a first group by a preferred left hand and by four digits of a second group by a preferred right hand respectively.
2. Description of Related Art
There are a number of well-known, prior art keyboards and systems used for inputting alphanumeric data into typewriters, braille writers, word processors, computers, laptops, PDAs and the like. Unfortunately, most modem systems are inherently slow, difficult to learn, not organized in a logical fashion and/or cumbersome for the general population, including the handicapped and sight disabled.
The best known system is the QWERTY keyboard layout which derives its name from the first six letters of the top row of the alphabet keys or sensors. The QWERTY system has been around for many years and was originally implemented in order to slow down typists so that manual typewriter keys would not jam. A good explanation of the history of the QWERTY keyboard is set forth in an article entitled "TYPING WITH A TWO-HAND CHORD KEYBOARD: WILL THE QWERTY BECOME OBSOLETE?" by Daniel Gopher and David Raij, IEEE Transactions on Systems, Man, and Cybernetics, Volume 18, No. 4, July-August 1988, pages 601-609.
In response to the relatively slow and cumbersome QWERTY system, some new word processors and computers have moved to a Dvorak layout, although very few. One of the characteristics of the Dvorak keyboard is that the vowels a, o, e, u and i form the first five keys of the second alphabetic row of the keyboard. The United States Department of the Navy tested the Dvorak design and found up to a twenty percent increase in typing speeds. While improved efficiencies are possible and proven with the Dvorak keyboard, it does have some drawbacks, the major one of which is that the keys are not laid out in an ergonomic fashion to follow the natural positions of the hands. Moreover, because there are more keys than the operator has digits, it is necessary for the operator to move his or her hands frequently and fingers up/down or left/right to find and depress the appropriate key or keys. This tends to reduce the overall speed of the typist.
In order to increase speed, the chordic keyboard was invented. There are a number of chordic keyboards on the market, some of which have sets of linear rows, some have curved rows, some have vertical rows or some have horizontal rows. The common denominator is that it has fewer keys than the common QWERTY keyboard or the Dvorak keyboard, and that chords are employed, i.e. combinations of keys or sensors, to enter or produce specific letters, numbers, symbols or functions. A good example of a modern one handed chordic keyboard for use by either hand is the BAT, U.S. Pat. No. 5,642,108 to Gopher et al., sold by Infogrip, Inc., 812 North Boulevard, Baton Rouge, La. 70802. The BAT keyboard comprises two sets of keys, seven for the left hand and seven for the right. Various combinations of keys, from either hand, form binary chords which enter letters, numbers, punctuation, etc., into a computer for processing. Other keyboards are available for attachment to personal computers and the like in order to provide additional functions or to increase the speed of data entry.
The patent literature describes a number of efforts to improve the speed and efficiency of data entry on keyboards. For example, U.S. Pat. No. 4,680,572 to Meguire, et al. entitled CHORD ENTRY KEYING OF DATA FIELDS describes a keyboard arrangement, which in one embodiment, has eleven keys arranged in two sets of five, for either hand, and a common enter key located between the two hands. The system permits the entry of data in a chord-like fashion provided that the common function key is depressed during a predetermined time frame prior to or after the depression of the last data key. Efforts to arrange keyboard keys in a vertical fashion is also described in certain prior art literature. U.S. Pat. No. 3,428,747 to Alferieff entitled MAN TO MACHINE COMMUNICATION KEYBOARD DEVICE discloses a keyboard arrangement in which the four digits and thumb of the right and left hands, respectively, are positioned adjacent to two sets of keyboards, each having five keys, that are vertical and substantially adjacent to each other. The keyboard system permits the entry of data into a computer, radio system, interface or the like.
Other keyboard apparatuses and systems of possible relevance include the following U.S. Patents: U.S. Pat. Nos. 329,675; 477,062; 506,718; 578,785; 753,318; 1,293,023; 1,409,386; 1,487,115; 1,733,605; 1,771,953; 1,932,914; 1,936,089; 1,998,063; 2,012,924; 2,028,516; 2,031,017; 2,040,248; 2,150,364; 2,187,592; 2,189,023; 2,190,752; 2,192,594; 2,200,807; 2,282,102; 2,312,138; 2,390,414; 2,428,605; 2,520,142; 2,532,228; 2,581,665; 2,616,198; 2,634,052; 2,641,769; 2,718,633; 2,823,468; 2,850,812; 2,972,140; 3,021,611; 3,022,878; 3,102,254; 3,166,856; 3,184;554; 3,197,889; 3,225,883; 3,234,664; 3,241,115; 3,277,587; 3,369,643; 3,375,497; 3,381,276; 3,428;747; 3,466,647; 3,507,376; 3,526,892; 3,582,554; 3,633,724; 3,675,513; 3,772,597; 3,781,802; 3,798,599; 3,818,448; 3,831,147; 3,831,296; 3,833,765; 3,879,722; 3,929,216; 3,945,482; 3,967,273; 3,970,185; 3,980,823; 3,982,236; 4,042,777; 4,067,431; 4,074,444; 4,132,976; 4,159,471; 4,185,282; 4,333,097; 4,350,055; 4,360,892; 4,467,321; 4,494,109; 4,516,939; 4,655,621; 4,680,572; 4,791,408; 4,804,279; 5,087,910; 5,217,311; 5,281,966; 5,361,083; 5,459,458; 5,486,058; 5,459,458; 5,515,305; 5,642,108, and an IBM Technical Disclosure Bulletin Vol. 18 No. 12 dated May 1976 entitled; DIGITAL X" TYPEWRITER KEYBOARD which discloses two sets of five ergonomically arranged keys for each hand, where each key is operated by one of the ten digits on the left and right hands. The two thumb keys each produce a space. The eight finger keys use a three position switch (down, away and toward) or a five position switch as home row keys. Downward activation produces home row data, away activation produces top alphabetic row data and toward activation produces bottom row data found on the QWERTY keyboard.
While the foregoing all appear to represent improvements in the art of keyboard systems, they nevertheless tend to be difficult to learn and difficult to use, especially by individuals who are sight or hearing impaired. Of all the patents and technologies researched, none use or claim an eight bit binary computer code as a data entry means. The most relevant technology to this patent application is the eight bit EBCDIC computer code (Extended Binary Coded Decimal Interchange Code), the eight bit ASCII and extended ASCII computer code (American Standard Code for Information Interchange) and the eight dot computer braille code, which is top dot configured for tactile reading.

8-bit binary code for use as an 8-dot braille arrangement and data entry system and method for 8-key chordic binary keyboards


A channel state information feedback method includes: generating, by a transmit-end device, codebook indication information of K transport layers, where K is an integer greater than or equal to 1; and for each of at least one of the K transport layers, the codebook indication information includes narrowband superposition coefficients of N sub-bands of the layer, where a quantity of the narrowband superposition coefficients of the N sub-bands is less than R(L−1)*N, N is an integer greater than or equal to 2, R is a quantity of polarization directions and R is an integer greater than or equal to 1, and L is a quantity of pieces of beam information used by the K transport layers and L is an integer greater than or equal to 2; and sending, by the transmit-end device, the codebook indication information.

Massive multiple-input multiple-output (Massive MIMO) is one of 5G key technologies widely accepted in the industry. Spectral efficiency is significantly improved by using a large-scale antenna.
Accuracy of channel state information (CSI) obtained by a base station determines performance of Massive MIMO to a great extent. In a time division duplex (TDD) system or a frequency division duplex (FDD) system in which channel reciprocity cannot be well satisfied, CSI is usually quantized by using a codebook. Therefore, design of the codebook is a key problem of Massive MIMO and a problem required to be resolved in this application.
In a long term evolution (LTE) system, a beam combination technology is usually as follows: A plurality of code words are selected from a predefined codebook, and a weighted sum of the plurality of code words is used as a precoding vector. Generally, one code word corresponds to one beam direction. To be specific, a plurality of optimal code words are selected from a plurality of candidate code words and each weighting coefficient (e.g., superposition coefficients including a broadband superposition coefficient and a narrowband superposition coefficient) of each of the plurality of code words is reported as CSI information in a form of precoding matrix indicators (PMI). New radio (NR) Massive MIMO has a higher requirement on channel state information feedback, and the foregoing mechanism cannot satisfy a requirement of NR on reducing signaling overheads.

Channel state information feedback and receiving method, transmit-end device, and receive-end device