In the information transfer method the information (I) is collected in the memory (55) of a pointing pen (51). A selected point on the display (43) is pressed with the tip of the pen (51), whereby a frequency change of the resonant circuit (42/52) indicates the contact, and a change in the resonance signal's strength in the receiving circuit determines the position of the pen. Then the oscillation of a second resonant circuit (43/53) is modulated with the information (I) in the memory. The received and demodulated (47) and possibly otherwise processed (48) signal is then presented on the display (43). With this method the user can transfer scanned information directly to the display of a pen computer or a mobile phone for further processing.

1. Field of the Invention
The invention relates to a method using a pointing device for transferring information e.g. at a microcomputer having a display, or at the user interface of a mobile phone, and to a device combination realizing the method.
2. Description of the Prior Art
In the development of small size portable data processing and communications equipment we are repeatedly faced with the problem how to realize flexible, versatile and user friendly data entering. For instance present day notebook microcomputers and mobile phones have comparatively small displays, and the keyboard sizes are very limited. Thus it will be a slow and cumbersome process to enter data in these devices, so that in practice only simple and short messages can be transferred through the user interface.
Different solutions to the above problem have been found and also put into use. Such solutions are presented e.g. by the user interfaces based on a touch screen. Different types of touch screens were discussed in the Finnish computer paper PROSESSORI, n:o 1/94, p. 31 to 33 "Kosketusnaytolla helpommin" (`Easier with a touch screen`). The article mentions analog methods based on capacitive, resistive, and force measurement techniques. Of the matrix methods the article mentions infrared, acoustic and possibly also resistive contact detection. This article, however, discusses touch screen applications primarily for larger monitors based on the cathode ray tube technology. FIG. 1 is a figure presented in said article, which shows how in principle a certain point P on the display can be selected with the finger H, and how changes in the capacitance are detected in the horizontal and vertical directions by the display's detection circuits S, which then produce a signal to be processed by the electronics of the display device.
For portable applications we know e.g. so called pen computers or PDA devices (Personal Digital Assistant) are on the market in the form of devices such as Apple Newton MessagePad, Sharp ExpertPad, or Casio XL-7000. These are microcomputers which easily fit in the hand and have no conventional keyboards, but data is entered by writing normal handwriting with a special pen on the touch screen of the device. Alternatively a keyboard picture corresponding to a standard keyboard may be activated on the device display, whereby the key positions are pressed with the tip of the pen. Then the display is realized by liquid crystal or LCD techniques, whereby the input section comprises a transparent digitizing layer over the display layer. The digitizing layer comprises for instance a plurality of digitizing points which are located in a matrix, and which as a result of a contact generate a physical response corresponding to the point of contact. The response is transformed into an electrical signal and in logic circuits it is interpreted into digital information. With the LCD technology the identification of contact points can be realized by different known methods, which for instance are based on the absorption of acoustic surface waves in the contact point, on infrared transmission and reception, on a change in the capacitance and a resulting change in frequency, on a change in pressure caused by the contact which is detected by a strain gauge or a piezoelectric transducer, on mechanical switch designs, and so on. One possibility is also to use the change of the magnetic field or the electromagnetic resonance to detect the point of contact.
FIGS. 2 and 3 illustrate a pen computer application presented in our patent application FI-941629 (the application's FIGS. 1 and 3b, respectively). FIG. 3 shows a mobile phone 31 and a display comprising layers 32, 33 on top of one another. The display also extends under the virtual keys 35. A permanent keyboard is located at 36. In this invention the pointing with the pen at a desired key location is aided by a sheet 34 provided with holes. In FIG. 2 it is shown in section, and its surface 11 has recesses 12, into which a pen is easily directed. A push with the pen 14 activates the transducer 13. In this case the transducers could be realized by keys in different technologies, such as mechanical miniature keys, membrane keys, or digitizing points on a digitizing pad or touch screen.
For instance an electromagnetic resonance method could be used when the above transducer is realized, see-figures 4 and 5. Then the pointing device, the pen 51, receives its operating power through the electromagnetic radiation created by the varying inductive field of the sensor table 41 and stores the energy in its own coupling circuit 52. The surface of the sensor table 41 is e.g. the glass sheet of an LCD display, and the electromagnetic radiation is created by resonant circuits under the display sheet 41, which are supplied by any suitable signal processing circuit 45. The resonant circuit 42 comprises a main capacitor and a coil. The pen 51 includes a resonant circuit 52 comprising a coil and a capacitor, whereby this circuit receives, stores and discharges a signal at the same frequency which it received from the sensor plate. When the display surface 41 is touched with the pen 51, the capacitance of the pen's electrical circuit will change, causing a mutual chance both in the received and in the transmitted signal. This causes a phase shift in the resonance frequency. The position of the pen 51 on the screen 41 is determined with the aid of the signal strength.
The above presented pen 51 can also include a lateral switch, which can be used to start a predetermined function in the receiving device 41. The state of the lateral switch can be detected e.g. by a change in the phase shift and/or in the frequency.
In order to automate data acquisition we know various equipment, of which we could mention scanners, for instance hand-held scanners, and bar code readers. A typical scanner assembly comprises the actual reader device, or a device which reads pictures and/or text and encodes them into an electrical signal, and further a cable and an interface card, through which the signal containing the scanned information is transformed into a form which can be processed e.g. by a computer. Alternatively the cable could be connected to a microcomputer's serial or parallel port through which the scanned information is read into the computer. In many cases the signal generated by the scanner is processed as such, in a bit map form. On the other hand the signal can be processed by a suitable program which detects the pixel position information generated by the scanner and combines these pixels in a suitable way to generate either simple lines or preferably e.g. characters. Character recognition programs have been developed into quite versatile programs, and now there are programs on the market which automatically can recognize different fonts and which can be "taught" to recognize different handwritings.
Bar code readers are quite widely used, for instance at shop check-outs where product information and prices are read and entered from the scanner through a cable/wire interface to the check-out computer. In the industrial production and storage field there are also different identification tasks where bar code readers are used. One typical application of a hand-held bar code reader is stocktaking, whereby a person performing the stocktaking with the aid of a reader identifies the contents of bar code stick-on labels fastened on the products and/or product packages. The collected information is stored in the memory of the bar code reader, and when the stocktaking is ended the data stored in the reader is discharged through a suitable cable interface to a microcomputer with a storage bookkeeping program, into which the collected data is entered. In addition to the mechanical connections the user must usually perform operations related to a microcomputer program, for instance enter instructions through a separate keyboard so that the collected data can be stored in the correct memory position determined by the program.

System for transferring information between a pointer and a display interface


Disclosed are systems and methods to encrypt an image for secure image transmission and parallel decryption using resources from a networked environment. Upon reception of encrypted data from the mobile user, the data can be decrypted by transforming the data, decrypting the transformed data, and inversing the transformation. The decrypted data can be sent for storage in a cloud storage.

Cloud based services are being delivered by more than 87,000 companies around the world. Over 300 million pictures are being uploaded to Facebook every day and over 300 petabytes of data are being stored in their data warehouses. The applications of Cloud computing can be seen in broad range of fields, such as, for example, social networking, healthcare, defense, NASA, etc. Increased use of mobile devices has encouraged developers to explore ways of making their applications fast and reliable.

Systems and methods for secure file transmission and cloud storage

Board of Regents, The University of Texas System


A machine is controlled by a system which has a pair of programmable controllers connected in tandem. One controller operates in the active mode governing the operation of the machine, while the other controller is in a backup mode able to assume control of the machine should the active controller fail. Each programmable controller has a backup module through which the two controllers are connected. In order to determine which controller is to be active upon power up, each backup module has an input means for receiving a first active mode request signal from another programmable controller. A means is provided to produce a tie breaker signal at one backup module which indicates that its programmable controller is to operate in the active mode when both programmable controllers simultaneously desire to operate in the active mode. A mode indicator in the backup module designates the active mode when the input means does not receive the first active mode request signal, or when the input means is receiving the first active mode request signal and the tie breaker signal is being produced at that backup module. Otherwise, the mode indicator designates that the programmable controller is to operate in the backup mode. An output means transmits a second active mode request signal to the other programmable controller when the mode indicator designates the active mode.

Programmable controllers are a common type of industrial computer for operating a wide variety of manufacturing equipment, such as assembly lines and machine tools, in accordance with a stored program. The program comprises a series of process control instructions which are read out and executed to examine the state of selected sensing devices on the controlled equipment, and to energize or deenergize selected operating devices contingent upon the state of one or more of the examined sensing devices.
The state of many sensing and operating devices can be represented by a single bit of data which is manipulated by the control program instructions. Other devices, such as position sensors, provide multiple bits of data representing a condition of the equipment being controlled. For these latter devices, instructions are provided to manipulate bytes and words of data representing the state of the sensing and operating devices. Additional program instructions perform arithmetic operations, timing and counting functions, and complex statistical reporting operations. Such instructions have become quite standardized in the industry and are directly associated with the elements of a ladder logic diagram which is easily understood by process control engineers. Program panels such as those described in U.S. Pat. Nos. 3,798,612; 3,813,649 and 4,070,702 have been developed to assist the user in developing and editing ladder logic control programs comprised of such programmable controller instructions.
There are many applications of programmable controllers in which "down time" resulting from malfunction of the controller must be minimized. For example, the cost of shutting down an automobile assembly line is enormous and extraordinary measures are taken to insure that quality components are employed in the control systems. In other manufacturing systems, such as chemical processing, failure of the control system can result in the loss of life or a large quantity of the product being produced. Despite these efforts it is statistically certain that malfunctions or failures will occur in the electrical and mechanical components.
An inherent characteristic of programmable controllers is the concentration of decision making functions of the system in certain subsystems and components. For example, a malfunction of the memory which stores the control program or a malfunction of the processor that reads and executes the control program is catastrophic in the sense that the entire system being controlled is affected. Malfunction detection techniques are employed to sense and quickly diagnose such problems and components are mounted on circuit boards for easy replacement. However even when a malfunction is quickly discovered, diagnosed and fixed, the resetting and power-up of the manufacturing system consumes considerable time.
The use of redundant components or modules is a common practice in a number of fields. In the aerospace field, for example, there is multiple redundancy of the entire flight control system and in the data processing field it is common to provide redundant processors or input/output controllers. In the industrial control field redundancy of the entire system is economically impractical. As a result one approach, described in U.S. Pat. No. 4,521,871, doubles selected hardware components which perform the program storage and execution functions. One set of the components is designated as the primary unit and the other as the backup unit which takes control of the system only when the primary unit fails. In order for a transition from one set of components to the other to occur smoothly, both sets must have the same information regarding the status of the manufacturing process and equipment. In addition, it has been found desirable that each set of components have knowledge of the status of the other set.

Programmable controller with backup capability


A vibration reducing interface which uses interconnected layers of three or more concentrically arranged isolators to reduce vibrations in tools, vehicles, machines, weapons and anything else which uses pumps, compressors, engines, motors, spinning elements, out of balance loads or inconsistent, variable loading. The vibration reducing interface provides for tiering arranged isolators for reducing varying degrees and directions of vibration. The vibration reducing interface reduces vibration and its related negative affects including injury, damage and reduced control in relation to use of tools, vehicles, machines, weapons and other equipment.

Vibration can be a nuisance or at times cause catastrophic consequences including personal injury and damage to property. Vibration occurs in many different forms, and regularly arises out of use of tools, equipment, and machinery common in everyday application. Vibration control and attenuation is important in preventing both injury and property damage. It is also important in preventing damage to structures either housing equipment or machinery, or upon which the equipment or machinery is being used.
Vibration control and attenuation can be accomplished in many different ways. This includes passive control devices, active control devices, and hybrid devices. It is not uncommon for tools, equipment or machinery causing vibrations to utilize dampeners that in many instances are solid structures having a durometer appropriate for absorbing vibration. For example, machinery such as aircraft and motor vehicles have motor mounts connecting an aircraft or motor vehicle motor to the aircraft or motor vehicle structure where the motor mounts contain structures including solid blocks of vibration absorbing material, such as rubber, that will attenuate vibration resulting from the motor operation. These types of vibration control devices are limited in their ability to entirely reduce vibration due to varying degrees of vibrations that occur as a result of variations caused by the oscillations of a tool, equipment and machinery. Further, it is well known that in many applications tools, equipment and machinery have continuing vibration conditions that are not adequately addressed with current dampeners. In addition, hand held tools and firearms exhibit vibrations that are not adequately addressed with current applications, including solid dampening systems. Therefore, it would be an advantage to provide a vibration dampening system that counters or attenuates vibrations in a manner that accounts for variations in the direction and degree of oscillations but does not add significant cost or weight and burden to existing tool, equipment or machinery systems.
Further, vibrations are known to cause injury, especially in applications where individuals control a tool, equipment or machinery that is vibrating during its operation. Injuries include vibration white finger (VWF), also known as hand-arm vibration syndrome (HAVS) or "dead-finger." This is an injury triggered by continuous use of vibrating machinery. HAVS is a widespread recognized industrial disease affecting tens of thousands of workers. It is a disorder that affects the blood vessels, nerves, muscles and joints of the hand, wrist and arm. Good practice in industrial health and safety management requires that worker vibration exposure is assessed in terms of acceleration, amplitude and duration. For example, using a tool that vibrates slightly for a long time can be as damaging as using a heavily vibrating tool for a short time. Therefore, it is important to develop and implement systems that dampen and attenuate vibration, that addresses heavy vibration and lighter vibration that can occur for longer periods of time.
In physics, dampening is an effect that reduces the amplitude of oscillations in an oscillatory system. Dampening can be achieved in an overdamp, critically damped, under damped and undamped result. The difficulty in addressing dampening of a vibrating system is accounting for variations in oscillations (vibrations) that in many instances change based on the operation of tool, equipment or machinery and associated motor/engine including its associated vibrating systems. Vibration dampening can be resolved through phase shifting occurring when a vibrating system is countered with a system that changes the oscillations in a manner that the oscillations are cancelled through phase differentiation. Therefore, it is desirable to develop and provide an economical system for dampening vibrations that is adaptable to wide application and will provide a safe and stable system for cancelling vibration in a wide range of vibrating systems.
Vibration control is important not only to reduce injury to operators and passengers in the case of vehicles/aircraft applications, but is also important to reduce damage to equipment and machinery, including the surrounding structure of the vibrating source and associated equipment such as control equipment in an aircraft. Further, vibration control is necessary to reduce damage to cargo. In addition, vibration control is important for allowing control of the vibrating system. For example, control of hand held tool or equipment could be greatly increased with adequate vibration control. Without it, hand held equipment can become cumbersome and virtually uncontrollable for its operators. This can relate to simple equipment such as a hand held hammer drill or floor cleaning or polishing equipment that if uncontrolled will be difficult to move due to its inherent vibrations.
In addition, it is important that the points of vibration control not create a weak link in a tool, equipment or machinery. Therefore, it is necessary to have a robust structure, having vibration dampening capability that adequately addresses the problems created by vibration but does not create structural weakness problems. Lastly, vibration may not be necessarily linear but frequently is multi-directional and results in permeation of vibration throughout a system or structure. Therefore, linear shock absorbers and other systems that are adept at reducing vibration in a linear direction are inadequate for multi-directional applications. Therefore, it would be an additional benefit to provide a system capable of vibration dampening in a multi-directional application.


A computer aided design system accurately determines the location, shape, and dimensions of a transparency that provides a field of view meeting a clear view area specified by a two dimensional polar vision plot. The computer aided design system projects points on the two dimensional polar vision plot onto a three dimensional surface of the transparency taking into account the observer's head position and the refraction of light caused by the transparency.

This invention facilitates the task of designing the flight deck windows for a new aircraft/cab design. The external field of view created by an airliner's flight deck windows must satisfy many regulatory and design requirements. The total amount of transparent material is generally limited because the window material is very heavy. In addition, the size of individual windows is limited due to the expense and technical challenges of manufacturing large glass panels of suitable optical quality and the increase in aircraft weight and complexity associated with transferring loads around large window cutouts.
The external visual field can be evaluated using "polar projections," which are angle-angle plots of the limits of the solid angle that the pilots can see out of the windows. The "polar projections" are plots of the limits of the clear view area expressed in terms of coordinates representing angles left/right (azimuth) and angles up/down (altitude), measured from a line straight forward from the pilot's eyes.
During the design process, proposed window designs can be evaluated by comparing the polar projection of the proposal against the polar projection of previous designs and against the regulatory requirements, expressed in angle/angle coordinates. Calculating and plotting the polar projection for a window design is not a straight-forward geometric construction due to the following factors. Both left and right eyes of the pilot are used. The final graph is a union of the vision from both eyes. The pilot's head is rotated as the window area is scanned; therefore the origin point for each "sight ray" is continuously changing. The sight rays also are refracted as they pass through the transparency material.
When the requirements for the external visual field for a new window design are expressed as an angle-angle plot, an initial design point can be found by "reverse projection," that is, to project the limits defined on the angle-angle plot back onto the three dimensional surface of the aircraft being designed. Due to the complicating factors mentioned above, this is a very difficult task. Previous to this invention there were two methods that could be used to accomplish a reverse projection, both entirely unsatisfactory.
The first method was trial and error: first, take an educated guess as to the shape of window edges that would produce a given polar projection, then create trial window geometry on the aircraft surface, next do a polar projection using all the rules set out above, and finally evaluate the result and iterate the process, adjusting the three dimensional geometry as necessary. This method is very laborious, time consuming and, due to the number of iterations required, inefficient and ineffective for optimizing the window shapes.
The second method was to create 3D surfaces radiating from an eye point to represent the desired angle-angle criteria. This set of surfaces would be intersected with the aircraft surface to create curves defining the edges of windows. Unfortunately, a simple geometric construction cannot account for the moving eye points and light refraction through the transparencies. Therefore this method is inaccurate, and the inaccuracy is more acute for windows that are not planar, yet this is a method previously used at Boeing and elsewhere to create window geometry during initial flight deck design.

Method and apparatus for transferring an angle-angle vision graph to a three dimensional surface


Provided herein is a reusable nano-imaging probe useful in surface enhanced Raman spectroscopic (SERS) applications demonstrating nanometer scale resolution. The nano-imaging probe generally comprises a fiber optic imaging bundle of fiber optic elements each having a tapered etched end and a non-tapered non-etched end. The tapered etched ends further comprise a SERS-active metal substrate deposited thereon effective to create a uniform SERS enhancement for an analyte or other substance of interest. Also provided is a SERS nanoimager for dynamic chemical imaging using the nano-imaging probe and methods of imaging and Raman spectral analysis and identification using the nano-imaging probe.

1. Field of the Invention
This invention relates generally to the fields of Raman spectroscopy and imaging. Specifically, the present invention relates to a nano-imaging probe useful in surface enhanced Raman spectroscopic applications.
2. Description of the Related Art
Recent technological advances in the controlled fabrication and manipulation of nanoscale systems and devices has generated increased interest in various nano-structures, both man-made, e.g., carbon nanotubes, (1-2) and naturally occurring, that is, biological cells or subcellular compartments (3). Synthesizing, characterizing and understanding such structures and their function, therefore, is extremely important to many fields ranging from drug delivery in the design of effective time-release materials (4-5) to space exploration in the fabrication of light-weight, rugged materials (6). In order to better characterize and further develop these nano-structures, the ability to visualize objects on the nanometer to hundreds of nanometer's scale is essential.
One area in which high-resolution imaging of individual chemical species will have a great impact is in biochemical studies. For example, a novel tool for characterizing dynamic intracellular and extracellular interactions on the nanoscale could offer insight into metabolic pathways, ion exchange mechanisms, and other essential cellular processes. In medical research, a tool for measuring and imaging localized chemical changes at the cellular and sub-cellular levels could allow for pre-symptomatic disease detection as well as potentially allow for the development of specific treatments for individuals (7-10).
Chemical imaging using optical spectroscopies has long been used for the identification and the determination of the spatial distribution of species within a sample. Using different optical spectroscopic techniques, i.e., fluorescence (11-13), Raman (14-18) and others (19-20), it is possible to obtain both qualitative, as well as quantitative, information about a sample. Fluorescence imaging is commonly used for the monitoring of trace amounts of a known analyte and Raman imaging is typically used for species identification. Recently, surface enhanced Raman spectroscopy (SERS) also has been employed for chemical imaging, providing both the qualitative identification of Raman imaging with the sensitivity necessary for trace analyses (21). However, the creation of uniform roughened metal surfaces, necessary for SERS, and thus uniform surface enhancement, is difficult to control from location-to-location which dramatically limits the use of SERS as an imaging technique (22-25). Additionally, the far-field imaging methodologies employed in conventional chemical imaging analyses ultimately limits the spatial resolution of such analyses to the diffraction limit of light, effectively preventing the imaging of nanometer scale objects.
To overcome this diffraction limited spatial resolution and to obtain chemical images with resolution on the nanometer scale, near-field chemical imaging techniques were developed, including near-field scanning optical microscopy (NSOM) (26-29). Coupling NSOM with the sensitivity of fluorescence spectroscopy, near-field chemical images of samples have been obtained for many different applications, including medical diagnostics (30), materials science studies (27,31) computer science (32) and chemical and biological research (33). More recently, the nanometer scale fiber optic tip used for scanning in most NSOM analyses was scanned over a SERS active surface to record SERS images with approximately 100 nm spatial resolution. This has resulted in the ability to visualize individual molecules, such as a single strand of DNA labeled with brilliant cresyl blue (BCB) (34-35).
While NSOM in conjunction with other spectroscopic techniques can be used to produce high-resolution chemical images below the diffraction limit of light, dynamic real-time sample imaging has not yet been feasible, as NSOM requires hours of scanning the probe tip across the surface (36). In addition, if a particular area of interest is found, it is often difficult to return to this exact location after the scan has been completed (36). Due to these limitations, NSOM is not particularly suited to studying dynamic chemical events.
Accordingly, a need is recognized in the art for improved surface enhanced Raman spectroscopic imagers useful for real time, reproducible imaging in a non-scanning format to overcome the challenge of SERS substrate reproducibility in SERS imaging and the dynamic limitation of NSOM. More specifically, the prior art is deficient in a SERS nanoimaging probe having a uniform, repeatable and regular nano-structured surface effective for nanoscale resolution and methods of making the same. The present invention fulfills this longstanding need and desire in the art.

Surface enhanced Raman spectroscopic nano-imaging probe and uses therefor

University of Maryland at Baltimore County


Techniques for determining a disk failure indicator for predicting disk failures are described herein. According to one embodiment, diagnostic parameters are received which are collected from a set of known working disks and a set of known failed disks of a storage system. For each of the diagnostic parameters, a first quantile distribution representation is generated for the set of known working disks, and a second quantile distribution representation is generated for the set of known failed disks. The first quantile distribution representation and the second quantile distribution representation of each of the diagnostic parameters are then compared to select one or more of the diagnostic parameters as one or more disk failure indicators for predicting future disk failures.

Data storage utilization is continually increasing, causing the proliferation of storage systems in data centers. Monitoring and managing these systems require increasing amounts of human resources. Information technology (IT) organizations often operate reactively, taking action only when systems reach capacity or fail, at which point performance degradation or failure has already occurred. Hard disk failures fall into one of two basic classes: predictable failures and unpredictable failures. Predictable failures result from slow processes such as mechanical wear and gradual degradation of storage surfaces. Monitoring can determine when such failures are becoming more likely. Unpredictable failures happen suddenly and without warning. They range from electronic components becoming defective to a sudden mechanical failure (perhaps due to improper handling).
Self-Monitoring, Analysis and Reporting Technology (S.M.A.R.T., or simply written as SMART) is a monitoring system for computer hard disk drives to detect and report on various indicators of reliability, in the hope of anticipating failures. When a failure is anticipated by S.M.A.R.T., the user may choose to replace the drive to avoid unexpected outage and data loss. The manufacturer may be able to use the S.M.A.R.T. data to discover where faults lie and prevent them from recurring in future drive designs. However, not all of the S.M.A.R.T. attributes can consistently provide reliable indications of possible disk failures. The S.M.A.R.T. attributes tend to vary and they may have different interpretation from one hard disk vendor or configuration to another. There has been a lack of reliable mechanism to determine which of the S.M.A.R.T. attributes to be the best disk failure indicator, as well as the efficient ways to predict single disk failure or multi-disk failures in a redundant array independent disks (RAID) environment.

System and method for determining disk failure indicator to predict future disk failures


A glass run mounted along an inner part of a door frame of a vehicle door to guide a window glass which moves up and down within the door frame. A main body portion of the glass run is provided with an exterior side wall, an interior side wall and a bottom wall, thereby formed into a shape having a substantially U-shaped cross section. An exterior seal lip and an interior seal lip are provided so as to extend into an inside of the substantially U-shaped cross section from distal portions of the exterior side wall and the interior side wall, respectively. The bottom wall has a bottom wall damping lip which is formed so as to be inclined inwardly from one of side end portions of an inner surface of the bottom wall. A space which is provided between an outer surface of the bottom wall portion and a door frame. A cushion material is provided in the space.

1. Field of the Invention
The present invention relates to a glass run for automobile which is mounted along an inner part of a door frame of a vehicle door to guide a window glass which moves up and down within the door frame.
2. Related Art
As shown in FIG. 3, a glass run 110 for an automobile is mounted along an inner part of a door frame 2 of a vehicle door to guide a window glass 5 which moves up and down within the door frame 2. A conventional mounting structure of the glass run is shown in FIGS. 4 and 5.
FIG. 4 is a sectional view taken along the line I-I in FIG. 3.
Conventionally, the glass run 110 is, as shown in FIG. 4, mounted in a channel 3 of the door frame 2 to guide the window glass 5 which moves up and down within the door frame 2 and to form a seal between the window glass 5 and the door frame 2. Furthermore, in the glass run 110, a top side portion, a front vertical side portion and a rear vertical side portion, which correspond to sections of the door frame 2 of the door 1, respectively, and which are provided with extruded portions 111 formed by extrusion molding, are connected together by corner portions 112 which are molded by injection molding in shape to connect the extruded portions so as to follow the shape of the door frame 2.
In addition, a seal between the door 1 and a vehicle body is made by a door weather strip 108 which is mounted along an outer periphery of the door frame 2 of the door 1 and/or an opening weather strip 109 which is mounted on a flange at a corresponding opening in the vehicle body.
The glass run 110 is, as shown in FIG. 4, provided with an exterior side wall 120, an interior side wall 130 and a bottom wall 140 which form a substantially U-shaped cross section. An exterior seal lip 126 is provided on the exterior side wall 120 so as to extend from the vicinity of a distal portion thereof into an inside of the substantially U-shaped cross section. In addition, an interior seal lip 136 is provided on the interior side wall 130 so as to extend from the vicinity of a distal portion thereof into an inside of the substantially U-shaped cross section. Furthermore, an external cover lip 124 is provided on the exterior side wall 120 so as to extend from the vicinity of a distal portion of an external outer surface thereof toward the bottom wall 140 along the exterior side wall 120. An internal cover lip 134 is provided on the interior side wall 130 so as to extend from the vicinity of a distal portion of an internal outer surface thereof toward the bottom wall 140 along the interior side wall 130.
The exterior side wall 120, the interior side wall 130 and the bottom wall 140 are inserted in the channel 3 provided in the door frame 2, and outer surfaces of the respective walls are brought into contact with an inner surface of the channel 3. A distal end portion of an outer panel 2c of the door frame 2 is inserted between the exterior side wall 120 and the external cover lip 124. A distal end of an inner panel 2d is inserted between the interior side wall 130 and the internal cover lip 134, whereby the glass run 110 is held.
The window glass 5 moves inside the substantially U-shaped cross section of the glass run 110 and is sealed and held on both sides thereof at positions which correspond to distal portions of the glass run 110 by the exterior seal lip 126 and the interior seal lip 136, respectively.
When the window glass 5 is closed, the window glass 5 of a powered window moves up within the door frame 2. An upper end of the window glass 5 is inserted in the top side portion of the glass run 110 mounted on a top side section of the door frame 2 to thereby be brought into contact with the bottom wall 140. As this occurs, since the elevating motion of the window glass 5 cannot be controlled completely, the upper end of the window glass 5 comes to hit the bottom wall 140 and the channel 3 to thereby produce impact noise, which damages the comfortableness. In addition, the deformation of the bottom wall 140 when hit by the upper end of the window glass 5 is not stabilized, whereby the upper end of the window glass 5 deviates within the glass run 110 and the seal lips 126, 136 are deformed, sometimes leading to a drawback that the sealing property is deteriorated.
Due to this, in order to absorb the impact, a hollow portion is provided in the bottom wall 140 or a sponge sheet is mounted thereon (refer to, for example, JP-A-60-213524 and JP-UM-A-62-413). However, while an extrusion molding with blowing is necessary to provide the hollow portion in the bottom wall 140, in the event that the hollow portion is formed at the same time as the extrusion molding with blowing is carried out, it is difficult to hold the shape of the hollow portion, and this triggers difficulty in increasing the extruding speed, leading to a bad productivity. In addition, in the event that the sponge sheet is mounted, only a simple mounting of the sponge sheet on a back side of the bottom wall 140 cannot suffice a necessary thickness to provide a sufficient impact absorbing capability, and in case the sponge sheet having such a sufficient thickness is used, the stability of the bottom wall 140 relative to the door frame 2 is not sufficient.
In addition, while some countermeasures is tried in which a lip is provided at an inside portion of the glass run 110 which lies in the vicinity of the bottom wall 140 so that the upper end of the window glass 5 is made to come into forcible contact with the lip so as to absorb impact (refer to, for example, JP-A-2002-187432). In this event, however, the lip is caused to deform permanently after a long-time service, leading to a risk that the impact absorbing effect is deteriorated.
Furthermore, as shown in FIG. 5, there is proposed a configuration in which the thickness of the bottom wall 140 of the glass run 110 is gradually increased from the interior side wall 130 side to the exterior side wall 120 side so as to facilitate the deformation of the bottom wall 140 to absorb impact upon the collision of the upper end of the window glass 5 against the bottom wall 140 (refer to, for example, Japanese Utility Model Registration No. 2578541).
However, only the deformation of the bottom wall 140 cannot absorb the impact sufficiently. In addition, it was difficult to provide a sufficient space between the door frame 2 and the bottom wall 140 and hence, the impact absorbing capability provided thereby was not sufficient.

This patent is subject to a terminal disclaimer.


The image forming unit 100 includes a photosensitive drum 11, a rotary developing device 30, and a rotation speed control device 70. Electrostatic latent images are formed on the surface of the photosensitive drum 11. The rotary developing device 30 includes a plurality of developing apparatuses 13 having a developing roller 14 disposed in opposition to the photosensitive drum 11, and a distance regulating collar 73 that regulates the distance between the photosensitive drum 11 and the developing roller 14. The rotation speed control device 70 includes a rotation speed control device 71 that controls the rotation speed of the rotary developing device 30 so that for a predetermined period of time until the developing apparatus 13 reaches the developing position the rotation speed of the photosensitive drum 11 and the movement speed in the circumferential direction of the distance regulating collar 73 are equal.

1. Field of the Invention
The present invention generally relates to an image forming unit and image forming device. More specifically, the present invention relates to an image forming unit that includes a rotation speed control device that controls the rotation speed of a rotary developing device and an image forming device that includes such an image forming unit.
2. Background Information
Image forming devices that form color images include a plurality of developing apparatuses that each house toner of a different color. Some image forming devices that form color images have rotary developing devices in which the plurality of developing apparatus is fitted around a rotatable frame. In an image forming device that uses a rotary developing device, the frame is rotated and the developing apparatus that houses the developer with the first color is brought into opposition with an electrostatic latent image carrier, and the developer in the developing apparatus is supplied to the electrostatic latent image carrier. After the developer for the first color has been supplied to the electrostatic latent image carrier, the frame is rotated and the developing apparatus that houses the developer with the second color is brought into opposition with the electrostatic latent image carrier, and the developer in the developing apparatus is supplied to the electrostatic latent image carrier. In this way, developer is supplied to the electrostatic latent image carrier in turn so that developer for all the colors is supplied to the electrostatic latent image carrier.
Here, when supplying developer from the developing apparatus to the electrostatic latent image carrier, there is a system in which the developer on a developing roller is supplied to the electrostatic latent image carrier without the developing roller contacting the electrostatic latent image carrier. In image forming devices that adopt this system, a distance regulating collar whose diameter is slightly larger than the diameter of the developing roller is provided at both ends of the developing roller in the axial direction. The distance regulating collars contact the electrostatic latent image carrier so a gap is maintained between the developing roller and the electrostatic latent image carrier as shown in Japanese Patent Application Laid-open No. H11-174826.
In the image forming device described in the aforementioned patent document, to prevent the distance regulating collars from applying shocks to the surface of the electrostatic latent image carrier as a result of the electrostatic latent image carrier and the distance regulating collars contacting at different movement speeds in the circumferential direction, the movement speed in the circumferential direction of the distance regulating collars is reduced before the electrostatic latent image carrier and the distance regulating collars contact. Then contact is made at the instant that the movement speed in the circumferential direction of the electrostatic latent image carrier and the distance regulating collars is the same.
However, in the image forming device described in the patent document, the phase speed in the circumferential direction of the distance regulating collars is reduced continuously so the movement speed in the circumferential direction of the electrostatic latent image carrier and the distance regulating collars is the same only for an instant. Therefore, if even a small error occurs the movement speed in the circumferential direction of the electrostatic latent image carrier and the distance regulating collars will be different, and a shock will be applied to the electrostatic latent image carrier by the distance regulating collars. When a shock is applied to the electrostatic latent image carrier in this way, the photosensitive layer of the electrostatic latent image carrier can peel off, and the electrostatic latent image carrier can become deformed. Therefore, a constant distance between the developing roller and the electrostatic latent image carrier cannot be maintained, and image quality can be reduced by unevenness in the image and so on.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved image forming device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Rotation speed control device and image forming device


Provided are a method and an apparatus for rebooting a computer system taking both security and user convenience into account. The computer system includes an authentication mode information storage unit storing authentication mode information related to an authentication mode when booting the computer system, a first driver sensing rebooting of the computer system and setting an authentication mode of the authentication mode information, and a second driver, which reads the authentication mode information and if the authentication mode is a first mode, performs rebooting without user authentication and if the authentication mode is a second mode, performs rebooting after user authentication.

1. Field of the Invention
An embodiment of the present invention relates to a computer system, and more particularly, to a method and an apparatus for improving user convenience and security by selectively performing user authentication when rebooting.
2. Description of the Related Art
Computer systems provide a variety of functions to many segments of today's modern society. A computer system may be a desktop or portable computer that consists of a system unit comprising a processor, associated volatile and nonvolatile memory, a display monitor, a keyboard, one or more diskette drives, fixed disk storage, and an optional printer. As computer systems are widely used in offices as well as at home, security of computer systems has become an important issue. Primary security of data inside a computer system relies on a basic input/output system (BIOS) password and an operating system (OS) password, which are prompted for when a computer system is booted.
Booting is a series of procedures required before a computer becomes operable. When a power switch of a computer is turned on for booting, a basic program called a ROM BIOS operates first. The program is recorded in a nonvolatile memory called a read only memory (ROM), which cannot be erased or lost even when the power is turned off. In the case of a booting operation of an IBM PC compatible computer, an inspection called a power on self test (POST) is performed first. Although the POST is performed in slightly different ways according to the contents of the ROM BIOS, an error message with an alarm is displayed on a monitor and booting stops if RAM used as main memory, a keyboard, or a hard disc are found to have any problems.
When the POST is completed, the operating system (OS) of a computer system is read and made resident in memory. A user refers to the ROM BIOS in order to obtain information about which drive the operating system (OS) is to be read from. The above-described booting procedure is usually referred to as cold booting. On the other hand, warm booting is a procedure in which the POST is not performed during booting. The computer system finishes the booting operation successfully before the user may perform a desired task.
Rebooting is a procedure in which a booting operation is performed to start the operating system (OS) again if an error occurs when, for example, a computer is running or information about the settings of a computer system is changed and the operating system should be run again or volatile information throughout the entire system is removed. Rebooting usually takes the form of warm rebooting, in which the POST is not performed thereby shortening the booting procedure.
The BIOS that performs booting is a kind of program run by a microprocessor when a computer system is turned on. The BIOS also manages data flow between peripheral devices such as hard disks, video adaptors, keyboards or mice etc. and the operating system (OS). The BIOS is stored in ROM. Recently, the BIOS has also been stored in changeable ROMs such as erasable programmable read only memories (EPROMs) or electrically erasable programmable read only memories (EEPROMs). A password can be set during BIOS booting so that when another person has access to the computer system, the computer system is prevented from being operated and power can be cut off.
The BIOS reads setting information of the computer system when starting. The setting information is usually changeable and maintainable. Thus, the setting information needs to be stored in nonvolatile and writable memory. In a typical computer system, the setting information of the BIOS is stored in a complementary metal oxide semiconductor (CMOS). Most computer microchips use CMOS type transistors. When the BIOS performs booting using the CMOS, necessary information can be changed.
The setting information related to the execution of the BIOS stored in the nonvolatile memory such as a CMOS includes a BIOS password. With the BIOS password, when user authentication is performed at an initial stage of booting using the BIOS and an error occurs in checking a password, the power of the computer system is cut off to prevent other people from accessing the computer system. The OS starts operating after the BIOS starts running, and user certification or authentication such as the entry of a password can be performed again when the operating system (OS) is first accessed.
The BIOS password and an OS password, when password protection is activated, are required to be input every time when booting. Since many users find this to be inconvenient, they often avoid using a password altogether. In particular, when installing and upgrading software, rebooting frequently occurs so that the entire system can be effectively executed, which in turn requires the frequent entry of a password. This may cause inconvenience to a verified user. In the prior art, a method for deactivating a password requirement utilizing a wireless signal so that the entry of a password can be selectively performed during booting is disclosed in U.S. Pat. No. 6,370,650. However, the wireless signal is applied to all types of booting (cold and warm), and the entry of a password is not deactivated only during rebooting. As a result, it is difficult to maintain security due to the drawback of the wireless signal. In addition, a method of managing a password related to network connection has been proposed but cannot prevent operation of the computer system.
Accordingly, a method by which rebooting can be performed without user authentication is desirable.

Apparatus and method for securely and conveniently rebooting a computer system


A method of manufacturing a semiconductor package, including: preparing a first semiconductor chip, where a plurality of first central electrode pads are formed along a center of an active surface of the first semiconductor chip, preparing a second semiconductor chip, where a plurality of second central electrode pads are formed along a center region of an active surface of the second semiconductor chip, and a plurality of edge electrode pads are formed along an edge of the second semiconductor chip, attaching the second semiconductor chip to a substrate, connecting electrically the edge electrode pads of the second semiconductor chip to the substrate, encapsulating the connection between the edge electrode pads and the substrate, forming a plurality of metal bumps on the central electrode pads of the second semiconductor chip, and stacking the first semiconductor chip on the second semiconductor chip so that the first central electrode pads of the first semiconductor chip attach to the respective second central electrode pads of the second semiconductor chip via the metal bumps.

1. Field of the Invention
The present invention relates to a semiconductor chip package, and more particularly to a package with multiple stacked semiconductor chips and a manufacturing method of the package.
2. Description of the Related Art
As higher performance and integrated improvement of a semiconductor device are required, the size of the semiconductor chips increases, and higher surface-mounting density of a semiconductor device is demanded. A semiconductor package including a number of semiconductor chips inside, which is called a chip-stack package, can satisfy such demand. For example, semiconductor chips can be stacked in the package. Alternatively, a number of packages, each of which includes a single chip, can be stacked to increase the surface-mounting density.
The stacking of the packages may cause the increased height of the stacked packages. Further, for interconnecting the external leads (or terminals) of the packages often requires customized shaping of the leads, which is an additional process. For instance, such additional process may include reforming of the leads so that the leads of a upper package can contact the leads of a lower package, or connecting the leads using additional pins. In addition, the additional stacking process may reduce the yield of the stacked device.
However, the chip-stack package can be effective than the stacked packages in accomplishing the reduction of the total height of the stacked semiconductor chips. FIG. 1 shows a conventional chip-stack package 10. A lower semiconductor chip 13 is attached to the lower surface of a lead frame die pad 11 via an adhesive 12, and an upper semiconductor chip 15 is attached to the upper surface of the die pad 11 via an adhesive 14. The active surface of the lower chip 13 faces downward, and the active surface of the upper chip 15 faces upward. Bonding pads (or electrode pads) 2 of the upper and lower semiconductor chips 13 and 15 are electrically connected to leads (or external terminals) 16 via bonding wires 17 and 18, respectively. The upper and lower semiconductor chips 13 and 15 and the bonding wires 17 and 18 are encapsulated by a package body 19 formed of a molding compound. In the package 10, the upper and lower semiconductor chips 13 and 15 are mirror chips to each other, and bonding pads 2 are formed along the edges of the chips 13 and 15.
FIG. 2 shows another known chip-stack package 20, in which the active surfaces of chips 23 and 25 face toward the same direction. Chip 23 is attached via an adhesive 22 on a die pad 21, and chip 25 is attached via an adhesive 24 on the active surface of the chip 23. The lower chip 23 is larger than the upper chip 25. Bonding pads 2 of the upper and lower chips 23 and 25 are electrically connected to leads 26 via bonding wires 27 and 28, and are protected by a package body 29. The upper and lower chips 23 and 25 may be different from each other, and bonding pads 2 are formed along the edges of the chips 23 and 25.
FIG. 3 shows still another known chip-stack package 30. A lower chip 33, on which bonding pads 2 are formed along the edges, is attached to the lower surface of a lead frame 31 via an adhesive 32, and an upper chip 35, on which bonding pads 2 are formed along the center line, is attached to the upper surface of the lead frame 31 via an adhesive 34. For electrical connection of the central pad chip 35, an opening is formed in the central portion of the lead frame 31. The edge pad chip 33 and the central pad chip 35 are electrically connected to the lead frame 31 via bonding wires 37 and 38, respectively. The end portions of the lead frames are exposed through the lower surface of a package body 39, and the end portions are connected to land type connections 36.
In memory chips, use of the central-pad chips is preferred because a signal skew for a number of memory shell blocks can be decreased when the bonding pads are formed along the center line of the semiconductor chip. Further, as memory capacity and speed of the memory chips increase, the central-pad memory chips are preferred to the edge-pad chips. Accordingly, technology for stacking a number of central-pad memory chips is in demand.

Semiconductor package with semiconductor chips stacked therein and method of making the package


A promotional display comprising a chamber having front and rear panels with inside and outside surfaces, for containing between expanses of the inside surfaces of the panels a first liquid. At least a portion of the outside surface of the front panel comprises a view surface which allows viewing of liquid flow inside the chamber. A liquid reservoir is positioned adjacent the chamber for containing a second liquid therein, which second liquid contrasts with and is not miscible with the first liquid. A restricted liquid flow path is located between the chamber and the reservoir, which allows flow of the second liquid into the chamber and across at least a portion of the view surface of the chamber. The chamber includes at least one recess formed in the outside of the front panel which extends the inside of the front panel substantially all the way to the inside surface of the back panel, so as to substantially cause any liquid which flows between the front and rear panels of the chamber in the area of the recess to flow around, rather than behind, the recess. An object, to which it is desired to attract the attention of a viewer of the display, is placed in the recess.

1. Field of the Invention
The present invention relates to promotional display device including a liquid component, and more particularly to embedding an object in the display in a manner so that it interacts with the liquid component, thereby drawing ones attention to and promoting the object having the liquid interactions.
2. Background Information and Description of the Related Art
Liquid displays for use in toys, signs and other novelties, for example, have been in use for years. Typical prior art liquid displays merely provide an interesting liquid background for drawing the eye of a viewer to the display, such as by having two liquids of different densities and color in one chamber, but usually there is no special effect to more particularly attract the viewers attention, such as to a particular portion of the display. PCT publication WO 90/03636 discloses a display sign that has a liquid flow surface as the inner side of a viewing panel, which viewing panel forms the front face of a sealed liquid reservoir. Due to irregularities on the inner surface of the viewing panel, the flow path of the liquid along the inner face is caused to have corresponding irregularities, which flow path irregularities attract a viewers attention.
It would be desirable to improve upon this concept to further increase the attention of the viewer to the display device, as well as to find a way of making the display more adaptable to providing different shapes/objects to which the attention of the viewer is directed. A more adaptable display would allow the display portion to be manufactured in a greater volume in order to reduce cost, yet still provide for customization of the final device.

Promotional display with liquid interactions


A “Charting Animator” enhances computer-based charting/graphing systems by rendering dynamic animations of chart displays. In general, when a user changes from one chart type to another, adds new data to a chart, or changes, sorts or deletes data, a new chart is generated to replace the old chart. Conventional charting systems simply replace the existing chart with the new chart. In contrast to conventional systems, the Charting Animator renders animated transitions that dynamically morph the original chart into the new chart. Consequently, these animations avoid abrupt changes that can disorient users. Examples of these animations include animating changes from one chart family to another (e.g., changing from a “Bar Chart” to a “Pie Chart”), animating changes from one chart type within a chart family to another chart type (e.g., changing 2D Bar Charts to 3D Bar Charts or Stacked Bar Charts), animating data changes, animating sorts, etc.

1. Technical Field
The invention is related to computer-based data charting and graphing, and in particular, to a system for automatically animating transitions when changing from one chart or graph type to another and/or when changing data values associated with those charts and graphs.
2. Related Art
Computer-based charting and graphing software tools are well known to those skilled in the art. Such software tools are often used to generate data displays such as, for example, pie charts, bar charts, data graphs, etc. Conventionally, these types of software tools allow a user to select or enter one or more data sets, and then select a chart type for rendering a chart or graph display of that data. Then, whenever a user changes from one chart type to another, or whenever data is added or changed, a new chart is rendered and the original chart is simply replaced by the newly rendered chart.
One of the problems with simply replacing one chart with another is that the user doesn't really get a sense of how the data has changed, especially if those changes are subtle or if they involve multiple data elements (such as changes to several related bars in a bar chart). Further, since one chart simply replaces another (at computer display rendering speeds), the change is essentially immediate. Unfortunately, this type of abrupt change is often disorienting to users.
Another feature of conventional charting and graphing software tools is that data is entered, and then the corresponding charts and/or graphs are rendered as a function of the data. Changes to those charts and graphs are accomplished by editing or otherwise changing the underlying data, at which point these conventional software tools will render a new chart or graph corresponding to the newly edited data. Unfortunately, this feature is typically one-way. In other words, charts and graphs are changed by direct manipulation of the underlying data, while the underlying data is not changed by direct manipulation of the corresponding chart or graph.

Animated transitions for data visualization


A touch module includes a touch device, a stylus, and a processing unit. The stylus includes a body, a motor, an angle encoder, and a distance sensor. The angle encoder and the distance sensor are disposed on a rotating shaft of the motor. The distance sensor detects relative distances between itself and first, second, third, and fourth sides of a front frame of the touch device respectively. The processing unit is disposed in the body or the touch device for controlling the rotating shaft to rotate when a mark of the body points to the first side, calculating rotating angles of the rotating shaft and determining whether the rotating shaft makes one rotation according to encoded data of the angle encoder, and calculating four local minimum distances according to relationship of the rotating angles and the relative distances for positioning the stylus on a touch surface of the touch device.

1. Field of the Invention
The present invention relates to a touch module and a touch positioning method thereof, and more specifically, to a touch module disposing an angle encoder and a distance sensor on a rotating shaft of a motor of a stylus respectively and a touch positioning method thereof.
2. Description of the Prior Art
In general, a conventional touch module usually adopts the design that touch positioning parts are additionally assembled on the touch module to position a touch object (e.g. a stylus) on a touch surface. For example, in an optical touch module, positioning of a touch object could be performed by utilizing an optical sensor additionally assembled on a screen frame to capture images toward a touch surface and to position the touch object on the touch surface by position comparison of the touch object and the screen frame in the captured images. In a capacitive or resistive touch module, positioning of a touch object could be performed after inductive capacitances or resistances are additionally distributed over a touch surface.
However, as mentioned above, since the aforesaid designs need to additionally assemble a touch positioning mechanism with a complicated design on the touch module, it is disadvantageous to the thinning design of the touch module. Thus, how to position a touch object on a touch surface without additionally assemble touch positioning parts on a touch module could be a concern to the touch positioning design of the touch module.

Touch module and touch positioning method thereof


An elongated shaft configured to receive the expeditious attachment of a line thereto, the shaft having adjacent to a first end a short length radially extending post, the shaft having a recess therein at the first end so that thereby the portion of the shaft from about the position of the post to the first end is tubular providing a tubular wall, and a V-shaped notch formed in the tubular wall, the notch extending from about the post to the shaft first end, the notch being configured to provide a portion of the tubular wall that is tooth-like, the post serving to receive a loop from a bight of the line after which the bight can be wrapped around the shaft and then looped in the notch and beneath the tooth-like portion, an end of the line extending out the shaft tubular end.

This invention is related to an elongated shaft configured to receive the expeditious attachment of a line thereto.
The need frequently arises for attaching a line to an elongated shaft. By the term "line" is meant a flexible string or rope such as a fishing line or a lanyard used in retaining sails or the like. A fishing line may be as simple as monofilament line or it can include a braided fishing line. Ropes are frequently braided as a way of adding together the tensile strength of individual fibers. An example of an application of the invention would be a system for attaching a fishing line to a fishing float in which the fishing float consists of a floatable bobber portion with a small diameter elongated shaft extending through the bobber. This type of fishing float has been in common use for many years. The invention herein provides a simple technique for very quickly and effectively tying a line to an end of the shaft that extends through the fishing bobber.
Others have provided devices for attaching lines to a solid object and for examples reference can be had to the following previously issued United States patents.
U.S. Pat. No.InventorTitle277,230ChubbFishing Rod Tip521,704DavisLine Guide For Fishing Rods757,820LykkeLine Holder796,342Miller et al.Tip For Fishing Rods or Poles1,010,301NeatsClamp or Securing Device For WireCables and The Like2,735,208BartlettiFishing Rods2,996,825TjernlundFishing Rod With Anti-Tangling Means4,300,303HutsonCane Fishing Pole Tip6,269,523BenoitReef Maker6,675,447HofeldtApparatus To Adjust And MaintainTautness Of A Serpentine Article


A phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device. The phase change memory cell array includes a first access transistor pair and a second access transistor pair formed on a semiconductor substrate to be adjacent to each other while each of the first and second access transistor pairs having a common drain, phase change resistance elements formed on source regions of the access transistors, respectively, and a semiconductor region formed on the same plane as the common drains to electrically connect the common drains of the first and second transistor pairs. The phase change memory cell array and the memory device of are suitable for the implementation of a high-density semiconductor device, and capable of improving the reliability of a contact forming process by securing a sufficient space for the contact forming process.

1. Field of the Invention
The present invention relates generally to a phase change memory device and, more particularly, to a phase change memory cell array suitable for the implementation of a high-density memory device.
2. Description of the Related Art
With the popularization of portable devices, demands for nonvolatile memory devices are increasing. As for the nonvolatile memory devices, ferroelectric memory, magnetic memory and phase change memory, except for flash memory that is widely used at present, have attracted attention. Especially, the phase change memory can overcome the disadvantages of the flash memory, such as a slow access speed and a limitation in the number of times of use, and solve the problem in which a high voltage is required at the time of operation. Therefore, research has focused on the development of the phase change memory to develop new promising memory devices.
The phase change memory is a memory device using Chalcogenide-based phase change materials mainly including Te or Se of Chalcogene elements belonging to group 16 (VIA) of the periodic table as the material of a resistance element. In particular, Ge—Sb—Te (mainly, Ge2Sb2Te5)-based materials are mainly used as phase change materials. A phase change resistance element exhibits the phase change characteristics in which the phase of a material is changed from a crystalline phase to an amorphous phase and vice versa according to the application conditions of thermal energy depending on the initial state of the material. The two phases have considerable differences in physical characteristics, such as an optical constant and resistivity, and the characteristics can be used in a memory device for performing the recording, removal and reproduction of information.
FIG. 1a is a graph used to explain a digital data storage device that uses the electrical characteristics of the phase change resistance element used in the phase change memory device.
If the phase change resistance element is heated to a melting point and then rapidly cooled by applying a high-voltage amorphizing reset pulse for a short time, as shown in the drawing, a phase change material is amorphised. Additionally, if the phase change resistance element is heated to the temperature between a crystallization temperature Tc and a melting point Tm by applying a low-voltage crystallizing set pulse for a long time, the phase change material is crystallized. The resistivity of the phase change resistance element varies during a phase change, and the resistivity in the amorphous phase is higher than that in the crystalline phase. In the phase change memory device, the state where the phase change resistance element is in a low-resistance crystalline phase is defined as a 'set' or 'ON' state, and the state where the phase change resistance element is in a high-resistance amorphous phase is defined as a 'reset' or 'OFF' state. The two states correspond to the logic values '0' and '1' of each memory cell, respectively.
FIG. 1b is a graph showing the resistance variations of the phase change resistance element according to a current pulse normalized to a critical reset current pulse value. In the graph, it can be understood that, when an initial state is a set state, there is no change attributable to the increase of a pulse size and, thereafter, the initial state is transitions to a reset state at or above a critical reset current (which is indicated by '□'). In contrast, when an initial state is a reset state, the initial state is first transitions to the crystalline phase according to the increase of the pulse size and, thereafter, transitions to the reset state at or above the critical reset current (which is indicated by '▪'). Furthermore, as understood from the graph, the resistivity in the reset state is different from that in the set state 100 or more times, which assures that a sufficient signaling ratio can be secured only by the phase change of the local region of the phase change resistance element.
FIG. 2 is a circuit diagram showing the equivalent circuit of a conventional memory unit cell using the phase change resistance element.
Referring to FIG. 2, a phase change memory cell includes a single access transistor TA, such as a Field Effect Transistor (FET), and a phase change resistance element GST. The lower electrode of the phase change resistance element GST is connected to the source of the transistor TA, and the upper electrode thereof is connected to a plate electrode PL. The drain of the access transistor TA is connected to a bit line BL and the gate thereof is connected to a word line. The construction of the conventional phase change memory unit cell is similar to that of a dynamic random access memory (DRAM) unit cell, except for the substitution of a capacitor with the phase change resistance element.
FIG. 3 is a cross section showing the sectional structure of a conventional phase change memory device formed on a semiconductor substrate using the phase change memory cell of FIG. 2 as the unit thereof.
Referring to FIG. 3, isolation layer 36 for defining the active region of a semiconductor device are formed in the predetermined regions of a semiconductor substrate 30. A pair of word lines 38 functioning as the gates of transistors, respectively, is arranged in parallel to intersect the active region. The word lines 38 define the source regions 42 and drain region 40 of the transistors. That is, the active region between the pair of word lines 38 corresponds to the common drain region 40 of the transistors, and the two regions outside the word lines 38 correspond to the source regions 42 of the transistors. As shown in the drawing, a first interlayer-dielectric 48 is placed on the semiconductor substrate 30 and the tops of the transistors, and the common drain region 40 of the transistors is electrically connected to the bit line 44 through a bit line contact that passes through the first interlayer-dielectric 48. A second interlayer-dielectric 50 is placed on the first interlayer insulation film 48 including the bit line 44, and phase change resistance elements 65 each including a lower electrode 52, a phase change resistance film 62a and an upper electrode 64a are formed on the second interlayer-dielectric 50. The phase change resistance elements 65 are electrically connected to the source regions 42 of the transistors through contacts 46, respectively, which pass through the first and second interlayer-dielectrics 48 and 50. Even though not shown in the drawing, a planar interlayer-dielectric is placed on the phase change resistance elements 65, and a plate electrode is placed on the planar interlayer insulation film.
As described above, in the conventional phase change memory device, the common drain region on the semiconductor substrate is electrically connected to the bit line through the bit line contact. In such a structure, a sufficient space for a contact forming process should be secured on the common drain, which unavoidably increases an area occupied by the unit cell. Accordingly, the conventional phase change memory device adopts a cell structure unsuitable for the implementation of a high-density phase change memory device.

High-density phase change cell array and phase change memory device having the same


We describe techniques which relate to bi-directional, in particular backwards, debugging of computer programs. Thus we describe identifying processes with shared memory access, such as threads or multicore processes, by arranging process (thread) memory ownership to deliberate provoke memory page faults to identify and handle concurrent memory access by multiple threads in such a manner as to enable deterministic replay, and hence backwards debugging.

When writing computer programs it is sometimes the case that errors, or 'bugs', are included in a program. Sometimes this is due to typographical errors in writing the source code (e.g. omitting a character or substituting one character for another), sometimes due to implementing incorrect functionality (e.g. causing a loop to terminate at one when it ought to terminate at zero) and sometimes due to errors in other programs upon which the author is relying, for example a library routine or even the compiler itself.
A debugger can help someone attempting to find and remove bugs from a program. Prior art debuggers have tended to focus upon inserting so-called breakpoints into a program and running a program forwards in time, stopping at one or more of the breakpoints in order to examine the state of the program (content of processor registers, content of memory) at that breakpoint in the hope of catching an error before it causes the program to crash. Crashing can take many forms, generally summarised as the program not running as intended, for example a segmentation fault, an unhandled exception or an infinite loop (where a program stops responding to user input and executes the same routines indefinitely). An example of such a prior art debugger is GDB, the GNU Project Debugger.
However, the cause of an error in a program may occur long before the error manifests itself. This makes such forward debugging difficult, as it may not be obvious which particular change in program state caused an error, especially if it occurred a long time previous to the error actually showing up, with many correct program operations in the intermediate period. Furthermore, some errors are more easy to spot than others, as in general a computer simply does what it is programmed to do, and the cause of the error may lie in the user's understanding of how it works, as distinct from how it actually works. On the other hand, a user may have a correct understanding of how his program is intended to work, but if there are errors in a library routine upon which he is relying (for example a mathematical square root function), then the program may give the wrong result even though the parts of the program written by the user are functioning as the user intended. In this case there are two options for correcting the error; the first is to correct the error in the library routine (which may not always be possible as a user may not always have access to the source code of library routines) and the second is to provide a 'workaround' in the user's program to ensure that the error in the library routine does not cause his own program to give the wrong results.
For these reasons and others it would be useful to be able to step backwards in the execution of a computer program so as to be able to trace an error from the moment it caused the program to crash back until the error first appeared. This is impossible with conventional prior art debuggers as these only allow forward execution of programs. Backwards execution is actually a hard problem to solve, as in the process of executing a program there may be intermediate results which are lost as the program executes, making it difficult to return to a previous state unless a record is kept of these results. Furthermore, due to the operation of jump instructions in a program, it can impossible to tell, without keeping a record of program execution, where execution was taking place in a program prior to the current position. It could have been executing the instruction before the current one, or it could have just executed a jump instruction somewhere else which caused execution to jump to the current position. In addition, with variable length instruction sets such as Intel IA32 it may not be possible to trace execution backwards at all without keeping some kind of record, since there may be no way of knowing whether the previous instruction was a one byte instruction just before the current position, or a two byte instruction two places before the current position, and so on.
Several attempts have been made to solve the problem of backwards debugging, but a solution to the problem of non-determinism in programs has remained elusive. One approach to the problem of backwards debugging is described in the paper "Efficient Algorithms for Bidirectional Debugging" (Boothe, 2000 ACM SIGPLAN Conference on Programming Language Design and Implementation, Vancouver, British Columbia). This describes a source code C and C++ debugger running on Digital/Compaq Alpha based UNIX workstations. This debugger describes embedding event counters into the program being debugged and using these counters to identify a target event on the fly as the target program executes.
However there are a number of problems with this approach. Firstly, it fails to properly address the problem of non-determinism. Secondly, as it operates on the source code of a program not the object code, if a problem occurs with a program for which the source code is not available, it will not be possible to debug the program using this method. Thirdly the bug that is being hunted is likely to cause the backwards debugger itself to malfunction. Fourthly the approach cannot be used on bugs which cause the program to function outside the normal control flow implied by the source language (for example, returning from a function after the stack has been corrupted). Fifth, if a problem occurs due to the functioning of the compiler itself, it may not be possible to detect the problem as the program is not compiled in its 'normal' form at all—instead a modified version of the program including debug routines is compiled, in which the problem with the compiler may not manifest itself, or may manifest itself in a completely different way. Sixth, different debugger programs would have to be written for debugging source code written in different programming languages, and it does not provide a solution at all for the problem of debugging programs written in machine code.
It would be advantageous to provide a debugger capable of backwards debugging which addresses the above-cited problems.

System and method for debugging of computer programs


A sequentially joined segment armature coil is provided which may be employed in an ac machine such as an ac motor or motor generator. The armature coil is equipped with three phase coils each of which is made up of a first and a second phase windings identical in number of turns. This structure permits the number of turns of the armature coil to be changed easily by changing a connection of the first and second phase winding between a series connection and a parallel connection or changing a connection of the phase coils between a star connection and a delta connection. The structure also enables terminal leads of the first and second phase windings of each of the phase coils to be collected and withdrawn outside the ac machine, thus facilitating ease of arrangement of the terminal leads.

1. Technical Field of the Invention
The present invention relates generally to a sequentially joined-segment armature and an ac machine using the same which may be employed as a rotary electric machine for automotive vehicles.
2. Background Art
Idle stop systems, as having been employed in automotive vehicles in recent years, are designed to perform frequent engine start-and-stop operations, therefore, use of ac motors is preferable to dc motors with brushes. However, ac motors capable being supplied with a great starting current equivalent to that use in typical dc series-wound motor will be greater in size than typical alternators, thus requiring a large amount of space within an engine compartment of the vehicles or a substantial change in engine layout, which may lead to an increase in weight of the vehicles.
As automotive ac generators, ac machines have been proposed which are equipped with a conductor segment-joined armature made up of U-shaped conductor segments which are disposed within slots formed in a stator core and joined sequentially. For instance, Japanese Patent First Publication Nos. 11-164506 and 2001-169490 disclose such a type of ac machine.
Japanese Patent First Publication No. 2001-169490 (corresponding to U.S. Pat. No. 6,417,592 B2 to Nakamura et al. assigned to the same assignee as that of this application) discloses segment-joined automotive ac generator which is equipped with U-shaped large-sized conductor segments and U-shaped small-sized conductor segments which partially extend through slots arrayed in a stator core in a circumferential direction thereof. Each of the slots has a first, a second, a third, and a fourth layer positions arrayed from inside to outside of the stator core in a radius direction thereof. The large-sized conductor segments each have legs disposed in the first and fourth layer positions of the slots. The small-sized conductor segments each have legs disposed in the second and third layer positions of the slots. A total of four turn coils, two disposed in two of the slots located across one of the slots, are so connected as to cross to joint two of the turn coils in parallel to make phase windings. Specifically, an eight conductor-in-two slot stator coil is taught to double the current permitted to be supplied to the coil without increasing poles.
Japanese Patent First Publication No. 11-164506 teaches a six conductor-in-one slot stator coil which is equipped with U-shaped large-sized conductor segments and U-shaped small-sized conductor segments which partially extend through slots arrayed in the stator core in the circumferential direction thereof. Each of the slots has a first, a second, a third, a fourth, a fifth, and a sixth layer positions arrayed from inside to outside of the stator core in the radius direction thereof. The large-sized conductor segments each have legs disposed in the first and sixth layer positions of the slots. Some of the small-sized conductor segments have legs disposed in the second and third layer position of the slots. The others have legs disposed in the fourth and fifth layer positions of the slots. This structure permits the number of turns of the stator coil to be five times greater than that disclosed in the former publication, thus providing a high-voltage stator coil.
The above described stator coils are designed to fix a wiring pattern or order of joints of the conductor segments. It is, thus, difficult to increase the turns of the stator coil without increasing rotor poles, thereby increasing a difficulty in using the rotary machine with a high-voltage battery in automotive vehicles. Further, increasing a sectional area of the conductor segments results in a difficulty in bending thereof, which increases a difficulty in use of the stator coil with a great current.
Locations where lead wires extend from the parallel-connected phase windings of each of the phase coils are greatly away from each other, thus resulting in an increase in length of the lead wires, which leads to increased resistance and inductance of the lead wires. The increase in length of the lead wires also requires a large amount of space in the rotary machine, thus resulting in an increased length of the rotary machine.

Sequentially joined-segment armature and ac machine using same


Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order. The test of a smallest addressable unit of a storage medium occurs completely and quickly in an optimum manner. To this end, a test procedure based on parity formation using at least first and second test patterns is used, wherein the effect of a bit error for a test pattern is transferred into the next test pattern. A combination of bit errors when checking this test pattern is thus recognized, derived from the addition of bit errors that appeared separately in the first and second test patterns.

The present invention relates in general to a method and apparatus for testing for bit errors in storage mediums, and in particular, in a RAM memory system.
A standard method, referred to as EDC monitoring, for recognizing faults of a storage medium of a RAM memory system during a normal operation is based on additionally co-storing a defined plurality of redundant bits under the address of the data word to be stored. These bits are referred to as check bits and are derived from the data word or from parts of the data word using a defined algebraic rule. Upon read-out of the stored word, check bits are again formed according to the defined algebraic rule and are compared to the read-out check bits for all bit locations. When there is equality for all check bits, it is assumed that the data word that was read out is error-free. For an inequality the type of error is identified from the pattern of the non-coincidence, referred to as a syndrome pattern. Those bit locations of the check bits that do not coincide are called syndromes. Certain syndrome patterns are decoded and the falsified bit position or falsified bit positions in the data word are identified as warranted and corrected by inverters.
The second formation of the check bits, the comparison, the decoding of the syndromes, as well as the correction and potential error notification are normally carried out in the prior art using specific LSI modules, that is EDC monitors.
FIG. 1 shows a specific algebraic rule, defining a modified Hamming code, with which the check bits are formed in a specific monitor module, for example a Am2960. As depicted in FIG. 1, data words are assumed that have 32 data bits. Seven check bits CX, CO, C1, C2, C4, C8 and C16 are allocated to these data bits, each monitor bit being respectively formed by parity formation from defined bit positions of a data word. The bit positions that are utilized for the parity formation of the respective check bit are marked with an X in FIG. 1. The type of parity that forms the foundation for the parity formation can be derived from FIG. 1. Thus, for example, the check bit CX is formed such that its binary value supplements the sum of the binary values of the bits 0, 4, 6, 7, 8, 9, 11, 14, 17, 18, 19, 21, 26, 28, 29 and 31 of a data word to an even parity. The check bit C2, by contrast, augments the bits 0, 1, 5, 6, 7, 11, 12, 13, 16, 17, 21, 22, 23, 27, 28 and 29 to an odd parity, etc. As a result of this rule, for example, the check bits 0001100 are allocated to a data word FFFFFFFF.
It is known to also utilize the above-described EDC monitoring for testing the storage medium for multiple bit errors.
The principle of such a test procedure is that the old test pattern previously written into the storage medium is read out using a read-write cycle, a check is carried out with reference to the check bits that are also read out and the next test pattern is subsequently written in. In order for addressing errors to produce a display of bit errors, a test cycle is respectively executed over a plurality of addresses of the storage medium before the method is continued with the next test cycle.
The comparison of the read-out check bits to newly formed check bits via the read-out data occurs on the basis of XOR formation. The result of this operation is the syndrome pattern that contains a 1 at the unequal bit positions and, as mentioned, corresponds to the type of error. When, for example, the specific algebraic rule depicted in FIG. 1 is used for the allocation of the check bits, then a syndrome pattern with an odd number of ones arises for the occurrence of a single bit error and a syndrome pattern with an even number of ones arises for the occurrence of a double bit error. It is assumed for the following comments regarding the prior art that, due to the negligibly low probability of errors of a higher order, multiple bit errors always appear as double bit errors. This assumption, for example, is reliably guaranteed when the storage medium is constructed with RAM modules having a word width of one bit and, thus, the simultaneous outage of two RAM modules would at most produce a double bit error.
The number of possible double bit errors derives from the plurality of selection possibilities of two bits from N bits, where N is the plurality of bits in a memory word including the check bits. There are in turn four possibilities of the occurrence of double bit errors for each of these possibilities:
1. First bit falsified to 0--Second bit falsified to 0 PA1 2. First bit falsified to 0--Second bit falsified to 1 PA1 3. First bit falsified to 1--Second bit falsified to 0 PA1 4. First bit falsified to 1--Second bit falsified to 1 PA1 1. TM 00000000 PA1 2. TM 11111111 PA1 3. TM 00001111 PA1 4. TM 11110000 PA1 5. TM 00110011 PA1 6. TM 11001100 PA1 7. TM 01010101 PA1 8. TM 10101010 PA1 (a) a first test pattern is written into the smallest addressable unit of the storage medium, the test pattern being composed of a data pattern and of a monitoring pattern, the monitoring pattern being formed from the data pattern according to a defined algebraic rule; PA1 (b) the first test pattern is later read out in turn, and a monitoring pattern is again formed from the read-out data pattern according to the same algebraic rule; PA1 (c) the monitoring pattern formed anew is compared to the read-out monitoring pattern, so that an occurrence of bit errors lying below a defined order and lying above a defined order are recognized; and PA1 (d) method steps (a) through (c) are repeated with a second test pattern that, given prior absences of a bit error, is completely inverted by comparison to the first test pattern or, respectively, given the prior occurrence of a number of bit errors lying below a defined order, the inversion of the monitoring pattern is modified such that the effect of the bit error(s) of this number continues to remain for the repeated implementation of method steps (a) through (c) and a combination of bit errors is thus recognized in method step (c) that is derived by means of an addition of bit errors that separately occurred in the first and second test patterns.
The number of overall double bit error possibilities thus amounts to N* (N-1)*2.
Two known testing procedures that are based on this testing principle shall be set forth below.
In the testing procedure, a first test pattern is first written in via all addresses of the storage medium, this test pattern is later read out in turn in a second method step and is monitored for single bit errors or double bit errors using EDC monitoring. Given the appearance of a single bit error, the affected address is tested with a second test pattern that has its data bit part completely inverted as compared to the first test pattern. When a single bit error occurs again, the double bit error is considered detected. When no further single bit error occurs, the same procedure is repeated with a third test pattern that has its check bits inverted.
The described, first testing procedure can be implemented in two versions. In the first version the appertaining address is stored given the occurrence of a single error in order to draw conclusions about the presence of a double bit error given the appearance of a further single error in a following test step. The disadvantage of this version of the first testing procedure is that it requires a corresponding amount of memory locations for the occurrence of many single bit errors.
In the second version the test cycle is interrupted given the appearance of a single bit error and the complete method is implemented at this address. Although the storing of the appertaining address is thus saved in comparison to the first version, time-consuming interruptions are necessary. This method is thus extremely time-consuming given the appearance of many single bit errors (for example, when the error affects an entire memory module).
In the second testing procedure the test is constructed such that every combination of two single bit errors appears as a double bit error in at least one test pattern TM. An example for 8 bits follows:
The test patterns TM are determined on the basis of continued, meander-like subdivision. Their number given N bits is (1d N+1)*2, whereby 1d is the logarithm for base 2. This minimum number of test patterns is further incremented when it is taken into consideration that the check bits must also be involved in the test and are dependent on the data bits. The second testing procedure thus requires a relatively large number of test patterns or, respectively, test runs.