A new and unique highly adjustable stationary exercise bicycle is presented incorporating a number of features specifically designed for youthful stationary bicycle users. The improvements over the prior art include infinitely adjustable vertical and horizontal seat heights and handlebar heights which are secured in their positions by a quick release lever rather than the standard pop pins. Also included is a lubrication port that allows the surface between the friction member and the working wheel to be lubricated. An emergency brake for the working wheel as well as a quick way to disengage the working wheel from the pedals is provided. Special pedal cage brackets are placed around each pedal so that the youth's use of such an exercise bicycle is made much more safely. All of the above elements combine to make this stationary exercise bicycle safe for use by children or adolescents.

This invention relates to the field of exercise equipment. More particularly, an exercise bicycle having numerous adjustments for size and workload is presented.
In the field of exercise equipment, stationary bicycles have become both useful and popular in the last few decades. The stationary bicycles currently in existence basically take the standard bicycle used on the roads and add either platforms or other framework such that the bicycle does not move. Various types of these stationary bicycles have been designed, including bicycles that entirely eliminate the back wheel. The bicycles usually have a seat and handlebars to simulate a regular bicycle but the pedals are connected to a front wheel that does not touch the floor.
Since obesity in North America is growing at a tremendous rate, innovations in the field of exercise equipment, particularly exercise bicycles, is quite desirable. With the advent of computers and television, children are becoming somewhat lazy and undisciplined. Children, in particular, need specialized equipment in order to keep up their exercise regiment.
Although many stationary exercise bicycles have been designed for adults, none have, as yet, been designed especially for children. A child's physical stature, as well as his somewhat inattentiveness to detail, necessitate a few important changes in the basic design of a stationary exercise bicycle. It is an object of this invention to provide an exercise bicycle designed especially for children or young adults.
One of the main advantages of a junior exercise bicycle is that the youngster can ride in the comfort of his home, thus exercising while still being entertained by their favorite music or television show. Further, while youth facilities are in big demand today, these gym facilities oftentimes only have equipment for adults. By creating an exercise bicycle developed especially for children, youngsters can make use of the gym facilities along with their adult parents or guardian, giving all participants a quality time together while increasing the fitness of adult and child alike. Studies with local universities and youth centers have proven that by working out in a group, the youth discipline and attentiveness is increased.
One of the problems encountered in the adult stationary exercise bicycle is that the smaller physique of children often prohibits them from using the exercise bicycle. For example, the positioning of the seat is very important for the comfort of the user. It is an object of this invention to provide a seat which may be specially adjusted to position a child to fit perfectly onto the stationary bicycle while still keeping in mind his growth patterns.
In addition to the height adjustment of the seat, it is also important to be able to adjust the height of the handlebars on the stationary bicycles. These adjustments have previously been made by the use of pop pins. However, pop pins are often not safe, particularly when used by inattentive youngsters. Further, pop pins also are not precise with respect to the spinal and leg adjustments. Pop pins utilize a series of incremental holes so that the adjustments must be made in incremental steps specified by the manufacturer. It is a further object of this invention to provide vertical and horizontal adjustments for the seat and height adjustments for the handle posts of a stationary bicycle such that they can be set at an infinite number of positions within the specified overall range. It is a still further object of this invention to provide for adjustments for the seat and handle posts of a stationary bicycle by means of a quickly releasable handle rather than a pop pin.
In the manufacture of exercise bicycles, it has been found that the tension placed on the exercise wheel could create a slight but irritating squeaking noise. Further, for children in particular, it is highly desirable to have the exercise wheel made such that the operator can coast, with the pedals remaining stationary even though the wheel is still moving forward. Further, for children's exercise bicycles in particular, it is also highly desirable that an emergency brake system or total release system be in place. The addition of these features greatly enhances the performance and safety of an exercise bicycle. These objects and other enhancements of this invention will become apparent upon reading the below-described Specification.


A system and method assists a driver of a motor vehicle. Driver operation, vehicle motion and vehicle environment are detected. The detected driver operation, vehicle motion and vehicle environment are evaluated. Based on the evaluation, the driver is prompted to effecting a change in driver operation by applying at least one of braking torque to the motor vehicle and additional reaction force at the accelerator. The change in driver operation is in such a direction as to restrain an increase in degree with which the obstacle is coming close to the motor vehicle.

1. Field of the Invention
The present invention relates generally to motor vehicles, and more particularly to method and system for assisting a driver of a motor vehicle.
2. Description of the Background Art
Various driver assisting systems of the above kind are known. One example is disclosed in JP-A 8-34326, which fully brakes a motor vehicle independent of a driver of the vehicle upon determination of emergency out of manipulation of a brake pedal and a steering wheel upon or immediately after determination of potential hazard out of the range between the vehicle and an obstacle and the time rate at which the range was changing. This automatic brake is intended to assist brake torque needed in such emergency atmosphere. Another example is disclosed in JP P2001-90831A, which decelerates a motor vehicle independent of a driver of the vehicle by shifting down an automatic transmission upon or immediately after determination that deceleration of the vehicle is required. The information from a navigation unit and the range between the vehicle and an obstacle determine the need for such deceleration.
The above-mentioned driver assisting systems are common in changing the operation of a motor vehicle independent of a driver of the vehicle. The action required to change the vehicle operation is intrusive. Conditions where that action is required should therefore be avoided or minimized.
Accordingly, a need remains for method and system for assisting a driver that prompt a driver of a motor vehicle to effecting deceleration of the vehicle in compatible manner with the reaction of the driver.
An object of the present invention is to provide a vehicle driver assisting method and system that prompt a driver of a motor vehicle to effecting deceleration of the vehicle in compatible manner with the reaction of the driver.

Method and system for assisting driver of motor vehicle with deceleration control


A keepsake device that is capable storing and displaying fortune cookie papers and printed messages. The device has an outer sleeve that is at least partially transparent and is attachable to and detachable from an inner sleeve to allow insertion and removal of the contents. The device also has a compartment which acts as a storage area for fortune cookie papers and printed messages. The device is shaped so that it can be displayed on a flat surface such as a table top and contains a magnet for attaching the device to a magnetizable surface.

The present invention relates to fortune cookies.
More particularly, the present invention is a device to store and display fortune cookie papers, or other printed messages.
Fortune cookies include an internal "fortune" message printed on paper for the consumer who opens the fortune cookie to find and enjoy. Sharing the written predictions or fortunes contained therein is a well-established and rich tradition. Consumers often save these fortune cookie papers as keepsakes, but there are currently no readily made devices available that allow the consumer to display and store them in a way that is aesthetically pleasing. Traditionally consumers have tacked fortune papers to a bulletin board, placed in a wallet or kept in a drawer, thereby not allowing the possibility a visually pleasing way to display and organize these fortune cookie messages. The present invention eliminates the above described problems.
In an alternative embodiment, the paper may have a printed message that did not originate from a fortune cookie.


A scan lookahead skip structure that allows a programmable number of test bits, I/O blocks, flip-flops, or columns to be skipped. One embodiment of the structure includes multiplexers to skip the scan paths for several adjacent I/O blocks, flip-flops, or columns, thereby reducing the number of clock cycles and overall delay required to utilize the scan path.

Two kinds of scan circuitry are used in integrated circuits--boundary scan and level-sensitive scan (LSSD). Boundary scan involves selectively isolating the I/O pads from the internal circuitry, applying stimulus to a shift register and applying those values to both the internal circuitry and the I/O pads, and then capturing the outputs from both the internal circuitry and the I/O pads. In this manner, boundary scan allows the I/O pads and on-chip logic circuitry to be tested independently. To facilitate this testing, the boundary scan circuitry is placed between the on-chip circuitry and the I/O pads.
IEEE Standard 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture" (published by the Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017 USA) provides "standardized" approaches to: testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate; testing the integrated circuit itself, and observing or modifying circuit activity during the component's normal operation. This standard is well known in the art and therefore is not explained in detail herein.
Boundary scan circuitry details are dependent on the type of I/O pad in use. Each I/O pad can be characterized as being either an input pad, an output pad, a tri-statable output pad or a bidirectional I/O pad. To be able to control and observe the state on an I/O pad, at least one boundary scan bit is required for each of the above-listed I/O block types. Specifically, each input and output pad requires one boundary scan bit, each tri-statable output pad requires two boundary scan bits, and each bidirectional I/O pad requires three boundary scan bits. FIG. 1 shows the boundary scan for an input pad; FIG. 2 shows the boundary scan for an output pad; FIG. 3 shows the boundary scan for a tri-statable I/O pad; and FIG. 4 shows the boundary scan for a bidirectional I/O pad.
In the case of a tristatable I/O pad, one of the two scan bits is for the output signal, IOB.O, and the other bit is the alternate for the tristate enable signal, IOB.T. In the case of a bidirectional I/O pad, three bits are required because a bidirectional I/O pad is a combination of an input pad and a tri-statable I/O pad. One scan bit is therefore needed for the output signal, IOB.O, the second bit is the alternate for the tristate enable signal, IOB.T, and the third bit is for the input signal, IOB.I.
An alternative use for available boundary scan logic is to capture all of the user logic levels at the I/O pads into the shift register at the same time and then scan them out of the shift register serially. The capture of the data bits is performed by setting the Shift/Capture line to 0 before strobing the DRCK line, as can be seen in FIGS. 1-4.
FIG. 4 illustrates boundary scan circuitry in which all four types of I/O pads are co-resident. This commonly occurs in programmable logic devices in which the I/O pad type is determined not when the integrated circuit (IC) is fabricated, but when a designer programs the IC for a particular application. Because the I/O pad type needed by the designer is not known when the circuit is fabricated, all four types of I/O pads must be available so that the designer has full flexibility to use whatever type of I/O pad is needed for a particular application. Because all four types of I/O pads are available in each I/O pad on these integrated circuits, the scan chain must have three bits, even though perhaps not all of them will be used in every I/O pad. For example, an I/O pad that is used for input uses only the first data bit. An output pad uses only the second bit. A bidirectional I/O pad uses all three bits. An unused I/O pad uses none of the three bits, even though those bits remain in the scan chain. Thus, if all the I/O pads in a programmable logic device are connected in a scan chain, the number of data bits is always three times the number of I/O pads. This scan chain has the advantage of being the same length, no matter what the configuration of the I/O pad. But this scheme also has the disadvantage that the number of clocks required to scan all the data bits and the data storage required for these data bits is always three times the number of I/O pads, whether or not they are all used.
As indicated previously, two kinds of scan circuitry are used in integrated circuits--boundary scan and level-sensitive scan (LSSD). LSSD is a circuit testing technique which uses either a specially modified flip-flop in place of all flip-flops in a design, or places a special multiplexer in front of every flip-flop in a design. In this manner, the flip-flops in a chip's internal circuitry are converted into a shift register that includes all sequential elements in the circuit and isolates the combinational logic for testing and observation. FIG. 9 shows a circuit 900 before adding LSSD. In circuit 900, combinational logic block 901 drives flip-flops 902A-902C, and feedback lines provide the output signals of these flip-flops back to combinational logic block 901.
FIG. 10 shows how circuit 900 (FIG. 9) can be modified to incorporate LSSD. Specifically, multiplexers 1003A-1003C are added in front of flip-flops 902A-902C, respectively. The signal on Operate/Scan line 1004 determines whether flip-flops 902A-902C get their data from combinational logic block 901 or from scan chain 1005. If the signal on Operate/Scan line 1004 is a logic 1, combinational logic block 901 is connected to flip-flop input terminals, and circuit 1000 operates in the "operate" mode. On the other hand, if the signal on Operate/Scan line 1004 is a logic 0, flip-flops 902A-902C are connected in a scan chain. In this configuration, the data in the scan chain is shifted one position each clock cycle, from Scan.sub.-- In to Scan.sub.-- Out.
A first operating mode loads the flip-flop scan chain from off-chip. In this mode, the clock is cycled through enough cycles to load every flip-flop 902. Then the Operate/Scan signal is set to a logic 1. Combinational logic block 901 then operates on the data in flip-flops 902. A second operating mode off-loads the data from the scan chain to some destination outside of the chip. This mode begins in "operate" mode. When the signal on Operate/Scan line 1004 is set to logic 0 and circuit 1000 operates in "scan" mode, the data in flip-flops 902A-902C (obtained during the "operate" mode) can then be shifted up the scan chain toward Scan.sub.-- Out.
An FPGA with built-in LSSD circuitry can implement the multiplexers as a dedicated resource and leave the combinational logic for implementation in configurable logic blocks (well known structures in programmable logic devices and therefore not explained in detail herein). In this implementation, if the end-user's programmed circuit doesn't use all of the flip-flops on the FPGA, the scan chain will still contain all of the "unused" flip-flops, thereby making the scan chain longer than is necessary and increasing the time required to scan the flip-flop data onto or off of the chip.
Therefore, a need arises for improving the testing of logic circuit networks, and specifically for accelerating the testing of both boundary and LSSD scan circuitry.

Lookahead structure for fast scan testing


The present invention relates to compositions and methods for creating insulating seals for use in a variety of applications, and to seals created by such compositions and methods. In particular, the present invention provides novel compositions and methods for creating insulating edge seals that provide multiple contact surfaces. The present invention further provides seals that facilitate attachment of flexible covering materials (such as fabrics, plastics, metals, etc.) to hard surfaces (such as plastics, metals, woods, etc.). The present invention is particularly useful for creating insulating edge seals that provide a means of attachment for removable covers for vehicles (such as tops for automobiles, watercraft, and aircraft), structures, and objects.

Compositions and methods for creating insulating edge seals are known in the art. However, existing seal technologies have limitations with regard to creating insulating edge seals that facilitate attachment of flexible covering materials to hard surfaces. The art is in need of novel compositions and methods for creating insulating edge seals that provide improved contact surfaces for more secure attachment and better insulation when used to facilitate attachment of flexible covering materials to hard surfaces.


The present invention provides a system and method for providing enterprise level platform that enables collaborative business service delivery and governance through access to underlying infrastructure for connected customer-vendor systems. The said enterprise platform that seamlessly brings together various point solutions with intent of providing a single window that enables access to the underlying infrastructure for a connected customer-vendor IT operations.

Large IT outsourcing engagements typically involve the participation of multiple stakeholders with complementing and competing capabilities. The rationale is being stakeholder diversity helps in keeping prices competitive and managing the risk of a particular stakeholder failing. While a move like this undoubtedly yields short to mid-term benefits, it fails in its endeavor to maximize long term benefits by itself, the reason being that competing stakeholders traditionally work in silos with the intent of optimizing within their own areas without having a holistic view of the business needs. Further, overlapping features among point solutions coupled with an unregulated adoption increases IT service management complexity that invariably affects an organization's aspirations to fully extract strategic benefits.
The effect of not addressing this status quo leaves organizations in a challenging position, which may result in:                Increased total cost of operations due to duplicity in vendor efforts;        Reduced efficiency due to significant efforts spent on multi-vendor governance;        Eventual vendor lock-ins and loss of control of data; and        Increased unpredictability due to lack of visibility into vendor processes.
The above drivers lead to the design of a common enterprise platform that address the above mentioned problem of the art.
Some of the products known to us which deal in addressing the above mentioned problems are as mentioned below:
Enlighta's product "Multi-vendor governance tool" describes a platform that provides the comprehensive support for the multi-vendor governance for globally sourced (i.e. internal, captive or outsourced) services.
EquaSiis's product "EquaSiis Enterprise" describes a collaborative solution which is designed specifically for teams that govern critical business services through outsourced or shared services delivery models. It also automates the more routine transactional components of governance while providing a rich suite of analysis and decision-support tools.
Digital fuel's product "IT Financial Management Technology Platform" describes an IT Financial Management built on an integrated SaaS platform that is used daily by leading organizations worldwide, managing thousands of IT assets and services.
The above mentioned prior-arts are customer-centric in nature, wherein the customer is managing a multi-stakeholder environment. However, there exists a need to have system that not only simplifies the adoption and implementation of business service management processes but also promotes stakeholder collaboration while retaining the flexibility to adopt individual best-in-class point solutions. Such a system should also focus on the stakeholders working in the customer's environment in terms of addressing their needs for seamless collaboration and business service delivery. The collaborative capability of the system under effective governance is expected to enrich stakeholders' performance resulting in faster and better service to customers.

Collaborative platform for it service and vendor management


Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.

The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate, and two spaced-apart n-type diffusion areas—one of which will serve as the "source", the other of which will serve as the "drain" of the transistor. The space between the two diffusion areas is the "channel". A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a "gate" structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as "gate oxide" or "gate dielectric".) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a "field effect" in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, the floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a "conductor").
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary "1". If no charge is stored on the floating gate, this represents a binary "0". (These designations are arbitrary, and can be reversed so that the charged state represents binary "0" and the discharged state represents binary "1".) That represents the programming "half" of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to "read" the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single "charge-storing area"—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary "1" or binary "0"). More recently, using a technology referred to as "multi-level cell" (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a "nitride, read only memory" (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary "1" or binary "0") can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary "1" or binary "0") can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell, which may be viewed as an FET with an "ONO" structure inserted between the gate and the substrate. (One might say that the ONO structure is "substituted" for the gate oxide of the FET.)
The ONO structure is a stack (or "sandwich") of lower oxide 322, a charge-trapping material such as nitride 324, and an upper oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316.
In FIG. 3, the diffusions are labeled "N+" (compare FIG. 1, n-type). This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is p-type cell well (CW) is doped with boron (or indium). This is the normal "polarity" for a NVM cell employing electron injection (which may also employ hole injection, such as for erase). With opposite polarity (boron or indium implants in a n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two "half cells", each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term "half cell", as it may be used herein, is used herein only to refer to the "left" or "right" bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as "charge storage areas", "charge trapping areas", and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left "bits".)
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2).
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary "1", and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary "0". (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary "0" and the discharged state represents binary "1".) That represents the programming "half" of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to "read" the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Generally, one feature of NROM cells is that rather than performing "symmetrical" programming and reading, NROM cells are beneficially programmed and read "asymmetrically", which means that programming and reading occur in opposite directions. The arrows labeled in FIG. 3 are arranged to illustrate this point. Programming may be performed in what is termed the "forward" direction and reading may be performed in what is termed the "opposite" or "reverse" direction.
"Reading" an NROM Cell
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing "symmetrical" programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read "asymmetrically", meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323 (in other words, to program the right "bit"), electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right "bit"), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 321 (in other words, to program the left "bit"), electrons flow from right (source) to left (drain). To read the left storage area 321 (in other words, to read the left "bit"), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, U.S. Pat. No. 6,768,165.
Memory Array Architecture Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated "source") of a plurality of memory cells are connected to a first bit line which may be designated "BL(n)", and second diffusions (usually designated "drain") of the plurality of memory cells are connected to a second bit line which may be designated "BL(n+1)". Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be "buried bitline" diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 4 illustrates an array of NROM memory cells (labeled "a" through "i") connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell "e" has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells "e" and "f" (to the right of "e") are both connected to the same word line WL(n). (The gate of the memory cell "d" to the left of "e" is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell "e" is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell "f". In this example, the memory cells "e" and "f" have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called "virtual ground architecture" wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
Modes of Operation
Generally, the modes of operation for any NVM memory cell (either floating gate or NROM) include "program", "erase" and "read". Modes of operation for NROM are now discussed.
Program generally involves injecting electrons into the charge storage areas of the NROM cell, typically by a process known as channel hot electron (CHE) injection. Exemplary voltages to program (by CHE injection of electrons) the right bit (right bit storage area) of an NROM cell,                the left BL (acting as source, Vs) is set to 0 volts        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to +8-10 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the drain (right BL) becomes programmed. To program the left bit storage area, source and drain are reversed—the left bitline serves as the drain and the right bitline serves as the source.
Erase may involve injecting holes into the charge storage areas of the NROM cell, typically by a process known as hot hole injection (HHI). Generally, holes cancel out an electrons (they are electrically opposite), on a one-to-one basis. Exemplary voltages to erase (by HHI injection of holes) the right bit of the NROM cell,                the left BL (acting as source, Vs) is set to float        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to −7 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the drain (right BL) becomes erased. To erase the left bit storage area, source and drain are reversed—the left bitline serves as the drain and the right bitline serves as the source.
Read involves applying voltages to the terminals of the memory cell and, based on subsequent current flow, ascertaining the threshold voltage of the charge storage area within the cell. Generally, to read the right bit of the NROM cell, using "reverse read",                the right BL (acting as source, Vs) is set to 0 volts        the left BL (acting as drain, Vd) is set to +2 volts        the gate (Vg) is set to +5 volts        the substrate (Vb) is set to 0 voltsand the bit storage area above the source (right BL) can be read. To read the left bit storage area, source and drain are reversed—the left bitline serves as the source and the right bitline serves as the drain.Reading the State of the Memory Cells
A memory cell may be programmed to different states, or program levels, determined by the threshold voltage (Vt) of the cell. For a single level cell (SLC), there are two program levels, generally "erase" and "program". For a multi-level cell (MLC) there are more than two program levels. An NVM cell's state may be defined and determined by its threshold voltage (Vt), the voltage at which the cell begins to conduct current. A NVM cell's threshold voltage level is usually correlated to the amount of charge stored in a charge storage region of the cell. Different threshold voltage ranges are associated with different states or program levels of an NVM cell.
Generally, in order to determine the state (program level) of an NVM cell, the cell's threshold level may be compared to that of a reference structure or cell whose threshold level is set, or otherwise known to be, at a voltage level associated with the specific state being tested for. Comparing the threshold voltage of a NVM cell to that of a reference cell is often accomplished using a sense amplifier or similar circuit. Various techniques for comparing an NVM cell's threshold voltage against those of one or more reference cells or structures, in order to determine the NVM cell's state, are well known.
When reading a NVM cell, to determine whether it is at a particular state, the cell's threshold voltage may be compared against that of a reference cell having a reference threshold voltage defined as a "read" level for the specific state. A "read" level is usually set lower than a program verify (PV) level and higher than the erase verify (EV) level in order to compensate for voltage drifts which may occur during operation.
In a "binary" or single level cell (SLC) capable of storing only one bit of information (a logic 1 or a logic 0), only a single read verify (RV) voltage is required, and it may be between the erase verify (EV) and program verify (PV) voltages for the cell.
FIG. 5A is a graph illustrating two states of a "binary" or single level cell (SLC) capable of storing one bit of information per cell (or per charge storage area with an NROM cell), and utilizes only one read verify threshold (RV). Generally, the two states are erased (represented by "1") and programmed (represented by "0"). The horizontal axis is threshold voltage (Vt), increasing from left to right.
Three voltage levels are illustrated in FIG. 5A, these are EV (erase verify), RV (read verify) and PV (program verify). As illustrated, EV is less than RV which is less than PV. A high VT may represent a program state of binary "0", and a low Vt may represent an erase state of binary "1". The binary designations are arbitrary, and may be reversed (high Vt="1", low Vt="0").
FIG. 5A is generalized, and is applicable to a typical floating gate NVM memory cell or a given charge storage area of an NROM cell. The curves represent the threshold voltages (Vts) for a number of cells at the given program level. Typically, there is a distribution, or spread, about a nominal (or average, or center) value. For example,                the center value for "1" equals approximately 3.5 volts        the center value for "0" equals approximately 6.0 volts        EV equals approximately 4.0 volts        RV equals approximately 4.5 volts        PV equals approximately 5.5 volts
FIG. 5B illustrates a situation wherein there are four possible MLC program levels (or states) 11, 01, 00, 10 for each memory cell (or, in the case of NROM, for each storage area of the memory cell). As illustrated, the program level 11 has the lowest Vt, the program level 01 has a higher Vt, the program level 00 has a yet higher Vt, and the program level 10 has a yet higher Vt. The program level 11 may be erase (ERS), which for purposes of this discussion is considered to be a program level, although it is not generally regarded as such.
There are a number of memory cells (or storage areas NROM cells) being programmed, erased and read. In a given array, or on a given memory chip, there may be many millions of memory cells. Programming may typically be performed in blocks, of thousands of memory cells. The different blocks of memory cells are typically located at different logical positions within the array, and at different physical positions on the chip. During (or before) programming, a checksum indicative of the number of cells programmed to each level may be stored, in the block, in the array, on the chip, or external to the chip.
At each program level (and this is also true for the SLC cell of FIG. 5A), there is typically a distribution of threshold voltages, within a range (a statistical spread). In other words, for a given program level, the threshold voltage is not likely to be exactly a unique, precise voltage for all of the memory cells being programmed to that level. Initially, in the act of programming the cell, the voltage may be off a bit, for example as a result of the state of neighboring cells (or the other charge storage area in the same NROM cell). Or, as a result of previous program or erase operations on the same cell, or neighboring cells. Or, as a result of a variety of other factors. And, after programming, the threshold voltage of a cell may change, as a result of programming neighboring cells (or the other charge storage area in the same NROM cell), or a variety of other factors.
Therefore, the threshold voltage (Vt) for a given program level may be more than average in some cells, in others it may be less than average. Nevertheless, in a properly functioning group of cells (such as a block, or an array), there should be a clear distribution of four distinct program levels, such as illustrated. And, the distributions of Vt for each of the program levels should be separated enough from one another so that read positions (RV voltage levels) can be established between adjacent distributions of threshold voltages, such as the following:    RV01 is between EV and PV01, or higher than the highest expected Vt for a cell at state "11" and lower than the lowest expected Vt for a cell at state "01";    RV00 is between PV01 and PV00, or higher than the highest expected Vt for a cell at state "01" and lower than the lowest expected Vt for a cell at state "00"; and    RV10 is between PV00 and PV10, or higher than the highest expected Vt for a cell at state "00" and lower than the lowest expected Vt for a cell at state "10".
For example,                the center value for "11" equals approximately 4.0 volts        the center value for "01" equals approximately 4.4 volts        the center value for "00" equals approximately 4.8 volts        the center value for "10" equals approximately 5.4 volts        EV equals approximately 4.0 volts        RV01 equals approximately 4.4 volts        PV01 equals approximately 4.8 volts        RV00 equals approximately 5.4 volts        PV00 equals approximately 5.6 volts        RV10 equals approximately 6.0 volts        PV10 equals approximately 6.3 voltsAn Aside about Binary Notation, and the Labeling of Program Levels
"Binary" generally means "two". In binary notation, there are only two possible digits, usually referred to as "1" and "0". Many 1s and 0s can be strung together to represent larger numbers, for example:                0000 is zero        0001 is one        0010 is two        0011 is three        0100 is four        1000 is eight        1010 is ten
In the examples above, the binary numbers have four digits each—four "places". For purposes of this disclosure, only two digits will be used. Two digits can represent four numbers. Counting (in binary) typically starts with zero, and counting from zero to three proceeds like this: 00 (zero), 01 (one), 10 (two), 11 (three). Notice, in the transition from 01 (one) to 10 (two), both bits change.
Since it is arbitrary, which program levels represent which digits, notice in FIG. 5B that the program levels appear to be out of sequence, starting with 11 (three), then 01 (one), then 00 (zero), then 10 (two). This sequence is common so that when moving from one program level to the next higher level, both bits do not change—as is the case with the transition from 01 (one) to 10 (two). In FIG. 5B it can be seen that when moving from one program level to another, only one of the bits changes.
Threshold Voltage Drift
The threshold voltage of a NVM cell seldom stays fixed (after it is programmed, or erased). Threshold voltage drift is a phenomenon which may result in large variations of the threshold voltage of a memory cell. These variations may occur due to charge leakage from the cell's charge storage region, temperature changes, and due to interference from the operation of neighboring NVM cells.
The drift in threshold voltage of a memory cell is well known, and is discussed for example in U.S. Pat. Nos. 6,992,932 and 6,963,505 discloses read error detection in a NVM array, and may hereinafter be referred to as the "moving reference patent(s)". These deviations in a cell's threshold voltage (Vt) may be either in the upward or downward direction, and may vary from cell to cell.
Variation of the threshold voltage of memory cells may lead to false reads of the cell's state and may further result in the corruption of the data in the memory array. Voltage drift is especially problematic in MLC cells (see FIG. 5A) where the Vt regions or sub-ranges associated with each programmed state are relatively smaller than those for a typical binary or SLC cell (see FIG. 5B).
It is known that, in order to reduce data loss and data corruption due to drift in the threshold voltages of the cells of a NVM array, threshold voltage drift of cells in the NVM array should be compensated for.
The moving reference patents disclose that, for a given NVM array, it is known to provide one or a set of reference cells whose references threshold voltages are offset from defined verify threshold levels by some value related to the actual voltage drift experienced by the NVM cells to be read. There is a well understood need for an efficient and reliable method of determining a set of reference voltage levels which may accommodate variations in the threshold voltages of cells of an NVM array, and of established reference cells with the determined reference voltages.
Generally, at least a subset of cells of a NVM block (or array) may be read, and the number of cells found at a given state (such as logic "0", or "00") associated with the block may be compared to one or more check sum values obtained during programming of the at least a subset of cells. A Read Verify threshold reference voltage associated with the given program state or associated with an adjacent state may be adjusted based on the result of the comparison.
Generally, the idea presented in the aforementioned moving reference patents is to select (establish) a set of reference cells (from N sets) to be used in operating an NVM block or array. For example, each set of test reference cells may have reference voltages at least slightly offset from each other set of test reference cells. For example, each set of test reference cells may be incrementally offset, such that each set may be associated with a series of threshold voltages that are slightly higher than a corresponding series of threshold voltages associated with the previous set of test reference cells (excluding the first set). As a further example, if the first set of test reference cells includes cells having reference voltages; Cell 1=4.2V, Cell 2=5.2V, Cell 3=6.2V, the second set may include cells having reference voltages offset, such that; Cell 1=4.3V, Cell 2=5.3V, Cell 3=6.3V.
A set of reference voltages associated with the selected test set may be obtained by a controller. The set of reference voltages may be recorded, for example in an error rate table. The controller may instruct an offset circuit to offset the threshold voltages of one or more of the reference cells in a set of global reference cells in accordance with the set of reference voltages. The controller may instruct the offset circuit to offset the reference voltages of one or more of the global reference cells in the set of global reference cells, such that the threshold voltages of the set of global reference cells may be substantially equal to the threshold voltages of the selected test set.
The offset circuit and the set of global reference cells may be substituted with a bank of reference cells (not shown). The bank of reference cells may include two or more reference cells each reference cell in the bank being incrementally offset from the other reference cells in the bank. For example, each reference cell in the bank may have a threshold voltage that is slightly higher than the threshold voltage of the previous reference cell (excluding the first reference cell).
Once selected, the selected set of test reference cells may be used to determine which of the reference cells in the bank of reference cells is to be used for establishing an operating set of reference cells. The selected set of reference cells from the bank of reference cells may be selected such that the selected set from the bank may have reference voltages that are substantially equal to those of the selected test set. Thus, the selected set of reference cells from the bank may provide a set of operating reference cells having reference voltages substantially equal to those of the selected test set. The set of operating reference cells may be used to operate the NVM array.
Determining that Shifting RV is Necessary
Prior to or during the programming of a set of cells in a NVM array, the number of cells to be programmed to each of one or more logical or program states associated with the set of cells may be counted, and may be stored, for example in a check sum table. The number of cells to be programmed to, up to and/or below each logical or program state may be counted and/or stored in a table which is either on the same array as the set of NVM cells or in memory on the same chip as the NVM array.
Upon the reading of the set of programmed cells, the number of cells found to be at a given logical or program state may be compared against either corresponding values stored during programming (such as the number of cells programmed to a given state) or against a value derived from the values stored during programming (such as the number of cells programmed at or above the given state, minus the number of cells programmed to or above an adjacent higher logical state).
If there is a discrepancy between the number of cells read at a given state and an expected number based on the values determined/counted/stored during programming, a Read Verify reference threshold value associated with the given program state may be adjusted upward or downward to compensate for the detected error. The read verify level of an adjacent logical state may also be moved upward or downward in order to compensate for detected read errors at a given state.
For example, if the number of cells found (read) in a given program state is below an expected value, either the Read Verify reference voltage associated with that given state may be reduced, or if there is found that the number of cells read above the given state exceeds an expected number, the Read Verify reference associated with a logical state higher and adjacent to the given state may be raised. Conversely, if the number of cells found. (e.g. read) in a given program state is above expectations, either the Read Verify reference voltage associated with that given state may be increased, or if there is found that the number of cells read above the given state is below an expected number, the Read Verify reference associated with a logical state higher and adjacent to the given state may be lowered. Thus, Read Verify reference voltages for a set of cells may be selected such that the number of cells found/read in each of the states associated with the set may be substantially equal to the a number either read from or derived from the values counted during programming of the set of cells, which values may have been stored in a check sum table.
The check sum table may reside on the same chip as the set of NVM cells, and a controller may be adapted to perform the above mentioned error detection and Read Verify reference value adjustments. The check sum table may either be stored in the same NVM array as the set of NVM cells, or on some other memory cells residing on the same chip as the NVM array, for example in a register or buffer used by the controller during programming and/or reading. Specialized error coding and detection circuits may be included with a controller on the same chip and the NVM array to be operated.
During the reading of the cells from the programmed set of cells, either the controller or some other error detection circuit may compare the number of cells counted in each program state during reading with the correspond check sum values stored during or prior to programming. For example, if the number of cells found in a given program state exceed the value derived from the check sum values, the read verify (RV) threshold value associated with that given program state may be raised or the Read Verify reference level associated with the adjacent higher state may be lowered. Conversely, if the number of cell's found in a given program state is below the expected number, either the read verify threshold value associated with the given program state may be lowered, or the read verify threshold value associated with the next higher adjacent state may be raised.
If the number of cells found (read) in a given program state is below an expected value, either the Read Verify reference voltage associated with that given state may be reduced, or if there is found that the number of cells read above the given state exceeds an expected number, the Read Verify reference associated with a logical state higher and adjacent to the given state may be raised. Conversely, if the number of cells found (e.g. read) in a given program state is above expectations, either the Read Verify reference voltage associated with that given state may be increased, or if there is found that the number of cells read above the given state is below an expected number, the Read Verify reference associated with a logical state higher and adjacent to the given state may be lowered.
Thus, Read Verify reference voltages for a set of cells may be selected such that the number of cells found/read in each of the states associated with the set may be substantially equal to the a number either read from or derived from the values counted during programming of the set of cells, which values may have been stored in a check sum table.
The steps described hereinabove may be repeated as part of an iterative process until the number of cells read in each program state substantially corresponds to the number of cells expected in each state based on data recorded during programming. The process may start with the checking of cells programmed to the highest logical state, or cells programmed to several different states may be checked in parallel.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at "Non Volatile Memory Technology", 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.

Rd algorithm improvement for NROM technology


An anti-backbend chain comprises a plurality of alternate chain links joined by respective chain hinges, a spring element comprising at least a first spring arm being provided. The spring element rests on a chain hinge and the first spring arm extends to a neighbouring chain hinge and is movably in contact therewith under the biasing force of the spring element, so as to obstruct bending of the anti-backbend chain in a first pivot direction. In addition, an anti-backbend chain drive is provided, in particular a chain drive for driving automated door or gate systems.

A chain with anti-backbend properties on the first and second sides is known from DE 10 2005 099 154 A1. In the case of this anti-backbend push chain for power transmission in a chain drive, the chain elements are pivoted radially inwards on a chain drive wheel. The hinge openings of the chain link plates are implemented as elongate holes and have a certain amount of play relative to the hinge pins, so that the effective chain pitch in the push strand is reduced. In addition, the ends of the hinge pins have rollers provided thereon, which guide the anti-backbend chain in a separate roller rail guide in the push strand. The hinge openings configured as elongate holes additionally allow a reliable contact of the stiffening contours formed on the end faces of the chain link plates in the push strand.
DE 1 450 699 C1 discloses a further anti-backbend chain. The outer link plates of the outer chain links and the inner link plates of the inner chain links have provided between them stiffening link plates, which are each arranged on a hinge pin and provided with a projection protruding in a direction of chain travel, the end faces of said projection being configured as support surfaces. One end face is configured as a protrusion and the other end face as a recess. The protruding and recessed end faces of the stiffening link plates stiffen the chain in a first pivot direction, whereas the chain remains flexible in the other, second pivot direction. Therefore, this chain runs in a push strand in a guide means so as to prevent, for power transmission through this anti-backbend chain, bending of the chain in the second pivot direction.
The prior art comprises a plurality of additional, very different structural designs of anti-backbend chains. Reference DE 1 180 318 B, for example, shows an anti-backbend chain drive with alternate inner and outer chain links, the contour of the chain link plates being provided with an end face-side stiffening means and the chain being guided between the chain link plates in a guide channel in a push strand. DE 2001 002 310 U1 discloses an anti-backbend chain with identical fork-shaped chain links provided with interengaging stiffening contours on their rear sides. In addition, EP 1 744 079 A1 discloses a chain with anti-backbend properties on the first and second sides, in the case of which the end faces of the chain link plates have complementary stiffening contours, at least one hinge opening being configured as an elongate hole so as to allow in the push strand a reliable interengagement of the end face-side stiffening contours by means of a reduced chain pitch.
Reference DE 1 046 422 B1 discloses a further anti-backbend plate link chain comprising a locking mechanism, which prevents the chain links from being pivoted relative to one another and which is disengaged by means of a lateral guide during deflection. A further locking mechanism of an anti-backbend chain is shown in DE 20 2007 002 767 U1, where an arresting element, which is pivotable transversely to the direction of chain travel, is disengaged by means of a guide rail.
The anti-backbend chains and chain drives known in the prior art make use of very different concepts and constructions so as to guarantee stiffening of the chain in the push strand and allow simultaneously deflection of the chain around a chain drive wheel. Many of the known anti-backbend chains are joined by additional measures after stiffening behind the chain drive wheel in the push strand or the chains are locked by means of arresting mechanisms in the second or in both pivot directions. Although many of the anti-backbend chains which have hitherto been used in the prior art proved to be very useful, the mechanisms used are partly complex stiffening and/or locking mechanisms as well as intricate constructions that often require additional space.
JP H07 172786 A deals with a lift chain for a forklift truck whose chain links can be biased relative to one another by means of a leg spring. Every second hinge pin has attached thereto such a leg spring, the two legs of said spring resting on the respective neighboring pin. The chain is therefore always forced back from a stretched position to the folded position.
US 2009/124445 A1 discloses a toothed chain comprising wire spring elements between the chain links. These wire spring elements are intended to make the chain resistant to bending.
GB 12985 A discloses a roller chain. Some of the chain links have upwardly protruding projections having a leaf spring element arranged thereon, which imparts to the chain a certain degree of spring elasticity.


A method and container for reducing fuming of asphalt in a heated vessel, including placing asphalt in a heated vessel to heat the asphalt to a molten state, adding a blanket material to the asphalt, the blanket material being substantially insoluble in the molten asphalt to form a skim thereon to reduce fuming therefrom.

This invention relates in general to asphalt materials for use in roofing, paving and other applications. More particularly, this invention relates to a container and method to produce such a container, for reducing fumes emitted from a vessel of the molten asphalt. The invention can be useful for providing asphalt for use in locations where fumes from the molten asphalt are a concern.
Asphalt from processing and terminalling facilities is transported to end users in one of several ways, including direct piping of molten asphalt to nearby customers, shipping in molten form via tanker truck, railcar and barge, and shipping in solid form in individual packages. The packages are used primarily by building contractors as a source of asphalt for roofing applications. The contractor typically places the solid asphalt in a heated kettle to melt the asphalt for use. Asphalt shipped in molten form is also usually further heated in a kettle prior to use.
A problem associated with such heated kettles of molten asphalt is that they can emit significant amounts of fumes. The fumes can be unsightly, and an irritant to workers and others in the surrounding area. Accordingly, it would be desirable to reduce the amount of fumes normally emitted from a kettle or other vessel of molten asphalt.
It would also be desirable to reduce fuming and odors without substantial modification of the processed or raw asphalt. By contrast with known polymermodified asphalt compositions, which are highly modified materials where the polymer is used, e.g., to impart elongation properties, an asphalt without such modification is desired for many applications.
It would also be desirable to reduce fuming and odors of molten asphalt while permitting for convenient, user-tailorable enhancement or alteration of the asphalt properties.
Furthermore, it would be desirable to produce a low-fuming asphalt in a convenient package. Individual packages of asphalt are typically formed at conventional asphalt processing facilities by pouring molten asphalt into containers made of a metal bottom and paper cylindrical sidewalls. The asphalt is typically poured at temperatures of about 177xc2x0 C. and the packages are allowed to cool for up to 24 hours prior to shipping.
The above objects as well as other objects not specifically enumerated are achieved by adding a blanket material to a kettle of molten asphalt to form a skim layer.
In a preferred embodiment, a method for reducing fuming of asphalt in a heated vessel includes placing asphalt in a heated vessel to heat the asphalt to a molten state. A blanket material is added to the asphalt, the blanket material being substantially insoluble in the molten asphalt to form a skim thereon to reduce fuming therefrom.

Method of reducing fumes from a vessel of molten asphalt

Owens Corning Fiberglas Technology, Inc.


The present invention provides an image display system implemented with a micro-electromechanical system (MEMS) device formed and supported on a substrate functioning as a spatial light modulator wherein the MEMS device further comprises a drive circuit disposed on the substrate; a micromirror functioning as a movable electrode supported on a deflectable hinge extended from the substrate; a stationary electrode disposed on the substrate and connected to the drive circuit to receive signals therefrom, wherein the stationary electrode comprises a first electrode, a second electrode and an insulation layer, wherein the insulation layer is disposed between the first electrode and second electrode.

1. Field of the Invention
The present invention relates to an image display system implemented with a mirror device manufactured as a MEMS device to function as a spatial light modulator (SLM). More particularly this invention relates to the mirror device implemented in an image display system manufactures as a MEMS device wherein each micromirror of the mirror device comprises a layered electrode.
2. Description of the Related Art
Even though there are significant advances of the technologies for implementing an electromechanical mirror device as a spatial light modulator (SLM) in recent years, there are still limitations and difficulties when current technologies according to the state of the art are applied to provide a high quality image. Specifically, when the images are digitally controlled, the image quality is adversely affected due to the limitation that the images are not displayed with sufficient number of gray scales.
An electromechanical mirror device is drawing a considerable interest and commonly employed as a spatial light modulator (SLM) in the image project apparatuses. The electromechanical mirror device is typically implemented with a "mirror array" comprising a large number of mirror elements. In general, the number of mirror elements may range from 60,000 to several millions of micromirror pieces are manufactured as two-dimensional array on a surface of a substrate in an electromechanical mirror device.
Referring to FIG. 1A for an image display system 1 disclosed in U.S. Pat. No. 5,214,420 that comprises a screen 2. The display system 1 further includes a light source 10 to project an illumination light for displaying images on the screen 2. The illumination light 9 from the light source is further focused and directed toward a lens 12 by a mirror 11. Lenses 12, 13 and 14 function together as a beam culminator to culminate light 9 into culminated light 8. A spatial light modulator (SLM) 15 is controlled on the basis of data input by a computer 19 via a bus 18 to selectively redirect portions of light from a path 7 toward an enlarger lens 5 and onto screen 2. The SLM 15 is implemented with a mirror array comprising large number of mirror 33 each includes a deflectable reflective element shown as elements 17, 27, 37, and 47 depicted in FIG. 1B. Each mirror 33 is connected by a hinge 30 on a surface 16 of a substrate in the electromechanical mirror device as shown in FIG. 1B. When the element 17 is in one position, a portion of the light from the path 7 is redirected along a path 6 to lens 5 where it is enlarged or spread along the path 4 to impinge on the screen 2 to display an illuminated pixel 3. When the element 17 is in another position, the light is redirected away from screen 2 and hence the pixel 3 is displayed as a dark pixel on the display screen 2.
The mirror device comprises a plurality of mirror elements to function as spatial light modulator (SLM) wherein each mirror element comprises a mirror and electrodes. A voltage applied to the electrode(s) generates a coulomb force between the mirror and the electrode(s) to control the mirror to tilt to an inclined angle. According to a common term used in this specification, the mirror is "deflected" to an angular position for describing the operational condition of a mirror element.
When a voltage applied to the electrode(s) controls the mirror to deflect to a controlled angular position, the deflected mirror also reflects an incident light to a controlled direction. The direction of the reflected light is therefore controlled in accordance with the deflection angle of the mirror and that in turn is controlled by a voltage applied to the electrode. The present specification refers to a state of the mirror as an ON state when the mirror reflects substantially the entirety of an incident light a projection path designated for image display and as an OFF state when the mirror reflects the incident light to a direction away from the designated projection path for image display.
Specifically, FIG. 1C exemplifies a control circuit for controlling a mirror element according to the disclosure in the U.S. Pat. No. 5,285,407. The control circuit includes a memory cell 32. Various transistors are referred to as "M*" where "*" designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5 and M7 are p-channel transistors; while transistors M6, M8, and M9 are n-channel transistors. The capacitances C1 and C2 represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a, which is based on a typical Static Random Access switch Memory (SRAM) design. The transistor M9 connected to a Row-line receives a data signal via a Bit-line. The memory cell 32 written data is accessed when the transistor M9 which has received the ROW signal on a Word-line is turned on. The latch 32a consists of two cross-coupled inverters, i.e., M5/M6 and M7/M8, which permit two stable states, that is, a state 1 is Node A high and Node B low, and a state 2 is Node A low and Node B high.
The control circuit, as illustrated in FIG. 1C, controls the micromirrors to switch between two states, and the control circuit drives the mirror to oscillate to either an ON or OFF deflection angle (or position) as shown in FIG. 1A.
The minimum intensity of light controllable to reflect from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally controlled image display apparatus, is determined by the least length of time that the mirror is controllable to be held in the ON position. The length of time that each mirror is controlled to be held in an ON position is in turn controlled by multiple bit words.
For controlling deflectable mirror devices, the PWM applies data to be formatted into "bit-planes", with each bit-plane corresponding to a bit weight of the intensity of light. Thus, if the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit-planes. Then, each bit-plane has a 0 or 1 value for each mirror element. According to the PWM control scheme described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled according to bit-plane values corresponding to the value of each bit during one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed for 1 time period.
When adjacent image pixels are displayed with a very coarse gray scale caused by great differences in the intensity of light, thus, artifacts are shown between these adjacent image pixels. That leads to the degradations of image quality. The image degradations are especially pronounced in the bright areas of image where there are "bigger gaps" between of the gray scales of adjacent image pixels. The artifacts are generated by technical limitations in that the digitally controlled image does not provide a sufficient number of the gray scale.
As the mirrors are controlled to operate in a state of either ON or OFF, the intensity of light of a displayed image is determined by the length of time each mirror is in the ON position. In order to increase the number of gray scales of a display, the switching speed of the ON and OFF positions for the mirror must be increased. Therefore the digital control signals need be increased to a higher number of bits. However, when the switching speed of the mirror deflection is increased, a stronger hinge for supporting the mirror is necessary to sustain the required number of switches between the ON and OFF positions for the mirror deflection. In order to drive the mirrors with a strengthened hinge, a higher voltage is required. The higher voltage may exceed twenty volts and may even be as high as thirty volts. The mirrors produced by applying the CMOS technologies are probably not appropriate for operating the mirror at such a high range of voltages, and therefore DMOS mirror devices may be required. In order to achieve a higher degree of gray scale control, more complicated production processes and larger device areas are required to produce the DMOS mirror. Conventional mirror controls are therefore faced with a technical problem in that accuracy of gray scales and range of the operable voltage have to be sacrificed for the benefits of a smaller image display apparatus.
In the meantime, there are reference materials related to the present disclosure.
U.S. Pat. No. 6,744,550 has disclosed a layered electrode having a step.
U.S. Pat. No. 6,552,840 has disclosed an electrode having a step or a slope surface.
U.S. Pat. No. 5,673,139 has disclosed a vertical silicon hinge.
U.S. Pat. No. 6,128,121 has disclosed a configuration in which electrodes are respectively placed on both sides of a vertical silicon hinge.
U.S. Pat. No. 7,068,417 has disclosed a configuration in which electrodes are respectively placed on both sides of a vertical silicon hinge.
U.S. Pat. No. 7,022,249 has disclosed a configuration in which a drive electrode and a mirror abut on each other.
U.S. Pat. No. 6,735,008 has disclosed a structure in which electrodes, each of which is constituted by an insulation layer and an electric conductor, are respectively placed on both sides of a vertical hinge.
U.S. Pat. No. 5,447,600 has discloses an electrode, on which a mirror abuts, and a drive electrode.
U.S. Pat. No. 6,914,709 has disclosed the structure of an electrode of a mirror.
U.S. Pat. No. 7,079,301 has disclosed the structure of an electrode of a mirror.
U.S. Pat. No. 6,912,336 has disclosed a metal-deposited electrode.
U.S. Pat. No. 6,962,419 has disclosed an electrode having different heights depending on the deflecting direction of a mirror.
U.S. Pat. No. 7,206,110 has disclosed a configuration using a metallic layer for shielding light.
U.S. Pat. No. 5,818,095 has disclosed a configuration using a metallic layer for shielding light.
However, these disclosures have not yet provided an effective configuration and method to overcome the technical limitations encountered in the conventional image display systems. Therefore, a need still exists in the art of image display systems applying digital control of a mirror array as a spatial light modulator to provide new and improved systems such that the above-discussed difficulties can be resolved.

Mirror device and MEMS device comprising layered electrode


A disclosed image forming apparatus includes an image scanning unit configured to generate image data by converting light reflected from an optically scanned printed page into electrical signals; an interface configured to receive image data from an external apparatus; an expansion bus to which the image scanning unit and the interface are connected; a bus control unit configured to control the expansion bus; an image data storage unit configured to store the image data; at least one image processing unit connected to the expansion bus and configured to perform an image processing operation on the image data; a task management unit configured to send an image processing request to the image processing unit; and an image writing unit connected to the expansion bus and configured to print the image data on which the image processing operation has been performed by the image processing unit.

1. Field of the Invention
The present invention generally relates to an image forming apparatus, an image processing unit, an image processing method, and a recording medium having an image processing control program, and more particularly relates to an image forming apparatus such as a digital copier, scanner, printer, facsimile, or a multifunction copier, and an image processing unit, image processing method, and recording medium having an image processing control program used in such an image forming apparatus.
2. Description of the Related Art
A multifunctional image forming apparatus having functions of a digital copier, printer, scanner, facsimile, and the like has been proposed (see, for example, patent document 1).
FIG. 20 is a schematic diagram illustrating an exemplary hardware configuration of a conventional image forming apparatus. In the conventional image forming apparatus shown in FIG. 20, functions of a scanner, printer, image processing unit, and the like are combined into an image processing engine 1000; and the image processing engine 1000 and a controller 1001 are connected via a general purpose bus 1002. The controller 1001 includes an operations display unit that is a user interface, an image data storage unit for storing processed image data, a communication unit for communication with external apparatuses, and a CPU that executes software programs for controlling the above units.
In the exemplary hardware configuration shown in FIG. 20, the controller 1001 communicates with an external apparatus and sends an image processing request to the image processing engine 1000; and the image processing engine 1000 performs the requested image processing. The controller 1001 stores processed image data in the image data storage unit.
As described above, in the exemplary hardware configuration, the controller 1001 communicates with an external apparatus and sends an image processing request to the image processing engine 1000 and a dedicated hardware unit of the image processing engine 1000 performs the requested image processing. Such a configuration improves individual processing efficiencies of the image processing engine 1000 and the controller 1001.
[Patent document 1] Japanese Patent Application Publication No. 2002-359743
The exemplary hardware configuration as shown in FIG. 20 has an advantage that since the image processing engine 1000 performs image processing, the controller 1001 is relieved of image processing load. However, since the image processing engine 1000 and the controller 1001 operate separately, it is difficult to make them interact to perform complicated image processing.
Especially, after an image processing operation is performed on image data and the image data are stored in the image data storage unit, it is difficult to perform another image processing operation on the image data. Thus, with a conventional image forming apparatus, only limited combinations of image processing operations are available.
Image processing operations, such as gamma processing, skew correction, and filtering, in an image processing apparatus are normally performed by hardware devices such as an application specific integrated circuit (ASIC) and a digital signal processor (DSP). An ASIC has a custom-designed circuit that provides, for example, a specific image processing function. Changing the image processing function of an ASIC requires changing the hardware itself. Therefore, in practice, it is difficult to change the function of or to add a function to an ASIC. An image processing function provided by an ASIC or DSP of the image processing engine 1000 may be implemented by software. However, since image data are stored in the image data storage unit and managed by the controller 1001, it is necessary to make the image processing engine 1000 and the controller 1001 interact to implement such an image processing function by software.

Image forming apparatus, image processing unit, image processing method, and recording medium having image processing control program with task management


The apparatus for cleaning a wafer includes an energy concentration relieving member positioned at the side of the wafer. An elongated portion of a probe extends over and substantially parallel to the wafer surface. A vibrator is attached to a rear end of the probe for vibrating the probe such that the elongated portion transfers acoustic vibrational energy to the wafer and dislodges debris.

1. Field of the Invention
The present invention relates to an apparatus and method for cleaning a wafer used in the manufacture of a semiconductor device.
2. Description of the Related Art
Recently, numerous methods for cleaning a wafer using high frequency acoustic energy, such as megasonic energy, have been introduced. An apparatus for cleaning a semiconductor wafer using megasonic energy removes pollutants (e.g., particles) from a wafer surface by providing megasonic energy through the cleaning fluid. One example of an apparatus for cleaning a semiconductor wafer that uses high frequency acoustic energy is the GOLD FINGER cleaning apparatus introduced by Verteq, Inc., which is disclosed in U.S. Pat. No. 6,039,059 (issued on Mar. 21, 2000 to Mario E. Bran, et al.) and hereby incorporated by reference in its entirety. Although, the apparatus for cleaning a semiconductor wafer by providing megasonic energy effectively removes particles from a wafer surface, patterns formed on the wafer are sometimes damaged during the cleaning process. Damage to the patterns includes, for example, lifting of the patterns. In particular, patterns can be severely damaged on the edge of the wafer.
It is known that damage to the patterns occurs due to a concentration of megasonic energy or vibrational energy of fluids. As design rules required for a semiconductor device become more narrow, damage to the patterns can increase. For example, if a line width of the pattern is less than 0.12 μm, damage to the patterns due to the cleaning process can increase.

Apparatus and method for cleaning a semiconductor wafer


Wheel disc, comprising a radially outer circular assembling part, a radially inner fixing and centering part with a bearing region comprising a given number of fixing apertures and ending radially inwardly with a centering vent, and arms connecting the inner and outer parts, each arm being disposed substantially opposite to one of the fixing apertures and the radially inner free edges of the radially outer circular part defining with the lateral free edges of the arms perforations, in which, in order to reinforce each arm mechanically, a pocket is housed, set back axially inwards relative to the outer face of the disc and in which a yoke connects each arm to the centering vent.

The invention relates to a motor vehicle wheel disc with arms, in particular for passenger car, formed in one piece from embossed sheet metal, which represents an excellent compromise in terms of weight, cost, style or freedom of possible added styling (decorative wheel cover for example).
In the designing of a sheet metal wheel for a motor vehicle, the general aim is to optimise the weight and cost of such a product. The development of embossing techniques, numeric simulation means, and materials has led to great progress over the last few years. However, the majority of products has remained within the concept of a substantially axisymmetric disc (i.e. one whose cross-sectional profile is virtually fixed in form), comprising perforations and sometimes embossing in the upper part.
This type of profile does not give the product a very enhanced style or image, which explains in most cases why manufacturers resort to a decorative wheel cover placed on the product when it is mounted on the vehicle.
One can count several attempts to create style directly from the sheet metal forming the wheel disc by forming deep embossed areas forming stiffeners and/or a particular assembly of the disc with the rim (under-seat, "full-face" assembly (i.e. disc whose radially outer edge includes the outer flange and seat of the rim), with the rim welded at the end, etc.) and sometimes associated with effects connected to painting. These attempts have not yet led to generalisation for reasons of excessive weight or difficulties in execution.
In general, the market for styled wheels for passenger cars is confined to the use of aluminium alloys. The process of manufacture (moulding, forging etc.) of these discs allows very broad freedom of style at reasonable weights, but has the disadvantage of being 4 to 8 (even 10) times more expensive.
The specification of DE 201 08 995-U discloses a wheel whose disc is formed from a single piece of embossed sheet metal, with an outer face and an inner face. This disc has a radially outer circular assembling part intended to be connected to a rim, a radially inner part for fixing and centering to a wheel hub with a bearing area having a given number of fixing apertures and ending radially inwardly with an edge which is turned axially outwardly or centering vent (aperture), and spokes connecting the inner and outer parts, each arm being disposed substantially opposite to one of the fixing apertures and the radially inner free edges of the radially outer circular part defining perforations with the free lateral edges of the arms. This disc has a substantially circular, plane bearing region and each arm comprises two lateral stiffening elements which extend radially from the bearing area to the radially outer circular assembly part and are disposed on either side of an intermediate strip axially set back towards the interior of the disc.
Although freedom of styling either bare or with an attached part (decorative wheel cover for example) is apparently obtained, such a disc has the disadvantage of requiring a relatively thick sheet metal to be able to withstand the forces to which it is subjected during operation, in particular in the joining region between the arms and the radially inner part for fixing and centering the disc.
Hereinafter:                the "outer face" of the disc will refer to the surface of revolution generated by rotation about the axis of rotation of the disc of the regions of the disc disposed axially outermost;        the "internal face" of the disc, to the side of the disc oriented inwards, in particular the internal face of the bearing region is intended to come into contact with the outer surface of the wheel hub to which the disc is to be fixed;        and the "external face" of the disc, to the side of the disc oriented outwards, which side is visible when the wheel is mounted on the vehicle.

Motor vehicle wheel disc, in particular for passenger car


The invention relates to an M2M device comprising a communication unit and a SIM card, the said SIM card comprising a controller or microcontroller (A), characterized in that the SIM card comprises at least one sensor (B; C), the said at least one sensor being a sensor selected from the group consisting of a temperature sensor, a strain sensor, a movement sensor, a displacement sensor, an inertia or acceleration sensor, a sound sensor, a pressure sensor, an impact sensor and a vibration sensor, the said controller or microcontroller (A) comprising an element for deactivating at least some of its functions following the receipt from the said at least one sensor (B,C) of at least one signal indicating that an environment status value is outside a predetermined range, thus preventing the malicious use of the said SIM card.

This invention generally relates to a SIM card for M2M applications and an M2M device.
The term M2M commonly designates "machine to machine communication". For example, M2M technology is designed to allow machines, industrial units, vehicles or generally any piece of equipment to communicate with any other machine, industrial unit, vehicle, device, server or generally any remote piece of equipment, with no human intervention, for example for applications relating to remote surveillance, telemetry, alerts, vehicle fleet management, assistance to persons etc.
Thanks to the growth in wireless communication technology (GSM, GPRS, EDGE, Wi-Fi etc.), M2M has now become an extremely efficient and competitive solution, for instance for managing remote machine bases. Where work in the field was once indispensable for monitoring, controlling or maintaining machines distributed in different locations, the integration of network connectivity and web technologies has made it possible to manage those machines remotely.
As part of the use of wireless telecommunications network(s) such as those of the GSM and GPRS types, the M2M device used typically comprises a communication unit (which in turn comprises means for processing baseband and radiofrequency signals) and a SIM card.
Conventionally, in a wireless communication terminal such as a GSM terminal for example, the SIM card is an external element and is removable from the communication terminal with which it is associated. Indeed, its task is to identify a "subscriber", who may need to change terminals without wanting to change their identifier associated with the SIM card. The card is placed in a space provided in the communication device and is inserted in that space by sliding it into a slot or opening provided for that purpose. It may be changed physically during the life of the communication device, for instance in order to obtain more functions or to change operators.
During the production of SIM cards, in a stage called the personalisation of the SIM card, the SIM card manufacturer puts in place in the SIM card functions that have been required by the operator and stores the parameters of the operator (such as for instance secret keys, encryption algorithms etc.)
As part of M2M applications, communication units are often embedded in equipment and are thus not easily accessible.
M2M devices are devices that may be left without particular human monitoring as they are integrated into equipment or machines that are away from all human presence and are thus liable to undergo degradations aimed at stealing the SIM card in order to reuse the mobile telephone subscription associated with it fraudulently.

Method for preventing the malicious use of a SIM card inserted in an M2M device and M2M device


An optical transmission medium bend working device that reduces bending loss of an optical transmission medium includes: an arc-discharge electrode that partially and sequentially heats a bend working area of a tape core wire in an up-down direction, the tape core wire extending in the up-down direction with a distal end thereof being located on a lower side, the bend working area being located above the distal end; a core wire holding unit that holds a portion of the tape core wire located above the bend working area; and a bending arm that applies force to the tape core wire in a state where the bend working area is heated to bend the tape core wire at the bend working area.

With regard to techniques for shaping an optical transmission medium such as an optical fiber, techniques disclosed in Patent Literature 1 and Patent Literature 2 are known, for example.
Patent Literature 1 discloses a technique of bending an optical transmission medium by pressing a portion of an optical transmission medium extending in a horizontal direction against a shaping jig disposed under the optical transmission medium while heating a portion of the optical transmission medium so that the optical transmission medium curves around the shaping jig.
In addition, Patent Literature 2 discloses a technique of bending an optical transmission medium extending in a horizontal direction by heating a portion of the optical transmission medium using arc discharge.

Optical transmission medium bend working device and optical transmission medium bend working method