Disclosed is a method for manufacturing a vertical cavity, surface-emitting laser. The method includes growing a distributed Bragg reflector having at least 10 layers of alternating composition on a gallium arsenide substrate. The growth surface of the substrate is tilted by an angle of 1.degree.-7.degree. from the orientation of a (100) surface toward the orientation of a (111)A surface. This results in improved reflectivity of the DBR.

Semiconductor heterojunction lasers are usefully made by processes that include the epitaxial growth of successive layers of III-V materials of varying composition on a III-V substrate, typically, a gallium arsenide or indium phosphide substrate. Such layers will herein be understood to extend horizontally, and the axis perpendicular to the layers will be understood to extend vertically. Such lasers may generally be classified into two groups, namely edge-emitting lasers and surface-emitting lasers. Edge-emitting lasers emit laser radiation in a substantially horizontal direction, whereas surface-emitting lasers emit laser radiation in a substantially vertical direction. A surface-emitting laser is said to have a vertical cavity (and is thus referred to as a vertical-cavity surface-emitting laser, or VCSEL) if the optical cavity is bounded by a pair of horizontally-extending reflective layers.
Laser radiation can be coupled out of the tops or bottoms of VCSELs without the need for structures, such as 45.degree. mirrors, for turning optical beams. As a consequence, VCSELs are regarded as desirable for applications involving optically emissive arrays and for optical integration, where they are packed side-by-side with other components or devices and access to the side portions of the laser elements may be precluded.
As for most lasers, it is generally desirable for one of the reflectors bounding the laser cavity to have high reflectivity, approaching 100%, at the lasing frequency. The other reflector, which functions as the exit mirror, desirably has a reflectivity that is less than 100%, but still relatively high. For example, the reflectivity of the exit mirror typically lies in the range 95%-99.9%. One useful method for forming a reflective layer structure is to grow a sequence of thin layers of alternating composition such that constructive interference occurs between reflections from the various included interfaces. This will take place if, for example, the thickness of each thin layer is at least approximately equal to one-fourth the wavelength corresponding to electromagnetic radiation of the laser frequency propagating in that layer. The resulting strong reflection (at the laser frequency) is referred to as a Bragg reflection, and a structure comprising such alternating layers is referred to as a distributed Bragg reflector (DBR).
For a given choice of layer compositions and a given laser frequency, the reflectivity of a DBR can be adjusted by appropriate selection of the number of layers. Thus a DBR having a relatively large number of layers can be used for the mirror of greater reflectivity, and a DBR having a smaller number of layers can be used for the mirror of lesser reflectivity. Moreover, a DBR can be used to enhance the reflectivity of a metallized reflective surface. Thus, for example, the mirror of greater reflectivity may comprise a metal layer and a DBR contiguous to the metal layer. In such a reflective structure, referred to as a hybrid metal DBR reflector (or, simply, a hybrid DBR), a relatively small number of semiconductor layers may suffice to provide reflectivity near 100%.
Significantly, because the active layer of a VCSEL is short, the gain in the laser cavity is generally limited by the reflectivity of the reflective structures. (This point is discussed, for example, in J. Faist, et al., "Characterization of GaAs/(GaAs).sub.n (AlAs).sub.m surface-emitting laser structures through reflectivity and high-resolution electron microscopy measurements," J. Appl. Phys. 66(1989) pp. 1023-1032.) Thus, in order to assure desirable levels of laser performance (e.g., relatively low values of the threshold current), it is important to provide reflective structures of high reflectivity. In particular, it is generally desirable to provide layers in the Bragg structure that are of high quality, i.e., that are substantially planar and of substantially uniform thickness, and that form sharp interfaces with neighboring layers. Roughness of the layers, i.e., spatial variations in thickness or spatially varying deviations from planarity, is capable of scattering laser radiation and thus decreasing the reflectivity.
As is evident from the foregoing discussion, DBRs are desirable as reflective structures because the reflectivity of such structures is readily adjusted by appropriate design. DBRs are also desirable because they can be designed to offer relatively low series resistivity to the flow of electric current through the laser. A VCSEL incorporating a DBR structure and a hybrid metal DBR reflector is described, for example, in K. Tai, et al., "Room-temperature continuous-wave vertical cavity surface-emitting GaAs injection lasers," Appl. Phys. Lett. 55 (1989) pp. 2473-2475, which is hereby incorporated by reference.
Although relatively high reflectivity is readily achieved in a hybrid DBR using relatively few, e.g., less than ten, semiconductor layers, a greater number of layers is generally required to achieve similarly high reflectivity in a semiconductor DBR. Thus, for example, Tai, et al. report the use of 22 layer pairs in a DBR for a VCSEL. However, spatial instabilities have been observed in at least some cases when a thin layer of a III-V material has been grown on a substrate of a different III-V material. Such instabilities are capable of causing roughness in a DBR, and such roughness may even propagate and grow in severity in subsequent layers as they are added to the DBR. For example, FIG. 6 is a transmission electron micrograph of a DBR structure in which such roughness is clearly apparent after the fifth layer pair, corresponding, typically, to about 670 nm of total growth in the DBR. As is apparent from the figure, this instability has a wave-like, or zig-zag, appearance, when the DBR structure is viewed in cross section. Moreover, it is apparent that the "waves" grow in amplitude as succeeding layers are added. One undesirable result of this instability is to limit the reflectivity achievable in DBR structures. As a consequence of relatively low DBR reflectivity, the threshold current achievable in a VSCEL incorporating such a DBR may be limited to a relatively high, and therefore undesirable, value.
The zig-zag instability described above is not the only instability plaguing the growth of epitaxial III-V layers. Thus, for example, R. K. Tsui, et al., "Effects of substrate misorientation on the properties of (Al, Ga)As grown by molecular beam epitaxy," J. Appl. Phys. 58 (1985) pp. 2570-2572 (Tsui I), reports that a rough surface morphology can appear in (Al, Ga)As epitaxial layers grown by MBE, under certain conditions, on GaAs substrates, and that the roughness can degrade a subsequently grown GaAs layer. The authors observe that the roughness is substantially eliminated by intentionally misorienting the substrate by a small tilt angle. Later, it was reported in R. K. Tsui, et al., "Properties of Al.sub.x Ga.sub.1-x As(x.sub.Al approximately 0.3) grown by molecular-beam epitaxy on misoriented substrates," J. Appl. Phys. 59, (1986) pp. 1508-1512 (Tsui II), that for growth of Al.sub.x Ga.sub.1-x As (x approximately equal to 0.3) on a (near) (100) surface of the GaAs substrate at substrate temperatures of 620.degree. C. and 650.degree. C., the optimum tilt angle was 3.degree.-5.degree., directed toward a nearest (111)A (gallium) surface. The authors also reported that reducing the growth temperature tended to increase the tilt angle required to grow smooth layers. Similarly, H. Z. Chen, et al., "Effect of substrate tilting on molecular beam epitaxial grown AlGaAs/GaAs lasers having very low threshold current densities," Appl. Phys. Lett. 51 (1987) pp. 2094-2096, reported that the morphology of structures grown on GaAs substrates, and consisting of GaAs quantum wells sandwiched between AlGaAs layers, was improved when the substrates were tilted from (100) by 4.degree. toward a nearest (111)A surface.
Thus, various authors have demonstrated that by appropriately tilting the substrate, it is possible to reduce or eliminate one particular growth instability that causes roughness in GaAs-AlGaAs heteroepitaxial structures. Relatively high substrate temperatures have also been found to improve the layer morphology. In the case of layers grown by molecular beam epitaxy, tilting of the substrate was successful in smoothing the layers when the substrate temperature was greater than 600.degree. C.
However, it is significant that the particular instability involved is one that appears in the very first "inverted interface;" i.e., the very first interface between an underlying GaAs surface and an AlGaAs layer grown on the surface. As described, for example, in H. Z. Chen, et al., the tilting method has been successfully applied for mitigating that particular instability and, as a result, for growing improved laser structures of a type that involve no more than about four heteroepitaxial layers. This situation is quite different from that of DBRs intended for incorporation in VCSELs. As noted, relatively many layers, typically more than ten, are required to provide adequate reflectivity of a DBR for bounding the optical cavity of a VCSEL. Unlike the "inverted interface" instability described by Tsui I, Tsui II, and Chen, cited above, the zig-zag instability does not appear in the first layer, but rather in subsequent layers, and it may even increase in severity as layers are added. In fact, the zig-zag instability can appear even under growth conditions such that the first inverted interface is smooth, and it can appear under growth conditions such that the roughness of each relevant aluminum-rich layer is smoothed by an immediately succeeding gallium-rich layer. Thus, the zig-zag instability occurs under circumstances quite different from those described, e.g., by Tsui I, Tsui II, and Chen, and as a consequence, those publications offer no guidance as to how it might be eliminated.
Zig-zag roughness in many-layered DBR structures has, in fact, been reported by J. Faist, et al., "Characterization of GaAs/(GaAs).sub.n (AlAs).sub.m surface-emitting laser structures through reflectivity and high-resolution electron microscopy measurements," J. Appl. Phys. 66 (1989) pp. 1023-1032. In that work, growth, at a substrate temperature of 680.degree. C., of quarter-wavelength layers of AlAs was alternated with growth of quarter-wavelength layers of (GaAs).sub.9 (AlAs).sub.2 superlattice. The roughness was mitigated by inserting six GaAs wells in each AlAs layer, each well having a width of about 2.5 .ANG.. However, this technique may offer some disadvantages because, inter alia, a lower substrate temperature during DBR growth is desirable, as discussed below, and also because the Faist technique necessitates the use of relatively many shutters in the MBE reactor, complicating the equipment and the procedure.
As noted, certain problems are posed by the substrate temperature. That is, when gallium-containing layers are grown by epitaxial growth methods such as MBE and MOCVD, it has been observed that the gallium sticking coefficient decreases as the temperature is increased. As a consequence, the mole fraction of gallium in the resulting layers is difficult to control, particularly at temperatures substantially greater than about 630.degree. C. As a consequence, it is desirable to reduce the substrate temperature even further, for example to less than 600.degree. C. while preserving desirable, i.e., smooth, layer morphology.
Thus, practitioners in the field have long sought a satisfactory method for growing VCSELs that comprise DBR structures that not only incorporate ten or more layers of alternating composition, but are also substantially free of roughness. Practitioners have hitherto been unsuccessful in finding such a method that does not involve the use of extra shutters for, e.g., intercalating included GaAs monolayers within aluminum-rich layers, and they have hitherto been unsuccessful in finding such a method that can be practiced at substrate temperatures, during DBR growth, of less than about 600.degree. C.


A bi-directional line switched mesh includes at least one bi-directional line switched ring (BLSR) sharing a common section with a partial bi-directional line switched ring (PBLSR). The partial bi-directional line switched ring has no working traffic along the common section, but may utilize the protection bandwidth associated with the common section of the BLSR in the event of a span failure of the PBLSR. Both electrical and optical PBLSR networks are also disclosed including methods of operating the asymmetrical ring nodes having unconfigured working ports (spans).

1. Field of the Invention
The present invention relates generally to optical ring and mesh networks. More particularly, the present invention is directed to bi-directional line switched partial rings and mesh networks composed of full and/or partial rings.
2. Description of Background Art
Bi-directional line-switched rings (BLSRs) are an important class of networks. In a BLSR network, working traffic can be carried along both directions of the ring. Each optical fiber in the ring supports transmission in one direction, either clockwise (CW) or counter-clockwise (CCW). During a normal mode of operation, working traffic is routed on the shortest optical path between two nodes in the ring. Half of the bandwidth between nodes is reserved for protection traffic, what is sometimes also known as protection bandwidth or protection channel access (PCA). Since the protection bandwidth is shared amongst all of the working traffic for any single fiber failure, the amount of bandwidth needed for protection is less than for a network using dedicated protection. But, because the switch is performed at the line level instead of each path level and requires little action at intermediate nodes, the switching times can be kept below the required limit of 50 milliseconds.
BLSR networks typically are configured with the spans coupling the nodes having either two-fibers or four-fibers. In a two fiber BLSR (2F-BLSR) each span has two fibers with one fiber assigned for CW traffic and the other fiber assigned for CCW traffic. In 2F-BLSR half of the bandwidth (channels or wavelengths) in a fiber are reserved for protection traffic (1513). In general, a 2F BLSR node may combine the working and protection bandwidth with associated multiplexers (354 also know as a working/protect splitter) onto one fiber. The switching equipment attached to these multiplexers within the node behaves like a 4F BLSR with half the capacity. Further details of conventional optical BLSR may be found in SONET Bi-directional Line Switched Ring Equipment Generic Criteria, GR-1230-CORE, Issue 4, December 1998 which is hereby incorporated by reference in its entirety
In a conventional optical BLSR, the nodes do not perform wavelength conversion. Therefore, when the network element performs a line switch, the half of channels that are used for working traffic in the CW direction, must be the same wavelength as the half that is used for protection in the CCW direction. With the bandwidth arranged in this way, changing the direction of the traffic changes its traffic type from working to protect. Thus, during a failure when BLSR changes the direction of the traffic for traffic 1530 in FIG. 18 from CW to CCW (see rerouted traffic 1630 of FIG. 19). The traffic has not changed structure, but is now flowing on the protection bandwidth and can remain optical.
In a four fiber BLSR (4F-BLSR) each span has four fibers coupling each set of nodes with two of the fibers being working fibers and the other two protection fibers. Instead of splitting the bandwidth of one fiber, a whole fiber is dedicated to either working or protection. Therefore, one must change the fiber and direction of traffic to change the type of traffic from working to protect.
SONET BLSR may be deployed using an electrical switch at each node after converting the optical signal into the electrical domain (more precisely, an O-E-O (optical to electrical to optical) switch). SONET BLSR may also take the form of a so called "virtual line switched ring" as described in U.S. Pat. No. 6,654,341, filed Oct. 19, 1999 and granted Nov. 25, 2003 the entirety of which is hereby incorporated by reference.
Also, optical BLSR (O-BLSR) may be deployed using an optical switch at each node which does not require the signal to be converted into the electrical domain (e.g. O-O (optical-optical) switch), saving this extra cost and allowing for non-SONET services. The extensions discussed in this patent application apply to both the electrical and optical BLSR networks.
For O-E-O switches, the node deals with optical fiber and timeslots carried inside the fiber, and performs timeslot assignment function. For an O-O switch, O-BLSR deals with fiber and wavelengths carried inside the fiber, and performs switching at the optical level. For the invention discussed in this application, O-E-O network elements (nodes) and O-O network elements (nodes) deal with the "signals" in different formats/granularities, but use the same network construction and control principles disclosed below.
The switching equipment has at least four modes to support a BLSR network as illustrated in the diagrams of FIGS. 1c-g show bi-directional traffic with one bidirectional line with one bidirectional port at each end. These may be shown as two parallel lines of unidirectional traffic—having twice as many unidirectional ports):
(i) Normal (N) mode has the switch passing traffic directly from the client tributary Add/Drop Multiplexer (ADM) to the line access ports and vice-versa. Lower priority traffic may be carried on the bandwidth unused during normal operation. This is shown as the dotted lines in FIG. 1c. This traffic is lower priority because it is dropped during a network failure that requires the bandwidth to be used.
(ii) Ring-Switch West (RS-W) mode is used when the failed span is on the East side of this node and has the switch passing west working traffic to the west working OADM and east working traffic to the west protection OADM. The protection tributary client traffic is not used. See FIG. 1d. An optional bridging of traffic to both the protection and working line access at the same time is possible (as shown by the dotted line) in both the optical and electrical implementations. This optional bridging is useful for keeping the working line access signal alive to determine when the link is restored. If this bridging is not implemented, an out-of-band communication signaling is required.
(iii) Ring-Switch East (RS-E) mode is used when the failed span is on the West side of this node and has the switch passing east working traffic to the east working ADM and west working traffic to the east protection ADM. The protection tributary client traffic is not used. See FIG. 1e. As with switch mode (ii), an optional bridging to the original working line access is also useful.
(iv) Intermediate nodes are not directly connected to the failed span and use the Bridge (B) mode to pass protection traffic straight through the network element. This connects the working east and west tributary traffic to the working east and west line access ports. See FIG. 1f. The protection tributary access traffic is dropped. However, the protection line access traffic is passed through as shown as the dotted line in FIG. 1f.
(v & vi) Two additional modes are also useful in an electrical implementation to recover from some additional failures: the East and West Span (S) Switch shown in. These failures include a fiber failure if this is implemented as 4 fiber BLSR or a equipment or fiber failure in the ADM that drops the working traffic, but allows the protection channel to survive. This switch mode simply puts the normal working traffic on the protection line access for the same direction (East or West) as the normal working traffic's direction as further shown in FIG. 1g.
In electrical BLSR networks, the electrical switch matrix is an O-E-O switch that implements the above switching operations with an Add/Drop Multiplexer at a minimum, or may utilize a more general combination of time division and space switching to permit a time slot interchange and arbitrary switching of timeslots between multiple input ports and multiple output ports. Such a non-blocking electrical switch matrix has been described in Klausmeier, et al. U.S. Pat. No. 6,343,075 granted Jan. 29, 2002 and filed Oct. 26, 1999 which is hereby incorporated by reference in its entirety. Such switches are also commercially available such as the CoreDirector® intelligent optical switch sold by CIENA Corporation.
In accordance with the SONET standard, spans transfer units of information called Synchronous Transport Signals (STS). For the different optical carrier levels OC-n (such as OC-1, OC-3 and OC-12), there is a corresponding STS-n, where n is the number of STS-1 segments or time slots. Typical spans are composed of 1, 3, 12, 48, or 192 STS-1's. All SONET spans transmit 8,000 frames per second, where each frame is composed of an integer number of STS-1 segments, such as 1, 3, 12, 48 or 192.
In an optical BLSR network each node has a ring switch module (also known as a ring switch matrix) that permits at a minimum the working traffic from a source node to be redirected onto the protection bandwidth in response to a line fault or node failure. The protection traffic is directed along an alternate optical path to a destination node that avoids the defect. Low priority "extra traffic" that may in a normal mode utilize the protection bandwidth is sacrificed to ensure that higher priority working traffic is directed to its destination. A general purpose optical space-switch may be used to provide this switching function.
FIG. 1A illustrates an exemplary and conventional BLSR network 100 having nodes 101, 102, 103, and 104. Each node includes a ring switch module (not shown) to switch working traffic either optically or electrically. Working paths between two nodes, node 101 and node 103, are shown for a normal mode of operation. As indicated in FIG. 1B, responsive to detecting a line failure (e.g., a loss of signal or a degraded signal condition) between nodes 101 and 104, the nodes detecting the line failure initiate a ring switch to redirect traffic away from the failed line using the protection capacity bandwidth.
One benefit of the conventional BLSR topology is that it efficiently utilizes protection bandwidth. However, one drawback of a conventional BLSR topology is that it requires working bandwidth to be available even when it is not used. This unused bandwidth also requires unused switching equipment, unused transponders and unused transport fiber.
Additionally, another drawback of the conventional BLSR topology is that it is difficult to implement an arbitrary mesh topology in a cost-effective manner. Referring to FIG. 2A, a single ring BLSR network 280 has nodes 201, 202, 203, 204, 205, and 206. However, for a particular application it may be desirable to form direct data links between nodes 202 and 205 to improve the quality of service and/or data capacity of the network. This results in mesh topology.
Conventionally, a mesh topology may be implemented as dual full BLSRs 200, as shown in FIG. 2B. A first full (complete) BLSR 220 includes nodes 201, 202, 204, and 205. The second full BLSR 230 includes nodes 207, 203, 206, and 208. Each BLSR 220 and 230 has its own working and protection bandwidth and acts as a conventional BLSR with half the bandwidth of each span reserved for protection traffic. However, as indicated by dashed lines 250, nodes 202, 205, 207, and 208 include an element, such as an optical-to-electrical (OEO) cross-connect (not shown) to permit data to be transferred between the BLSRs 220 and 230.
Comparing the dual BLSR network 200 with a single ring BLSR network, it can be seen that a dual BLSR ring network 200 greatly increases the equipment requirements compared with a single ring BLSR 280. In the example of FIG. 2B, at least two additional nodes and two associated spans are required to implement a link between node 202 and node 205. Additionally, high data rate electrical/optical cross-connect is typically required to couple data between the rings, further increasing the incremental hardware costs.
What is desired is a flexible BLSR protection scheme that does not require bandwidth and equipment when not needed and an optical network design that combines the benefits of a mesh topology and the benefits of bi-directional line switching with reduced hardware requirements.

Bidirectional line switched partial rings, mesh networks, and methods of operation


Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN1). A ripple voltage (Vripple) present on the input voltage causes a ripple current (Iripple) through parasitic gate-drain capacitance of the pass transistor. A small ripple current (Ifraction) proportional to the ripple current (Iripple) is generated and amplified to generate a cancellation current (Icancel). The cancellation current is drawn from the gate of NMOS pass transistor (MN1) to cancel the ripple current so that no net ripple current flows through the finite output impedance of an error amplifier (2), to thereby achieve the PSRR improvement.

The present invention relates generally to LDO (low dropout) voltage regulators, and more particularly to improvements in LDO voltage regulators which utilize an N-channel pass transistor and also provide both high PSRR (power supply rejection ratio, also referred to as power supply ripple rejection) and low VIN-to-VOUT voltage "headroom" at high frequencies. A conventional LDO, with either an NMOS or a PMOS pass device, is essentially a 3-terminal device having VIN, VOUT, and GND terminals. VIN not only delivers power to VOUT, but also is used as a supply voltage, sometimes referred to as a "supply rail", for the LDO control circuit. In the case of N-channel pass transistor LDO, VIN can no longer be used as the supply rail for controlling the gate of an N-channel pass transistor of an LDO as VIN-to-VOUT becomes lower and lower (to be less than 0.7 volts), because N-channel MOS transistors need at least one gate-to-source (VGS) voltage, typically around 0.7 volts, to be turned on. That is why a separate voltage rail higher than VIN, either an external biasing rail VDD or an internally generated charge-pump voltage VCP, must be used to provide the gate drive for an N-channel MOS pass transistor. The penalties of using an external biasing voltage rail include limited use of N-channel pass transistor LDO's to systems where an extra high voltage rail is available and increased system complexity. The penalties for using an on-chip charge pump needed for N-channel LDO pass transistors include introducing switching noise and increasing the cost for integrated circuit die area. Nevertheless, the need to regulate from low input voltages makes it even more desirable to use N-channel MOS pass transistors in LDO voltage regulators because an N-channel MOS pass transistor can provide a lower dropout voltage (i.e., the VIN-to-VOUT voltage headroom) than a P-channel pass transistor due to the higher mobility of the charge carriers in N-channel transistors. In other words, the higher mobility charge carriers allow N-channel pass transistors to be substantially smaller and therefore less costly than P-channel pass transistors.
It has been very challenging to obtain high PSRR in voltage regulators having low dropout voltages because there is a trade-off between achieving high PSRR and reducing the size of the pass transistor. The PSRR for a linear regulator is defined as PSRR=vi(s)/vo(s), where vi(s) is the small AC excitation signal on VIN and vo(s) is the AC responsive signal on VOUT. For a given amount of dropout voltage or VIN-to-VOUT headroom, a larger MOS pass transistor operates closer to its saturation region and consequently provides better isolation of its regulated output voltage VOUT from ripple voltage components in its input voltage VIN. (By way of definition, the terms "ripple voltage" and "noise voltage" as used herein have generally the same meaning.)
Referring to Prior Art FIG. 1A, a typical low-dropout LDO voltage regulator 1A includes an error amplifier 2 and a large N-channel pass transistor MN1. The (+) input of error amplifier 2 is coupled to a reference voltage VREF, which is typically generated by a conventional band gap reference voltage circuit. A resistive voltage divider circuit including resistors R1 and R2 feeds a divided-down portion of the regulated output voltage VOUT back to the (−) input of error amplifier 2. The output of error amplifier 2 is coupled by conductor 3 to drive the gate of N-channel pass transistor MN1 acting as a source follower. Since the physical size of the N-channel pass transistor MN1 is relatively large, its gate-to-drain parasitic capacitance Cgd also is proportionately large, so the AC voltage component of the input voltage VIN can inject significant "displacement current" through the parasitic capacitance Cgd to the gate of pass transistor MN1, as indicated by arrow 9 in FIG. 1A. Since error amplifier 2 has finite output impedance ro, the injected displacement current generates a noisy ripple voltage related to the input ripple voltage on the gate of pass transistor MN1 (except for some phase shifts). Because of the source follower operation of pass transistor MN1, a "replica" of the noisy ripple voltage on the gate of pass transistor MN1 is passed onto VOUT conductor 6 as a corresponding ripple voltage component of VOUT. This degrades the PSRR of LDO voltage regulator 1.
FIG. 1B is a copy of a CMOS (complementary metal oxide semiconductor) LDO voltage regulator lB shown in the reference "A 25 mA 0.13 μm CMOS LDO Regulator with Power-Supply Rejection Better than −56 dB up to 10 MHz Using a Feedforward Ripple-Cancellation Technique", by Mohamed El-Nozhi et al., ISSCC Digest of Technical Papers, pp. 330-331, February, 2009. The basic idea of this reference is to use ripple cancellation to improve the PSRR of a LDO voltage regulator that uses a P-channel pass transistor MP. In FIG. 1B, one can see that VIN drives the source of P-channel pass transistor MP and any ripple voltage in the VGS (gate-to-source-voltage) will be converted into ripple current to VOUT, causing PSRR degradation. By using a feed-forward amplifier 12 to duplicate the ripple noise component of VIN onto the gate of the P-channel pass transistor MP, the P-channel pass transistor MP does not "see" any ripple voltage component of VIN between its gate and source, so the PSRR is improved.
It can be seen that input ripple voltage cancellation for the LDO regulator of FIG. 1B can only be obtained within the bandwidths of the feed-forward amplifier 12 and summing amplifier 11, as the high frequency components in the input ripple voltage that are beyond the bandwidths of the two amplifiers can not be replicated to the gate of pass transistor MP. Moreover, in order to obtain optimal ripple voltage cancellation, pass device MP has to operate in its saturation region, as the cancellation is based on nullifying the ripple voltage superimposed on the gate-to-source voltage VGS of pass transistor MP so that no input ripple voltage can be converted to a ripple current flowing to the regulator output to cause PSRR degradation. However, as previously indicated, the pass transistor in an LDO voltage regulator usually operates in or near its linear region to improve power efficiency. If pass transistor MP in FIG. 1B is operating in its linear region, not only the output conductance of the pass transistor, gds, can be comparable to, or even larger than, its transconductance gm, but the output conductance also changes substantially with the load of the LDO regulator. The cancellation is not so effective because most of the noise coupled from VIN to VOUT passes through the output conductance gds of pass transistor MP. Also, it should be noted that although the cancellation technique of prior art FIG. 1B is effective for a P-channel pass transistor LDO, it is not applicable for an N-channel pass transistor LDO.
FIG. 1C is a copy of a CMOS LDO voltage regulator 50 shown in US Published Patent Application Pub. No. US2011/0193540 entitled "Enhancement of Power Supply Rejection for Operational Amplifiers and Voltage Regulators", by Uday Dasgupta, filed Feb. 11, 2010 and published Aug. 11, 2011. This reference describes the implementation of PSRR improvement in an intermediate frequency range using feed-forward power supply ripple cancellation. A differential transistor pair 62 drives a load 64 to control the P-channel pass transistor MPD, in a conventional LDO. In addition, an amplifier 52 also drives load 64 to generate a feed-forward path for the power supply noise signal to cancel a power supply ripple voltage signal present on the gate of the pass transistor MPD. The cancellation is completed if the two signals are exactly equal and opposite. In this reference, the cancellation is optimized by digitally modifying the PSRR transfer function. Current signals resulting from the power supply ripple voltage are injected into a first stage to cancel first order terms in the PSRR transfer function, and a digital current gain adjustment circuit is used to optimize the PSRR, which occurs mainly within the bandwidth of the feedback loop. Similarly to the prior art shown in FIG. 1B, the effectiveness of the PSRR cancellation in Prior Art FIG. 1C is reduced when the operation of P-channel pass transistor MPD is near or in its linear operating region. Furthermore, the disclosed technique is not applicable to an N-channel pass transistor.
Thus, there is an unmet need for an LDO voltage regulator having an N-channel pass transistor, and also having substantially higher PSRR at higher frequencies than the closest prior art.
There also is an unmet need for an LDO voltage regulator having an N-channel pass transistor, and also having substantially higher PSRR at higher frequencies than the closest prior art irrespective of whether the pass transistor is operating near or in its linear region.

NMOS LDO PSRR improvement using power supply noise cancellation


An apparatus for animating a figurine movable element having a pivot point for pivotally coupling the movable element to the figurine to allow the movable element to pivot between the first position and a second position, a first portion of the movable element extending in front of the pivot point and a second portion of the movable element extending behind the pivot point; a hollow solenoid on the figurine with an elongated steel shaft having one end inserted in the hollow solenoid winding and the other end pivotally attached to the second portion of the movable element behind the pivot point such that the shaft pivots the movable element between the first position and the second position depending upon the solenoid operation.

(1) Field of the Invention
The present invention relates in general to apparatus for animating a movable element of a figurine and specifically relates an eye mechanism for mounting in an animated figurine to enable an eyeball replica with a pupil thereon to appear to blink.
(2) Description of Related Art
Animated figurines are well known in the art and include animal forms as well as human forms. These figurines walk, roll over, dance, talk, move their arms and provide various other animated features. It is extremely difficult and expensive to provide the necessary mechanical and electromechanical devices and configurations which enable the animation of the figurine.
Movement of the eye is a particularly difficult procedure. In simple doll mechanisms, a weight is pendulously attached to a pivoting eyeball replica such that when the doll is in the upright position, the eyes appear to be open and, when the doll is placed on its back, the weight pivots downwardly thus closing the eye.
In newer versions of animated figures, the figure may speak, if a person, or bark, if a dog, or make other sounds. When the electrical signals for causing the voice and/or movements of the eye, mouth, arms and legs are generated from a data storage device such as a magnetic tape, the eyes, mouth, arms and legs may be caused to be moved in coordination by the signals stored on the tape such as disclosed in commonly assigned copending U.S. patent application Ser. No. 07/943,766 filed Sep. 11, 1992 and entitled TALKING FIGURE WITH ANIMATED FEATURES. In that case, pulses are stored on a magnetic tape that coordinate with the speech sounds digitally recorded on the tape. When the tape is activated, the sounds on the tape are coupled to a circuit and speaker for producing the sounds. Pulses recorded on the tape are coupled to a circuit that decodes the pulses and provides a signal to a solenoid for movement of the eyes, arms, legs, mouth or tail, if an animal is involved. In order to keep the costs within reasonable limits for such a device, it is necessary that an electromechanical arrangement be devised to move the element in question is a simple, efficient and economical manner.

Solenoid mechanism for movement of figure portions


An apparatus and method are provided for composing a data input key array with a plurality of keys wherein multiple character groups are assigned to respective ones of the plurality of keys, each of the multiple character groups comprising multiple characters. The multiple characters of each character group are arranged on the corresponding key in the same pattern as the multiple character groups on the data input key array. The data input key array may operate by selecting a particular key assigned with a desired character, and selecting a key disposed to correspond with the position of the desired character on the particular key, thereby displaying the desired character. The data input key array may also be operated by selecting a particular key assigned to a desired character by inputting one of the directional keys, the directional key being disposed to correspond with the position of the particular key.

1. Field of the Invention
The present invention relates to a method of composing and operating a data input key array and an apparatus using the inventive data input key array. More particularly, the present invention relates to a method and apparatus which facilitate key operation when inputting character data through the data input key array.
2. Description of the Related Art
The conventional mobile phone has a data input key array comprising a plurality of keys representing characters and symbols, whereby the user may input desired characters by selecting or pressing the keys assigned with the desired characters.
The data input key array consists of a plurality of basic numeric keys represented by respective Arabic numbers and a few auxiliary keys. In addition, each numeric key is assigned usually with two or more letters, for example English language characters, whereby the user may input character data by pressing the key one to three times. However, it is an inconvenience to the user to operate a key three times in order to input one character.
Referring to FIG. 1 for illustrating the conventional data input key array, in order to input the word "LOVE", the user must select or press key numbered "5" three times to input character "L", key number "6" three times to input character "O", key numbered "8" three times to input character "V", and then key numbered "3" twice to input character "E".
Accordingly, there is a need for an improvement in composing and operating data input key array.

Method of composing and operating data input key array and apparatus employing the same


A low temperature rendering process for converting animal trimmings to a meat product which can be classified as finely textured meat. The low temperature rendering process includes the steps of heating desinewed animal trimmings in a heat exchanger having a first-in and first-out arrangement to provide heating of the desinewed animal trimmings to a temperature in the range of about 90.degree. F. to about 110.degree. F. to form a heated slurry; separating a solids stream and a liquids stream from the heated slurry, the solids stream containing an increased amount of protein and moisture, and the liquids stream containing an increased amount of tallow, water soluble protein, and moisture; separating a heavy phase and a light phase from the liquids stream, the heavy phase containing an increased amount of moisture and water soluble protein, and the light phase containing an increased amount of tallow; and combining the solids stream and the heavy phase to form a meat product.

Low temperature rendering processes have been used to separate protein from fatty tissue in animal trimmings. Low temperature rendering processes are described in, for example, U.S. Pat. Nos. 3,008,831; 3,020,160; and 3,078,165. The processes generally involve comminuting fatty tissue from animals, such as hogs or cattle, to form a semi-solid slurry or meat emulsion, heating the slurry or emulsion to melt the fat, and then separating the fat and protein by centrifugation. The protein can then be used as an ingredient in processed meat products such as sausage and other cured and processed meats.
As reported in U.S. Pat. No. 3,219,616 to Brissey, it has been found that the protein or meat provided by prior art low temperature rendering processes suffer from undesirable flavor changes shortly after production. In order to reduce the flavor changes after low temperature rendering processes, this patent teaches using a heme-conditioning agent which reacts or combines with the heme pigments of the meat to reduce the activity of the heme pigments which catalyzes the development of off-flavor.
The government provides that a certain quality of meat product obtained from animal trimmings can be used undeclared in meat products of the same species. For example, "finely textured beef" and "lean finely textured beef" can be used in ground beef without being declared on the label. "Finely textured meat" is required to have a fat content of less than 30%; a protein content of greater than 140%, by weight; a protein efficiency ratio (PER) of 2.5 or higher, or an essential amino acids (EAA) content of 33% of the total amino acids or higher; must be prepared in a federally inspected plant; must not have a product temperature during processing exceeding 110.degree. F.; must be frozen in less than 30 minutes after processing; must not allow a significant increase in bacterial numbers; and must not be treated with chemicals or additives. "Lean finely textured meat" is required to have a fat content of less than 10%, by weight, and complies with the other requirements of "finely textured meat."


Apparatus and process for removing unwanted foreign material from particulate material. The apparatus and process find particular application in the pulp and paper industry to remove contaminating plastic material from wood chips. The apparatus includes a transporting conveyor for moving the particulate material between a inlet area and an outlet area and a vibrating motor for vibrating the conveyor to sort the particulate material and the foreign material. Heated rollers heated to a temperature sufficient to render the foreign material tacky are applied to the sorted material and cause the foreign material to adhere thereto such that the foreign material is extracted from the particulate material which is delivered to the outlet area.

In the pulp and paper industry, logs provide the raw material for the manufacture of paper and paper products. These logs are processed in large mills and the first step in handling of the logs often involves converting them into wood chips which are a convenient form for further processing.
The raw logs that are delivered to a mill often include pieces of waste plastic that are unfortunately becoming a common part of the environment. Plastic is used in a great deal of packaging and often ends up discarded into the environment. Unfortunately, when the logs are converted into wood chips, the plastic tends to be converted into smaller pieces as well. In the conversion of the wood chips into pulp and paper, the plastic pieces can contaminate the resulting paper product leading to reduced quality paper or paper that is unsuitable for use at all. Spoilage of new paper by plastic contamination can be a costly problem in the industry where a large batch of paper can be ruined or reduced in quality by a relatively small amount of unwanted plastic. Presently, to address this problem, mills simply rely on workers handling logs and wood chips to visually inspect the material and remove visible pieces of plastic. Obviously, this method is very inefficient and does not remove all plastic waste.

Method and apparatus for removing plastic from wood chips


A redundant binary code conversion circuit consists of first to third RBC conversion circuits 261 to 263. The circuit 261 consists of decoders 30 to 38 of the same construction, the circuit 262 consists of RBC 2-digit conversion circuits 40 to 47 of the same construction and the circuit 263 consists of decoders 50 to 58 of the same construction. The circuit 261, as an exception, converts RBC patterns `...TT011...`(`T` is -1), `...110TT...`, `...TT1...` and `...11T...` of n digits to RBC patterns `...T10T0T...`, `...1T0101...`, `...T10T...` and `...1T01...` of (n+1) digits, respectively, circuit 262 converts RBC patterns `...1T...` and `...T1...` to RBC patterns `...01...` and `...0T...`, respectively, and circuit 263 converts RBC patterns `...10TT...` and `...T011...` to RBC patterns `...0101...` and `...0T0T...`, respectively.

1. Field of the Invention
The present invention relates to a redundant binary code conversion circuit and a multiplication circuit in which the same is used.
2. Description of the Related Art
FIG. 11 shows a brief configuration of a prior art multiplication circuit.
It is assumed that a multiplicand and multiplier are a positive integer of n bits. Furthermore, it is assumed that each of register 10 and higher-order bit part 11H and lower-order bit part 11L of shift register 11 is of n bits. In the drawing, C is a count of counter 13 and CO is a carry output from adder circuit 14. The following processes are carried out by control circuit 12.
(1) A multiplicand is loaded in register 10, a multiplier is loaded in lower-order bit part 11L of shift register 11, and higher-order bit part 11H of shift register 11 is cleared to be zero. Initial-value n is loaded in counter 13.
(2) With CO provided in the MSB of shift register 11, shift register 11 is shifted by one bit in the direction of the arrow.
(3) If the shifted output bit from the LSB of shift register 11 is `1`, (Higher-order bit part 11H).rarw.(Higher-order bit part 11H)+(Register 10), and if the bit is `0`, the process is skipped.
(4) C.rarw.C-1
(5) If C=0, the process ends, and if C.noteq.0, the process returns to step (2).
Although the construction of this multiplication circuit is simple, the calculation time is lengthened since addition and shift processes are repeatedly carried out. This problem will become remarkable with an increase of the number of digits, wherein the process rate such as DSP equipped with a multiplication circuit is greatly influenced by the calculation rate of the multiplication circuit. Especially, in DSP which is used for a portable telephone, image processing device, etc., a fast process is requested.
From the above-mentioned (3), the more the number of zeros which are included in multiplier becomes, the more the time of multiplication is decreased.
On the other hand, according to RBC (redundant binary code) of ternary code, it can be converted to a code of the same value including more zeros by utilizing its redundancy. The RBC n digits of a number Z is ##EQU1## where .alpha.i.epsilon.{1, 0, -1} and this number Z is expressed in vector notation as EQU Z=`.alpha.n-1.alpha.n-2....alpha.2.alpha.1.alpha.0`.
Usual binary codes are included in RBCs of ternary code. For example, RBC `01111111` can be converted to RBC `01000000T`, where T represents -1. A.times.`1000000T` needs only the calculation of the above step (3) only two times while A.times.`01111111` needs calculations of the step (3) seven times.
Therefore, in FIG. 11, an RBC multiplier is loaded in register 15, the multiplier is converted in RBC conversion circuit 16 to increase the number of zeros, and the same is loaded in the lower-order bit part 11L of shift register 11. The process in RBC conversion circuit 16 can be carried out in parallel with the previous multiplication.
In such an RBC multiplication circuit, the output of RBC conversion circuit 16, the lower-order bit part 11L and higher-order bit part 11H are of n digits of RBC. Further, registers 10 and 15 are of n digits of RBC, and adder- subtracter circuit 14 is for addition or subtraction between a RBC n digits and another RBC n digits.
In the prior art, code conversion is carried out by RBC conversion circuit 16 on the basis of the following truth TABLE I.
TABLE I ______________________________________ INPUT OUTPUT No. X.sub.i+1 X.sub.i X.sub.i-1 X.sub.i-2 Y.sub.i ______________________________________ 1 1 1 0 2 1or1 1 0 1 3 1 1 0 4 0 1 1 1 5 0 1 1 1 6 1 1 0 7 1or1 1 0 1 8 1 1 0 ______________________________________
Values at the blank on TABLE I are don't care. Furthermore, 1 with a top bar is equal to -1 (T), and rows No. 1 through No. 4 are complementary with rows No. 8 through 5, respectively.
Generally converted value Yi of the ith digit is defined by pre-conversion values Xi+1 through Xi-2 of the (i-1)th through (i-2)th digits. For example, `X4X3X2X1X0`-`01111` coverted to `Y4Y3Y2Y1Y0` as described below with Xj=0 for j=-2, -1 and 5 which do not exist.
For i-0 as input is `1100`, row No. 7 in Table is applied, then Y0=`T`.
For i=1; as input is `1110`, row No. 8 in Table is applied, then Y1-`0`.
For i=2; as input is `1111`, row No. 8 in Table is applied, then Y2=`0`.
For i=3; as input is `0111`, row No. 8 in Table is applied, then Y3=`0`.
For i=4; as input is `0011`, row No. 5 in Table is applied, then Y4=`1`.
Thus, RBC `01111` is converted to RBC `1000T`. These processes of i=0 through 4 can be carried out in parallel to one another.
However, the number m of zeros included in the converted RBC differs in compliance with the numerals of pre-conversion, and in design, the slowest multiplication speed with m at the minimum must be used. This problem will become remarkable with an increase of the digit number according to a high performance tendency of DSP, etc. in which a multiplication circuit is used.

Redundant binary code converting circuit and multiplication circuit using same


A display device includes a display portion having red, green, blue and white sub pixels, a converter generating red, green and blue conversion signals using a brightness ratio from a ratio storage, an upper limit value calculator calculating an upper limit value of a display brightness of the white sub pixel using the red, green and blue conversion signals and the brightness ratio, a lower limit value calculator calculating a lower limit value of the display brightness of the white sub pixel using the red, green and blue conversion signals and the brightness ratio, and a white control signal generator generating a white output control signal for controlling the display brightness of the white sub pixel such that the display brightness is not more than the upper limit value and not less than the lower limit value, and outputting the generated white output control signal to the display portion.

As the foregoing display device, proposed is a display device which displays a color video picture configured from the three primary colors of red, green and blue with four colors on a display portion having pixels including red sub pixels, green sub pixels, blue sub pixels and white sub pixels (for example, refer to Patent Document 1). In the device described in Patent Document 1, a minimum value among the three-primary-color signals is generated as a white output control signal, and this white output control signal and three-primary-color output control signals obtained by subtracting the white output control signal from the foregoing three-primary-color input video signals are supplied to the display portion.
However, in the device described in Patent Document 1, since the white sub pixels are always used for a color that can be reproduced using the red sub pixels, the green sub pixels and the blue sub pixels or for a color that can be reproduced using the white sub pixels, the red sub pixels, the green sub pixels and the blue sub pixels become dark in comparison to the white sub pixels, and there were cases where black vertical streaks would become noticeable.
Patent Document 1: Japanese Patent Application Publication No. 2004-286814

Display device having a generator for generating RGBW signals based on upper and lower limit value calculator and display method thereof

Panasonic Intellectual Property Management Co., Ltd.


A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

1. Field of Invention
The present invention relates to a method for fabricating a package. More particularly, the present invention relates to a method for fabricating a wafer-level chip package.
2. Description of Related Art
Along with the trends of electronic devices toward lighter and more compact, the semiconductor chip corresponding to the electronic device has a reduced size and increased wiring density. Therefore, it is more difficult and challenging to fabricate a semiconductor chip package in the subsequent process for the semiconductor chip. Wafer-level chip package is a method of packaging the semiconductor chip, which the method means all the chips are packaged and tested after completion of manufacturing these chips on the wafer, and then the wafer is cut into single chip packages. Since the size of the semiconductor chip is decreased and the functional density on the semiconductor chip is increased, the wiring density of the redistribution layer on the semiconductor chip should be increased correspondingly. Generally, a complicated electro-deposited photoresist technique is applied to complete the lithography process of the high-density redistribution layer. However, the process often leaves metal residues on sides of the chip package, which brings in defects and thus water infiltration to the packaged product. Accordingly, a more reliable electronic device package and a fabrication method thereof, which is more suitable for mass production, have become one of important issues in electronics industry.

Method of fabricating wafer-level chip package


A system, method and computer program are provided for facilitating viewer navigation within a virtual reality three-dimensional workspace containing functional three-dimensional objects. The viewer has the capability of navigating towards such three-dimensional functional objects and interacting with them functionally in specific tasks. Such specific tasks often require a fairly narrow viewpoint to provide close viewer interaction with the object in the specific task. The present invention provides a means for facilitating the viewer's navigation along his desired or planned path after he has completed a specific task relationship with a particular selected object. Means are provided for monitoring the task specific relationship of the viewer with the object and as soon as a determination is made that the viewer has completed his task, the system automatically changes the viewpoint of the viewer from the task specific viewpoint to the optimum browsing or navigation viewpoint with respect to the viewer's current viewpoint so that the viewer can proceed further in his navigation.

The 1990's decade has been marked by a societal technological revolution driven by the convergence of the data processing industry with the consumer electronics industry. This advance has been even further accelerated by the extensive consumer and business involvement in the internet over the past two years. As a result of these changes, it seems as if virtually all aspects of human endeavor in the industrialized world requires human-computer interfaces. As a result of these profound changes, there is a need to make computer directed activities accessible to a substantial portion of the world's population which, up to a year or two ago, was computer-illiterate, or at best computer indifferent. In order for the vast computer supported market places to continue and be commercially productive, it will be necessary for a large segment of computer indifferent consumers to be involved in computer interfaces. Thus, the challenge of our technology is to create interfaces to computers which are as close to the real world as possible.
Industry has been working towards this challenge and there is presently a relatively high degree of realism possible in interfaces. This presents a need and an opportunity for even more realistic interaction techniques to better match the visual metaphors used and to achieve a higher level of ease of use for computer systems. We are striving towards the representation of object as photo realistic, three-dimensional (3D) models rather than as the icons and two-dimensional desktops of conventional computer technology.
Some examples of current technology for the creation of virtual three-dimensional workspace display interfaces are copending application Ser. No. 08/813,891 (Attorney Docket No. AT9-96-310), entitled "VIEWER INTERACTIVE OBJECT IN VIRTUAL THREE-DIMENSIONAL WORKSPACE" and Ser. No. 08/813,848 (Attorney Docket No. AT9-96-311), entitled "VIEWER INTERACTIVE OBJECT WITH MULTIPLE SELECTABLE FACE VIEWS IN VIRTUAL THREE-DIMENSIONAL WORKSPACE", assigned to the Assignee of the present application.
A 3D virtual workspace display environment is also described in an article entitled, "RAPID CONTROLLED MOVEMENT THROUGH A VIRTUAL 3D WORKSPACE", Jock Mackinlay et al., Computer Graphics Publication, Vol. 24, No. 4, August 1990, pp. 171-175, as well as in its related U.S. Pat. No. 5,276,785.
It is clear that current technology in virtual three-dimensional workspaces has provided environments which are user friendly, i.e. make the casual computer user feel more comfortable and at home with the interface. However, researchers in human factors have found downsides to three-dimensional virtual reality displays. Because of the many choices that the user has in wandering down various "streets and roads" or visiting a wide variety of "buildings or stores" or going through many possible "doors", the user may wander through this reality and perhaps get lost from the track or goal he is pursuing.
The present invention addresses this problem, i.e. that of helping the interactive user in three-dimensional graphic environments to stay focused and relate to the paths he is seeking to travel to in the manner he is seeking to travel to reach objects even when these objects are arranged in 3D space in what appears to be infinite configurations. The invention facilitates the user's navigation in the 3D space so that the user may easily and quickly continue on his navigational path and stick to his navigational objectives.

Three-dimensional workspace interactive display having browsing viewpoints for navigation and work viewpoints for user-object interactive non-navigational work functions with automatic switching to browsing viewpoints upon completion of work functions

International Business Machines Corporation


In an auger-type product chiller having an auger including a series of successive flights that form a generally helical structure that, when rotated, moves product through cold water for chilling the product, control elements extending from faces of the flights at a non-zero angle. The control structures prevent "clumping" and packing of poultry product, break up any "clumps" and packs of the product that may develop, and improve product uniformity. In this manner, the advantages of proper agitation, as well as rapid, predictable and even product cooling and moisture introduction, are achieved. Implementations of the control elements include sets of rods extending from the flights at 30.degree. angles from radial lines of affixation to the flights, flat plates extending from the flights at 30.degree. angles from radial lines of affixation to the flights, and sets of rods extending between successive flights near peripheries of the flights.

1. Field of the Invention
The present invention relates to poultry chillers. More specifically, the invention relates to auger-type poultry chillers in which "clumping" or packing of poultry in the auger is minimized or prevented.
2. Related Art
Poultry chillers, such as auger-type poultry chillers, are known in the art. A partial cutaway view of a portion of one such auger-type poultry chiller is illustrated in FIG. 1 and a side cutaway view thereof is illustrated in FIG. 2.
An auger of the chiller includes a series of flights 100A, 100B, 100C, 100D, 100E, and so forth. Each flight includes a series of steps 101, 102, and so forth. The steps are inherent in the construction of the flights. The flights are connected in a series so that their outer edges form a continuous helical structure located within a housing 105. Suitable means, such as a motor, rotates the auger counter-clockwise as viewed in FIG. 1 within the housing to move the product at a controlled rate from an inlet end to an outlet end.
Items of a poultry product, such as slaughtered, eviscerated chickens or turkeys, enter the housing through a first end 110 and are moved through a chilled water bath by rotation of the auger toward a second end 120. During the chilling process, chilled water enters the housing at entry points 130, and exits at point 140, the water flowing in a direction opposite to that of the poultry product. The water being warmed by contact with the initially-warmer poultry product, is re-circulated and re-chilled by a refrigeration unit 150 before being returned to the auger housing.
In this manner, the poultry product entering the housing is chilled by the water flowing in the opposite direction to its own motion. When operating properly, the chilled water flowing in the chiller lowers the temperature of the product uniformly and sufficiently from approximately 100.degree. F. to approximately 35.degree. F. before the product exits the chiller at end 120.
The chiller illustrated in FIG. 1 has the disadvantage that the poultry product sometimes packs and "clumps" in certain areas in the housing rather than progressing; uniformly through the chiller When the product packs and clumps in certain flights rather than being evenly distributed among the flights, the chilled water does not surround each item uniformly, retarding the chilling of the product to USDA (United States Department: of Agriculture) standards, impeding the desired agitation of the product, and thwarting uniform control of moisture introduced into the product as well as uniform final temperature. It is to prevent such clumping, and to maximize the functional advantages of an auger-type chiller, that the present invention is directed.

Auger type poultry chiller with clumping prevention


For communication networks comprising user devices, edge routers, core routers, access and core links, a specification is given for a novel method and apparatus computing and allocating fair transmission rates to user data flows from a plurality of quality of service levels. The fair rates satisfy the minimum transmission rates, the end-to-end delays and the data loss rates required by each flow and also avoid network congestion. The method comprises: an edge router process and a flow control shaper for each edge router and a core router process for each edge and core router. All processes are executed in a distributed and asynchronous manner, are stable and converge to the desired fair rates. Each flow shaper process shapes the transmission rates based on local measurements driving them to the desired fair rates. The processes are efficient and lend themselves into ASIC and network processor unit implementations.

1. Field of Invention
The present invention relates to a method and apparatus for adaptive allocation of fair bandwidth in the links attached to routers of a backbone network comprising edge routers, core routers and links serving a plurality of flows from a plurality of Quality of Service (QoS) classes, so as to meet the end-to-end QoS requirements of each flow, avoid network congestion and utilize the network resources optimally.
2. Description of Prior Art
A backbone (communication) network comprises a plurality of edge and core routers interconnected by a plurality of links facilitating data communication between end user applications running in user computer devices at the user premises. The user devices, which comprise the end sources and the end destinations of the data traversing the backbone network, are connected to the edge routers by access links. The edge routers, which are connected to the user devices on one end, are also connected to core routers by core links on the other end. The core routers, however, are connected by core links only to other routers (either core or edge routers). Some enterprise backbone networks, e.g., Intranets, and public backbone networks, e.g., the Internet, comprise multiple network domains, where each network domain could utilize a different switching and routing protocol such as Internet Protocol (briefly IP), Frame Relay (briefly FR), Asynchronous Transfer Mode (briefly ATM), Multi-Protocol Label Switching (briefly MPLS) and Generalized Multi-Protocol Label Switching (briefly GMPLS). Since almost all user end applications communicate by IP, almost all edge routers support IP routing and switching.
Most user applications utilize Transport Control Protocol (briefly TCP) and User Datagram Protocol (briefly UDP) communication sockets, both generating IP packets. IP packets could be further encapsulated into network transmission units (briefly NTU) being transported through particular transport networks such as FR, ATM, MPLS and GMPLS. Efficient operation of a network requires tight control of the data flowing throughout the network. A data flow (briefly a flow) comprises all IP packets with the same QoS class flowing from a common source node, alternatively network number, to another common destination node, alternatively network number, along the same route. In accordance with IETF RFC 791, both, the source and the destination IP addresses, which also contain the respective network numbers, as well as the QoS class, are specified in the IP packet header. The QoS class is marked in the TOS header specifying performance requirements, e.g., minimum transmission rate, end-to-end packet delay and packet loss rate.
Flow control is the method of allocating the bandwidth of the network links between the flows and shaping the flow transmission rates accordingly. Flow control in a network is implemented by one or more distributed asynchronous and adaptive algorithms that are designed to meet some performance measures and to avoid network congestion. It is further desired from a flow control method to fully utilize the link bandwidths and to share the bandwidths between the flows in a fair manner as specified in reference [J. MO AND J. WALRAND, 2000]. Generally, fairness is subjective and several definitions exist. Therefore, it is of utmost importance to have a flow control method that can handle a wide range of fairness definitions. Although prior art provide a plurality of flow control methods, none of which handle multiple QoS classes in a manner that guarantee end-to-end QoS requirements for all flows, neither can they achieve fair bandwidth allocation between all flows and all QoS classes. The method of the present invention handles multiple QoS classes, guarantees end-to-end QoS requirement for every flow in any QoS class as well as allocates rates fairly in accordance to any given fairness definition within a wide range fairness notions.
Network flow controls could be practiced in several protocol layers such as the OSI network layer (e.g., IP layer), the OSI transport layer (e.g., TCP, ATM, MPLS and GMPLS). Also, the control processes could be executed in network processor devices (routers and switches) and/or in end user computer devices. A significant design consideration for flow control is to select the OSI layer. Prior art fair flow controls that are executed in network processor devices and handle a plurality of QoS classes, are applicable only in Virtual Circuit (VC) switched networks such as ATM (see U.S. Pat. Nos. 5,734,825; 5,966,381; 5,991,268; 6,185,187; 6,615,271; 6,324,165; 6,766,387; and 6,769,043). One embodiment of the method of the present invention that is executed in network processor devices controls the flows at the IP packet level rather than at the ATM cell level. It is also applicable to almost any transport network for the reasons explained herein. The generic format of the data traversing the network is dictated by the Application Program Interface (API) utilized in the user devices for networking applications. The two dominant APIs, which are not likely to change in the foreseeing future, are TCP and UDP sockets, both injecting IP data packets into the networks. Although IP packets could be encapsulated further into FR, ATM, MPLS or GMPLS NTUs, controlling the flows at the IP packet level is more general than controlling those at the NTU level since NTU format could change along the various network domains. Such a variety of domains would require a complex combination of flow control types, rather than a single generic one at the IP packet level. The latter is particular important for the Internet network and for multiple-domain enterprise networks.
Another significant design consideration is the scope of the flow control method. Some prior art fair flow controls that are executed in network processor devices and handle a plurality of QoS classes are limited to specific network topologies such as a metropolitan ring or a single switch (see U.S. Pat. Nos. 7,061,861 and 7,123,622). Some other prior art flow controls are limited to a single notion of fairness, known as max−min fairness (specified in reference [D. BERTSEKAS AND R. GALLAGER, 1992]), or a weighted variant of max−min fairness. The method of the present invention is applicable to any network topology and to a wide range of fairness notions including max−min fairness and proportional fairness as proposed in references [F. KELLY, A. MAULLOO AND D. TAN, 1998] and [J. MO AND J. WALRAND, 2000]. Hereinafter, the extended fairness notion is referred to as extended proportional fairness, or briefly fairness.
Whereas practical QoS requirements refer to end-to-end performance requirements, some prior art flow control guarantee only per-hop performance behavior (see reference [CISCO IOS, Release 12.0.] and the Differentiated Services QoS architecture, aka DiffServ [S. BLAKE, D. BLACK, M. CARLSON, E. DAVIES, Z. WANG AND W. WEISS, 1998]). Furthermore, each network processor router/switch requires manual configuration which should be coordinated across multiple network administrative domains and rely on a network provisioning tool. Another prior art method, the Integrated Services QoS architecture, aka IntServ, does guarantee end-to-end performance behavior but scarifies the scalability of the solution, hence applicable only for small networks. The method of the present invention is scalable, as DiffServ, and at the same time it also guarantees end-to-end performance, as IntServ. Furthermore, it adapts itself to the network traffic requiring only very simple configuration in the edge routers.
Some prior art network flow controls are executed in the end user devices rather than in the network processor devices. TCP flow control is the most common one and streaming application flow controls are others. Unlike the flow controls executed in ATM switches which adjust the transmission rates directly (known as rate-based flow control), prior art TCP flow controls are window-based methods which adjust the number of outstanding bytes that a flow can transmit, i.e., the window size. Prior art TCP window flow control are driven by the measurements of packet round trip times (briefly RTT); the resulting transmission rates and RTTs are implied and cannot be determined from the outset. Therefore, prior art TCP flow control suits only best-effort traffic flows. One embodiment of the method of the present invention also utilizes window-based flow control; however, it can also achieve pre-specified transmission rates and RTTs as required in the outset by the QoS classes. Prior art flow controls for streaming applications are rate-based and utilize the local network configuration of the user device to determine each rate target; these rates are not necessarily achievable.
In the quest for improving flow control, prior art research studies have studied the stability and the convergence of various flow control methods that can achieve fairness for a single flow QoS class known as the best effort class (see references [K. KAR, S. SARKAR AND L. TASSIULAS, 2002] [F. KELLY, A. MAULLOO AND D. TAN, 1998] [S. KUNNIYUR AND R. SRIKANT, 2003] [C. LAGOA, H. CHE AND B. A. MOVSICHOFF, 2004] [S. H. LOW AND D. E. LAPSLEY, 1999] [S. H. LOW, 2003] [L. MASSOULI AND J. ROBERTS, 2002] [J. MO AND J. WALRAND, 2000] [J. WANG D. X. WEI AND S. H. LOW, 2005]). These studies have inspired new fairness notions and have lead to better understanding of the stability issues involved in flow control. They have further contributed new rate-based and window-based flow controls that manifest fairness for best effort flows. Prior art rate-based fair flow controls are specified in references [K. KAR, S. SARKAR AND L. TASSIULAS, 2002] [F. KELLY, A. MAULLOO AND D. TAN, 1998] [S. KUNNIYUR AND R. SRIKANT, 2003] [C. LAGOA, H. CHE AND B. A. MOVSICHOFF, 2004] [S. H. LOW AND D. E. LAPSLEY, 1999] [L. MASSOULI AND J. ROBERTS, 2002] and U.S. Pat. Nos. 5,734,825; 5,966,381; 5,991,268; 6,185,187; 6,615,271; 6,324,165; 6,766,387; and 6,769,043. Prior art window-based fair flow controls are specified in references [J. MO AND J. WALRAND, 2000] D. WANG D. X. WEI AND S. H. LOW, and US patent applications 20050018617 and 20060050640. This prior art specifications are not addressing fair flow control for multiple flow QoS classes. Both embodiments of the method of the present invention, the window-based and the rate-based flow controls, do address extended proportional fairness for multiple flow QoS classes.
One shortcoming of prior art TCP flow control is that fairness, which is manifested in the case of single flow QoS class, breaks in the presence of non-conforming flows such as streaming application, e.g. RTSP, reference [H. SCHULZRINNE, A. RAO AND R. LANPHIER, and MMS (Microsoft media services]. Another shortcoming is that network congestion can emerge unless another protocol, known as congestion avoidance and implemented by an active queue management (AQM) module, is utilized (see references [D. CLARK AND W. FANG, 1998] [S. FLOYD AND V. JACOBSON, 1993] [V. MISRA, W. GONG AND D. TOWSLEY, 200] [Ref 19]). Currently, congestion avoidance is utilized by TCP but not by most of the streaming applications. Both shortcomings are addressed by the method of the present invention.
A common prior art rate-based traffic shaper, which is implemented in most current routers, is known as token bucket (see reference [A. K. PAREKH AND R. G. GALLAGER, 1993]). Token bucket is also utilized by one embodiment of the method of the present invention.

Method and apparatus for fair flow control and congestion avoidance supporting multiple QoS class requirements


An improved method for manufacture of coated fiber material, for example a composite fly fishing line, is disclosed. The method includes coating fiber of a first material with a hot melt adhesive material. For fly lines, indices of refraction of the materials are preferably selected so that the finished product is substantially transparent absent addition of pigment. The coated fiber material is exposed to electron beam treatment to improve the physical profile of the coating.

Hydrophobic synthetic materials are known to be well adapted as fishing line, netting and the like, and, more particularly, composite lines made from such materials have been heretofore suggested and/or utilized for buoyant fly fishing lines.
For fly fishing (or casting), buoyant lines are often utilized. Such lines must have a specific gravity of less that about 1.15 or the surface tension of a still body of water will not be sufficient to keep the line afloat. However, since both the end of the leader and the fly (or lure) attached to the line are light weight, substantially all of the mass required for propelling, or casting, the fly to a desired position on the water is necessarily in the fly line itself. Moreover, while sufficient mass is required, bulk (cross-sectional size) of the line is desirably minimized to avoid undue wind resistance when casting.
Buoyant composite lines heretofore known and/or utilized have included lines having a braided nylon filament core with a vinyl plastisol coating, with the coating having microspheroids blended thereinto to promote buoyancy. Lines having a core made of the fiber known as "KEVLAR" with a polyester urethane coating which is foamed to provide a multiplicity of air pockets to promote buoyancy have also been illustrated (see, for example, U.S. Pat. No. 3,043,045 and the article by A. J. Hand appearing in the March 1988 issue of Rod and Reel).
Floating fly lines such as those heretofore known have always exhibited, because of the materials and/or methods utilized in their manufacture, at least some degree of opaqueness, transparent or substantially transparent floating fly lines being thus unknown.
From the foregoing, it is apparent that a fly fishing line having a specific gravity which is low enough so that the line remains buoyant and lands consistently lightly on the surface of the water, while yet providing sufficient mass to maintain desired casting characteristics and cast distance, is in demand. Such a line preferably optimizes air resistance characteristics during casting by reducing line bulk, is durable and less subject to hardening and cracking over time (due, for example, to migration of plasticizers from the line coating material), and is substantially free of abrasive surface characteristics. In many uses, a substantially clear, or transparent, floating fly line would be highly desirable to minimize the obtrusiveness of the fly line on the water, for example where low water levels are present and thus line presentation without substantial disturbance of fish is difficult at best.
Moreover, methods and polymeric materials, such as vinyl plastisols, utilized for a wide variety of fabric and substrate coating applications are known and/or utilized. However, many require long periods of exposure of the coating after application to elevated temperatures (usually above about 350.degree. F.) to cure the coating. Difficulties are inerrant therein, for example when the fabric or substrate is heat sensitive. Many such coatings may also become brittle over time, stiffen with low temperature exposure, are solvent sensitive, and are subject to separation from their underlayment. Further improvement could thus be utilized.

Method of manufacture of coated fiber material such as a fly line


The disclosed technology reveals a hierarchical policy network, for use by a software agent, to accomplish an objective that requires execution of multiple tasks. A terminal policy learned by training the agent on a terminal task set, serves as a base task set of the intermediate task set. An intermediate policy learned by training the agent on an intermediate task set serves as a base policy of the top policy. A top policy learned by training the agent on a top task set serves as a base task set of the top task set. The agent is configurable to accomplish the objective by traversal of the hierarchical policy network. A current task in a current task set is executed by executing a previously-learned task selected from a corresponding base task set governed by a corresponding base policy, or performing a primitive action selected from a library of primitive actions.

The subject matter discussed in this section should not be assumed to be prior art merely as a result of its mention in this section. Similarly, a problem mentioned in this section or associated with the subject matter provided as background should not be assumed to have been previously recognized in the prior art. The subject matter in this section merely represents different approaches, which in and of themselves may also correspond to implementations of the claimed technology.
Deep reinforcement learning has demonstrated success in policy search for tasks in domains like game playing and robotic control. However, it is very difficult to accumulate multiple skills using just one policy network. Knowledge transfer techniques like distillation have been applied to train a policy network both to learn new skills while preserving previously learned skills as well as to combine single-task policies into a multi-task policy. Existing approaches usually treat all tasks independently. This often prevents full exploration of the underlying relations between different tasks. The existing approaches also typically assume that all policies share the same state space and action space. This assumption precludes transfer of previously learned simple skills to a new policy defined over a space with differing states or actions.
When humans learn new skills, we often take advantage of our existing skills and build new capacities by composing or combining simpler ones. For instance, learning multi-digit multiplication relies on the knowledge of single-digit multiplication; learning how to properly prepare individual ingredients facilitates cooking dishes based on complex recipes.
Inspired by this observation, the disclosed hierarchical policy network can reuse previously learned skills alongside and as subcomponents of new skills. It achieves this by discovering the underlying relations between skills.
The disclosed systems and methods do not assume that a global task can be executed by only performing predefined sub-tasks. For the disclosed multi-task reinforcement learning (RL) with multi-level policy, global tasks at a lower-level layer may also be used as sub-tasks by global tasks carried out at higher levels.
Complex policies often require the modeling of longer temporal dependencies than what standard Markov decisions processes (MDPs) can capture. Hierarchical RL introduces options, or macro options, on top of primitive actions to decompose the goal of a task into multiple subgoals. In hierarchical RL, two sets of policies are trained: local policies that map states to primitive actions for achieving subgoals, and a global policy that initiates suitable subgoals in a sequence to achieve the final goal of a task. This two-layer hierarchical policy design significantly improves the ability to discover complex policies which cannot be learned by flat policies. However, two-layer hierarchical policy design also makes some strict assumptions that limit its flexibility: a task's global policy cannot use a simpler task's policy as part of its base policies; and a global policy is assumed to be executable by only using local policies over specific options. It is desirable to not impose these two limiting assumptions.
An opportunity arises to train a software agent to employ hierarchical policies that decide when to use a previously learned skill and when to learn a new skill. This enables the agent to continually acquire new skills during different stages of training, reusing previously learned skills alongside and as subcomponents of new skills. Global tasks at a lower-level layer may also be used as sub-tasks by global tasks carried out at higher levels. The disclosed technology also includes encoding a task with a human instruction to learn task-oriented language grounding, as well as to improve the interpretability of plans composed by the disclosed hierarchical policies.

Hierarchical and interpretable skill acquisition in multi-task reinforcement learning


A louver with a slidable face plate may be used to direct fluid flowing through the louver in a desired direction (e.g. right or left) Vanes of the louver may include pinions that couple to rack gears of a housing and a face plate. Sliding the face plate may rotate louver vanes so that fluid flowing through the louver is directed in the desired direction. The face plate may also be rotatively mounted to the housing so that the face plate has a limited amount of rotational movement. Rotating the face plate may allow control of direction of fluid flow through the louver in directions other than the direction controlled by sliding the face plate (e.g. up and down).

1. Field of Use
This invention relates generally to air conditioning systems, and more particularly to a louver for directing and maintaining air flow from a vent in a desired direction.
2. Description of Related Art
Louvers may be used to direct and control fluid flow from a system in a desired direction. Louvers may also control an amount of fluid that flows from the system. Louvers may be used in an automobile ventilation system to control the direction that air flows when the air exits the ventilation system. Louvers may be used in building ventilation systems. Louvers may also be used in a number of other applications, including but not limited to, controlling an amount of light that enters a window or aperture, and controlling liquid flow through a system.
A louver may include a number of louver vanes that allow fluid passing through the louver to be directed in a desired direction (e.g., right or left, or up and down). Louvers may include a mechanism that allows the direction of the vanes to be simultaneously adjusted. Typical mechanisms require that the vanes of the louver include linking structure that allows all of the vanes to simultaneously move when an actuator is moved. One type of louver includes a wheel actuator. Another type of louver includes a lever actuator. When the actuator is rotated (a wheel actuator) or moved (a lever actuator) the directional position of louver vanes are changed. The linking structure may require that the vanes be placed within a louver body in a particular order. The need for particular vane structures may increase complexity, assembly cost, and number of individual parts needed to form the louver.
A louver may include a mechanism that allows the louver to be rotated so that fluid flowing through louver is directed in a first or second direction (e.g., up and down, or right and left). Typically, a rotational portion of the louver allows control of air flow in a direction that is substantially perpendicular to control of air flow provided by positional adjustment of louver vanes. For example, if louver vanes allow air flow to be adjusted in a left and right direction, a rotational portion of the louver may allow the air flow to be controlled in an up and down direction. In some louver embodiments, such as louvers for building ventilation systems, louvers may not include rotational portions.
A louver with a rotational portion may include projections and grooves on mating rotational and stationary portions of the louver. The projections and grooves may provide interlocking engagement that holds the rotational portion of the louver in a fixed position relative to the stationary portion of the louver. The interlocking engagement may inhibit unintentional movement of the rotational portion of the louver due to vibrational forces or other forces applied to the louver. U.S. Pat. No. 5,538,470 issued to Norbury et al., which is incorporated by reference as if fully set forth herein, describes a louver with a rotational portion that interlocks with a stationary portion.
A louver may be used to diffuse and direct fluid exiting a vent of a ventilation system in a desired direction. A louver may include a rack and pinion system. The rack and pinion system may allow louver manufacturers to mold or machine louver components that are easy to assemble. Louvers that utilize rack and pinion systems may have fewer individual parts than conventional louver designs. The components of a louver may be easily, quickly and efficiently assembled together to produce a louver.
In a louver embodiment, the louver includes a face plate or bezel, a first housing, louver vanes and a second housing. The face plate and the first housing may include rack gears that engage pinions of the louver vanes when the face plate and first housing are joined together.
In a louver embodiment, the louver includes a face plate, a first housing, and louver vanes. The louver vanes include axles that fit within holders. The holders may be, but are not limited to, recesses or retainers of the first housing. The face plate includes at least one rack gear that engages pinions of the louver vanes. When the face plate is laterally moved relative to the first housing, the rack gear rotates the pinions so that the louver vanes rotate. In an alternate embodiment, axles of louver vanes are placed within holders in the face plate. The holders may be, but are not limited to, recesses or retainers. The first housing includes a rack gear that engages pinions of the louver vanes. When the face plate is laterally moved relative to the first housing, the rack gear rotates the pinions so that the louver vanes rotate. As the vanes rotate, the vanes laterally translate along with the face plate.
Conventional louver designs typically include linking structures attached to louver vanes that allow the vanes to simultaneously move when a wheel, lever or other actuator is engaged. The connecting links may require that each vane of the louver be different from other vanes. The connecting links may make assembling a louver difficult and/or time consuming. The use of a rack and pinion system to allow simultaneous movement of louver vanes may allow a face plate of the louver to be the actuator of the louver. The use of the face plate as the actuator provides a large surface for a user to contact so that a user may contact and adjust the louver without needing to visually check operation of the louver.
Elimination of a separate component actuator from a louver design may expand possibilities of face plate styles. The use a face plate to control positions of louver vanes may remove design restrictions that limit face plate styles of conventional louvers due to space restrictions associated with louver vane actuators and linking structures. Various grid patterns in conjunction with a crown, dome, flat, square, round, oval or other style of face plate body may be used. The face plate may be free of vane actuator mechanisms that protrude from the plate and mar or otherwise influence the aesthetic appearance of the louver and system to which the louver is attached.
Use of a rack and pinion system of louver movement may allow all louver vanes of the louver to be substantially identical. Having substantially identical louver vanes may simplify the louver design, may reduce inventory requirements, and may reduce time and labor needed to assemble louvers. The simplified louver design may reduce the possibility of louver failure. The louver vanes may include domed surfaces that contact other louver body surfaces to inhibit rattling of the vanes due to vibration during use.
An advantage of the louver is that a frame of the louver is used to change the directional flow of forced air through the louver. An external face of the louver is the activation mechanism of the louver. The louver requires no connecting link mechanism to each vane or separate component actuator that extends above the louver face to allow for adjustment of vane position. The face provides a user with a large surface to contact or grasp when the user adjusts the position of the louver vanes.
Another advantage of the louver is that each louver vane may be substantially identical to other louver vanes. Having substantially identical louver vanes may reduce the number of distinct parts needed to assemble a louver, may simplify assembly of the louver, and may reduce assembly time needed to form a louver. The reduction of the number of distinct parts needed to produce a louver may simplify and reduce the expense of molds that produce the components of the louver. In some louver embodiments, louver vanes may not be identical. For example, in a louver embodiment, end louver vanes have wider blades than central vanes of the louver so that the end vanes contact surfaces of a louver housing when a face plate of the louver is fully extended in a first or second direction. The ability to use louver vanes of varying widths may allow for the use of louver vanes that are sized to fit a louver of a specific length with a louver that has a longer length.
An advantage of the louver is that the louver may have a position indicator that indicates when the louver is in a reference position. Typically, the reference position indicates when a face plate of the louver is at, or substantially at, a mid-point position relative to an unmovable portion of the louver or relative to an opening in a ventilation system. When the position indicator is in an engaged position, the louver vanes may be positioned substantially perpendicular to a rack of the louver so that fluid flow through the louver is directed substantially straight out of the louver. In some embodiments, movement of a face plate of the louver may allow vanes of the louver to be closed or substantially closed to inhibit fluid flow through the louver. In some embodiments, the louver vanes may be moved to a closed position by linearly moving a face plate fully away from the engaged position in a first direction or in a direction that is opposite to the first direction. Some louver embodiments may include position indicators that are not located at or substantially at a mid-point position of the face plate.
Further advantages may include that the louver is sturdy, strong, compact, durable, light-weight, simple, safe, efficient, versatile, ecologically compatible, energy conserving, and reliable; yet the louver may also be easy to manufacture, install, operate and maintain.