An auxiliary apparatus for sampling blood serum according to the invention comprises a disklike flattening member having a flat surface and capable of flattening a separation surface of a blood serum separating medium contained in a sample container by urging the flat surface against the separation surface, a mounting member having a cylindrical shaft for lowering the flattening member through the blood serum contained in the sample container to thereby mount the flattening member in the sample container such that the flat surface of the flattening member horizontally urges the separation surface of the blood serum separating medium, and means for securing a space which permits a sampling/dispensing tip capable of sampling and dispensing the blood serum, to be inserted into the sample container, by detaching the cylindrical shaft from the flattening member and taking the cylindrical shaft out of the sample container, after the flattening member is mounted in the sample container by the mounting member.

This invention relates to an auxiliary apparatus to be used at the time of sampling only blood serum from a centrifuged blood sample.
Before performing various types of blood tests such as a biochemical analysis, etc., blood contained in a specimen container such as a test tube is subjected to a centrifugal treatment, and then blood serum contained therein is sampled and dispensed into several test vessels.
In general, the centrifuged blood sample in a test tube is definitely separated into blood serum and a blood clot by means of a separating medium such as silicon. More specifically, in the test tube, the centrifuged blood sample is separated into the blood serum, the separating medium and the blood clot arranged in this order from above.
To sample the blood serum in the test tube, a sampling/dispensing tip with a sharply tapered, hollow and conical tip portion is inserted into the test tube from above. When the tip portion reaches the blood serum, the tip sucks only the blood serum using an air sucking mechanism, etc., and then is raised and kept at a raised position.
After the sampling operation, the sampling/dispensing tip is shifted to a predetermined position, where the blood serum contained therein is discharged (i.e. dispensed) into several predetermined test vessels.
The blood sample components (i.e. the blood serum, the blood clot, the separating medium) contained in the test tube after the centrifugal treatment do not always show clearly separated states, but may show abnormal states.
FIGS. 15 to 17 show such abnormal states of blood sample components (blood serum 2, a blood clot 3, a separating medium 4) contained in a test tube 1. FIG. 15 shows a case where the separating medium 4 has a separation surface A with irregularities, which contacts the blood serum 2. FIG. 16 shows a case where a separation surface B inclines by a certain angle relative to the axis 0 of the test tube 1. FIG. 17 shows a case where the separation surface of the separating medium 4 is relatively flat and horizontal, and fibrin 5 which may cause clogging of a sampling/dispensing tip (not shown) is floating in the blood serum 2.
When the separating medium 4 assumes a state as shown in FIGS. 15 or 16, the level at which the separation surface of the separating medium 4 is formed cannot definitely be determined. In other words, the level of the separation surface of the separating medium 4 or that of a deepest portion of the blood serum 2 will assume different values when it is sensed by a sensor (not shown), etc. several times. If the sampling/dispensing tip is lowered to a tip insertion limit set on the basis of such an indefinite sensed level, a lower open end portion of the tip may well thrust into the separating medium 4 and be clogged with the medium.
To avoid this, the prior art takes a measure, for example, to set the tip insertion limit to a level much shallower than the sensed level. This measure, however, makes it impossible to sample all blood serum 2 in the test tube 1, and inevitably limits the effective use of valuable blood serum obtained by a centrifugal treatment.
On the other hand, in the case of FIG. 17 where fibrin is floating in the blood serum 2, the fibrin may be sucked into the open end of the sampling/dispensing tip to thereby clog the same. As a result, it is possible that clogging of the tip will start immediately after the sampling of the blood serum 2. In this case, the aforementioned measure to set the insertion limit of the tip to a much shallower level is quite useless.

Auxiliary apparatus for sampling blood serum


A utility bag has an elongate flexible sleeve having an upper end and a lower end and front and back sides extending between the upper and lower ends, the upper end having a first aperture therein for access to a first cavity defined by the front and back sides and the lower end whereby articles may be placed through the first aperture into and removed from the first cavity, a flexible releasably securable flap provided at the first end of the sleeve for releasable closure of the first aperture. At least one flexible expandable pocket is mounted externally to the front side of the sleeve and expandable by pleating, whereby access may be had to a second cavity within the expandable pocket when the first cavity is full of material being carried and the sleeve is thereby firmly cylindrical, the first and second cavities for storing small articles therein, the expandable pocket having thereon a second releasably securable flap for releasably closing a second aperture for access to the second cavity, mounting straps at the upper and lower ends of the sleeve for releasable mounting of the utility bag to an elongate member, such as a pet leash.

Many cities have by-laws requiring dog owners to clean up after their pets. Thus, in order to avoid possible fines, it is advantageous that a dog owner keep plastic bags to hand.
In the prior art addressing this problem, applicant is aware of U.S. Pat. No. 5,441,017 which issued to Lindsay on Aug. 15, 1995. Lindsay discloses a cylindrical dispenser for dispensing plastic bags from a roll, the cylinder mountable to a pet leash. The cylinder may be rigid or may be flexible. Although, Lindsay teaches that the dispenser is flexible, it is likely that the dispenser would be sewn integrally with the line portion of the leash, apparently to overcome the stated disadvantage that the bags from the roll of bags held in the dispenser would not dispense quite as easily from a flexible cylinder and would not provide as good a handle as a rigid cylinder. The structure of Lindsay is dictated by the cylindrical roll of bags he teaches vending from the bag dispenser. Thus, the dispenser, if flexible, is integral with the leash in an attempt to make the dispensing structure semi-rigid.


The switch mode power supply includes a switching cell SC controllable cyclically and including only one inductive element L and several individually selectable outputs. During each conduction cycle, a total power level corresponding to the sum of the individual power levels respectively required by all the outputs OUTi during this cycle is injected into the inductive element L, the outputs requiring a non-zero individual power level are selected successively and in a predetermined order that is identical for all the cycles, and, at each selected output, the corresponding individual power level is produced.

1. Technical Field of the Invention
The present invention relates to switch mode power supplies and more specifically to those having only one inductive element and several regulated outputs. The invention is advantageously applicable to, but not limited to, portable systems powered by battery, in particular, but not exclusively, wireless remote communication system terminals, for example, cellular mobile telephones.
2. Description of Related Art
Integrated systems for controlling the power aspects of portable applications (battery operated) increasingly require different output supply voltages to be regulated. The traditional solution consists in creating a regulated supply from the power supply using a linear regulator. This regulator uses an external capacitor to fulfill its function. Further, as many linear regulators are used as there are outputs to be regulated. The main drawback of this type of regulator is its low efficiency.
To address this problem of low efficiency, switch mode power supplies, also known as "DC—DC converters," are used. Efficiency levels are then close to 85 to 90%, while under the same conditions, a linear regulator would have an efficiency of only 50%. However, the main drawback of a switch mode power supply is the need for both an external capacitor and an external inductive element.
To regulate several outputs, it is conceivable to use several switch mode power supplies. However, this then assumes using as many external inductive elements, the main drawback of such an approach being the cost of such an inductive element and the large surface area taken up by it on the printed circuit board.
It has also been considered to use switch mode power supplies capable of regulating several separate outputs using only one inductive element. The main solutions that exist in this field then rely on a time-division multiplexing of the power delivered to the various outputs. In other words, the various outputs to be regulated are fed respectively during successive conduction cycles.
The prior art solutions exhibit a number of drawbacks.
One of these concerns the implementation of a "discontinuous conduction" type regulation on the various outputs. Also, this type of conduction gives rise to high peak currents in the inductive element, thus resulting in a significant drop in efficiency (65 to 75% instead of 85 to 90%). Furthermore, to withstand the very high peak currents, the saturation current of the inductive element must be higher. Consequently, an inductive element having a larger volume must be used, which is a major constraint for portable applications. Furthermore, this type of conduction produces significant ripple on the regulated output voltage supplies. Another drawback concerns the use of complex digital functions taking up considerable surface area. These functions are for controlling the power delivered at the various outputs according to given algorithms. Another drawback concerns the fact that the conduction is, for most of the existing solutions, a pulse frequency modulation type conduction. This principle leads to significant and uncontrollable spectral pollution. Also, although in some applications, such as applications for supplying power to microcomputers or liquid crystal display screens, such a pollution is not critical, this pollution is unacceptable in other portable applications, such as cellular mobile telephones, and this means that switch mode power supplies using frequency modulation cannot be used.

Switch mode power supply having only one inductive element an several outputs and method of controlling same


An integrally formed bottle or jug carrier strap for securely and comfortably carrying a pair of bottles or jugs by their neck. An elongate grip has rings at each end and a neck-retaining collar attached to the inner circumference of each ring. Scores on the underside of each ring cause the ring to break at the score when the rings are deformed, permitting the bottle or jug to easily be removed from the carrier strap.

This invention relates to an inexpensive, integrally formed bottle or jug carrier strap for securely and comfortably carrying a pair of bottles or jugs by their neck.
Bottles and other liquid containers, in particular gallon containers, weigh a substantial amount. For example, a filled one gallon milk jug weighs approximately 8.3 pounds. Shoppers wishing to purchase multiple one gallon containers generally must use each hand to carry each container.
Bottle carriers which enable bottles to be carried by their neck are well known in the art, as shown by the following:
Erickson U.S. Pat. No. 4,235,468 discloses an integrally formed bottle carrier wherein the bottle necks are engaged in and supported by a substantially keyhole shaped opening. The bodies of the bottles themselves are clustered and secured by a plurality of integrally formed depending supports.
Erickson U.S. Pat. No. 4,471,987 describes and claims a bottle carrier capable of carrying a plurality of bottles in a close cluster using a connecting band which is separated and apart from a bottle-engaging means mounted around the necks of the bottle.
Erickson U.S. Pat. No. 4,249,766 describes a two-element strapping mechanism, comprising a connecting band which is separated and apart from a bottle-engaging means around the bottle necks for carrying the bottles.
Erickson U.S. Pat. No. 4,093,295 describes an integrally-formed bottle carrier for carrying a row of bottles side by side by their necks. The bottles are locked into and removed from a plurality of uniformly based split collars which are mounted within individual frames interconnected in a single row by one or more longitudinally extending rigid bridging bars. The split collar is substantially keyhole shaped having splits in a longitudinal direction. Oppositely disposed handles are also provided for.
Erickson U.S. Pat. No. 4,090,729 describes a strap for carrying a single bottle by the neck within a split ring opening within a frame member.
The above-mentioned prior art devices each rely upon a substantially keyhole-shaped split collar. Insertion and removal of a bottle is made by forcing open the angular portion of the collar. The bottle carriers are lifted by various means, including finger openings in the top of the device or handles which are pivotable upwardly.


A method for communicating across first and second frequency domains of an integrated microchip is provided. The method initiates with determining a clock ratio between the first frequency domain and the second frequency domain. The first frequency domain is associated with a faster clock cycle. Then, a synchronizing signal based upon the clock ratio is generated. The synchronizing signal coordinates communication of data between the first and second frequency domains. Next, the data is transferred between respective frequency domains according to the synchronizing signal. A microchip and a system enabling synchronous data transfer across different frequency domains are also provided.

1. Field of the Invention
The present invention relates generally to microprocessors, and more specifically to a method and apparatus for the transfer of data across disparate within a micro-chip.
2. Description of the Related Art
In a multi-processor environment, it is important to transmit data between processors. For example, system on a chip (SoC) technology enables the packaging of all the parts and electronic circuits for a system on an integrated circuit. This technology may be used for cell phones, digital cameras, and other consumer electronics. Here, multiple processors may be in communication with each other. The highly integrated micro-chips operate various parts of the chip at different frequencies. The conventional approach to the communication across different frequency domains is to treat each clock as completely independent and the interface as completely asynchronous.
FIG. 1 is a simplified schematic of an apparatus for accommodating the multiple clock domains associated with a system on a chip. Region 100 is associated with clock domain A while region 102 is associated with clock domain B. Input data X 106 comes into storage cell F1 108 operating at a frequency associated with clock domain A. Double synchronizer 104 includes storage cells F2 110 and F3 112 which are driven at a frequency associated with clock domain B. The configuration of double synchronizer 104 enables protection from a metastable condition occurring between storage cell F2 110 and F3 112 through a logic threshold adjustment.
Therefore, between each clock domain three types of storage cells are necessary and the special design, i.e., design complexity, of the double synchronizer configuration and storage cells F2 110 and F3 112. Furthermore, the amount of time associated with converting input data X to output data Y is non-deterministic. That is, due to clock skew between clock domain A and clock domain B the timing can not be determined. Thus, for scan testing or debugging purposes deterministic behavior is achieved by forcing clock A and clock B to be the same through special test circuitry. However, this does not produce the actual functionality of operating conditions as the timing of events are being changed. Therefore, the chip may pass during the system debug but fail during functional testing. Another shortcoming of this technique is the relatively high overhead and transfer latency associated with the technique.
In light of the foregoing, it is desired to implement a design and scheme to communicate across frequency domains with a minimum of overhead with respect to the design and the latency of the data transfer across the frequency domains.

Method for generating a synchronization signal based on the clock ratio between two clock domains for data transfer between the domains


In a conventional manufacturing process where the number of manufacturing processes is reduced to form a semiconductor layer of a channel etch-type insulating gate-type transistor and source-drain wires in one photographic etching processing using half-tone exposure technology, the manufacturing margin is narrow, lowering the yield if the distance between the source and the drain wire shortens.

1. Field of the Invention
The present invention relates to a liquid crystal display device with a color image display function, and in particular to an active-type liquid crystal display device.
2. Description of Related Art
Televisions and various other image display devices which have a liquid crystal display of 5 to 75 cm in diagonal length are commercially available in mass quantity through the progress in recent years in micro-fabrication, liquid crystal material, high-density packaging technology, and other such technologies. In addition, color displays can easily be obtained by forming an RGB color layer on one of the two glass substrates composing the liquid crystal panel. In particular, in a so-called active liquid crystal panel with a switching element inside each pixel, there is little cross-talk, the response rate is high, and images with a high contrast ratio are guaranteed.
For these liquid crystal displays (liquid crystal panels), the matrix organization generally comprises around from 200 to 1200 scan lines and 300 to 1600 signal lines, but recently increases in screen size and definition are progressing simultaneously in response to the increase in display capacity.
FIG. 9 shows a state of liquid crystal panel mounting in which electric signals are provided to an image display part using packaging means such as COG (Chip-On-Glass) in which a conductive adhesive is used to connect a semiconductor integrated-circuit chip 3 for supplying a drive signal to electrode terminals 5 for scan lines formed on one of the transparent insulating substrates composing a liquid crystal panel 1, for example a glass substrate 2, or TCP (Tape-Carrier-Package) for fixing a TCP film 4, to electrode terminals 6 for signal lines using pressure and a suitable adhesive including a conductive medium using, for example, a thin polyimide-base plastic film with a copper foil terminals plated with gold or solder as a base. Herein, both of these mounting methods are shown at the same time for convenience, but in actual practice, either method may be arbitrarily selected.
Wire paths connecting the interval between the pixels in the image display area positioned nearly in the center of a liquid crystal panel 1 and electrode terminals 5 and 6 for scan lines and signal lines are 7 and 8, and do not necessarily need to be constructed of the same conductive material as the electrode terminals 5 and 6.9 is a color filter or an opposing glass that is another transparent insulating substrate having transparent conductive opposing electrodes on its opposing side, which is common to all the liquid crystal cells.
FIG. 10 shows an equivalent circuit of an active-type liquid crystal display device with an insulating gate-type transistor 10 disposed as a switching element at each pixel. In the figure, 11 (7 in FIG. 9) is a scan line, 12 (8 in FIG. 9) is a signal line, 13 is a liquid crystal cell, and the liquid crystal cell 13 is treated as a capacitance element electrically. The elements drawn with solid lines are formed on the glass substrate 2, one of the glass substrates composing the liquid crystal panel, and opposing electrode 14 drawn with dotted lines common to all the liquid crystal cells 13 is formed on the main surface opposite the other glass substrate 9. If the "off" resistance of the insulating gate-type transistor 10 or the resistance of the liquid crystal cell 13 is low, or if gradation in the displayed image is to be emphasized, circuitry means may be introduced such as adding an auxiliary storage capacitor 15 in parallel with the liquid crystal 13 as a load to increase the time constant thereof. 16 is a storage capacitor line forming a mother line common to the storage capacitors 15.
FIG. 11 shows a cross-sectional view of the essential part of an image display part of a liquid crystal display device. The two glass substrates 2 and 9 composing the liquid crystal panel 1 are formed separated by a specified distance of several μm by a spacer material (not illustrated) such as pillar-shaped resin spacers formed on a color filter 9, plastic fibers, or plastic beads, and that gap is a closed spaced sealed by a sealing material and an end-sealing material made from an organic resin (neither of which are illustrated) at the periphery of the glass substrate 9, and the gap is filled with liquid crystal 17.
To obtain a color display, a thin organic film about 1 to 2 μm thick including either a dye or pigment or both called a color layer 18 is deposited on the closed space side of the glass substrate 9, providing a color display function, in which case the glass substrate 9 may also be referred to by the name a color filter (abbreviated as CF). Depending on the property of the liquid crystal material 17, a polarization plate 19 is attached to the top of the glass substrate 9 or the bottom of the glass substrate 2 or both, so the liquid crystal panel 1 functions as an electro-optical element. TN (Twisted-Nematic)-type liquid crystal material is currently used in most liquid crystal panels available commercially, and two polarization plates 19 are normally required. Although not illustrated, a back light source is disposed as a light source in the transmission-type liquid crystal panel, irradiating white light from below.
A thin polyimide-type resin film 20 about 0.1 μm thick, for example, formed on the two glass substrates 2 and 9 and in contact with the liquid crystal 17 is an alignment film for orientating liquid crystal molecules in a fixed direction. 21 is a drain electrode (wire) for connecting a drain of the insulating gate-type transistor 10 and a transparent conductive pixel electrode 22, and is often formed at the same time as a signal line (source line) 12. A semiconductor layer 23 is positioned between the signal line 12 and the drain electrode 21 and is described in further detail below. A thin Cr film layer 24 about 0.1 μm thick formed at the interface of the adjacent color layer 18 on the a color filter 9 is a light shield material for preventing external light from radiating on the semiconductor layer 23, the scan line 11, or the signal line 12. This is an established technology referred to as black matrix (abbreviated as BM).
Here, a description is given of the structure of an insulating gate-type transistor as a switching element and its manufacturing method. Two types of insulating gate-type transistors are currently used commonly, one of which will be introduced as a prior art example and be referred to as an etch-stop type. FIG. 12 is a plan view of a unit pixel of an active substrate (semiconductor devices for display devices) composing a conventional liquid crystal panel. Cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 12(e) are shown in FIG. 13. The manufacturing process thereof is described briefly below.
First, a first metal layer about 0.1 to 0.3 μm thick is deposited over the main surface of a glass substrate 2, product name 1737 manufactured by Coming, Incorporated, for example, about 0.5 to 1.1 mm thick as an insulating substrate with high transparency, chemical-resistance, and heat-resistance, and scan lines doubling as gate electrodes 11A and storage capacitor lines 16 are selectively formed using photosensitive resin patterns with micro-fabrication technology as shown in FIG. 12(a) and FIG. 13(a). The material for the scan line may be selected taking into consideration the combined properties of heat-resistance, chemical-resistance, hydrofluoric acid resistance, and conductance, though a metal with a high heat-resistance such as a Cr, Ta and an alloy thereof such as MoW is generally used.
While using Al (aluminum) as the material for the scan lines is reasonable for lowering the resistance value of the scan lines in response to the larger screens and higher definitions of liquid crystal panels, by itself, Al has a low heat-resistance, so adding an oxide layer (Al2O3) in anodization of the Al surface or laminating with Cr, Ta or Mo or a silicide thereof which are the said heat-resistance metals is currently the general technology in use. In other words, the scan lines 11 are constructed of one or more metal layers.
Next, a PCVD (plasma CVD) equipment is used to successively deposit three thin film layers about 0.3, 0.05, and 0.1 μm thick, for example, comprising a first SiNx (silicon nitride) layer 30 composing a gate insulating layer, a first amorphous silicon (a-Si) layer 31 composing a channel for an insulating gate-type transistor including almost no impurities, and a second SiNx layer 32 composing an insulating layer for protecting the channel, over the entire surface of the glass substrate 2, and micro-fabrication technology is used to selectively leave the second SiNx layer above the gate electrodes 11A narrower than the gate electrode 11A to form protection layers 32D as shown in FIG. 12(b) and FIG. 13(b), exposing the first amorphous silicon layer 31.
Continuing, the second amorphous silicon layer 33 including phosphorous, for example as an impurity, is deposited similarly about 0.05 μm thick, for example, over the entire surface using the PCVD equipment. Then, a thin film layer 34 of Ti, Cr, Mo, or the like, for example, is deposited as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 about 0.3 μm thick is deposited as a low-resistance wiring layer, and a Ti thin film layer, for example, is deposited as an intermediate conductive layer about 0.1 μm thick. Drain electrodes 21 of insulating gate-type transistors comprising a laminate of these three thin film layers 34A, 35A, and 36A, which are source-drain wire materials, and signal lines 12 doubling as source electrodes are selectively formed with micro-fabrication technology using photosensitive resin patterns as shown in FIG. 12(c) and FIG. 13(c). This selective patterning is made by successively etching the Ti thin film layer 36, the Al thin film layer 35, and the Ti thin film layer 34 using the photosensitive resin patterns used in forming the source-drain wires as masks, and then removing the second amorphous silicon layer 33 between the source-drain electrodes 12 and 21 to expose the protective insulating layers 32D as well as removing the first amorphous silicon layer 31 in other regions to expose the gate insulating layer 30. Because the second SiNx layers 32D (protective insulating layers, etch-stop layers), which are layers for protecting the channels, are thus present, and the etching of the second amorphous silicon layer 33 automatically ends, this manufacturing method is called etch-stop.
Source-drain electrodes 12 and 21 are formed partly (a few μms) overlapped on a flat surface with protective insulating layers 32D so that the insulating gate type transistors do not form offset structures. This overlapping is better when small, for it works electrically as parasitic capacitance. However, its practical value is only about 2 μms for it is determined by the overlay accuracy of mask aligners (exposure equipments), the accuracy of photo-masks, the expansion coefficient of glass substrates, and the temperature of glass substrates during exposure.
Furthermore, after removing the said photosensitive resin patterns, a SiNx layer about 0.3 μm thick is deposited over the entire surface of the glass substrate 2 similarly to the gate insulating layer as a transparent insulating layer using the PCVD equipment to form a passivation insulating layer 37, the passivation insulating layer 37 is selectively removed using photosensitive resin patterns with micro-fabrication technology to form openings 62 on the drain electrodes 21 and openings 63 on the scan lines 11 and openings 64 on the signal lines 12 outside an image display area to expose the drain electrodes 21, part 5 of the scan lines 11 and part 6 of the signal lines 12, respectively as shown in FIG. 12(d) and FIG. 13(d). Openings 65 are similarly formed on the electrode patterns bundled and in parallel with the storage capacitor lines 16 to expose part thereof.
Finally, ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide), for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and pixel electrodes 22 are selectively formed on the passivation insulating layer 37 containing the openings 62 using photosensitive resin patterns with micro-fabrication technology to complete the active substrate 2 as shown in FIG. 12(e) and FIG. 13(e). Part of the scan lines 11 exposed in the openings 63 may be used as the electrode terminals 5, and part of the signal lines 12 exposed in the openings 64 as the electrode terminals 6, and the electrode terminals 5A and 6A made from ITO on the passivation insulating layer 37 containing the openings 63 and 64 may be selectively formed as illustrated, but transparent conductive short lines 40 are ordinarily formed at the same time connected between the electrode terminals SA and 6A. The reason for this is so a high resistance can be made as a measure against static electricity by forming the interval between the electrode terminals 5A/6A and the short wires 40 into long-narrow striped forms to increase the resistance (not illustrated). Similarly, electrode terminals are formed on the storage capacitor lines 16 containing the openings 65, though a number thereof is not provided.
If wiring resistance of the signal wire 12 is not a problem, a low-resistance wire layer 35 made from Al is not necessarily required, in which case it is possible to simplify the layers of the source-drain wires 12 and 21 by selecting heat-resistant metal material such as Cr, Ta, or MoW. Ensuring an electrical connection with the second amorphous silicon layer using a heat-resistant metal layer is thus more important for the source-drain wires; the heat resistance of an insulating gate-type transistor is described in detail in Unexamined Patent Application Number H 7-74368 [i.e., 1995-74368] as an example of prior art. A region 50 (a right-slanting oblique portion) over which the storage capacitor line 16 and the drain electrode 21 are superimposed in a planar manner via the gate insulating layer 30 in FIG. 12 (c) forms a storage capacitor 15, though a detailed description is omitted here.
A detailed history of the five-mask process described above is omitted, but it is obtained as the result of streamlining the semiconductor islanding processing and decreasing the number of contact-formation processes. Photo-masking, which initially required seven to eight times, has been reduced to the current five layers by the introduction of dry etching technology, which greatly contributes to the decreasing process costs. It is a well-known target of development that lowering the process cost in the manufacture of the active substrate and the material cost in the panel assembly and module packaging processes is effective in lowering the production costs of liquid crystal display devices. To lower process costs, either process may be eliminated to make the process shorter, or inexpensive process development or replacement to inexpensive process is available. Here, four-mask process resulting in an active substrate with four photo-masks is described as an example of eliminating processes. The photo-etching process is eliminated by introducing half-tone exposure technology. FIG. 14 shows a plan view of a unit pixel in an active substrate corresponding to the four-mask process. The cross-section views of lines A-A′, B-B′ and C-C′ in FIG. 14(e) are shown in FIG. 15. As already mentioned, two types of insulating gate-type transistors are commonly in use. Here, a channel etch-type insulating gate-type transistor is selected.
First, a first metal layer about 0.1 to 0.3 μm thick is deposited on the main surface of the glass substrate 2 using the SPT or other vacuum film-depositing equipment similar to as done in the five-mask process, and the storage capacitor lines 16 and scan lines 11 doubling as the gate electrodes 11A are selectively formed using photosensitive resin patterns with micro-fabrication technology as shown in FIG. 14(a) and FIG. 15(a).
Next, three thin film layers comprising the SiNx layer 30 composing a gate insulating layer, a first amorphous silicon layer 31 composing a channel for an insulating gate-type transistor including hardly any impurities, and a second amorphous silicon layer 33 composing source-drain for an insulating gate-type transistor including impurities are successively deposited about 0.3 to 0.2 to 0.05 μm, for example, over the entire surface of the glass substrate 2 using the PCVD equipment. Next, a Ti thin film layer 34, for example, as a heat-resistant metal layer about 0.1 μm thick, an Al thin film layer 35 as a low-resistance wire layer about 0.3 μm thick, and a Ti thin film layer 36, for example, as an intermediate conductive layer about 0.1 μm thick, namely, source-drain wire material are successively deposited using the SPT or other vacuum film-depositing equipment. Drain electrodes 21 of insulating gate-type transistors and signal lines 12 doubling as source electrodes are selectively formed. But in this selective patterning, it is a major feature of the streamlined four-mask process to form photosensitive resin patterns 80A and 80B thinner than the 3 μm of source-drain wiring formation regions 80A(12) and 80A(21) with the channel formation region 80B (oblique portion) between the source-drain 1.5 μm thick, for example, as shown in FIG. 14(b) and FIG. 15(b) using half-tone exposure technology.
For such photosensitive resin patterns 80A and 80B, a positive photosensitive resin is ordinarily used in the production of substrates for liquid crystal display devices, so a black, that is, a thin Cr film is formed for the source-drain wire formation region 80A, a gray line and space Cr pattern is formed with a width of 0.5 to 1 μm, for example, for the channel region 80B, and for other regions, a photo-mask may be used to make them white, that is, remove the thin Cr film. It is possible to transmit about half of the photo-mask passing light from a lamp source because the lines and spaces are not resolved due to inadequate exposure resolution, so the photosensitive resin patterns 80A and 80B may be obtained in the gray region having a concave cross-section shape such as that shown in FIG. 15(b) corresponding to the residual film properties of the positive-type photosensitive resin. By forming a MoSi2 thin film, for example, rather than a Cr thin film slit in the gray region, a photo-mask with an equivalent function may be obtained.
After successively etching the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 using the said photosensitive plastic patterns 80A and 80B as masks to expose the gate insulating layer 30 as shown in FIG. 15(b), the photosensitive resin patterns 80A and 80B are decreased at least 1.5 μm by ashing means such as oxygen plasma, eliminating the photosensitive resin patterns 80B to expose the channel regions, and leaving the photosensitive resin patterns 80C (12) and 80C (21) unchanged only on the source-drain wire formation regions as shown in FIG. 14(c) and FIG. 15(c). Then, the Ti thin film layer, Al thin film layer, Ti thin film layer, second amorphous silicon layer 33A, and first amorphous silicon layer 31A are successively etched again using the reduced photosensitive resin patterns 80C (12) and 80C (21) as masks, and then the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm. After the metal layer is etched, the first amorphous silicon layer 31A is etched leaving around 0.05 to 0.1 μm, forming the source-drain wires, so the insulating gate-type transistor obtained with such a method is referred to as a channel-etch. The resist pattern 80A is reduced so as to be converted to 80C in the said oxygen plasma treatment, so it is desirable to strengthen the anisotropicity to suppress changes in the pattern dimensions. In further detail, RIE (Reactive Ion Etching) oxygen plasma treatment is desirable, and ICP (Inductive Coupled Plasma) or TCP (Transfer Coupled Plasma) oxygen plasma treatment with a higher density plasma source is even more desirable.
After removing the said photosensitive resin patterns 80C (12) and 80C (21), a second SiNx layer about 0.3 μm thick is deposited as a transparent insulating layer over the entire surface of the glass substrate 2 to make a passivation insulating layer 37 as same as prior five-mask process; openings 62, 63, and 64 are formed on the drain electrodes 21 and in regions to be formed for the electrode terminals for the scan lines 11 and for the signal lines 12, respectively using a photosensitive resin pattern with micro-fabrication technology as shown in FIG. 14(d) and FIG. 15(d); the gate insulating layer 30 and the passivation insulating layer 37 in the openings 63 are removed to expose part 5 of the scan lines; and the passivation insulating layer 37 in the openings 62 and 64 are removed to expose part of the drain electrodes 21 and part 6 of the signal lines. Similarly, openings 65 are formed on the storage capacitor lines 16 to expose part thereof.
Finally, ITO or IZO, for example, is deposited as a transparent conductive layer about 0.1 to 0.2 μm thick using an SPT or other vacuum film-depositing equipment, and transparent conductive pixel electrodes 22 containing the openings 62 are selectively formed on the passivation insulating layer 37 using a photosensitive resin pattern with micro-fabrication technology to complete the active substrate 2 as shown in FIG. 14(e) and FIG. 15(e). For the electrode terminals, transparent conductive electrode terminals 5A and 6A made from ITO are selectively formed on the passivation insulating layer 37 containing the openings 63 and 64.

Liquid crystal display device and its manufacturing method

Abstract: A 4-mask process proposal needless of half-tone exposure technology is constructed by streamlining the formation of scan lines and pseudo-pixel electrodes at the same time, both comprising a laminate of a transparent conductive layer and a metal layer, and the formation of the transparent conductive pixel electrodes through removing the metal layers on the pseudo-pixel electrodes at the time of the formation of the opening in the passivation insulating layer, as well as by reducing the formation process of the opening through removing a gate insulating layer also at the formation of semiconductor layers for channel-etch type insulating gate transistors.


Systems, methods, and computer-readable media for controlling data transmission in TCP subflows of a MPTCP connection based on monetary cost. A low cost link and a high cost link of TCP subflows of a MPTCP connection formed between a first MPTCP peer and a second MPTCP peer can be identified. A congestion level on the low cost link can be determined based on feedback from a TCP congestion control mechanism for the MPTCP connection. Further, whether to send a data packet over the low cost link of the high cost link based on the congestion level on the low cost link can be determined. As follows, the data packet can be sent over the low cost link connection if it is determined to send the data packet over the low cost link.

MPTCP provides the ability to simultaneously use multiple paths between two TCP peers. Using MPTCP extensions, a TCP application client and an application server, e.g. two MPTCP peers, can establish multiple TCP subflows over different access networks and split the data stream over those paths and links. This essentially offers the key benefits of better user experience in the form of both higher throughput and also increased resiliency to path failures.
Recently, standards bodies, e.g. the Internet Engineering Task Force (IETF), and researchers have analyzed the MPTCP protocol, RFC 6824, thoroughly and greatly improved performance of MPTCP connections established and maintained according to the protocol. One goal of improving the MPTCP protocol has focused on efficient utilization of links/TCP subflows to realize a higher aggregate application throughput.
However, one of the fundamental gaps in the protocol is the lack of awareness on the monetary cost associated with a given link. For example, one of the two access links used to establish MPTCP subflows may be a metered link where a customer pays for every octet of data transmission, e.g. an LTE link. Further, the other link may either be a link with no usage-based cost associated with it, or a link with a flat-rate cost, e.g. WiFi. In turn, consideration of incurring minimal costs to a user while still providing the best user experience in forming an MPTCP connection over such links is lacking in the current MPTCP protocol. Specifically, such consideration is not present in the protocol, at a local peer, a remote peer, or in data distribution techniques for forming MPTCP connections. There therefore exist needs for systems and methods for establishing and maintaining MPTCP connections based on monetary cost. In particular, there exist needs for systems and methods for establishing and maintaining MPTCP connections based on monetary cost while still achieving significant or higher aggregate application throughput to provide a satisfactory user experience.

Traffic distribution approaches in multipath TCP with monetary link-cost awareness


An essentially flat base of a bed liner is positioned on a vehicle cargo bed. The base includes a forward edge and a rear edge. A plurality of panels extend upwardly from the base. A front panel includes a protrusion projecting beyond the base forward edge. The base includes one or more continuous recessed channels extending from the base rear edge to the protrusion. Each channel includes a continuous track for receiving a movable tie-down device. The tie-down device includes a portion contoured to slide within the track and an anchor portion.

1. Field of the Invention
This invention relates to a cargo securing system for a vehicle cargo bed and, more particularly, to an apparatus and method for securing cargo in a pickup truck bed liner cargo area with a slidable tie-down device.
2. Description of the Related Art
Vehicles that include cargo areas, such as vans and pickup trucks, have achieved great popularity. Pickup trucks typically have a cargo bed with a substantially rectangular horizontal floor frequently between four and six feet wide and six and ten feet long, and with vertical sides between one and three feet high. Typically, stationary walls form the front and two adjacent sides, and a removable or hinged tailgate forms the remaining rear side and provides access to the bed floor for cargo loading and unloading. The trucks are thus particularly suited to carry any article of most any size, even approximating the bed size.
A pickup truck may include a device for dividing the cargo bed. U.S. Pat. No. 5,044,682 discloses a bed liner divider system that divides a pickup truck cargo area into multiple sections. The system includes a pair of slotted brackets that attach to the pickup truck bed side walls using conventional fastening techniques. The brackets are mounted on the side walls, so that the slots are aligned vertically. A divider wall is inserted into the slots to form the separate sections of the pickup truck cargo area.
Vans may also include devices for dividing the cargo area. U.S. Pat. No. 5,167,479 discloses a van cargo area divider that includes a beam member and a pair of track members. The track members are slider mechanisms that insert into channels that form a pair of integral tracks within the van cargo area floor. Each slider mechanism attaches to an end cap positioned at opposite ends of the beam member. The beam member divides the cargo area into multiple sections.
Pickup truck bed floors are typically smooth and flat, so that any carried article(s) smaller than the cargo bed itself can slide about on the bed floor under the dynamic forces created when the truck is being driven. The cargo bed will typically include a bed liner that has one or more surfaces with a higher coefficient of friction.
U.S. Pat. No. 6,237,980 discloses a plastic vehicle bed liner for use in a cargo bed. The bed liner includes a relatively rigid body having a bottom wall member for frictionally engaging the vehicle cargo bed. A pair of side wall members and a front wall member project upwardly from the bottom wall member. Each wall member includes a wear inhibiting area covering at least a portion of the wall member outer surface for engaging a corresponding member of the vehicle cargo bed.
U.S. Pat. No. Des. 302,143 discloses an ornamental design for a vehicle cargo space bed liner. The bed liner includes a plurality of shallow walls lengthwise along the base of the bed liner.
U.S. Patent Application Publication No. 2002/0149223 discloses a knock-down, multi-component bed liner. The bed liner includes five sections, a front panel assembly, a left side assembly, a right side assembly, a center bottom panel, and a tailgate panel. The left side assembly and the right side assembly attach to the bottom panel to form the bed liner floor. The assemblies are attached to one another by strips or flanges that receive conventional fasteners that are inserted into a plurality of spaced-apart openings or apertures.
While plastic bed liners for the cargo bed typically provide greater friction against the carried article(s), the bed liners do not always prevent a carried article(s) from sliding around in the bed. A sliding article could fall from the truck, or could smash against the cargo bed sides to cause damage to the truck or itself and/or create instability in the driving characteristics of the truck. Thus, it is desirable and common when easily possible to secure the carried article(s) relative to the bed.
One common way of securing these carried article(s) relative to the cargo bed includes the use of a cargo securing system. U.S. Pat. No. 5,509,764 discloses a metal cargo securing system having a crossbar member attached to a beam member. The beam member includes ends that are adapted to slide within a pair of U-shaped channel tracks that are mounted on the bed walls of the pickup truck bed.
Cargo securing systems may include one or more fastener assemblies. U.S. Pat. No. 6,827,531 discloses a slidable, retainable fastener assembly for attaching to a track that is mounted to or near a truck bed. The fastener assembly includes an anchor portion and a bottom portion. The anchor portion includes one or more eyelets, hooks, rings, carabiners, clamps, clasps, or other suitable tie-down members. The bottom portion slides within the track slot. The bottom portion includes a retainer that engages a pair of opposing extension positioned on the track upper, open portion. The retainer includes a pair of upper surfaces specially contoured to conform to the ribs and abscesses on each extension.
Other cargo securing systems utilize tracks that are integral with the cargo bed floor. U.S. Pat. No. 6,712,568 discloses a cargo bed having a pair of integral tracks within the cargo bed floor and a tie-down system that uses the integral tracks. The tracks include channels that essentially extending lengthwise along the cargo bed base. The channels receive fittings that facilitate the attachment of various objects to the cargo bed. Unfortunately, the cargo securing system cannot be used with a truck bed liner that covers the entire cargo bed floor.
U.S. Pat. No. 6,511,270 discloses a cargo clamp system that can be used with a truck bed liner that covers the entire cargo bed floor. The bed liner includes a plurality of corrugations that define a plurality of troughs extending lengthwise along the bed liner base. The clamp system includes a pair of jaws that attach the clamp system to the bed liner. Unfortunately, the existing cargo clamp system must be used with a bedliner that includes corrugations. Accordingly, there is a need for an improved cargo securing system that can be used with corrugated or non-corrugated bed liners.

Bed liner rail system for cargo holddown


Stable topical compositions having a pH of from 3.5 to 4.5 comprising a self-tanning agent, a polymer and a polyhydric alcohol humectant. The compositions of the present invention are highly stable, and deliver high levels of active self-tanning agent to the skin upon topical application.

A wide variety of cosmetic compositions containing self-tanning agents have been used to increase the pigmentation of the skin. These compositions have been used to create artificial tans, bronzing the skin in a similar fashion to exposure to the sun. These compositions are typically quite unstable, having poor shelf life. This is thought to be due to the highly reactive nature of the self-tanning agents therein.
The prior art teaches several solutions to the problem of stability of self-tanning agents in cosmetic compositions. U.S. Pat. No. 6,231,837 B1 teaches the use of polyethoxyglycols such as ethoxydiglycol and polyols to stabilise self-tanning agent-containing compositions. WO 98/00098 teaches the combination of self-tanning agents and cross-linked non-emulsifying siloxane elastomers to form stable emulsions. U.S. Pat. No. 6,197,287 discloses anionic polymers and compositions comprising them, including self-tanning agents. However, these solutions are not entirely satisfactory at maintaining the stability of self-tanning agent-containing formulations or have other disadvantages such as poor skin feel when topically applied.
It is desirable to provide stable cosmetic compositions comprising a self-tanning agent to provide a unique level of skin tanning that lifts the skin tone. Furthermore, it is desirable to provide a cosmetic composition comprising both self-tanning skin colouring agents and chronic skin care actives that act synergistically to maximise skin tone enhancement. It is further desirable to include chronic skin regulating agents in the compositions of the present invention to improve the skin barrier and so minimise any areas of dry or compromised skin. This is desirable as dry skin areas have uneven uptake of colour resulting in a blotchy or patchy result.
A supplier brochure by SEPPIC (XP-002260687), entitled "Simulgel™ NS—An emulsifying/thickening polymer . . . for New Sensations" disclose a self-tan gel-cream composition comprising 5% by weight Simulgel NS and 2.00% by weight dehydroxyacetone, but no humectant.
A summary of a poster by T. Kurz (P043, "The Color of DHA Tan") presented at an International Federation of Societies of Cosmetic Chemists (IFSCC) conference in Venezia (1994) relates to the possibilities to influence the hue of a DHA tan. The influence of having a moisturizer is discussed, and according to this document, "addition of 10% moisturizer does not increase the intensity of the tanning, it even seems to lead to a slight reduction of it". Different results were obtained at a level of 20% moisturizer.

Stable cosmetic composition comprising a self-tanning agent


Copper-filled carbon nanotubes and methods of synthesizing the same are provided. Plasma-enhanced chemical vapor deposition can be used to synthesize vertically aligned carbon nanotubes filled with copper nanowires. The copper filling can occur concurrently with the carbon nanotube growth, and the carbon nanotubes can be completely filled by copper. The filling of Cu inside the CNTs can be controlled by tuning the synthesis temperature.

Metals in their one-dimensional nanostructures such as nanowires, nanorods, and nanoparticles are fundamental for miniaturizing sophisticated mechanical, optical, and electronic devices. Since the report of single-crystal metals encapsulated in carbon nanoparticles in 1993, much attention has been concentrated on the synthesis of metal-carbon hybrid materials, especially metal nanowires encapsulated by carbon. Carbon nanotubes (CNTs) are well known for their high tensile strength and chemical stability. CNT encapsulated nanowires can survive in harsh environments because the carbon shells act as a protective barrier, allowing the material to be preserved in its pure form. The synergistic effect of the core metal nanowires and CNT shells, as well as the well-defined dimension of the nanowires, can open up novel applications or improve the performance of existing devices. CNTs filled with metals have diverse applications in multifunctional nanodevices such as nanomagnets, nanoswitches, nanopipettes, nanowelding, and nanothermometers.

Copper-filled carbon nanotubes and synthesis methods thereof

The Florida International University Board of Trustees


A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto. A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device. Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line. The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device. The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches. The test flag is output through a multiplexer to a second DQ line. As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line. The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word. Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word.

Computer designers desire fast and reliable memory devices that will allow them to design fast and reliable computers. Manufacturers of memory devices, such as random access semiconductor memories, must test a full range of functionality and timing characteristics of the memory devices in order to provide a reliable product to their customers. Because each memory cell of the device must be tested, the time and equipment necessary for testing memory devices having increasing density represents a significant portion of the overall manufacturing cost of such devices. Any reduction in the time to test each unit will reduce manufacturing costs.
Semiconductor manufacturers have developed fast testing routines to allow a greater number of chips to be tested simultaneously using a given testing device. One known testing routine, Jedec, simply compares the data written to a memory device with the data read from that memory device, and assigns a 1 value to one or more memory cell addresses if the data matches (passes), or a 0 if the data does not match (fails). While the Jedec routine is fast, it does not output the actual data written to the memory device. As a result, if the tester outputs a continuous string of 1s, indicating that the memory device passes, a technician is unsure whether the device actually passes, or if an error has occurred in the device, or at some point along the path from the device to the tester, to cause such an output.
To compensate for this shortcoming of the Jedec routine, a Micron Test Mode Routine provides three outputs. The Micron Routine outputs the actual data, as a 0 or a 1, and a mid-level tri-state value therebetween. If the tri-state value is output, rather than a 1 or a 0, the technician recognizes that an error has occurred. Unfortunately, while the Micron Routine provides superior testing of most semiconductor devices, the routine typically cannot bias the output back to the tri-state value before the beginning of the next read/write cycle rapidly enough to allow current high-speed memory devices to be tested at their normal operating speed. As a result, such high-speed memory devices must be tested at speeds slower than their typical operating speed.
To save testing time and cost, manufacturers of memory devices increasingly automate the testing procedure so that a tester applies the testing routine simultaneously to several chips. Automated testing is most easily accomplished after the memory device has been packaged as a semiconductor chip, because the chip can be automatically inserted into a test socket using pick and place machinery. Automated testing circuitry then performs the testing routine by applying predetermined voltages and signals to the chip, writing test data patterns to the memory, reading data, and analyzing the results to detect memory speed, timing, failures, etc. The more chips that can be tested simultaneously, the greater testing time savings per chip.
Most testers used in testing semiconductor chips are expensive. For example, a current tester manufactured by Teradyne has 128 input/output ("I/O") lines. To maximize the number of chips that this tester can test simultaneously, the on-chip data input/output lines, or "DQ lines," are multiplexed so that fewer I/O lines from the tester are required to be coupled to each chip. For example, the tester writes a predetermined data pattern simultaneously to multiple locations in each memory device and then accesses the written data during a read cycle. Comparator circuits fabricated on-chip compare the data read from the multiple locations and indicate whether all the data read matches the data written. If the chip has 32 DQ lines (DQ0-DQ31), on-chip 4:1 multiplexers and testing circuitry compress data onto only 8 of the 32 DQ lines. As a result, only 8 of the 128 lines of the tester are required for each chip. Consequently, the tester's 128 I/O lines can simultaneously test 16 chips.
In another solution, certain semiconductor memory devices, manufactured by Micron Technology, Inc., provide on-chip test mode circuitry that helps compensate for such delays during testing of devices. Under such test mode circuitry, the external testing device writes data to the chip during a first interval, and then writes the same data again to the DQ lines during a second interval. During the second interval, while the data is written again to the DQ lines, the data previously written to the memory device is read therefrom and latched. On-chip comparators then compare the latched data to the data written during the second interval. If the latched data equals the data written during the second interval, then the chip passes. Such a device can rapidly analyze the read data written to the device.
While the above solutions can detect for typical cell-to-cell defects and functionality of the chip, they cannot accurately test the speed of the chips. As semiconductor memory chips provide increasingly faster data I/O rates, particularly with synchronous DRAMs, data is required to be transferred to and from the chips in as little as 9 nanoseconds or less, based on a 10-nanosecond or faster clock cycle. As a result, such chips provide only a 1-nanosecond margin of error. Today's increasingly fast memory devices require highly precise generation of timing signals and precise measurement of the memory device's response thereto. Gate delays caused by the multiplexing circuitry required during testing cause the data to be read from the chips in greater than 10 nanoseconds. As a result, the tester cannot determine if the chip accurately output data within the required 9 nanoseconds. In other words, the on-chip testing circuitry prohibits the tester from testing the speed of such chips.
Obviously, it is desirable to determine the performance, and thus the speed of, semiconductor memory chips, especially high-speed chips. Additionally, because of manufacturing process tolerance and variations, one memory device of a particular design may be faster than another memory device of the very same design. Manufacturers therefore typically also desire to test the speed of such chips so that such chips can be sorted based on speed grades. To provide such speed testing, typical address compression mode testing, and on-chip multiplexing of DQ lines, must be abandoned. As a result, where 16 or more chips could previously be simultaneously tested using multiplexing, only 4 of such chips can be simultaneously speed tested because all 32 DQ lines of each chip must be coupled to the tester's I/O lines. As a result, there is a need to simultaneously speed test an increasing number of chips using a given tester.
One solution has been to purchase a larger number of testers, or more expensive testers having a greater number of I/O lines. However, as noted above, such testers are quite expensive.

High-speed test system for a memory device


An apparatus, system and method for synchronizing an asynchronous mirror volume using a synchronous mirror volume by tracking change information when data is written to a primary volume and not yet written to an asynchronous mirror, and storing the change information on both the primary storage system and the synchronous mirror system. In the event the primary storage system becomes unavailable, the asynchronous mirror is synchronized by copying data identified by the change information stored in the synchronous mirror system and using the synchronous mirror as the copy data source.

1. Field of the Invention
This invention relates to copy operations between a primary storage volume and one or more data mirror volumes. More particularly, the invention relates to maintaining data consistency between a synchronous data mirror volume and an asynchronous data mirror volume when the primary storage volume becomes unavailable.
2. Description of the Related Art
It is well known that a CPU randomly and sequentially updates one or more data storage volumes in an attached storage subsystem. It is further known that remote electronic copying of data storage volumes is a frequently used strategy for maintenance of continuously available information systems in the presence of a fault or failure of system components. Among several copy techniques, mirroring is often favored over point-in-time copying because a data mirror may be quickly substituted for an unavailable primary volume.
Conventionally, volume-to-volume mirroring from a primary volume to a data mirror volume is accomplished either synchronously or asynchronously. Synchronous mirroring can be made transparent to applications on the central processing unit (CPU) and incur substantially no CPU overhead by direct control unit to control unit copying. However, completion of a write or update is not given to the host until the write or update is completed at both the primary mirror volume and the synchronous mirror volume. In contrast, asynchronous mirroring allows the CPU access rate of the primary volume to perform independent of the mirror copying. The CPU may, however, incur copy management overhead.
In recognition for the need of multiple backup/copy approaches, several large systems offer a suite of copy functions. One such suite is offered as part of the IBM Enterprise Storage Server (ESS) package. This package includes synchronous volume-to-volume copy operations under the control of a storage controller, for example, the Peer-to-Peer Remote Copy (PPRC). It also includes asynchronous single or multi-volume copying under host control such as the Extended Remote Copy (XRC).
Referring now to FIG. 1, a prior art peer-to-peer remote copy (PPRC) system 100 is illustrated. The PPRC system 100 exemplifies a synchronous mirror system and includes a primary storage system 110 and a secondary storage system 120. A primary host 130 is connected to the primary storage system 110. The primary host 130 stores data by sending write requests to the primary storage system 110.
Data written to primary storage system 110 is copied to the secondary storage system 120, creating a mirror of the data on the primary storage system 110 on the secondary storage system 120. The copy process is a synchronous data mirroring process. In the PPRC system 100, a write made by primary host 130 is considered complete only after the data written to the primary storage system 110 is also written to the secondary storage system 120. The primary host 130 may take various forms, such as a server on a network, a Web server on the Internet, or a mainframe computer. The primary storage system 110 and secondary storage system 120 are disk systems in these examples.
A communication path 140 connects the primary host 130 to the primary storage system 110. A communication path 150 connects the primary storage system 110 with the secondary storage system 120. Communication paths 140 and 150 may comprise various links, such as fiber optic lines, packet switched communication links, enterprise systems connection (ESCON) fibers, small computer system interface (SCSI) cable, and wireless communication links.
The primary storage system 110 includes at least one storage volume 160 typically referred to as a primary volume and other well-known components such as a controller, cache, and non-volatile storage. The secondary storage system 120 includes at least one storage volume 170, typically referred to as a secondary volume. The volumes 160, 170 in the primary and secondary storage systems 110, 120 are set up in PPRC pairs. PPRC pairs are synchronous mirror sets in which a storage volume in the primary storage system 110 has a corresponding storage volume in the secondary storage system 120. For instance, primary storage volume 160 is paired with secondary storage volume 170. This pair is referred to as an established PPRC pair or synchronous mirror set, wherein the secondary storage volume 170 mirrors the data on the primary storage volume 160.
In operation, each time a write request is sent to the primary volume 160 by the primary host 130, the primary storage system 110 stores the data on the primary volume 160 and also sends the data over the communication path 150 to the secondary storage system 120. The secondary storage system 120 then copies the data to the secondary volume 170 to form a mirror of the primary volume 160. In some systems, a non-volatile cache in the primary storage system 110 and/or a non-volatile cache in the secondary storage system 120 may be temporarily used to store data directed at the primary storage volume 160 and/or the secondary storage volume 170.
Significantly, the primary storage system 110 must receive an acknowledgement that the copied data has been written to the secondary storage system 120 before terminating the I/O operation. This means that a subsequent I/O access to the same block cannot start until after the acknowledgement has been received. This acknowledgement requirement increases the response time to write requests directed to the primary storage system. In addition, as the distance between the primary storage system and the secondary storage system is increased the response time is also increased, which further decreases performance. High response times can cause unacceptable latency for completing the transaction.
The asynchronous remote copy method (XRC) is an asynchronously mirrored, volume-to-volume copy process. XRC asynchronously copies track updates on a primary volume in a primary storage system to a secondary volume in a secondary storage system. The copies are often transmitted over a long-distance communications path, possibly thousands of kilometers in length.
Referring to FIG. 2, this figure depicts a prior art XRC system 200 including a primary site 210 and a secondary site 220. The XRC system 200 exemplifies an asynchronous mirror system. The primary site 210 includes a primary host 230, for example, an IBM host running DFSMS/MVS host software. The primary host 230 further includes one or more application programs 235. A primary storage system 245 is connected to the primary host 230 by one or more channels, for example, fiber optic channels. Contained within or connected to the primary storage system 245 is at least one primary volume 250.
The secondary site 220, located for example, some thousands of kilometers remote from the primary site 210, includes a secondary host 260 having a data mover 265 operating therein. A secondary storage system 270 is connected to the secondary host 260 via one or more channels. Contained within or connected to the secondary storage system 270 is at least one secondary volume 280, typically called an asynchronous mirror volume.
The primary storage system 245 communicates with the secondary site 220 via a communication link 290. More specifically, the primary storage system 245 provides data and control information to the secondary host 260 by a communications protocol. The communication link 290 can be realized by multiple suitable communication methods, including telephone (T1, T3 lines), radio, radio/telephone, microwave, satellite, etc.
The XRC system 200 encompasses collecting data from the primary storage systems 245 so that all write requests from the primary host 230 to the primary volume 250 are preserved and applied to the secondary volume 280 without significantly impacting access rates for the primary host 230. The data and control information transmitted to the secondary site 220 must be sufficient such that a consistent copy of the primary volume 250 is established at the remote site 220.
The applications 235 generate write requests which update data on the primary storage system 245. The locations of the data updates are monitored and recorded by the primary storage system 245. In addition, an array of bits, often referred to as an active track array or changed track array, is typically used to keep a real-time record by track address on the primary volume that have been changed since the last synchronization. The changed track array is maintained in the primary storage system 245.
The updates are provided by the primary storage system 245 via the communication link 290 to the data mover 265. The data mover 265 may form the updates into a consistency group and thereafter transfer the consistency group to the secondary storage system 270, which writes the updates to the secondary volume 280. To maintain data integrity during an XRC session, the primary storage system 245 may use a second bit map, sometimes called a recovery track array or copy track array, to designate which tracks are currently being copied from the primary volume 250 to the secondary volume 280. The copy track array is maintained in the primary storage system 245.
The copy track array is typically loaded with the contents of the changed track array at the start of a synchronization operation and then the changed track array is cleared, permitting the changed track array to track the subsequent write requests to the primary volume 250. The copy track array identifying tracks that the primary storage system 245 must copy to the secondary volume 280 is cleared when acknowledgement is received that the tracks have been successfully copied to the secondary volume 280.
In the event that communication is lost during a copy session with the secondary host 260, due to any reason, the copy track array indicates which tracks must be retransmitted to retry the previous synchronization of the secondary volume 280. In some implementations, the data mover 265 inspects the updates to determine whether any records for a given time interval have been lost or are incomplete.
XRC has minimal impact on the access rate between the primary host 230 and the primary storage system 245 because a subsequent I/O operation may start directly after receiving acknowledgement that data has been written to the primary volume 250. While write requests may occur constantly according to the needs of the application programs 235, the synchronization of the secondary volume 280 is an independent, asynchronous event scheduled periodically throughout the day, typically several times per minute. Thus, an asynchronous mirror volume is only rarely identical to the primary volume 250, since writes requests to the primary volume 250 may occur during the copy operation necessary to synchronize the asynchronous mirror volume.
If the changed track array becomes unavailable for any reason, the data mover 265 cannot determine the location of tracks changed since the last synchronization in order to copy the tracks to the secondary volume 280. Additionally, if the copy track array becomes unavailable during a synchronization, the data mover cannot determine the locations of tracks relating to the interrupted synchronization that remain to be copied to the secondary volume 280. Consequently, to ensure consistency, the XRC system 200 typically performs a time consuming process of copying the entire contents of the primary volumes to the associated secondary volumes to reconstruct the asynchronous mirror.
In some systems, both synchronous and asynchronous data mirrors are maintained. This configuration permits rapid promotion of a synchronous mirror system to become a replacement primary storage system in the event that the original primary storage system becomes unavailable. The configuration also provides for the maintenance of a nearly real-time remote copy of the primary storage system data for use if the primary site becomes unavailable. In this configuration, the storage volumes on the primary storage system may act as the primary volumes for both local synchronous mirror volumes and remote asynchronous mirror volumes.
However, if the primary storage system incurs a fault or becomes otherwise unavailable, the changed track array and the copy track array stored in the primary storage system become unavailable. Without access to this information, synchronization of the asynchronous mirror may require copying the contents of the complete set of primary volumes or the synchronous secondary volumes to the associated asynchronous mirror volumes. In a large installation, this synchronization may involve hundred of volumes and may require hours or days of recovery time. Since the asynchronous mirror cannot offer protection until the synchronization is complete, the system data will be unprotected against a disaster at the primary site during the recovery period.
A need exists for a method, apparatus, and system to synchronize an asynchronous mirror volume using a synchronous mirror volume. Beneficially, such a method, apparatus, and system would decrease recovery time from a primary storage system going offline and provide a means for a continuous remote copy of system data to be maintained for use in the event the primary site becomes unavailable.

Apparatus, system, and method for synchronizing an asynchronous mirror volume using a synchronous mirror volume

International Business Machines Corporation


A protective helmet includes an energy dissipative assembly including a conforming protective base adapted to directly contact and conform to a corresponding bony anatomical region of a wearer's head. A supported flexible suspended crown adapted to be affixed to the conforming protective base and configured to define a gap separating substantially all of the interior surface of the supported flexible suspended crown from contact with a corresponding anatomical crown region of the wearer when the helmet is donned by the wearer. The supported flexible suspended crown including at least one contoured flexible shell or a plurality of cantilevered members comprising a compliant energy dissipating material that, when impacted, undergoes deformation to an extent that is greater than deformation, when impacted, of the deformation resistant material of the conforming protective base. An uncoupled cantilevered posterior cranial shield system includes a yoke configured to attach to or be integrated with shoulder pads or another garment and an attenuating cantilevered arch attached to the yoke at first and second emplacements, the attenuating cantilevered arch being configured to extend over a head of an individual wearing the shoulder pads or garment.

In recent years, scrutiny of American football player safety has intensified due to further elucidation that head impact exposures may increase risk of delayed neurologic and psychiatric dysfunction (NPD), including the neurodegenerative disease chronic traumatic encephalopathy (CTE). NPD and CTE symptoms include cognitive decline, impaired judgment, diminished impulse control, aggression, depression, anxiety, degraded motor function, and progressive dementia. No consensus has formed to define the aggregate football risk factors for chronic NPD and CTE due to study limitations and disparate findings; HOWEVER, it is universally accepted that advances in brain protection are essential for both short- and long-term player safety.
A concussion is a form of traumatic brain injury (TBI) that results when mechanical force transmission to the brain causes overt acute symptoms. The sudden accelerative/decelerative forces transmitted by an external impact are thought to structurally strain the brain as it "jostles" within the skull. Such forces are transferred to the brain resulting in damage to the neuronal tissue. Stretching of the neurons occur in response to these forces as the brain and its surrounding cerebrospinal fluid move in a delayed fashion. Stretching of the neuronal axons will disrupt their overall physiologic functioning and culminate in concussion symptoms. A sub concussive event occurs when the transmitted mechanical energy injures neurons by a similar mechanism, but the impact intensity does not exceed the severity threshold to instigate the cellular damage that causes overt symptoms (a sub-concussive sub-clinical injury).
While acute concussions inherently receive the most attention from the general public, the insidious, cumulative, sub-concussive repetitive head impacts (RHI) may pose an equal or greater risk in the development of delayed NPD/CTE. Repetitive sub-concussive hits may also introduce an independent mechanism for a concussion. Depending on the level of competition and position played, helmet accelerometer studies have demonstrated that football players may sustain 500 to 2,000 low-impact sub-concussive hits to the head during a typical football season. Investigators have diagnosed CTE in brains that have a history of RHI but lack a known history of concussion.
Youth football participation has significantly declined in recent years, due in large part to parental safety concerns regarding potential head and/or brain injuries. Canada has banned full-team youth football, starting in 2022. Members of five (5) state legislatures within the U.S. have introduced bills to ban tackle football for young players, and public sentiment/initiatives to translate such efforts into law will gain momentum with accumulation of corroborating evidence that early football participation is associated with NPD/CTE. Pediatric head and brain injuries related to sports is now firmly within the public health domain.
Innovation with respect to protective equipment for the head and brain in football has focused almost entirely on enhancement of the materials and properties of the contemporary helmet. The basic design of the modern football helmet consists of a hard polycarbonate plastic external shell, internal padding and cushioning, and an externally attached metal caged facemask. Other than incremental improvements in materials utilization, external shell strength/deformation properties, padding integrations, and overall aesthetics, this basic design has remained essentially unchanged for over a half-century; however, during this same period of time, players have become bigger, faster, and stronger, which translates to a concomitant increase in potential supraphysiological dynamic force exposure on the field of play.
Contemporary plastic shell football helmets have markedly reduced skull fractures compared to their pre-1950 leather predecessors, but they have offered limited benefits for concussion prevention. One study actually concluded that antiquated leather soft helmets provide the same concussive injury protection as modern helmets. Such a conclusion likely confirms that protective equipment applied as a single unit that directly contacts the surface area of the head simply is incapable of sufficiently attenuating the complex mechanical force transmission responsible for concussions. Most football head impacts are a complex combination of linear and rotational accelerative mechanical forces, which may cause an intense transient torsional strain on the brain and worsen with secondary rebound from the more compliant helmet components (i.e., foam lining that compresses upon impact and rebounds). As stated previously, concussive events are likely only one of several factors posing risks to long-term brain health in certain players, and the accumulation of sub-concussive hits/RHI may present an equal or greater risk.
Football concussions have relatively decreased over the last several years (although there was an increase within the NFL during the 2019 season), most likely due to a combination of modifications in practice methods/culture, coaching, officiating emphasis, tackling technique, and rules; however, despite such efforts and helmet technology improvements, the potential for a concussion persists due to the inability to eliminate the complex accelerative and rotational forces inherent in the high frequency collision sport that is American football. Therefore, there is a vital need for a new paradigm and/or solution for a sport that faces justifiable intensive scrutiny from a manifold cast of groups to include safety advocates, politicians, researchers, parents, and the players themselves. A profound advance in head and brain protection combined with effective exposure safety guidelines derived from high-quality research may provide a path to preserving football and other collision sports for younger players.
As noted above, in some instances, protective equipment applied exclusively to the head simply is incapable of sufficiently attenuating the complex mechanical force transmission responsible for concussions. Furthermore, the hard-shell helmets with foam linings do not provide ample dampening of the forces and may transfer greater forces to the brain tissue.
The following corollary from that conclusion most likely also applies: Protective equipment applied exclusively to the head is incapable of sufficiently attenuating and reducing the myriad of sub-concussive head impacts sustained in football and other collision sports. Most football head impacts are a combination of complex linear and rotational accelerative mechanical forces, which may cause an intense transient torsional strain on the brain and worsen with secondary rebound from the more compliant helmet components (i.e., foam lining that compresses upon impact and rebounds). As stated previously, concussive events are likely only one of several factors posing risks to long-term brain health in certain players, and the accumulation of sub-concussive hits/RHI may present an equal or greater risk. Repetitive sub-concussive hits to the player's head and/or body resulting in a subthreshold acceleration/deceleration force event to the skull and brain, is analogous to tissue fatigue. Tissue fatigue is due to long term repetitive cyclic loading at subthreshold forces that if applied one to two times to tissue may not induce short or long-term injury; however, if the subthreshold force is repetitively transferred to the tissue, the tissue will eventually suffer injury. In essence, where a single cycle of peak acceleration at threshold levels to tissue can cause injury after a single hit (i.e., concussions can occur at thresholds exceeding at least 65 g to 70 g forces in adult athlete measurements) (Broglio™), repetitive forces to the skull and brain can occur after a series of repetitive forces at sub-concussive or subthreshold levels. It is well documented that fatigue of human tissue occur at significantly lower values than the static ultimate strength of the tissue. Fatigue failures in human tissue have been shown to occur at approximately 50-60% of the static ultimate failures through cadaveric testing. In essence, it will take less force to induce injury to the brain and neural tissue with repetitive loading (hits) to the head. There is an exponential correlation between force magnitude and repetitive cycles.
While helmets ostensibly reduce impact intensity or the overall force transmission ultimately absorbed by the brain soft tissue itself, no current head protective system offers a practical means to reduce RHI frequency. Therefore, not only is added protection needed to supplement the helmet protection, but there is a vital need for a new option and/or solution for a sport that faces justifiable intensive scrutiny from a manifold cast of groups to include safety advocates, politicians, researchers, parents, and the players themselves.
Football concussions have relatively decreased over the last several years (although there was an increase within the NFL during the 2019 season), most likely due to a combination of modifications in practice methods/culture, coaching, officiating emphasis, tackling technique, and rules; however, despite such efforts and helmet technology improvements, the potential for a concussion persists due to the inability to eliminate the complex accelerative and rotational forces inherent in the high frequency collision sport that is American football. Principal among the significant rules modifications implemented over the last decade is the penalty "targeting," which, at the collegiate level, results in disqualification of a player initiating and engaging in helmet-to-helmet contact. Despite best efforts by players, the high-speed dynamic nature and action of the game does not permit complete elimination of such helmet-to-helmet contacts, and unintentional/unavoidable head-to-head collisions are inevitable.
Protective headgear having one or more improvements in comparison to the prior art would be desirable in the art. In addition, there is a vital need for a new option and/or solution for a sport that faces justifiable intensive scrutiny from a manifold cast of groups to include safety advocates, politicians, researchers, parents, and the players themselves. Players would benefit from a more comprehensive head protective system that decreases the probability and frequency of unintentional (and intentional) direct helmet-to-helmet contacts. A profound advance in head and brain protection combined with effective exposure safety guidelines derived from high-quality research may provide a path to preserving football and other collision sports for younger players.


A piezoelectric vibrator having excellent shock resistance and high reliability is offered. The centers of first and second piezoelectric vibrating plates are supported by pillars on a main surface of an enclosure and nearly or substantially parallel to the main surface of the enclosure. Spacers having a Young's modulus of less than 2 GPa are mounted on both end sides of the second piezoelectric vibrating plate to prevent contact between the vibrating plates, thus preventing damage. Other spacers are mounted on the main surface of the enclosure in positions corresponding to the first-mentioned spacers to prevent contact with the main surface of the enclosure, thus preventing damage to the second piezoelectric vibrating plate.

1. Field of the Invention
The present invention relates to a piezoelectric vibrator used in an acoustic transducing electronic appliance (such as an enclosure vibration type flat speaker or receiver) or in a vibration transducing electronic appliance such as a vibrator. More particularly, the invention relates to a piezoelectric vibrator having improvements in shock resistance, mountability, and reliability.
2. Description of the Related Art
Piezoelectric vibrators utilizing piezoelectric elements are widely employed as simple electro-acoustic transducers and actuators. Especially, in recent years, they are often used in the field of mobile phones, personal digital assistants, and so on. A conventional piezoelectric vibrator (e.g., Japanese Patent Laid-open No. 2000-224696-, especially FIGS. 4-8)) uses a bimorph device or unimorph device obtained by bonding together piezoelectric elements on the surface of a metallic vibrating plate. The device is supported around its center by a support member, constituting a cantilevered piezoelectric vibrator. When this vibrator is driven, high driving force is obtained in a low frequency range.
In another actuator, plural piezoelectric vibrating plates having different resonant frequencies are used to produce a distribution mode. For example, International Publication WO 01/54450, especially FIG. 9, discloses a transducer in which plural rectangular_piezoelectric vibrating plates are supported as a piezoelectric vibrator for a panel speaker by a single pillar substantially parallel over the panel. Vibration of the piezoelectric vibrating plates is transmitted to the panel via the pillar to thereby vibrate the panel. Thus, sound is produced. Japanese Patent Laid-open No. 2000-134682, especially FIGS. 1 and 3, describes a sound-producing device in which one or more disk-like piezoelectric vibrating plates are supported by a single pillar. A resilient body is mounted along the fringes of the vibrating plates. Thus, the acoustic feature is improved.
FIG. 10 shows one example of the conventional piezoelectric vibrators. In the shown piezoelectric vibrator 200, a piezoelectric vibrating body 201 is fixed on an acoustic panel 202, a body 201 consisting of a pillar 204 and piezoelectric vibrating plates 206, 212. The piezoelectric vibrating plates 206 and 212 are supported by the pillar 204 so as to be substantially parallel to the acoustic panel 202. The piezoelectric vibrating plate 206 is considered to have a bimorph structure. That is, piezoelectric elements 209 and 210 are bonded to a vibrating plate 208 made of a metal-based material such as 42 alloy or a resinous material such as polyethylene terephthalate (PET). An electrode layer of Ni, Pd, Ag, or the like is formed on a surface of each of the piezoelectric elements 209 and 210. The other piezoelectric vibrating plate 212 is similar in structure. Piezoelectric elements 215 and 216 are bonded to a vibrating plate 214. Thus, a bimorph structure is formed. The pillar 204 is molded from a metal-based material such as stainless steel or from a resinous material such as PET or acrylonitrile butadiene styrene (ABS). The acoustic panel 202 is made of glass or aluminum of honeycomb structure, for example.
Lead wires 222 and 228 are connected to the electrodes of the piezoelectric vibrating plates 206 and 212 and the vibrating plates 208, 214 by a conductive paste or by solder 218, 220, 224, 226, for example. An electrical signal is applied via the lead wires 222 and 228, so that the piezoelectric vibrating plates 206 and 212 vibrate. The vibration is transmitted to the pillar 204. The vibration is further transmitted via the pillar 204 to the acoustic panel 202 to which the piezoelectric vibrating body 201 is fixed. Consequently, the acoustic panel 202 vibrates, producing sound. However, the conventional device described so far has the following problems.
(1) When an impact load is applied to the piezoelectric vibrating body, an excessive stress is applied to the piezoelectric vibrating plates. This may destroy the piezoelectric elements made of a fragile material, or they may come off the pillar or the vibrating plates may bend. In this way, structural damage occurs. In addition, a pyroelectric effect produces an electromotive force. Concomitantly with this, there arises the danger that the circuit is affected. Furthermore, where plural piezoelectric vibrating plates are used, contact between any piezoelectric vibrating plate and its enclosure leads to destruction of the piezoelectric elements. Further, collision between the piezoelectric vibrating plates destroys the piezoelectric elements.
(2) Where plural piezoelectric vibrating plates are used, mounting methods including an electrical connection method such as soldering using cotton threads, bonding of the piezoeletric vibrating plates to the pillar, and mounting of the pillar and electrical connector terminals are complicated. This deteriorates the productivity and increases the cost of production.


A breast pump for extracting milk from a human breast includes an extracting cup and has an engagement portion for engaging the breast. A container has a mouth portion connected to the extracting cup. A milk receiving bag is mounted to the mouth portion and suspended in the container. An air suction source is connected to the container in order to produce air suction inside the container. An air path connects the interior of the extracting cup and the inside of the container, wherein the air suction creates a negative air pressure condition to assist in the suction of milk. The milk flows by gravity through the extracting cup and into the milk receiving bag without contact with the air suction source or the inside of the container.

1. Field of the Invention
The present invention relates to a breast pump for extracting milk from a human breast and collecting the extracted milk in a milk receiving bag. Further, the present invention relates to a pressure adjusting mechanism for adjusting the pressure applied by the breast pump, as well as a milk receiving bag for freezing the extracted milk.
2. State of the Prior Art
One conventional breast pump is disclosed in Japanese publication 41,364/1984. The breast pump described in this document has a section for producing suction on the breast that is electrically driven, a milk extracting section and a bottle. The suction section has a pressure adjusting knob and a pressure release button for changing the internal pressure by the introduction of outside air. The milk extracting section has a funnel-like receiver vertically connected to the bottle by the suction section.
When the electrically driven suction section is operated and the funnel-receiver applied to a breast, a negative pressure or suction is created in the milk extracting section for extracting milk. The extracted milk is guided to flow into the bottle.
However, the above-described conventional breast pump has the following disadvantages. The milk extracting section of the breast pump is connected to the bottle, and thus the extracted milk is collected in the bottle. Thus when milk is preserved in a home freezer, it has to be moved from the bottle to a suitable freezing bag. When the frozen milk is then used to feed a baby, it has to be moved back to the bottle, which involves removing the freezing bag from the freezer, defrosting the freezing bag and warming the bag up to a desired temperature. Thus the milk has to be moved at least two times when milk is frozen and subsequently defrosted to feed a baby. This not only involves some trouble in moving the milk back and forth, but because the milk is moved at least two times, there is a risk that the bottle and bag might become unsanitary.

Breast pump having a pressure adjusting mechanism