A method of estimating the difference in frequency between base station transmissions received over a radio channel and a locally generated carrier frequency in a mobile receiver. The differential phase shifts imparted to different parts of a received synchronization code because of a frequency offset of the local reference oscillator are detected in the receiver. A series of partial correlations of the received synchronization code over a single transmission slot allows detection of the differential phase shifts. Signal to noise ratios may be improved by means of a series of overlapping partial correlations. The period over which the correlations are performed is much less than the coherence time of the radio channel.

In cellular systems the timing and frequency accuracy of transmissions from network base stations rely on very stable and highly accurate reference oscillators. In the competitive market for supply of mobile stations for communication with the network base stations a low cost is demanded by the prospective purchasers of mobile equipment. Therefore low cost reference oscillators e.g voltage controlled crystal oscillators (VCXO) would be the usual choice for the reference oscillator of a mobile station such as is used in a wideband code division multiple access (WCDMA) network.
The frequency accuracy of these low cost reference oscillators e.g. 5 parts per million (ppm), is very much less than the frequency accuracy of the reference oscillators available to the base stations (e.g. 0.05 ppm). The resulting difference in frequency between the base station transmissions and the locally generated carrier frequency used for down-conversion in the mobile station, the so-called frequency offset, causes problems with synchronization. Further frequency errors can arise at the mobile station because of the Doppler shifts produced by the movements of the mobile station.
When power is applied to a mobile station the task of synchronization with a base station is initiated (initial cell search). The characteristics of the Universal Mobile Telecommunications System (UMTS) and the procedure for initial cell search to which the following description relates is described in the European Telecommunications Standards Institute (ETSI) publication TR 101 146 version 3.0.0 Universal Mobile Telecommunications System, Concept evaluation. As will be clear to those skilled in the art the instant invention is not restricted to use with the UMTS and may also be applied to other WCDMA systems. Reference is made to U.S. Pat. No. 5,982,809 to Liu which forms part of the prior art.
The initial cell search by the mobile station is performed in three steps and the first step is the acquisition of slot synchronization to the transmissions of the base station providing, through a fading path, the strongest signal at the receiver of the mobile station. With reference to FIG. 1 which is a schematic illustration of base station broadcast transmissions, base station transmissions are represented at 1, the transmission channel at 2 and the mobile station receiver at 3. In FIG. 1 by way of example the transmissions from only two base stations (BTS1 and BTS2) are shown.
These base station transmissions are not synchronized with each other and are maintained to transmit over common fixed duration time intervals referred to as slots and common fixed duration framing intervals referred to as frames. One frame comprises 15 slots. In FIG. 1 the start of a slot for the transmissions from BTS 2 is shown delayed from the start of a slot for the transmissions from BTS1 by an arbitrary amount t seconds.
The base station transmissions include a synchronization channel (SCH) aligned with the slot boundary and a primary common control physical channel (PCCPCH). The synchronization channel comprises a primary synchronization code (PSC) and a secondary synchronization code (SSC) as illustrated in FIG. 2. The code transmitted as the primary synchronization code (Cp) is repeated at the beginning of each slot by all base stations.
The BTS transmissions to the receiver 3 will be affected by channel 2 and the transmissions of BTS 2 are illustrated as received through a 3-path (multipath) channel while the transmissions of BTS1 are illustrated as received through a 2-path channel. The signals from BTS 1 and BTS2 are effectively summed in channel 2 before arriving at receiver 3. Correlation of the received signal with the expected primary synchronization code which is stored in the receiver provides a number of correlation peaks. The highest peak detected corresponds to that base station of the network (the found base station) to which the receiver will synchronize.
The second step of initial cell search establishes frame synchronization and identifies the code group of the base station found in step 1 (the found base station). The third step of initial cell search determines the scrambling code assigned to the found BS. To avoid prolixity further details regarding the second and third steps of the initial cell search are not presented here and reference is made to ETSI publication TR 101 146 supra.
It is an object of this invention to provide an improved method of estimating the frequency offset in a direct sequence spread spectrum communications receiver.
In accordance with the invention there is provided a method of estimating the frequency offset in a direct sequence spread spectrum communications receiver comprising computation of differences in phase imparted by down-conversion in the receiver to parts of a synchronization code received over a radio channel, said differences in phase being computed from a series of correlations of parts of the received synchronization code with a synchronization code stored in the receiver, in which the period over which the series of correlations is performed is not greater than the length of said stored synchronization code.
The implementation of the invention described herein is applicable to the initial cell search performed at a mobile station operating in the frequency division duplex (FDD) mode in a UMTS network.
The performance of the UMTS cell search can be degraded by offsets in the carrier and sampling clock frequencies. In practice, both the carrier and sampling clock frequencies are derived, from the frequency of a reference oscillator (usually a VCXO). The carrier (fc) and the sampling clock frequencies (fsmp) may be expressed as in equations (1) and (2) respectively. The terms k1 and k2 in these equations represent constants and fx is the reference frequency supplied by the reference oscillator of the mobile station.fc=k1×fx  (1)fsmp=k2×fx  (2)
The equations (1) and (2) indicate the ways in which inaccuracies in the reference frequency generated by the crystal oscillator translate into the inaccuracies in the carrier and sampling clock frequencies. When expressed in parts per million, the same inaccuracy will apply to each of the three frequencies, fx, fc and fsmp. For example, for a desired carrier frequency of 2 GHz, and a sampling clock frequency of 15.36 MHz, an inaccuracy of 1 ppm (in fx) represents offsets of 2 kHz in the carrier frequency and 15.36 Hz in the sampling frequency.
With regard to WCDMA cell search, the carrier frequency offset results in a continuous phase variation of the received complex signal. The sampling clock frequency offset may cause incorrect detection of vital system timing instances. Any effects of an offset in the sampling clock frequency are observed only after processing of the signals in a large number of slots. The phase rotation caused by the offsets in the carrier frequency results in a decrease in the received ratio of the signal power versus the noise plus interference power and as a consequence, an increase in the probability of instances of false detection of timing. Therefore offsets in both the carrier frequency and the sampling clock frequency will result in a degradation of the performance in all three steps of the UMTS cell search process.
The loss of performance in the cell search caused by the frequency inaccuracies is evident during the first step of the cell search process. Sampling clock offsets may cause errors in detection of the slot boundaries i.e. the slot boundaries will be positioned in the wrong places. If the error in locating the slot boundaries is larger than one chip period, the results obtained by the remaining cell search steps will also be in error. For practical frequency inaccuracies, however, a slippage of 1 chip caused by the sampling clock inaccuracies is observed over long time intervals.
Consequently, the inaccuracies of the sampling clock are of secondary importance when compared to the offsets in the carrier frequency. As the effects of an offset in the carrier frequency are observable immediately, these effects can be measured and used to correct the reference frequency. A reduction in the inaccuracy of the reference frequency will reduce the offsets in both the carrier and sampling clock frequencies also. The method described herein is based on the differential phase offsets imparted to the received primary synchronization code at down-conversion by errors in the local oscillator frequency used for down-conversion. The resulting measurements of phase offset are used to correct the reference oscillator frequency.
A complex baseband signal transmitted by a base station may be represented asSt=A(t).ejθ(t),where A(t) and θ(t) represent the magnitude and phase respectively of the signal. The transmitted signal when received via a fading path can be represented as:Sr=β(t).St.ej(Δωt+φ(t)+σ(t))  (3)where Δω is the carrier frequency offset in radians per second, φ(t) is the random phase (in radians) due to the Doppler shift and σ(t) is the random phase due to noise and interference. Variations of the signal envelope are represented as β(t).
In the first step of the UMTS cell search, the in phase (I) and quadrature (Q) components of the received signal are correlated with the primary synchronization code. When the local primary synchronization code is aligned with the first symbol of a received PCCPCH+SCH time-slot (i.e. at the slot boundary), the transmit signal may be expressed as:
                              S          t                =                  M          ·                      ⅇ                          j              ·                              π                4                                                                        (        4        )            where M is a constant. The correlation of the corresponding received signal with the local primary synchronization code stored in the receiver is shown in equation (5), where T is the correlation period.
                    C        =                              ∫            0            T                                                        [                                                β                                                        (                    t                    )                                                  ·                                  M                  2                                ·                                  ⅇ                                      j                    ·                                          π                      4                                                                      ·                                  ⅇ                                      j                                                              (                                                                        Δω                                                                                t                                                +                                                  ϕ                                                                                (                            t                            )                                                                          +                                                  σ                                                                                (                            t                            )                                                                                )                                                                                ]                        ·                                                                            ⅆ              t                                                          (        5        )
Equation (5) represents the correlation between the local primary synchronization code and the received signal at the slot boundaries. As the primary synchronization code is a known signal, the carrier frequency offset may be estimated by measuring the change in the phase of the received primary synchronization code. The effect of the signal components due to Doppler and noise plus interference are discussed below and for clarity are removed from equation 5 which may then be reduced to
                    C        =                              ∫            0            T                                                        M              2                        ·                          ⅇ                              j                ·                                  π                  4                                                      ·                          ⅇ                              j                                                  (                                      Δω                                                                                t                                    )                                                      ·                                                                            ⅆ              t                                                          (        6        )
To evaluate the phase due to the carrier offset, the above integral may be evaluated over a number of intervals (i.e. by using partial correlations). The differential phase of the results will then contain a component which is directly proportional to the carrier frequency offset. This process is shown in the following equations where 2 intervals are used. An illustration of the use of two non-overlapping partial correlations is given also at FIG. 4.
                              C          1                =                              ∫            0                          T              2                                                                    M              2                        ·                          ⅇ                              j                ·                                  π                  4                                                      ·                          ⅇ                              j                                                  (                                      Δω                                                                                t                                    )                                                      ·                                                                            ⅆ              t                                                                        C          2                =                              ∫                          T              2                        T                                                        M              2                        ·                          ⅇ                              j                ·                                  π                  4                                                      ·                          ⅇ                              j                                                  (                                      Δω                                                                                t                                    )                                                      ·                                                                            ⅆ              t
The differential phase between the results is given by:
                    ΔΦ        =                                            ∠C              2                        -                          ∠C              1                                =                                                    (                Δω                )                                          T                        2                                              (        7        )
The carrier frequency offset may then be computed from:
                    Δω        =                              2                        ΔΦ                    T                                    (        8        )
By making use of N partial correlations, N−1 differential phase values may be obtained each indicating a carrier frequency offset of:
                    Δω        =                                            (              ΔΦ              )                                    N                    T                                    (        9        )            where ΔΦ isΔΦ=∠Ci−∠Ci−1  (10)with Ci representing the ith partial correlation.
Multiple values of differential phase can be used to estimate the carrier frequency offset under additive white Gaussian noise (AWGN), multi-path and multi-user conditions by applying averaging to the individual results obtained from equation 10:
                              Δω          _                =                                            ∑                              i                =                1                                            N                -                1                                                                Δω              i                                            N            -            1                                              (        11        )
The effect of Doppler is minimized by ensuring that the differential phase values are obtained using partial correlation over periods which are much less than the coherence time of the channel. The coherence time is a period within which there is a high degree of correlation between faded signal samples and is approximately equal to the inverse of the Doppler frequency.
For a mobile speed of 500 km/h and a nominal carrier frequency of 2 GHz, the Doppler frequency approximates to 925 Hz. The corresponding value of coherence time is around 1×10−3 seconds. Evaluation of differential phase values as described above is accomplished within the duration of a single PCCPCH+SCH symbol period (i.e. ˜67×10−6 seconds), which is much less than the coherence time.
Phase variations due to Doppler usually may be assumed to be small and therefore would not significantly affect the computations described above. Improved estimates of the carrier frequency offset may be obtained, however, by computation of a set of values for the frequency offset over a number of slots. An averaging process can then be applied.
An averaging process is shown by the equation
      Δω    _    =                    ∑                  k          =          1                M                                    ∑                      i            =            1                                N            -            1                                            Δω          ik                            M                    (                  N          -          1                )            where Δωik represents the frequency offset estimate of the ith correlation of the kth slot. M is the number of slots used in the averaging process. The frequency offset is then derived from the average value taken from the series of partial correlations within each slot and over a number of slots.
Various factors affect the choice of the number of partial correlations per primary synchronization code to be used in the above process. An increase in the number of partial correlations in the series of correlations results in a shorter correlation period (relative to the coherence time). With shorter correlation periods smaller variations of phase due to Doppler may be expected. Use of shorter correlation periods, however, causes a drop in the detected signal power and leads to a reduced signal to noise plus interference ratio. For reduced signal to noise ratios the effect of AWGN and interference on the detected differential phase values becomes more severe. It has been found that two partial correlations per primary synchronization code are sufficient for estimates of the carrier frequency offset to be obtained.
The minimum detectable frequency offset is dependent upon the ratio of the powers of the signal to the noise plus interference and also on the variations in the signal phase due to Doppler over the partial correlation intervals. Experimental results indicate that for a mobile station moving at 80 kilometres per hour (km/h) the method described herein can be expected to detect more than 95% of the carrier frequency offsets and the detection rate remains above 75% for 500 Km/h.
For increased correlation powers overlapping between the partial correlations may be employed. By this means each of the correlations in a series of correlations include a part of the synchronization code common to another of the correlations in the series of correlations. With reference to FIG. 5 two overlapping partial correlations are illustrated as performed within a single slot. In UMTS the primary synchronization code X is of length 256 chips. A first partial correlation PC1 is performed with the first (256-a) chips and a second partial correlation PC2 is performed with the last (256-a) chips. In this series of correlations 256-2a chips are common to both PC1 and PC2. More generally first and second overlapping partial correlations may be represented as
            PC      1        =                  ∫        0                                            (                              X                -                a                            )                        ·            T                    X                                            M          2                ·                  ⅇ                      j            ·                          π              4                                      ·                  ⅇ                      j                                      (                              Δω                                                                                t                            )                                      ·                                                    ⅆ          t                                PC      2        =                  ∫                              a            ·            T                    X                T                                    M          2                ·                  ⅇ                      j            ·                          π              4                                      ·                  ⅇ                      j                                      (                              Δω                                                                                t                            )                                      ·                                                    ⅆ          t
Owing to the increase in the length of each partial correlation period the arrangement shown in FIG. 5 provides a correlation power greater than that obtained from the non-overlapping arrangements. The corresponding differential phase is given by (Δω.a.T)/X, where X is the total number of chips in the primary synchronization code, T is the duration of tie primary synchronization code in seconds and a is the number of chips of the primary synchronization code not used in the partial correlation process.
For a carrier frequency offset of 1 ppm, a carrier frequency of 2 GHz, and with a=64 chips as shown in this example, the nominal correlation peak of the partial correlations will be approximately 2.5 dB less than that provided by a correlation with the complete 256 chip code. The nominal differential phase resulting from use of an overlap with a=64 chips is 12 degrees and this difference is sufficiently large to be detected by the algorithm of FIG. 3.
The advantage conferred by the use of overlapping partial correlations may be demonstrated by comparison of the above example (a=64 chips) with an arrangement where there is no overlapping of the partial correlations. Where a=128 chips and two partial correlations are performed in a single slot the partial correlation peak will be 6 dB less than for the case of a full correlation (a=0). When a relatively high level of noise plus interference is encountered, overlapping partial correlations can be used to increase the power in a partial correlation peak thereby to avoid an unacceptable degradation in performance.
In general, a suitable value for a will be such that the overlapping correlation power is maximised while the resulting differential phase remains within the range of detection of the system. The invention may be carried into effect by means of standard digital techniques well known in the art.

Method for frequency offset estimation in a direct sequence spread spectrum communications receiver


The buck frame is in a one-piece construction and is designed to be embedded in a poured concrete wall. The exterior of the buck frame is provided with reinforcing ribs, while its interior surfaces form a centrally-located boss, the side faces of which are provided with lips and grooves to releasably retain a window frame, made of four separate interfitting parts. A resilient polyurethane board is fitted between the lintel part of the window frame and the registering boss of the buck frame to provide for installation and removal of the horizontally-slidable window panes and also of the window frame parts.

Installation of a window frame in the poured concrete foundation of a building, such as a house, has, up to now, required the construction of a wooden frame inserted in the concrete form and around which concrete was poured. After concrete curing, the wooden frame had to be removed and the conventional window frame fitted within the concrete wall aperture. The installation of such a basement window was therefore time-consuming.
It is known to provide buck frames to be permanently embedded in a poured concrete wall, for instance the buck frame described in U.S. Pat. No. 3,769,769 dated Nov. 6, 1973--inventor: William J. Kohl and entitled: PERMANENT BASEMENT WINDOW FRAME AND POURING BUCK. However, none of the known buck frames permit the installation and removal of a window frame of the type having a multiplicity of horizontally-slidable glass panes, with or without sashes.

Buck frame and window frame removably fitted therein


A semiconductor memory device is provided with a plurality of input circuits each having a mask information generating circuit to enable bit writing in page mode. The mask information generating circuit generates mask information from a mask control signal supplied from a mask control circuit, mask data supplied from a mask data input buffer circuit, an internal signal and a special function signal. The mask information generating circuit controls the mask information, depending on the state of the special function signal at the fall of an external column address strobe signal such that the mask information may change on each column address strobe cycle.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a write per bit function in page mode.
2. Description of the Background Art
FIG. 22 is a block diagram showing a conventional semiconductor memory device having a write per bit function in page mode. Before describing the write per bit function in page mode, a construction and an operation of a semiconductor memory device in FIG. 22 will be described below.
This semiconductor memory device has the construction allowing input and output of 4-bit data in parallel. A memory array 1 includes four memory array blocks B0-B3. Each memory array block is disposed correspondingly to each bit of the data. Each of memory array blocks B0-B3 includes a plurality of memory cells disposed in plural rows and plural columns.
An RAS buffer 2 receives an external row address strobe signal /RAS and generates an internal signal /RASI. The internal signal /RASI has the same phase as the external row address strobe signal /RAS. A CAS buffer 3 receives an external column address strobe signal /CAS, and generates an internal signal /CASI. The internal signal /CASI has the same phase as the external column address strobe signal /CAS. A W-buffer 4 receives an external data write control signal /W, and generates an internal signal /WI. The internal signal /WI has the same phase as the external data write control signal (external write signal) /W.
A row address buffer 5 receives an external address signal Add and generates a row address signal in response to fall of the internal signal /RASI. A row decoder 6 decodes the row address signal, and selects one row in each of the memory array blocks B0-B3.
The data of one row read from the memory cells in the selected one row is amplified by a sense amplifier included in a sense amplifier and IO gate 7 and is held.
A column address buffer 8 receives the external address signal Add, and generates a column address signal in response to the internal signal /CASI. A column decoder 9 decodes the column address signal and selects one column in each of the memory array blocks B0-B3. Thereby, the data selected in each of the memory array blocks B0-B3 is transmitted through an IO gate included in the sense amplifier and IO gate 7 to corresponding one of input/output lines IO0-IO3.
In a write operation, the data externally applied to external data input terminals WIO0-WIO3 is sent through four input circuits 10 to the input/output lines IO0-IO3, respectively.
In a read operation, the data on the input/output lines IO0-IO3 is sent through four output circuits 11 to external data output terminals RIO0-RIO3, respectively. An output control circuit 12 controls the output circuits 11 in response to an external output enable signal /OE.
A timing generator 13 is responsive to the internal signals /RASI, /CASI and /WI to generate various timing signals. This semiconductor memory device is formed on a semiconductor chip CH.
Now, the write per bit function in page mode will be described below. In the page mode, the memory cells in the selected one row are sequentially selected by repetitively dropping the external column address strobe signal /CAS, while maintaining the state where one row in each memory array block is selected in response to the fall of the external row address strobe signal /RAS. This mode allows random access within a range of one row in the memory matrix at a higher speed than the normal mode and with lower power consumption. The write per bit function is a function inhibiting the write of an arbitrary bit of externally applied data.
The semiconductor memory device in FIG. 22 has the write per bit function in page mode. Now, a specific construction of the input circuit 10 in the semiconductor memory device in FIG. 22 will be described below, and further the write per bit function in page mode will be described.
FIG. 23 is a block diagram showing one of the input circuits 10. The input circuit 10 includes a mask data input buffer 101, a data input buffer 102 and an IO buffer 103.
The mask data input buffer 101 is responsive to the internal signals /RASI and /WI, and receives the data through an external data input terminal WIOi to generate mask data MDi. The mask data MDi forms mask information MSKi. Here, "i" represents an integer from 0 to 3.
The data input buffer 102 is responsive to the internal signals /CASI and /WI, and receives the data through the external data input terminal WIOi to generate write data DBi.
The IO buffer circuit 103 is responsive to the mask information /MSKi, and applies the write data DBi to the input/output line IOi or inhibit the input. The input/output line IOi includes two input/output lines IO and /IO receiving complementary data.
FIG. 24 is a circuit diagram showing a specific construction of a mask data input buffer circuit 101 shown in FIG. 23. The mask data input buffer circuit 101 includes inverters G1-G8, NOR gates G9 and G10, inverter circuits INV1 and INV2, and a latch circuit LT1.
When the internal signal /RASI and internal signal /WI go to "L", the output of inverter G1 goes to "L", and the output of NOR gate G10 is maintained at "H" for a predetermined time period. Thereby, the inverter circuit INV1 is activated, and the inverter circuit INV2 is maintained at an active state for the predetermined time period. Therefore, the data at external data input terminal WIOi is fetched through the inverter circuit INV1, inverter G8 and inverter circuit INV2 to the latch circuit LT1. The latch circuit LT1 latches the data and outputs the same as the mask information MDi.
FIG. 25 is a circuit diagram showing a specific construction of the data input buffer circuit 102 in FIG. 23. The data input buffer circuit 102 includes inverters G11-G18, NOR gates G19 and G20, inverter circuits INV3 and INV4, and a latch circuit LT2.
When the internal signals /CASI and /WI go to "L", the output of inverter G11 goes to "L", and the output of NOR gate G20 is maintained at "H" for a predetermined time period. Thereby, the inverter circuit INV3 is activated, and the inverter circuit INV4 is maintained at the active state for the predetermined time period. Therefore, the data at external data input terminal WIOi is fetched through the inverter circuit INV3, inverter G18 and inverter circuit INV4 to the latch circuit LT2. The latch circuit LT2 latches the data and outputs the same as the write data DBi
FIG. 26 is a circuit diagram showing a specific construction of the IO buffer circuit 103 shown in FIG. 23. The IO buffer circuit 103 includes inverters G21 and G22, NAND gates G23 and G24, NOR gates G25 and G26, P-channel MOS transistors P1 and P2, and N-channel MOS transistors N1 and N2.
If the mask information /MSKi is "L" (write inhibit state), the outputs of NAND gates G23 and G24 are "H", and the outputs of NOR gates G25 and G26 are "L". Thereby, the transistors P1, P2, N1 and N2 are turned off. Thus, the write data DBi is not transmitted to the input/output lines IO and /IO.
If the mask information /MSKi is "H" (write enable state), NAND gates G23 and G24 as well as NOR gates G25 and G26 operate as the inverters, respectively. Thus, the write data DBi is transmitted to the input/output line IO, and the inverted data of write data DBi is transmitted to the input/output line /IO.
Referring to a timing chart of FIG. 27, the write per bit operation in page mode of the conventional semiconductor memory device shown in FIGS. 22-26 will be described below.
In response to the fall of the external row address strobe signal /RAS, the external address signal Add is fetched as a row address signal X. Thereby, one row in each memory array block is selected. If the external data write control signal /W is "L" when the external row address strobe signal /RAS falls, the data at external data input terminals WIO0-WIO3 is fetched as mask information /MSK0-/MSK3.
In an example shown in FIG. 27, the mask information MSK0 and /MSK2 goes to "L" (write inhibit state), and the mask information /MSK1 and /MSK3 goes to "H" (write enable state). Thereby, the external data input terminals WIO0 and WIO2 are maintained at the write inhibit state, and the external data input terminals WIO1 and WIO3 are maintained at the write enable state.
While maintaining the external row address strobe signal /RAS at "L", the external column address strobe signal /CAS is repetitively fallen to "L". In response to the fall of the external column address strobe signal /CAS, the external address signals Add are sequentially fetched as column address signals Y1, Y2, Y3 and Y4. Thereby, in each memory array block, the memory arrays on one row selected by the row address signal X are sequentially selected by the column address signals Y1, Y2, Y3 and Y4, respectively. The column selecting operation, which is responsive to the fall of the external column address strobe signal /CAS, is called a CAS cycle.
In a CAS cycle T1, the writing of data D01 at external data input terminal WIO0 and the data D21 at external data input terminal WIO2 is inhibited, and the writing of data D11 at external data input terminal WIOl and data D31 at external data input terminal WIO3 is carried out. Similarly, in each of CAS cycles T2, T3 and T4, the writing of data at external data input terminals WIO0 and WIO2 is inhibited, and the writing of data at external data input terminals WIO1 and WIO3 is carried out.
As described above, according to the write per bit operation in page mode of the conventional semiconductor memory device shown in FIGS. 22-26, the mask information was fetched when the external row address strobe signal /RAS fell, and in every CAS cycle thereafter, the write inhibit state or write enable state of each external data input terminal is determined, depending on the fetched mask information. Thus, the mask information, which was fetched when the external row address strobe signal /RAS fell, affects every CAS cycle thereafter, so that the mask information in each cycle has no arbitrariness.

Semiconductor memory device having a write per bit function in page mode


A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware.

1. Field of the Invention
The present invention relates to a test apparatus.
2. Description of the Related Art
In recent years, various kinds of semiconductor devices are known which are employed in various kinds of electronic devices. Examples of such semiconductor devices include: (i) memory devices such as DRAM (Dynamic Random Access Memory), flash memory, and the like; (ii) processors such as a CPU (Central Processing Unit), an MPU (Micro-Processing Unit), a micro-controller, and the like; and (iii) multifunctional devices such as a digital/analog hybrid device, SoC (System On Chip), and the like. In order to test such semiconductor devices, a semiconductor test apparatus (which will also be referred to simply as "test apparatus") is employed.
The test items for such semiconductor devices can be broadly classified into functional verification tests (which will also be referred to simply as the "functional tests") and DC (Direct Current) tests. With a functional verification test, judgment is made whether or not a DUT (device under test) operates normally according to its design. Examples of such a functional verification test include identification of defect positions, and acquisition of evaluation values which indicate the performance of the DUT. Examples of such a DC test include DUT leak current measurement, operation current (power supply current) measurement, breakdown voltage measurement, and the like.
The functional verification test and the DC test have various kinds of specific content for each of the various kinds of semiconductor devices. For example, in the memory functional verification test, first, a predetermined test pattern is written to the memory. Subsequently, the data thus written to the DUT is read out from the memory, and the data thus read out is compared with an expected value so as to generate pass/fail data which represents the comparison result. Although RAM and flash memory are both memory devices, different test patterns are written to the RAM and the flash memory. Furthermore, there is a difference in the writing/readout data units and the writing/readout sequence between the RAM test and the flash memory test.
In a D/A converter functional verification test, a digital signal is supplied to the input terminal of the D/A converter while sweeping the digital signal value in a predetermined range. With such an arrangement, an analog voltage is output from the D/A converter according to the respective digital values, and the analog voltage values thus output are measured. As a result, the offset voltage or the gain is measured.
On the other hand, in an A/D converter functional verification test, an analog voltage is supplied to the input terminal of the A/D converter while sweeping the analog voltage in a predetermined range. With such an arrangement, digital values are output from the A/D converter according to the respective analog voltage values, and the digital values thus output are measured. As a result, the INL (Integral Nonlinearity) or DNL (Differential Nonlinearity) is measured.
Micro-controllers, digital/analog hybrid devices, SoC, and the like, each include various kinds of built-in components such as RAM, flash memory, a D/A converter, and an A/D converter. Thus, there is a need to perform respective functional verification tests for the built-in components.
Furthermore, in many cases, a boundary scan test is executed for such a semiconductor device.
In the present specification, the test item, test pattern format, test sequence, test condition, and the like, are included in the concept that will be referred to as the "test algorithm".

This patent is subject to a terminal disclaimer.


A well fracturing system in which a fracturing fluid storage vessel, high pressure pump and high pressure conduit are connected in series to a well. A pressure vessel is connected to the high pressure conduit for injecting proppant carrying fracturing fluid into the well without the proppant carrying fracturing fluid passing through the high pressure pump. The pressure vessel may be formed of a pipe with a free floating piston dividing the pressure vessel into a drive side and driven side. Proppant carrying fracturing fluid is stored in the driven side, and may be emplaced within the pressure vessel at a remote site from the well. Drive fluid is injected into the drive side to force the proppant carrying fracturing fluid into the high pressure conduit and down the well. The drive fluid may be a diverted portion of fracturing fluid pumped by the high pressure pumper. Several pressure vessels may be used in parallel, and proppant may be stratified in the pressure vessel.

In conventional fracturing of wells, proppant and fracturing fluid are mixed in a blender and then pumped into a well. As a consequence, the blender, pump and lines carrying the fracturing fluid downstream of the blender are subject to wear from the proppant, which is frequently highly abrasive material such as sand. In addition, any flow meters or other apparatus in the lines are subject to wear and possible wash out due to the proppant. Such wear may result in failure of the equipment, or leaks that may be hazardous. The potential for wear and the possibility of fire resulting from a leak makes it necessary to inspect equipment regularly.
In addition, when proppant is mixed with fracturing fluid in a blender the proppant may clump together and it is difficult to ensure uniform mixing of the proppant in the fracturing fluid. Since fracturing operations are carried out very quickly, there is little time to rectify an error in proppant concentration, with the result that too little or too much proppant may be injected into the formation at a critical part of the fracturing operation. This may ruin the fracturing operation, or require it to be repeated, in the case that is feasible.


An odor control system for removing hydrogen sulfide from a gas stream. In a first chamber, the gas stream is initially treated with NaOH at low pH for removal of about 70% of the H.sub.2 S. Unreacted NaOH and the reaction product Na.sub.2 S flow into a first sump while the initially treated gas stream flows into a second chamber, fluidly connected to a second sump. In the second chamber, the gas stream is scrubbed with a solution of NaOH and NaOCl for scrubbing of the remaining H.sub.2 S before the cleaned gas is exhausted to atmosphere. From the second chamber, unreacted NaOH and NaOCl, together with reaction products sulfur, Na.sub.2 SO.sub.4 and Na.sub.2 S flow into the second sump. The contents of the two sumps are flushed out separately by adding make up water to each of them. Each sump has a separate drain and each drain empties into a common drain where the Na.sub.2 S from the first sump reacts with unreacted NaOCl from the second sump to produce sulfur and Na.sub.2 SO.sub.4. These products are then washed from the common drain into a sewer.

The increasing concentration of population in urban settings presents important environmental problems. Prominent among them is presented when it becomes desirable, from a public health or aesthetic consideration, to remove unwanted odorous constituents from a gas stream, prior to its release into the atmosphere.
Various techniques have been developed in response to the need for odorous constituent removal. As a general rule, an effective technique should be tailored to the particular constituent to be removed. In the waste water system environment, a primary cause of odor is hydrogen sulfide which is detectable by the human olfactory sense at very low concentrations. In addition to the unpleasant odor associated with it, hydrogen sulfide is noted for its toxicity and its capacity for corroding materials with which it comes in contact.
Because of the undesirability of introducing hydrogen sulfide into the atmosphere, it is desirable to have systems for removing, in a cost effective manner, substantial amounts of the unwanted substance, preferably at or near the source of its production.
As more particularly discussed in copending U.S. patent application Ser. No. 08/427,128, removal of odorous constituents from a waste gas stream can be accomplished by several techniques. In many cases, an odor control technique of choice is absorption, or chemical oxidation, a process in which odorous constituents in a gas stream are transferred into a liquid solution and are chemically oxidized in the liquid phase. Acceptance of this process is due, at least in part, to cost considerations, especially when large gas volumes, having relatively low concentrations of odorous constituents, are involved. In general, the technique is utilized in a packed tower conventionally known as a scrubber.
In scrubber systems utilizing the absorption method, reaction between chemical treating agents and the odorous constituents takes place in the liquid phase. Removal efficiency depends on the transfer rate of the compounds from air into liquid, and reaction kinetics. This, in turn, is dependent on the mass transfer coefficient and total interfacial surface area. Such considerations drive scrubber packed tower design.
A significant problem in conventional packed towers is plugging of the packing as a result of accumulation of solids. Such accumulations can quickly lead to reduced system efficiency. Plugging may be caused by a variety of operational parameters such as hardness of make-up water, the chemical reagents utilized, and system pH. It is generally recognized that plugging can be effectively reduced or eliminated by purging the system. In the purging process, an amount of the recirculation stream, together with an equal or greater amount of the by-product salts created and added to the system, must be constantly removed from the sump to prevent the accumulation of solids and resultant plugging. Fresh make-up water and new chemical reagent must be added to replace the purge stream.
However, a major concern in consideration of system purge rate is the cost of unreacted chemical reagent which is sent to the drain during the purging process. Over time, this cost can make system operation prohibitively expensive. The alternative, an inefficient, plugged system, is also unacceptable.
In other cases, hardness in the water supply and the carbonates which are often present cause precipitates to form on packing medium surfaces, especially when the system is operated at an elevated pH. In some cases, it becomes necessary to shut down the odor control system in order to acid wash or otherwise clean control system surfaces.
In view of the foregoing, it would be highly desirable to have an odor control system which could function efficiently while reducing scaling problems. Of course, it would be beneficial if such a system would conserve reagents, thereby reducing operating costs.
A review of prior art systems reveals that one conventional technique for scrubbing hydrogen sulfide includes using only sodium hydroxide while, in another technique, sodium hydroxide and sodium hypochlorite are utilized to oxidize the hydrogen sulfide. The advantages and disadvantages of each technique deserve some mention.
In the first case, in which NaOH only is used, typically in a single stage system, a reaction occurs as follows: EQU H.sub.2 S+2NaOH.fwdarw.Na.sub.2 S+2H.sub.2 O
An advantage of this conventional technique is that it is relatively inexpensive to operate since the cost to remove H.sub.2 S with sodium hydroxide is about eight to ten times less expensive than with sodium hypochlorite. As an example, for a gas stream flowing at 10,000 cfm, bearing 100 ppm H.sub.2 S, to have about 127 lbs./day of H.sub.2 S removed, the annual cost with NaOH as the reagent of choice is about $20,000 per year, compared with about $293,000 with other conventional systems, as pointed out below.
However, the cost advantage of the sodium hydroxide process is offset by several limitations. One limitation of the sodium hydroxide technique is that scaling is a problem. Another is that a long residence time is required for thorough gas treatment. This means that facility costs are increased because a large treatment tower is required. Another significant limitation is evident in some cases when system blow down is discharged into a sewer having an acidic pH. In these cases, the above reaction is reversible and, when the pH drops below about 7, H.sub.2 S is regenerated.
In addition to the foregoing limitations in the conventional sodium hydroxide system, such systems operate at high pH (typically 11-12). Hydrogen sulfide containing gases typically contain carbon dioxide which, at elevated pH, reacts with sodium hydroxide as follows: EQU CO.sub.2 +2NaOH.fwdarw.Na.sub.2 CO.sub.3 +H.sub.2 O
Thus, it will be appreciated that the presence of the carbon dioxide, coupled with the requirement of operating at an elevated pH, results in the need for additional sodium hydroxide than would be predicted for hydrogen sulfide removal alone. This factor, of course, means increased reagent usage resulting in elevated operating costs over the life of the system.
In the second conventional technique for removing hydrogen sulfide from a gas stream, sodium hydroxide is utilized in combination with sodium hypochlorite. System reactions, assuming complete oxidation, are as follows: EQU H.sub.2 S+2NaOH+4NaOCl.fwdarw.Na.sub.2 SO.sub.4 +4NaCl+2H.sub.2 O EQU NaOCl+H.sub.2 S.fwdarw.NaCl+H.sub.2 O+S
Advantages of this process, in contrast to the use of sodium hydroxide alone, are that the system pH is generally lower (typically 9-10) and CO.sub.2 absorption is reduced. In addition, less scaling occurs and there is less H.sub.2 S regeneration. Further, a smaller scrubber tower may be utilized, thereby reducing facility operating costs.
A significant disadvantage of the sodium hydroxide/sodium hypochlorite process is reagent cost. For example, in scrubbing the 10,000 cfm gas stream mentioned above, from which 127 lbs./day of H.sub.2 S are removed, typical annual operating costs can be as high as $293,000.
By way of summary of advantages and disadvantages of the two conventional processes described herein, reference may be made to Table I.
TABLE I ______________________________________ COMPARISON OF SYSTEMS UTILIZING NaOH WITH SYSTEMS UTILIZING NaOH and NaOCl ______________________________________ NaOH ADVANTAGE DISADVANTAGES ______________________________________ Low Operating Cost High pH (11-12) Scaling CO.sub.2 Absorption H.sub.2 S Regeneration Longer Residence Time ______________________________________ NaOH and NaOCl ADVANTAGES DISADVANTAGE ______________________________________ Lower pH (.about.10) High Operating Cost Lower CO.sub.2 Absorption Less Scaling No H.sub.2 S Regeneration Smaller Tower ______________________________________
As Table I shows, there are several advantages to the second process. In view of the comparative results, the second process would be expected to be the system of choice in many cases. However, the high annual operating cost, multiplied by the many years of useful life of a scrubber using the process, often makes the process economically prohibitive.
In view of the foregoing, it would be desirable to have an odor control system which affords the advantages of conventional systems while substantially avoiding their limitations. Ideally, such a system would be capable of efficient performance over many years with substantial reductions in operating costs, as compared to conventional systems.


A rotational phase difference of a camshaft relative to a crankshaft in a variable valve timing mechanism is controlled by an operation of an oil control valve. That is, in the oil control valve, there is outputted an operational signal which is defined by adding a feedback correction amount corresponding to a difference between an actual value and a target value of the rotational phase difference, to a holding learning value as the operational signal for holding the rotational phase difference. The holding learning value is altered only by a specified value on condition that the operational signal for holding the rotational phase difference is assumed to change.

A rotational phase difference-adjusting device varies a rotational phase difference of a camshaft relative to a crankshaft in an internal combustion engine for adjusting operating timing of an engine valve. The rotational phase difference-adjusting device is provided with a variable valve timing mechanism and an oil control valve. The variable valve timing mechanism is usually provided with rotational elements connected respectively to the crankshaft and the camshaft. An advance chamber for advancing a rotational angle of the camshaft and a retard chamber for retarding it are defined in the two rotational elements. The oil control valve is an electromagnetic driven type valve which supplies oil to one of the advance chamber and the retard chamber and discharges it from the other.
On the other hand, a control device for controlling the rotational phase difference, at the time of holding the rotational phase difference, operates the oil control valve to prevent inflow and outflow of oil between the advance chamber and the retard chamber. In addition, at the time of variably controlling the rotational phase difference to a desired value, the control device operates the oil control valve to adjust an inflow amount of the oil to one of the advance chamber and the retard chamber and an outflow amount of the oil from the other.
The variable control for the rotational phase difference actually sets as a reference a holding learning value as an operational signal of the oil control valve which can hold the rotational phase difference and is performed by operating the oil control valve with a feedback correction amount based upon a difference between an actual rotational phase difference and a target value. However, the operational signal which can hold the rotational phase difference changes with a rotational speed of the crankshaft, temperatures of oil or the like. This change invites deterioration in controllability of the feedback control.
Conventionally, there is, as shown in JP-8-74530A (U.S. Pat. No. 5,562,071), proposed a control device which in advance sets the holding learning value for each region of plural regions regionally divided based upon a rotational speed of a crank shaft and temperatures of oil. According to this technology, even if a learning value capable of holding the rotational phase difference in response to the rotational speed or the temperature of the oil changes, an appropriate holding learning value can be used, resulting in maintaining high controllability of the rotational phase difference.
In this case, however, since the holding learning value is required for each region, a great deal of work is to be required for adaptation of the holding learning value.
In view of the above, there exists a need for a control device for an engine valve and a control system for an engine valve which overcome the above mentioned problems in the conventional art. The present invention addresses this need in the conventional art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Control device for engine valve and control system for engine


A method for closing an incision (I) deep within a patient's body (B) with a suture (S). A medical instrument (C) has arms 1 and 2 for openings and closing opposed jaws (3,4). Each jaw has a pair of openings (3A-3B, 4A-4B). A knot (K) is formed using the ends (S1, S2) of the suture. For this purpose, the ends of the suture are withdrawn from the body. This allows the surgeon to form a proper surgical knot. After forming the knot, the suture ends are inserted through the respective pairs of openings. The surgeon can now draw the knot tightly down on the incision to close it by inserting the jaws end of the instrument into the patient's body while applying a slight pulling force on the ends of the suture. The surgical knot thus made will not thereafter loosen.

This invention relates to arthroscopic and/or endoscopic surgery and more particularly, to a method of performing a surgical procedure and a surgical appliance useful in performing the method.
In performing surgical procedures, one problem commonly encountered is tying off stitches closing an incision in such a way as to prevent the knot from loosening or coming undone. If the surgery is performed in a locale where the patient's skin is, or can be drawn back, exposing the surgical site, tying off stitches so they do not come undone should not be a problem. In arthroscopic and/or endoscopic surgeries where the surgical site is deep inside the body so the site is not readily accessible, this is not easily done. Because the surgical site is usually also very small, the surgeon is typically working in a very confined area and is probably using an endoscope in order to view the work he is performing. As a consequence, he does not have the space to make the type of surgical knot he would like to make, or to make it sufficiently tight it will not later loosen. The knot he uses in this situation is usually a slip knot, or some variation thereof, rather than a double knot which is preferred for closing incisions. If a knot becomes undone in this latter instance, the surgical site must be reopened so the stitches can be tied off again. This is not acceptable. It would be preferable if the surgeon could prepare the knot ex situ where there is adequate room for him to work, but current surgical procedures and instruments do not allow him to do so.


A method for packaging in block form a sheathed hot-melt adhesive product comprises the steps: (a) of continuously supplying a sheathed hot-melt adhesive product, (b) of immersing the sheathed hot-melt adhesive product in a liquid refrigerant, (c) of pressing the sheathed adhesive product at a portion thereof, (d) of ultrasonically welding the sheathed adhesive product at the pressed portion; and (e) of cutting the sheathed adhesive product into a block at the pressed portion. A block of sheathed hot-melt adhesive product and an installation for packaging a sheathed hot-melt adhesive product are also provided.

The invention relates to a novel device and a novel method for packaging in block form a sheathed hot-melt adhesive product.
Various ultrasonic welding devices are known.
Ultrasonic waves are waves with frequencies typically ranging between 15 kHz and a few hundred megahertz. High-intensity ultrasonic waves are able to alter the medium in which they propagate, with repercussions on the physicochemical properties of the medium.
An ultrasonic weld normally requires a transducer, a sonotrode and an anvil. The transducer produces ultrasound from which ultrasonic vibrations are generated. If applicable, a speed transformer amplifies these vibrations and transmits them to a sonotrode, which generally takes the form of a metal finger that can be vibrated at ultrasonic frequency. Layers of elements to be welded are generally placed between the anvil and the sonotrode. The hammering experienced locally transforms the elements and permits local interpenetration of the surfaces of these elements. The temperature rises, the deformation zone extends, and the weld is achieved. The weld is typically obtained in a few tenths of a second.
Routine applications using ultrasound include the cutting and slicing of soft products, stripping, the perforation of thin products, and the welding of hot-melt materials.
Various devices for packaging hot-melt adhesives are also known.
For example, in WO-A-94/13451, a mass of hot-melt adhesive is packaged directly by pouring or pumping the molten adhesive into a cylindrical thermoplastic tube, the cylindrical tube being in contact with a heat sink.
The packaged article resulting from this operation is supplied in the form of a handable bag or block which can be manufactured in an in-line operation.
In particular, the adhesive-filled tube is passed through rollers that press or pinch the filled cylinder in order to form bags of appropriate length. A liquid refrigerant is sprayed until the packaging is sufficiently cooled, so that the packaged adhesive forms a seal at the pressed or pinched portions. The sets of bags can then be cut at the pressed portions using conventional means, for example mechanical shears, laser, water jet, knife or hot wire, and then cooled to ambient temperature.
Document EP-A-0 957 029 discloses a method and an installation for packaging an adhesive product and similar products, the liquid adhesive product being sheathed in a protective sheath of a nonadhesive thermoplastic material. The adhesive product is sheathed by a coextrusion method. The coextrusion product thus formed, composed of the adhesive product and the protective sheath, is, at least as regards the protective sheath, solidified.
The advantage of sheathing the adhesive product in a nonadhesive sheath resides in the possibility of handling (particularly for transport, storage or packaging) or using the product after its manufacture.
It is also known to use a sheath that is miscible with the hot-melt adhesive at a given temperature. In this way, the product and its sheath can be melted together before application, without the need to remove the sheath.
However, the methods and devices described above are not compatible with the packaging of bags or blocks weighing more than 0.5 kg, and for certain compositions and sheath thicknesses. In fact, the heat and pressure exerted by the hot material in the sheath of the block formed are detrimental to the quality of the seal of the sheath. Typically, when the mass of sheathed adhesive exceeds the above values, the seal of the sheath yields (gaping occurs) at certain places. The adhesive product then comprises sticky zones that are detrimental to the subsequent handling or use of the product.

Device and method for packaging in block form a sheathed hot-melt adhesive product


An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically coupled to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region.

As is known, in the last few years a wide range of solutions has been developed for increasing the efficiency of semiconductor power devices, in particular in terms of increase in the breakdown voltage and decrease in the output resistance.
For example, U.S. Pat. Nos. 6,586,798, 6,228,719, 6,300,171 and 6,404,010, which are incorporated by reference, describe vertical-conduction semiconductor power devices, in which columnar structures of opposite conductivity are formed inside an epitaxial layer, forming part of a drain region having a given type of conductivity. The columnar structures have a dopant concentration which is substantially the same as, and of a type opposite to, the dopant concentration of the epitaxial layer in such a way as to provide a substantial charge balance (the so-called "Multi Drain (MD) technology"). The charge balance enables high breakdown voltages to be obtained, and moreover the high dopant concentration of the epitaxial layer enables a low output resistance (and low losses in conduction) to be achieved.
In brief, the formation of the aforesaid columnar structures envisages a sequence of steps of growth of N-type epitaxial layers, each step being followed by a step of implantation of a P-type dopant. The implanted regions are stacked so as to form the columnar structures. Next, body regions of the power device are formed in contact with the columnar structures, in such a manner that the columnar structures constitute an extension of the body regions into the drain region.
The evolution of this technology has witnessed a progressive increase in the density of the elementary strips forming the devices, for further increasing the charge concentration in the epitaxial layer and obtaining devices that, given the same breakdown voltage (which is substantially related to the height of the columnar structures), have a lower output resistance. On the other hand, however, the increase in the density of the elementary strips has led to a reduction of the thermal budget of the devices and a corresponding increase in the number of steps of epitaxial growth, and accordingly to an increase in the manufacturing costs and times, and in the defectiveness intrinsically linked to epitaxial growth.
Alternative technologies have consequently been developed to obtain charge-balance columnar structures; these technologies envisage, for example, formation of trenches inside the epitaxial layer and subsequent filling of the trenches with semiconductor material appropriately doped to obtain the charge balance.
For instance, in co-pending patent applications WO-PCTIT0600244, filed on Apr. 11, 2006, and WO-PCTIT0600273, filed on Apr. 21, 2006, both in the name of the present applicant and incorporated by reference, improved techniques (which will in part be referred to in what follows) have been described for the formation of trenches and their filling, in particular substantially free from residual defectiveness, to obtain charge-balance structures, and for the formation of semiconductor power devices provided with the charge-balance structures. In particular, in WO-PCTIT0600273 a non-selective epitaxial growth inside the trenches is proposed, also affecting a top surface of the layer in which the trenches are formed. Consequently, at the end of the epitaxial process a wrinkled surface layer made of semiconductor material may be formed, characterized by the presence of a plurality of grooves in areas corresponding to the columnar structures. It is also proposed to form the power devices at least in part inside this wrinkled surface layer.
Furthermore, as is known, the provision of efficient edge-termination structures is a key point for ensuring proper operation of power devices; in fact, it is in the edge areas that the largest number of breakdowns occur on account of the concentration of the electrical field lines due to the curvature of the edge regions. The edge terminations have the function of locally reducing the intensity of the electrical field so as to prevent peaks of intensity at the edges.
So far, the problem of providing edge-termination structures for charge-balance power devices, which enable maximization of the performance in reverse biasing of said devices, has not yet been solved in a satisfactory way for all applications.

Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device


Disclosed is an organic/inorganic composite porous separator comprising: (a) a polyolefin-based separator substrate; and (b) an active layer formed by coating at least one region selected from the group consisting of a surface of the substrate and a part of pores present in the substrate with a mixture of inorganic particles and a binder polymer, wherein the inorganic particles in the active layer are interconnected among themselves and are fixed by the binder polymer, and interstitial volumes among the inorganic particles form a pore structure. A method for manufacturing the same separator and an electrochemical device including the same separator are also disclosed. An electrochemical device comprising the organic/inorganic composite porous separator shows improved thermal and electrochemical safety and quality, simultaneously.

Recently, there is increasing interest in energy storage technology. Batteries have been widely used as energy sources in portable phones, camcorders, notebook computers, PCs and electric cars, resulting in intensive research and development for them. In this regard, electrochemical devices are the subject of great interest. Particularly, development of rechargeable secondary batteries is the focus of attention.
Among the currently used secondary batteries, lithium secondary batteries, developed in early 1990's, have a drive voltage and an energy density higher than those of conventional batteries using aqueous electrolytes (such as Ni-MH batteries, Ni—Cd batteries and H2SO4—Pb batteries), and thus are spotlighted in the field of secondary batteries. However, lithium secondary batteries have problems related to their safety, due to ignition and explosion caused by the use of organic electrolytes, and are manufactured by a complicated process. Lithium ion polymer batteries, appearing more recently, solve the above-mentioned disadvantages of secondary lithium ion batteries, and thus become one of the most potent candidates of next generation batteries. However, such secondary lithium ion polymer batteries still have low capacity compared to secondary lithium ion batteries. Particularly, they show insufficient discharge capacity at low temperature. Hence, there is an imminent need for the improvement of secondary lithium ion batteries.
A lithium ion battery is manufactured by coating a cathode active material (e.g. LiCoO2) and an anode active material (e.g. graphite), which have crystal structures including interstitial volumes, onto the corresponding current collector (i.e. aluminum foil and copper foil, respectively) to provide a cathode and an anode. Then, a separator is interposed between both electrodes to form an electrode assembly, and an electrolyte is injected into the electrode assembly. During a charge cycle of the battery, lithium intercalated into the crystal structure of the cathode active material is deintercalated, and then intercalated into the crystal structure of the anode active material. On the other hand, during a discharge cycle, lithium intercalated into the anode active material is deintercalated again, and then intercalated back into the crystal structure of the cathode. As charge/discharge cycles are repeated, lithium ions reciprocate between the cathode and the anode. In this regard, a lithium ion battery is also referred to as a rocking chair battery.
Such batteries have been produced by many battery producers. However, most lithium secondary batteries have different safety characteristics depending on several factors. Evaluation of and security in safety of batteries are very important matters to be considered. Particularly, users should be protected from being damaged by malfunctioning batteries. Therefore, safety of batteries is strictly restricted in terms of ignition and combustion of batteries by safety standards.
Many attempts have been made to solve the problem related to the safety of a battery. However, ignition of a battery, caused by a forced internal short circuit due to external impacts (particularly, in the case of a customer-abused battery) cannot be solved yet.
Recently, U.S. Pat. No. 6,432,586 discloses a polyolefin-based separator coated with an inorganic layer such as calcium carbonate, silica, etc., so as to prevent an internal short circuit, caused by dendrite growth inside of a battery. However, the polyolefin-based separator merely using conventional inorganic particles cannot provide significant improvement in the safety of a battery, when the battery experiences an internal short circuit due to external impacts. There is no mechanism for preventing such problem in the separator. Additionally, the inorganic particle layer disclosed in the above patent is not particularly defined in terms of the thickness, pore size and porosity. Moreover, the inorganic particles used in the separator have no lithium conductivity, and thus cause a significant drop in the quality of a battery.

Organic/inorganic composite microporous membrane and electrochemical device prepared thereby


An animal amusement device includes a base having an upwardly opening recess in which a corrugated scratch pad is installed. A pole extends upwardly from the base through the scratch pad and journals at its upper end a rotatable arm. The arm suspends an object by a flexible tether cord radially outward of the pole and above the level of the upper surface of the scratch pad. In another embodiment, the arm is mounted to a drive shaft of a motor secured in the pole whereby the object may be driven in a circular path about the pole by the motor.

1. Field of the Invention
This invention relates generally to animal toys, and more particularly, but not by way of limitation, to an improved scratch pad and amusement device for cats in particular.
2. Brief Description of the Related Art
Various cat amusement devices are known to the art that include a corrugated paper scratch pad installed within the recess of a base. In some of these devices, the base includes an endless track surrounding the pad that opens to either the top or side to receive and guide a ball around the track when the ball is struck by the cat. U.S. Pat. Nos. 5,269,261 and 5,572,955 are examples of this type of amusement device.
Manufacturing the base with a track adds to the complexity and cost of producing the device and restricts movement of the ball to the confines of the track.


A data-driven system for fast response to security vulnerability, in one example embodiment, comprises a request detector, a content type evaluator, and a presentation module. A request detector may be configured to detect a request to display content. A content type evaluator may be configured to determine a type of the requested content. A presentation module may be configured to selectively display the requested content based on the determined type of the requested content. The content type evaluator and the presentation module may utilize a data file that stores information related to potential vulnerabilities associated with a content viewing application. Example data file may be an XML file.

The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A computer system may be a subject of attacks by intruders who utilize malicious computer code downloaded onto the system in order to jeopardize or corrupt data or applications resident on a computer system, or to otherwise compromise the integrity of the system. Both network and stand alone computer systems may be subject to such intrusion. The intrusion typically is the result of malicious code gaining access to and changing the content of a portion of the computer system's visual control software. Some existing solutions addressing security of a computer system include virus checkers, security risk evaluators, etc. For example, computer users fight against viruses by applying a security patch to the computer's operating system and applications, updating the current virus definition file, and executing a virus check. In particular, as a countermeasure against a new strain of virus, users need to update the current virus definition file and execute a virus check immediately after notified of a new virus definition file being available.

Data driven system for responding to security vulnerability


The present disclosure provides a three-coil type round window driving vibrator, which includes a permanent magnet having the same magnetic poles adjoining each other and is designed to allow electric current flowing through coils to run in opposite directions in order to increase driving force without being affected by an external magnetic field. The round window driving vibrator includes a permanent magnet having three poles of SNS or NSN, a coil member wound around an outer periphery of the permanent magnet, and a vibration member connected to one end of the permanent magnet. Here, the coil member includes a first coil wound around a middle section of the permanent magnet and second and third coils wound around upper and lower sections of the permanent magnet, respectively.

1. Technical Field
The present invention relates to a round window driving vibrator, and more particularly to a two-magnet three-coil type round window driving vibrator, which is provided to an inlet of a round window in a cochlea to allow a person suffering from hearing loss to hear, and includes two permanent magnets arranged to have the same magnetic poles adjoining each other and three coils disposed around the permanent magnets such that a direction of electric current flowing through one of the coils is opposite to the direction of the electric current flowing through another coil adjacent thereto, in order to increase driving force without being affected by an external magnetic field.
2. Description of the Related Art
In many countries, as a low birth rate and increasing longevity lead to an expanding elderly population and the number of persons suffering from hearing loss increases due to frequent exposure to noise in daily life, demand for medical devices and otologic surgery for hearing aid tend to increase.
Hearing aids serve to amplify and modulate sound for a person suffering from hearing loss and can be classified based on the degree of difficulty in hearing and the placement position into an external type and an internal type. External type hearing aids can be conveniently mounted on the external ear, but has a disadvantage in that it cannot satisfy the needs for persons suffering from severe hearing loss.
Thus, internal type hearing aids are suited to persons suffering from severe hearing loss and can be classified into an implantable artificial middle ear for replacing the middle ear and an implantable artificial inner ear for replacing the inner ear.
The implantable artificial middle ear hearing aid generally includes a microphone and a vibrator, and has been mainly studied in that this type of hearing aid can achieve effective transfer of sound signals to persons suffering from severe hearing loss through a simple structure thereof. The human ear is composed of an external ear, a middle ear and an inner ear, and external sound signals are sequentially transferred therethrough. Most implantable artificial middle ear hearing aids are designed to apply vibration to the oval window of the cochlea through these paths of the ear. Recently, however, it has been spotlighted to develop implantable artificial middle ear hearing aids which apply vibration from the round window of the cochlea through a reverse path.
In the implantable artificial middle ear hearing aid, the vibrator may be classified into an electromagnetic vibrator including a permanent magnet and a coil, and a piezoelectric vibrator including a piezoelectric device and electrodes. In designing the vibrator of the implantable artificial middle ear hearing aid, various factors such as biostability, biocompatibility, a smaller volume for easier implantation, and low power consumption are taken into consideration. To this end, there is a need for high performance vibrators. Particularly, despite low design costs, the piezoelectric vibrator has difficulty in realizing a high voltage output unit for operation of the vibrator while minimizing power consumption under spatial restriction.
Although the electromagnetic vibrator is broadly used for compensating for hearing of a person suffering from sensorineural hearing loss, a round window driving vibration transducer employing the electromagnetic method provides low driving force, making it difficult to achieve improved efficiency, particularly, in a high frequency band.

Three-coil type round window driving vibrator having excellent driving force

KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION


The invention provides an interfacing circuit for a removable microphone. In one embodiment, the interfacing circuit comprises a jack for receiving the removable microphone and an integrated circuit comprising a biasing circuit, a buffer amplifier, and an insertion detecting circuit. The jack comprises a first terminal receiving an output voltage of the removable microphone and a second terminal coupling the removable microphone to a ground voltage source. The integrated circuit is coupled to the first terminal of the jack via a first node. The biasing circuit, coupled between the first node and a second node, biases the removable microphone and passes only an alternative current (AC) portion of the output voltage of the removable microphone to the second node. The buffer amplifier, coupled to the second node, buffers the AC portion to generate a voltage signal. The insertion detecting circuit, coupled to the first node, generates an insertion signal indicating whether the removable microphone is inserted in the jack.

1. Field of the Invention
The invention relates to microphones, and more particularly to microphone circuits.
2. Description of the Related Art
When audio processing devices are required to record audio signals, the audio processing devices need microphones for converting exterior sound pressures to electric signals. A microphone may be an optional removable component of an audio processing device and inserted to a jack of the audio processing device or removed from the jack of the audio processing device for a user's convenience. Thus, the audio processing device must comprise an interfacing circuit for detecting insertion of the removable microphone in the jack and biasing the removable microphone.
Referring to FIG. 1A, a block diagram of a conventional interface circuit 100 without a microphone plug inserted therein is shown. The interface circuit 100 comprises a jack 102, a resistor 106, a capacitor 108, and an integrated circuit 104. The jack 102 comprises terminals 112 and 116 and a metal sheet 114. The terminal 116 is coupled to a ground voltage source VGND via a node 136. The metal sheet 114 is coupled to a node 144 in the integrated circuit 104 via a node 134. The terminal 112 is coupled to a node 132. The resistor 106 has a resistance ranging between 2.2 kΩ and 4.7 kΩ and is coupled between a high voltage source VDD and the node 132, wherein a voltage of the high voltage source VDD ranges from 2V to 10V. The capacitor 108 has a capacitance ranging between 0.1 μF and 10 μF and is coupled between the node 132 and a node 142 in the integrated circuit 104.
The integrated circuit 105 comprises resistors 122, 124, and 126, an operational amplifier 128, and an analog-to-digital converter 130. The resistor 126 has a high resistance ranging between 200 kΩ and 2 MΩ and is coupled between a high voltage source VDD and the node 144. The resistor 122 is coupled between the node 142 and a negative input terminal of the operational amplifier 128. The resistor 124 is coupled between the negative input terminal of the operational amplifier 128 and an output terminal of the operational amplifier 128. A positive input terminal of the operational amplifier 128 is coupled to a reference voltage source VR. The output terminal of the operational amplifier 128 is further coupled to an input terminal of the analog-to-digital converter 130.
The integrated circuit 104 detects a voltage of the node 144 to determine whether a microphone plug is inserted in the jack 102. When there is no microphone plug inserted in the jack 102 as shown in FIG. 1A, the voltage of the node 144 is at a high level VDD. When there is a microphone plug inserted in the jack 102, the voltage of the node 144 is at a ground level VGND. Referring to FIG. 1B, a block diagram of a conventional interface circuit 150 with a microphone plug 160 inserted therein is shown. The microphone plug 160 comprises a sleeve and a tip respectively coupled to one output terminal of an electret condenser microphone (ECM). When the microphone plug 160 is inserted in the jack 102, the terminal 116 of the jack 102 couples the sleeve of the microphone plug 160 to the ground voltage source VGND. In addition, the sleeve 160 presses the metal sheet 114 of the jack 102 to couple the metal sheet 114 to the ground voltage source VGND. The voltage of the node 144 is therefore lowered to the ground voltage VGND when the microphone plug 160 is inserted in the jack 102.
When the microphone plug 160 is inserted in the jack 102 as shown in FIG. 1B, the terminal 112 of the jack 102 couples the tip of the microphone plug 160 to the node 132. Because a terminal of an electret condenser microphone is coupled to the tip of the plug 160, the high voltage source VDD can therefore bias the electret condenser microphone via the tip of the plug 160. In addition, an AC portion of an output voltage of the electret condenser microphone passes through the capacitor 108 to the node 142. Because the resistors 122 and 124 and the operational amplifier 128 form an amplifier with an inverse configuration, the AC portion of the output voltage of the electret condenser microphone is then amplified by the operational amplifier 128 and delivered to the analog-to-digital converter 130 for analog-to-digital conversion.
The conventional interface circuit 100, however, has a few shortcomings. First, the metal sheet 114 increases the hardware cost of the jack 102. Additionally, the resistor 106 and the capacitor 108 are not integrated into the integrated circuit 104 and must be provided on a printed circuit board, increasing layout cost of the interfacing circuit 100. Moreover, the integrated circuit 104 must have two pins, increasing hardware cost of the integrated circuit 104, wherein a pin couples the node 142 to the capacitor 108 and a pin couples the node 144 to the node 134. Thus, an interfacing circuit for a microphone is therefore provided to reduce hardware cost.

Interfacing circuit for a removable microphone


A quarter wavelength plate for reducing the dependence of a retardation value on an incident beam angle in optically anisotropic crystals. The quarter wavelength plate is formed of optically anisotropic crystals in a thickness of 0.1 mm to 0.5 mm. The quarter wavelength plate can contribute to a reduction in the dependence of the retardation value on the angle at which a light beam impinges on the quarter wavelength plate, and to a reduction in color shading caused by a rise in temperature. A reflection type liquid crystal display device which employs the quarter wavelength plate can enhance the luminance and contrast.

The present invention relates to a quarter wavelength plate which is particularly advantageous in enhancing the contrast, and an optical unit using the same for use in a reflection type liquid crystal display device.
A reflection type liquid crystal display device using a reflex liquid crystal display element for displaying images is disclosed, for example, in JP-B-7-38050.
FIG. 1 is a schematic diagram illustrating an optical unit in the reflection type liquid crystal display device disclosed in the above-cited document. The optical unit herein referred to is assumed to be an optical display device which comprises a light source, an illumination optical system, a video display element, and a projection lens. The video display element is irradiated with light from the light source through the illumination optical system. A light intensity modulation is performed for converting the irradiated light to the contract of each pixel on the video display element. A resulting image is enlarged by the projection lens for display.
In FIG. 1, the optical unit comprises a light source 1, a polarization beam splitter 2, a quarter wavelength plate 3, a reflex liquid display element 4, and a projection lens 5.
Light from the light source 1 is split by the polarization beam splitter 2 into an S-polarization component which is reflected by the beam splitter 2 and a P-polarization component which transmits the beam splitter 2. The S-polarization component reflected by the polarization beam splitter 2 transmits the quarter wavelength plate 3 and impinges on the reflex liquid crystal display element 4. The S-polarization component is converted to a P-polarization component by the reflex liquid crystal display element 4. The resulting light for producing a bright display again transmits the quarter wavelength plate 3, and is projected onto a screen by the projection lens 5 along a light path which extends through the polarization beam splitter 2. The light not converted by the reflex liquid crystal display element 4 again transmits the quarter wavelength plate 3 and travels back to the light source 1 along a light path which is bent by the polarization beam splitter 2.
Here, the quarter wavelength plate 3 is used with the intention of improving the contrast which would be degraded by incident light on the polarization beam splitter, tilted with respect to the optical axis, in the reflection type liquid crystal display device, as disclosed in detail in JP-B-7-38050.
Materials suitably used for forming the quarter wavelength plate include, for example, a stretched polycarbonate film adhered on a glass substrate (hereinafter called the "phase difference film"), a crystal having optical anisotropy such as quartz.
FIG. 2 is a schematic diagram illustrating a quarter wavelength plate which is formed of a stretched polycarbonate film adhered on a glass substrate. In FIG. 2, the quarter wavelength plate comprises the glass substrate 6, the stretched polycarbonate film 7, and a phase delay axis 8 of the quarter wavelength plate.
FIG. 3 in turn is a schematic diagram illustrating a quarter wavelength plate formed of quartz, which is for use in a reflection type liquid crystal display device. In FIG. 3, the quarter wavelength plate 12 comprises a reference axis 9; a first optically anisotropic crystal 10 having a phase delay axis 131 which is parallel with the reference axis 9; and a second optically anisotropic crystal 11 having a phase delay axis 132 which is perpendicular to the reference axis 9. The quarter wavelength plate 12 is formed by adhering the first optically anisotropic crystal 10, the phase delay axis 131 of which is parallel with the reference axis 9, to the second optically anisotropic crystal 11, the phase delay axis 132 of which is perpendicular to the reference axis 9. The quarter wavelength plate 12 has a thickness t which is conventionally set to approximately 1.0 mm from a viewpoint of workability.
In the optical unit for use in a reflection type liquid crystal display device, a retardation value required to a quarter wavelength plate is in a range of 100 to 180 nm because visible light has wavelengths ranging from 400 to 700 nm. The retardation value used herein refers to the product of a difference between the refractive index in the direction of the phase delay axis of the quarter wavelength plate and the refractive index in the direction of the phase advance axis perpendicular to the phase delay axis (hereinafter called the "birefringence difference") and the thickness of the quarter wavelength plate. However, for providing the above-mentioned retardation value, for example, with a quarter wavelength plate formed of quartz chosen from among optically anisotropic crystals, the quarter wavelength plate must be made to have a thickness of approximately 15 μm or less because quartz has the birefringence difference of approximately 0.009. However, a quarter wavelength plate having a thickness of 15 μm or less is virtually impossible from viewpoints of the yield rate and strengths of parts in the manufacturing. To solve this problem, two optically anisotropic crystals having a thickness of approximately 1.0 mm are adhered with their phase delay axes oriented orthogonal to each other, as illustrated in FIG. 3. By ensuring that a difference between the retardation value of the first optically anisotropic crystal, the phase delay axis of which is parallel with the reference axis, and the retardation value of the second optically anisotropic crystal, the phase delay axis of which is perpendicular to the reference axis, falls within a range of 100 to 180 nm, it is possible to achieve the retardation value required for a quarter wavelength plate for use in an optical unit of a reflection type liquid crystal display device.

Quarter wavelength plate and projection type video display device using the same


A lamp for a vehicle includes an array module including a plurality of micro Light Emitting Diode (LED) chips. The array module has an emission surface that is concave in a first direction of the array module. The lamp further includes a lens system configured to change a waveform of light output from the array module, where the lens system has a positive optical power that represents a degree of convergence of the waveform through the lens system.

A vehicle is an apparatus that can transport a user in a direction desired by the user. One example of a vehicle may be an automobile.
A vehicle may include lamps that can be classified as lamps for securing visibility for a driver (e.g., a head lamp and a fog lamp), and lamps for notifying a signal (e.g., a rear combination lamp).
Various devices may be used as light sources of the lamps provided in a vehicle.
Recently, there have been efforts to utilize a plurality of micro Light Emitting Diode (LED) chips as light sources of the lamps for vehicle.
It is of interest to enhance light output efficiency of a vehicular lamp including a plurality of micro LED chips while ensuring visibility for a driver and transmitting a notifying signal from the vehicle.