A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits wherein semiconductor-on-insulator techniques are employed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, which include, in particular, field effect transistors. In a field effect transistor, a gate electrode may be separated from a channel region by a gate insulation layer that provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are provided.
The channel region, the source region and the drain region may be formed in a semiconductor material, wherein the doping of the channel region is different from the doping of the source region and the drain region. Depending on an electric voltage applied to the gate electrode, the field effect transistor may be switched between an on-state, wherein there is a relatively high electrical conductance between the source region and the drain region, and an off-state, wherein there is a relatively low electrical conductance between the source region and the drain region.
For improving the performance of integrated circuits including field effect transistors, it has been proposed to employ semiconductor-on-insulator technology. In semiconductor-on-insulator technology, a semiconductor-on-insulator structure is provided. The semiconductor-on-insulator structure includes a thin layer of a semiconductor material, for example silicon, that is provided above a substrate of a semiconductor material, for example silicon. The layer of semiconductor material is separated from the substrate by a layer of an electrically insulating material, for example silicon dioxide. Compared to integrated circuits wherein field effect transistors are formed on a bulk semiconductor substrate, semiconductor-on-insulator technology allows reducing parasitic capacitances and leakage currents. Moreover, integrated circuits formed in accordance with semiconductor-on-insulator technology may be less sensitive with respect to ionizing radiation.
However, semiconductor-on-insulator technology has some specific issues associated therewith, which include the so-called floating body effect. The body of a field effect transistor forms a capacitor with the insulated substrate. In this capacitor, electric charge can accumulate and cause adverse effects, which may include a dependence of the threshold voltage of the field effect transistor on its previous states.
For substantially avoiding the floating body effect, it has been proposed to use fully depleted field effect transistors. Fully depleted field effect transistors are formed using a semiconductor-on-insulator structure wherein the semiconductor layer provided on the insulator layer has a smaller thickness than a channel depletion width of the field effect transistor. Thus, the electric charge and, accordingly, the body potential of the field effect transistor are fixed.
However, fully depleted field effect transistors may be less suitable for some applications, including the processing of input to a digital integrated circuit and output from a digital integrated circuit. For such applications, field effect transistors formed on a bulk substrate may provide more appropriate device characteristics. Moreover, field effect transistors formed on a bulk semiconductor substrate may be of advantage when used in analog integrated circuits.
In view of the situation described above, the present disclosure relates to a structure and a method for the formation thereof that allow using the advantages of semiconductor-on-insulator structures in parallel with devices that may benefit from a bulk semiconductor substrate.

Semiconductor structure including a semiconductor-on-insulator region and a bulk region, and method for the formation thereof


The invention includes Rh(D) binding proteins, including antibodies, and DNA encoding such proteins. Methods of generating such proteins and DNAs are also included.

The ability to produce monoclonal antibodies has revolutionized diagnostic and therapeutic medicine. Monoclonal antibodies are typically produced by immortalization of antibody-producing mouse lymphocytes thus ensuring an endless supply of cells which produce mouse antibodies. However, for many human applications, it is desirable to produce human antibodies. For example, it is preferable that antibodies which are administered to humans for either diagnostic or therapeutic purposes are human antibodies since administration of human antibodies to a human circumvents potential immune reactions to the administered antibody, which reactions may negate the purpose for which the antibody was administered.
In addition, there exists certain situations where, for diagnostic purposes, it is essential that human antibodies be used because other animals are unable to make antibodies against the antigen to be detected in the diagnostic method. For example, in order to determine the Rh phenotype of human red blood cells (RBCs), human sera that contains anti-Rh antibody must be used since other animals cannot make an antibody capable of detecting the human Rh antigen.
The production of human antibodies in vitro by immortalizing human B lymphocytes using Epstein Barr virus (EBV)-mediated transformation or cell fusion has been fraught with technical difficulties due to the relatively low efficiency of both EBV-induced transformation and cell fusion when compared with the murine system. To overcome these problems, processes have been developed for the production of human antibodies using M13 bacteriophage display (Burton et al., 1994, Adv. Immunol. 57:191-280). Essentially, a cDNA library is generated from mRNA obtained from a population of antibody-producing cells. The mRNA encodes rearranged immunoglobulin (Ig) genes and thus, the cDNA encodes the same. Amplified cDNA is cloned into M13 expression vectors creating a library of phage which express human Fab fragments on their surface. Phage which display the antibody of interest are selected by antigen binding and are propagated in bacteria to produce soluble human Fab Ig. Thus, in contrast to conventional monoclonal antibody synthesis, this procedure immortalizes DNA encoding human Ig rather than cells which express human Ig.
There are several difficulties associated with the generation of antibodies using bacteriophage. For example, many proteins cannot be purified in a non-denatured state, in that purification procedures necessarily involve solubilization of protein which may render some proteins permanently denatured with concomitant destruction of antigenic sites present thereon. Such proteins thus cannot be bound to a solid phase and therefore cannot be used to pan for phage bearing antibodies which bind to them. An example of such a protein is the human Rh antigen.
To solve the problem, a method was developed wherein intact RBCs were used as the panning antigen (Siegel et al., 1994, Blood 83:2334-2344). However, it was discovered that since phage are inherently "sticky" and RBCs express a multitude of antigens on the cell surface, a sufficient amount of phage which do not express the appropriate antibody on the surface also adhere to the RBCs, thus rendering the method impractical for isolation of phage which express antibody of desired specificity.
De Knif et al. (1995, Proc. Natl. Acad. Sci. USA 92:3938-3942) disclose a method of isolating phage encoding antibodies, wherein antibody-expressing phage are incubated with a mixture of antigen-expressing cells and cells which do not express antigen. The antibody-expressing phage bind to the antigen-expressing cells. Following binding with phage, a fluorescently labeled antibody is added specifically to the antigen-expressing cells, which cells are removed from the mixture having antibody-expressing phage bound thereto. The isolation of fluorescently labeled cells is accomplished using the technique of fluorescently-activated cell sorting (FACS), an expensive and time-consuming procedure.
There remains a need for a method of isolating recombinant proteins, preferably antibodies, which is rapid and economical, and which will provide a vast array of protein-binding proteins useful for diagnostic and therapeutic applications in humans.

This patent is subject to a terminal disclaimer.

Compositions and methods for detection of antibody binding to cells

The Trustees of the University of Pennsylvania


A beverage holder for a video monitor, such as a computer monitor, a laptop computer monitor, a television, etc. The beverage holder is either formed integrally with the video monitor or is removably attachable to the video monitor. Several embodiments of a beverage holder are described. Each embodiment includes a generic video monitor with an integral or removably attachable beverage holder for supporting a beverage container which could include a variety of hot or cold beverages, such as a cup or mug, or a can of the type used with soft drinks, beer and other beverages which are normally chilled before being served and consumed. The beverage holder is generally in the form of a relatively thin surface of firm material. For example, the beverage holder may be insertable into a slot in the side wall or underneath the video monitor where it can be secured when not in use. The beverage holder may also be attached to a pivotable arm which may be attached to the top of the video monitor. Finally, the beverage holder may be integrally molded into the side wall of the video monitor in the form of a recessed slot which can receive a beverage container. The particular beverage holder geometry and dimensions are variable so as to suit the desires of the user.

1. FIELD OF THE INVENTION
The present invention relates generally to beverage holders, and more particularly, to integral and attachable cup holders for video monitors, such as computer monitors, laptop computer monitors, televisions, etc.
2. DESCRIPTION OF THE RELATED ART
Many people drink hot or cold beverages while watching a video monitor, such as a computer monitor, a laptop computer monitor, a television, etc., so a beverage container, such as a coffee mug or a pop can, is often placed within arm's reach near the video monitor. Coasters have long been used to protect furniture against the damage caused by moisture from cans, bottles and like containers. A vast majority of soft drinks, fruit juices, beer, wine coolers and other consumable beverages are sold in cans, bottles and other like containers which have been cooled either by refrigeration or immersion in ice cubes or ice water preparatory to being served. People are generally conditioned not to place a beverage container directly on a table top or desktop simply to avoid the risk of leaving water marks on the desktop. Particularly on fine furniture, a moist or dripping can or bottle can cause considerable damage through water stains, veneer separation, raised grain and discoloration of any table cloths or other coverings. It would be desirable for video monitors to be equipped with beverage holders.
The related art is represented by the following patents of interest.
U.S. Pat. No. 4,828,211, issued on May 9, 1989 to Deal McConnell et al., describes a beverage holder that can be mounted on the sides or walls of a vessel. McConnell et al. do not suggest a beverage holder for a video monitor according to the claimed invention.
U.S. Pat. No. 4,984,722, issued on Jan. 15, 1991 to Steven W. Moore, describes a beverage holder for use in automobiles. Moore does not suggest a beverage holder for a video monitor according to the claimed invention.
U.S. Pat. No. 5,167,392, issued on Dec. 1, 1992 to Douglas A. Henricksen, describes a beverage holder for use in automobiles. Henricksen does not suggest a beverage holder for a video monitor according to the claimed invention.
U.S. Pat. No. 5,318,266, issued on Jun. 7, 1994 to Hui-Long Liu, describes a collapsible beverage holder. Liu does not suggest a beverage holder for a video monitor according to the claimed invention.
U.S. Pat. No. 5,423,508, issued on Jun. 13, 1995 to Steven R. Isenga et al., describes a beverage holder for a moving vehicle. Isenga et al. do not suggest a beverage holder for a video monitor according to the claimed invention.
U.S. Pat. No. 5,533,697, issued on Jul. 9, 1996 to James R. Fletcher et al., describes a mouse pad with a hole formed through the mouse pad to selectively retain a beverage container proximate the mouse pad. Fletcher et al. do not suggest a beverage holder for a video monitor according to the claimed invention.
International Patent Application (PCT) Number WO 92/11793, published on Jul. 9, 1992, describes a beverage holder for use in automobiles. PCT '793 does not suggest a beverage holder for a video monitor according to the claimed invention.
Japan Patent Document Number 6-270730, published on Sep. 27, 1994, describes an adjustable beverage holder. Japan '730 does not suggest a beverage holder for a video monitor according to the claimed invention.
None of the above inventions and patents, taken either singularly or in combination, is seen to describe the instant invention as claimed.


A method for compressing speech. An audio signal comprising speech is broken down into its phonetic components. These phonetic components are then converted into data elements that represent each of the phonetic components. The determination of data elements is accomplished using a predefined table that correlates phonetic sounds to data elements. The data elements representing the phonetic sounds are then stored.

Signal compression is the translating of a signal from a first form to a second form wherein the second form is typically more compact (either in terms of data storage volume or transmission bandwidth) and easier to handle. The second form is then used as a convenient representation of the first form. For example, suppose the water temperature of a lake is logged into a notebook every 5 minutes over the course of a year, generating thousands of pages of raw data. After the information is collected, however, a summary report is produced that contains the average water temperature calculated for each month. This summary report contains only twelve lines of data, one average temperature for each of the twelve months.
The summary report is a compressed version of the thousands of pages of raw data because the summary report can be used as a convenient representation of the raw data. The summary report has the advantage of occupying very little space (i.e. it has a small data storage volume) and can be transmitted from a source, such as a person, to a destination, such as a computer database, very quickly (i.e. it has a small transmission bandwidth).
Sound, too, can be compressed. An audio signal comprising spoken words (speech) comprises continuous waveforms that are constantly changing. The signal is compressed into a digital format by a process known as sampling. Sampling an audio signal involves measuring the amplitude of the analog waveform at discrete intervals in time, and assigning a digital (binary) value to the measured amplitude. This is called analog to digital conversion.
If the time intervals are sufficiently short, and the binary values provide for sufficient resolution, the audio signal can be successfully represented by a finite series of these binary values. There is no need to measure the amplitude of the analog waveform at every instant in time. One need only sample the analog audio signal at certain discrete intervals. In this manner, the continuous analog audio signal is compressed into a digital format that can then be manipulated and played back by an electronic device such as, for example, a computer or a personal digital recorder. In addition, audio signals can be further compressed, once in the digital format, to further reduce the data storage volume and transmission bandwidth to allow, for example, high quality audio signals to be quickly transmitted across even low bandwidth interlinks.

Compressing speech into a digital format


An air intake system comprising an air duct suitable for providing airflow to the inside of an aircraft, preferably to an auxiliary power unit; an inlet arranged at one end of the air duct; a skin surrounding the inlet; a plurality of slots arranged on the skin; a driving arrangement, a flap door connected to the driving arrangement, and a plurality of fins connected to the driving means. The driving arrangement is configured for moving the flap door between at least two positions, the positions being a closed position wherein the flap door closes the inlet, and an opened position wherein the flap door is driven away from the closed position. The driving arrangement is also configured for moving the plurality of fins such that the plurality of fins protrudes through the slots.

In the aircraft industry, air intake systems are installed in parts of the aircraft that need air supply for feeding a number or systems, like the auxiliary power unit.
Normally, the air intake systems are positioned as close to the systems they feed as possible, for example at the tail of the aircraft in the case of the auxiliary power unit. As a consequence, the inlet of the air intake systems can be shadowed by other aircraft parts like the wing, the engines, or the fuselage itself. Furthermore, they operate often under adverse pressure gradients for the intake of air, which may result in the reverse of the flow of the stream of air in different areas of the ducts. Therefore, the process of drawing air from the surrounding stream is carried out under unfavorable conditions that needs solutions to increase the efficiency of air ingestion.
In order to redirect and convey the stream of air directly into the ducts, some aircraft have implemented different solutions such as doors in the fuselage that open when the intake of air is needed. Another solution is installing scoops that extend from the aircraft surface and keep interfering with the air stream for the entire aircraft performance.
However, these solutions present some disadvantages. First, the presence of bodies in the stream of air increases aerodynamic drag. Also, as it is well known in the field of aerodynamics, the extent of separation of the boundary layer of the air stream depends on the flying conditions. Generally, when the speed of the aircraft increases, the boundary layer separates from certain curved aircraft surfaces and turns turbulent. As a consequence, the boundary layer in the ducts tends to turn turbulent and separate, thus creating areas where the effectiveness effectiveness of the intake is greatly reduced, an effect that reduces the overall air intake effectiveness effectiveness.
As a result, the effectiveness of the intake of air is greatly reduced depending on the flight conditions.
One solution developed in order to minimize the problems derived from the boundary layer separation phenomenon is the implementation of vortex generators before (upstream of) the inlet. Vortex generators are known and commonly used in the architecture of aerodynamic surfaces meant to fly at high Mach numbers. They are usually installed before control surfaces like spoilers or ailerons in order to increase their efficiency, reducing the amount of separated boundary layer of the air stream.
Vortex generators energize the air stream, generating micro turbulences in the boundary layer, which makes the boundary layer less prone to separate, thus helping to delay the separation.
However, the presence of the vortex generators in every stage of the flight is not always recommended. At low Mach numbers, where the boundary layer tends to remain laminar and adhered, and, therefore, does not need of any auxiliary element, the vortex generator's only contribution is increasing aerodynamic drag, thus increasing the fuel consumption while providing the aircraft performance with no positive effects at all.


A delay circuit that includes a logic gate through which an input signal passes, a capacitor configured to be charged and discharged at an output terminal of the logic gate and delaying the input signal, and a mirroring unit configured to constantly maintain current output by the logic gate by mirroring current output by a constant current source.

The present invention relates to a technology for preventing a delay value of a delay circuit whose function is to adjust a sensing margin of a bit line sense amp (BLSA) in a semiconductor memory device according to variations of process, voltage, and temperature (PVT) conditions in a chip. The delay circuit of the invention can be applied to a variety of integrated circuits (ICs) and semiconductor devices as well as semiconductor memory devices.
FIG. 1 is a circuit diagram illustrating a core region of a conventional semiconductor memory device, and FIG. 2 is a timing diagram illustrating the operation of a core region of a semiconductor device. The operation of a core region of a semiconductor memory device will be described with reference to FIGS. 1 and 2.
Once an active command is inputted, a word line is enabled (i.e., WL='high') and a transistor 101 is turned on. Therefore, data stored in a cell capacitor 102 may experience a charge-sharing phenomenon with respect to a bit line BL. Accordingly, nodes SA and SAB have a predetermined potential difference ΔV and, a bit line sense amp (BLSA) 103 is enabled after a predetermined delay (i.e., a sensing margin shown in FIG. 2) elapses. Thus, the nodes SA(BL) and SAB(BLB) have a predetermined potential difference between an effective ground VSS and a core operating voltage VCORE (it is assumed that data of 0 is stored in a cell capacitor).
Here, a time difference between when the word line WL is enabled and when the bit line sense amp (BLSA) 103 is enabled is called a sensing margin. If the time difference becomes shortened and the bit line sense amp (BLSA) 103 is enabled without adequate ΔV, data cannot be amplified properly. Consequently, a read failure occurs. Additionally, if the sensing margin exceeds a predetermined level, time for performing a read operation is increased such that tRCD (an important parameter of a memory device) also is increased.
Accordingly, the minimum sensing margin is secured under the PVT conditions in order for a memory device to operate stably and fast.
Signals BISH and BISL of FIG. 1 are signals for connecting and disconnecting the bit lines BL and BLB of a cell array with the bit lines SA and SAB of the bit line sense amp (BLSA) 103. A signal BLEQ is a bit line equalize signal for equalizing the bit lines BL and BLB during a precharge operation. The signal BLEQ is known to those skilled in the art. Thus, its detailed description will be omitted for conciseness.
FIG. 3 is a view illustrating a part for driving a word line and a sense amp in a conventional semiconductor memory device. As illustrated in FIG. 3, the conventional semiconductor memory device includes a word line driving circuit 310 for driving a word line WL, and a sense amp driving circuit 330, a delay circuit 320, and the sense amp driving circuit 330.
Once an active command is inputted, a word line enable signal WLE is enabled. In response to the word line enable signal WLE, the word line driving circuit 310 enables the word line WL.
The word line enable signal WLE is also inputted to the delay circuit 320, and the delay circuit 320 delays the word line enable signal WLE by its delay value and then outputs the delayed sense amp enable signal SAE. The sense amp driving circuit 330 enables the bit line sense amp (BLSA) 103 of FIG. 1 in response to the sense amp enable signal SAE. The bit line sense amp (BLSA) 103 is enabled by supplying driving voltages RTO and SB.
The word line enable signal WLE for determining the timing of enabling the word line WL is delayed by the delay circuit 320 and thus becomes the sense amp enable signal SAE for determining the timing of enabling the bit line sense amp (BLSA) 103. A time difference between enabling the word line WL and enabling the bit line sense amp (BLSA) 103 is the sensing margin of the bit line sense amp (BLSA) 103. As a result, a delay value of the delay circuit 320 becomes the sensing margin of the bit line sense amp (BLSA) 103.
Accordingly, the delay value of the delay circuit 320 corresponds to a very important factor during a particular operation of a core region of a memory device.
FIG. 4 is a circuit diagram illustrating a detail structure of the delay circuit 320 of FIG. 3. As illustrated in FIG. 4, the conventional delay circuit 320 delays a word line enable signal WLE through a plurality of capacitors 450 to 480 disposed between a plurality of inverters 410 and 440.
In relation to the above-mentioned operation, the inverters 410 to 440 invert an input signal (i.e., the word line enable signal WLE), and capacitors 450 to 480 are discharged and charged by a current flowing through transistors and resistors 411, 421, 431 and 441 in the inverters 410 and 440. The capacitors 450 to 480 are charged and discharged and also delay a time for transmitting the word line enable signal WLE. Accordingly, the word line enable signal WLE inputted to the delay circuit 320 is delayed by the inverters 410 to 440 and the capacitors 450 to 480, and then becomes a sense amp enable signal SAE. For reference, N+ active resistors are typically used as the resistors 411, 421, 431 and 441.
A delay time of the delay circuit 320 is dependent upon a time for charging and discharging the capacitors 450 to 480. Also, the time for charging and discharging the capacitors 450 to 480 is dependent upon a current flowing through the capacitors 450 to 480. The current flowing through the capacitors 450 to 480 may vary according to the resistance values of the transistors and the N+ active resistors 411, 421, 431 and 441, which constitute the inverters 410 to 440.
If a fabrication line of a semiconductor memory device is changed or its fabrication process is unstable, the resistance values of the transistors and the N+ active resistors 411, 421, 431 and 441, which constitute the inverters 410 to 440, are changed. Additionally, the changed resistance values affect a time for charging and discharging the capacitors 450 to 480. That is, a delay value of the delay circuit 320 having a conventional structure may vary greatly if the fabrication line is altered or its fabrication process is performed with no predictable pattern.
FIG. 5 is a view illustrating a change of a sensing margin according to a design of the delay circuit 320. A reference letter (A) represents a case in which a delay value of the delay circuit 320 is designed with a relatively small value, and a reference letter (B) represents a case in which a delay value of the delay circuit 320 is designed with a relatively large value. A reference letter FF represents a condition of when a delay value of the delay circuit 320 is the smallest because a fabrication process has a fast characteristic and a power supply voltage VDD is high. A reference letter NOM is represents a condition of when a delay of the delay circuit 320 is average because a fabrication process has an average characteristic and a power supply voltage VDD is average. A reference letter SS represents a condition of when a delay value of the delay circuit 320 is the largest because a process has a slow characteristic and a power supply voltage VDD is low.
First, let's examine the case (A). According to the conventional delay circuit 320, a delay change varies greatly according to changes of a fabrication process and a power supply voltage, as mentioned above. Therefore, the fabrication process is performed being biased toward a direction where the fabrication process is performed at a faster speed, and a delay value of the delay circuit 320 may become smaller than the minimum sensing margin SM_MIN in the case FF. If a delay value of the delay circuit 320 becomes smaller than the minimum sensing margin SM_MIN, the bit line sense amp (BLSA) 130 starts an amplification process when charge sharing is not completely finished. This causes a read failure.
To resolve the limitation of the case (A), let's examine the case (B) in which a delay value of the delay circuit 320 is designed with a large value.
In the case (B), because a delay value of the delay circuit 320 is designed with a large value, the delay circuit 320 has a larger delay value than the minimum sensing margin SM_MIN even under the condition FF. However, under the condition SS (i.e., the delay value of the delay circuit is largest), a delay value of the delay circuit 320 increases excessively such that an operating speed of a memory device can deteriorate.
That is, if a delay value of the delay circuit 320 is changed according to the conditions, the minimum sensing margin SM_MIN may not be obtained (i.e., the case A) or an operating speed of a memory device can deteriorate (i.e., the case B), leading to undesirable operation.
Therefore, a delay circuit capable of having a predetermined delay value constantly even when conditions are changed is desirable.

Delay circuit and semiconductor memory device including the same


This invention provides in a safe and effective manner the experience of observing potential collision obstacles or other hazard images to the human operator of an otherwise conventional vehicle, (such as an automobile or aircraft) moving in a normal manner in a natural environment (such as an outdoor test track). The invention incorporates in addition to the mobile vehicle, computer-based image generation devices, and position, velocity, acceleration, measurement instruments to enable the simulated visual hazard images, including operator perception of and response to those hazard images. Making the actual moving vehicle part of the simulated hazard encounter means the vestibular (motion) cues and visual cues of the natural environment are very realistic, while only the computer-generated hazard images imposed on the natural environment view are virtual. The system results in a safe and cost efficient way of producing a realistic experience of vehicle operation encounters, including both the observation and response.

Since the advent of computer technology first made them possible, vehicle simulators have been used for a number of purposes, including research, training, and vehicle engineering. Simulators have become increasingly prevalent and useful for reproducing the experience of operating aircraft, motor vehicles, trains, spacecraft, and other vehicles. Aviation simulators have become particularly prevalent, with nearly every airline now using simulators for training and research—the first time a commercial pilot flies a new aircraft, it is often filled with passengers. The military services use simulators extensively for training personnel in the operation of ships, tanks, aircraft, and other vehicles.
Despite their varied usage, simulators, especially those providing the operator(s) with motion cues, have primarily remained the tools of large organizations with significant financial resources. The use of motor vehicle (i.e., driving) simulators has not yet progressed beyond manufacturers, suppliers, government agencies (including the military), and academic institutions, largely because of their cost. However, driving simulators have a number of valuable safety applications. First, they offer research into driver response behavior. Highways are becoming populated by more vehicles, moving at greater speeds, with a greater portion of drivers comprised of older adults with reduced sensory and response capabilities. Cellular telephones, navigation systems, and other devices (often developed by third parties and added to vehicles without suitable integration with manufacturer-supplied devices) place increased demands on the driver's attention, and drugs continually arrive on the market that affect driver alertness. These factors mandate a better understanding of driver limitations, particularly those of older drivers. Researching driver behavior in emergencies by examination of real accidents has limited yield, because every accident is unique to some extent, determining causation is difficult, and controlled experimental research is inherently not possible for real accidents. Driving simulators could provide data on the driver's response to emergency situations without exposure to actual risk.
Second, simulators can provide an improved means for training and evaluating drivers. Most driver training is conducted either in classrooms or in automobiles in normal traffic, which rarely exposes trainees to unexpected hazards. Devices that would allow trainees to experience potential collision situations, visibility hazards, or other unusual driving situations, without actual exposure to risk would provide useful training.
Third, simulators provide manufacturers and suppliers useful data from which to further develop their products. Vehicle manufacturers, suppliers and car/truck fleet owners usually perform developmental tests in actual vehicles, but this is limited to experiences not involving collision or other hazards. The use of simulators to perform these functions is costly, particularly for programming and measuring motion and configuring the simulator to represent the appropriate vehicle, limiting the usefulness of these simulators for most research applications.
Simulators are primarily tasked with recreating the sensory cues their "real-world experience" counterparts offer. Most state of the art simulators do a credible job recreating visual and audible stimuli, but only the most expensive provide credible cues for the vestibular senses (controlled by semicircular canals in the inner ear, which sense rotary acceleration, and otolith organs, which sense translational acceleration) and the muscle and joint sensors of motion. Motor vehicle simulators, in particular, struggle to provide a faithful motion representation without exorbitant cost. Because of the cost of providing such functionality, relatively few driving simulators even attempt to provide motion cues, despite the fact that tests reveal subjects tend to over-steer or experience vertigo because of a mismatch between visual and motion cues. Those that provide motion cues usually do so with an expensive hydraulic simulator base, but very few motion-base driving simulators are in use, and even these lack the ability to accurately convey translational acceleration. Some state of the art simulators promise to rectify this problem, but this capability typically entails a significant cost. Clearly, simulators that represent motion cues faithfully are not cost-effective research or training tools for most applications. FIG. 1 shows the state-of-the-art National Advanced Driving Simulator operated by University of Iowa for the Department of Transportation. Motion fidelity requires the test driver to ride inside a cab moving on a 20×20 meter X-Y hydraulic motion platform while viewing a computer-generated 360 degree screen.
The same financial barriers that prevent more widespread use of driving simulators have also prevented the development of simulators for the operation of wheelchairs, skis, snowboards, and many other vehicles which move, sometimes at high speeds, when in actual operation. Clearly the availability of more cost-effective simulators could enable better research, training, and engineering, resulting in safer and more user-friendly vehicles, both those indicated above and others, and in better, safer operation thereof.

Vehicle operations simulator with augmented reality


The invention provides a character and picture data compression apparatus which can collectively compress document data of the character code form and still picture data and moving picture data of the bit map form. A conversion section converts document data of the character code form into those of the bit map form. A display image composition section composes the document data of the bit map form, still picture data of the bit map form and a first one frame of moving picture data into a display image of the first page, and then produces, for each of the succeeding frames, a display image wherein the moving picture data portion in the display image of the first page is replaced with moving picture data of the frame. A difference processing section calculates, for each of the display images of the succeeding pages, a difference from the display image of the immediately preceding page in the bit map form. A bit map data compression section successively receives the display image of the first page and the display images of the succeeding pages obtained by the difference processing section and performs compression of the images in units of one page.

1. Field of the Invention
This invention relates to a character and picture data compression apparatus which collectively compresses document data of the character code form and still picture data and moving picture data of the bit map form of binary or multiple values.
2. Description of the Related Art
Much effort has been and is being directed to development of a portable terminal equipment wherein character data and/or picture data of binary or multiple values of characters, line drawings, photographs and so forth recorded in a book, a newspaper, a magazine or the like are recorded onto an electronic, optical or magnetic recording medium. Thus, allowing the recorded data to be read out and developed into a display image so that it may be displayed on a display apparatus such as a liquid crystal display apparatus, or an equipment wherein a display image developed in such a manner as described above is displayed on a display apparatus such as a CRT (cathode ray tube) apparatus. Meanwhile, as a result of development of multi-media in recent years, recording data often include, in addition to character data and still picture data, moving picture data of binary or multiple values called simplified animation.
FIG. 6 shows a system construction by which a display image in which characters, a still picture and a moving picture are included in a mixed condition which is displayed. Referring to FIG. 6, document data wherein characters and so forth are represented in character codes of 2 bytes are recorded in a character recording apparatus 101, and still picture data and moving picture data of the bit map form are recorded in a still picture recording apparatus 102 and a moving picture recording apparatus 103, respectively. When the data are to be displayed, a display image composition section 104 reads out the document data from the character recording apparatus 101 and passes them on to a data display section 105 so that the document is displayed in a document displaying area of a screen of a display apparatus 106. Simultaneously, the display image composition section 104 reads out the still picture data of the bit map form from the still picture recording apparatus 102 and passes them on to the data display section 105 so that the still picture is displayed in a still picture displaying area of the screen of the display apparatus 106. Further, the display image composition section 104 reads out the moving picture data of the bit map form of the first page from the moving picture recording apparatus 103 and passes them on to the data display section 105 so that the moving picture data are displayed in a moving picture displaying area of the screen of the display apparatus 106. Similarly, the display image composition section 104 successively reads out the moving picture data of the bit map form of the second and succeeding pages at predetermined time intervals and passes them on to the data display section 105 so that the moving picture display area of the screen of the display apparatus 106 is successively updated with the moving picture data.
In the system construction described above, where a recording medium having a comparatively small recording capacity such as a floppy disk is used for any of the recording apparatus 101 to 103, or even if a recording medium having a sufficiently large recording capacity is employed, where a large amount of still picture data or moving picture data is to be stored, care must be taken regarding the shortage of the recording capacity of the recording apparatus.
FIG. 7 shows another system construction which solves the problem just described. Referring to FIG. 7, the system shown includes three decompression sections 107, 108 and 109 in addition to similar components to those of the system described above with reference to FIG. 6. In the present system, document data compressed using a known data compression technique are recorded into the character recording apparatus 101 whereas data of a still picture and a moving picture of the bit map form compressed using a known data compression technique are recorded also into the still picture recording apparatus 102 and the moving picture recording apparatus 103, respectively. Then, when the data are to be displayed, the data are decompressed by the decompression sections 107, 108 and 109 and then passed on via the display image composition section 104 to the data display section 105 so that they are displayed in the individual displaying areas of the screen of the display apparatus 106.
With the construction of the system of FIG. 7, since a document, a still picture and a moving picture are recorded in individually compressed conditions, the capacity required for each recording apparatus is small compared to that of the system of FIG. 6. The data compression techniques for a document, a still picture and a moving picture have exhibited remarkable progresses in recent years, and data compression techniques having a high compression efficiency have been proposed. Thus, use of any of the techniques would allow further reduction in storage capacity.
For example, Japanese Patent Laid-Open Application No. Heisei 2-205982 discloses a technique wherein a nature of a picture of an object of compression is identified based on a statistical distribution of the compression object picture, and an optimum one of a plurality of data compression algorithms prepared in advance is selectively used based on a result of the identification to compress data. This technique can be utilized for compression of still picture data.
Meanwhile, Japanese Patent Laid-Open Application No. Showa 64-10387 discloses another technique wherein a moving picture is represented in difference data between frames and the data are represented in two kinds of binary data to perform compression processing such as run-length compression which is used for compression of ordinary frame data. This technique can be utilized for compression of moving picture data. Further, various methods have been proposed for the compression technique of character codes, such as a method which employs a combination of several coding methods. Those techniques can be utilized for compression of document data. Naturally, also such a high efficiency coding technique as the MPEG or the JPEG can be applied to compression of moving picture data.
In this manner, the approaches to reduction in storage capacity in systems which display a display image in which a still picture and a moving picture are included in a mixed condition have been principally directed to an effort to raise the compression efficiency of document data themselves, a still picture itself or a moving picture itself. Consequently, although the compression efficiency exhibits some improvement, since the document data, still picture and moving picture are compressed independently of each other, another problem is invited that a large scale is required for a compression apparatus used for compression of those data. Particularly, with such a system which selectively uses a plurality of data compression algorithms, as disclosed in Japanese Patent Laid-Open Application No. Heisei 2-205982 mentioned hereinabove, or another system which compresses character codes using a combination of several coding methods, the problem of increase in scale of the compression apparatus is even more significant.

Apparatus for converting document data into bit map data and compressing display image formed by combining the bit map data and image data


The present invention makes it possible to inexpensively and quickly execute a process of rewriting data stored in a memory, thus reducing the power consumption of an information processing apparatus. In connection with a conventional Read-Modify-Write function, an information processing apparatus 1 first issues a write instruction, and after all the write commands in the write instruction have been issued, issues read commands from the read instruction. That is, the read commands are issued immediately after the write commands without issuing a precharge command from the write instruction or an active command from the read instruction. This serves to avoid executing the precharge and active commands between instructions which commands are unwanted for accesses to the same row address. The adverse effect of a CAS latency can also be avoided. Therefore, it is possible to inexpensively and quickly execute the process of rewriting data stored in the memory.

1. Field of the Invention
The present invention relates to an information processing apparatus that reads and rewrites information stored in a memory as well as a method of accessing the memory.
2. Description of the Related Art
General-purpose memories such as SDRAM (Synchronous Dynamic Random Access Memories) have hitherto been used for information processing such as image processing.
With these memories, a specified bit width is set as a management unit. For example, for a memory with connections made using a 32-bit data bus, predetermined 32 bits are generally read and written at a time.
Thus, when an attempt is made to write data of a size smaller than the management unit described above (for example, 4-bit data) to the memory, the data in the other part of the management unit (for example, the remaining 28-bit data) may have invalid values.
Thus, a technique called Read-Modify-Write is used in order to prevent such a situation. The Read-Modify-Write technique employs a method of reading the whole data for the management unit containing write data specified, rewriting only the rewrite data part, and then writing the rewritten data for the management unit back to the memory.
For a memory such as an SDRAM which has the concept of pages, a memory access speed is often improved using a method called a burst transfer which transfers all data corresponding to a plurality of addresses within the same page at a time. In this case, the management unit described above corresponds to the amount of data transferred during a single burst transfer. For example, for a memory with connections made using a 32-bit data bus, if 4-word data is transferred during a single burst transfer, the management unit is 128 bits (32 bits×4 words).
FIG. 6 is a timing chart showing the case in which the read, modify, and the write technique is executed in a conventional information processing apparatus. FIG. 7 is a flow chart of the timing chart shown in FIG. 6.
In FIG. 7, when the Read-Modify-Write is specified, the information processing apparatus issues an active command (step S101). The information processing apparatus waits for one cycle (executes NOP) (step 102).
In this case, the information processing apparatus waits for one cycle. However, the information processing apparatus may wait for two or more cycles or zero cycle (no wait) depending on the specifications of the SDRAM used. This also applies to all the wait steps.
Subsequently, the information processing apparatus issues a read command (which reads data directly from the memory) (step S103). The information processing apparatus then determines whether a burst transfer of read data from the memory has been finished (step S104). If the information processing apparatus determines that the burst transfer has not been finished, it shifts to the processing in the step S103. On the other hand, if the information processing apparatus determines that the burst transfer has been finished, it waits for a number of cycles required in step S105. Then, in step S106, the information processing apparatus issues a precharge command. However, since the timing chart in FIG. 6 indicates that the SDRAM used is of a type that does not require the wait in step S105, FIG. 6 does not show the wait in step S105.
Then, the information processing apparatus waits for one cycle (step S107). The information processing apparatus then rewrites the data read from the memory (step S108).
The processing in step S108 is executed in parallel and thus does not appear in the timing chart in FIG. 6.
Subsequently, the information processing apparatus issues an active command for a succeeding write (step S109). The information processing apparatus waits for one cycle (step s110).
Then, the information processing apparatus issues a write command (which actually inputs and writes data to the memory) (step S111). The information processing apparatus then determines whether or not a burst transfer of write data to the memory has been finished (step S112).
In step S112, if the information processing apparatus determines that the burst transfer of the write data to the memory has not been finished, it shifts to the processing in step S111. If the information processing apparatus determines that the burst transfer of the write data to the memory has been finished, it waits for one cycle (step S113).
Then, the information processing apparatus issues a precharge command (step S114) and then waits for one cycle (step S115). The information processing apparatus then finishes executing the Read-Modify-Write.
However, if Read-Modify-Write such as that shown in FIG. 6 is executed, a process must be executed in order to protect data that is not rewritten; data for the management unit is read from the memory and then changed, and the data changed is written back to the memory. This increases the time required for processing.
Thus, various methods for improving the Read-Modify-Write technique have been proposed.
For example, the technique described in JP5-266177A omits a write command if rewriting is not required. Further, the technique described in JP2003-256271A masks parts that are desired not to be rewritten.
In addition, the technique described in JP8-123402A or JP8-123716A are known.
However, the prior art, including the techniques described in the above publications, increases the speed of a process of rewriting the memory under special conditions. Thus, the prior art is not applicable to general purposes.
Further, the prior art requires a memory having a special structure, thus increasing costs.
In other words, it is difficult to inexpensively and quickly execute a process of rewriting data stored in the memory. As a result, a long time is required to rewrite data. This is one of the causes of an increase in the power consumption of the information processing apparatus.
It is an object of the present invention to enable the inexpensive and quick execution of a process of rewriting data stored in the memory, to reduce the power consumption of the information processing apparatus.

Information processing apparatus and method of accessing memory


An acceleration sensor includes a housing member, a spring member attached to the housing member, the spring member having freedom in at least one direction of acceleration to be detected, a weight and magnetic field generation member fixed to the spring member, and at least one magnetic field detection sensor attached to the housing member to face the weight and magnetic field generation member. The at least one magnetic field detection sensor is provided with at least one multi-layered MR element including a magnetization fixed layer and a magnetization free layer. A direction of magnetic field applied to the at least one multi-layered MR element from the weight and magnetic field generation member is perpendicular to a lamination plane of the at least one multi-layered MR element when no acceleration is applied.

1. Field of the Invention
The present invention relates to an acceleration sensor with at least one magnetoresistive effect (MR) element and to a magnetic disk drive apparatus with the acceleration sensor.
2. Description of the Related Art
There are magnetic disk drive apparatuses or hard disk drive (HDD) apparatuses assembled in mobile equipments such as for example walkabout personal computers, mobile phones and other mobile gears, provided with shock sensors. The shock sensor generates a signal for immediately interrupting write current when a drop impact is applied to the HDD apparatus so as to avoid corruption of data written in a magnetic recording medium or a hard disk.
The shock sensor is used to merely detect whether a certain impact is applied or not. Therefore, corruption of the written data due to the drop impact can be prevented to some extent, but it is impossible to prevent a collision of a magnetic head with the hard disk surface due to the drop impact and thus damage of the hard disk and breakage of the magnetic head may be induced.
In order to reliably prevent both corruption of data and damages of the magnetic head and the hard disk, it is necessary to detect the instant at which the HDD apparatus falls before occurrence of drop impact and to retract the magnetic head from the hard disk surface. Such instant of the falling can be detected from a change in the acceleration of gravity.
Japanese patent publication No. 02-248867A discloses a piezo-electric type acceleration sensor for detecting a small change in the acceleration of gravity from a change in stress of springs. This sensor has springs in dual tuning fork vibrators, a weight supported by the springs, and piezo-electric elements attached on the springs to detect the change in stress applied to the springs from the weight.
U.S. Pat. No. 5,747,991 discloses an electrostatic capacitance type acceleration sensor for detecting a small change in the acceleration of gravity from a displacement of a weight. This sensor has a movable electrode and a static electrode faced to each other to detect a change in electrostatic capacitance from a change in distance between the movable and static electrodes due to the acceleration.
Such known piezo-electric type acceleration sensor or electrostatic capacitance type acceleration sensor needs to have electrodes for extracting detection signals there from on the spring or the weight attached to the spring and also lead lines electrically connected to the electrodes. Thus, the structure of the sensor becomes complicated due to the lead lines connected to the electrodes. Also, when the spring and weight are miniaturized, wiring process of such lead lines becomes extremely difficult. Further, the lead lines formed on the miniaturized spring or weight may induce breakage of the spring when an excessive value of impact is applied, and prevent movement of the spring to interface with the improvement in sensitivity of the sensor. This tendency becomes more pronounced as the acceleration sensor becomes smaller.
U.S. Pat. No. 6,131,457 discloses an acceleration sensor that may solve the above-mentioned problems in the conventional piezo-electric type acceleration sensor and electrostatic capacitance type acceleration sensor. This acceleration sensor has a magnetic body including a mass point, mounted to a vibrator having three-dimensional freedom and an axis in line with a Z-axis, and four or more detector MR elements positioned on an X-axis and a Y-axis with their centers located along a perimeter of a concentric circle around the origin point of the orthogonal coordinate axes. The sensor is thus capable of detecting each of acceleration in the direction of X-axis through a relative difference in output voltage between the two detector elements on the X-axis due to a vibration of the magnetic field, acceleration in the direction of Y-axis through a relative difference in output voltage between the two detector elements on the Y-axis due to a vibration of the magnetic field, and acceleration in the direction of Z-axis through a sum total of the output voltages of all the detector elements.
According to the acceleration sensor disclosed in U.S. Pat. No. 6,131,457, as it is not necessary to form electrodes on the spring nor the weight, the structure of the sensor becomes simple. However, because an anisotropic MR (AMR) element with a single layer structure of an MR material is used as for each magnetic field detector element, two or more detector elements are necessary for detecting acceleration in a direction along a single axis. Thus, this acceleration sensor requires the great number of detector elements causing the miniaturization of the sensor itself to become extremely difficult. Also, wiring of the many detector elements induces complicated structure of the sensor. Furthermore, using of the AMR elements causes lower sensitivity of the magnetic field, so that it is difficult to provide a highly sensitive acceleration sensor.

Acceleration sensor and magnetic disk drive apparatus


According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.sub.4 F.sub.8 /Ar or C.sub.4 F.sub.8 /CO/Ar mixture. There is no longer the notion of process window because both the "silicon polish" and "Si.sub.3 N.sub.4 pad residuals" type of defects are eliminated. The present method offers significant advantages in terms of final test yield improvement, cost reduction and reproducibility.

In the manufacture of semiconductor integrated circuits (ICs), deep and shallow isolation trenches are extensively used, in particular in the manufacture of 16 Mbits DRAM chips. Deep trenches are created in a silicon substrate to define the storage capacitors while shallow trenches are used to isolate each capacitor trench from its neighbours. As far as shallow isolation trenches are concerned, a conventional process includes three basic steps: (1) forming shallow trenches in a silicon substrate provided with a patterned Si.sub.3 N.sub.4 layer (IT mask), (2) filling said trenches with a layer of an insulating material such as TEOS SiO.sub.2 and (3) planarizing the insulating layer. All these processing steps are conducted in the Shallow Trench Isolation (STI) module. The planarization basic step mentioned above is basically comprised of two main steps: (1) forming a layer of a planarizing medium having a substantially planar surface onto the TEOS SiO.sub.2 layer and (2) a RIE etching (AB etch) followed by a chemical-mechanical polishing of the structure (referred to hereinbelow as the planarization main step). The aim of the planarization basic step as a whole is to produce a surface of the TEOS SiO.sub.2 as planar as possible without any defect.
FIG. 1 schematically illustrates a structure 10 which is a part of a wafer consisting of a silicon substrate 11 with a passivation layer 12 formed thereon. Typically, this passivation layer 12 consists of a 14.5 nm thick SiO.sub.2 bottom layer and a 175 nm (nominal) thick top Si.sub.3 N.sub.4 layer. The passivation layer 12 will be referred to hereafter as the Si.sub.3 N.sub.4 layer 12 for sake of simplicity. Basically, substrate 11 is comprised of two regions 13 and 14 referred to as the "array" and ".kerf/support/street" regions respectively. The memory elements, each being comprised of an active device (an IGFET) and a capacitor are integrated in the "array" area. The ".kerf/support/street" area includes all the test devices and the "glue" circuitry that are necessary to make these memory elements operative. Deep isolation trenches are only formed in the "array" region 13 as standard. Two deep trenches referenced 15A and 15B are shown in FIG. 1. Each deep trench, generically referenced 15 is partially filled with intrinsic polysilicon whose upper portion is doped. A classic ONO (Oxide/Nitride/Oxide) layer 16 isolates the polysilicon fill 17 from the silicon substrate 11. Surrounding the top portion of the polysilicon fill 17, an SiO.sub.2 collar 18 is provided to increase the isolation between the doped polysilicon and the ONO layer 16 on the trench sidewall. As apparent from FIG. 1, the thickness of the Si.sub.3 N.sub.4 layer 12 is substantially thinner above the "array" region 13 than above the ".kerf/support/street" region 14, e.g. about 120 nm compared to about 150 nm (there has been a partial consumption of the Si.sub.3 N.sub.4 material forming passivation layer 12 mainly during collar formation). As such, structure 10 is a typical example of a part of a silicon wafer after a conventional deep isolation trench process used in the fabrication of 16 Mbits DRAM chips. Now, the shallow isolation trenches have to be delineated in the silicon substrate 11.
First, the structure 10 of FIG. 1 is coated with a layer 19 of a photosensitive material having a thickness of about 1.1 um. An adequate material is the photoresist labelled IP3250 commercially sold by TOKYO-OHKA, Tokyo, Japan. After deposition, the photoresist layer 19 is exposed, then baked and developed as standard to leave the patterned layer or mask still referenced 19 in FIG. 2. The purpose of this mask 19, referred to as the IT mask, is to define the locations of the shallow trenches at the surface of the silicon substrate 11. After the IT mask 19 has been defined, the process continues with the IT etch. The wafer is placed in an AME 5000, a MERIE plasma etcher manufactured by Applied Materials Inc., Santa Clara, Calif., USA with the following operating conditions:
NF.sub.3 . . . : 8 sccm PA1 N2 . . . : 65 sccm PA1 CHF.sub.3 . . . : 4 sccm PA1 Pressure . . . : 5.32 Pa (40 mTorr) PA1 Power . . . : 600 W PA1 Mag. field . . . : 0 Gauss PA1 Temp. cathode.: 20.degree. C. PA1 Time . . . : 275 s PA1 CHF.sub.3 . . . : 70 sccm PA1 NF.sub.3 . . . : 60 sccm PA1 Pressure . . . : 18.25 Pa (137 mTorr) PA1 Mag. field . . . : 0 Gauss PA1 RF Power . . . : 562 W PA1 Optical endpoint: Yes PA1 Overetch . . . : 12 s PA1 Sel. resist/TEOS: 1.5/1 (blanket) PA1 Uniformity . . . : <2% PA1 CHF.sub.3 . . . : 80 sccm PA1 NF.sub.3 . . . : 50 sccm PA1 Pressure . . . : 30 Pa (220 mTorr) PA1 Mag field . . . : 20 Gauss PA1 RF Power . . . : 700 W PA1 Etch time . . . : 30 sec PA1 Sel. resist/TEOS: 1/1 (blanket) PA1 Uniformity . . . : <2% PA1 CHF.sub.3 . . . : 95 sccm PA1 CO.sub.2 . . . : 40 sccm PA1 Pressure . . . : 20 Pa (150 mTorr) PA1 Mag. field . . . : 25 Gauss PA1 RF Power . . . : 900 W PA1 Optical endpoint: Yes PA1 Overetch . . . : No PA1 Sel. TEOS/resist: 6/1 (blanket) PA1 Uniformity . . . : <3%
This etching mixture is not selective and thus attacks the different materials (polysilicon, SiO.sub.2, Si.sub.3 N.sub.4 and monocrystalline silicon) forming the exposed layers substantially at the same rate down to a deepness of about 675 nm. The IT mask 19 is then removed by ashing as standard. At this stage of the process, the structure 10 is shown in FIG. 3. Now turning to FIG. 3, two different sized shallow trenches, a narrow and a relatively wide, have been shown and are referenced by numerals 20A and 20B. In the "array" region 13, shallow trenches are required to nest the active devices of the memory elements and therefore must be as small as possible to increase integration density. On the contrary, in the ".kerf/support/street" area, the trenches are relatively wide for test device isolation. As apparent from FIG. 3, it remains isolated Si.sub.3 N.sub.4 pads still referenced 12.
The next step consists in the thermal growth of a sacrificial thin SiO.sub.2 layer on the portions of horizontal surfaces that are not protected by said Si.sub.3 N.sub.4 pads 12 and on the sidewalls of the shallow trenches 20A and B formed in the silicon substrate 11. This oxidation of silicon surfaces is performed in order to eliminate surface damages due to the preceding reactive ion etching (RIE) step (IT etch). At this stage of the process, as apparent from FIG. 4, the bottom and sidewalls of shallow trenches 20A and 20B are covered with a thin sacrificial SiO.sub.2 layer 21 having a thickness of about 22.5 nm (layer 21 will no longer be illustrated in the drawings).
Now, the shallow trenches 20A and 20B are filled with TEOS SiO.sub.2 material. To that end, a TEO.sub.2 S SiO layer 22 is conformally deposited onto the structure 10 with a thickness of about 845 nm to overfill the trench. An overfill of 175 nm is the target. This TEOS SiO.sub.2 layer 22 is generally formed by LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition) techniques using tetra ethyl ortho silicate (TEOS) and oxygen as standard. The resulting structure is shown in FIG. 5. A small depression 23A and a wide depression (or recess) 23B can be noticed above respective shallow trenches 20A and 20B. Another small depression referenced 23C is also illustrated in FIG. 5. Between depressions, the structure 10 surface presents typical mounts. At this stage of the fabrication, the structure 10 must be planarized and the initial thickness of the TEOS SiO.sub.2 layer 22 must be reduced to a given value determined by the product specifications.
The planarization basic step now takes place. In reality, it is comprised of two main processing steps: first forming a planarizing medium onto the surface of the structure 10 of FIG. 5, then planarizing the structure approximately down to the surface of the Si.sub.3 N.sub.4 pads 12 surface. In short, the main step of forming a planarizing medium will consist in the successive deposition of two photoresist layers and the planarization main step will be performed in two steps: first, an etch-back (referred to as the AB etch) of the structure which is performed in the same plasma etcher, then the resulting structure is chem-mech polished. In essence, the purpose of the AB etch is to reach the bottom of the recess 23B, while the purpose of the chem-mech polishing step is to have the final surface of the TEOS SiO.sub.2 layer 22 quite planar and at about -60 nm with respect to the Si.sub.3 N.sub.4 pads 12 surface.
Preferably, the main step of forming a planarizing medium is achieved in depositing two successive layers of photoresist. A first layer 24 (AB1) of a photoresist such as described in U.S. Pat. No. 5,273,856 assigned to IBM Corp. with a thickness of 830 nm is deposited onto the structure 10, then exposed, baked and developed as standard to leave a patterned layer referred to as AB1 mask still referenced 24. In essence, the aim of this mask 24 is to fill the wide depressions such as 23B and a determined number of small depressions such as 23A (but not 23C) as apparent from FIG. 5. This design is correlated to uniformity process problems to reduce the "silicon polish" related defects that will be discussed later on. Finally, the structure 10 is raised to a temperature sufficient (about 140.degree. C.) to cause the photoresist material of AB1 layer 24 to flow and completely fill the depressions.
Next, a second 830 nm thick layer 25 of the same photoresist material is applied over layer 24 and baked. After this second step, we can consider that the wafer surface is coarsely planar. In fact, some resist bubbles can occur and a slight relief topography does exist at locations where layers 24 and 25 are superposed. At this stage of the process, the structure 10 is shown in FIG. 7.
Now, the coarsely planarized surface of the FIG. 7 structure will be transferred to the TEOS SiO.sub.2 layer 22 to produce a thinner but substantially planar layer all over the silicon substrate 11. In reality, the AB etch step mentioned above is completed in three different sub-steps, to adjust the TEOS SiO.sub.2 layer 22 thickness whatever the pattern factor difference existing between the "array" and ".kerf/support/street" regions. The final objective is to etch the TEOS SiO.sub.2 layer 22 surface at the mount locations until the bottom of the wide depression 23B is attained. All these three sub-steps are achieved in the AME 5000 plasma etcher mentioned above, only the chemistries are different.
According to the first sub-step, the wafer is placed in the AME 5000 plasma etcher and the top resist AB2 layer 25 is etched until the surface of the TEOS SiO.sub.2 layer 22 (at mount locations) is reached. The operating conditions are:
By means of an adequate algorithm, an interferometric optical endpoint is used to detect the AB2 layer 25/TEOS SiO.sub.2 layer 22 interface. A fixed overetching is done after etch endpoint detection: about 40 nm of the TEOS SiO.sub.2 layer 22 at the mount locations and of the bottom AB1 resist layer 24 are removed during this overetch. The resulting structure is shown in FIG. 8.
Now the second etching sub-step is performed with the following operating conditions:
During this sub-step, the AB1 resist layer 24 and TEOS SiO.sub.2 layer 22 are supposed to be etched at the same rate. It is not completely true because of the pattern factor between "array" and ".kerf/support/street" regions. About 160 nm are etched for both resist layer 24 and TEOS SiO.sub.2 layer 22. At this stage of the fabrication, the structure is shown in FIG. 9. One may note the presence of small remains of the AB1 photoresist layer 24 at the location of the small depressions (e.g. 23A & 23C) and of a substantive remaining of the same at the location of the wide depression 23B. These remains will act as a mask for the subsequent processing step to be now described.
In the third and last sub-step, the TEOS SiO.sub.2 layer 22 is etched using the following operating conditions.
The resulting structure 10 at this stage of the process is shown in FIG. 10. This mixture has been selected so that during this sub-step, the TEOS SiO.sub.2 of layer 22 is etched faster than the material forming the AB1 photoresist layer 24 in order to be sure to protect the TEOS SiO.sub.2 material over the shallow isolation trenches 20A and 20B. As illustrated in FIG. 10, the etching has been conducted deeper in the "array" region 13 than desired (as mentioned above, the optimal level is the bottom of recess 23B). Due to different etch rates and anisotropic conditions, peak shaped TEOS SiO.sub.2 remains, usually called "fences", are left at the structure 10 surface. They are referenced 22' in FIG. 10.
At the end of the AB etch, the thickness of the remaining TEOS SiO.sub.2 layer 22 over Si.sub.3 N.sub.4 pads 12 is measured.
Finally, the remaining portions of the AB1 photoresist layer 24 are eliminated in a dedicated chamber of the AME 5000 plasma etcher. After photoresist stripping, the resulting structure 10 is shown in FIG. 11.
Now the step of chem-mech polishing is performed. During this step, the TEOS SiO.sub.2 layer 22 remaining over the Si.sub.3 N.sub.4 pads 12 is eliminated. The structure 10 is first chem-mech polished until the Si.sub.3 N.sub.4 pad surface is reached and the polishing is continued down to about 60 nm under Si.sub.3 N.sub.4 pads upper level. This step is achieved with commercially available polishing slurries. For example a suitable slurry is sold under commercial reference SC1 by CABOT-SPERCE, Eldorado Hills, Calif., USA. At this stage of the fabrication, the structure 10 is shown in FIG. 12.
The shallow trench formation process terminates by the steps of annealing the TEOS SiO.sub.2 layer 22 and the removal of the Si.sub.3 N.sub.4 pads 12. The anneal aims to densify the TEOS SiO.sub.2 material so that the final thickness is the thickness of the TEOS SiO.sub.2 layer 22 at the stage of FIG. 12 reduced by about 5%. At this stage of the fabrication, Si.sub.3 N.sub.4 pads 12 are quite necessary to protect the underlying monocrystalline silicon that would otherwise suffer. The Si.sub.3 N.sub.4 pads 12 stripping is performed by wet etching. As this wet process has a very high Si.sub.3 N.sub.4 /TEOS SiO.sub.2 selectivity, it is not capable to etch the Si.sub.3 N.sub.4 pads 12 in presence of a film of unpolished TEOS SiO.sub.2 material remaining thereon, even this film is very thin (e.g. 1.5 nm). Si.sub.3 N.sub.4 pads remains can be revealed only after this removal step.
The wafer road-map for the total AB etch sequence will be summarized by reference to FIG. 13. Now turning to FIG.13, there is schematically shown the AME 5000 plasma etcher referenced 26 comprised of four chambers 27A to 27D, a central load/unload module 28, a queueing station 29 coupled thereto and finally, vacuum locks that are referenced 30. FIG. 13 also shows the thickness measurement apparatus (e.g. a PROMETRIX) which bears numeral 31. Arrows illustrate the movements of the wafer within plasma etcher 26. As apparent from FIG. 13, only two reaction chambers are necessary. The three above mentioned sub-steps are conducted in chamber 27A while the remains of AB1 photoresist layer 24 are stripped in chamber 27B. The TEOS SiO.sub.2 thickness measurement is performed (above a Si.sub.3 N.sub.4 pad in the ".kerf/support/street" region) in the meantime in apparatus 31.
In the present fabrication process, the chem-mech polishing is a long and expensive processing step. Unfortunately, due to process monitoring difficulties: etch rate drifts as a function of the number of wafers to be polished, different etch rates between "array" and ".kerf/support/street" regions referred to as the "dishing effect" in the technical literature, the chem-mech polishing step is not performed in a single run but rather in two or three runs. Before the first run and between runs, all the wafers must be measured (this time, the TEOS SiO.sub.2 layer 22 thickness is measured at the center of a wide depression such as 23B) and process parameters adjusted. FIG. 14 shows the wafer road-map between the thickness measurement unit 32 (e.g. a PROMETRIX) and the chem-mech polisher 33 such as model 372M sold by WESTECH, Tempe, Ariz., USA. As known for those skilled in the art, the chem-mech polishing step has a very small process window since it is greatly dependent on all the previous processing steps, moreover it cannot heal any process variations. But, because the presence of fences 22' produced during AB etch, the chem-mech polishing step is really mandatory.
FIG. 15 illustrates the ideal structure that is sought at the end of the planarization main step described by reference to FIGS. 6 to 13. After the planarization main step, there is a "wrap-around" target of about -60 nm as clearly illustrated in the enlarged view of FIG. 15. Unfortunately, in spite of all the parameter adjustments mentioned above and outstanding cares, the wrap-around that is obtained can significantly vary between the first and the last wafer of a given lot and even between the "array" and ".kerf/support/street" regions of a same wafer.
Two types of problems appear when the above described planarization main step sequence (including the chem-mech polishing step which is a major contributor thereto) is used, they are usually referred to as "silicon polish" and "Si.sub.3 N.sub.4 pad residuals". These problems have different causes, including the thickness variations of the Si.sub.3 N.sub.4 layer 12 over the "array" and ".kerf/support/street" regions, the difficulty to properly control the chem-mech polishing step, and finally the effects due to different pattern factors.
If the chem-mech polishing is "too important", some Si.sub.3 N.sub.4 pads 12 will be completely removed and the silicon of substrate 11 is no longer protected during the anneal. As a final result, the gate oxide of IGFET's will be of poor quality. This case is illustrated in FIG. 16A where an arrow shows the exposed silicon surface. This directly results of the thickness variations in the Si.sub.3 N.sub.4 layer 12 as mentioned above.
On the contrary, if the chem-mech polishing step is "not long enough", in this case, some TEOS SiO.sub.2 material may remain over the Si.sub.3 N.sub.4 pads 12 and will act as a hard mask protecting film during the above mentioned Si.sub.3 N.sub.4 pad removal step thus preventing their complete removal. In this case, some Si.sub.3 N.sub.4 pads remain under the gate conductors (GC) as known for those skilled in the art which in turn, cause the IGFET's to be inoperative. This case is illustrated in FIG. 16B where an arrow shows an unremoved Si.sub.3 N.sub.4 pad.
In both cases, even if process adjustments made from measurements conducted in box 32 are appropriate, these defects cannot be satisfactorily corrected because chem-mech polishing is essentially a mechanical technique which cannot integrate all the possible variations or non-uniformities resulting from the previous processing steps. As a matter of fact, the process window of the chem-mech polishing step is very small and strongly depends on the product families. Zero yield at the final test can be expected for chips suffering of these defects. Finally, the above planarization step sequence does not allow the great reproducibility that is highly desired for the successful completion of processing steps to which the wafers will be subsequently submitted.

Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches

International Business Machines Corporation


An optimizing apparatus includes a data item extraction unit, a layout unit, an unused data item extraction unit, a merge determination unit, and a data item merge unit. The data item extraction unit extracts data items from a program. The layout unit lays out the extracted data item in memory. The unused data item extraction unit extracts defined but unused data items from the extracted data items. The merge determination unit determines based on the layout result whether or not a plurality of unused data items forming a data item having a hierarchical structure can be merged into a new data item. The data item merge unit merges the plurality of data items into a data item based on the determination result.

1. Field of the Invention
The present invention relates to the technology of optimizing a program, and more specifically to the technology of merging and deleting an unused data item in the program.
2. Description of the Related Art
Data items such as a variable, etc. are defined in a program in many cases. However, not all defined data items are not used in the program. In the following explanation, a data item defined but used in a program is referred to as an unused data item. Although a data item dictionary is generated during compilation, program analysis, etc., a larger memory requirement is required when unused data items are contained in the data item dictionary. Since an unused data item is not used in a program, a code for definition of the data item is not required. Therefore, a compiler is provided with the function of deleting a code for definition of an unused data item in many cases so that memory sources can be effectively used.
The function of deleting a code for definition of an unused data item is described below by referring to a compiler. In addition to the above mentioned function, an actual compiler has the functions of removing a simple assignment, optimizing a constant calculation, etc. However, for simple explanation, it is assumed that a compiler does not perform optimization other than deletion of a code for definition of an unused data item.
FIG. 1 shows an example of a source program described in COBOL (COmmon Business Oriented Language). In the source program, since the variables IREC01, IDATA11, IDATA12, IDATA13, and IDATA14 defined in lines 130 through 170 are not referred to in the procedure division in and after line 300, they are unused data items. Similarly, the variables WDATA12, WDATA13, WREC02, WDATA21, WDATA22, and WDATA71 defined in lines 210, 220, and 240 through 270 are also unused data items.
When a code for definition of an unused data item is removed by the conventional technology from the source program shown in FIG. 1, the source program shown in FIG. 2 can be obtained. In FIG. 2, the codes in lines 240 through 270 are removed.
FIG. 3 shows an example of a source program described in C. The source program shown in FIG. 3 has almost the same contents as the source program described in COBOL shown in FIG. 1. FIG. 4 shows a result of removing a record for definition of an unused data item from the source program shown in FIG. 3 by the conventional technology.
According to the compiler disclosed in the Japanese Patent Application Laid-open No. Hei 7-239788, it is determined whether or not a variable for which a data type is declared in the program has been used in the process description. If no use is determined, an error message is output to an output device, thereby notifying the user of the wasteful type declarlation in the program, and suppressing the generation of a variable for which a wasteful type declarlation is made. The compiler prevents a wasteful type declarlation from being included in a compiled program.
However, according to the above-mentioned conventional technology, the following unused data item cannot be removed to prevent the address from being shifted in the memory allotted to each data item.
data item forming at least a part of a record (a record is a data item having a hierarchical structure.)
Using the source program described in COBOL shown in FIGS. 1 and 2, the above-mentioned problems are practically described below. IREC01, IDATA11, IDATA12, IDATA13, IDATA14, WDATA12, and WDATA13 defined in the source program shown in FIG. 1 in lines 130 through 170, 210, and 220 are unused data items, but these unused data items are not removed in the source program shown in FIG. 2. Relating to the unused data item IREC01, IFILE01 is used in the SELECT statement in line 70. The unused data items IDATA11, IDATA12, IDATA13, and IDATA14 are data items configuring the IREC01. The unused data items WDATA12 and WDATA13 are data items configuring the record WREC01.
From the source program described in C shown in FIGS. 3 and 4, similar unused data items cannot be removed not only in COBOL but also in other languages.
However, the size of the memory area in a computer is limited. If unused data items in a source program which cannot be deleted are processed as is, then the process may not continue because the available memory area possibly becomes insufficient during compilation, generation of a data item dictionary, etc.
To reduce the memory requirement when a source program is compiled and a data item dictionary is generated for the source program, it is desired that the smallest possible number of unused data items are contained in the source program.

Program optimization by unused data item


The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain regions. A halo region is associated with one of the source/drain regions of the access transistor construction and no comparable halo region is associated with the other of the source/drain regions of the access transistor construction. The invention also encompasses methods of forming DRAM devices.

Dynamic random access memory (DRAM) is commonly utilized for computer memory. DRAM is incorporated into integrated circuit chips. Such chips frequently comprise a memory array of DRAM devices, and further comprise logic devices provided around a periphery of the memory array. The logic devices can be referred to as peripheral devices.
There is a continuing goal to reduce the size of memory devices and peripheral devices to conserve valuable semiconductor substrate real estate. Another continuing goal is to utilize common fabrication steps during formation of peripheral and memory device structures to reduce the processing time utilized in forming a complete integrated circuit construction.
It would be desirable to develop methods for DRAM fabrication which allow utilization of relatively small memory device structures, and it would be further desirable if such methods could utilize fabrication steps in common with the fabrication of peripheral device circuitry.


An accelerator sensor that is mounted on an engine block may be used to detect vibration of a compression ignition engine, and the detected vibration signal is analyzed to determine the combustion timing of the engine. A method for detecting combustion timing may include measuring a block vibration signal generated in a combustion process of an engine, setting up a frequency area that is to be analyzed in the block vibration to divide the frequency area into wavelet scales, executing continuous wavelet transformations of the divided wavelet scales to extract respective result values thereof and to calculate differences between former result values and latter result values, comparing the calculated difference value with a predetermined value to store crank angles of pertinent timing if the calculated difference values exceed the predetermined value, and averaging the stored crank angles to determine combustion timing in a case that all wavelet scales are processed.

1. Field of the Invention
The present invention relates to a method for detecting combustion timing of an engine that analyzes an engine vibration signal that is measured so as to determine combustion timing of an engine, and a system thereof.
2. Description of Related Art
Unlike a conventional gasoline or diesel engine, in a direct injection compression ignition type of engine such as a homogeneous charge compression ignition (HCCI) engine and a controlled auto ignition (CAI) engine, factors that are related to the combustion are restricted such that an indirect control method is used to control the combustion thereof.
An important factor in the compression ignition engine that indirectly controls combustion timing is to determine how the combustion of the engine is progressing.
As techniques that directly analyze combustion, there are a method of measuring the pressure of the combustion chamber and a method using an ion probe.
In the method measuring the pressure of the combustion chamber, the released heat amount is calculated during combustion to accurately analyze the combustion process.
The method of using an ion probe measures the ion amount that is generated before and after the combustion to analyze the combustion progress of the combustion chamber.
In the above techniques for directly measuring the combustion, the combustion is measured through data that are extracted from sensors that are mounted inside the combustion chamber such that there is a merit of accurately analyzing the combustion progress.
However, when high temperature and high pressure conditions are repeated inside the combustion chamber, in a case that the sensors are directly exposed to the combustion fire, there is a problem that sufficient durability thereof cannot be achieved, and further the sensors are expensive such that it is difficult to apply to a mass produced vehicle in a practical aspect.
The information disclosed in this Background of the Invention section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.

Method for detecting combustion timing and system thereof


A differential carrier phase GPS navigational device comprises an integer estimator 32! adapted to estimate an integer that resolves an integer cycle ambiguity, a reference phase predictor 30! adapted to predict a present reference phase value from reference phase information received by a data link receiver 22!, and a position calculator 28! for computing a present vehicle position from the estimated integer, the predicted present reference phase value, and GPS signals received at a vehicle GPS receiver 20!. The reference phase predictor 30! comprises electronic circuitry adapted to determine a polynomial function which fits the reference phase information, and to evaluate the polynomial function to determine the predicted reference phase value. Because the position calculator uses a reference phase value that is not delayed, the navigational device is able to provide a vehicle position that corresponds to the present time.

Since the advent of the global positioning system (GPS), considerable research has gone into developing techniques for improving its performance. In particular, the technique of differential GPS (DGPS) is based on the fact that many errors in GPS measurements are relatively constant over short distances and can be eliminated by taking the difference between two nearby measurements. Consequently, DGPS provides improved position accuracy. For example, FIG. 1 shows a vehicle 12 located in the vicinity of a GPS reference station 14. A GPS signal measured by the GPS reference station can be transmitted to the vehicle where it is subtracted from a GPS signal measured by the vehicle to obtain a differential GPS signal with respect to a single satellite 16. Using several similar differential GPS signals from other satellites, together with the known location of the reference station, the vehicle navigational equipment can determine the vehicle location.
Traditional DGPS systems are based on the measurement of satellite pseudorandom noise clear acquisition (C/A) code signal phases. Although this approach can provide position determinations accurate to within a few meters, some navigational applications of GPS require accuracies on the centimeter scale. In addition, the integrity of this approach is also insufficient for some applications. For example, traditional DGPS does not meet all the specifications for a Category III (zero visibility) aircraft landing system.
One technique for improving the performance of traditional DGPS systems is called kinematic DGPS, or differential carrier phase GPS. Kinematic DGPS is based on carrier phase measurements rather than C/A code phase measurements. Because the GPS signal carrier has a wavelength of about 19 cm, these measurements provide a potential accuracy on the order of a centimeter. In order to use carrier phase measurements, however, it is necessary to accurately resolve the integer cycle ambiguity of the carrier signal. In many applications it is also necessary to resolve this ambiguity quickly.
An integrity beacon landing system (IBLS) developed by researchers at Stanford University resolves integer cycle ambiguities through the use of ground-based GPS transmitters called pseudolites 18. The pseudolites, which are placed beneath the final approach path of the aircraft 12, transmit low power GPS signals which define hemispherical bubbles through which the aircraft passes. As the aircraft passes through the bubbles, the geometry of the combined satellite/pseudolite constellation changes rapidly, which allows the integer cycle ambiguities from the satellites to be resolved with high accuracy and integrity. Once the ambiguities are resolved, centimeter level accuracy can be obtained, even after the aircraft exits the integrity beacon bubbles.
Although the IBLS system succeeds in providing integer cycle ambiguity resolution with high integrity and accuracy, it does not solve other problems inherent in all differential carrier phase GPS systems. In particular, it does not overcome the differential correction latency problem, that is, the delay between the time a measurement is taken by the GPS reference station 14 and the time the corresponding correction is received at the vehicle 12. The amount of the delay is determined by the data uplink frequency and by the time required for the link signal to travel from the reference station 14 to the vehicle 12. Because the delayed reference signal must be compared to a vehicle signal which was measured at the same time, the calculated vehicle position will correspond to a past vehicle position rather than the present vehicle position. Consequently, the latency introduces undesired uncertainty in the present vehicle position.
Conventional kinematic DGPS systems either tolerate the position uncertainties introduced by differential correction latency, or use inertial integration techniques to determine the present vehicle position from the calculated past position and additional inertial data. In many automated vehicular control applications, such as Category III landing systems, the latency introduces an intolerable degradation in control performance. Inertial integration techniques, on the other hand, have the disadvantage that they introduce considerable hardware and software complexity to the navigational system.

Reference carrier phase prediction for kinematic GPS

The Board of Trustees of the Leland Stanford Junior University


Improved biological material imaging systems and related methods are provided by using an imaging system for imaging biological materials, the imaging system comprising a sensor having one or more receptors, and an image transfer medium to scale the one or more receptors to an object field of view.

Microscopes give us a large image of a tiny object. Greater magnification can be achieved if the light from an object is made to pass through two lenses compared to a simple microscope with one lens. A compound microscope has two or more converging lenses, placed in line with one another, so that both bend and refract the light in turn. The result is to produce an image that is magnified more than either lens could magnify alone. Light illuminating the object first passes through a short focal length lens or lens group, called the objective, and then travels on some distance before being passed through a longer focal length lens or lens group, called the eyepiece. A lens group is often simply referred to singularly as a lens. Usually these two lenses are held in paraxial relationship to one another, so that the axis of one lens is arranged to be in exactly the same as orientation as the axis of the second lens. It is the nature of the lenses, their properties, their relationship, and the relationship of the objective lens to the object that determines how a highly magnified image is produced in the eye of the observer.
The first lens or objective, is usually a small lens with a very small focal length. A specimen or object is placed in the path of a light source with sufficient intensity to illuminate as desired. The objective lens is then lowered until the specimen is very close to, but not quite at the focal point of the lens. Light leaving the specimen and passing through the objective lens produces a real, inverted and magnified image behind the lens, in the microscope at a point generally referred to as the intermediate image plane. The second lens or eyepiece, has a longer focal length and is placed in the microscope so that the image produced by the objective lens falls closer to the eyepiece than one focal length (that is, inside the focal point of the lens). The image from the objective lens now becomes the object for the eyepiece lens. As this object is inside one focal length, the second lens bends the light in such a way as to produce a second image that is virtual, inverted and magnified. This is the final image seen by the eye of the observer.
Alternatively, common infinity space or infinity corrected design microscopes employ objective lenses with infinite conjugate properties such that the light leaving the objective is not focused, but is a flux of parallel rays which move and do not converge until after passing through a tube lens where the projected image is then located at the focal point of the eyepiece for magnification and observation. Compound microscopes such as described herein are commonly employed to view biological material.
Many microscopes, such as the compound microscope described above, are designed to provide images of certain quality to the human eye through an eyepiece. Connecting a Machine Vision Sensor, such as a Charge Coupled Device (CCD) sensor, to the microscope so that an image may be viewed on a monitor presents difficulties. This is because the image quality provided by the sensor and viewed by a human eye decreases, as compared to an image viewed by a human eye directly through an eyepiece. As a result, conventional optical systems for examining biological material often require the careful attention of a technician monitoring the process through an eyepiece. Real time images via a monitor are of poor quality.
While a scanning electron microscope can provide highly magnified images of biological material, there are several limitations associated with scanning electron microscope images. For example, it is difficult to impossible to provide real time images of a biological material. Scanning electron microscopy is typically a destructive technique, preventing further use of the imaged sample. A scanning electron microscope is a large apparatus requiring dedicated facilities, and is not portable.

Imaging system for examining biological material