An in-FPGA carry chain is provided that does not exhibit significant leakage current. In particular, parts of the carry chain can be switched on/off when desired. In this manner, carry chain parts can have their leakage currents substantially disabled when they are not in use, thus saving power. Additionally, there is provided a carry chain whose logic is separate from the other parts (e.g., LUTs) of the logic blocks that perform the remaining arithmetic functions, and whose inputs are the input data to be added, rather than data that is output in delayed fashion from the other parts (e.g., LUTs) of the logic blocks. Such a configuration reduces latency by allowing the carry chain to operate directly on the received input data without need to wait on results from the other parts (e.g., LUTs) of the logic blocks.

The rise in popularity of portable electronic devices has led to a corresponding increase in demand for low-power FPGAs. For instance, it is increasingly desirable for hand-held devices to utilize low-power FPGA controllers that do not detract from long battery life. Ongoing efforts therefore exist to develop and refine FPGAs that consume less power, and are thus more compatible with portable and hand-held applications. Such ongoing efforts may include those that heretofore were not publically known and thus, it is to be understood that this Background section may include concepts and teachings that are not part of the prior art.
Concurrently, performance demands on such portable electronic devices continue to increase. Therefore, FPGAs used in these devices should desirably be structured to not only consume less power, but also to exhibit higher performance (e.g., high switching speeds). Accordingly, the ongoing efforts that currently exist include efforts to develop low-power FPGAs that also exhibit higher performance.
One heretofore and generally overlooked area in the ongoing efforts is FPGA carry chains, e.g., the logic used for generating and moving carry bits between successive stages during addition/subtraction operations. In particular, conventional FPGA carry chains typically consume excessive power and/or perform relatively slowly. As one example, FIG. 1 illustrates a plurality of FPGA Configurable Logic Blocks (CLBs) configured and interconnected for implementing a conventional ripple carry adder. Each configurable logic block 10 (e.g., CLB 100) receives two addend input bits (e.g., I0, I1), along with a corresponding carry bit, e.g., C0 from a previous stage and the respective CLB (10k) is configured to produce a respective sum bit Sk (k=0, 1, 2, etc.). Thus, the bottom logic block 100 of FIG. 1 adds corresponding input bits I0(0), I1(0), along with corresponding carry bit C0, to produce the respective sum bit S0 and the output carry bit C1, where the output carry bit is a 0 or 1 depending on the result of the addition of I0(0), I1(0) and C0. The output carry bit C1 is then transmitted to the next configurable logic block 10 (e.g., CLB 101), where it is used in calculating the next sum bit S1, and so on. It can be observed that, due to the ripple up way in which signals are generated and forwarded to the next successive stage, the dependency of the more significant stages (e.g., CLB 103) on receiving valid (e.g., settled) results from carry operations of the less significant stages (e.g., CLB 100) in this ripple carry adder contributes to latency and delay given that each previous carry bit must settle into a correct state before the next addition operation can commence in the next more significant stage. That is, each logic block 10(k) must wait for the carry output bit from the previous logic block 10(k−1) to be fully determined (e.g., well settled into a deterministic state). This delay is detrimental to the performance of FPGAs that employ such ripple carry adders. Furthermore, such, inside-the-CLB and ripple-based carry logic generally exhibits detrimental leakage current, leading to power drain even when a carry operation is not being actively performed inside the CLB.
As another example of conventional design, FIG. 2 illustrates an FPGA where its configurable logic blocks (e.g., CLBs 200-203, 30) are programmed to implement a conventional carry look-ahead adder. Each logic block 20 adds together its correspondingly received inputs I0(k), I1(k) together, along with its received carry bit C(k), and outputs the respective sum bit S(k). The logic blocks 20 also output respective propagate and generate signals PG(k) to a carry look-ahead block 30, where the state of PG(k) is based on whether a carry is to be further propagated from a less significant stage or a carry is to be generated at that stage (CLB 20k). The carry look-ahead block 30 determines from the PG signals whether a carry is to be propagated to the next block, and sends carry signal C(k) accordingly to stages 201-204, (last stage not shown). However, while the carry look-ahead adder helps reduce the problem of latency, the carry look-ahead block 30 still requires some time to process the PG signals and to generate the correct set of carry signals C for generating a correct final sum signal, S0:Sn. Additionally, the carry look-ahead adder, like the ripple carry logic, typically exhibits a leakage current even when unused for performing addition operations.


A dry-type transformer heater includes a closed housing, and at least one transformer winding arranged in the housing. The at least one transformer winding includes at least one corresponding winding conductor and a corresponding insulation layer surrounding the transformer winding, respectively. In addition to the respective winding conductor, at least one coil heating wire is provided in at least one of the insulation layer and on the surface of the insulation layer to input thermal power into the respective insulation layer.

It is generally known that dry-type transformers are used in power distribution systems to adapt the voltage levels of different system components. These have a power range of, for example, 100 kVA to some 10 MVA and are provided for rated voltages between, for example, a few kV to 110 kV. In contrast to oil-filled transformers, a liquid insulation medium is dispensed with here; rather, for example, the windings are surrounded by a solid insulation material, such as a fiber roving which is impregnated with resin and subsequently cured. In the case of a three-phase transformer, three windings of this type are then arranged around each limb of a transformer core. To dissipate the heat loss which occurs during operation, cooling ducts through the windings are necessary, for example, to a greater extent in the case of a hot working environment.
For certain applications, it is necessary to encapsulate dry-type transformers, to arrange them inside a closed housing. This can be the case, for example, for dry-type transformers which are arranged inside a very cold working environment or else on a ship or an oil-drilling platform and against the effects of salt-containing sea water. However, an encapsulation can occasionally be necessary merely because of the mechanical protective effect thereof. For example, in the event that an encapsulated transformer is subjected to frequent shutdowns depending on use, condensation can form inside the transformer housing since the transformer then cools down owing to the lack of heating effect of the winding losses. Even during permanent operation of an encapsulated transformer, condensation can be formed if the transformer is positioned in such a cold working environment that the winding losses do not lead to sufficient heating of the transformer or the housing thereof, with the result that the dew-point temperature is not exceeded. In this case, in the event of relatively long shutdowns, condensation collects on the interior surface of the housing or also on the surface of the windings.
In order to avoid condensation appearing inside a transformer housing, it is therefore usual, depending on requirements, to integrate space heaters in the housing, for example radiators. The radiators are often arranged, owing to a simplified arrangement, on either side of the transformer core on the base of the housing and have a heating region which is directed upward. As a result of this, the regions on either side of the transformer core are heated and the formation of condensation is avoided there. However, the transformer windings and the housing region thereabove are not directly covered by the heating region and so condensation can form there which can drip in a disadvantageous manner, for example from the upper housing region, onto the transformer windings located below.


The present invention provides, in one embodiment, a system and method for concealing video errors. The system encodes, reorders, and packetizes video information into video data packets for transmission over a communication network such that the system conceals errors caused by lost video data packets when the system receives, depacketizes, orders, and decodes the data packets. In one embodiment, the system and method encodes and packetizes video information, such that adjacent macroblocks are not placed in the same video data packets. Additionally, the system and method may provide information accompanying the video data packets to facilitate the decoding process. An advantage to such a scheme is that errors due to video data packet loss are spatially distributed over a video frame. Thus, if regions of data surrounding a lost macroblock are successfully decoded, the decoder may predict motion vectors and spatial content with a higher degree of accuracy, which leads to higher video quality.

1. Field of the Invention
This present invention relates generally to video communication, and more particularly to video error concealment.
2. Description of Related Art
Video images have become an increasingly important part of global communication. In particular, video conferencing and video telephony have a wide range of applications such as desktop and room-based conferencing, video over the Internet and over telephone lines, surveillance and monitoring, telemedicine, and computer-based training and education. In each of these applications, video and accompanying audio information is transmitted across telecommunication links, including telephone lines, ISDN, DSL, and radio frequencies.
A standard video format used in video conferencing is Common Intermediate Format (CIF), which is part of the International Telecommunications Union (ITU) H.261 videoconferencing standard. The primary CIF format is also known as Full CIF or FCIF. Additional formats with resolutions higher and lower than FCIF have also been established. FIG. 1 is a table of the resolution and bit rate requirements for various video formats under the assumption that 12 bits are required to represent one pixel, according to the prior art The bit rates (in megabits per second, Mbps) shown are for uncompressed color frames.
Presently, efficient transmission and reception of video signals may require encoding and compression of video and accompanying audio data. Video compression coding is a method of encoding digital video data such that it requires less memory to store the video data and reduces required transmission bandwidth. Certain compression/decompression (CODEC) schemes are frequently used to compress video frames to reduce required transmission bit rates. Thus, CODEC hardware and software allow digital video data to be compressed into a smaller binary format than required by the original (i.e., uncompressed) digital video format.
Several conventional approaches and standards to encoding and compressing source video signals exist. Some standards are designed for a particular application such as JPEG (Joint Photographic Experts Group) for still images, and H.261, H.263, MPEG (Moving Pictures Experts Group), MPEG-2 and MPEG-4 for moving images. These coding standards, typically, use block-based motion-compensated prediction on 16×16 pixels, commonly referred to as macroblocks. A macroblock is a unit of information containing four 8×8 blocks of luminance data and two corresponding 8×8 blocks of chrominance data in accordance with a 4:2:0 sampling structure, where the chrominance data is subsampled 2:1 in both vertical and horizontal directions.
As a practicality, audio data also must be compressed, transmitted, and synchronized along with the video data. Synchronization, multiplexing, and protocol issues are covered by standards such as H.320 (ISDN-based video conferencing), H.324 (POTS-based video telephony), and H.323 (LAN or IP-based video conferencing). H.263 (or its predecessor, H.261) provides the video coding part of these standards groups.
A motion estimation and compensation scheme is one conventional method typically used for reducing transmission bandwidth requirements for a video signal. Because the macroblock is the basic data unit, the motion estimation and compensation scheme may compare a given macroblock in a current video frame with the given macroblock's surrounding area in a previously transmitted video frame, and attempt to find a close data match. Typically, a closely matched macroblock in the previously transmitted video frame is spatially offset from the given macroblock by less than a width of the given macroblock. If a close data match is found, the scheme subtracts the given macroblock in the current video frame from the closely matched, offset macroblock in the previously transmitted video frame so that only a difference (i.e., residual) and the spatial offset needs to be encoded and transmitted. The spatial offset is commonly referred to as a motion vector. If the motion estimation and compensation process is efficient, the remaining residual macroblock should contain only an amount of information necessary to describe data associated with pixels that change from the previous video frame to the current video frame and a motion vector. Thus, areas of a video frame that do not change (e.g., the background) are not encoded and transmitted.
Conventionally, the H.263 standard specifies that the motion vectors used for motion estimation and motion compensation be differentially encoded. Although differential encoding reduces data amounts required for transmission, any error in which motion vector data is lost or corrupted for one macroblock negatively impacts adjacent macroblocks. The result is a propagation of error due to the corrupted data which leads to lower video quality.
When preparing video frame information for transmission over a packet switched communication network, encoding schemes transform the video frame information, compressed by motion estimation and compensation techniques, into data packets for transmission across a communication network. Although data packets allow for greater transmission efficiency, lost, corrupted, or delayed data packets can also introduce errors resulting in video quality degradation. Alternatively, video data may be transmitted on heterogeneous communications networks in which one of the endpoints is associated with a circuit-switched network and a gateway or other packet-switched to circuit switched network bridging device is used.
Currently, lost or corrupted data packets often cause reduced video quality. Therefore, there is a need for a system and method which organizes and transmits data packets in order to conceal errors caused by data packet loss.

System and method for video error concealment


Disclosed are a sensor interface device and an amplifier used in a sensor system. The sensor interface device in one implementation has a first chopper configured to shift input signals of the sensor system from a baseband frequency to a first frequency, an instrumentation amplifier configured to amplify the shifted signals, a bandpass Delta-Sigma modulator configured to digitize the amplified signals, and a second chopper configured to shift the digitized signals from the a first frequency back to the baseband frequency. The instrumentation amplifier removes the DC offset generated from the first chopper and therefore all sources of DC offset are eliminated in this interface device without bandwidth limitation.

Sensor systems are widely used in the fields of industrial and medical electronics, wherein a sensor interface device is essential to establish a link between a sensor of a sensor system and the rest components of the same.
The sensor systems, to which the invention relates, have two common characteristics. Firstly, the output signal of a sensor in the sensor systems is a voltage quantity and has very small amplitude. For example, a bridge gauge sensor often generates a peak differential voltage in the order of a few tens mini-volt and the electroencephalogram signal has a magnitude less than 1 μV. Secondly, the output signal has a low bandwidth, or at most, a medium bandwidth. For example, a 10 Hz bandwidth is sufficient in strain gauge stress sensors. In bio-potential acquisitions, most input signals have a bandwidth less than 1 kHz.
Key requirements of these sensors are low DC-offset and low flicker noise because these errors are indistinguishable from the signals of interest. Over the years, various techniques have been developed in this regard, including auto-zero (also known as correlated double sampling, CDS) and chopper techniques.
The chopper technique is now widely used in various applications. In this technique, an input signal is firstly modulated to a higher frequency by chopping it at a high frequency so that a desired signal can be distinguished from the low frequency offset and flicker noise. Then, the modulated signal is amplified by an amplifier and the amplified signal is chopped again at the same chopping frequency. The desired signal is modulated back to a baseband, while the offset and the flicker noise are shifted to a high frequency and can be removed by lowpass filtering, which can be implemented by the amplifier itself.
A problem with the conventional chopper technique is that the choppers themselves generate offset errors that are indistinguishable from the desired signal. The chopper-induced errors are often proportional to the chopping frequency. However, the frequency range of the flicker noise posts a limit on lowering the chopper frequency.
An improved technique called nested chopper technique uses a pair of inner choppers operating at a high frequency to reduce the flicker noise, and a pair of outer choppers operating at a low frequency to suppress the DC-offset generated by the inner choppers. A drawback of the nested chopper technique is that, since the outer choppers operate at a very low frequency, the input signal bandwidth is limited.


A camera stabilizer having a base with an aperture in front and in back, and in alignment with one other. A shoulder support, removably attachable to the base, has an adjustable rod extending forward of it with a detent at its distal end. The adjustable rod inserts into the base through its two apertures with the detent passing through the front aperture to prevent rearward movement of the adjustable rod. A second support removably attaches to the base. It has two telescoping rods connected to each other at their bottoms from which they are pivotable. Adjustable straps on one telescoping rod are adapted to wrap around one's back and fasten to themselves for greater stability. Another strap at the bottom of one telescoping rod is adapted to loop around one's belt and fasten to itself thereby providing addition stability and vertical support.

This present invention relates to an improvement in camera supports and more particularly to camera stabilizers.
A steady camera for still pictures or moving pictures [movie camera or video camera] makes for better more professional finished pictures. A camera for still pictures, because of its shutter speed, can be hand-held and still be capable of capturing a good quality picture. For more professional results, tripods are generally used.
Holding a moving camera or video camera by hand to capture moving pictures can typically yield a 'jittery' result [for the purpose of all further discussion, such moving pictures will be referred to herein as 'video' and the device as 'video camera' and includes all types of cameras capable of capturing and presenting moving pictures—it must be understood, however, that the camera stabilizer of the present invention may be used with all types of cameras; still, moving, 35 mm, digital, and the like]. Tripods can be used but, once set up, their use is limited in scope in that once the tripod is set on the ground, it generally stays put and the camera operator swivels the mounted camera up and down and back and forth as needed. Should an event require the camera operator to move about to better capture the moments, the end result of the video will be jittery.
Various, more portable and mobile, camera supports and stabilizers have been crafted to meet the needs of the video camera operator to minimize or completely eliminate the jitter effect when recording moving events and moving with the event to better capture it. Most typically involve some form of adjustable rod attachable to the video camera with some form of support structures mountable onto a camera operator. In many different forms, these generally involve some form of telescoping rod from video camera to the operator at or near the operator's shoulder with another telescoping rod from video camera to the operator at or near the operator's waist or chest thereby forming a triangular support structure well-suited for stabilizing the video camera.
All the prior art camera support devices are either complicated in structure and use; costly to manufacture and, concomitantly, costly to buy; and, in spite of the complexities of the device and high cost, do not offer flexibility of use nor do they provide for greater versatility in use. Most merely support the video camera without according the user more features necessary to produce more professional results. My co-pending application referenced above fills that void. This continuation-in-part present invention enhances upon my previously filed application.
Accordingly, several objects and advantages of my invention are to:
a. provide an advantage for near- and far-sighted users to permit either to easily use either an LCD monitor for viewing or the viewfinder of the video camera;
b. produce an inexpensive camera stabilizer which provides excellent vertical and horizontal support for a video camera;
c. provide additional support between operator and camera by stabilization means around the operator's back and upward in a bi-pod [also referred to as V-pod] configuration from a user's waist to the camera;
d. provide a camera stabilizer which may easily function as a mono-pod support for a camera, a bi-pod support for a camera, and accommodate an external tri-pod;
e. introduce a camera stabilizer which easily assembles and dis-assembles;
f. provide for a camera stabilizer which is easily adjustable and extremely easy to use;
g. provide a camera stabilizer which facilitates the use of remote control devices and other camera-related components;
h. create a camera stabilizer which assists the camera operator in registering a level plane; and
i. make an easily portable and storable camera stabilizer capable of easy storage and movement from one site to another site.
The foregoing has outlined some of the more pertinent objects of the present invention. These objects should be construed to be merely illustrative of some of the more prominent features and applications of the intended invention. Many other beneficial results can be attained by applying the disclosed invention in a different manner or by modifying the invention within the scope of the disclosure. Accordingly, other objects and a fuller understanding of the invention may be had by referring to the summary of the invention and the detailed description of the preferred embodiment in addition to the scope of the invention defined by the claims taken in conjunction with the accompanying drawings.


A method for configuring resources in IA-32 computers enables the PCI memory address range to be reclaimed with minimal loss of available physical memory. The BIOS establishes a remap window at the top of physical memory. The remap window corresponds to the PCI memory address range. The BIOS reports to the operating system that a portion of the remap window is reserved. The reserved portion corresponds to the AGP aperture within the PCI memory address range. The BIOS reports the remaining regions of the remap window as usable memory. All of the PCI memory range except the AGP aperture is thereby successfully reclaimed for general use.

Memory-Mapped IO. IA-32 processors permit applications to access input/output ("IO") ports in either of two ways: through a separate IO address space or through the physical memory address space. The latter approach is commonly referred to as "memory-mapped IO."
Address Space, Chipsets, and the BIOS. Beginning with the introduction of the Pentium Pro, IA-32 processors provide a 36-bit address bus. This enables them to support up to 64 GB of physical memory. Accesses to this address space by the CPU and other devices within a computer are generally handled by several chips commonly known as the "chipset." A chipset provides bus interface, data path, instruction caching and similar functions on the motherboard. System firmware known as the basic input/output system ("BIOS") must configure the chipset at boot time with various information, including information about where main memory is located within the address space.
Chipset Configuration and the AGP Aperture. As a practical matter, the capabilities and requirements of the chipset dictate in large part where main memory can be located. The Intel E7505 chipset, for example, is designed to assume that certain devices will always be mapped into the peripheral component interconnect ("PCI") memory address range—that is, the address range beginning at 4 GB and extending downward far enough to include certain address regions. Specifically, it assumes that the advanced programmable interrupt controller ("APIC") addresses, the hub interface addresses, and any memory-mapped IO addresses will reside in this range. Another range of addresses the chipset assumes to exist in the PCI range is the accelerated graphics port ("AGP") aperture. By way of background, the operating system allocates numerous 4 KB pages in main memory for use by the graphics controller. These allocated pages are normally discontiguous; but the graphics controller needs contiguous memory. So, a translation mechanism is used to create a series of contiguous logical addresses (the AGP aperture) within the PCI address range. These addresses map to the discontiguous pages that are allocated in main memory, wherever those might be.
By way of further background, configuration of the Intel E7505 and similar chipsets requires among other things that the BIOS write appropriate values into the top of lower memory ("TOLM") register and into the DRAM row boundary 7 ("DRB7") register. The TOLM register is designed to contain the maximum address below 4 GB that should be treated as main memory. The DRB7 register is designed to contain the maximum address in the machine that should be treated as main memory. Thus, for machines having less physical memory than 4 GB minus the minimum size required for the PCI memory address range, the TOLM and DRB7 registers will contain the same value. But for machines having more memory than that, the physical memory must be split because the PCI memory address range may not be moved. In such machines, there will be one region of physical memory located below the PCI range, and another region of physical memory located above the PCI range. The TOLM register will indicate the highest address within the first range. The DRB7 register will indicate the highest address within the second range.
Memory Reclaiming. In previous generation chipsets, any physical memory that was overlapped by the logical address space allocated to the PCI range was unusable. But in some workstations, the amount of memory allocated to memory-mapped IO devices could easily exceed 1 GB. An unacceptably large amount of physical memory was rendered unusable in such machines.
Now, chipsets such as the E7505 attempt to provide a capability for "reclaiming" physical memory that is overlapped by the PCI range. In theory, this is done by remapping the physical memory lying within the PCI range to an equivalent-sized logical address range located just above the top of physical memory. During chipset configuration, the bottom and top of a remapped window are defined by values written by the BIOS into a REMAPBASE register and a REMAPLIMIT register, respectively. During normal operation, each incoming logical address is checked to determine whether it falls in the remapped window. If so, then the incoming logical address is remapped to the physical memory starting at the address defined by the TOLM register.
The AGP Aperture Bug. Unfortunately, the memory reclaiming feature of the current E7505 chipset operates erroneously: When a device writes to an address within the remapped window, the write is executed correctly. But when a device reads from an address within the remapped window, the E7505 chipset sometimes returns data from reclaimed physical memory, and other times returns data from a corresponding address within the AGP aperture! Moreover, no warning is given to the consumer of this memory when the error occurs.
The straightforward approach to addressing this problem would be to avoid using the memory reclaiming feature of the E7505 chipset altogether. This approach would ensure that no memory accesses could result in errors. The downside of the straightforward approach, however, is that it results in losing a large range of addresses as unusable memory—a range equal in size to the entire PCI memory address range. As was mentioned above, this range can exceed 1 GB in some workstations.

Reclaiming the PCI memory range with minimal memory loss in IA-32 platforms

Hewlett-Packard Development Company, L.P.


An installation tool for vacuum cleaners having a rotary brush and a motor drive shaft in which a tensioned belt is used between the brush and the motor shaft. The tool has a straight shaft portion with a handle at a proximal end and a hook at a distal end. A carrier portion is formed between the straight shaft portion and the hook to capture a loop of the elastic belt. The hook is located in a belt groove on the motor drive shaft while the belt inserted in the tool. The handle is then raised and rotated to move the belt over the hook and into the belt groove.

Many household vacuum cleaners have a rotary brush driven by an electric motor through an 0-ring type belt encircling the brush and received on a pulley connected to the drive shaft of the motor. Manufacturers of vacuum cleaners often recommend changing the belts twice a year. The elastic belt is under considerable tension and it is difficult for the average person to install the elastic belt on the shaft. The difficulty in installing a new belt often necessitates seeking a professional repair service at great inconvenience and expense to the user.
Various tools are known, mainly in the automotive field, for applying a drive belt to a pulley. One such tool is disclosed in U.S. Pat. No. 2,505,216 which describes a tool for installing a fan belt to drive a cooling fan of an automobile engine. The tool has a shoulder to engage a flange of a pulley as the belt rests on the head of the tool. The tool is then moved along the edge of the flange until the belt slips into the pulley groove.
Another tool is disclosed in U.S. Pat. No. 2,621,529 which describes a tool for removing and applying fan belts for automobiles. The tool has a long limb to be seated in the groove of the pulley as the belt rests on the short limb. The tool is then rocked and manipulated step by step to stretch the belt onto the pulley.
However, these prior devices are not adapted for safely applying a drive belt to a vacuum cleaner because neither tool can securely remain in the belt groove of a vacuum cleaner drive shaft while applying the belt resulting in possible injury to the user's fingers.


An electronic assistant handles instant messages sent to a user when the user is away or offline. The electronic assistant may respond intelligently and helpfully to inquiries regarding the user's away or offline status, may take messages for delivery to the away or offline user, and may intelligently forward messages to the user, as appropriate.

With the advent of the Internet and a decline in computer prices, many people are communicating with one another through computers interconnected by networks. A number of different communications programs have been developed to facilitate such communications between computer users. Instant messaging (IM) programs are one type of communication program. IM programs typically have a user interface that presents representations of user selected buddies (i.e., other users of the IM program that have been selected by the user). When a buddy's instant messaging program is connected to the network and the buddy is available, a user may manipulate the user interface to initiate instant messaging communications with the buddy. For example, the user may use the IM program to engage in a real-time textual messaging session with the buddy identified using the instant messaging user interface.
At times, a user may be away from his or her computer or otherwise unavailable to engage in communications with a buddy, even though his or her instant messaging program is connected to the network or otherwise available for communications. In such a situation, a user typically is considered to be "away." Traditionally, some IM client programs have allowed users to configure preset "away messages" that are sent as textual messages to buddies that attempt to communicate with the user while the user is away. When a buddy sends an instant message to the away user, the user's instant messaging program responds with the preset message, thereby alerting the buddy that the user is away. The instant message sent to the away user may be displayed on the client system running the instant message program so that the away user may view the message when the user returns to that client system.
A user also may be unavailable because his or her instant messaging program is not connected to the network. In such a situation, a user typically is considered to be "offline." While some instant messaging programs provide no way of sending messages to a buddy in this situation, others (e.g., ICQ) allow messages to an offline buddy to be stored at a server and delivered to the user when he or she later comes online (i.e., when he or she connects the IM client program to the network).

Intelligent processing in the context of away and offline instant messages


A semiconductor device and a method of producing the semiconductor device, fabricated by forming a memory device and a logic device on a single semiconductor substrate, are provided. A side wall (9) and a silicide protection film (10) of a gate electrode (7e) are used instead of forming a silicide protection film in a logic device region (101), whereby the number of steps in forming a logic process consolidating device can be reduced. Further, high concentration impurity regions are formed using the silicide protection film (10) as a mask, whereby a degree of freedom of a condition of implanting ions becomes high. In a memory device region (100), because the silicide protection film does not remain, an opening (17) can be formed in a self-replicating manner without deteriorating reliability of the semiconductor device, whereby it is possible to realize a preferable electrical connection between a source/drain area of the semiconductor device to a wiring layer in a self-alignment contact opening of the memory device region (100).

1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same, in particular to, a semiconductor device having a semiconductor substrate, on which both of a memory device and a logic device are formed, hereinbelow referred to as a logic process consolidating device, and a method of producing the semiconductor device.
2. Discussion of Background
In recent years, it is required that semiconductor devices are formed to be a single chip in response to an age of multimedia. For example, a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory, and a logic device are formed on a single semiconductor substrate and mounted on a single chip.
FIG. 24 is a cross-sectional view illustrating a structure of a conventional logic process consolidating DRAM. In FIG. 24, numerical reference 100 designates a memory device region; and numerical reference 101 designates a logic device region. Hereinbelow, the structure of the conventional logic process consolidating DRAM will be described in reference of FIG. 24.
A cross-sectional structure of the memory device region of the conventional logic process consolidation DRAM will be described. In the memory device region, an active region formed by a bottom n-well 52 and a p-well region 53a formed on a bottom n-well 52 is located on a silicon substrate 51. On a principle surface of the silicon substrate 51, an isolating region 54 and a gate oxide film 55 are formed. On the p-well region 53a surrounded by the isolating region 54 has source/drain areas 56a, 56b.
On the gate oxide film 55 and an isolating oxide film 54, gate electrodes 57a through 57c are formed with a predetermined interval. On upper surfaces of the gate electrodes 57a through 57c, for example, an insulating film 58 made of a silicon nitride film or a TEOS oxide film is formed. Further, a silicon oxide film 59 is formed on the insulating film 58, the source/drain areas 56a, 56b, and the isolating region 54 so as to cover these. A silicon nitride film 60 is formed so as to cover an upper surface of the silicon oxide film 59. Further, an inter-layer insulating film 67 is formed to cover the silicon nitride film 60.
Above the source/drain area 56b, the inter-layer insulating film 67, the silicon nitride film 60, the silicon oxide film 59, a part of the insulating film 58 formed on the gate electrodes 57b and 57c, and a self-alignment contact opening 69 for exposing the gate oxide film 55 are formed. The self-alignment contact opening 69 is formed to expose a surface of the source/drain area 56b.
A plug made of a conductive material and so on is formed in the self-alignment contact opening 69. Such a plug is used as a contact for, for example, a storage node contact of a bit wire or a capacitor cell. After forming the plug, a lower electrode (not shown) of a bit wire or a capacitor is formed. The lower electrode of a bit wire or the capacitor is electrically connected to the source/drain area 56b through the plug.
Meanwhile, in the logic device region, the isolating region 54 is formed on a principle surface of the silicon substrate 51. Further, on the active region surrounded by the isolating region 54, the n-well region 53b and the p-well region 53c are respectively formed. In the n-well region 53b, low concentration impurity regions 56c, 56d and high concentration impurity regions 62c, 62d are formed, whereby source/drain regions 70c, 70d having a lightly doped drain (LDD) structure are configurated.
Further, in the p-well region 53c of the silicon substrate 51, low concentration impurity regions 56e, 56f and high concentration impurity regions 62a, 62b are formed, whereby source/drain areas 70a, 70b having a LDD structure are configurated. On a channel region between source/drain areas 70c and 70d, a gate electrode 57d is formed through a gate oxide film 55. Further, in the p-well region 53c, a gate electrode 57e is formed through the gate oxide film 55.
The insulating film 58 made of a silicon nitride film or a TEOS oxide film is formed respectively on upper surfaces of the gate electrodes 57d and 57e. A side wall made of the silicon oxide film 59 and the silicon nitride film 60 is formed so as to be in contact with side surfaces of the gate electrode 57d and the insulating film 58. In a similar manner, a side wall made of the silicon oxide film 59 and the silicon nitride film 60 is formed so as to be in contact with side surfaces of the gate electrode 57e and the insulating film 58.
A silicide protection film 64 is formed to cover parts respectively of the insulating film 58 formed on the upper surface of the gate electrode 57d, a surface of the side wall, and the source/drain areas 62c, 62d. On the source/drain areas 70a through 70d without the silicide protection film 64, a high-melting metallic silicide film 66 made of, for example, a cobalt silicide film, a titanium silicide film, and so on is formed. The inter-layer insulating film 67 is formed above an entire surface of the semiconductor substrate 51.
In the conventional logic process consolidating device, a conduction type of the active region and a conduction type of the impurities to be implanted are not limited to those described above, and adverse conduction types may be used.
In the next, in reference of FIGS. 13 through 24, a method of producing the conventional logic process consolidating device will be described. In FIG. 13, the isolating region 54 is formed on the principle surface of the silicon substrate 51, in which the bottom n-well 52, the p-well region 53a, the n-well region 53b and the p-well region 53c are formed. A structure of isolating of the isolating region 54 is obtained by opening a deep groove in the silicon substrate 51, and embedding an insulating film such as an oxide film in use of a Shallow Trench Isolation (STI) process, whereby the structure of isolation becomes flat.
The gate oxide film 55 is formed on the principle surface of the silicon substrate 51. In a predetermined area on the gate oxide film 55 or the isolating oxide film 54, the gate electrodes 57a through 57e are formed. An n-type impurity is implanted in the p-well regions 53a, 53c in the silicon substrate 51 by ion implantation. A p-type impurity is implanted in the n-well 53b in the silicon substrate 51 by ion implantation. Thus, the source/drain areas 56a, 56b and the low concentration impurity regions 56c through 56f are formed. As illustrated in FIG. 14, the silicon oxide film 59 is formed above the entire surface of the silicon substrate 51 so as to cover the gate electrodes 57a through 57e and the insulating film 58 formed thereon. The silicon nitride film 60 is formed on the silicon oxide film 59. As illustrated in FIG. 15, a resist 61 is coated, and an n-type transistor area in the logic device region is opened by photoengraving.
In the next, the silicon oxide film 59 and the silicon nitride film 60 are subjected to anisotropic etching to form side walls on both sides of the gate electrode 57e. An n-type impurity is further implanted in a self-replicating manner using the side walls and so on as a mask to form the high concentration impurity regions 62a, 62b. The source/drain area 70a having the LDD structure is configurated by the low concentration impurity region 56e and the high concentration impurity region 62a. Further, the source/drain area 70b having the LDD structure is configurated by the low concentration impurity region 56f and the high concentration impurity region 62b.
As illustrated in FIG. 16, the resist 63 is coated, and the p-type transistor region in the logic device region is opened by photoengraving. Succeedingly, the silicon oxide film 59 and the silicon nitride film 60 are subjected to anisotropic etching to form side walls on both sides of the gate electrode 57d. A p-type impurity is further implanted in a self-replicating manner using the side walls and so on as a mask to form the high concentration impurity regions 62c, 62d. The source/drain area 70c having the LDD structure is configurated by the low concentration impurity region 56c and the high concentration impurity region 62c. The source/drain area 70d having the LDD structure is configurated by the low concentration impurity region 56d and the high concentration impurity region 62d.
After removing the resist 63, a silicon oxide film 64 is formed above an entire surface of the silicon substrate 51 to be served as a silicide protection film in the logic device as illustrated in FIG. 17. In the next, a resist is coated, and a resist pattern 65 is formed by photoengraving as illustrated in FIG. 18. Further, the silicon oxide film 64 is subjected to anisotropic etching using the resist pattern 65 as a mask, whereby the resist pattern 65 is removed as illustrated in FIG. 19. As illustrated in FIG. 20, the high melting point metal silicide film 66 is formed on surfaces of the source/drain areas 70a through 70d externally exposed.
As illustrated in FIG. 21, the inter-layer insulating film 67 is formed above the entire surface of the silicon substrate 51. As illustrated in FIG. 22, a resist 68 is coated, and the resist above the source/drain area 56b in the memory device region is patterned by photoengraving. As illustrated in FIG. 23, the inter-layer insulating film 67 is subjected to anisotropic etching using the resist 68 as a mask and using the silicon nitride film 60 as an etching stopper.
Then, the resist 68 is removed. As illustrated in FIG. 24, the silicon nitride film 60, the silicon oxide film 59, and the insulating film 58 are subjected to anisotropic etching in a self-replicating manner to expose the source/drain area 56b. Thus, the self-alignment contact opening 69 is formed.
FIGS. 25 through 30 are cross-sectional views for illustrating a structure of the conventional logic process consolidating device, wherein problems in steps after the step illustrated in FIG. 18 are explained. Processes of the method of producing the device will be briefly described in reference of FIGS. 25 through 30. As illustrated in FIG. 18, in the conventional logic process consolidating device, a silicide protection film 64 is formed even in a memory device region, in which the silicide protection film 64 is unnecessary. As illustrated in FIG. 25, the silicide protection film 64 is etched using a resist pattern 65 as a mask. As illustrated in FIG. 26, a high-melting metallic silicide film 66 is formed on exposing surfaces of source/drain areas 70a through 70d.
As illustrated in FIG. 27, an inter-layer insulating film 67 is formed above an entire surface of a silicon substrate 51. Thereafter, as illustrated in FIG. 28, a resist 68 is coated, and a part of the resist above a source/drain area 56b in the memory device region is patterned by photoengraving. As illustrated in FIG. 29, the inter-layer insulating film 67 is subjected to anisotropic etching using the resist 68 as a mask and a silicon nitride film 60 as an etching stopper. The resist 68 is removed. As illustrated in FIG. 30, the silicon nitride film 60, a silicon oxide film 59, and an insulating film 58 are subjected to anisotropic etching in a self-replicating manner to expose the source/drain area 56b, whereby a self-alignment contact opening 69 is formed.
As illustrated in FIG. 25, in the conventional logic process consolidating device, the silicon nitride film 60 above gate electrodes 57a through 57c is etched as a result of over-etching, which occurs at time of etching the silicide protection film 64 in the memory device region. Therefore, any etching stopper does not exist above the source/drain area 56b, whereby there is a possibility that the gate electrode is exposed at time of forming the self-alignment contact opening 69. When the gate electrode is exposed, there is a problem that a wiring layer such as a bit wire formed after forming the self-alignment contact opening 69 is shorted with the gate electrode, wherein reliability of the semiconductor device is deteriorated.
Meanwhile, as illustrated in FIG. 25, it is difficult to etch the silicide protection film 64 between the gate electrodes to completely remove this because an aspect ratio between the gate electrodes is high. Thus the silicide protection film 64 is left between the gate electrodes. The aspect ratio between the gate electrodes are further increased by the remaining silicide protection film 64. As a result, as illustrated in FIG. 27, the inter-layer insulating film 67 is not formed between the gate electrodes at time of forming the inter-layer insulating film 67 made of BPSG and so on, whereby a cavity is formed therein. Accordingly, there is a problem that transistors are not securely insulated, wherein reliability of the semiconductor device is deteriorated.
Further, because the remaining silicide protection film 64 left at time of etching the inter-layer insulating film 67 in steps illustrated in FIGS. 28 and 29 is hardly etched since the remaining silicide protection film 64 does not contain boron or phosphorous. Thus, the remaining silicide protection film 64 is left between the gate electrodes 57b, 57c and a hole. Accordingly, there are problems that the aspect ratio of the self-alignment contact opening 69 is increased as illustrated in FIG. 30, and it becomes difficult to connect a wiring layer formed after forming the self-alignment contact opening 69 to the source/drain area 56b in the silicon substrate 51.
Further, in the logic process consolidating device, because there are processes for all of devices integrated in the logic process consolidating device and processes for a single device, the number of steps for forming the logic process consolidating device is increased, wherein the producing process is in tendency of complicating.
It is an object of the present invention to solve the above-mentioned problems in the conventional logic process consolidating device and to provide a semiconductor device having different devices on one semiconductor substrate, namely a logic process consolidating device, and a method of producing the semiconductor device without complicating a production process.
According to a first aspect of the present invention, there is provided a semiconductor device having a memory device region (100) and a logic device region (101) on a principle surface of a semiconductor substrate comprising:
a pair of first and second source/drain areas (6a, 6b) formed with an interval so as to sandwich a first channel region (3a) on a principle surface of the memory device region (100);
a pair of first and second low concentration impurity regions (6c, 6d) formed with intervals so as to sandwich a second channel region (3b) on a principle surface of the logic device region;
a first gate electrode (7b) and a second gate electrode (7d) formed on a gate oxide film (5) respectively formed on the first channel region (3a) and second channel region (3b);
a silicon oxide film (9) formed so as to cover the first gate electrode (7b) and the second gate electrode (7d);
a silicon nitride film (10) formed on the silicon oxide film (9);
an inter-layer insulating film (15) formed on the silicon nitride film (10);
a self-alignment contact opening (17) formed in an area above the first source/drain area (6b) of the inter-layer insulating film (15), the silicon nitride film (10), and the silicon oxide film (9) formed on the memory device area (100);
a side wall film made of the silicon oxide film (9) and the silicon nitride film (10) extending through areas above the first and the second low concentration impurity regions (6c, 6d) so as to cover an upper portion and a side wall of the second gate electrode (7d); and
first and second high concentration impurity regions (12c, 12d) formed from ends of the side wall film on the semiconductor substrate (1).
According to a second aspect of the present invention, there is provided the semiconductor device,
wherein the silicon oxide film (9) and the silicon 25 nitride film (10) formed on the upper portion and the side surface of the second gate electrode (7d) in the logic device region (101) have a function as a silicide protection film in addition to a function as the side wall film for the second gate electrode (7d).
According to a third aspect of the present invention, there is provided a method of producing a semiconductor device having a memory device region (100) and a logic device region (101) on a principle surface of a semiconductor substrate (1) comprising steps of:
forming a pair of first and second source/drain areas (6a, 6b) with an interval so as to sandwich a first channel region (3a) on the memory device region (100) and a pair of first and second low concentration impurity regions (6e, 6f) with an interval so as to sandwich a second channel region (3c) in the logic device region (101);
forming a first gate electrode (7b) and a second gate electrode (7e) on gate oxide films (5) respectively above the first channel region (3a) and the second channel region (3c);
forming a silicon oxide film (9) on the semiconductor substrate (1) so as to cover the first gate electrode (7b) and the second gate electrode (7e);
forming a silicon nitride film (10) on the silicon oxide film (9);
coating a resist (11) on an upper portion of the second gate electrode (7e) and providing the silicon oxide film (9) and the silicon nitride film (10) with anisotropic etching using the resist as a mask; and
implanting impurity ions into the semiconductor substrate (1) in a self-replicating manner using the resist (11), the silicon oxide film (9), and the silicon nitride film (10) as a mask to form first and second high concentration impurity regions (12a, 12b).
According to a fourth aspect of the present invention, there is provided the method of producing the semiconductor device further comprising steps of:
forming a high-melting metallic silicide film (14) on surfaces of the first and second high concentration impurity regions (12a, 12b) after the step of forming the first and second high concentration impurity regions (12a, 12b).
According to a sixth aspect of the present invention, there is provided the method of producing the semiconductor device further comprising steps of:
forming an inter-layer insulating film (15) on an entire surface of the semiconductor substrate (1) after the step of forming the high-melting point metallic silicide film (14); and
forming a self-alignment contact opening (17) in a region positioned above the first source/drain area (6b) of the inter-layer insulating film (15), the silicon nitride film (10), and the silicon oxide film (9) formed in the memory device region (100).
According to a seventh aspect of the present invention, there is provided the method of producing the semiconductor device,
wherein the step of forming the self-alignment contact opening (17) comprising steps of:
forming a first opening by etching the inter-layer insulating film (15) above the first source/drain area (6b) using the silicon nitride film (10) as an etching stopper film; and
forming a second opening reaching the first source/drain area (6b) by etching the silicon nitride film (10) and the silicon oxide film (9) inside the first opening.

Semiconductor device and a method of producing the same


A universal reel device includes an upper cover and a lower cover fastened together, a spool, a spiral spring and a safety switch for locking the spool. The spool has a bottom layer, a middle layer and a top layer. The middle layer is an annular cable distributing disk having a cable hooking slot. A bottom portion of the bottom layer is formed with a planar track and a U-shaped movable tongue for positioning is disposed between the bottom layer and the lower cover. The universal reel device can reel in various cable products, and may also be combined with a cable to form a single-pull or dual-pull reel. In use, a safety switch is used to lock the spool. The spool cannot rotate until the user unlocks the safety switch so that the high safety feature is obtained.

(1) Field of the Invention
The invention relates to a cable reel device, and more particularly to a universal reel device for storing cables of various electronic apparatuses, wherein the universal reel device can be combined with a cable to form a single-pull reel or a dual-pull reel.
(2) Description of the Prior Art
As is well known in the art, products including a wired earphone, a mouse, a keyboard, a charger and the like have to obtain information, transmit information or be powered through a cable such as a data transmission cable. Alternatively, a key ring, stationery and accessory can be reeled in and out through a simple cable connected thereto. In the early period, the cable is usually wound or irregularly collected. However, the irregular cable tends to intertwine so that the use becomes awry. Thus, many designers sequentially design many structures and products on the reel-in and reel-out functions of such a kind of cables. Such kind of product mainly has a spiral spring serving as a main body, and the elastic winding force of the spiral spring reels in the cable according to a helical path or an annular path. When the cable is pulled out, the outward extending latching force of the spiral spring slightly restricts the operation of pulling out the cable. However, the restricting force still can be easily overcome. Thus, the cable being reeled in and out has a track path and encounters the restricted force, so that the cable can be smoothly reeled in and out.
However, the above-mentioned cable reels have the cables therein. That is, one end of the cable of the product, such as the earphone, the mouse, the keyboard, the charger and the like, needs to be fixed to the cable reel, and one cable reel only can be applied to only one product, thereby restricting the used range of the cable reel. In addition, when the existing cable reel is being used and the cable or the cable reel is unintentionally or accidentally touched, the cable reel tends to enter the automatic reel-in state and the elastic winding force of the spiral spring is instantaneously released, and the product connected to the cable suddenly bounces to hurt the user. Thus, the safety is not high.

Dong Guan Top Den Electronics Limited Company


Chimeric somatostatin-based polypeptides, polynucleotides used to encode the polypeptides, the methods for isolating and producing the polypeptides and the uses thereof are provided. In addition, low cost adjuvants for enhanced immunogenic response are provided. Vaccinations that include both chimeric somatostatin-based polypeptides and novel adjuvants are included, useful in facilitating farm animal productivity.

Somatostatin (also known as growth hormone inhibiting hormone or GHIH) is a peptide hormone produced in the hypothalamus as well as certain portions of the digestive system. Somatostatin is generally involved in regulation of the endocrine system via interactions with G-protein-coupled somatostatin receptors. This somatostatin-based signaling cascade leads to a number of actions spread throughout the body.
Relevant to aspects of the present invention, somatostatin is known to inhibit the release of growth hormone and thyroid stimulating hormone from the anterior pituitary. (Patel Y C and Srikant C B, Somatostatin and its receptors Adv Mol Cell Endocrinol, 1999. 3 43-73). Other hormones inhibited by somatostatin include insulin, glucagon, secretin, gastrin, pepsin, maletin, etc. (Patel Y C and Srikant C B Somatostatin and its receptors Adv Mol Cell Endocrinol, 1999. 3 43-73). The ability of somatostatin to regulate so many factors/hormones necessary for growth and utilization of food has made somatostatin a central target for controlling animal growth in the animal husbandry field, i.e., inhibiting somatostatin results in increased levels of growth hormone being present in a target animal and thereby results in animals with enhanced capacity to produce milk, to provide greater amounts of meat, etc.
In particular, immunization of animals to somatostatin has been recognized as a means of neutralizing somatostatin in a target animal and thereby removing somatostatin's normal inhibitory effects on various aspects of the animal's productivity, e.g., milk production in a dairy cow. Reichlin S., ed., 1987, Somatostatin, Basic and Clinical Status, Plenum Press, New York (pp 3-50, 121-136, 146-156, 169-182, 221-228, 267-274) Spencer G. S., 1985, Hormonal systems regulating growth, review, Livestock Production Science, 12, 31-46. Importantly, these somatostatin-based immunization procedures avoid the direct use of anabolic hormones, e.g., growth hormone, and the like, in the animal and allow for small changes in the concentration of the endogenous anabolic factors and thereby ecologically pure food products.
Somatostatin is known to have a relatively short half-life in the blood. In order to enhance the immunologic effects of somatostatin, immunization protocols have been developed to enhance the proteins half-life by conjugating somatostatin to target carrier proteins. These conjugated somatostatin proteins are designed to have increased half-life and increased antigenicity in the blood and therefore provide enhanced benefits (especially in light of the cost of preparing somatostatin). For example, chimeric somatostatin proteins are disclosed in U.S. Pat. No. 6,316,004, (and corresponding European Patent EP0645454) where various conjugated somatostatin-containing proteins are shown to have increased antigenicity and function with regard to productivity of farm animals as compared to other conventional immunization or anabolic hormone-based procedures.
However, lower dose, higher antigenicity based immunization compositions and procedures are needed to improve overall productivity and timeliness in the animal husbandry field. The present invention is directed toward providing these more antigenic and functionally active somatostatin-based immunization compounds, compositions and procedures.
Against this backdrop the following disclosure is provided.

Chloramphenicol acetyl transferase (CAT)-defective somatostatin fusion protein and uses thereof


Targets to be read by image capture are illuminated and imaged over an extended range of working distances. A near imager captures return light over a relatively wide imaging field of view from a target located in a close-in region of the range. A far imager captures return light over a relatively narrow imaging field of view from a target located in a far-out region of the range. A single illuminating light assembly is shared by both the near and far imagers. An illumination light source emits illumination light, and an illuminating lens assembly optically modifies the emitted illumination light, and simultaneously illuminates a wide illumination field to illuminate the target located in the close-in region of the range, and a narrow illumination field to illuminate the target located in the far-out region of the range.

The present invention relates generally to an imaging module and an imaging reader for, and a method of, illuminating and imaging targets to be read over an extended range of working distances.
Solid-state imaging systems or imaging readers have been used, in both handheld and/or hands-free modes of operation, to electro-optically read targets, such as one- and two-dimensional bar code symbol targets, and/or non-symbol targets, such as documents. A handheld imaging reader includes a housing having a handle held by an operator, and an imaging module, also known as a scan engine, supported by the housing and aimed by the operator at a target during reading. The imaging module includes an imaging assembly having a solid-state imager or imaging sensor with an array of photocells or light sensors, which correspond to image elements or pixels in an imaging field of view of the imager, and an imaging lens assembly for capturing return light scattered and/or reflected from the target being imaged, and for projecting the return light onto the array to initiate capture of an image of the target. Such an imager may include a one- or two-dimensional charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) device and associated circuits for producing and processing electronic signals corresponding to a one- or two-dimensional array of pixel data over the imaging field of view. In order to increase the amount of the return light captured by the array, for example, in dimly lit environments, the imaging module generally also includes an illuminating light assembly for illuminating the target with illumination light in an illumination pattern for reflection and scattering from the target.
In some applications, for example, in warehouses having targets on products located on high shelves, it is necessary that such targets be capable of being read by the reader at an extended range of working distances, for example, on the order of thirty to fifty feet, away from the reader. For this purpose, it is known to employ two imagers: a so-called near imager or camera to image close-in targets over a relatively wide imaging field of view, and a so-called far imager or camera to image far-out targets over a relatively narrow imaging field of view. It is also known to employ two illuminating light assemblies, each customized for each imager. For example, the illuminating light assembly for the far-out targets generally illuminates such far-out targets with more intense, brighter illumination light as compared to the illuminating light assembly for the close-in targets. It is further known to employ zoom-type or liquid crystal-based illumination mechanisms to sequentially illuminate targets at different working distances from the reader.
Although generally satisfactory for its intended purpose, the known use of two imagers and two illuminating light assemblies, as well as the known use of zoom-type or liquid crystal-based illumination mechanisms, increases the size, cost, electrical power consumption, and complexity of the imaging module, and, in turn, of the overall reader. Sequential switching between illuminating light assemblies, and zooming between working distances, can cause the illumination patterns to appear to flicker and can, in some cases, annoy the operators of the readers, as well as bother nearby bystanders or consumers. Zoom response times can be slow. Any mechanical zoom part is subject to wear and tear and can produce undesirable noise. Stray illumination light from the illuminating light assemblies may, sometimes, interfere with the operation of the imaging assembly, which can cause reading performance to deteriorate.
Accordingly, there is a need to reduce the size, cost, electrical power consumption, and complexity of the imaging module and of the overall reader, to avoid flickering illumination light patterns, to improve response times, to avoid wear and tear from moving parts, and to prevent stray illumination light from degrading reading performance.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions and locations of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The system and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

Imaging module and reader for, and method of, illuminating and imaging targets to be read over an extended range of working distances


An improved process is disclosed for preparing flavored confectionery compositions containing certain reduced calorie cocoa butter substitute fats. The improvement involves rapidly cooling such a composition from a non-crystalline state to a temperature of less than about 70.degree. F. (21.1.degree. C.) using a swept-wall, scraped-wall, or screw-type heat exchanger. The cooled composition is then conditioned for at least about 5 minutes by warming it to a temperature of about 70.degree. to 85.degree. F. (21.1.degree. to 29.4.degree. C.) in an agitated vessel before further processing into finished confectionery pieces. Under these dynamic tempering conditions, bloom-stable products can be produced much faster than with static tempering.

Chocolate derives its desirable eating qualities largely from the melting properties of cocoa butter which is typically present at 25-35% by weight. At room temperature (70.degree.-74.degree. F., 21.1.degree.-23.3.degree. C.) cocoa butter is a firm solid. Firmness is desirable not only to provide "snap" at initial bite, but also to resist deformation and surface marking of the chocolate from time of manufacture to time of consumption.
Above room temperature, cocoa butter melts progressively until it is fully melted near 93.degree.-94.degree. F. (33.9.degree.-34.4.degree. C.), and is therefore entirely liquid below body temperature (98.6.degree. F., 37.degree. C.). This rapid melting at mouth temperature ("mouthmelt") provides a smooth, creamy consistency during eating and insures rapid release of chocolate flavors to the mouth. The relatively sharp melting behavior just a few degrees below body temperature is unique to cocoa butter among natural fats.
The melting behavior of cocoa butter is the result of its unique triglyceride composition. However, this unique triglyceride composition, like the triglyceride composition of other natural fats, is relatively high in calories. Approximately 50% of the calories in chocolate products come from the fat which is exclusively or predominantly cocoa butter. This means that persons who must restrict their intake of calories must either reduce the amount of chocolate products they consume, or in the extreme case, completely exclude such products from their diet. Accordingly, it would be desirable to be able to replace all or a portion of the cocoa butter present in such chocolate products with a substitute fat having fewer calories, while maintaining the desirable physical properties of cocoa butter in chocolate products.
The selection of a reduced calorie substitute fat for cocoa butter is not straightforward. First, the substitute fat must be less efficiently absorbed and/or metabolized by the body in order to exhibit a lower caloric density. Second, the substitute fat should temper and crystallize into a solid form that is very sharp melting and has mouth-melt characteristics the same, or similar, as those of cocoa butter, or combinations of cocoa butter and milkfat, present in confectionery products. Third, the crystalline form of the substitute fat should be stable under typical conditions of confectionery product distribution and handling without any significant change in the mouthmelt characteristics or appearance of the substitute fat-containing confectionery product. Such undesirable changes include the development of a waxy or grainy mouthfeel and the development of bloom, i.e. a whitish or grayish discoloration visible on the surface, or sometimes in the interior, of the confectionery product. These changes can be caused by the growth of excessively large fat crystals, the transformation of the fat crystals into a higher melting polymorphic form, the presence of too high a level of lower-melting fatty components, or incompatibility between the substitute fat and other fats present in the confectionery product, in particular cocoa butter that is typically present in the chocolate liquor and/or cocoa powder used to impart a chocolate flavoring to such products. Lastly, the substitute fat should be processable in current commercial operations used to make confectionery products.
One reduced calorie fat that has been found to be useful as a cocoa butter substitute comprises a fairly high level (e.g., at least about 85%) of combined MML and MLM triglycerides, where M is typically a mixture of C.sub.8 and C.sub.10 saturated fatty acids and L is predominantly behenic acid. See Ehrman et al. U.S. Pat. No. 4,888,196, issued Dec. 9, 1989. Unlike other cocoa butter replacers, this reduced calorie cocoa butter substitute fat exhibits polymorphism and needs to be tempered or precrystallized and then crystallized into its stable .beta.-3 crystalline phase, just as cocoa butter does. However, if chocolate products based on this reduced-calorie cocoa butter substitute fat are tempered using typical equipment and conditions suitable for cocoa butter-based chocolate products (i.e. rapidly cooling to about 82.degree. to 86.degree. F. (27.8.degree. to 30.0.degree. C.) and then warming to about 88.degree. to 93.degree. F. (31.1.degree. to 33.9.degree. C.), the products do not harden sufficiently when cooled to be wrapped or otherwise packaged, nor shrink sufficiently in molds to be easily demolded with glossy appearance, and will develop bloom.
The Ehrman et al. patent discloses an alternative tempering process for obtaining flavored confectionery products using this reduced calorie cocoa butter substitute fat. This tempering process involves rapidly cooling the flavored confectionery composition to a temperature of about 57.degree. (13.9.degree. C.) or less. This cooled composition is then held at this temperature for at least about 16 hours, which is sufficient to form, or nucleate, an effective amount of .beta.-3 crystals from a portion of the reduced calorie cocoa butter substitute fat. The cooled composition is then warmed to a temperature in the range of from about 57.degree. to about 72.degree. F. (about 13.9.degree. to about 22.2.degree. C.) to transform the remaining portion of the reduced calorie cocoa butter substitute fat into the stable .beta.-3 crystalline phase, in about 4 to about 120 hours.
Using the tempering scheme disclosed in the Ehrman et al. patent, it typically takes from about 1 to about 3 days after preparing the molten chocolate mass to obtain chocolate-flavored products which are stable against resulting bloom formation, especially when subjected to thermal stress. Accordingly, it would be desirable to develop a process for preparing chocolate-flavored confectionery compositions containing these reduced calorie cocoa butter substitute fats that does not require a prolonged tempering scheme according to the Ehrman et al. patent to provide a bloom-stable .beta.-3 phase. In particular, it would be desirable to develop a process for preparing these reduced calorie chocolate-flavored confectionery compositions that can be more easily adapted to standard manufacturing and packaging processes used in commercial cocoa butter-based chocolate operations.

Process for preparing reduced calorie flavored confectionery compositions using dynamic tempering conditions


A memory-fabric-based processor context switching system includes server devices coupled to a memory fabric. A first processing system in a first server device receives a request to move a process it is executing and, in response, copies first processing system context values to its first local memory system in the first server device, and generates a first data mover instruction that causes a first data mover device in the first server device to transmit the first processing system context values from the first local memory system to the memory fabric. A second processing system in a second server device generates a second data mover instruction that causes a second data mover device in the second server device to retrieve the first processing system context values from the memory fabric and provide the first processing system context values in a second local memory system included in the second server device.

The present disclosure relates generally to information handling systems, and more particularly to switching context between processing systems via a memory fabric.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
In information handling systems such as, for example, server devices, it may be desirable in some cases to provide for the switching of a processor context between processors. As would be understood by one of skill in the art, processor context switching may include the operation of transferring processor context values included in the registers in a first processor to registers in a second processor so that a process, thread, or other processing result being provided by the first processor may be provided by the second processor. However, conventional processor context switching performed in server devices that utilize the von Neumann architecture requires the processor(s) to perform read, copy, write, transfer, and/or other context switching operations that utilize relatively valuable processing cycles on what is a relatively mundane data transfer operation. For example, such operations may include a first processor stopping a process or thread running on the first processor, storing the processor context values for the first processor in a local memory provided for the first processor, and transmitting the processor context values for the first processor from the local memory that is provided for the first processor to the second processor, with the second processor storing the processor context values for the first processor in a local memory provided for the second processor, loading the processor context values for the first processor from the local memory provided for the second processor and into the second processor, and using the processor context values (e.g., instruction pointer information included in the processor context values) to resume the process or thread at the point at which it was stopped on the first processor.
Accordingly, it would be desirable to provide an improved processor context switching system.

Memory-fabric-based processor context switching system


A network management system (NMS) including a policy manager (PM) associated with a set of policies and including distribution means for sending said policies to policy enforcement points (PEP1, PEP2, PEP3, PEP4) in accordance with distribution instructions via policy decision points (PDP1, PDP2), characterized in that said policy manager further includes validation means for validating if said policy enforcement points can enforce said policies and correcting said distribution instructions as a function of said validation.

Accordingly, as shown in FIG. 1, a network N, in particular a telecommunications network, is made up of a set of equipment units E1, E2, E3, E4. It is generally associated with a network management system NMS, one object of which is to manage the behavior of the network, as function of requests submitted to it. In particular, each service request from a client can lead to reconfiguration of some of the network equipment. This reconfiguration is more widely known as "service provisioning".
A conventional way to establish a dynamic link between requests (in particular service requests) and the required reconfigurations is to define a set of policies. This approach is recommended by the Internet Engineering Task Force (IETF) and is described in its RFC 3060 "Policy Care Information Model—Version 1 Specification", February 2001, and RFC 3198 "Terminology for Policy-Based Management", November 2001, for example.
The policies are managed by a Policy Manager PM. The policy manager PM sends the policies to policy decision points PDP1, PDP2 in accordance with distribution instructions. The distribution instructions are typically provided by the operator when the policies are created.
Finally, the policy decision points PDP1, PDP2 send the policies to policy enforcement points PEP1, PEP2, PEP3, PEP4. The policy enforcement points PEP1, PEP2, PEP3, PEP4 are associated with respective network equipment units E1, E2 E3, E4.
Because it uses policies, the network is able to adapt dynamically and automatically to requests, in particular service requests, as and when they arise.
However, this kind of approach has a major drawback in that it presumes that the distribution instructions are free of errors. This leaves the operator responsible for defining the policies and distribution instructions, which is a heavy responsibility, and for the time-consuming task of consulting a detailed map of the network in order to determine the capabilities of each network equipment unit.
In the event of an error, a policy enforcement point PEP will attempt to apply a policy to a network equipment unit that is incapable of enforcing it. This can interfere with the operation of the network unit and, on the other hand, lead to poor performance of the policy deployed by the operator.

Network management system with validation of policies


A shifter for an automatic transmission is prevented from shifting out of Park position when the ignition switch is on unless the service brake is applied. An articulated solenoid-operated blocking arm is positioned to selectively block movement of a locking pin to prevent the shift lever from leaving the Park position of the shift gate. A circuit, including switches responsive to ignition, service brake application and shift lever position, controls solenoid activation. A cam responsive to the shift lever release button and to the lever position controls the shift lever position switch. The blocking arm can comprise two segments joined by a hinge. In blocking position, the hinge lies on one side of the path of pin movement. If the pin release is prematurely actuated, the pin engages the blocking arm. Subsequent solenoid activation pushes the hinge overcenter so that pin force will collapse the blocking arm, enabling its movement out of blocking position by the solenoid. An alternative blocking arm is an integral plastic piece with two segments interconnected by an integral hinge or two independent segments interconnected by a hinge pin. Alternatively, the blocking arm can comprise a single segment mounted for movement by a pin-and-slot arrangement.

This invention relates generally to a brake-transmission interlock and particularly to a mechanism for permitting automatic transmission shifter movement from Park position only when the vehicle service brake is applied.
In automobiles with an automatic transmission, it is a preferred practice for the operator to apply the service brakes at the time the transmission selector lever is moved from Park position to one of the Drive range positions. This practice not only assures that the vehicle is held stationary during this shift, but also assures that the operator's foot does not inadvertently operate the accelerator pedal. It has been proposed to provide an interlock mechanism to prevent shifting out of Park position unless a brake is first applied.
A shift lever and parking brake control which has a pin on a shift lever movable through a shift gate having a Park position is shown in U.S. Pat. No. 4,473,141 to Mochida. An electromagnetically controlled plunger spring is biased into the gate to block pin movement into or out of the Park position. The electromagnet is electrically connected in series with a parking brake switch and an ignition switch. This causes the plunger to be withdrawn by the electromagnet to permit shifting between Park and Reverse only when the engine is running and the parking brake is on.
An electromagnetically controlled lock for a shift selector which is released for operation when ignition is turned on is disclosed in U.S. Pat. No. 3,994,183 to Markl. A brake interlock is not included in this disclosure.
In another brake-transmission interlock in current use, a pin on a shift lever movable through a shift gate having a Park position is blocked from leaving the Park position by a solenoid operated blocking member in the path of the pin. The blocking member is pivotally mounted on the same axis as the shift lever for movement between blocking and release positions. A solenoid, actuated only when the service brake is released, moves the blocking member to a blocking position and when the brake is applied, a spring moves the member to a noninterfering position.
Another brake-transmission interlock in current use is illustrated in U.S. Pat. No. 5,062,509 to Carpenter et al, and owned by the assignee hereof. In this shifter, the blocking member is pivoted commonly with the shift lever and presents a radial shoulder blocking radially inward movement of a release pin by the shift lever-mounted release button. This shoulder prevents movement of the release pin out of the Park position notch in the shift gate and subsequent movement of the shift lever out of Park position.
A problem encountered with this arrangement is that premature depression of the release pin (prior to actuation of the solenoid by depressing the brake pedal) will cause the release pin to engage the outer surface of the blocking member. This engagement produces a frictional force which can be substantial if the release button is depressed firmly. If this force is large enough, it can cause the pin to bind up the blocking member and prevent its movement out of blocking position by the solenoid.
Thus, it is desirable to provide a brake-transmission interlock having a blocking member that cannot be bound up by premature depression of the shifter release button.

Shifter park position brake-transmission interlock


A method and apparatus is disclosed for manufacturing papermakers or like fabrics wherein preformed apertured fabric bands are joined together in spaced edge-to-edge disposition in a manner to provide substantial uniformity of construction throughout the fabric width. The invention proposed supporting the bands (11, 12) in spaced parallel disposition on a pinned roller (26) wherein the distribution and configuration of the pins (34) matches the apertures in the bands and creating an infill band in the region between adjacent preformed bands (11, 12) by feeding thermoplastic matrix material to the surface of the pinned roller in said region, causing said matrix material to flow into interstices between the pins and to bond with the material of the preformed bands. Reinforcing yarns (13) will be provided in the region between adjacent preformed bands and extending in a direction parallel to the bands and will be embodied within the matrix material of the joined structure. Transversely extending yarns may be provided on the preformed bands for like encapsulation by the matrix material of the infill band.

In the manufacture of papermachine and like clothing it has been proposed to create an apertured fabric by feeding an array of yarns and polymeric matrix material to the surface of a pinned drum and passing the yarns and matrix material through a roller nip thereat to be pressed into full engagement with the drum surface, the matrix material being in molten form and the resultant apertured sheet material being cooled and removed from the drum. The molten matrix material will ordinarily be provided from a heated reservoir through which the yarns pass, and from which the yarn/matrix material combination is fed to the drum surface, the matrix material flowing into the channels in the profiled drum surface under the effect of the pressure applied by the nip roller.
Papermachine and like fabrics are of significant dimensions, a typical fabric being, say, 60 meters long by 10 meters wide, and such fabrics require a high degree of permeability which is sensibly constant throughout the body of the fabric, although a reduction in permeability is perhaps desirable in the edge regions of the structure. Given the accuracy required of the pins provided on the drum, both as to their small dimensions and close centres, each pin representing a single aperture and an aperture being, for example, 0.2 mm square and the pins being at 1.1 mm centres both in the axial and peripheral directions of the drum, and the need to produce a fabric having a width of significant proportions, for reasons of economy, in terms both of financial and space considerations, it is more realistic to produce a plurality of relatively narrow fabric bands to be joined together in side-by-side disposition, rather than to produce the fabric to its full intended width in the first instance, and it is to this concept that the present invention is directed.


The present invention is directed to immunochemical detection procedures, e.g., using both Western blotting and direct immunoassays, for fragments of Factor Va, which can thus be used; (a) in a predictive manner to evaluate the existence and/or extent of a thrombotic complication; (b) to monitor the efficacy of prophylaxis for a thrombotic condition; and (c) as a means to evaluate potential risk of hemorrhage during thrombolytic therapy.

The formulation of .alpha.-thrombin is a central event during the blood coagulation cascade. Prothrombin is activated to .alpha.-thrombin by the prothrombinase complex which is composed of the serine protease factor Xa and the protein cofactor factor Va assembled on a membrane surface in the presence of Ca.sup.2+ ions (1).sup.1. In the absence of factor Va, factor Xa is capable of activating prothrombin to .alpha.-thrombin (2); however, the prothrombinase complex is 5 orders of magnitude more efficient in generating .alpha.-thrombin than factor Xa acting along (2). Once formed, .alpha.-thrombin acts as a procoagulant enzyme, catalyzing the formulation of the fibrin clot by converting soluble fibrinogen to insoluble fibrin polymers (3). .alpha.-Thrombin also binds to the endothelial cell receptor thrombomodulin, and the resulting .alpha.-thrombin-thrombomodulin complex exhibits altered proteolytic specificity (4,5). This complex catalyzes the activation of protein C to form the anticoagulant enzyme activated protein C (APC)..sup.1 FNT .sup.1 Reference articles are indicated herein by (number) and are identified before the claims under the heading CITED REFERENCES.
Activation of bovine protein C occurs by cleavage of a single peptide bond (Arg.sup.171) located at Arg.sup.14 of the heavy chain of protein C (5). Bovine protein C is also activated by the factor Xz-thrombomodulin complex which produces an APC molecule (6). The proteolytic APC antithrombotic function is expressed by inactivating factor Va and factor VIIIa, two important cofactors of the blood coagulation cascade (7, 8).
Factor V circulates s a single chain procofactor (M.sub.4 330,000). The CDNA sequence for bovine factor V and deduced amino acid sequence have been determined (9). The active form of the protein, factor Va (10-12), is composed of a heavy chain (M.sub.r 94,000) containing the NH2-terminal part of the procofactor (residues 1-713) and a light chain (Mr 74,000) containing the COOH-terminal part of the molecule (amino acids 1537-2183; Ref. 9). The two chains are noncovalently associated (13, 14).
The inactivation of factor Va by APC occurs in the presence as well as in the absence of a lipid bilayer or platelet surface (15-20). Previous studies have demonstrated that bovine factor Va in the absence of a lipid bilayer and in the presence of high concentrations of APC is slowly and partially inactivated (20). In contrast, earlier kinetic data showed that in the presence of an anionic phospholipid membrane surface factor Va is rapidly and completely inactivated by APC (15-17). Recent data also showed that bovine factor Va phosphorylation at the COOH-terminal end of the heavy chain on Ser.sup.690 results in a molecule that is more sensitive to APC inactivation that its native counterpart (21). The identification of the APC proteolytic cleavage sites in the cofactor observed in the absence of phospholipid has been correlated with the partial inactivation of factor Va. Thus, although studies demonstrate that inactivation of the cofactor is a rapid phenomenon in the presence of a membrane surface (15-17), the chemical studies relating the APC effect on the factor Va molecule functions have been performed in the absence of lipids (18,22,23).
APC cleavage of the bovine factor Va heavy chain at Arg.sup.505 and Arg.sup.662 (and Arg.sup.506 in the human sequence) is responsible for the partial inactivation of the cofactor (20). However, in these studies even after prolonged incubation of factor Va with high APC concentrations (i.e., 4 h, 1:1 molar ratio) in the absence of a membrane surface the cofactor still retained 30-35% of its initial cofactor activity (20). Thus, the contribution of the membrane to the mechanism by which APC inactivates factor Va has not been elucidated yet.
It has been shown that vitamin K-dependent protein S plays a role in the APC inactivation process only in the presence of a phospholipid membrane (24,25). Its functions have not been established clearly yet, but protein S must play an important role as an antithrombotic agent since studies demonstrated that familial heterozygous deficiency of protein S is associated with venous and arterial thrombosis (26,27).

Immunologic detection of factor VA fragments in hemorrhagic and thrombotic clinical settings


This invention provides a method of inhibiting the transcription of a gene, which is activated by AP-1 or an AP-1 component, comprising binding AP-1 or the component with a nuclear receptor so as to prevent the binding of AP-1 to the gene. The nuclear receptor can be the retinoic acid receptor, glucocorticoid receptor, vitamin D3 receptor, thyroid receptor, or estrogen receptor. Also provided is a composition of matter comprising AP-1 or an AP-1 component bound to a nuclear receptor. These methods and compositions can be used to treat arthritis and cancer.

References are cited throughout the specification. These references in their entirety are incorporated by reference into the specification to more fully describe the state of the art to which it pertains.
Positive and negative control of gene expression by retinoids is mediated by nuclear receptors that are part of a large family of regulatory proteins including the steroid and thyroid hormone receptors, the vitamin D receptor, and the retinoid receptors (RAR). This latter group comprises three retinoic acid (RA) receptors: RAR.alpha., .beta. and .tau., that contain highly conserved DNA and ligand binding domains. In addition a more distantly related receptor, RXR, appears to be activated by a RA metabolite.
Nuclear receptors function as transcriptional activators in the presence of their ligand. RARs, like the thyroid hormone receptors, do not require ligand binding for nuclear localization and specific DNA interaction. Until the subject invention, interaction with specific DNA sequences was thought to be essential for all regulatory functions of nuclear receptors.
Since glucocorticoids and RA are known to repress members of the collagenase family they have promise as therapeutic agents in rheumatoid arthritis where proteinases, such as collagenase and stromelysin, play an important role in joint destruction. Collagenase is the only enzyme known to cleave collagen, a major structural component of bone and cartilage destroyed by the enzyme. Retinoids inhibit the production of collagenase by synovial cells while the tumor promoter 12-0-tetradecanoylphorbol-13-acetate (TPA) and the inflammatory mediators interleukin 1 (IL1) and tumor necrosis factor alpha (TNF.alpha.) stimulate collagenase secretion and transcription.
Thus, while the RA and glucocorticoid nuclear receptors are known to repress members of the collagenase family, the mechanism of this repression was not known. A logical presumption was that the repression relates to the receptors known ability to bind DNA. However, the present invention provides the surprising discovery that these nuclear receptors actually inhibit transcription through a protein/protein interaction with AP-1, a protein complex composed of Jun homodimers and Jun/Fos heterodimers. Hence, a major discovery that regulatory function of nuclear receptors are mediated by a mechanism that does not involve direct binding to DNA is provided. This discovery provides a mechanism through which arthritis and cancer can be treated.

Method of inhibiting transcription utilizing nuclear receptors