A semiconductor integrated circuit device comprises an n-type well 8-1 formed in a p-type silicon substrate 1, an n-type well 8-2 formed so as to surround a part of the substrate 1, in which a pxe2x88x92-type well is formed, a pxe2x88x92-type well 15-1 formed in the substrate 1, a pxe2x88x92-type well 15-2 formed in a part of the substrate 1, which is surrounded by the n-type well, an embedded n-type well 12-1 formed below the pxe2x88x92-type well 15-1, and an n-type well 12-2 which is formed below the pxe2x88x92-type well 15-2 and which is connected to the n-type well 8-2. Thus, it is possible to provide a semiconductor integrated circuit device capable of suppressing the increase of the number of photolithography steps and reducing the manufacturing costs.

1. Field of The Invention
The present invention relates generally to a semiconductor integrated circuit device which has a well having the same conductive type as that of a substrate and being pn-separated from the substrate and which has various gate insulator films having different thickness, and a method for producing the same. More specifically, the invention relates to a technique for reducing the number of masks for use in the production of the semiconductor integrated circuit device.
The present invention also relates generally to a semiconductor integrated circuit device including two kinds of transistors having the same conductive channel. More specifically, the invention relates to a method for producing a semiconductor integrated circuit device, which forms wells for element regions by ion implantation before forming an element isolating insulator film.
2. Related Background Art
A typical CMOS semiconductor integrated circuit device has an n-type well for forming a p-channel MOSFET (which will be hereinafter referred to as a xe2x80x9cPMOSxe2x80x9d), and a p-type well for forming an n-channel MOSFET (which will be hereinafter referred to as an xe2x80x9cNMOSxe2x80x9d).
Some of such typical CMOS semiconductor integrated circuit devices have a well which is pn-separated from a substrate and which has the same conductive type as that of the substrate. For example, there is a semiconductor integrated circuit device wherein an NMOS, in which a back gate potential is the same as the potential of a p-type substrate, and an NMOS, in which a back gate potential is different from the potential of the p-type substrate, are integrated on the single p-type substrate. In the case of such a semiconductor integrated circuit device, a p-type well pn-separated from the p-type substrate is formed, and an NMOS, in which the back gate potential is different from the p-type substrate, is formed in the p-type well.
FIG. 72 is a sectional view of a semiconductor integrated circuit device having a p-type well which is pn-separated from a p-type substrate. FIGS. 73(A) through 73(E) are profile diagrams showing the distribution of an impurity in a substrate, wherein FIG. 73(A) shows a profile along line 73Axe2x80x9473A in FIG. 72, FIG. 73(B) showing a profile along line 73Bxe2x80x9473B in FIG. 72, FIG. 73(C) showing a profile along line 73Cxe2x80x9473C in FIG. 72, FIG. 73(D) showing a profile along line 73Dxe2x80x9473D in FIG. 72, and FIG. 73(E) showing a profile along line 73Exe2x80x9473E in FIG. 72.
However, in a process for producing a semiconductor integrated circuit device having a p-type well pn-separated from a p-type substrate, it is required to add a photolithography step of forming the p-type well pn-separated from the p-type substrate, to a typical process for producing a semiconductor integrated circuit device. Therefore, the number of masks for use in the photolithography step increases, so that the manufacturing costs increase.
As the prior art of the present invention, a method for producing the semiconductor integrated circuit device shown in FIG. 72 will be described below.
FIGS. 74(A) through 74(C), 75(A) through 75(C) and 76(A) and 76(B) are sectional views showing principal steps of producing the semiconductor integrated circuit device shown in FIG. 72.
First, as shown in FIG. 74(A), an element isolating region 102 is formed on the surface of a p-type silicon substrate 101 by the LOCOS method to define divided element regions 103 on the surface of the substrate 101. Then, the surface of the (silicon) substrate 101 exposed to the element regions 103 is, e.g., thermally oxidized, to form buffer oxide films 104 on the surfaces of the element regions 103. FIGS. 77(A) through 77(E) show impurity profiles in the substrate 101 after the buffer oxide films 4 are formed. FIG. 77(A) shows a profile along line 77Axe2x80x9477A in FIG. 74(A), FIG. 77(B) showing a profile along line 77Bxe2x80x9477B in FIG. 74(A), FIG. 77(C) showing a profile along line 77Cxe2x80x9477C in FIG. 74(A), FIG. 77(D) showing a profile along line 77Dxe2x80x9477D in FIG. 74(A), and FIG. 77(E) showing a profile along line 77Exe2x80x9477E in FIG. 74(A). As shown in FIGS. 77(A) through 77(E), after the buffer oxide films 4 are formed, the conductive impurities in the substrate 101 are only p-type impurities originally contained in the substrate 101.
Then, as shown in FIG. 74(B), a photoresist is applied on the substrate 101 to form a photoresist film 105. Then, holes 106a, 106b are formed in the photoresist film 105 by the photolithography method. The hole 106a is formed so as to correspond to a region wherein an n-type well is formed, and the hole 106b is annularly formed so as to surround a region wherein a pxe2x88x92-type well separated from the substrate 101 is formed. Then, using the photoresist film 105 as a mask, an n-type impurity 107 is ion-implanted into the substrate 101. Thus, an n-type well 108-1, and an n-type well 108-2 surrounding a region, in which the pxe2x88x92-type well separated from the substrate 101 is formed, are simultaneously formed. FIGS. 77(F) through 77(J) show impurity profiles in the substrate 1 after the n-type wells 108-1 and 108-2 are formed. FIG. 77(F) shows a profile along line 77Fxe2x80x9477F in FIG. 74(B), FIG. 77(G) showing a profile along line 77Gxe2x80x9477G in FIG. 74(B), FIG. 77(H) showing a profile along line 77Hxe2x80x9477H in FIG. 74(B), FIG. 77(I) showing a profile along line 77Ixe2x80x9477I in FIG. 74(B), and FIG. 77(J) showing a profile along line 77Jxe2x80x9477J in FIG. 74(B). As shown in FIGS. 77(F) through 77(J), the n-type impurity 107 is introduced so that the density thereof is higher than that of the p-type impurity originally contained in the substrate 101, to form the n-type wells 108-1 and 108-2 in the substrate 101.
Then, as shown in FIG. 74(C), after the photoresist film 105 is removed from the substrate 101, a photoresist is applied again to form a photoresist film 109. Then, a hole 110 is formed in the photoresist film 109 by the photolithography method. The hole 110 is formed so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed. Then, using the photoresist film 109 as a mask, an n-type impurity 111 is ion-implanted into the substrate 101. Thus, an embedded n-type well 112 apart from the surface of the substrate 101 is formed in a region surrounded by the n-type well 108-2 of the substrate 1. FIGS. 78(A) through 78(E) show impurity profiles in the substrate 101 after the n-type well 112 is formed. FIG. 78(A) shows a profile along line 78Axe2x80x9478A in FIG. 74(C), FIG. 78(B) showing a profile along line 78Bxe2x80x9478B in FIG. 74(C), FIG. 78(C) showing a profile along line 78Cxe2x80x9478C in FIG. 74(C), FIG. 78(D) showing a profile along line 78Dxe2x80x9478D in FIG. 74(C), and FIG. 78(E) showing a profile along line 78Exe2x80x9478E in FIG. 74(C). As shown in FIGS. 78(A) through 78(E), the n-type impurity 111 is introduced so that the density thereof is higher than that of the p-type impurity originally contained in the substrate 1, to form the embedded n-type well 112 in the substrate 101.
Then, as shown in FIG. 75(A), after the photoresist film 109 is removed from the substrate 101, a photoresist is applied again to form a photoresist film 113 thereon. Then, holes 114-1 and 114-2 are formed in the photoresist film 113 by the photolithography method. The hole 114-1 is formed so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed, and the hole 114-2 is formed so as to correspond to a region wherein pxe2x88x92-type well pn-separated from the substrate 101 is formed. Then, using the photoresist film 113 as a mask, a p-type impurity 115 is ion-implanted into the substrate 101. Thus, a pxe2x88x92-type well 116-1 is formed in the substrate 101, and a pxe2x88x92-type well 116-2 is formed in a region surrounded by the n-type well 108-2 of the substrate 101. The pxe2x88x92-type well 116-1 is connected to the substrate 101, and the pxe2x88x92-type well 116-2 is pn-separated from the substrate 101. FIGS. 78(F) through 78(J) show impurity profiles in the substrate 1 after the pxe2x88x92-type wells 116-1 and 116-2 are formed. FIG. 78(F) shows a profile along line 78Fxe2x80x9478F in FIG. 75(A), FIG. 78(G) showing a profile along line 78Gxe2x80x9478G in FIG. 75(A), FIG. 78(H) showing a profile along line 78Hxe2x80x9478H in FIG. 75(A), FIG. 78(I) showing a profile along line 78Ixe2x80x9478I in FIG. 75(A), and FIG. 78(J) showing a profile along line 78Jxe2x80x9478J in FIG. 75(A). As shown in FIGS. 78(F) through 78(J), the p-type wells 116-1 and 116-2 are formed by adding the p-type impurity to the originally p-type substrate 101, so that the p-type wells 116-1 and 116-2 have a higher density of p-type impurity than that of the substrate 101.
Then, as shown in FIG. 75(B), the photoresist film 113 is removed from the substrate 101.
Then, as shown in FIG. 75(C), the buffer oxide films 4 are removed. Thus, the surface of the substrate 101 (the surface of each of the n-type well 108-1 and the pxe2x88x92-type wells 116-1, 116-2 in this embodiment) is exposed to the element regions 103.
Then, as shown in FIG. 76(A), the surface of the substrate 101 exposed to the element regions 3 is thermally oxidized to form a gate oxide film 117.
Then, as shown in FIG. 76(B), a conductive film serving as a gate electrode of a transistor, e.g., a laminated film of a polycrystalline silicon and tungsten silicide film, is formed on the structure shown in FIG. 76(A). Then, the laminated film is patterned to form a gate electrode 118. Then, in accordance with a well-known method, a p-type impurity for forming a p-type source/drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, in accordance with a well-known method, an n-type impurity for forming an n-type source/drain is ion-implanted into the pxe2x88x92-type wells 116-1 and 116-2 to form n-type source regions 120S-1, 120S-2 and n-type drain regions 120D-1, 120D-2.
Then, as shown in FIG. 72, an interlayer insulator film 121 of, e.g., a CVD oxide film, is formed on the structure shown in FIG. 76(B). Then, contact holes 122, which are communicated with the p-type source/drain regions 119S, 119D and the n-type source/drain regions 120S-1, 120D-1, 120S-2, 120D-2, respectively, are formed in the interlayer insulator film 121. Then, a conductive film serving as a wiring, e.g., an aluminum film, is formed. The aluminum film thus formed is patterned to form a wiring 123.
In such a producing method, it is required to carry out a photolithography step when the n-type wells 108-1 and 108-2 are formed (FIG. 74(B)), when the n-type well 112 is formed (FIG. 74(C)), and when pxe2x88x92-type wells 116-1 and 116-2 are formed (FIG. 75(A)). In particular, the step of forming the n-type well 112 shown in FIG. 74(C) is peculiar to the semiconductor integrated circuit device shown in FIG. 72. For that reason, when the semiconductor integrated circuit device shown in FIG. 72 is produced, the number of photolithography steps increases, and the number of masks for use in the photolithography steps increases. Therefore, the manufacturing costs increase in comparison with usual semiconductor integrated circuit devices.
In order to reduce the cost of producing the semiconductor integrated circuit device shown in FIG. 72, there is another producing method as follows.
FIG. 79 is a sectional view of a semiconductor integrated circuit device produced by another producing method. FIGS. 80(A) through 80(D) are profile diagrams showing the distribution of an impurity in a substrate. FIGS. 80(A) through 80(D) are profile diagrams showing the distribution of an impurity in a substrate, wherein FIG. 80(A) shows a profile along line 80Axe2x80x9480A in FIG. 79, FIG. 80(B) showing a profile along line 80Bxe2x80x9480B in FIG. 79, FIG. 80(C) showing a profile along line 80Cxe2x80x9480C in FIG. 79, and FIG. 80(D) showing a profile along line 80Dxe2x80x9480D in FIG. 79.
This producing method will be described below.
FIGS. 81(A) through 81(C), 82(A) and 82(B), and 83(A) and 83(B) are sectional views showing principal steps of producing the semiconductor integrated circuit device shown in FIG. 79.
First, as shown in FIG. 81(A), the surface of a p-type silicon substrate 101 is, e.g., thermally oxidized, to form a buffer oxide film 104 on the surface of the substrate 101. Then, a photoresist is applied on the buffer oxide film 104 to form a photoresist film 105. Then, holes 106a, 106b are formed in the photoresist film 105 by the photolithography method. The hole 106a is arranged so as to correspond to a region wherein an n-type well is formed, and the hole 106b is arranged so as to correspond to a region wherein a pxe2x88x92-type well separated from the substrate 101 is formed. Then, using the photoresist film 105 as a mask, an n-type impurity 107 is ion-implanted into the substrate 101. Thus, an n-type impurity injecting regions 108-1, and 108-2 are obtained. FIGS. 84(A) through 84(D) show impurity profiles in the substrate 101 after the n-type impurity 107 is ion-implanted. FIG. 84(A) shows a profile along line 84Axe2x80x9484A in FIG. 81(A), FIG. 84(B) showing a profile along line 84Bxe2x80x9484B in FIG. 81(A), FIG. 84(C) showing a profile along line 84Cxe2x80x9484C in FIG. 81(A), and FIG. 84(D) showing a profile along line 84Dxe2x80x9484D in FIG. 81(A). As shown in FIGS. 84(A) through 84(D), the n-type impurity 107 is injected so that the density thereof is higher than the density of the p-type impurity originally contained in the substrate 101.
Then, as shown in FIG. 81(B), after the photoresist film 105 is removed, a photoresist is applied again to form a photoresist film 113. Then, holes 114-1, 114-2 are formed in the photoresist film 113 by the photolithography method. The hole 114-1 is arranged so as to correspond to a region wherein a pxe2x88x92-type well connected to the substrate 101 is formed, and the hole 114-2 is arranged so as to correspond to a region wherein a pxe2x88x92-type well pn-separated from the substrate 101 is formed. Then, using the photoresist film 113 as a mask, a p-type impurity 115 is ion-implanted into the substrate 101 and the injecting region 108-2. Thus, p-type impurity injecting regions 116-1, 116-2 are obtained. FIGS. 84(E) through 84(H) show impurity profiles in the substrate 101 after the p-type impurity 115 is ion-implanted. FIG. 84(E) shows a profile along line 84Exe2x80x9484E in FIG. 81(B), FIG. 84(F) showing a profile along line 84Fxe2x80x9484F in FIG. 81(B), FIG. 84(G) showing a profile along line 84Gxe2x80x9484G in FIG. 81(B), and FIG. 84(H) showing a profile along line 84Hxe2x80x9484H in FIG. 81(B). As shown in FIGS. 84(E) through 84(H), the p-type impurity 115 is injected so as to have a higher density and shallower than the n-type impurity 107 contained in the injecting region 108-2.
Then, as shown in FIG. 81(C), the photoresist film 113 is removed. Then, heat treatment is carried out to diffuse/activate the n-type impurity of the injecting regions 108-1, 108-2 and the p-type impurity of the injecting regions 116-1, 116-2. Thus, the injecting regions 108-1, 108-2 become n-type wells 108-1, 108-2, respectively, and the injecting regions 116-1, 116-2 become pxe2x88x92-type wells 116-1, 116-2, respectively. FIGS. 84(I) through 84(L) show impurity profiles in the substrate 101 after the heat treatment is carried out. FIG. 84(I) shows a profile along line 84Ixe2x80x9484I in FIG. 81(C), FIG. 84(J) showing a profile along line 84Jxe2x80x9484J in FIG. 81(C), FIG. 84(K) showing a profile along line 84Kxe2x80x9484K in FIG. 81(C), and FIG. 84(L) showing a profile along line 84Lxe2x80x9484L in FIG. 81(C). As shown in FIG. 84(I) through 84(L), the p-type well 116-2 is particularly formed only in the n-type well 108-2 and pn-separated from the substrate 101.
Then, as shown in FIG. 82(A), an element isolating region 102 is formed on the surface of the substrate 101 to define divided element regions 103.
Then, as shown in FIG. 82(B), the buffer oxide film 4 is removed. Thus, the surface of the substrate 101 (the surface of each of the n-type well 108-1 and the pxe2x88x92-type wells 116-1, 116-2 in this embodiment) is exposed to the element regions 103.
Then, as shown in FIG. 83(A), the surface of the substrate 101 exposed to the element regions 3 is thermally oxidized to form a gate oxide film 117.
Then, as shown in FIG. 83(B), a conductive film serving as a gate electrode of a transistor, e.g., a laminated film of a polycrystalline silicon and tungsten silicide film, is formed on the structure shown in FIG. 83(A). Then, the laminated film is patterned to form a gate electrode 118. Then, in accordance with a well-known method, a p-type impurity for forming a p-type source/drain is ion-implanted into the n-type well 108-1 to form a p-type source region 119S and a p-type drain region 119D. Then, in accordance with a well-known method, an n-type impurity for forming an n-type source/drain is ion-implanted into the pxe2x88x92-type wells 116-1 and 116-2 to form n-type source regions 120S-1, 120S-2, 120D-1, 120D-2.
Then, as shown in FIG. 79, an interlayer insulator film 121 of, e.g., a CVD oxide film, is formed on the structure shown in FIG. 83(B). Then, contact holes 122, which are communicated with the p-type source/drain regions 119S, 119D and the n-type source/drain regions 120S-1, 120D-1, 120S-2, 120D-2, respectively, are formed in the interlayer insulator film 121. Then, a conductive film serving as a wiring, e.g., an aluminum film, is formed. The aluminum film thus formed is patterned to form a wiring 123.
According to such another producing method, the n-type well 108-1, the pxe2x88x92-type well 116-1 connected to the substrate 101, and the pxe2x88x92-type well 116-2 pn-separated from the substrate 102 can be formed by two photolithography steps shown in FIGS. 81(A) and 81(B). Therefore, it is possible to reduce the number of photolithography steps and the number of masks for use in photolithography steps.
However, in order to form the pxe2x88x92-type well 116-2 in the n-type well 108-2, the dose of the p-type impurity 115 injected in the step shown in FIG. 81(B) must be set to be higher than the impurity density of then-type well 108-2. That is,the amount of the p-type impurity 115 for forming the pxe2x88x92-type wells 116-1, 116-2 is rate-controlled by the impurity density of the n-type well 108-2. Therefore, there is no degree of freedom in the setting of the impurity density of the pxe2x88x92-type wells 116-1 and 116-2.
In addition, although the gate insulator film of a typical semiconductor integrated circuit device usually has one thickness, some of semiconductor integrated circuit devices have various gate insulator films having different thickness. A device of this type is used as, e.g., a semiconductor integrated circuit device wherein a plurality of potentials are applied to a gate of a MOSFET, or the like.
In such a semiconductor integrated circuit device, it is required to carry out a photolithography step in order to obtain various gate insulator films having different thickness. Therefore, the number of masks for use in the photolithography step increases, and the manufacturing costs increase as described above.
As described above, in a semiconductor integrated circuit device having an n-type well, a p-type well connected to a substrate, and a p-type pn-separated from the substrate, there is a problem in that the number of photolithography steps increases and the manufacturing costs increase.
In addition, although there is a method for producing a semiconductor integrated circuit device of this type without increasing the number of photolithography steps, there is a problem in that this method is difficult to freely set the impurity density of a p-type well.
Moreover, in a semiconductor integrated circuit device having various gate insulator films having different thickness, there is a problem in that the number of photolithography steps increases and the manufacturing costs increase.
By the way, most of semiconductor integrated circuits comprise different kinds of transistors. For example, a non-volatile semiconductor memory device, wherein a high voltage must be applied in the writing/erasing in a memory cell, uses a high-voltage transistor, to which a high voltage is applied, in addition to a low-voltage transistor for use in a logic circuit. The high-voltage transistor needs an element region having a lower impurity density than that of an element region for the low-voltage transistor, because of limitations of junction resistance and substrate bias characteristics.
Therefore, for example, when a p-type semiconductor substrate is used, a low-voltage n-channel MOS transistor and a low-voltage p-channel MOS transistor are formed in p-type and n-type wells formed by ion implantation, respectively, and a high-voltage n-channel MOS transistor is formed by using the p-type substrate, in which no well is formed, as an element region as it is.
When the p-type semiconductor substrate is used, the p-type and n-type wells are usually formed by ion implantation after forming an element isolating insulator film. In addition, the circuit region of the high-voltage transistor has a lower impurity density than that of the well region, so that it needs to have a p-type element isolating layer below the element isolating insulator film in order to insure element isolation. The applicant has proposed a technique for forming a p-type element isolating layer, which serves to isolate a high-voltage transistor, at the same time that the ion implantation step for forming the p-type well for a low-voltage transistor is carried out (Japanese Patent Application No. 9-44243).
FIG. 97 shows an example that low-voltage p-channel MOS transistors QP1, QP2, low-voltage n-channel MOS transistors QN1, QN2, and high-voltage n-channel MOS transistors QN3, QN4 are formed on a pxe2x88x92-type silicon substrate 1 by a conventional method. An element isolating insulator film 202 is formed by, e.g., the shallow trench isolation (STI) technique, before forming an n-type well 203 and a p-type well 204. That is, a groove is formed in the substrate 201, and the element isolating insulator film 202 is embedded in the groove by the CVD.
After forming the element isolating insulator film 202, ion implantation is carried out to sequentially form the n-type well and the p-type well 204. Directly below the element isolating film 202 adjacent to the high-voltage transistors QN3 and QN4, a p-type element isolating layer 205 is formed by ion implantation simultaneously with the ion implantation process for the p-type well 204.
FIG. 98 shows the ion implantation process for the p-type well 204 and the p-type element isolating layer 205 after forming the element isolating insulator film 202. As shown in the drawing, a resist mask 206 having openings 207a, 207b is patterned in a region wherein the p-type well 204 and the p-type element isolating layer 205 should be formed, by the lithography, and ion implantation is carried out. Since this ion implantation serves to form an impurity layer more deeply than the bottom of the element isolating insulator film 202, ion implantation at a high acceleration voltage is utilized.
As described above, in a conventional method for simultaneously forming a p-type well for a low-voltage transistor circuit and a p-type element isolating layer in a high-voltage transistor circuit region having a lower impurity density than that of the p-type well for the low-voltage transistor circuit after forming an element isolating insulator film, there is the following problem.
As shown in FIG. 98, the ion implantation for the p-type well 204 is carried out via the wide opening 207a including the element region for the n-channel MOS transistors QN1, QN2 and the element isolating region adjacent thereto, whereas the ion implantation for the p-type element isolating layer 205 in the element isolating region adjacent to the high-voltage n-channel MOS transistors QN3, QN4 is carried out via the narrow opening 207b. However, there is usually a step between the element isolating insulator film 202 and the substrate surface of the element region. Because the STI technique carries out the formation of a groove and the embedding of an element isolating insulator film while an element region is covered with a mask (not shown) of a silicon nitride film or the like, and then, removes the mask from the element region. Since such a step exists, it is not easy to form the resist mask 206 having the fine opening 207b at the lithography step.
In addition, in the method for carrying out ion implantation after forming the element isolating insulator film 202, the thickness of the resist must be great in order to obtain a sufficient mask effect for ion implantation since a high acceleration voltage is used. Thus, it is difficult to form the fine opening using the lithography. For these reasons, it is difficult to provide excellent element isolation characteristics in a low impurity density region when the element is scaled down.
Moreover, in the conventional method for forming the well after forming the element isolating insulator film 202, the depths of the element region and element isolating region in the p-type well 204 and n-type well 203 are different from each other as shown in FIGS. 97 and 98. This difference in depth corresponds to the height of the element isolating insulator film 202 projecting from the substrate surface of the element region. Therefore, the lateral resistance of the well increases by the substantial decrease of the thickness of the well in the element isolating region. Consequently, it is difficult to provide a constant potential in the whole well.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor integrated circuit device, which has a well having a conductive type different from that of a substrate, a well having the same conductive type as that of the substrate and being connected to the substrate, and a well having the same conductive type as that of the substrate and being pn-separated from the substrate and which can inhibit the increase of the number of photolithography steps and reduce the manufacturing costs while maintaining the advantage of capable of freely setting the impurity density of wells having the same conductive type as that of the substrate, and a method for producing the same.
It is another object of the present invention to provide a semiconductor integrated circuit device which has various gate insulator films having different thickness and which can suppress the increase of the number of photolithography steps and reduce the manufacturing costs, and a method for producing the same.
It is a further object of the present invention to provide a semiconductor integrated circuit device, which has a well having a conductive type different from that of a substrate, a well having the same conductive type as that of the substrate and being connected to the substrate, a well having the same conductive type as that of the substrate and being pn-separated from the substrate, and various gate insulator films having different thickness and which can inhibit the increase of the number of photolithography steps and reduce the manufacturing costs while maintaining the advantage of capable of freely setting the impurity density of wells having the same conductive type as that of the substrate, and a method for producing the same.
It is a still further object of the present invention to provide a semiconductor integrated circuit device having good element isolating characteristics, and a method for producing the same.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate of a first conductive type; a first semiconductor region which is formed on the semiconductor substrate and which includes an impurity of a second conductive type; a second annular semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a third embedded semiconductor region which is formed in a region surrounded by the second annular semiconductor region and which includes an impurity of the second conductive type; a fourth embedded semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a fifth semiconductor region which is formed above the third embedded semiconductor region and which includes an impurity of the first conductive type; a sixth semiconductor region which is formed above the fourth embedded semiconductor region and which includes an impurity of the first conductive type; and a transistor formed in the first, fifth and sixth semiconductor regions.
In the semiconductor integrated circuit device with the above described construction, the fourth embedded semiconductor region including the impurity of the second conductive type is arranged below the sixth preferred embodiment including the impurity of the first conductive type. Consequently, the mask used for introducing the impurity of the first conductive type for forming the fifth and sixth semiconductor regions can be in common with the mask used for introducing the impurity of the second conductive type for forming the third and fourth embedded semiconductor regions. Therefore, in the semiconductor integrated circuit device having the well (the first semiconductor region) having different conductive type from that of the substrate, the well (the sixth semiconductor region) which has the same conductive type as that of the substrate and which is connected to the substrate, the well (the fifth semiconductor region) which has the same conductive type as that of the substrate and which is pn-separated from the substrate, it is possible to suppress the increase the number of photolithography steps.
In addition, the fifth semiconductor region of the first conductive type is formed above the third semiconductor region of the second conductive type so as to correspond to the region surrounded by the second annular semiconductor region of the second conductive type. Consequently, the impurity density can be freely set without being under the influence of the semiconductor region of the second conductive type. Therefore, it is possible to maintain the advantage in that the impurity density of the well (the fifth and sixth semiconductor regions) of the same conductive type as that of the substrate can be freely set.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: preparing a semiconductor substrate of a first conductive type; introducing an impurity of a second conductive type, which serves to form a first semiconductor region of the second conductive type and a second annular semiconductor region of the second conductive type, into the semiconductor substrate using a first mask; introducing an impurity of the second conductive type, which serves to form third and fourth embedded semiconductor regions of the second conductive type, into the semiconductor substrate and a region surrounded by the second annular semiconductor region using a second mask; introducing an impurity of the first conductive type, which serves to form fifth and sixth semiconductor regions of the first conductive type, into regions above the third and fourth semiconductor regions using the second mask; and forming a transistor in the first, fifth and sixth semiconductor regions.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate using a second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
In the above described method for producing the semiconductor integrated circuit device, the same mask (the second mask) is used for introducing the second impurity for forming the second semiconductor region and for removing the first gate insulator film. Therefore, in the semiconductor integrated circuit device having various gate insulator films having different thickness, it is possible to suppress the increase of the number of photolithography steps.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate and a region, into which the first impurity has been introduced, using a second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate; introducing a first impurity, which serves to form a first semiconductor region, into the semiconductor substrate using a first mask; introducing a second impurity, which serves to form a second semiconductor region, into the semiconductor substrate using a second mask; introducing a third impurity, which serves to form a third semiconductor region, into the semiconductor substrate, a region, into which the first impurity has been introduced, and a region, into which the second impurity has been introduced, using a third mask; removing the first gate insulator film using the third mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming a first gate insulator film on a semiconductor substrate of a first conductive type; introducing a first impurity of a second conductive type, which serves to form a first semiconductor region of the second conductive type and a second annular semiconductor region of the second conductive type, into the semiconductor substrate using a first mask; introducing a second impurity of the second conductive type, which serves to form third, fourth and fifth embedded semiconductor regions of the second conductive type, into the semiconductor substrate, a region surrounded by the second annular semiconductor region, and a region, into which the first impurity has been introduced, using a second mask; introducing a third impurity of the first conductive type, which serves to form sixth, seventh and eighth semiconductor regions of the first conductive type, into regions above the third, fourth and fifth semiconductor regions, using the second mask; removing the first gate insulator film using the second mask; forming a second gate insulator film in a portion, from which the first gate insulator film has been removed, and increasing the thickness of a portion of the first gate insulator film, in which the first gate insulator film has been left; and forming a transistor using the first gate insulator film, and a transistor using the second gate insulator film.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises; a first gate insulator film formed on a semiconductor substrate of a first conductive type; a first semiconductor region which is formed on the semiconductor substrate and which includes an impurity of a second conductive type; a second annular semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a third embedded semiconductor region which is formed on the semiconductor substrate and which includes an impurity of the second conductive type; a fourth embedded semiconductor region which is formed in a region surrounded by the second annular semiconductor region and which includes an impurity of the second conductive type; a fifth embedded semiconductor region which is formed in the first semiconductor region and which includes an impurity of the second conductive type; a sixth semiconductor region which is formed above the third semiconductor region and which includes an impurity of the first conductive type; a seventh semiconductor region which is formed above the fourth embedded semiconductor region and which includes an impurity of the first conductive type; an eighth semiconductor region which is formed above the fifth embedded semiconductor region and which includes an impurity of the first conductive type; a second gate insulator film which is thinner than the first gate insulator film formed in the sixth, seventh and eighth semiconductor regions; a transistor using the first gate insulator film; and a transistor using the second gate insulator film.
In the semiconductor integrated circuit device with the above described construction, the third, fourth and fifth embedded semiconductor regions of the second conductive type are arranged below the sixth, seventh and eighth semiconductor regions. In addition, the second gate insulator film, which is thinner than the first gate insulator film, is arranged in the sixth, seventh and eighth semiconductor regions. Consequently, the mask used for introducing the impurity of the first conductive type for forming the sixth, seventh and eighth semiconductor regions, the mask used for introducing the impurity of the second conductive type for forming the third, fourth and fifth embedded semiconductor regions, and the mask used for removing the first gate insulator film can be in common with each other. Therefore, in the semiconductor integrated circuit device having the well (the eighth semiconductor region) of different conductive type from that of the substrate, the well (the sixth semiconductor region) which has the same conductive type as that of the substrate and which is connected to the substrate, the well (the seventh semiconductor region) which has the same conductive type as that of the substrate and which is pn-separated from the substrate, and various gate insulator films having different thickness, it is possible to suppress the increase of the number of photolithography steps.
According to another aspect of the present invention, a semiconductor integrated circuit device comprises: a semiconductor substrate; a first element region of a first conductive type defined in the semiconductor substrate by an element isolating insulator film; a second element region of the first conductive type defined in the semiconductor substrate by the element isolating insulator film, the second element region having a lower impurity density than that of the first element region; first and second transistors of a second conductive channel formed in the first and second element regions, respectively; and an element isolating layer of the first conductive type formed below an element isolating insulator film adjacent to the second element region of the semiconductor substrate, the element isolating layer having an impurity density substantially equal to that of the first element region and a depth substantially equal to that of the first element region from the substrate surface of the first and second element regions.
In this semiconductor integrated circuit device, the semiconductor substrate may have the first conductive type, the first element region may be defined, by the element isolating insulator film, in a first conductive type well formed by ion implantation before forming the element isolating insulator film, and the element isolating layer may be formed at the same time that an ion implantation step of forming the first conductive type well is carried out.
In this semiconductor integrated circuit device, the element isolating insulator film may be embedded in a groove formed in the semiconductor substrate.
In this semiconductor integrated circuit device, a third element region of a second conductive type defined by the element isolating insulator film may be formed in the semiconductor substrate, and a transistor of a first conductive channel may be formed in the third element region.
According to a further aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising the steps of: forming an ion implantation mask having an opening in first, second and fourth predetermined regions of a semiconductor substrate, among the first predetermined region serving to form therein a first element region of a first conductive type, the second predetermined region serving to form therein an element isolating region adjacent to the first element region, a third predetermined region of the first conductive type serving to form therein a second element region having a lower impurity density than that of the first element region, and the fourth predetermined region serving to form therein an element isolating region adjacent to the second element region; ion-implanting an impurity into the semiconductor substrate via the opening of the ion implantation mask to simultaneously form a first conductive type well in the first element region and the element isolating region adjacent thereto, and an element isolating layer of the first conductive type in the element isolating region adjacent to the second element region; forming an element isolating insulator film in the element isolating region of the semiconductor substrate; and forming first and second transistors of a second conductive channel in the first and second element regions, respectively.
In this producing method, the semiconductor substrate may have the first conductive type, and the step of forming the first conductive type well and the element isolating layer may ion-implant an impurity of the first conductive type more deeply than a bottom of the element isolating insulator film formed thereafter.
According to a still further aspect of the present invention, there is provided a method for producing a semiconductor integrated circuit device, the method comprising: a step of forming a first ion implantation mask having an opening in first, second and fourth predetermined regions of a semiconductor substrate, among the first predetermined region serving to form therein a first element region of a first conductive type, the second predetermined region serving to form therein an element isolating region adjacent to the first element region, a third predetermined region of the first conductive type serving to form therein a second element region having a lower impurity density than that of the first element region, and the fourth predetermined region serving to form therein an element isolating region adjacent to the second element region; a first ion implantation step of ion-implanting an impurity into the semiconductor substrate via the opening of the first ion implantation mask to simultaneously form a first conductive type well in the first element region and the element isolating region adjacent thereto, and an element isolating layer of the first conductive type in the element isolating region adjacent to the second element region; a step of forming a second ion implantation mask having an opening in the third predetermined region of the semiconductor substrate; a second ion implantation step of ion-implanting a first conductive type impurity into the semiconductor substrate via the opening of the second ion implantation mask, at a lower dose than that of the impurity in the first ion implantation step, and more shallowly than the impurity in the first ion implantation step; a step of forming an element isolating insulator film in the element isolating region of the semiconductor substrate; and a step of forming first and second transistors of a second conductive channel in the first and second element regions, respectively.
In this producing method, the first ion implantation step may ion-implant the impurity of the first conductive type more deeply than a bottom of the element isolating insulator film formed thereafter, and the second ion implantation step is a channel ion implantation for controlling a threshold of the second transistor.
In this producing method, the step of forming the element isolating insulator film may have a step of forming a groove in the semiconductor substrate and a step of embedding an element isolating insulator film in the groove.
This producing method may further comprise the steps of: forming an ion implantation mask having an opening in a fifth predetermined region serving to form therein a third element region of a second conductive type and a sixth predetermined region serving to form therein an element isolating region adjacent to the third element region, before forming the element isolating insulator film; ion-implanting a second conductive type impurity into the semiconductor substrate via the opening of the ion implantation mask to form a second conductive type well in the third element region and the element isolating region adjacent thereto; and forming a transistor of a first conductive channel in the second conductive type well after forming the element isolating insulator film.
According to the present invention, the first and second transistors are formed in the first and second element regions which have the same first conductive type and different impurity density, respectively, whereas the element isolating layer of the first conductive type formed in the element isolating region adjacent to the second transistor formed in the second element region of the low impurity density has substantially the same impurity density as that of the first element region, in which the first transistor is formed, and has substantially the same depth from the substrate surface of the element region as that the first element region.
Specifically, this structure is obtained by forming the element isolating layer of the first conductive type in the element isolating region adjacent to the second element region at the same time that the ion implantation step of forming the well of the first conductive type in the region including the first element region is carried out, before forming the element isolating insulator film in the semiconductor substrate. Thus, the second transistor formed in the region of the low impurity density has excellent element isolation characteristics.
In addition, according to the present invention, since the ion implantation for the well of the first conductive type and the element isolating layer of the first conductive type is carried out before forming the element isolating insulator film, there is no step when the ion implantation mask is patterned by the resist. In addition, the thickness of the resist must not be so great unlike the ion implantation carried out after forming the element isolating insulator film. Therefore, it is possible to easily pattern the resist having the fine opening, and it is possible to surely form the element isolating layer in a narrow region via the obtained fine opening.

Semiconductor integrated circuit device with high and low voltage wells

Abstract: Alternatively, low-voltage n-channel MOS transistors QN1, QN2 and low-voltage p-channel MOS transistors QP1, QP2 are formed in a p-type well 214 and n-type well 213 of a pxe2x88x92-type silicon substrate 211, respectively, and high-voltage n-channel MOS transistors QN3, QN4 are formed in the substrate 211. The p-type well 214, in which the transistors QN1, QN2 are formed, and the p-type element isolating layer 215 of the element isolating regions for the transistors QN3, QN4 are simultaneously formed by ion implantation using a resist mask by the lithography on a flat surface having no step. The p-type well 214 and the p-type element isolating layer 215 have the same depth from the substrate surface of the element regions and the same impurity density. Thus, it is possible to provide a semiconductor integrated circuit device capable of achieving good element isolation characteristics, and a method for producing the same.


A method of identifying problems in a speech recognition application is provided and includes the step of obtaining a speech application call log containing log data on question-answer (QA) states and transitions. Then, in accordance with the method, for each of a multiple transitions between states, a parameter is generated which is indicative of a gain in a success rate of the speech recognition application if all calls passing through the transition passed instead through other transitions. In exemplary embodiments, the parameter is an Arc Cut Gain in Success Rate (ACGSR) parameter. Methods of generating the ACGSR, as well as systems and tools for aiding developers are also disclosed.

The present invention generally pertains to speech recognition applications and systems. More specifically, the present invention pertains to methods of identifying and analyzing performance problems during development of speech recognition applications.
Although great progress has been made in speech recognition technology during the past two decades, adoption of speech technology has not gone as smoothly as might be desired. This is evidenced by the relatively limited deployment of speech applications. The main barrier to wider adoption of speech recognition technology stems from the cost incurred in developing the speech applications. A typical speech application includes application logic, dialog, one or more grammars, a speech recognition engine, etc. Since it is unlikely that the system will be available right at the very beginning (i.e., without significant development), constructing a quality speech application usually involves four steps, namely, (1) design; (2) prototyping; (3) evaluation and tuning; and (4) deployment. Typically, the prototyping step and the evaluation and tuning step are performed iteratively, fine tuning the speech application through each iteration to improve performance.
Among these four steps, evaluation and tuning during test and pilot stages is one of the most important phases and usually costs most. The tuning phase can take many months and requires a team of developers, testers, and speech technology experts.
Significant efforts have been directed toward the goal of reducing the total cost needed to develop and deploy speech applications. For example, a series of development tools have recently been released by companies working in speech recognition. The development tools significantly improved the development process. However, some critical functionality is not available in these tools. For instance, speech application authors usually don't know what to do when the success rate of their application is not satisfactory, even though they have access to large quantities of application logs. It would therefore be very valuable to automatically (or semi-automatically) determine what callers are struggling with, or which parts of their application need the most work.
The present invention provides solutions to one or more of the above-described problems and/or provides other advantages over the prior art.

Method of automatically ranking speech dialog states and transitions to aid in performance analysis in speech applications


A sliding door handle and strike assembly includes a locking member for engaging the strike to prevent the door from opening. The locking member is biased to an unlocked position, until it is moved into a locking position, in which magnetic co-operation acts to hold the locking member in the locking position.

Door handles for sliding doors are generally well known in the art. However, for sliding door handles and particularly interior latching sliding doors handles operated via a snib, it is common that the latch and/or strike can be damaged if the latch/snib is moved into a locked position (while the door is open), and then the door is closed (or slammed) on to the latch mechanism.
Further, it is considered desirable for such door hardware to be aesthetically pleasing, and this often means that door hardware should be simple, sleek, and not adorned with multiple obtrusive functional features that may detract from the aesthetic of the hardware.
It is an object of the present invention to provide an improved sliding door latch that will ameliorate one or more of the abovementioned disadvantages or that will at least provide the public with a useful choice.


A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

A variety of analog to digital converter circuits are known. Analog to digital converter circuits ("ND circuit" or "ADC") are used to convert analog signals to digital signals. In other words, analog electrical signals that vary continuously are converted by analog to digital converter circuits into digital signals. Digital signals, in contrast to analog signals that vary continuously, vary by stepping from one level to another. Analog to digital converter circuits are applied in a variety of applications, for example, when trying to convert an analog signal into a signal that a digital processor can read and understand. In one example, power supplies can be made to provide power to other electronics in a variety of forms. In one such form, power supplies provide power in the form of direct current ("DC") power. In such a power supply, a power output is generally constant at a particular voltage, for example, 5 volts.
Many such power supplies include feedback loops to help determine whether the output provided by the power supply is the expected output. A typical feedback system includes a sensor to sense the output of the power supply and a circuit to determine whether the output is within a given range as expected to be provided by the power supply. For power supplies with digital controllers, the signals indicating variance from the expected power output need to be changed from analog signals to digital signals such that the digital controllers can understand and react to correct the output of the digital power supply. Various types of analog to digital circuits for doing this conversion from an analog error signal to a digital signal readable by a digital controller are known and have been applied in such power supplies.
One such analog to digital conversion circuit is known as a flash analog to digital converter circuit or "flash ADC". Flash ADCs are generally characterized by having a very fast response time and being relatively simple to construct. Flash ADCs, however, lack sufficient resolution for high quality or highly precise power supplies. For example, in order to obtain a resolution suitable for certain precision power supplies, a flash ADC would have to include hundreds of comparator circuit elements. Such circuit sizes are undesirable because the circuit consumes too much power and space.
Another example analog to digital converter circuit used with a digital controller includes high resolution analog to digital converter circuits such as a delta sigma ADC circuit. Such circuits provide much improved resolution over flash ADC circuits. High resolution circuits, however, operate much too slowly to provide the necessary near-instant feedback necessary for maintaining a constant output power from a digitally controlled power supply.

Hybrid analog to digital converter circuit and method


Structures and methods for tissue engineering include a multicellular body including a plurality of living cells. A plurality of multicellular bodies can be arranged in a pattern and allowed to fuse to form an engineered tissue. The arrangement can include filler bodies including a biocompatible material that resists migration and ingrowth of cells from the multicellular bodies and that is resistant to adherence of cells to it. Three-dimensional constructs can be assembled by printing or otherwise stacking the multicellular bodies and filler bodies such that there is direct contact between adjoining multicellular bodies, suitably along a contact area that has a substantial length. The direct contact between the multicellular bodies promotes efficient and reliable fusion. The increased contact area between adjoining multicellular bodies also promotes efficient and reliable fusion. Methods of producing multicellular bodies having characteristics that facilitate assembly of the three-dimensional constructs are also provided.

Tissue engineering provides promising solutions to problems caused by the growing demand for organ and tissue replacement coupled with a chronic shortage of transplantable organs, including blood vessels. In the United States, for example, thousands of people are on the national waiting list for organ transplants. Many will likely perish for lack of replacement blood vessels for diseased arteries or veins or replacement abdominal organs. To lessen and eventually solve the problem of inadequate supply of blood vessels and organs for transplantation, tissue engineers strive to build and grow transplantable blood vessels, blood vessel substitutes, organs, or organ substitutes in a laboratory, with high precision, on large scale, and in a relatively short amount of time.
A variety of methods to build engineered tissues have been attempted and developed with limited success. However, assembly of vascularized three-dimensional organs has not been accomplished.
Prior art solutions, though promising, have presented a number of challenges. Scaffold choice, immunogenicity, degradation rate, toxicity of degradation products, host inflammatory responses, fibrous tissue formation due to scaffold degradation, and mechanical mismatch with the surrounding tissue may affect the long term behavior of the engineered tissue construct and directly interfere with its primary biological function. For example, myocardial tissue requires high cell density to assure synchronous beating through gap junctions that tightly interconnect neighboring cells. The use of scaffolds in cardiac tissue engineering has been associated with reduced cell-to-cell connection, as well as incorrect deposition and alignment of extracellular matrix (ECM; e.g., collagen and elastin), affecting scaffold biodegradation and the force-generating ability of myocardial constructs. ECM-related factors are also particularly critical in vascular tissue engineering. Largely for this reason the promise of a scaffold-engineered small-diameter blood vessel substitute with mechanical strength comparable to native vessels for adult arterial revascularization, often described as the "holy grail" of tissue-engineering, remains unfulfilled. Besides the recurrent difficulty of producing elastic fibers in vitro, the use of scaffolds presents additional problems. The inherent weakness of the gels may hinder the final strength of the tissue-engineered vessel. In addition, the presence of residual polymer fragments can disrupt the normal organization of the vascular wall and even influence smooth muscle cell (SMC) phenotype. Therefore it is not surprising that the first clinical applications of tissue-engineered vascular grafts have either targeted low-pressure applications or relied on an entirely scaffold-free method termed sheet-based tissue-engineering.
Organ printing, especially the technique described in U.S. patent application Ser. No. 10/590,446, has shown promise for producing three-dimensional tissues. Organ printing is generally a computer-aided, dispenser-based, three-dimensional tissue-engineering technology aimed at constructing functional organ modules and eventually entire organs layer-by-layer. In the technology described in U.S. patent application Ser. No. 10/590,446, individual multicellular aggregates are printed into a gel or other support matrix. The final functional tissue results form the post-printing fusion of the individual aggregates.

This patent is subject to a terminal disclaimer.

Self-assembling multicellular bodies and methods of producing a three-dimensional biological structure using the same

The Curators of the University of Missouri


A nozzle sheet has arrays of nozzles, and additionally has two first positioning holes on opposite sides of the arrays of nozzles, respectively, that are opposite to each other in a lengthwise direction of the nozzle sheet, and two second positioning holes in respective vicinities of the two first positioning holes. When the nozzle sheet is adhered to a lower surface of a channel unit consisting of a plurality of sheet members and having a plurality of ink channels, first, two first positioning pins of a first jig are fitted in the two first positioning holes of the nozzle sheet so as to position the nozzle sheet relative to the first jig and, subsequently, the channel unit is adhered to the nozzle sheet so as to provide a cavity unit. When a plurality of ejector units each of which includes an actuator fixed to an upper surface of the cavity unit are fixed to a frame member of an ink jet printer head, such that the ejector units extend parallel to each other, first, two pairs of second positioning pins of a second jig are fitted in the respective pairs of second positioning holes of the respective nozzle sheets of the ejector units and then the ejector units are fixed with an adhesive to the frame member.

1. Field of the Invention
The present invention relates to an ink jet printer head, such as a piezoelectric-type one, and an ejector unit for use in the printer head and having a nozzle and an actuator to eject a droplet of ink from the nozzle, and particularly to such an ejector unit which has a structure assuring that the ejector unit per se can be accurately assembled and that a plurality of ejector units can be fixed to a frame member of a printer head that has an ink-supply passage to supply ink to the ejector units, while the ejector units can be accurately positioned relative to each other.
2. Discussion of Related Art
An on-demand-type piezoelectric ink jet printer head is disclosed by, e.g., Japanese Patent Application Publication No. 2002-144590A1 or its corresponding U.S. Patent Application Publication No. 2002-0024568A1. The known printer head employs an ejector unit including a cavity unit consisting of a plurality of sheet members stacked on each other. The stacked sheet members include a nozzle sheet having a number of nozzles arranged in at least one array; at least one manifold sheet stacked on the back surface of the nozzle sheet with an adhesive and having at least one ink manifold communicating with an ink supply source; a base sheet having a number of pressure chambers communicating with the nozzles, respectively; and a spacer sheet interposed between the base sheet and the manifold sheet and having first ink channels connecting between the ink manifold and the pressure chambers and second ink channels connecting between the pressure chambers and the nozzles. The ejector unit additionally includes an actuator that is bonded to the back surface of the cavity unit and is operated to apply an energy (e.g., a pressure) to each of the pressure chambers so as to eject a droplet of ink from the each pressure chamber via a corresponding one of the nozzles.
The above-identified document recites that two or more ejector units are fixed, with an adhesive, to respective recesses formed in a lower surface of a frame member formed of a synthetic resin. To this end, the above-indicated nozzle sheet of each of the ejector units has two positioning holes in two opposite end portions thereof, respectively, that are opposite to each other in the direction in which the nozzles are arranged in the array, and two or more pairs of positioning pins of a jig are fitted in the respective pairs of positioning holes of the respective nozzle sheets of the ejector units, so that the ejector units, fixed to the frame member, extend parallel to each other and are distant from each other by a predetermined distance.
Meanwhile, when the nozzle sheet having the nozzles is bonded to a channel unit consisting of stacked sheet members having the pressure chambers and the ink channels, the above-indicated two positioning holes of the nozzle sheet have conventionally been used to accurately position the ink channels and the nozzles relative to each other,
That is, the two positioning holes of the nozzle sheet are used twice in two operations, i.e., the first operation to prepare the ejector unit by bonding the channel unit and the nozzle sheet to each other, and the second operation to attach the ejector unit to the frame member. In the first operation, however, when positioning pins of a first jig are fitted in the positioning holes of the nozzle sheet, or are pulled out of the positioning holes, the positioning holes may be deformed and/or the diameter thereof may be increased. In this case, in the second operation in which the positioning holes are used for the second time, positioning pins of a second jig may not be fitted in the positioning holes, or may rattle in the positioning holes. In addition, in the case where two or more ejector units are fixed by adhesion to the frame member, it is difficult to accurately align the direction of extension of each of the nozzles of the ejector units with respect to a reference direction on the frame member. Moreover, the degree of parallelism between the respective nozzle arrays of the ejector units, and/or a distance between the respective nozzle arrays may suffer an increased error, so that ink is recorded, on a recording medium such as a sheet of paper, at a position deviated from a correct position. This means a lowered accuracy of printing of the printer head,

Method of manufacturing an ink jet printer head including a plurality of cavity units


A printed material production apparatus comprises: a picture image input section for inputting a picture image string; a picture image conversion section for converting an inputted picture image string inputted into a panoramic picture image; a picture image processing section for generating a viewing point converted picture image string including a plurality of viewing point converted picture images in accordance with the panoramic picture image generated; and a printing section for producing printed material in accordance with the viewing point converted picture image string generated.

1. Field of the Invention
The present invention relates to a picture image generation apparatus for generating parallax picture images and a method thereof, and a printed material production apparatus for producing printed material in accordance with the parallax picture images thus generated and a method thereof.
2. Related Art
Recently, such an image print providing system as disclosed in Japan Utility Patent No. 3014733 that can provide services from photographing to printing of the photographed image in the same spot is widely known.
Further, recently, a new system that can image and print not only a still picture image but also a motion picture and/or parallax images has been developed, thereby enabling to obtain printed material the image of which changes when the printed material is viewed from a different direction.
For example, there is such a service to provide a parallax picture image photograph as printed material using the lenticular technology, which includes,
"Torikkiri Konica 3D (Trade Name)" available with a three-eyes-lens equipped film and its print service from Konica Corp.;
"Kodak Snap Kids 3D (Trade Name)" available with a three-eyes-lens equipped film and its print service from Kodak Corp.;
"MIP (Motion Image Print) card (Trade Name)" synthesized with 6 images, and "UgoiTaro (Trade Name)" apparatus for producing the card, both developed by Matsushita Denki Sangyo K.K.;
"Chikyuya K.K.'s Internet Service" for accepting orders for the card produced by the above-mentioned "UgoiTaro (Trade Name)" on the internet;
"Motion Picture Card Auto Vendor" as business entertainment equipment from Matsushita Denki Sangyo K.K., available as a card comprising a plurality of continuous photographs of an object, and in which the object appears as if moving when viewed from a different angle.
Further, as a similar system, there is such one that produces printed material utilizing the holographic technology capable of rendering parallax images only in the horizontal direction, which includes, for example,
"Instant holographic portrait printing system" authored by Akira Shirakura, Nobuhiro Kihara and Shigeyuki Baba, and published in the Proceeding of SPIE, Vol. 3293, pp. 246–253, January 1998;
"Fast holographic portrait printing system" authored by N. Kihara, A. Shirakura, and S. Baba, and published in the 3-D Imaging Conference 1998, July 1998.
In addition to the above, there is another system for producing printed material capable of rendering parallax images in both of the horizontal and vertical directions, which includes, for example,
"Holographic 3-D printer using the Lipman holographic stereogram" proposed by Yamaguchi, Honda and Ohyama, at the 20th Imaging Engineering Conference, December 1989;
"High density recording with the holographic 3-D printer" proposed by Endo, Yamaguchi, Honda and Ohyama at the 23rd Imaging Engineering Conference, December 1992.
Such systems for producing the printed material using the parallax images described above are capable of producing printed material by displaying a plurality of still picture images as if a motion picture film, imaging a plurality of images of an object from different viewing points using a dedicated imaging apparatus, or producing a plurality of images as viewed from different viewing points using the computer graphics (CG).
Further, digital image handling equipment such as a digital still camera, digital video camera recorder and the like are also popular. With widespread of these equipments, a so-called panoramic image generation is enabled using a computer or the like that capable of processing picture images by inputting sequential images or panning images as picture image data and joining there between.
As software for generating the above-mentioned panoramic image, there are available, for example,
"PictureGear Version 4.0 (Trade Name)" and "PictureGear Version 5.0 (Trade Name)", available from Sony Corp.;
"Reality Studio (Trade Name)" developed by "Live Picture Inc., USA" and available from "Live Picture Japan";
"QuickTime VR Authoring Studio (Trade Name)" developed by "Apple Computer Inc., USA" and available from "Apple Computer K.K. Japan"; and
"Panorama Boutique Light (Trade Name)", "Panorama Boutique Pro (Trade Name)" and "Tailing Boutique (Trade Name)" available from "Sanyo Denki K.K.".

Picture image generation and printed material production apparatus, and a method thereof


An embedded resistor and capacitor circuit and fabrication method is provided. The circuit includes a substrate, a conductive foil laminated to the substrate, and a thick film dielectric material disposed on the conductive foil. One or more thick film electrodes are formed on the dielectric material and a thick film resistor is formed at least partially contacting the thick film electrodes. A capacitor is formed by an electrode and the conductive foil. The electrodes serve as terminations for the resistor and capacitor.

Embedded passive electrical circuit components are commonly designed as individual components that are individually fabricated and embedded into a substrate. For example, resistors and capacitors are typically designed as individual electrical circuit components that may be formed using thick film materials, usually applied in the form of a thick film ink applied via a printing technique.
Conventional thick film resistors can be formed by printing an ink film of copper compatible resistor material, such as resistor formulations utilizing LaB6 as a functional phase, on a copper foil substrate. The printed thick film ink is then fired at an elevated temperature to cure. An encapsulation material may be printed on top of the resistor. The copper foil may be etched and laser trimming may be employed to achieve desired electrical resistance characteristics. The resistor circuit is then embedded into a substrate, such as a laminated substrate.
Conventional thick film capacitors can similarly be formed by printing and firing a thick film dielectric material on top of a copper foil and forming a capacitor electrode on top of the dielectric material. The resulting capacitor may be encapsulated and laminated onto a core of a substrate. Additionally, the capacitor electrode may be laser trimmed to achieve desired electrical capacitive characteristics. The capacitor circuit is then embedded into a substrate, such as a laminated substrate.
The conventional methodology for fabricating individual resistors and capacitors is generally limited to achieving certain circuit component densities which limits the number of passive components in a given amount of space that is available. Additionally, the embedded resistor and capacitor components typically can only be tested and trimmed after being laminated into the inner layer of the substrate which risks performing valuable steps on a potentially defective foil.
What is desired is a passive circuit that provides multiple circuit components and does not suffer the space limitations of conventional thick film passive circuit designs. In particular, it is desirable to provide for a resistor and capacitor circuit that may be easily employed in a laminated circuit board. Additionally, it is desirable to provide for a fabrication method that achieves enhanced embedded passive circuit densities. It is also desired to test and adjust the resistors and capacitors prior to lamination into the core of a substrate.

Embedded resistor and capacitor circuit and method of fabricating same


A method for decoding video signals comprising decoding a bit stream, and reproducing a video signal in reverse order of frames, the bit stream including each frame of the video signal which has been encoded using one of an intra coding system (I picture), a predictive coding system (P picture), and a bidirectionally predictive coding system (B picture), includes a group of frames including at least one frame of I picture, which can be decoded from the I picture and consecutively reproduced in order of the frames, being called a GOP (Group of Pictures); the frames being output in reverse order of the frames to obtain a desired frame, wherein: when the desired frame is one of I picture and P picture, only the I picture and P pictures from the first I picture in a GOP to the desired frame are decoded; and when the desired frame is B picture, only the desired frame is decoded if reference frames required for decoding of the desired frame are present in frame memories. As described above, in the method for decoding video signals according to the present invention, decoding processing of a desired frame is performed each time to output a reproduced image. Consequently, an increase in circuit scale can be avoided, resulting in smooth backward reproduction with a small memory capacity.

In recent years, development of techniques for compressing and encoding video signals, and larger capacities of storage media, such as magnetic disks or optical disks, have made it practicable to compress and encode video signals or sound signals and record the compressed and encoded signals in a storage medium.
FIG. 8 is a block diagram illustrating a prior art apparatus for decoding video signals. In the figure, reference numeral 1 designates an optical disk for recording bit streams that are obtained by compressing and encoding video signals and sound signals. When the bit streams are recorded in the optical disk 1, in order to prevent errors, interleaving is performed for the bit streams and error-correcting codes are added thereto. Reference numeral 2 designates an optical disk reading circuit for performing de-interleaving for a signal that is read from the optical disk 1 and correcting an error of the read signal, and outputting a bit stream 21. Reference numeral 8 designates a decoding circuit of video signals for decoding the bit stream 21 output from the optical disk reading circuit 2 to output a reproduced signal 81. Reference numerals 91 and 92 designate frame memories for storing the reproduced signal 81 that is produced in the decoding circuit 8. The reproduced signal 81 stored in the frame memories 91 and 92 is used as a reference image in the decoding circuit 8. Reference numeral 10 designates a frame memory for inputting and temporarily storing the reproduced signal 81 output from the decoding circuit 8, and reading out the reproduced signal 81 temporarily stored, according to a control signal from a reproduced signal output control circuit, thereby obtaining an output signal of this decoding apparatus. Reference numeral 12 designates a reproduced signal output control circuit for outputting a control signal required for readout of the reproduced signal 81 that is stored in the frame memory 10, to the frame memory 10.
The optical disk 1 in the apparatus for decoding video signals constituted as described above records video signals which are compressed and encoded according to the MPEG video standard of the ISO (hereinafter referred to as MPEG system). This MPEG system is a system of compressing and encoding video signals with high efficiency, based on interframe predictive coding. In this system, by changing prediction methods of respective plural frames, it is possible to realize high compression efficiency and reproduction in the middle of a sequence.
FIG. 9 is a diagram illustrating a plurality of consecutive image frames in time series. A prediction method in the MPEG system will be described. In the figure, numerals in the frames represent consecutive numbers of the frames, respectively, and it shows that time passes as the number increases. For example, the frame No.11 is a frame after the frame No.10.
In addition, alphabetical characters I, P, and B under the frames represent prediction methods of the frames, respectively. The frame with I, which is called I picture, is an intra coded picture that is encoded with only information in the frame. The frame with P, which is called P picture, is a predictive coded picture that is encoded by using the I picture or the P picture of three frames before as a reference image. For example, the P picture of the frame No.13 is predicted and encoded from one way using the P picture of the frame No.10 as a reference image. The frame with B, which is called B picture that is the characteristic of the MPEG system, is a bidirectlonally predictive coded picture that is encoded by using the frames before and after the B picture as a reference image. For example, the B picture of the frame No.12 is predicted and encoded from both way using the P pictures of the frames No.10 and No.13 as a reference image.
In the MPEG system, a group of a plurality of frames including one frame as I picture is called GOP (group of pictures). For example, in FIG. 9, a GOP unit comprises fifteen frames from the B picture of the frame No.2 to the P picture of the frame No.16, and corresponds to GOP(n), i.e., a range shown by a line with arrows at both ends. In addition, consecutive numbers n-1, n, n+1 of GOP are given for explanation. In the MPEG system, because the frames as P picture and B picture are predicted and encoded, based on data of the frames in one way and in two way, respectively, no perfect information is obtained from only data of the P picture or the B picture. Therefore, for example, random access to a GOP unit with data of a plurality of frames makes it possible to decode and reproduce a desired image from halfway through a serial video image. In this case, since the GOP unit includes one frame as I picture that is encoded with only information in the frame, decoding and reproduction are started from the I picture.
FIG. 10 shows a bit stream that is obtained by encoding the respective frames shown in FIG. 9. Since the order of the frames shown in FIG. 10 becomes one convenient for encoding processing and decoding processing, it is different from the order of the consecutive frames in time series shown in FIG. 9. For example, 41 represents the I picture of the frame No.4, 2B represents the B picture of the frame No.2, and 7P represents the P picture of the frame No.7. This notation will be used hereinafter when a specified frame and its picture type are described.
A description is given of operations of such an apparatus for decoding video signals as described above.
First, the operation in forward reproduction is described. The optical disk reading circuit 2 reads a bit stream from the optical disk 1 in order of the consecutive numbers of GOP. In the case of the bit stream shown in FIG. 10, that is in order of GOP(n-1), GOP(n), GOP(n+1), and GOP(n+2). The bit stream thus read is input to the decoding circuit 8. The decoding circuit 8 decodes the input bit stream sequentially to output the reproduced signal 81 according to the consecutive numbers of the frames. The frame memory 10 serves as a mere buffer, and temporarily stores the reproduced signal 81 and reads out the same, thereby producing an output 81 of this apparatus for decoding video signals.
Next, the operation in backward reproduction is described. The optical disk reading circuit 2 reads a bit stream from the optical disk 1 in reverse order of the consecutive numbers of GOP. In the case of the bit stream shown in FIG. 10, that is in order of GOP(n+2), GOP(n+1), GOP(n), and GOP(n-1). The bit stream thus read from the optical disk 1 is decoded in a forward direction by the decoding circuit 8 to obtain a reproduced image. The obtained reproduced image is stored in the frame memory 10. Then, the frame memory 10 reads out the reproduced image in a backward direction, thereby obtaining an output signal 81 of this apparatus, resulting in backward reproduction.
FIG. 11 is a diagram for explaining the operation of the frame memory 10 in backward reproduction. In the figure, GOP(n+1) shows the state in which a reproduced image obtained by decoding a bit stream of GOP(n+1) with the decoding circuit 8 is stored in the frame memory 10. Numerals 0 to 12 represent region numbers of the frame memory 10. This reproduced image, which is stored in the frame memory 10 with a storage region corresponding to thirteen frames, is read out, for each frame, from the region number 12 toward the region number 0, thereby obtaining an output signal 81 in which the reproduced image is in reverse of the forward order, like 31P, 30B, 29B, . . . . After outputting the reproduced image of the frames of GOP(n+1), a reproduced image obtained by decoding a bit stream of GOP(n) with the decoding circuit 8 is stored in the frame memory 10. In FIG. 11, GOP(n) shows this state. Then, the same operation as in the case of GOP(n+1) is performed, thereby producing an output signal 81 in which the reproduced image of GOP(n) is in reverse order. Hereafter, the operations described above are repeated to realize backward reproduction.
The prior art apparatus for decoding video signals constituted as described above requires a frame memory of a large capacity that can store a reproduced image of one GOP when backward reproduction of video signals is performed, leading to an increase in circuit scale and cost up.
Further, in the prior art decoding apparatus, when backward reproduction of video signals is performed, after the reproduced image of GOP(n+1) is output as an output signal from the frame memory, GOP(n) is decoded and the reproduced image of GOP(n) is stored in the frame memory 10 to produce an output signal. Therefore, there is a space of time between the output of the reproduced image of GOP(n+1) and the output of the reproduced image of GOP(n), whereby a space of reproduction time is produced between the frames which belong to the boundary between GOP(n+1) and GOP(n), for example, the frame 17B as the last output of GOP(n+1) and the frame 16P as the first output of GOP(n). As a result, it is difficult to obtain a smooth reproduced image.
Furthermore, when backward reproduction of video signals is performed in the prior art decoding apparatus, in the case of decoding B pictures which will make a reproduced image after I picture, for example, the frames 17B and 18B of GOP(n+1), the P picture, i.e., the frame 16P, of GOP(n) before GOP(n+1) including the reproduced image is used as a reference image. Therefore, another frame memory for storing a reproduced image of GOP(n) obtained by decoding GOP(n) is required, resulting in an increase in circuit scale of frame memories. In addition, when decoding of the frames 17B and 18B is omitted in order to avoid the increase in circuit scale, no perfectly consecutive frames are obtained, so that the quality of the image is adversely affected.

Method and apparatus for decoding video signals

Matsushita Electric Industrial Co., Ltd.


A collimator capable of being reduced in its external size without sacrificing an aperture is to be provided. To this end, the collimator comprises a pair of first plate members which defines a radiation passing aperture by a spacing between respective opposed end faces, a pair of second plate members which respectively overlap the first plate members at least partially so as to block any other radiation than the radiation passing through the aperture, a pair of third plate members which respectively overlap the second plate members at least partially so as to block any other radiation than the radiation passing through the aperture, an adjusting mechanism which adjusts the aperture by moving the pair of first plate members, and a follow-up mechanism which causes the pair of second plate members to move following the pair of first plate members with movement of the first plate members.

The present invention relates to a collimator and a radiation irradiator. Particularly, the invention is concerned with a collimator for a radiation, e.g., X-ray, and a radiation irradiator provided with the collimator.
In a radiation irradiator there is used a collimator for controlling the irradiation range of a radiation. The collimator has an aperture which permits a radiation to pass therethrough, and the radiation cannot pass through other than the aperture. Thus, the irradiation range of the radiation is controlled by the aperture. The degree of opening of the aperture can be changed to adjust the irradiation range of the radiation.
As shown in FIG. 10, the aperture-adjustable collimator has a pair of movable plate members having a radiation shielding property, i.e., blades 901 and 901′. The blades 901 and 901′ are disposed so that respective end faces are opposed to each other, and are movable in directions opposite to each other in a plane parallel to their surfaces. For widening the aperture, the pair of blades 901 and 901′ are moved away from each other, while for narrowing the aperture, the both blades are moved to close to each other. Thus, the aperture becomes maximum when the pair of blades are remotest from each other, and becomes minimum when both blades are closest to each other.
In a collimator having a large aperture adjusting range, there are used blades of a large area. If the blade area is large, an external form of the collimator comes to have a large size corresponding to a maximum moving distance of blade outer edges, as shown in FIG. 11.
In a mammography apparatus which makes fluoroscopy of the breast with X-ray, a collimator assumes a position confronting the face of a subject and so it is preferable that its external form be as small as possible. However, in the case of a mammography apparatus capable of making tomography, an increase in external form of the collimator has heretofore been unavoidable because a large aperture is needed.

GE Medical Systems Global Technology Company, LLC


A method including receiving a request for a report on a data set. The method also includes providing the report. The report includes a macro page having a subset of the data set. The method also includes converting the macro page into a primary tree data structure having levels. The method also includes buffering the primary tree data structure in a buffer to form a buffered tree data structure. The buffered tree data structure is buffered in a level order of the levels. The method also includes selecting a first micro page from the buffered tree data structure. The first micro page is configured for display on a user interface. The method also includes transmitting, to the user interface, the first micro page.

As used herein, a "large data set" is a data set which cannot be displayed practically as a single data set on a single display screen, or which cannot be processed by a selected processor within a pre-determined time period. In some cases, a computer will be unable to display the large data set, and/or the computer may experience undesirable delays in calculating the pagination or scrolling for the large data set, leading to user dissatisfaction.

Pagination processing and display of data sets


A flow meter for calculating fluid flow rate and/or volume includes a flow cell shaped to define an internal passageway through which the fluid travels, and four separate transducer assemblies independently mounted within mounts in the flow cell in fluid communication with the internal passageway. Each transducer assembly includes a transducer, a transducer stud with a recess in its front surface that is dimensioned to receive the transducer, and a sensor plate mounted onto the stud for retaining the transducer in the recess. A bore extends vertically through the transducer stud and into communication with the recess, the bore being dimensioned to receive wiring for the transducer. The separation and independent mounting of the four transducer assemblies in the flow cell minimizes the disruption of normal fluid flow through the internal passageway, thereby enabling greater accuracy of measurements to be achieved.

A flow meter is a fluid measurement device that measures the velocity of fluid traveling through a designated flow tube, or conduit, in order to calculate total volume flow. In this manner, a flow meter can determine the total volume of fluid used in a particular environment. For this reason, flow meters are commonly utilized in both public and private water systems to measure water consumption.
An ultrasonic flow meter is one type of flow meter that relies upon the transmission and measurement of ultrasonic waves within the designated conduit in order to accurately calculate fluid flow rate and/or volume. An ultrasonic flow meter typically comprises a flow cell with a tubular main body which defines the interior channel through which the designated fluid travels.
In one type of flow meter which is well known in the art, a first transducer assembly is mounted within an externally-accessible, vertical support, or mount, formed along one exterior side of the main body towards its inlet port. Similarly, a second transducer assembly is mounted within an externally-accessible, vertical support, or mount, formed along the opposing exterior side of the main body towards its outlet port. Each transducer support is in fluid communication with the interior channel, thereby providing the first and second transducer assemblies with the capability to measure fluid velocity, as will be explained further below.
Each of the first and second transducer assemblies is constructed as an elongated cylindrical member which is inserted downward into an open-top bore defined by its corresponding support mount. More specifically, each transducer assembly typically includes an elongated, cylindrical post on which a pair of transducers are mounted in vertical alignment. As can be appreciated, the pair of transducers is mounted on the single-piece post such that, with the flow meter assembled, one transducer is positioned towards the top of the interior channel and the other transducer positioned towards the bottom of the interior channel.
In use, the upper and lower pair of transducers in the first transducer assembly transmits ultrasonic sound waves through fluid traveling within the flow tube. The ultrasonic sound waves are received by the upper and lower pair of transducers in the second transducer assembly. The pair of transducers in the second transducer assembly then transmit ultrasonic sound waves back to the pair of transducers in the first transducer assembly to complete the sound wave travel path, or cycle. The sound wave data is then compiled and processed by an integrator in electrical communication with the transducers in order to calculate fluid flow rate and/or volume.
Although well known in the art, it has been found that flow meters of the type as described above suffer from a notable shortcoming. Specifically, the integration of single-piece, post-type, transducer assemblies into the flow cell compromises the overall effectiveness of the flow meter. Most notably, the significant length and diameter of the post which supports the pair of transducers creates an inwardly-extending, vertical protrusion along one side of the internal passageway. Further, since the first and second transducer assemblies are mounted on opposite sides of the flow cell, the pair of transducer assemblies together create substantial protuberances along both sides of the internal passageway. Due to its considerable size, each post disrupts normal fluid flow within the internal passageway and creates turbulence, thereby directly affecting the accuracy of fluid flow rate and volume calculations.

Ultrasonic flow meter having four separate transducer assemblies mounted within mounts in a flow cell