A semiconductor device may include a MOS transistor having source and drain regions in a semiconductor substrate, a first inter-layer insulator having first contact holes that reach the source and drain regions over the MOS transistor. Cell contact plugs in the first contact holes contact with the source and drain regions. A second inter-layer insulator over the first inter-layer insulator and the cell contact plugs has second contact holes that reach the cell contact plugs. Contact plugs each have first and second portions. The first portion is in the second contact hole. The second portion extends over the first second inter-layer insulator. Metal barrier layers cover the upper surfaces of the second portions of the contact plugs. Capacitors each have a bottom electrode layer, a capacitive insulating layer and a top electrode layer. The bottom electrode layers each have a contact portion that contacts with the metal barrier layer.

1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same. More specifically, the present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory) including memory cells having contact structures and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2006-317302, filed Nov. 24, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
The DRAM has memory cells, each of which may have a pair of a single transistor for selecting a memory cell and a single capacitor. In general, the transistor and the capacitor may be connected to each other through one or more contact plugs.
The capacitor may be formed in a hole such as a capacitor-hole in an insulating film such as an inter-layer insulator. The capacitor may include a bottom electrode, a capacitive insulating film, and a top electrode. The bottom electrode contacts with a capacitance contact plug. The capacitance contact plug may be positioned under the bottom electrode. The capacitance contact plug contacts with a cell contact plug. The cell contact plug may be positioned under the capacitance contact plug. The cell contact plug is connected to the transistor. In other words, the transistor is connected through the cell contact plug and the capacitance contact plug to the capacitor.
Increasing the degree of integration of the DRAM needs the shrinkage of each memory cell. The shrinkage of each memory cell needs to limit the plan-area in which the capacitor is present. The limited plan-area for the capacitor may result in reduced capacity of the capacitor. The reduction in the capacity of the capacitor may make it difficult for the conventional DRAM to ensure the normal memory operation thereof There was an issue of how to ensure the necessary capacity of the capacitor of each memory cell when each memory cell is shrunken. The limited plan-area for the capacitor needs increasing the height or vertical dimension of the capacitor in order to ensure the necessary capacity of the capacitor. The increased height or vertical dimension of the capacitor needs the increased thickness of the insulating film or inter-layer insulator having a capacitor hole of a high aspect ratio in which the capacitor is formed. Atypical example of the increased thickness of the insulating film or inter-layer insulator may be about 3000 nanometers.
The capacitor hole of the high aspect ratio may decrease in horizontally sectioned area as the depth thereof becomes deeper. In other words, the bottom of the capacitor hole is smaller in horizontally sectioned area than the top thereof The smaller sectioned area of the bottom of the capacitor hole results in a smaller contact area between the bottom electrode and the capacitor contact plug. Decreasing the contact area between the bottom electrode and the capacitor contact plug may increase contact resistance between the bottom electrode and the capacitor contact plug. Increasing the contact resistance may inhibit desired high performance of the DRAM.
The following descriptions are concerned with the issues caused by decreasing the contact area between the bottom electrode of the capacitor and the capacitor contact plug which contacts with the bottom electrode.
FIG. 5 is a fragmentary cross sectional elevation view illustrating a conventional DRAM having capacitors. Cell contact plugs 105 contact with transistors for selecting cells, wherein the transistors are not illustrated. Capacitor contact plugs 104 are formed in an inter-layer insulator 103. The capacitor contact plugs 104 contact with the cell contact plugs 105. An inter-layer insulator 102 is provided over the inter-layer insulator 103 and the capacitor contact plugs 104. An inter-layer insulator 100 is provided over the inter-layer insulator 102. Capacitor holes are formed in the stack of the inter-layer insulators 102 and 100. The capacitor holes reach the top surfaces of the capacitor contact plugs 104. Capacitors are provided in the capacitor holes. Each capacitor includes a bottom electrode 106, a capacitive insulating film 107 and a top electrode 108. The bottom electrode 106 is provided on the bottom and side walls of each capacitor hole, so that the bottom electrode contacts with the capacitor contact plug 104. The capacitive insulating film 107 is provided on the bottom electrode 106 and the top surface of the inter-layer insulator 100. The capacitive insulating film 107 is common to the capacitors. The top electrode 108 is provided on the capacitive insulating film 107 so that the top electrode 108 is separated from the bottom electrode 106 by the capacitive insulating film 107.
As shown in FIG. 5, the capacitor holes are coaxially misaligned to the capacitor contact plugs 104 even the bottom electrodes 106 contact with the capacitor contact plug 104. The coaxial misalignment of the capacitor holes to the capacitor contact plugs 104 reduces a contact area A2 between each capacitor and the corresponding capacitor contact plug 104.
FIG. 6 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the conventional DRAM having capacitors. In the inter-layer insulator 100, the capacitor holes 101 are formed. The inter-layer insulator 100 may in general be made of silicon oxide. The known anisotropic etching process can be used to form capacitor holes 101 in the silicon oxide inter-layer insulator. The anisotropic etching process uses, as a main etchant, fluorine ions that are field-accelerated in high frequency plasma.
The capacitor holes 101 may in general have a center axis which is vertical to the surface of the semiconductor substrate on which the DRAM is formed. In the anisotropic etching process, fluorine ions are field-accelerated in the direction vertical to the surface of the semiconductor substrate. In some cases, field distribution in the capacitor holes 101 may vary so as to change the acceleration direction of fluorine ions. The orbit of the field-accelerated fluorine ions may have a curvature but be not straight. In this case, the capacitor holes 101 as formed may have a curvature B. The curvature B of the capacitor holes 101 may further reduce the contact area between the bottom electrode 106 and the capacitor contact plug 104 in addition to the above-described misalignment between the capacitor holes 101 and the capacitor contact plugs 104. Further reduction of the contact area may further increase the contact resistance between the capacitor and the capacitor contact plugs 104.
FIG. 7 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the other conventional DRAM having capacitors. Each capacitor contact plug in the capacitor contact hole 101 has a contact pad that is wider than other portion. The contact pad is greater in horizontally sectioned area than the pother portion. The contact pad provides larger contact area A4 with the bottom electrode 106 in the capacitor hole.
The contact pad also provides larger allowance for misalignment between the capacitor hole and the capacitor contact plug under the condition for ensuring the minimum necessary contact area A4. The contact pad is suitable for increasing the density of the memory cells.
The capacitor contact plugs 101 having contact pads are made of silicon. If the bottom electrodes of the capacitors are made of a metal, a metal barrier layer needs to be interposed between the metal bottom electrode and the silicon contact pad in order to prevent reaction of silicon with the metal. Further, a silicide layer needs to be formed between the metal barrier layer and the silicon contact pad in order to reduce the contact resistance between the metal barrier layer and the silicon contact pad. The metal barrier layer may be made of titanium nitride. The silicide layer may be made of titanium silicide.
The metal barrier layer and the silicide layer may be formed as follows. Capacitor holes 101 are formed in an inter-layer insulator 100 so that parts of the top surfaces of the contact pads of the silicon capacitor contact plugs are shown through the capacitor holes 101. A chemical vapor deposition (CVD) process is carried out to supply titanium on the surfaces of the silicon contact pads, and a silicidation reaction is caused to form titanium silicide films on the surfaces of the silicon contact pads. Subsequently, metal barrier layers of titanium nitride are formed on the titanium silicide films. When the capacitor holes 101 have a high aspect ratio or a greater depth, an insufficient amount of titanium may be supplied on the surface of each silicon contact pad, thereby causing an abnormal silicidation reaction. As a result, a desired or intended silicide layer can not be formed.
FIG. 8 is a fragmentary cross sectional elevation view illustrating the capacitor holes of the other conventional DRAM having capacitors. High aspect ratio or larger depth of the capacitor holes may cause insufficient amount of titanium to be supplied on the bottoms of the capacitor holes, thereby forming undesired or unintended silicide layers of off-stoichiometric composition on the surfaces of the silicon contact pads. The silicide layers of off-stoichiometric composition may be highly resistive. Further, silicon migration can be caused, thereby forming voids on the surfaces of the silicon contact pads. Such voids may cause bad connection between the bottom electrode 106 and the silicon contact pads. The likelihood of causing these problems may depend upon the depth of the capacitor holes 101.
Japanese Unexamined Patent Application, First Publication, No. 2002-083881 discloses a conventional technique to prevent the last-mentioned problem with the off-stoichiometric composition of the silicide layers. The conventional technique is to avoid the above-described abnormal silicidation that results in off-stoichiometric composition of the silicide layers. After the capacitor contact plug is formed in a lower inter-layer insulator, a metal barrier layer including a stack of TiN/Ti layers is formed on the surface of the capacitor contact plug. Then, an upper inter-layer insulator is formed over the lower inter-layer insulator and a capacitor hole is formed in the upper inter-layer insulator, wherein the capacitor hole reaches the metal barrier layer.
The contact pad of the capacitor contact plug increases the contact area between the bottom electrode and the capacitor contact plug. When the bottom electrode is made of a metal or a metal compound, the abnormal silicidation reaction can be caused thereby making it difficult to ensure the electronic connection between the capacitor contact plug and the bottom electrode of the capacitor.
In accordance with the conventional technique disclosed in Japanese Unexamined Patent Application, First Publication, No. 2002-083881, the barrier layer covering the surface of the contact plug can prevent abnormality of silicidation reaction. This structure may, however, not prevent the other problem with misalignment between the capacitor contact plug and the capacitor hole. As described above, the misalignment decreases the contact area between the capacitor contact plug and the bottom electrode of the capacitor, thereby making it difficult to ensure the minimum necessary contact area for obtaining sufficiently reduced contact resistance between the capacitor contact plug and the bottom electrode of the capacitor.
In accordance with the conventional method of forming a capacitor having a bottom electrode of a metal or a metallic compound which is connected to a capacitor contact plug, it is not easy both to prevent the abnormality of silicidation reaction on the interface between the capacitor contact plug and the bottom electrode of the capacitor and to ensure a sufficiently large contact area between them and reduce the contact resistance between them. This results in decreasing the yield of manufacturing the semiconductor device.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved semiconductor device and/or method for forming the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Semiconductor device and method of forming the same


Methods are provided for helping to automate the design of electronic circuitry in which multiple memory functions are provided by common physical memory. Interactive computer screens prompt the user to enter information about the multiple memory functions that the user desires. The data thus entered by the user is then reformatted for use as specific values of parameters in a parameterized function that can provide the required circuit design when its parameters are thus supplied with specific values.

This invention relates to utilization of electronic memory, and more particularly to automating the sharing of a physical memory by several functional circuits, each of which may have its own memory needs that may be asserted in parallel.
Programmable logic integrated circuit devices ("PLDs") typically have many regions of programmable logic that are interconnectable in any of many possible ways by programmable interconnection resources. PLDs also typically include input/output resources that are used via the programmable interconnection resources. It has also become quite common to include blocks of memory on PLDs. The PLD may use such memory as random access memory ("RAM"), read-only memory ("ROM"), or other types of memory. For example, with suitable additional control circuitry, such memory may be used as first-in/first-out ("FIFO") memory. The additional control circuitry may be implemented in the programmable logic of the PLD.
Because of the extremely large logic capabilities of many PLDs, such PLDs are often used to perform multiple functions simultaneously, or at least partly or substantially simultaneously. Each of these functions may have its own requirements for supporting memory. Because the PLD is typically a generic device that is intended to satisfy many possible uses, the details of which are not known in advance by the PLD manufacturer, it is difficult to provide PLDs with memory blocks in the numbers and sizes that will meet the memory needs of the many functions that the PLD user may want to have the PLD perform. Also, for reasons of economy, there is interest in providing relatively large blocks of memory on PLDs, rather than providing many relatively small memory blocks. However, when this is done, the user may be burdened with the task of figuring how to have several functions share one large memory.
Although up to this point this background has been provided in the context of memory on PLDs, it will be understood that the same problem may arise in other contexts such as PLDs using external memory, application-specific integrated circuits ("ASICs") using on-board or external memory, systems of multiple integrated circuits or other components sharing memory, etc. This invention can be used to help solve the problem of sharing physical memory in any of the various contexts in which it may arise. For simplicity and convenience herein, the invention will be illustratively described, for the most part, in its application to PLDs with on-board memory. But from this description, those skilled in the art will fully understand how the invention can be applied in many other contexts.

Logic generation for multiple memory functions


Implants include a film layer containing cellulose secured to a surface of the porous layer that also contains cellulose, wherein the film layer is secured to the porous cellulose without the use of an adhesive.

1. Technical Field
The present disclosure relates to medical devices which include a porous cellulose-containing substrate having a cellulose-containing film secured thereto without the use of an adhesive.
2. Background of Related Art
In situ hemostatic therapy has primarily focused on the transformation of precursor solutions into solids within a patient's body. Transformations have been achieved by a variety of means, including precipitation, polymerization, crosslinking, and desolvation. However, significant limitations exist when using solutions for in situ hemostatic therapy. Solutions of low viscosity may flow away and be cleared from an application site before transformation and solidification occurs. Furthermore, formulation of the solutions may be complex, as preparation of precursor solutions typically requires reconstitution of the precursors, or, when the solutions are stored frozen, thawing.
Therefore it would be desirable to provide in situ hemostatic therapy which includes implantable devices combined with dry materials that are activated by the presence of aqueous physiological fluids. The combination of an implantable device with dry materials ensures the situ hemostatic therapy occurs at the site of implantation.

Cellulose-containing medical device having a multi-layer structure produced without adhesive


In one aspect, the present invention provides isolated nucleic acid molecules that each encode a geranyl diphosphate synthase protein, wherein each isolated nucleic acid molecule hybridizes to a nucleic acid molecule consisting of the sequence set forth in SEQ ID NO:1 under conditions of 5×SSC at 45° C. for one hour. The present invention also provides isolated geranyl diphosphate synthase proteins, and methods for altering the level of expression of geranyl diphosphate synthase protein in a host cell.

The monoterpenes are a large family of plant natural products that function as defensive agents, pollination attractants and allelopathic compounds (J. B. Harborne, in J. B. Harborne and F. A. Tomas-Barberan (eds.), Ecological Chemistry and Biochemistry of Plant Terpenoids, Vol. 31, Clarendon Press, Oxford, 1991, pp. 396-426; J. H. Langenheim, J. Chem. Ecol. 20:1223-1280, 1994). Over 500 naturally occurring monoterpenes have been identified (J. Buckingham, Dictionary of Natural Products on CD-ROM, Ver. 6.1, Chapman & Hall, London, 1998), a number of which are of commercial importance as flavors and fragrances, pharmaceuticals, insecticides and synthetic intermediates (D. F. Zinkel and J. Russell (eds.), Naval Stores: Production, Chemistry, Utilization, Pulp Chemical Association, New York, 1989, pp. 477-572; B. M. Lawrence, Perfum. Flavor 17:15-28, 1992; F. A. Dawson, Naval Stores Rev. March/April 1994, pp. 6-12).
The universal precursor of the monoterpenes is geranyl diphosphate (GPP) produced by geranyl diphosphate synthase (GPPS) which catalyzes the condensation of isopentenyl diphosphate (IPP) and dimethylallyl diphosphate (DMAPP) to the C10 product (see THE FIGURE). This enzyme is similar to farnesyl diphosphate synthase (FPPS) which condenses two molecules of IPP with DMAPP to form the C15 precursor of the sesquiterpenes and triterpenes, and to geranylgeranyl diphosphate synthase (GGPPS) which condenses three molecules of IPP with DMAPP to form the C20 precursor of diterpenes and tetraterpenes (see THE FIGURE). These enzymes, referred to collectively as short-chain prenyltransferases, function at the branch-points of isoprenoid metabolism and are considered to play a regulatory role in controlling the flux distribution of IPP into the various terpenoid families (J. Gershenzon and R. Croteau, in T. S. Moore, Jr. (ed.), Lipid Metabolism in Plants, CRC Press, Boca Raton, Fla., 1993, pp. 339-388).
Given the importance of GPPS in plant isoprenoid metabolism, there is a continuing need to isolate additional types of GPPS proteins, and nucleic acid molecules that encode GPPS proteins, to facilitate genetic manipulation of plants to optimize, or otherwise alter, plant isoprenoid metabolism. In this regard, an unsuccessful attempt was made to purify a GPPS from A. grandis which resulted in only a 15-fold purification of the enzyme with 88% loss of enzymatic activity. The partially purified enzyme was not visible by SDS-PAGE analysis (D. Tholl et al., Arch. Biochem. Biophys. 386:233-242, 2001).

Geranyl diphosphate synthase molecules, and nucleic acid molecules encoding same

Washington State University Research Foundation


A machine guarding system generally includes a switch mat in electrical communication with a machine being guarded. The switch mat is adapted to be placed on a floor adjacent the machine being guarded and includes a pressure actuated switch mechanism which causes power to the machine to be terminated when a pressure is applied to the switch mat. The switch mat further includes a status indicator display disposed on a surface of the switch mat which is illuminated based on a status of the machine being guarded. In a preferred embodiment, the machine guarding system further includes a machine control unit for controlling power to the machine being guarded. The switch mat is in electrical communication with the machine control unit, wherein the switch mechanism causes the machine control unit to terminate power to the machine when a pressure is applied to the switch mat. The machine control unit also illuminates the indicator display based on a status of the machine being guarded.

The present invention relates generally to safety systems to protect persons from injury from industrial machines, and more particularly, to a system for terminating power and indicating an active condition of a machine.
It is known in the art to provide safety systems for dangerous machinery and industrial apparatus to protect persons from injury from such equipment. Such dangerous equipment includes welding machines, robotic assembly devices, metal cutting equipment and the like, all of which may be self-operating or person-operated. Generally, safety systems for such machinery typically involve some form of means for preventing personnel from inadvertently approaching the dangerous equipment or involve some form of alarm or power cut-off to the machine which is activated upon a dangerous condition, such as when a person gets too close to the dangerous equipment. Examples of such safety systems include dual hand operated controls which forces an operator to keep both hands on the controls, presence sensing devices incorporating light beams and receivers and electric switch mats connected to a machine controller for terminating power to the machine if someone steps on or off the mat.
Various types of electrical switch mats are known in the art. Electrical switch mats have been designed for use in many different applications including use in floor mats for security, safety or other purposes to detect movement of objects or pedestrian traffic thereover. Generally, electrical switch mats include one or more pressure-actuated switches incorporated within a floor mat material which protects the switch against wear. For example, normally open and normally closed pressure-sensitive electrical ribbon switches have been incorporated into numerous designs for electrical switch mats. Open and closed pressure-sensitive ribbon switches generally include a pair of either spaced or closed conductors respectively supported in an insulative jacket. Generally, relatively light pressure on the jacket will close the space in an open switch and open the conductors in a close switch thereby activating the switch. Thus, someone stepping on or off an electrical switch mat having a ribbon switch incorporated therein will activate the switch.
Electrical switch mats as described above have been extremely useful in detecting and responding to the presence, or absence, of the operator or others anywhere on its sensing surface, wherein the sensing surface is defined as the area covered by a single mat or a plurality of mats in combination. In one typical application, one or more sensing mats are placed directly in front of a piece of machinery, wherein the machine operator stands on the mat during operation of the machinery. If the operator steps off the mat, or if someone else steps on the mat, the switch mat is activated to terminate power to the machine.
In another application, the dangerous equipment may be surrounded by a plurality of switch mats to define a danger zone, wherein a person entering the danger zone will step on a mat, thereby activating a switch to terminate power to the equipment. Alternatively, the dangerous equipment may be substantially surrounded by a protective barrier, such as a guard cage or fence, to define a danger zone and a switch mat is placed at the only entrance into the danger zone. Similarly, anyone entering the danger zone will step on the switch mat to terminate power to the dangerous equipment.
While such switch mat based safety systems are effective in terminating power to a piece of dangerous equipment upon a change in status within the danger zone, it is often difficult for persons approaching such a danger zone to ascertain the present status within the danger zone. In particular, a person having a need to enter the danger zone may not be able to easily determine if it is indeed safe to enter (e.g., the dangerous machinery is already turned off), or whether the zone is in a danger status (e.g. the machinery is operating).
Accordingly, it would be desirable to provide a machine guarding safety system that can readily indicate a present status of a danger zone surrounding the dangerous machinery. It would be further desirable to provide a machine guarding safety system utilizing a switch mat having a visual status indicator incorporated directly in the switch mat to display an active status of the danger zone to those approaching the switch mat.

Machine guarding system having a sensing mat with status indicator lights


An input system for an electronic apparatus including at least one force sensing element and a joystick member. The at least one force sensing element is connected to an underside of a printed wiring board (PWB) of the electronic apparatus. The at least one force sensing element includes a plurality of force sensing domes extending in a downward direction from the PWB. The joystick member extends through the PWB and contacts the force sensing domes. The joystick member has a user contact section located above an upper side of the PWB. The joystick member is adapted to be moved to depress the force sensing domes towards the PWB.

1. Field of the Invention
The present invention relates to an input device for an electronic apparatus and, more particularly, to an input system having a joystick.
2. Brief Description of Prior Developments
Joysticks are commonly known in many different types of electronic devices, such as a computer game system controller or on a computer control console. U.S. Pat. No. 5,499,041 describes one type of joystick for use as a pointer on a laptop computer keyboard.
Radio telephone handsets have displays where text and graphics are displayed. A user can scroll through a menu or telephone numbers or even play games by use of arrow keys (up/down and/or left/right) on the handset. Another type of radio telephone handset interface has a roller that rolls along a single axis. U.S. Pat. No. 6,480,185 B1 describes a trackball type of input device for use in a portable radio telephone.
In addition to radio telephone handsets, there are also other types of communicator devices which use radio frequency and/or satellite transmissions. These communicators can include mobile terminals having a wireless communication function as well as features such as, for example, a camera, a PDA, or even a laptop computer with a radio telephone communications module. U.S. Pat. No. D447,740 S shows one type of communicator which has a general clamshell design with a radio telephone feature in a collapsed configuration and a keyboard and larger display available in an open configuration.
In the future, most communicators are expected to have some kind of a navigation device in them. A joystick is a common form of navigation device for many people and is commonly used. However, manufacturing of a joystick in a portable communicator, such as the communicator shown in U.S. Pat. No. D447,740 S has its limitations. More specifically, a joystick is relatively high and is not particularly adapted for use with a hand held communicator, such as a hand-held portable mobile terminal.
There is a desire to provide a joystick type of input device or navigation device in a portable mobile terminal which has a reduced height. There is also a desire to provide a joystick type of input device in a hand-held mobile radio telephone flip-open communicator which can be covered by a lid of the flip-open communicator when the communicator is in a collapsed configuration.


A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times. Raw data files corresponding to each model input are generated by the fet level simulator. The raw data files preferably comprise lists of node values with corresponding time stamps. Corresponding latch node values in the raw data files are compared to identify the nodes of a circuit which are affected by races. Identifying affected latch nodes allows a race's root cause to be quickly pinpointed. Vector inputs to the fet level simulator may be varied. If vector inputs are varied, comparison of the raw data files comprises comparing the files generated for differing models with common vector inputs. Apparatus for implementing the above method is also disclosed. The method and apparatus provide for increased race coverage, and decrease the time and effort required to debug races once their presence is identified.

The invention pertains to a method of checking for races in a digital design. More particularly, the invention pertains to an efficient and accurate method of locating races within a very large scale integrated (VLSI) circuit comprising only one system clock.
The performance of VLSI circuits has been significantly improved in recent years. Many of their improvements are derived from new hardware devices which are capable of operating at higher clock frequencies. However, as the clock frequencies of such circuits are increased, increased efforts must be made to prevent performance degradation as a result of clock skew, edge degradation, and the like.
Clock skew is demonstrated in FIG. 2. Overlapping clock signals CK1 204 and CK2 206 may be ideally timed as illustrated by the dashed lines in FIG. 2. However, their timings, upon reaching a particular unit of a hypothetical VLSI circuit, may be as shown by the solid lines 200, 202 of FIG. 2. By design, the clock signals 204, 206 have an overlap designated by the left-most arrow 208. However, routing paths, manufacturing variances, and other factors can result in one or both of the clock signals being delayed before reaching a particular unit of the hypothetical VLSI circuit. These delays are known as clock skew. In FIG. 2, signal CK1 200 is "skewed", resulting in an additional overlap 210 between signals CK1 and CK2.
Another problem caused by manufacturing variances, line coupling, and other factors is edge degradation. Edge degradation is demonstrated in FIG. 3. If edge degradation is significant, clock signal edges may rise and fall slowly (demonstrated by the waveforms of clocks CK1N 300 and CK2N 302 in FIG. 3). In a high frequency circuit, these slow transitions from "clock HI" to "clock LO", or vice versa, can cause errors in a circuit pipeline (e.g., 1100, FIG. 11). Note that ideally, clock signals CK1N 304 and CK2N 306 are non-overlapping, but due to edge degradation, an overlap 308 between the signals can result.
Errors caused by clock skew and/or edge degradation are herein referred to as clock signal races and are characterized by data from one stage 1104 of a pipeline being passed to a subsequent stage 1114 before the proper clocking signal has been received to clear the subsequent stage 1114 of data previously stored in that stage.
Thus, a race may lead to a data collision and result in lost and/or corrupted data. As known to those skilled in the art, approximately 99% of all races are attributable to clock skew, and the slower rise/fall times of clock signal edges due to edge degradation.
Fortunately, clock races may be fixed using various "gated" clock signals. Examples of gated signals are disclosed in U.S. Pat. No. 5,124,572 to Mason et al., and U.S. Pat. No. 5,306,962 to Lamb, which are hereby incorporated by reference for all that they disclose. Gated clock signals are also disclosed in the U.S. Pat. Application of Perez filed Mar. 1, 1996 (Ser. No. 08/609,592) entitled "High-Performance, Low-Skew Clocking Scheme for Single-Phase, High-Frequency Global VLSI Processor Clocks", and the U.S. Patent Application of Naffziger filed Mar. 1, 1996 (Ser. No. 08/609,306) entitled "Local CMOS Clock Buffer Circuits". These applications are also incorporated by reference for all that they disclose. Mason et al. and Lamb disclose a clocking methodology for VLSI circuits which selectively uses the edges of two overlapping clocks and two non-overlapping clocks to eliminate race conditions. The overlapping clocks are used wherever possible to provide superior timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers.
However, before one may fix a race, one must first identify where race specifications have been violated. Existing methods which are used to induce and/or identify races include: inspection, varying clock inputs, and asserting top level signals.
Inspection relies on one or more engineers making a visual inspection of a circuit's schematic. Circuits are checked, and then cross-checked. This method is not only time consuming, but also error prone and non-exhaustive.
One method of inducing races involves creating a model of the circuit, and then varying the timing of the model's clock inputs. A disadvantage of this method is that it relies on the existence of more than one system clock.
Races are often identified by asserting top level signals. This method relies on induced race failures propagating to the "top" of a circuit (i.e., its input/output (I/O) ports, or contact pads). Unfortunately, many races do not propagate to the top. Of the races that do propagate to the top, a large percentage of the races may have a root cause which lies significantly distant from a top level signal. Failures must be traced to their root cause, and some races can be extremely difficult to debug. Furthermore, there is a problem of masking. When relying on a race to propagate to the top, one race can often mask the affects of another race. Such an occurrence can lead to numerous repetitions of the method, and complex, repetitive tracings through circuit paths.
Some of the newer VLSI circuits have only one system clock, and existing methods of race checking are ill-equipped to deal with these circuits. Race checking by inspection is obviously difficult due to the inherent complexity of VLSI circuits. Likewise, signal assertion is a less than adequate method since once a failure is identified, a race must be traced to its root cause through multiple stages of logic. This can be an extremely time consuming, costly, and unbearable task.
Varying clock signals to induce races is not even an option with a circuit having only one system clock. In such a circuit, overlapping and non-overlapping clocks are locally generated by each unit of a VLSI circuit. Variation of the single system clock input, from which all other clock signals are derived, fails to create the varying degrees of clock overlap which help to induce races.
Regardless of the method(s) used to check for races, it is very important to locate all races prior to building a silicon prototype. If races are not identified "pre-silicon", locating and debugging races becomes significantly more time consuming and costly.
It is therefore a primary object of this invention to provide an exhaustive method of checking for clock-based races.
It is another primary object of this invention to provide a method which more precisely pinpoints the location of races, thereby decreasing the time and effort required to debug them.
It is also an object of this invention to provide a method which increases the observability of races.
It is yet another object of this invention to provide a method which decreases the occurrence of race checking oversights and/or errors.
It is a further object of this invention to provide a method which may be used to identify races prior to the creation of circuit masks and/or a silicon prototype.
An additional object of this invention is to provide a method which can be used to locate races in a VLSI circuit having only one system clock.
A final object of this invention is to provide a method which can be used to detect races which do not propagate to the "top".

Method of checking for races in a digital design


A display apparatus (1) according to the present invention has display means (3) that detects contact and proximity of operating means with respect to a display range of the display means, and control means (5) that determines a position where an item designated by contact is to be displayed, based on the position of contact and the position of proximity which are detected by the display means (3).

Recent years have seen many touchscreens having a display unit with added input functions, incorporated in information processing terminals. An information processing terminal that incorporates a touchscreen displays buttons that describe names of items on the screen. When the user touches a button with a finger, a command representing the name of item that corresponds to the touched button is entered into the information processing terminal.
When the user selects a button displayed on the screen, the finger of the user may hide the name of item displayed on the button. Even if the name of item is hidden, no significant problem is posed when the user is entering commands in succession or when the user has sufficiently confirmed the name of item before selecting the item. However, when the user is not experienced enough to operate the touchscreen or has taken its eyes off the display unit immediately before operating the touchscreen, if the user's finger has hidden the name of item, then the user may feel anxious because the user may not be sure what it has selected. The user may make an attempt to stop himself/herself from feeling anxious by wastefully redoing the action on the touchscreen, e.g., canceling the item that the user has selected. Alternatively, the user may let the uncertainly selected item be executed, possibly performing a function that he/she did not intend.
One method of alleviating the above shortcoming or allowing the user to take reliable actions may be to increase display areas to be touched and reduce areas that are hidden by the finger for better visibility. However, since the screen of information processing terminals is limited in size, increased display areas (areas to be touched) are disadvantageous in that they tend to reduce the amount of information which can be displayed on the screen.
More and more mobile phones have been using touchscreens, as typified by smartphones. Of the mobile phones, those other than smartphones are required at all times to have a smaller casing and are more limited in screen size than the smartphones. The mobile phones tend to incorporate an increased number of functions, and the number of items that can be selected on the mobile phones also tends to increase accordingly.
The increased number of selectable options due to the increased number of functions may be resolved by displaying more selectable options on the screen. However, displaying many selectable options on a screen of limited size requires that the selectable options have smaller display areas, which results in a disadvantage in that they are likely to be hidden by the finger.
An example of display method for solving the above problem is disclosed in Patent document 1. Patent document 1 reveals that of a plurality of image keys displayed on a touch screen, the name of item of the image key to which the user's finger has moved most closely is displayed in a speech balloon near the image key. Even if the name of item of the image key is hidden by the user's finger, the user is able to recognize to which image key the user's finger is closest.

Display apparatus, display method, and program


A lighting module for illuminating cultivated crops in indoor farming comprises at least one monolithic efficiency enhancing optical element (EEOE) further comprising: (a) a front portion comprising a spectrum conversion layer; (b) an optically transparent middle body portion having at least one light source embedded there within and configured to emit spectrally controllable radiation; and (c) a back portion configured to reflect the radiation emitted by the spectrum conversion layer to the cultivated crops. The back portion has a central area being adjacent to the optically transparent middle body portion configured for reflecting radiation propagating within the optically transparent middle body portion and a peripheral area configured for reflecting radiation emerged from the optically transparent middle body portion via the side surface.

Artificial light sources are used as grow lights to replace sun light in indoor farming. This mainly includes plants but also livestock and insects farming. The most common types of grow lights are High Intensity Discharge (HID) lamps, Fluorescent lamps, and Light Emitting Diode (LED) lamps. One of the main costs of operating a grow light is its energy consumption. Unfortunately, many grow lights are not very efficient and using them leads to high operation costs. When speaking about efficiency of grow lights, the important parameter is the photosynthetic photon efficacy (PPE) which is the ratio between the light source photon output utilized in photosynthesis to its electrical energy consumption (the PPE units are micromole per joule). In recent years LED-based grow lights are becoming more and more popular due to their high efficacy and long lifetime. Although LED-based lamps are significantly more efficient than HID lamps, energy consumption is still the main cost of operating a grow light; therefore, it is important to make them as efficient as possible. So, every increase in the efficacy of LED grow lights is desirable and will benefit the users of grow lights, allowing them to reduce the costs of operating their indoor gardening venture. A grow light with high efficacy reduces operating costs firstly by reducing direct consumption of electrical energy, and secondly by producing much less heat to a level that makes active cooling systems such as fans and air conditioners unnecessary.
There are various factors that limit the efficacy of current LED lights. One of them is that some of the light emerging from the LED die is reflected by the various surfaces of the LED and by surfaces surrounding the LED and results in multiple reflections and consequently absorption of light, thus reducing the amount of useful light exiting the LED. In addition, some of the light that exits the LED surfaces goes into undesired directions and is also wasted.
Another factor is related to white LEDs that employ an embedded phosphor. Some of the light that is emitted from the phosphor is reflected back to the LED and is wasted. In the case of high-power LEDs, the phosphor heats up (being close to the LED die), and its efficiency decreases.
Another factor is related to cases where the phosphor is not close to the LED die (i.e., remote phosphor). Significant part of the light that is emitted by the phosphor is directed back into the lighting device toward the LED and its surroundings and is reflected by the LED surfaces and by the surrounding surfaces inside the lighting device to various directions, resulting in multiple reflections and absorption that reduce the amount of useful light that is emitted from the phosphor.
U.S. Ser. No. 10/151,446 discloses a light-emitting device comprising a light source and an extractor element coupled to the light source. The extractor element includes at least in part a total internal reflection surface.
US 20120170303A1 and U.S. Pat. No. 8,579,466B2 employ a remote phosphor in a planar waveguide.
Efficacy of lighting devices is the main factor affecting their operating costs and their maximum achievable output. Reducing operating cost and increasing light output are especially important in the field of indoor farming. Therefore, there is a real need for improving the efficacy of LED-based grow lights by maximizing both the amount of light extracted from the LED and the efficiency of the optical system that delivers the light to the plant.


Described techniques provide for prioritization of radio bearers and logical channels based on mixed transmission time interval (TTI) durations or numerologies of the bearers or logical channels. Two or more bearers may be identified for uplink data transmission that carry data to be transmitted using different TTI durations or numerologies. Each bearer may be prioritized based on the associated bearer type, TTI duration or numerology, or combinations thereof. Additionally, one or more logical channels may be associated with one or more bearers, and also prioritized based on the associated bearer type, TTI duration or numerology, or combinations thereof. A buffer status report (BSR) may be generated that has one or more portions associated with the different priorities of bearers or logical channels. Buffer information associated with the higher priority bearers or logical channels may be provided ahead of buffer information associated with lower priority bearers or logical channels.

The following relates generally to wireless communication and more specifically to uplink data transfer for wireless communications with mixed transmission time intervals (TTIs).
Wireless multiple-access technologies have been adopted in various telecommunication standards to provide a common protocol that enables different wireless devices to communicate on a municipal, national, regional, and even global level. An example telecommunication standard is Long Term Evolution (LTE). LTE is designed to improve spectral efficiency, lower costs, improve services, make use of new spectrum, and better integrate with other open standards. LTE may use orthogonal frequency division multiple access (OFDMA) on the downlink, single-carrier frequency division multiple access (SC-FDMA) on the uplink, and multiple-input multiple-output (MIMO) antenna technology.
In some examples, a wireless multiple-access communication system may include a number of base stations, each simultaneously supporting communication for multiple communication devices, otherwise known as user equipment (UEs). In an LTE or LTE-Advanced (LTE-A) network, a set of one or more base stations may define an eNodeB (eNB). In other examples (e.g., in a next generation new radio (NR) or Fifth Generation (5G) network), a wireless multiple access communication system may include a number of smart radio heads (RHs) in communication with a number of access node controllers (ANCs), where a set of one or more RHs, in communication with an ANC, defines a base station (e.g., an eNB or next generation NodeB (gNB)). A base station may communicate with a set of UEs on downlink channels (e.g., for transmissions from a base station to a UE) and uplink channels (e.g., for transmissions from a UE to a base station).
A base station in some LTE or NR deployments may transmit to one or more UEs using multiple different TTIs that may include a shortened TTI (sTTI) that has a reduced length relative to a 1 millisecond (1 ms) or legacy LTE TTI. Users communicating using sTTIs may be referred to as low latency users. An sTTI may be a subset of one or more subframes that correspond to 1 ms or legacy TTI subframes. A UE may have data that is to be transmitted using different TTIs, and efficient identification and reporting of such data may help enhance network efficiency.

This patent is subject to a terminal disclaimer.

Uplink data transfer for wireless communications with mixed transmission time intervals


The invention provides a shift register which can function normally even with an abnormal register or a broken register while suppressing the manufacturing cost as little as possible. The shift register of the invention includes n regular registers (SR(1) to SR(n)) connected in series and n output lines (L1 to Ln) corresponding to the n regular registers, r (r≦n) redundant registers (SR(n+1) to SR(n+r)) connected in series to the n regular registers, and a switch circuit for selectively connecting the regular and redundant resistors to output lines. The switch circuit connects the n regular registers to the corresponding output lines in a normal state, connects normal registers of upper and lower stages of the broken register by skipping and disabling the broken register if any, and connects normal regular registers and the same number of redundant registers as the broken registers to the n output lines.

1. Field of the Invention
The present invention relates to a shift register and an electronic device using the same.
2. Description of the Related Art
In an active matrix display device such as a liquid crystal display device (LCD) and an EL panel, a shift register is used as a driver circuit (scan line driver circuit and signal line driver circuit) for reducing the number of signal input terminals. A shift register is configured by a plurality of registers connected in series. A signal inputted in each register is transferred to a next register according to a clock signal.
In such a driver circuit, a transistor which forms a register in a shift register may be abnormal (or broken) by static electricity and the like. In such a case, a signal is not transferred to a register of lower stage than the abnormal register (or broken register), which causes a defect in display. Such a display device cannot be shipped as a product, thus manufacturing yield is reduced. In view of this, a redundant structure is employed in which a plurality of shift registers are connected in parallel so that a driver circuit can function normally even when a register in the shift register is broken (see Patent Document 1). In the case of connecting two shift registers in parallel, for example, when a register of one shift register is broken, a corresponding register of the other shift register can be used instead. Thus a driver circuit can keep operating normally.    [Patent Document 1] Japanese Patent Laid-Open No. 6-83286

Shift register and electronic device using the same

Semiconductor Energy Laboratory Co., Ltd.


A direction selective unidirectional clutch assembly for a fluid meter counter module assembly is characterized by a drive selector mechanism to couple a direction selection drive shaft to a unidirectional clutch to select one of a first flow direction and a second flow direction of flow of the fluid to drive a counter module. The direction selection draft is coupled to a rotating member (e.g. impeller) driven by flow of the fluid and rotates in a direction that is responsive to the direction of rotation of the rotating member. A pair of gears are mounted to slide along the direction selection draft between a first position and a second position. A direction changing gear is mounted at the second position. Further provided is a flow meter with a direction selective unidirectional clutch assembly.

Gas meters, particularly for industrial use, include measurement devices to measure large volumes of gas. A gas meter pressure body converts gas flow into rotational motion via two solid impellers. As a result of their fixed orientation and swept volumes, when the impellers are driven by a gas flow, the impellers only allow a set volume of gas to pass through the meter on each rotation. Accordingly, the quantity of gas passing through the meter can be calculated by counting the number of rotations of at least one of the impellers. A counter module may be driven by the rotation of the impellers. Flow through a meter may become interrupted or temporarily reversed during normal operation of the meter, which can lead to reverse rotation of the impellers. Also, a meter may be installed for a reverse flow. Therefore a direction of rotation may affect the counting.
U.S. Pat. No. 8,789,413B2 issued Jul. 29, 2014 discloses a unidirectional clutch assembly to drive a counter for a positive displacement rotary gas meter. The unidirectional clutch assembly disclosed therein may be used to drive a counter using only rotations in a single, desired direction. The clutch assembly may be installed at manufacturing to be responsive to only the one desired direction, for example, for only forward flow or only reverse flow counting. At manufacture, the counting direction is fixed such that a forward flow meter cannot count fluid in a reverse flow and vice versa.
It may be desired to mount a meter with flow in a first direction and then reuse the meter in a second installation with a flow in the reverse direction. Thus may be desired to set or reset the flow direction of the counting in a fluid flow meter having a unidirectional clutch.

Direction selective unidirectional clutch assembly for a fluid meter counter module assembly and a fluid meter with a direction selective unidirectional clutch assembly


A frequency synthesizer according to the direct digital synthesis method is provided. The frequency synthesizer includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored in its memory cells for the determination of sine-function values corresponding to phase values of the phase signal, a digital-to-analog converter for the conversion of time-discrete sine-function values into a quasi-analog sinusoidal time function and an anti-aliasing low-pass filter for smoothing the quasi-analog sinusoidal time function. The frequency synthesizer additionally contains an adder, which is connected between the memory unit and the digital-to-analog converter and which superimposes a non-periodic signal over the time-discrete sine-function values.

1. Field of the Invention
The invention relates to a frequency synthesiser according to the direct digital synthesis method with the capability of suppressing secondary lines in the frequency spectrum of the output frequency signal.
2. Description of the Background Art
Contemporary high-resolution broadband frequency synthesisers are essentially based upon two different methods, the fractional-N-method and the direct digital synthesis method.
In the case of the fractional-N-method, the frequency is adjusted through defined frequency division of the reference frequency in a forward branch disposed upstream of the phase-locking loop or of the output frequency of the phase-locking loop in the closed-loop branch of the phase-locking loop, in each case via one programmable frequency divider. The frequency divider operates digitally via sigma-delta modulation of a digital word acting as a reference frequency value. A high-frequency phase-locking loop can be realized through the use of high division factors in the frequency divider of the closed-loop branch. However, high division factors bring about a significant increase in the phase noise of the phase-locking loop (phase noise of the phase-locking loop=20*log (division factor of the output frequency divider)). Moreover, the sigma-delta modulator generates a quantization noise increasing further away from the carrier, which must absolutely be suppressed by the PLL. The attenuation of the increased phase noise and/or of the increasing quantization noise by means of low-pass characteristics of the phase-locking loop is purchased at the cost of poorer control dynamics of the phase-locking loop (longer transient recovery time because of reduced bandwidth of the phase-locking loop). The maximum realisable control bandwidths, according to the existing prior art are around a few KHz. The fractional-N-method also provides a comparatively poor transient recovery performance, because the algorithm of the fractional-N-method approaches the optimum in an integrating manner. A final disadvantage of the fractional-N-method is that the frequency spectrum of the output frequency contains secondary lines, which occur during the division of the output frequency signal through the fractional-N-frequency divider in the closed-loop branch of the phase-locking loop with a division factor close to a whole-number division factor (so-called "fractional-N-secondary lines").
One advantage of the phase-locking loop is the fact that it can be realized in a comparatively cost-favorable manner and is therefore used primarily in applications in the low-price segment. The method of direct digital frequency synthesis does not suffer from the disadvantages mentioned above and is therefore used primarily in frequency synthesisers with rapid transient recovery and low-phase-noise.
A frequency synthesiser based on the method of direct digital synthesis according to document EP 0 469 233 A2 consists of a phase accumulator, which increments the phase of a phase signal cyclically at the clock pulse of a reference frequency by phase increments, which can be adjusted in a frequency word at the input of the phase accumulator. A memory unit downstream of the phase accumulator with a stored table of sine-function values supplies the sine-function values associated with the relevant phase values of the cyclical phase signal to a digital-to-analog converter at the clock pulse of the reference frequency as a time-discrete functional sequence. Smoothing through an anti-aliasing low-pass filter to the desired sinusoidal frequency signal takes place after the digital-to-analog converter.
The disadvantage with direct digital frequency synthesisers is the occurrence of secondary lines very close to the carrier in the frequency spectrum. If the lines appear close to the useful signal, these secondary lines cannot be regulated out of the frequency spectrum by a series-connected phase-locking loop with optimised bandwidth. The following reasons can be given for the occurrence of secondary lines of this kind in the frequency spectrum of the output frequency, also with reference to the specialist article: Papay, "Numerical Distortion in Single-Tone DDS", IEEE-Instrumentation and Measurement Technology Conference, Budapest, May 21–23, 2001:                Secondary lines caused by restricted phase resolution of the phase signal in the sine table of the memory unit:
As a result of limited memory capacity of the memory unit, all the bits of the phase signal are not used in addressing the memory cells containing the sine table. As a result of a restriction to the higher-value bits of the phase signal, the number of phase interpolation points used per sinusoidal oscillation is significantly reduced corresponding to a lower resolution of the phase interpolation points. This leads to a sawtooth phase error between the optimum phase interpolation points realisable, for example, with a 32 bit-wide phase-signal data word and the phase interpolation points actually used. This periodicity in the phase error, which corresponds to a phase modulation, leads to discrete secondary lines around the carrier frequency in the frequency spectrum of the output frequency generated.                Secondary lines caused by excessively low-amplitude resolution of the digital-to-analog converter:
The quantization of the time-discrete sine-function values for a predetermined phase value causes an amplitude error, which is dependent upon the resolution of the quantization (number of bits for the quantization of the amplitude value). Through this quantization of the amplitude value, an amplitude error of ΔA=1/(2A*√{square root over (12)}) is caused, under the assumption that rounding errors are distributed uniformly in the range ±½ LSB (A=number of bits of the D/A converter). If the length of the phase accumulator is a whole-number multiple of the frequency word, then the phase values are repeated periodically and the quantization error associated with each phase and amplitude value provides a periodic characteristic, which leads to higher value harmonics (=secondary lines) in the frequency spectrum. In the absence of periodicity of the phase values and therefore of the amplitude values in the case of a non-whole-number ratio between frequency word and the length of the frequency accumulator, interference lines can occur throughout the frequency spectrum instead of the higher value harmonics.                Secondary lines caused by nonlinearities in the transmission characteristic of the digital-to-analog converter:
As shown in FIG. 1, the transmission characteristic of a digital-to-analog converter generally provides a nonlinearity in the curve by comparison with an ideal-linear characteristic. This is strongly exaggerated in the presentation in FIG. 1. This may be a nonlinearity, which extends over the entire level range (a so-called integral nonlinearity) or only a deviation from the theoretical value difference for the transition between two conditions of the analog-to-digital converter (so-called differential nonlinearity). These nonlinearities are attributable to asymmetries in the internal structure of the digital-to-analog converter (e.g. asymmetries in difference amplification, power sources, resistance chains etc.). In the case of harmonic excitation, nonlinearities in the transmission behaviour lead to the generation of harmonic waves, which, once again, lead to secondary lines in the frequency spectrum of the output frequency. Because the system involved is a sampled system, aliasing can occur. As shown in FIG. 2, these aliasing effects mean that harmonic secondary lines above the first Nyquist zone can be folded into corresponding non-harmonic secondary lines within the first Nyquist zone. It is problematic that non-harmonic secondary lines of this kind in the first Nyquist zone can come to be disposed very close to the carrier frequency. While harmonic secondary lines can be removed by means of low-pass filtering, this is not a viable possibility with non-harmonic secondary lines close to the carrier.                Secondary lines caused by the non-ideal dynamic behaviour of the digital-to-analog converter:
From a certain sampling frequency, dynamic effects become more prominent, by comparison with the static effects described in the previous paragraph, in the transmission behaviour of the digital-to-analog converter. This relates primarily to differences in rise and fall times and differences in overshooting in the case of transmission behaviour with multiple delays in the phase of sampling and holding of the time-discrete sinusoidal interpolation points ("glitches"). These dynamic interference effects are attributable to asymmetries and error adaptations in the internal structure of the digital-to-analog converter (e.g. error-adapted RC-elements, different switching times and the absence of synchronicity of individual logic units etc.). Since these dynamic interference effects occur periodically, undesired harmonics (=secondary lines), which are dominant from a given frequency by comparison with the secondary lines caused for the previously named reasons, also occur in the frequency spectrum. A minimisation of these dynamic irregularities through an additional sampling and holding while exploiting the resulting smoothing effect is not possible especially at higher sampling frequencies, because the sampling period can then become smaller than the transient recovery time.
The occurrence of secondary lines resulting from restricted phase and amplitude resolution is nowadays largely manageable. While an increased phase resolution, can be realized, for example, using advanced interpolation algorithms, an increased amplitude resolution no longer represents a substantial problem with contemporary digital-to-analog converters with 14 bit data-word width even in the upper clock-pulse frequency range of 100 MHz and above. Secondary lines caused by nonlinearities in the transmission characteristic and caused by dynamic asymmetries of the digital-to-analog converter, however, still present an unresolved problem with contemporary direct digital frequency synthesisers.


The compounds secoisolariciresinol (SECO), enterodiol (ED) and enterolactone (EL), which are metabolites of secoisolariciresinol diglucoside obtained from flaxseed, are used for the treatment of diseases or conditions requiring administration of an antioxidant. Diseases or conditions that may be treated include hypercholesterolemic atherosclerosis, type I and type II diabetes, ischemic heart disease, heart failure, endotoxic and hemmorhagic shock, inflammatory bowel disease, rheumatoid arthritis, Parkinson""s disease, and stroke.

This invention relates to a method for the use of metabolites of secoisolariciresinol diglucoside (SDG) for the treatment of diseases or conditions requiring administration of an antioxidant. These metabolites include secoisolariciresinol (SECO), enterodiol (ED) and enterolactone (EL).
Reactive oxygen species, which include superoxide anion (O2xe2x88x92), hydrogen peroxide (H2O2), hydroxyl radical (.OH) and singlet oxygen (1O2), have been implicated in the pathophysiology of numerous diseases, including hypercholesterolemic atherosclerosis, diabetes mellitus, ischemic/reperfusion injury, volume or pressure overload heart failure, hemorrhagic shock, endotoxic shock, ageing, inflammatory bowel disease (Crohn""s disease, ulcerative colitis), Parkinson""s disease, rheumatoid arthritis and stroke.
Antioxidants such as vitamin E, secoisolariciresinol diglucoside (SDG), probucol, vitamin C, superoxide dismutase, catalase, sulphasalazine, and various other drugs without antioxidant activity, have been shown to be effective to a varying degree in the diseases referred to above. These drugs, with the exception of vitamin C and E and SDG, are expensive and have adverse side effects.
As described in Prasad, U.S. Pat. No. 5,846,944, incorporated herein by reference, SDG, isolated from flaxseed, has been shown to be effective in lowering cholesterol, and in reducing the development of atherosclerosis in hypercholesterolemic rabbits. It is also effective in reducing the incidence of diabetes mellitus and preventing endotoxic shock.
Reactive oxygen species are known to be involved in the pathophysiology of ageing and numerous diseases, such as hypercholesterolemic atherosclerosis, type I and type II diabetes, ischemic heart disease, heart failure, endotoxic and hemmorhagic shock, inflammatory bowel disease, rheumatoid arthritis, Parkinson""s disease, and stroke.
Secoisolariciresinol diglucoside (SDG), which is obtained from flaxseed, is metabolized to secoisolariciresinol (SECO), enterodiol (ED), and enterolactone (EL). A description of the above metabolites can be found in a report by R. K. Harris et al. (1991) Methods Development for Phytochemical Compliance Markers in Designer Foods (Flaxseed Powder), Midwest Research Institute. These metabolites are respectively 4.86, 5.02, and 4.35 times more potent than vitamin E, and 3.82, 3.95, and 3.43 times more potent than SDG. Vitamin E, SDG and various other drugs, some with antioxidant activity and some without, are currently used for the treatment of the above diseases.
Drugs presently used to treat the diseases listed above, are expensive and have been less than satisfactory for the treatment of these diseases because of their adverse side effects. The discovery of SDG metabolites offers a safe, less expensive antioxidant that is useful in the treatment of these diseases and conditions. They are derived from dietary flaxseed and are therefore from a natural source, having little to no side effects.
Thus, the present invention relates to the use of secoisolariciresinol (SECO), enterodiol (ED) or enterolactone (EL) for the treatment of diseases or conditions requiring administration of an antioxidant. These diseases or conditions include hypercholesterolemic atherosclerosis, type I and type II diabetes, ischemic heart disease, heart failure, endotoxic and hemmorhagic shock, inflammatory bowel disease, rheumatoid arthritis, Parkinson""s disease, and stroke.
The SECO, ED or EL is preferably used in purified form and can be administered orally or intravenously. It can, for instance, be administered in a once daily oral dosage of about 5-15 mg per kg of body weight. The oral doses may conveniently be in the form of tablets or capsules and these metabolites may be used together with a variety of pharmaceutically acceptable diluents or carriers.
Morbidity and mortality associated with the diseases referred to above and their complications, such as lost wages, increased health costs and social burdens, are enormous. Treatment with the metabolites according to this invention serve to reduce or prevent the late complications associated with these diseases. The morbidity and mortality associated with these diseases is reduced or prevented. This reduces the burden of illness to society, and overall health care costs, and permit these patients to return to the workplace and be productive members of society.

University of Saskatchewan Technologies Incorporated


A motor control for a reciprocating load includes overvoltage suppression. The motor control comprises a variable frequency drive (VFD) operatively connected to a power source for operating a motor to drive the reciprocating load. A sensor determines motor torque. A control unit is connected to the VFD and to the sensor and is adapted to control the VFD in a normal mode to operate the motor at a select reference frequency. The control unit predicts occurrence of a negative motor torque condition based on sensed motor torque and in response to a negative motor torque condition controls the VFD in a negative motor torque mode to operate the motor at a higher frequency than the select reference frequency to prevent the motor from entering a negative slip condition.

A motor drive system, in one known form, comprises an AC source supplying three-phase AC power to a variable frequency drive (VFD). The VFD includes an AC/DC converter connected by a DC link or bus to a DC/AC converter. The DC/AC converter may comprise a pulse width modulated inverter using insulated GATE bipolar transistors (IGBTs).
Many industrial applications use reciprocating loads that are driven by VFDs. In most of such applications, during certain portion of one complete load cycle, the load tends to accelerate the motor at speeds higher than that commanded by the VFD. This is referred to as "overhauling". Under such a condition, the inverter is required to absorb the regenerated energy. Typically, this is achieved by providing braking resistor and transistor units know as 'braking units'. The braking units are sized according to the duty cycle and stored regenerative energy in the load. Sometimes, multiple braking units may need to be employed in a master-slave manner to accommodate large amounts of regenerated energy. Use of braking units, while accepted in the industry, suffer from high costs, require large space to mount, and are inherently inefficient since the regenerated energy is dissipated as heat in the braking resistors.
Alternative methods that can handle overhauling load without the use of external brake resistors have been considered. Some of the methods include high slip braking, disabling or reducing torque component of current during overhauling, and increasing output frequency based on DC bus voltage.
Kume et al., U.S. Pat. No. 6,429,612, assigned to the assignee of the present application, discloses high slip braking. This patent relates to bringing a rotating load to a stop, rather than to absorb the regenerated energy during overhauling and continue operating in the motoring mode in the next part of the cycle.
Another technique that has been adopted in the industry for handling an overhauling type load reduces the torque-generating component of the output current during regeneration to zero. In other words, the motor is operated at approximately zero slip. Operation at zero slip yields zero regenerated torque and thus the motor is prevented from converting the mechanical energy into electrical energy. This has been implemented in high performance inverters. However, this requires an inverter capable of operating in a closed loop vector control manner that can track the actual speed of the motor and maintain operation at zero slip throughout the regenerative part and come out of this mode once this part of the cycle is complete. Such inverters need sophisticated control algorithms operating on dedicated DSP chips.
Another alternative method currently being used in the oil industry is described in Watson, U.S. Pat. No. 6,414,455. The '455 patent discusses three modes of operating a variable speed drive to handle overhauling type loads. The three modes are "TM" mode or constant torque mode, "BSM" mode or base speed mode, and "DM" mode or dual mode. In the TM mode, the speed is allowed to change in order to maintain a certain torque reference. In the BSM mode, the torque is allowed to change within the lower and upper torque limits in order to maintain the desired set speed. In the DM mode, the controller is fed with two speed reference values (Fref) and two torque reference values (Tref). The user then has the choice to either select one of the speed reference values or one of the torque reference values. The basis of the control philosophy is to limit the torque provided by the inverter to the motor during the upstroke part of the cyclic load. Doing this reduces or eliminates regenerative torque being produced during the down-stroke, thereby increasing the overall system efficiency, and reducing the size and cost of the inverter, since the inverter does not need the braking resistor unit. Some drawbacks of this method are that there is need for a DC bus voltage sensor and a DC bus current sensor. Most inverters do not have DC current sensors at the correct position and rely on the DC current flowing into the capacitor, which flows only when the capacitor voltage has gone lower than the instantaneous value of the input AC voltage and hence does not truly mirror the instantaneous torque profile of the load. Further, DC voltage across the DC bus capacitor is a parameter that changes very slowly and cannot be relied upon to take corrective action since it would be too late to act upon it. If the torque reference is maintained at a value needed for motoring action and is not changed during regenerative action, such a control philosophy will fail to limit the magnitude of the regenerated energy and this can cause a rise in DC bus voltage and eventually put the inverter in a fault state.
The present invention is directed to solving one or more of the problems discussed above.

Overvoltage suppression technique for variable frequency drives operating reciprocating loads


An image forming apparatus which can detect a defect in a nozzle and an optical system, and inform an execution of maintenance.

1. Field of the Invention
The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus, which is provided with an image reading device, and can diagnose conditions of nozzles in a print head and an optical system in the image reading device.
2. Description of the Related Art
There have so far been provided a method, which is used for detection of a defect in the print head by a test pattern, and for visual check of the printed test pattern to see if any defect being occurred. However, this method may have a shortcoming that the results of a visual check differ according to each person""s subjective point of view. For example, nozzle clogging may be overlooked, or sometimes such a magnifying glass as a loupe is needed.
In addition, Japanese Unexamined Patent Publication, No. 9-240017 discloses an art for detecting which nozzles are defective.
However, JPP 9-240017 lacks a special diagnostic function for an optical system. That is, the production of a high-quality image will not be able to expect when a defect occurs in a scanner portion as an image reading device. Since optical systems such as a scanner are usually covered, contamination adhered to an optical system cannot be visually checked. Further, a dedicated image reading means is needed for locating a defective nozzle.
An object of the present invention is to provide an image forming apparatus, which can detect a defect in a nozzle and an optical system.
Another object of the present invention is to provide an image forming apparatus in which a user is informed of an execution of maintenance.
According to the present invention, there is provided an image forming apparatus comprising: a scanner which reads an image and a print head which prints an image; a head control unit which controls the print head to print a test pattern with the print head; and an image processing unit which diagnoses a defect in the print head and the scanner by processing data of the test pattern which is read by the scanner.
The image forming apparatus according to the present invention have the following exceptional advantages.
(i) Starting a test pattern printing operation by the head control unit, in response to power switch-on, a print start command input from a user, or a demand of a user allows a printing operation to perform in a good condition. Even if the situation where a defect in the ink jet nozzle or contamination adhered to the optical system is caused by having been left unused for a long time.
In addition, it allows image degradation to avoid in an unusual situation.
(ii) Printing a test pattern repeatedly by the head control unit, or reading it repeatedly by the scanner permits accuracy of the results of comparing processing to enhance.
In addition, determining whether a defect is occurred in the nozzle in the print head or the optical system of the scanner by the image processing unit permits a proper countermeasure to take according to where a defect occurs and what is a cause therefor.
(iii) Providing a display unit for displaying a command to clean the ink nozzle when the image processing unit determined a defect to be occurred in the ink nozzle system enables a user to prompt to input a command.
In addition, locating a defect in the ink nozzle by the image processing unit when a defect is occurred, and providing a cleaning unit for cleaning the nozzle with respect to defective portions enables the amounts of ink needed for cleaning the nozzle and time required for cleaning operation to reduce, with the minimum cleaning operation.
(iv) Providing the display unit for displaying a command to perform maintenance of the optical system when the image processing unit determined a defect to be occurred in the optical system of the scanner makes it possible to prompt a user to perform maintenance of the optical system.
In addition, locating a defect in the optical system when a defect is occurred in the optical system by the image processing unit, and providing the display unit for displaying defective portions makes it possible to reduce the time required for cleaning operation with the minimum cleaning operation.

Image forming apparatus diagnosing print head and optical system conditions based on printed test pattern

Abstract: The apparatus comprises a scanner which reads an image; a print head which prints an image; a test pattern image data ROM stored a test pattern; and an image processing unit which diagnoses a defect in the print head and the scanner by processing data of the test pattern which is read by the scanner.


A system and method for using an easy query in a business warehouse system environment that includes external end-user systems. A method includes providing a flag in a query to a business warehouse data system, the flag marking the query for access to the query by sources external to the business warehouse data system. The method further includes providing, by the at least one data processor the access points having a number of parameters that are fixed at a design time associated with the query, providing a query result to the access points of the sources external to the business warehouse system according to the number of parameters. The system and method provide an easy way of creating an access function at design time, as well as an easy way of result set consumption provided by the function at runtime.

A business warehouse system is a business information storage system that includes a database. The database typically requires a reporting tool with which a user can access and work with any type of document. For example, SAP AG of Walldorf Germany provides its own Business Warehouse (BW), which includes a reporting tool used to work with data in the BW database, called a Business Explorer (BEx). BEx has a Web-based user interface and is made up of two components, a BEx browser and a BEx analyzer.
The BEx browser provides an organized interface in the BW to documents such as workbooks, links, and BW Web reports. The BW database itself is segmented into discrete data areas called InfoCubes, which are made up of data and associated metadata. The BEx analyzer allows the user to examine segmented data in a variety of useful combinations, for example when comparing financial data for different fiscal years.
A database such as in SAP BW contains all the relevant data a customer needs for their analysis. To read and access this data, the customer creates and uses queries, such as BEx Queries. These queries are the basic element for various types of analysis. However, these queries are each a local object, which means it is only possible to work with them locally within the business warehouse system.
It is common behavior for companies to work with large system landscapes that have several servers and several business warehouse systems. Thus, there exists a need to combine data from different systems within a single application, as well as a need for a query protocol for receiving queries from a number of data consumers, including mobile devices.


A compule for storing dental composite material to be extruded from the compule using a standard dispenser in the preparation or repair of a dental restoration. The compule comprises: a cylindrical body having an orifice at one end thereof through which the dental composite material is extruded and a means at the opposite end thereof to facilitate the extrusion of said dental composite material using the dispenser. The body of the compule is composed of an electrically conductive plastic or alternatively may be composed of a thermally and electrically conductive plastic having a thermal conductivity in the range of between 1.0 w/mk and 500 w/mk and an electrical resistivity in the range 0.01–10,000 ohm-cm.

Light cured materials have become regularly used in dentistry. The advantages of light curing a one-part material over a two-part system are well documented. The ability to cure on command offers the dental practioner a wide degree of control over the shape and shade of a dental restoration. This inventor has discussed various methods of delivering heated dental materials, which because of the heating effect causes these materials to take on superior handling characteristics as well as improved physical properties in the polymerized state.
In the case of dental composite fillings, all these methods relate to either heating them in syringes, in compules in which they are delivered or simply heating the material directly in an external device.
New research on dental materials has shown many benefits to heating these materials prior to polymerization. Demonstrated advantages are as follows:                1. Substantially faster monomer conversion (shorter curing time) (IADR—0819 Thermal Effects on Composite Photopolymerization Monitored by Real-time NIR By Drs. M. Trujillo and J. W. Stansbury, University of Colorado Health Sciences Center, Denver, Colo., USA).        2. Greatly reduced viscosity (IADR—Composite Film Thickness at Various Temperatures By Drs. R. G. Holmes, J. S. Blalock, and F. A. Rueggeberg, Medical College of Georgia, Augusta, Ga. USA).        3. Much greater material flow offering better adaptation to tooth surface (Dr. Broome, Associate Professor, University of Alabama School of Dentistry, Birmingham, Ala., USA) Report to AdDent Quantification of Flow Increase Resulting from Preheating Composite Compules dated Jun. 6, 2003).
Recently, research has also shown that when a composite is preheated, we can achieve much less microleakage at the cervical margin of a dental restoration (IADR—Effect of Pre-Heating Composite on Microleakage in Class II Restorations By M. N. Aksu, A.-M. L. Neme, S. Walker, F. E. Pink, J. B. Linger, and W. C. Wagner, University of Detroit Mercy, Mich., USA). Microleakage is a major factor in causing decay under a dental restoration.
The use of heated dental restorative materials has been described in U.S. Pat. Nos. 6,236,020 and 6,616,448. A method for using heated dental materials has been described in U.S. Pat. No. 6,320,162. In both of these earlier applications, I described a method and a device for heating dental materials. In the devices used in my previous applications, a widely used compule that stores the material is heated externally. One method uses a heater placed in a block of thermally conductive material another method uses a heating element embedded in a molded plastic holder that is also part of a means for dispensing material.
Previous attempts to warm dental materials have either done so in a laboratory oven or in the container it is packaged in such as a syringe or compule. While these methods work for introducing heated composite materials into the mouth, they suffer from several drawbacks. In the case of heating a syringe, a large bulk of material is heated needlessly, and the heating time is long. In the case of heating a compule (dose package), the heating time is shortened but still significantly long. In the case of heating material expressed from a syringe onto a heated surface, the material needs to be first picked up, then introduced into the dental cavity and then repeated with each layer, also in a time consuming procedure. The invention described herein eliminates these drawbacks. In this invention, the heat is generated directly within the compule itself, and in so doing, creates a very efficient method of heat transfer from the source of heat directly into the material to be heated.
Many dentists have found it useful and convenient to dispense restorative composite, root canal filling materials; dental bleach as well as dental sealants and coatings directly from a pre dosed compule. Currently, the various compules on the market are made from polyethylene either high (HDP) or low density (LDP) as well as other commonly used plastics.


A semiconductor device includes (a) a semiconductor substrate, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a wiring layer having a thickness T and a width W1 greater than the thickness T formed on the first interlayer insulating film, the wiring layer being divided into a plurality of wiring layer segments each of which has a width W2 equal to or smaller than the thickness T, and (d) a second interlayer insulating film covering the wiring layer segments therewith. The semiconductor device ensures that even when a second interlayer insulating film is formed on a wiring layer by means of bias sputtering or bias CVD, projections are not formed on the second interlayer insulating film above the wiring layer. Namely, it is possible to completely planarize the second interlayer insulating film.

1. Field of the Invention
The invention relates to a semiconductor and a method of fabricating the same, and more particularly to a wiring layer made of metal such as gold and a method of fabricating the same.
2. Description of the Related Art
As semiconductor elements become smaller, it is absolutely necessary to use a multi-layer wiring structure. An interlayer insulating film for a semiconductor device having such a multi-layer wiring structure, may include an insulating film made of silicon dioxide having a small dielectric constant and uniform quality for reducing parasitic capacitance between an upper wiring layer and a lower wiring layer or between wirings in a common wiring layer.
Further, as semiconductor elements become smaller, a width of wirings in a lower wiring layer and a spacing between adjacent wirings in a wiring layer are smaller. However, a wiring is required to have a cross-sectional area greater than a certain value in order to avoid increasing wiring resistance. As a result, an aspect ratio of the wiring defined by a thickness of the wiring divided by a width of the wiring, and an aspect ratio between wirings defined by a thickness of the wiring divided by a spacing between the wiring and an adjacent wiring both increase. In addition, it is required to planarize a surface of an interlayer insulating film which covers a lower wiring layer. If there were a large step at a surface of an interlayer insulating film, it would not be possible to form a fine photoresist pattern because of shortage of a focus margin in photolithography, when an upper wiring layer is formed on such an interlayer insulating film. The large step would bring problems of breakage of an upper wiring layer and generation of etching residue of material of which an upper wiring layer is made. For those reasons, an interlayer insulating film to be formed covering a lower wiring layer is required to have a flat surface.
In addition, when an interlayer insulating film is formed covering a wiring layer made of aluminum, a temperature at which an interlayer insulating film is formed has to be equal to or smaller than about 450.degree. C., which is a melting point of aluminum.
Bias sputtering and chemical vapor deposition (CVD) employing bias ECR may be used to form an interlayer insulating film for a multi-layer wiring structure made of aluminum or similar metal. The bias sputtering and bias ECR CVD correspond to improved sputtering and ECR plasma. According to the bias sputtering and bias ECR CVD techniques, projections of an interlayer insulating film which are formed simultaneously with deposition of an interlayer insulating film are cut off by virtue of a bias voltage. Thus, an interlayer insulating film is planarized at its upper surface.
However, bias sputtering and bias ECR have a problem that an interlayer insulating film formed on a wiring having a narrow width can be readily planarized, but an interlayer insulating film formed on a wiring having a wide width is quite difficult or impossible to planarize.
The above mentioned problem is explained hereinbelow in detail with reference to FIGS. 1 and 2. FIG. 1 is a plan view of a wiring layer constituted of three wirings 103, 104 and 105, and FIG. 2 is a cross-sectional view taken along the line II--II in FIG. 1.
As illustrated in FIG. 1, there are formed three wirings 103, 104 and 105 on a silicon substrate. Specifically, as illustrated in FIG. 2, a first interlayer insulating film 102 is formed on a silicon substrate 101, and the wirings 103, 104 and 105 are formed on the first interlayer insulating film 102. The wirings 103, 104 and 105 make a wiring layer. The wirings 103, 104 and 105 have a common thickness, but have different widths. That is, the wiring 104 is greater than the wiring 103 in width, and the wiring 105 is greater than the wiring 104 in width.
A second interlayer insulating film 106 is formed on the wirings 103 to 105 by bias sputtering or bias ECR-CVD so that the second interlayer insulating 106 fully covers the wirings 103 to 105. As illustrated in FIG. 2, the second interlayer insulating film 106 has a completely flat surface above the wiring 103 having the smallest width among the wirings. In contrast, there is produced a triangular projection 107a at a surface of the second interlayer insulating film 106 above the wiring 104 having a width greater than that of the wiring 103. Similarly, there is produced a trapezoidal projection 107b at a surface of the second interlayer insulating film 106 above the wiring 105 having a width much greater than that of the wiring 103.
As mentioned earlier, bias sputtering and bias ECR-CVD are quite useful for forming an interlayer insulating film, when there is fabricated a semiconductor device having a multi-layer wiring structure. However, when an interlayer insulating film is formed by those methods, it would be quite difficult to planarize the interlayer insulating film above wirings having a wide width, as having been explained with reference to FIGS. 1 and 2.
As a result, when an upper wiring layer is formed on an interlayer insulating film as the film 106 illustrated in FIG. 2, the upper wiring layer may be broken or may have an undesirable pattern. Such a problem is more remarkable, as a multi-layer wiring structure is made smaller in size.
In addition, if a through hole is intended to form throughout such an interlayer insulating film as the film 106 illustrated in FIG. 2, it is often impossible to form a through hole passing through projections formed on an interlayer insulating film, such as the triangular projection 107a and the trapezoidal projection 107b illustrated in FIG. 2.
One of solutions to the above mentioned problems has been suggested in Japanese Unexamined Patent Publication No. 2-22843 published on Jan. 25, 1990. The Publication suggests a semiconductor device comprising a semiconductor substrate, a first electrode or wiring formed on the substrate, an interlayer insulating film formed over the first electrode or wiring, and a second wiring formed on the interlayer insulating film, the second wiring being in electrical connection with the first electrode or wiring through a contact hole, characterized by a split pattern contact through which the first electrode or wiring makes contact with the second wiring.
However, the above mentioned Publication does not fully overcome the problems as mentioned above.