Applications and users dynamically make QoS provisioning requests for individual traffic flows traversing client and server hosts. A traffic flow provisioning request is conveyed to a services manager, which determines a set of traffic attributes for the flow and determines the networks the flow traverses between the client and server hosts. The services manger then oversees the admission of the flow to appropriate traffic classes in each determined network and the obtaining of a DSCP value for each network. Lastly, the services manger conveys the DSCP value of the first network traversed back to the client or server host, depending on the direction of the flow, which host is then configured to appropriately mark the DSCP field of the traffic flow packets. In a further embodiment, the services manager also instructs the client or server host to perform packet policing and shaping for the flow.

Users have an increasing need to dynamically prioritize the individual traffic flows of application sessions traversing IP (Internet Protocol) based networks, such as enterprise networks and VPN-type services provided by Internet Service Providers. An application session, for the purposes of this discussion, is a connection between any given instance of a client application and a server application, wherein the session comprises one or more individual traffic flows. The need to prioritize traffic flows exists because networks are carrying increasingly diverse traffic types that all compete for network resources. When a given traffic flow has particular bandwidth, latency, and packet loss requirements (i.e., particular quality of service (QoS) needs), other network traffic can consume network resources and thereby adversely affect the flow. Network administrators will typically use Diff Serv (differentiated services) enabled networks to allocate network resources to critical applications so that the performance needs of these application sessions are met.
Specifically, a Diff Serv enabled network allows heterogeneous traffic types from different application sessions to co-exist while at the same time allocating these varying traffic types different network resources based on the needs of the application. As indicated, some traffic types have bandwidth, latency, and packet loss requirements that the total mix of traffic on a network can adversely affect. Diff Serv allows a network administrator to establish traffic classes in the network by allocating network resources to each class. (In general, traffic classes are established by configuring the network routers to support varying packet queuing and forwarding techniques and thereby providing different throughput, latency, and loss services for each class). Application sessions are then assigned to these classes and are thereby generally able to receive a certain quality of service.
Traffic classes are not specific to any given user, application, or session. Rather, any given traffic class will typically carry data packets from many different applications originating from many different users. In particular, edge routers of the network (or a dedicated hardware coinciding with the router) assign packets from application sessions to traffic classes. The edge routers analyze each packet as it enters the network, classifying the packet according to an assigned traffic class, and insert a specific Differentiated Services Code Point (DSCP) value in the DSCP field of the packet based on the assigned traffic class. The network routers use a packet's DSCP value to process the packet according to the assigned traffic class. The edge routers also typically condition the traffic before forwarding it into the network. Traffic conditioning includes packet shaping, dropping, and policing. Policing ensures that any given application session does not utilize more bandwidth than associated with the assigned service. Importantly, for edge router performance reasons, the network administrator typically configures the edge routers to assign traffic flows to traffic classes on an application and site basis. In other words, all traffic flows from a given application session from a set of designated sites are assigned to the same traffic class.
Although the traditional approaches to Diff Serv can provide critical applications with the required resources to the meet the application needs, these approaches have several drawbacks. In particular, there are an increasing number of application sessions that users want to prioritize. At the same time, however, very often only a particular traffic flow from a given session requires prioritization. Similarly, users often want to dynamically decide when a given application session receives prioritized service and when it does not. However, typical Diff Serv approaches are not sufficiently scalable and dynamically configurable to meet the increasing number of applications sessions and individual user needs. Another issue is that Diff Serv approaches are often susceptible to unpredictable traffic loads.
More specifically, the assignment of application sessions to traffic classes is static under Diff Serv. Once a network administrator configures the edge routers to mark specific application packets, all application sessions for that application from a set of designated sites are assigned to the given traffic class and these configurations are essentially static. This is problematic because in any given instance, a user may decide that a given application session requires the services of a particular traffic class and the network administrator has not configured the edge routers to assign that user to the class or, similarly, may not have assigned that given application to a traffic class. In addition, users often determine that a given session does not require the services of a given traffic class or requires a higher service. One solution to these issues is for a user to dynamically contact the network administrator for reconfiguration of the edge routers on a per need basis. However, this is both time-consuming and unusable from a user perspective and unfeasible from an administrative perspective.
A similar issue is that the network resources are limited. Accordingly, administrators must take care when configuring the edge routers to not over admit application sessions/users to the traffic classes. However, not all admitted users simultaneously run application sessions, which results in administrators essentially underestimating the number of application sessions that should be allowed access to a traffic class and thereby under-utilizing the network resources. Similarly, it is usually only a given traffic flow within a given session that actually requires the services, causing traffic classes to often carry unnecessary data packets. Accordingly, administrators should allocate network resources on a per-traffic flow basis and when specifically needed. Again, such a system is time consuming and unusable from a user perspective and unfeasible from an administrative perspective. In addition, such continuous/dynamic assignment of traffic flows to traffic classes is not scalable, which is further described below.
Similar issues exist in network environments where IP addresses are dynamically assigned through DHCP (Dynamic Host Configuration Protocol) and therefore dynamically change. In this environment, network administrators are required to constantly reconfigure the edge routers as IP addresses are re-assigned to network users or are forced to assign applications to traffic classes at a more coarse level, disregarding the individual sites. Again, quality of service is more appropriately designated on a per user/application session level.
A second issue with traditional Diff Serv approaches is that they are not scalable. On a fundamental basis, as more users are added to a network and/or as administrators increase the number of applications requesting traffic class services, the edge routers correspondingly must perform additional packet filtering/marking/conditioning/policing responsibilities. At some point, the functional ability of the edge routers is reached, thereby causing the administrators to have to add additional edge routers to the network at additional cost. Similarly, as the edge routers are configured to admit more application sessions, the internal network resources must also be increased. However, as described above, the number of application sessions simultaneously needing the network resources is usually less than the number the edge routers are configured to admit, thereby causing network administrators to over provision the network.
Similarly, as described above, quality of service is more appropriately designated on a dynamic user basis at the traffic flow level. Again, edge router performance issues will occur if routers are made to mark and condition at the traffic flow level, especially as users and applications are added to the network. In addition, continuously configuring and reconfiguring edge routers on a per user basis compromises edge router performance.
A third issue with the traditional Diff Serv approaches is admission control. Typically, when configuring network resources to establish traffic classes, an administrator approximates the number of instantaneous application sessions that will occur and the traffic classes each should be assigned to. As long as the number of simultaneous application sessions for a given traffic class does not exceed the configured approximation, each session will receive adequate resources. However, an unexpected number of sessions for a given traffic class can occur, which results in performance degradation across the class causing no session to receive adequate resources. One solution to this is to over-provision the traffic class, but this wastes network resources.
Prior solutions have only partially addressed the above issues, including systems referred to as bandwidth broker systems. A bandwidth broker is a network management system that provides admission control and bandwidth management for Diff Serv enabled networks by tracking the amount of bandwidth being used in each traffic class. When an application session requires the services of a traffic class, the application makes an admission request to the bandwidth broker, providing the bandwidth and the traffic class being requested. The bandwidth broker determines whether sufficient bandwidth is available in the respective traffic class. If there is sufficient bandwidth, the bandwidth broker decreases the amount of available bandwidth for the traffic class, and configures the appropriate edge router to mark, condition, and police the new traffic. Otherwise the new session is denied admission.
Advantageously, bandwidth broker systems prevent traffic classes from becoming over-utilized thereby preventing performance degradation; they allow for dynamic/automatic application controlled QoS management; and, they allow for better utilization of internal network resources. However, the systems have several disadvantages. First, bandwidth broker systems fail to address the scalability issues described above. While these systems are suitable for small-scale networks, edge routers are not capable, from a performance perspective, of marking/conditioning/policing numerous application sessions or worse, traffic flows, and are compromised as users increasingly make numerous configurations/reconfigurations on a dynamic basis. A second issue is that applications must be specifically designed/programmed to communicate with bandwidth broker systems and, as such, applications are not easily integrated into the framework making bandwidth broker systems difficult to use. More specifically, an application developer must understand the low-level detailed traffic attributes of the application sessions the application will generate and translate these attributes into one of the traffic classes supported by the network so that the actual traffic class request can be made to the bandwidth broker. This issue becomes worse if an application session needs to traverse several networks, each with different traffic classes and managed by different bandwidth brokers. Here, the application developer must make the traffic-attributes to traffic-class translation for each network/bandwidth broker. In addition, the developer must determine which networks a given session will traverse in order to communicate with the appropriate bandwidth brokers.

Scalable and dynamic quality of service control


A polarized beam splitter is provided for transmitting a beam of linearly polarized light vibrating in a predetermined plane. A titanium diffused layer is developed on the lithium niobate substrate and then, a portion of the same is treated by proton exchange thus forming a proton exchanged region. The boundary surface between the titanium diffused and proton exchanged regions is used as a polarizing plane allowing an incoming polarized light vibrating in the predetermined plane to pass through and a polarized light vibrating at a right angle to the plane to reflect.

1. Field of the Invention
The present invention relates to a polarized beam splitter for transmitting or reflecting a beam of incoming polarized light according to its plane of polarization.
2. Description of Background Information
Polarized beam splitters for transmitting one of two linearly polarized light beam, the polarization planes of which are at a right angle to each other and for reflecting the other are widely used as an optical splitter or a light propagation shifter disposed in optical application apparatuses. Such known polarized beam splitters are generally made of calcite or quartz, e.g. Wollaston prism, or may be formed by coating a prism with a dielectric material.
FIG. 1 illustrates the arrangement of a known polarized beam splitter using prisms. As shown, a polarized beam splitter 1 consists mainly of two right-angle prisms 1a and 1b with their base sides coated with layers of dielectric material and cemented to each other with an adhesive. The prism 1 is arranged so that the cemented area 1c (referred to as a dielectric layer hereinafter) allows a linearly polarized light vibrating vertically (referred to as an S polarized light) to pass through and a linearly polarized light vibrating horizontally (referred to as a P polarized light) to reflect. Also, the dielectric layer 1c is arranged at 45.degree. to the direction of incident of an incoming light A.
A beam of S polarized light A is introduced to pass through the prism 1 and through a quarter wave plate 2 prior to reflecting on a mirror 3. A reflected beam from the mirror 3 passes again through the quarter wave plate 2 and returns to the prism 1. The quarter wave plate 2 has a thickness equal to 1/4 the optical path length of a transmitting light, thus shifting the polarization of the linearly polarized light by 90.degree. through two pass actions. Accordingly, the reflected beam becomes a P polarized-light which is reflected by the dielectric layer 1c and propagates at a right angle to the incident direction of the incoming or S polarized light A, as shown in FIG. 1.
The disadvantages of such a prior art polarized beam splitter are however that its production and the assembly and adjustment of its components are troublesome and not suited for automated manufacturing. Also, its three-dimensional construction in principle is hardly reducible in size and particularly, in thickness.

Light waveguide type polarized light beam splitter


Power save proxy functionality can be implemented to enable power save devices to switch to a power save mode and still receive communications from legacy communication devices. A first communication device determines that a second communication device is in a power save mode. The first communication device designates itself as a power save proxy for the second communication device that is in the power save mode. In response to detecting packets that are transmitted from a legacy communication device to the second communication device, the first communication device transmits a control message to the second communication device to request the second communication device to exit the power save mode, transmits a hold control message to the legacy communication device to request the legacy communication device to temporarily stop transmitting packets to the second communication device, or stores the packets intended for the second communication device.

Embodiments of the inventive subject matter generally relate to the field of communication systems and, more particularly, a power save proxy in a communication network.
Communication devices typically implement power saving mechanisms by operating in a power save mode to conserve power and to reduce energy consumption. In the power save mode, the communication device can periodically transition between an awake sub-state and a sleep sub-state. The communication device can temporarily suspend transmission and reception of packets, thus reducing the average power consumption associated with the communication device. The duration of the awake sub-state and the sleep sub-state in the power save mode can influence the amount of power that can be saved at the communication device.

Power save proxy in communication networks


An information asset management system in a network environment includes a monitoring program 11 that monitors operation events performed by users and creates terminal logs 12, a terminal log collection program 21 that stores an integrated log 22 created by collecting the terminal logs 12, and a correlation analysis program 31 that analyzes the whereabouts of information assets using the integrated log 22. When the user exports an information asset from the network environment and when the user imports the information asset into the network environment, the monitoring program 11 monitors these export and import events including feature values of the information assets. The correlation analysis program 31 compares a pre-export feature value of each information asset with a post-import feature value of each information asset to determine whether the information assets are identical and reports a list of information assets in the organization.

The present invention relates to an information asset management reporting technology for visualizing and reporting the whereabouts of information assets under management of an organization.
Information such as personal information or trade secrets in an organization has recently been increasingly computerized. The computerized information is provided as files on a computer or as data in a memory. Leakage of files containing such information frequently occurs, causing significant damage. In the following description, a file containing confidential information such as personal information or trade secrets will be referred to as an "information asset". Since such information assets are files, they are easily duplicated, transferred, and processed and it is difficult to manage and determine their whereabouts (or locations). It is nearly impossible to determine usage of information assets such as how and by whom they are used. For example, it is very difficult to cope with accidental leaks such as leakage of information assets that were duplicated without the user's knowledge or leakage of information assets due to forgetting to delete them although they should be deleted according to the rules of the organization.
Outsourcing companies mostly conduct work using information assets received from customers. Outsourcing companies should delete information assets received from customers after the term of the outsourcing contract expires. Thus, it can be easily expected that outsourcing companies need to prove to customers that they have properly handled the information assets and also to delete the information assets without leakage after the term of the contract expires.
To deal with the risk of authorized users easily taking (or exporting) information assets or copies of information assets outside a network environment under management or a file management system (hereinafter referred to as a "network environment"), Japanese Unexamined Patent Application Publication No. 2006-518893 (Document 1) suggested a system that monitors and reports usage of information assets in the network environment to a manager, thereby easily detecting unexpected behavior patterns. With knowledge of where information assets under management of an organization are present, this system can detect, for example, whether or not any file has been sent as an email attachment, whether or not any file has been uploaded to a common storage region on the Internet, and whether or not any file has been written to a Universal Serial Bus (USB) flash memory or CD-Recordable (CD-R)/Digital Versatile Disk Recordable (DVD-R).
Google has introduced "Enterprise Solution" (URL:http://www.google.co.jp/enterprise/) (Document 2). To determine where information assets are present in a network environment, this system crawls files and indexes the contents of the files to find information assets at high speed. This system permits a user who desires to find an information asset to quickly locate the information asset simply by specifying a keyword.
According to a system disclosed in Japanese Patent Application Publication (JP-A) No. 2005-109779 (Document 3), to prevent an encrypted file from being decrypted at an arbitrary Personal Computer (PC), a dependent file for generating a decryption key is stored in specific PCs so that the decoding key can be generated only at the specific PCs which contain the dependent file. Even if information assets are exported to an arbitrary PC, this system prevents leakage of the information assets by preventing decryption of the information assets at the PC.

Information asset management system, log analysis server, log analysis program, and portable medium


A vaporizer device includes a resistive heating element; circuitry configured to control delivery of electrical power to the resistive heating element from a power source; and a controller configured to perform operations including: receiving inputs representative of a power delivery to the resistive heating element, a temperature of the resistive heating element, and/or a flow rate of air past the resistive heating element; predicting, using the received inputs, an amount of evaporation of the vaporizable material at the resistive heating element; and controlling the power delivery to the resistive heating element in response to the predicted amount of evaporation of the vaporizable material, the controlling including increasing or decreasing an instantaneous power delivery to the heating element such that a target aerosol yield is produced. Related devices, systems, methods, and articles are also described.

Vaporizer devices, which include and/or may be referred to as electronic inhalable aerosol devices, vaporization devices, electronic vaping devices, and/or electronic aerosol devices, typically utilize a vaporizable material that is vaporized to create an aerosol vapor capable of delivering an active ingredient to a user. Maintaining some degree of control of the temperature of the resistive heater is generally desirable, for example, to avoid overheating of the vaporizable material, to ensure that sufficient heat is available to form the aerosol, to maintain longer battery life of the vaporizer device, and the like.


In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set, several embodiments are presented for granting higher priority processing to the designated thread. For example, more instructions from the higher priority thread may be executed as compared to the lower priority thread. Also, a higher priority thread may be given comparatively more access to a given resource, such as memory or a bus.

The present invention pertains to the operation of a processor or the like. More particularly, the present invention pertains to establishing priority of a thread in a multi-threaded processor.
As is known in the art, a processor includes a variety of sub-modules, each adapted to carry out specific tasks. In one known processor, these sub-modules include the following: an instruction cache, an instruction fetch unit for fetching appropriate instructions from the instruction cache; decode logic that decodes the instruction into a final or intermediate format, microoperation logic that converts intermediate instructions into a final format for execution; and an execution unit that executes final format instructions (either from the decode logic in some examples or from the microoperation logic in others).
Programming code to be executed by the processor can sometimes be broken down into smaller components referred to as "threads." A thread is a series of instructions whose execution achieves a given task. For example, in a video phone application, the processor may be called upon to execute code to handle video image data as well as audio data. There may be separate code sequences whose execution is designed to handle each of these data types. Thus, a first thread may include instructions for video image data processing and a second thread may be instructions for audio data processing.
In some multi-threaded processors, the processor may switch between execution of two or more threads. In other multi-threaded processors, the threads may be executed simultaneously. In either of these processors, there is no delineation between how the threads are treated. In particular, code from one thread is given the same priority as code from another thread. This could lead to a negative impact on overall system performance, especially when execution of critical code is suspended or slowed by the execution of non-critical code.
In view of the above, there is a need to establish priority between two or more threads.

This patent is subject to a terminal disclaimer.

Establishing thread priority in a processor or the like


A method of optimizing a chemical reaction in a plate-type open reactor, the method consisting in:                establishing a dynamic model of the reactor for a given reaction on the basis of a model of the reactor and its heat exchanges;        applying an integration software tool to the dynamic model in order to solve the above-mentioned equations;        determining and optimizing a set of dimension and/or operation parameters of the reactor on the basis of evaluating targets to be achieved, constraints to be complied with, and variable data for the reactor and/or the reaction;        building a plate reactor of the said type accordingly to the set of optimized parameters; and        doing measurements of physical parameters during the execution of said reaction in the built reactor, for validating its operation.

The present invention relates to a method of optimizing a chemical reaction in a plate-type open reactor constituted by a stack of plates defining between them at least one block having a reaction chamber and two side chambers for circulating a heat-exchange utility fluid.
Attempts are being made at present to optimize the running and to improve the yield of chemical reactions in general, which reactions are usually implemented in batch type reactors, i.e. reactors that operate discontinuously, comprising vessels in which determined quantities of reagents are placed and mixed together, and subsequently subjected to environmental conditions (pressure, temperature, pH, etc.) optimized for promoting the reactions.
A major drawback of such reactors is the difficulty of removing the heat produced by a reaction, which puts constraints on controlling and optimizing the reaction.

Optimizing a chemical reaction in a plate-type open reactor


An imaging apparatus for two-stage light modulation in high-definition digital projection or cinema can include two light modulators. Each light modulator can include a multi-chip imaging system coupled to a total internal reflection prism (TIR) system, which has a light input face and an on-state face. Relay optics can be positioned between the two light modulators. The relay optics can be configured to defocus light received from the pre-modulator and to provide defocused light to the prime modulator using a substantially Gaussian pixel shaping function. The prime modulator can be oriented to receive defocused light from the relay optics at the light input face of its TIR prism system. The pre-modulator can be oriented backwards, so as to receive source light at the on-state face of its TIR prism system and to output pre-modulated light to the relay optics via the light input face of the TIR prism system.

In imaging apparatuses, such as digital projection systems, dynamic range of an image is limited by the capabilities of the chosen imager. This applies to digital light processing (DLP) imagers (e.g., digital micromirror displays), liquid crystal on silicon (LCOS) imagers, liquid-crystal display (LCD) imagers, as well as imagers using other technologies. Two-stage modulation can be used to increase dynamic range as well as improve contrast ratio. However, many known two-stage modulation systems are inefficient and do not provide dynamic range that is suitably high or do not provide adequate contrast ratio.

Two-stage light modulation for high dynamic range


A communication apparatus which transmits information on a position at which the communication apparatus is positioned is disclosed. The communication apparatus includes a detecting unit which detects one of a first signal which is detected when the communication apparatus is fixed to an installed location and a second signal which is detected when the communication apparatus is brought to a state in which it is not fixed to the installed location; a storage unit which stores therein the position information; and a control unit which erases the position information stored in the storage unit when the second signal is detected after the first signal is detected by the detecting unit.

Various position information management systems are being proposed which grasp and manage a position of a wireless terminal, or a person or an article having the wireless terminal in a facility in which an accurate positioning using GPS, etc., is difficult.
Patent document 1 discloses a system in which a passive RF (Radio Frequency) tag attached to a person is read with a fixed RF (Radio Frequency) reader/writer and a position thereof is reported to a different wireless terminal, etc.
Patent document 2 discloses a system in which a wireless terminal converts an identifier which is wirelessly transmitted from a neighboring transmitter to position specifying information to specify an own position.
Patent document 3 discloses a system in which a wireless terminal receives specific information transmitted from a lighting apparatus and transmits the specific information to a server to specify a position of the wireless terminal.
However, with the system in Patent document 1, a large number of RF (Radio Frequency) reader/writers needs to be installed in order to read the passive RF (Radio Frequency) tag with a narrow range in which communications are possible, which may lead to higher cost in implementing the infrastructure.
Moreover, with the system in Patent document 2, power consumption of the wireless terminal may become high depending on a communications scheme between the wireless terminal and a server.
Furthermore, also in the system in Patent document 3, power consumption of the wireless terminal is not taken into account as in Patent document 2. Moreover, in a server, in order to specify the position of the wireless terminal, it is necessary to search a position associated with the specific information, which could lead to a higher computation cost.

Communication apparatus, position information management system, and position information management method


Provided is an aerosol manufacture facility including an aerosol generator (600), an aerosol heater (604), an aerosol cooler (604), a particle collector (606), a precursor liquid supply system (608), a carrier gas supply system (610), and a cooling gas supply system (612), and optionally other components. Also provided is an aerosol method for manufacturing particles in the aerosol manufacture facility, which, in one embodiment, involves automated process control.

Powdered materials are used in many manufacturing processes. One large use for powders is for thick film deposition to prepare films of a variety of materials. Some thick film applications include, for example, deposition of phosphor materials for flat panel displays, and patterning of electrically conductive features for electronic products.
For thick film applications, and for other applications, there is a trend to use powders of ever smaller particles. Generally desirable features in small particles include a small particle size; a narrow particle size distribution; a dense, spherical particle morphology; and a crystalline grain structure. Existing technologies for preparing powdered products, however,often could be improved with respect to attaining all, or substantially all, of these desired features for particles used in thick film applications.
One method that has been used to make small particles is to precipitate the particles from a liquid medium. Such liquid precipitation techniques are often difficult to control to produce particles with the desired characteristics. Also, particles prepared by liquid precipitation routes often are contaminated with significant quantities of surfactants or other organic materials used during the liquid phase processing.
Aerosol methods have also been used to make a variety of small particles. One aerosol method for making small particles is spray pyrolysis, in which an aerosol spray is generated and then converted in a reactor to the desired particles. Spray pyrolysis systems have, however, been mostly experimental, and unsuitable for commercial particle production. Furthermore, control of particle size distribution is a concern with spray pyrolysis. Also, spray pyrolysis systems are often inefficient in the use of carrier gases that suspend and carry liquid droplets of the aerosol. Moreover, spray pyrolysis systems are frequently operated in batch mode, and there is a significant potential for inefficiency during transient periods during the early and late stages of particle production. During these periods, variations in particle properties may degrade the quality of the entire batch.
There is a significant need for improved manufacture techniques for making powders of small particles for use in thick film and other applications.

Aerosol method and apparatus for making particulate products


A climate control system (10) for a cab/berth of a vehicle, comprises a climate control circuit (12) in which a first refrigerant circulates between at least an energy accumulator (20) in which an accumulator refrigerant is in heat exchange with the first refrigerant, a radiator (22) in the cab/berth to adjust a temperature of the cab/berth, and a heat-exchange unit (23). A refrigeration circuit (14) is provided for submitting a second refrigerant to a refrigeration cycle. An evaporation stage (43) is in heat-exchange relation with the heat-exchange unit (23) of the climate control circuit (12) such that the second refrigerant absorbs heat from the first refrigerant. A controller system (50) is powered by an electric power source (A) of the vehicle and selectively actuates the climate control circuit and the refrigeration circuit (14) so as to store cold or hot energy in the energy accumulator (20) when the electric power source (A) is charged, and selectively actuates the climate control circuit (12) to cool the cab/berth with the radiator (22).

1. Field of the Invention
The present invention generally relates to ventilation systems for vehicles and, more particularly, to a heating and air-conditioning system for berths and cabs of a plurality of types of vehicles.
2. Background Art
Cabs of road transport vehicles are often equipped with sleeper berths, which consist of resting accommodations for the driver. Road transport vehicles often travel over long distances, whereby sleeper berths are provided for the driver to recuperate. Similarly, recreational vehicles have self-contained living berths for the vehicle occupants.
In order to maintain suitable climate conditions, sleeper berths and living berths are typically provided with HVAC systems (i.e., heating, ventilating and air-conditioning systems) that treat, heat and/or cool the air that is fed to the berths/cabs, so as to provide adequate resting conditions for its occupants.
Berths, and cabs of specific types of vehicle (e.g., cranes, service vehicles, buses, cars and other passenger vehicles), often accommodate occupants while the engine is turned off as well as when the vehicle is in operation. Accordingly, the actuation of such ventilation systems is of concern, in that the engine may be turned off while the HVAC systems has to work, whereby the alternator associated with the engine does not maintain the voltage level of the electrical systems of these vehicles. In various instances, no external power supply is available, whereby some ventilation systems of berths and cabs are powered by the electrical system of the vehicle. In order to avoid the discharge of the batteries of the electrical systems while heating or cooling berths or cabs, vehicle engines are kept on so as to keep, for instance, the alternator in a charging mode for the electrical system.
Accordingly, some uses of such ventilation systems involve vehicle fuel consumption, either by requiring that the engine be turned on to operate, or by affecting the performance of the vehicle by being mechanically related to the engine. This results in combustion by-product emissions. Therefore, not only are such ventilation systems costly to operate because of fuel consumption, they also have a negative effect on the environment.

Climate control system for vehicle berths and cabs


The invention proposes a method of managing an electronic circuit of the type comprising a memory (EEPROM) for the storage of confidential information, the method comprising masking variations of the electrical current (I) consumed by the electronic circuit, during a fraction of the time only (ti-tj), at least during the portion(s) of time during which an instruction bearing on confidential data is executed, and notably an instruction for reading out from the memory (EEPROM).

FIG. 1 is a block diagram showing the internal architecture of such an electronic circuit. A central processing unit (CPU) exchanges data with internal peripheral units by means of a data bus DB. These peripheral units comprise a first read only memory ROM for permanently storing a management program. They also comprise a second read only memory which is an electrically erasable and programmable read only memory (EEPROM) for permanently storing confidential information. They further comprise a random access memory RAM for temporarily storing information connected with the operation of the circuit. In general, they also comprise at least one register Reg for storing binary information.
The invention applies notably to a microcontroller for an IC card, also known as a smart card. The confidential information stored in the EEPROM would for example be a personal code known only to the user. This personal code must be supplied by the user for using an apparatus such as a cash dispenser, a pay TV decoder, a GSM type mobile telephone, etc . . . in combination with the IC card.
The IC card is classically inserted inside a card reader of the apparatus. The IC card comprises contact pads cooperating with corresponding terminals of the reader for exchanging data between the card and the reader, and for supplying electrical power to the IC card using an electrical power supply at the reader. The apparatus comprises a keyboard or similar device by means of which the user enters his personal code. The personal code entered by the user is sent to the microcontroller of the IC card, which comprises means for comparing it with the personal code stored in the EEPROM. In case of agreement, the user is given access to the service provided by the apparatus.
A typical attempt to fraud consists in using a stolen IC card in a pirated IC card reader comprising means for observing the data placed on the data bus DB. It is then theoretically possible to see on the data bus DB the confidential data corresponding to the user's personal code when these data are read from the EEPROM and inserted on the data bus DB. The only difficulty for the pirate user is knowing at what precise moment these data appear on the data bus DB so as to identify them amongst the flow of data transiting on that bus when the electronic circuit is in operation.
Now, it is observed that the electrical current consumed by the electronic circuit during operation is not constant but exhibits variations as a function, amongst others, of the reading operations carried out in different memories of the electronic circuit. Indeed, the memory cells of the different memories exhibit an impedance which, to a certain extent, depends on the programmed or erased state of the cell but which—to a larger extent—varies from one type of memory to another.
In FIG. 2, curve 21 thus indicates the time variations of the electrical current I consumed by the microcontroller during operation. This current can take on different increasing values I(Reg), I(ROM), I(RAM), I(EEPROM) for readout operations respectively in the register Reg, the ROM memory, the RAM memory or the EEPROM memory. Accordingly, in order to know the confidential data read from the EEPROM it only requires the pirate user to observe the instantaneous electrical current consumed by the microcontroller (using appropriate means such as an ammeter in series between a power supply terminal of the reader provided for electrically supplying the IC card and the corresponding contact pad of the latter) and to note down the data present on the data bus DB at the moment when this current exhibits the value I(EEPROM).
In order to prevent this type of fraud, there has already been proposed means for masking the variations in the current consumed by the electronic circuit during operation, such means acting so that the current consumed by the electronic circuit in operation continuously has a same value Iconst. The latter is greater than the highest current normally consumed by the electronic circuit during operation. An example of such means is described in patent application EP-A-0 500 461, where they are used to mask variations in the consumed current during a memory readout operation due to the programmed or erased state of the memory cells. They comprise for instance a constant current source (of constant value Iconst) connected in series with the memory cells between the positive power supply terminal Vcc and ground, as well as resistor connected in parallel with the memory cells.
In FIG. 2, the current (constant at value Iconst) consumed by the electronic circuit according to this prior art is depicted by curve 22, which substantially corresponds to a horizontal line. The weak ripples in curves 21 and 22 correspond to spurious impedances in the electronic circuit.
This known solution nevertheless has the drawback of significantly increasing the electronic circuit's current consumption. Indeed, the current consumed by the electronic circuit in operation is continuously equal to the value Iconst which is greater than the maximum value of the current consumed in itself by the electronic circuit during operation. This high consumption generates problems connected notably with temperature rises in the electronic circuit due to the Joule effect.

Electric circuit management method and device


Defibrillator lead designs and methods for manufacturing a lead having a fibrosis-limiting material covering, a shocking coil electrode, and an implantable lead body are disclosed herein. The shocking coil electrode includes at least one laser welded portion.

Cardiac and other defibrillation systems typically include an implantable medical device (IMD), such as a pulse generator, electrically connected to the heart by at least one implantable defibrillator lead. More specifically, an implantable defibrillator lead provides an electrical pathway between the EMD, connected to a proximal end of the lead, and cardiac tissue, in contact with a distal end of the lead. In such a manner, electrical stimulation (e.g., in the form of one or more shocks or countershocks) emitted by the IMD may travel through the implantable defibrillator lead and stimulate the heart via one or more exposed, helically wound shocking coil electrodes located at or near the lead distal end portion. Once implanted, the exposed shocking coil electrodes often become entangled with fibrosis (i.e., a capsule of inactive tissue which grows into the exposed coils) with the end result being that a chronically implanted lead can be extremely difficult to remove by the application of tensile force to the lead proximal end.
Over time, situations may arise which require the removal and replacement of an implanted defibrillator lead. As one example, an implanted defibrillator lead may need to be replaced when it has failed, or if a new type of cardiac device is being implanted which requires a different type of lead system. As another example, bodily infection or shocking coil electrode dislodgement may require the replacement of an implanted defibrillator lead. In such situations, the implanted defibrillator lead may be removed and replaced with one or more different implantable leads.
To allow for easier removal, some implantable defibrillator leads include a fibrosis-limiting material covering a portion of the one or more otherwise exposed shocking coil electrodes thereon. When subjected to shear loads, such as during lead implantation procedures, the fibrosis-limiting material may separate from the associated shocking coil electrode or the shocking coil electrodes themselves may separate from the lead body or deform, thereby leaving uncovered coils that are subject to future fibrotic entanglement.


Embodiments relate to photo cell devices. In one embodiment, a trench-based photo cells provides very fast capture of photo-generated charge carriers, particularly when compared with conventional approaches, as the trenches of the photo cells create depleted regions deep within the bulk of the substrate that avoid the time-consuming diffusion of carriers.

Various sensors and gauges use delay measurements of acoustic and optic pulses or coded signals. In some applications, the measurement of a distance is coupled with pattern detection. This is the case, for example, in some time-of-flight techniques that use visible or infrared light. Due to the high velocity of light, the read-out circuitry has to work in a time-critical domain. The fast capture and evaluation of photo-generated charge carriers is a particular focus of cell design and read-out technique. Background current from carriers outside the space charge regions is to be avoided because carrier diffusion is time-consuming.
This is a challenging task, in particular, for infrared light because of its penetration depth, on the order of ten microns or more. Spreading an electric field from the place where photo-generated charge carriers have to be gathered to the penetration depth of infrared light, or deeper, is a challenging task. It is desired to address this disadvantageous situation, given that infrared light is the signal of choice in many applications because of its invisibility.
Conventional solutions use transient switching modes: at fast bias sweep conditions the semiconductor region underneath a metal-insulator-semiconductor (MIS) electrode is pulsed into a deep depletion state. In this operation mode the depletion width is larger than the maximum depletion width under equilibrium. This effect is used at devices with surface electrodes for carrier capturing, i.e., charger coupled devices (CCDs) or a photonic mixer device. As can be seen in FIG. 1A, infrared light generates electron hole pairs at least partly outside the space charge region at moderate substrate doping levels. These carriers contribute to noise and should be avoided. Additionally, and referring to FIG. 1B, three-dimensional formation of space charge regions can also occur, implying cross-talk in some device geometries and limiting the shrinking potential of the device. Therefore, there is a need for improved photo cell devices.

Photo cell devices for phase-sensitive detection of light signals


A web application receives a user input with a SQL injection attack string that references a function. The application generates a corresponding statement based on the user input string, which the application sends to a database server. Upon receiving the statement, the database server executes the statement that invokes the referenced function. When invoked, the referenced function stores a value. The presence of the stored value indicates that the database server invoked the function. Storing the value indicative of the function invocation identifies a vulnerability of the web application to SQL injection attacks, since the function reference is introduced solely through user input and function invocation is not intended by the application. This provides proof of SQL injection vulnerability of the application.

Information is conveniently stored in repositories such as databases. Various applications access and use the information stored in such databases. The value and importance of information to modern enterprises cannot be overstated. Efforts to secure information comprise a serious modern endeavor and database security is a major concern. However, databases and the applications that access information therein have become targets for malicious attacks such as "hacking," which can compromise information by destruction, damage and/or misappropriation of data. Unfortunately, a large and developing array of attack techniques and modalities exist.
When a user of a client browser makes an input to a web application, the web application may generate one or more statements containing SQL (Structured Query Language), PL/SQL (Procedural Language/SQL) code or the like that proffers a query to a database. A database server accesses the information from the database and returns information to the web application, which returns the information to the client. The client browser then displays or otherwise presents the requested information to the user. It is noteworthy that the information queried from the database and presented to the user typically depends on the user input in that different input values may result in different information returned.
Modern, well-crafted, robust web applications are typically designed and configured to resist attacks from hackers, whose attacks may be aimed to corrupt, damage, destroy, and/or compromise information stored in a database. However, not all web applications in use are modern, robust or well crafted. Older web applications are still in use. Some older applications were designed and configured without regard to attack modalities that did not exist or which were not well known or especially troublesome at the time the web application was deployed.
Further, some more modern web applications may lack one or more features that would otherwise harden the applications against attack. For instance, applications prepared in ad hoc efforts, inartfully or amateurishly, and those developed under time constraints or low budgets, may be particularly vulnerable in this sense. Moreover, even modern, robust and well-crafted web applications may suffer design flaws and configuration errors, which can leave the applications vulnerable in similar ways.
Stored information can be corrupted or damaged by a hacker making unauthorized, typically incorrect, random, or nonsensical changes to stored data values or similarly flawed entries to data fields. Stored information can be destroyed by a hacker deleting tables, object classes or rows and objects contained respectively therein. Stored information can be compromised by a hacker gaining unauthorized access to data that are supposed to be confidential, private, and protected from disclosure.
Such attacks take many forms, but one particular attack modality that has been used successfully by hackers is the so-called SQL injection attack.
An instance of a more general class of vulnerabilities that can arise where a scripting or programming language is embedded within another language, SQL injection refers to a class of security related vulnerabilities in the data access layer of an application. Successful SQL injection allows hackers to execute queries in SQL, PL/SQL or the like, which are unintended by the application and allow the hacker unauthorized access to stored data.
SQL injection attacks are typically launched using cleverly modified input strings to the application. A vulnerable application is compromised by manipulative exploitation of these relatively simple, but potentially pernicious, strings. SQL injection vulnerability is associated with inadequate filtering of input strings for string literal escape characters combined with the (full or partial) inclusion of those input strings in SQL statements proffered to the database, resulting in the unexpected execution of SQL that is modified with user input that is not strongly typed.
Client/Server/Database Operation
For instance, many modern web applications function with a three-tier configuration. Web applications frequently comprise a layer of Java or related code that is hosted by a middle tier web application server. Web applications receive inputs from web browsers, which are hosted by front-end tier client computers. In response to a browser request for a particular web page or other document, a web application accesses or retrieves the document and returns the document to the browser, which renders the webpage and displays the page at the client.
Frequently, information that the web application accesses and passes back to the browser associated with the document is stored in a relational or other database in a back-end tier, from which the information is retrieved. The database accesses the information by executing a statement in SQL or similar database query language. The database tier returns the information to the web application, which may format or otherwise process the information before sending it to the browser for display. Under some circumstances, the web application accepts input from the browser and, upon processing the input, uses some or all of the input to transform or modify the SQL query proffered to the database. For simplicity and brevity of explanation, the term SQL will be used herein, although it should be understood that references herein to SQL are examples that are intended to refer to PL/SQL and other database languages.
Information exchange in this three-tier environment may be explained with the following example. Using a client browser, the user opens a webpage associated with a hypothetical book-vending enterprise, "http://www.bookelephant.com," and uses a search feature associated therewith to find books by a certain author, such as "Beresniewicz." A web server may be associated with "www.bookelephant.com." The web server may host a web application associated with the enterprise. The search feature may include a data entry field displayed by the browser as the webpage is rendered. The browser accepts textual user inputs therewith. The webpage sends the inputs to the web application encoded as XML (Extensible Markup Language) or similar data transfer encoding. Upon receipt of the input from the browser, the web application transforms the encoded input:                Books/Beresniewicz/Searchinto a SQL statement. For instance, the example encoded input above may be transformed into a SQL query as shown below:
selecttitlesfrombookswhereauthor = 'Beresniewicz';The "single quote" (i.e., apostrophe) marks around the input data "Beresniewicz" in the query denote that this query token is a string literal. The web application places these single quote marks around the input data ("Beresniewicz") as part of transforming the input into the SQL statement proffered to the database. From one or more databases associated with "www.bookelephant.com," the titles of books that are stored therein are retrieved in response to the query and supplied to the web application. The web application returns the titles to the browser in HTML (Hypertext Markup Language) or similar code. The browser renders the HTML with a new or revised webpage. The browser displays the webpage for the user. However, the way the web application transforms user-entered request inputs into SQL queries in this example leaves the web application vulnerable to a SQL injection attack.
SQL Injection Attacks
SQL injection attacks target the web application's transformation of all or part of user request inputs (e.g., search query terms) into SQL database queries. A hacker's clever manipulation and use of various strings in inputs to a web application can cause the web application's transformation thereof to generate queries that are not intended by the web application. When executed by a database server, such queries can return data that the hacker lacks authorization to access. The hacker essentially exploits the transform to execute potentially pernicious and/or nefarious SQL statements.
A hacker can exploit the query structure resulting from the web application's transform of the user input. For example, a hacker may modify the author's name "Beresniewicz" to read as shown below.
Beresniewicz'∥' union select password from security_table
In this example, the hacker cleverly inserts the single quote mark followed by the concatenation symbol (∥), followed by another single quote mark and the phrase "union select password from security_table." Unfortunately, upon receiving and processing this input, the vulnerable web application transforms this input request into a SQL statement that includes a pernicious and unintended query such as the example shown below.
selecttitlesfrombookswhereauthor = 'Beresniewicz'unionselectpasswordfromsecurity_table;What the hacker has accomplished here is to "inject" SQL code within the browser input that was sent to the vulnerable web application. This injected SQL essentially "tricks" the web application into generating a SQL query that the web application is not intended to generate. The "trick" exploits the fact that the application simply concatenates single quotes around the input data and appends the resulting string literal token to the SQL statement without further validation of the input data. Such simplistic transformations of input data into SQL statements are unfortunately a common form of SQL injection vulnerability. Ominously in this example, SQL injection enables the hacker to access private passwords (e.g., of other users) from a security table in the database being queried. This is private, sensitive, and potentially damaging information to which the hacker is not entitled. Moreover, there is possibly no evidence that the sensitive, private data has been compromised. This dearth of evidence that the attack has occurred can be equally ominous.
Detecting Vulnerable Applications
In the example above, the SQL injection attack string was added to the end of valid input ("Beresniewicz"). However, other SQL strings can be injected at other parts of the input, as well. It is appreciated that not every such injection attack will allow successful access to unauthorized data sought by the hacker. Frequently (perhaps more often than not) a hacker will receive an "Error" message in response to a particular input. The hacker may essentially have to guess at the workings of a suspected vulnerable web application, specifically to determine how input data is transformed into SQL statements and whether these transforms can be exploited by injection attacks. From parsing some such error statements generated by one or more input attack strings and strategies, however, the hacker may glean clues for refining the injection attack. In this way, the hacker may eventually succeed. A successful SQL injection attack is called an exploit.
Various efforts are made to harden modern web applications against such attacks and to prevent vulnerabilities to exploits. For instance, more informed or sophisticated application programs may require statements to associate user input data with bind variables in SQL statements, which prevents unintended SQL statements from being injected with queries as input data does not transform the resulting query. As discussed above however, not all of the millions of existing web applications are so hardened.
Furthermore, detecting vulnerabilities in web applications poses a number of challenges. Confirming the vulnerability of a particular web application can involve interpretation of webpage response information that is very specific to the application. This can be difficult to automate and error prone as error messages can vary widely from application to application and even within an application from input to input. Large web applications can be associated with large numbers of web pages. Testing such large applications for SQL injection vulnerability can therefore be tedious, error prone, time consuming and expensive. Moreover, web pages may respond in variable ways, depending upon the particular inputs they may receive. Current techniques exist that automate SQL injection vulnerability testing from the input side (e.g., by automatically injecting common attack strings for data inputs at the front end). However, the variability in page response possibilities means that it is difficult to ascertain with these techniques, under all possible input circumstances, whether SQL injection vulnerability exists or not.
The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Based on the foregoing, it could be useful to reduce the tedium, error probability and time and expense involved in detecting SQL injection vulnerability in web applications.

Indicating SQL injection attack vulnerability with a stored value


A speed-variable speech signal reproduction apparatus and method for playing back speech signals stored in a storage medium at an adjusted speed while preventing any degradation in tone or loss of the speech signals from occurring. The method includes the steps of detecting the pitch of input digital speech signals using an average magnitude difference function, separating voice and voiceless sounds of the speech signals from each other based on the result of the detecting step, temporarily storing the separated voiceless sound, modulating the lengths of the speech signals by copying or eliminating a part of the separated voice sound, and synthesizing the modulated voice sound step with the voiceless sound temporarily stored in the storing step. The apparatus includes the a detector for detecting the pitch of input digital speech signals using an average magnitude difference function, a device for separating voice and voiceless sounds of the speech signals from each other based on the result of the detecting step, a memory for temporarily storing the separated voiceless sound, a modulator for modulating the lengths of the speech signals by copying or eliminating a part of the separated voice sound, and a synthesizer for synthesizing the modulated voice sound step with the voiceless sound temporarily stored in the storing step.

1. Field of the Invention
The present invention relates to an apparatus and method for use with a speech signal reproduction apparatus such as a tape player, VCR, multimedia equipment, computer or the like, for reproducing speech signals stored in a storage medium at variable speeds while preventing any degradation in tone or loss of the speech signals from occurring.
2. Description of the Related Art
In conventional tape or video players, the reproduced audio tone typically will vary when the play-back speed of the recorded signal is varied. That is, when the play-back speed is high, the audio signal being played back will vary from its original audio level and is heard as a "peep-peep" sound. At a low play-back speed, however, the audio signal will have what is known as a "loosened tape sound".
These phenomenons occur because the levels of frequency and pitch components of the recorded audio signal varies in relation to a variation in the play-back speed of the audio signal. A conventional method for preventing such phenomenons by partially playing back audio signals which have been read into a memory buffer is set forth in Japanese Patent Laid-Open Publication No. Heisei 4-168499 (Jun. 16, 1992). In accordance with this method, when the play-back speed is doubled, the audio signals that were read into the memory buffer are partially played back in such a way that only one of each of its two successive time-slices is played back.
For example, when a vocal recording of "I go to school with Jane" is played back at double speed in accordance with this conventional method, components of the original speech signal, which respectively correspond to the shaded portions shown in FIG. 1, are eliminated, so that only the speech "I to with Jane" is reproduced. Hence, since the conventional method plays back only a portion of the speech at a higher play-back speed so as to keep the tone of the speech in tact, the original meaning of the speech is lost. As a result, it is very difficult to understand the meaning of the speech using this conventional reproduction method.

Speed-variable speech signal reproduction apparatus and method


A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

This invention is generally related to the design of Very Large Scale Integrated Circuit (VLSI) chips and, more particularly, to a method for performing a physical verification of the integrated circuit (IC) layout design.
Physical verification is typically divided into three areas: i) design rules checking, ii) circuit extraction and layout to be compared against a corresponding schematic representation, and iii) parasitic parameter extraction. Of particular interest is finding how the circuit extraction and layout are applied against a schematic (LVS) representation of a multi-fingered MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) layout to improve the confidence level of the physical verification process. Ultimately, the LVS comparison verifies the device layout properties and connectivity against circuit schematics.
As the integration of semiconductor process technology progresses with sub-100 nm lithography and 300 mm multi-part number wafers, the investment for processed wafers demands an increased level of confidence that the physical circuit layouts, (i.e., sets of drawings containing coordinates of rectangles drawn in different layers used to generate the masks for integrated circuit manufacturing) match the intended circuit schematic designs. The schematic or netlist of the circuit is simulated on a Computer Aided Design (CAD) tool to verify the circuit functionality.
A semiconductor integrated circuit layout, including the dimensional accuracy of the pattern shapes, must be efficiently verified with high level of accuracy. The method and the algorithm defining this process provide the aforementioned layout versus schematic verification.
A significant number of patents and publications exist that relate to the physical verification of integrated circuit designs. Typically, only the MOS transistor channel length (L), the channel width (W) or channel width per finger (WF), and the number of fingers (NF) are checked, a process that is globally referred to as flat layout extraction. The aforementioned features are deemed to be the most basic features of the MOS transistor at a level that cannot be broken down any further. This approach is illustrated in FIGS. 1 and 2 as they apply, respectively, to a single finger and to a multi-finger layout. In the invention to be described hereinafter, the channel width of a single finger transistor will be denoted, for sake of simplicity, by the referenced nomenclature WF. In both figures, NF matches the number of gates 110. The prior art that utilizes a layout versus schematic comparison in a hierarchical methodology only applies to a logic gate level design but not to a transistor level design. In contrast, at the transistor level, as will be described hereinafter in the Detailed Description of the Invention, circuits will be broken down into sub-circuits, the sub-circuit consisting of a set of basic circuit elements, such as transistors, resistors, capacitors, and the like, with their corresponding interconnections wherein the combination of such circuit elements does not perform an electrical function. Accordingly, a typical hierarchical structure will consist of basic independent circuit elements, followed by the aforementioned sub-circuits, by a circuit, logic, and the like.
A conventional IC layout extraction and LVS process are shown by way of the prior art flow chart illustrated in FIG. 3. No MOS transistor source and drain diffusion dimensions can be checked when using a flat extraction. It is known in the art that the dimensions of the source and drain diffusion are critical parameters in contemporary VLSI chip designs because the impact of the source and drain parasitic capacitances of the transistor increases dramatically as the transistor feature size is scaled downward. These parasitic capacitances are fully dependent on the dimensions of the source and drain diffusion. As a result, what is needed is a detailed comparison of the layout versus the schematic check that also includes checking the source and drain dimensions. The performance of the circuit being manufactured may deviate significantly from the design target specifications because differences between the physical layout and the circuit schematic are not fully checked. The dimensions of the source and drain diffusion, referenced as "DIFFL", "DIFFM", and "DIFFR" are illustrated in FIG. 4, and are intended to be examples of layout features which can be checked by utilizing the device sub-circuit based extraction method to perform LVS. Also shown therein are three layers referred to "Multi" (410), "Left" (420), and "Right" (430). This cannot be achieved by way of a conventional flat extraction method. As the semiconductor industry continues scaling down the size of the device features to the nanometer region, other transistor geometric parameters such as gate shapes, number of source/drain/gate contacts, and other hybrid devices, e.g., interdigitated differential pairs, will also be required to be checked by way of LVS. The inventive method to be described hereinafter is intended to become a generic method to perform a complete LVS checking for any VLSI design based on the sub-circuit based extraction algorithm.
In three related patents, U.S. Pat. No. 5,831,316, U.S. Pat. No. 5,789,791, and U.S. Pat. No. 6,404,030, a multi-finger MOS transistor layout is described. Comparing the single finger MOS transistor layout shown in FIG. 1, the multi-finger transistor layout shown in FIG. 2 breaks the MOS transistor layout into basic shapes which are placed in parallel with the proper wiring connections (not shown).
U.S. Pat. No. 5,831,316 describes a method of equally positioning the source and drain regions between multi-gates, the base resistance values of parasitic bipolar transistors in each finger MOS being equal to each other. Thus, each finger MOS transistor in the multi-finger MOS transistor is turned on simultaneously to enhance the electrostatic discharge (ESD) protection performance. In the analog and mixed signal circuit domain, the gate resistance of a MOS transistor is one major factor affecting the high frequency performance.
U.S. Pat. No. 5,789,791 describes how the gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer.
U.S. Pat. No. 6,404,030 describes the high frequency performance of a MOS transistor which is improved by linking the gates and by forming conductive vias in each gate finger. Therefore, the multi-finger strategy is preferred since it improves the performance of the device by reducing the gate resistance, equalizing the turn-on of each single finger MOS transistor and reducing the area occupied by the MOS transistor. This consideration has long dominated modem IC designs.
U.S. Pat. No. 6,009,252 describes a method for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices. The color symmetrizing matrices that are generated correspond to respective 'child cells' in the circuit schematic. Child cells are characterized by having a number of symmetrical configurations that are electrically equivalent at the port level. The definition of child cells is advantageously used for a hierarchical LVS comparison algorithm. However, two electrically equivalent child cells may be matched inappropriately if the detailed cell attributes are not fully extracted and compared. In most cases, the channel length and width and the number of fingers are attributes to be extracted and compared in a flat extraction and LVS process. Other device attributes, such as the dimensions of the source and drain diffusions, the number of source to drain and drain to gate contacts, and the like, are not extracted and compared altogether. For way of example, FIGS. 5a–5b show transistor and layouts having different geometric dimensions. Explicitly, the dimensions of the source to drain diffusions 120, 130, and 220 differ between (a) and (b) while the channel length L (equal to L0), channel width WF (equal to W0), and number of fingers NF (=3) coincide for both transistors. In the prior art, the extraction and LVS is achieved by extracting L, WF, and NF and comparing these parameters against a schematic netlist that includes among others, a flat model element with L=L0, WF=W0, and NF=3 fully defined. This results in the transistors shown in FIGS. 5a–5b to be successfully matched to an identical schematic cell inappropriately because it is based on a presumption that the two transistors, i.e., FIG. 5a and 5b match each other, which, is incorrect. This is due to information of source and drain diffusion dimensions (DIFFL, DIFFM, and DIFFR) missing in the LVS comparison process.
U.S. Pat. No. 5,712,794 describes an automated method for adding attributes identified on a circuit schematic diagram to an integrated circuit layout. Even though the process of adding an attribute or property of a device can be automated, no mention is made in this patent or other references on how to check the correctness of the added attribute.
Although flat MOS transistor modeling has been used for many decades and it is known that it runs the fastest, it lacks the flexibility and accuracy of a parameterized sub-circuit modeling. The use of sub-circuit models, which are hierarchical models based on flat FET models with technology specific elements and parameters added, has become a standard practice in industry. The parameterized sub-circuit models not only supports useful features such as statistical analysis, but they also increase the accuracy because of additional components such as gate resistance, gate tunneling current, number of device fingers, etc. Examples of features that can be added are: i) Additional circuit elements such as gate resistance, gate to source and drain tunneling current, and a modified body resistance; ii) Geometrical layout parameters so that the dimensions of the transistor can be specified in a more natural way; iii) New instance parameters such as a new set of device dimensions, a different number of device fingers or number of body contacts; iv) Instances when model parameterization can also be applied locally to a sub-circuit, such that local statistical supporting analysis of neighboring device variations can, likewise, be included; and v) Cases where the sub-circuit also allows adding customized features to the model.
Other related references are:
An article by M. Lee, R. B. Anna, Jui-Chu Lee, S. M. Parker, K. M. Newton entitled "A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contact", published in the 2002 IEEE International Symposium on Circuits and Systems, Vol. 5, May 2002, pp 221–224, there is described a scalable RF (Radio Frequency) sub-circuit MOS transistor model using a commercial modeling tool to support a simple RC (Resistance and Capacitance) substrate network with well defined intrinsic parasitic parameters for Scattering Parameter (also referred to as an S-parameter, a common measure in RF technology) scalability. It is claimed that using a sub-circuit modeling strategy provides accurate and scalable modeling capability for high performance RF circuit design.
A gate level sub-circuit extraction algorithm is described in an article by W.-H. Chang, S. D. Tzeng, C. Y. Lee, entitled "A novel sub-circuit extraction algorithm by recursive identification scheme", published in the 2001 IEEE International Symposium on Circuits and Systems, Vol. 5, May 2001, pp 491–494. Based on a recursive graph identification scheme, the proposed sub-circuit extraction algorithm can decrease the run time significantly and is technology independent.
Articles by N. Vijaykrishnan, N. Ranganathan, entitled "SUBGEN: a genetic approach for sub-circuit extraction", published in the 1996 Ninth International Conference VLSI Design, January 1996, Pages: 343–345 and by Z. Ling, D. Y. Y. Yun, entitled "An efficient sub-circuit extraction algorithm by resource management", published in the 1996 Second International Conference on ASIC, October 1996, pp. 9–14, describes a sub-circuit extraction algorithm to identify a sub-circuit in a large scale integrated circuit layout. The algorithm described by N. Vijaykrishnan et al. begins with a random population potential match and details a so-called genetic representation algorithm. In the paper by Z. Ling et al., an efficient approach is described to solve the subgraph isomorphism problem based on the resource management paradigm is transformed to extract sub-circuit.
An article by G. Yokomizo, C. Yoshida, M. Miyama, Y. Motono, K. Nakajo, entitled "A new circuit recognition and reduction method for pattern based circuit simulation", published in the 1990 IEEE Custom Integrated Circuits Conference, May 1990, pp. 9.4/1–9.4/4, a circuit recognition and reduction method to extract sub-circuit data corresponding to the critical path is described. When including all relevant parasitics and internal loading, the critical path can be optimized and the design can be improved substantially.
Comparing the combined methods described by W.-H. Chang et al., N. Vijaykrishnan et al., Z. Ling et al., to the method described by Yokomizo et al., the latter takes one more step, i.e., the circuit reduction, to further simplify the extracted sub-circuit when finding a critical path. However, the sub-circuit described in the combined publications is a combination of several MOS transistors and/or resistors, etc., but not a transistor level representation that can be used to improve the geometric property comparison accuracy.
Finally, the article by W. Kim, H. Shin, entitled "Hierarchical LVS based on hierarchy rebuilding" and published in the 1998 Design Automation Conference. February 1998, pp. 379–384, described a method for extracting sub-circuit(s) from a VLSI design and then performing layout versus schematic comparison hierarchically. Experimental results show that this technique is effective and efficient regarding CPU time and memory usage. Once again, since the sub-circuit usage at the transistor level is not suggested, the hierarchical LVS only provides increased accuracy and efficiency on the circuit connectivity verification. Increasing the accuracy of device property checking can only be achieved by using the sub-circuit based LVS method as proposed in this invention, where each critical property or parameter in a transistor sub-circuit level has to be compared and matched.
The typical prior art flat extraction method is described below. Referring back to prior art FIG. 1 there is shown a flat modeled single finger MOS transistor layout. The extraction obtains the gate pattern and node from the interaction of polysilicon gate 110 and active region 140. The source and drain (120 and 130, swappable) are then extracted by the difference of 140 and 110. Then the extracted netlist can be written as Netlist (1).T1 (GNode, SNode, DNode) model=NMOS L=L0, W=W0,  (1)where T1 is a sequence name of the transistor observing a particular naming rule in a particular electronic design tool. Each electrical node is defined in parenthesis where GNode represents Gate, SNode for Source and DNode for Drain. Since the electrical connectivity extraction and checking is not within the scope of the invention, it is assumed that the electrical nodes of the gate, source, and drain of the MOS transistor will be referred to as GNode, SNode, and DNode, respectively. The node definitions in parenthesis are followed by "model=" and "NMOS", which is the model name of the extracted transistor, i.e., a flat model or sub-circuit model. The device properties of channel length (L) and channel width (WF) are calculated and listed accordingly. After the netlist is generated and the properties extracted, LVS is initiated to compare the node connections and property values. In the present case, only the channel length and width will be compared against the design schematic values.
Referring now back to FIG. 2, there is shown a multi-finger layout where three polysilicon gate fingers 110 break the entire active diffusion 140 in four sections, 120, two of 220, and 130. Another horizontal polysilicon bar 210 joins the three fingers 110, making the three gate fingers transistor wired as one. In case of a multi-finger layout, a conventional method extracts three MOS transistors as Netlists (2)–(4), i.e.,T2 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (2)T3 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (3)T4 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (4)
The extracted transistors look exactly the same to each other except for different notation names. Usually, after the primitive extraction, most LVS tools perform a reduction process intended to merge all the devices connected in parallel (the source and drain wiring are not shown) to one device. In this case, the final extracted netlist will be like Netlist (5).T5 (GNode, SNode, DNode) model=NMOS L=L0, W=Wall,  (5)where Wall=3W0, since the three devices are in parallel. It will be noticed that, in both examples, critical model properties such as the number of fingers (NF) are not extracted and compared. Moreover, it is not possible to compare additional device features such as diffusion segment dimensions, which typically have a significant impact on the device and circuit performance.
The problem solved by the invention is that LVS checks all the layout geometric parameters after performing a sub-circuit based extraction. The prior art for the general layout physical verification process is shown in FIG. 3. The layout extraction and LVS process (310) need to be performed after the layout is completed. If the comparison shows that the layout is correct, i.e., the extracted netlist is equivalent to the schematic netlist, the physical verification branches to the "parasitic extraction" stage 360. When the post-layout simulation results satisfy the design specification, the complete physical verification process is terminated and is followed by the tape-out process (i.e., formalizing a verified layout and readying it for mask generation).
As shown in FIG. 3, present solutions typically only recognize devices as a group of flat basic components like resistors and single finger MOS transistors represented by "Flat extraction" 320. In addition to breaking the design coherence with the schematic by recognizing a single device as multiple primitive elements, this practice leads to simulation inefficiencies downstream requiring an iterative solution of multiple elements instead of a single sub-circuit device model. Simulation efficiency may be improved by merging the primitive elements, as discussed above for Netlist (5), but important structural details may be lost in the merge. This practice only partially works for a multi-finger layout because the critical device property "number of fingers" cannot be checked. The single finger device of FIG. 1 and the three-finger device of FIG. 2 after reduction achieves the same result as Netlist (5) even though individually they perform differently from one another. Certain advanced algorithms handle the property "number of fingers" by using a multiplicity factor but no other geometric parameters, such as source and drain diffusion dimensions are extracted and compared during LVS. No known solution has been disclosed to solve the general layout geometric parameter extraction and LVS.
In summary, LVS is a critical step in the physical verification phase of the IC design process. Known solutions cannot extract a complete list of geometric parameters of a transistor and perform a complete parametric and connectivity verification. The invention solves this problem by incorporating three additional marking layers and utilizing a sub-circuit based extraction algorithm to extract a complete list of transistor geometric parameters. Followed by the sub-circuit based LVS method, the stated shortage of current extraction and LVS is resolved, resulting in an improved match of the IC layout to the design specification.

Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction

International Business Machines Corporation


A fixing apparatus includes: a fixing roller and a pressure roller which transport a recording paper while sandwiching the recording paper P therebetween so that an unfixed toner image formed on the recording paper is fixed thereon under heat and pressure; two support rollers; an endless belt which is set over the support rollers and comes into contact with a surface of the fixing roller; and heater lamps which are provided respectively inside the support rollers. A fixing apparatus satisfies a relationship indicated by (C2+C3)/C1≧2 where C1 is a heat capacity of each of the heater lamps, C2 is a heat capacity of each of the support rollers, and C3 is a heat capacity of the endless belt in each of areas where the endless belt is in contact with the support rollers. This realizes an external belt heat fixing apparatus which suppresses (a) heat damage to the endless belt and the surface of the fixing member and (b) unevenness of an image.

A fixing apparatus used in an electrophotographic image forming apparatus such as a copying machine, a printer, and the like, is typically constituted by a pair of rollers (fixing roller and pressure roller) which are pressed against each other. As such a fixing apparatus, a heat roller type fixing apparatus is frequently used, wherein halogen heaters disposed in both the rollers or a halogen heater disposed in one of the rollers heat the pair of rollers at a predetermined temperature (fixing temperature), and a recording paper P on which an unfixed toner image is formed is allowed to pass through a pressing section (fixing nip area) of the pair of rollers so as to fix the toner image under heat and pressure.
Especially, in a fixing apparatus provided in a color image forming apparatus, it is general to use an elastic roller having an elastic layer which is made of silicon rubber or the like and which is provided on a fixing roller surface layer.
The elastic roller is used as the fixing roller, so that the fixing roller surface is elastically deformed corresponding to an uneven surface of the unfixed toner image and is in contact with the toner image so as to cover the toner image. This allows the color unfixed toner image whose toner amount is larger than that of monochrome unfixed toner image to be favorably fixed under heat. Further, due to strain release of the elastic layer which occurs in the fixing nip area N1, it is possible to improve a releasing property with respect to color toner which is more likely to offset than monochrome toner. Further, a nip shape of the fixing nip area N1 has a concave upward (that is, the nip shape is a so-called inverse nip shape), so that it is possible to more favorably separate the recording paper P from the fixing roller. As a result, it is possible to separate the recording paper P without using any separation means such as a separation claw (self stripping), so that it is possible to prevent insufficient image formation which is caused by the separation means.
However, in the fixing roller having the elastic layer, the elastic layer cannot sufficiently conduct heat. Thus, in case where the heating means is provided in the fixing roller, heat is less efficiently conducted, so that it takes longer time to warm up. In case where the process is carried out at higher speed, the fixing roller cannot follow the process.
As a method for solving these problems, an arrangement in which external heating means is brought into contact with the fixing roller surface so that the fixing roller is heated from the outside (external heat fixing process) is known. Especially, an arrangement in which an endless belt is used as the external heating device (external belt heat fixing process) has been recently proposed (Patent document 1: Japanese Unexamined Patent Publication No. 198659/2004 (Tokukai 2004-198659; published on Jul. 15, 2004) and Patent document 2: Japanese Unexamined Patent Publication No. 189427/2005 (Tokukai 2005-189427; published on Jul. 14, 2005).
However, the above external belt heat fixing process that was conventionally carried out offers a high ability to supply heat to the fixing roller. In addition, heat is transmitted from the heat source to the fixing roller surface, passing though a plurality of members (an endless belt and support rollers for suspending the endless belt) provided between the heat source and the fixing roller surface. As a result, wide temperature variations occur between the heat source and the fixing roller surface. That is, temperature variations between the heat source, the support rollers, the endless belt, and the fixing roller surface are as follows: heat source>support rollers>endless belt>fixing roller surface.
In a situation where rotation of the fixing roller is stopped, a temperature of each of the support rollers is raised by heat of the heat source even if heat supply from the heat source is stopped. Furthermore, an area of the endless belt where the endless belt is in contact with the support roller is small in heat capacity and thus instantly reaches a temperature that is the same as a temperature of the support rollers. Accordingly, a temperature of the endless belt becomes higher than a temperature that the endless belt has during the fixing operation. This can cause heat damage to the endless belt.
Also, there occurs rise in temperature of the fixing roller surface in an area where the fixing roller is in contact with the support rollers via the endless belt. This causes heat damage to the fixing roller surface or temperature variations in the fixing roller surface. Under such a situation, if the fixing operation is restarted, there occurs unevenness of the image.
That is, as compared with the external heating process in which rollers are brought into contact with a fixing member, a heating nip area becomes wider in the external belt heat fixing process in which the endless belt is brought into contact with the fixing member. Therefore, even if the endless belt has a smaller heat capacity, the endless belt can supply a large amount of heat to the surface of the fixing member, and a temperature of the fixing member can excellently respond to a high-speed fixing. However, when the operation of the fixing member is stopped after the end of the fixing, a temperature of the endless belt in an area where the endless belt is set over the support rollers rapidly increases, the endless belt and the fixing member are partly heated and therefore deteriorated (hereinafter such phenomenon is referred to as overshoot).

Fixing apparatus and image forming apparatus


This invention relates to control techniques and controllers for resonant discontinuous forward power converters (RDFCs). We describe a controller for a resonant discontinuous forward converter (RDFC), said forward converter including a transformer with first and second matched polarity windings and a switch to switch dc power to said first winding of said transformer, said converter further having a dc output coupled to said second winding of said transformer, and wherein said controller has two modes, a first operational mode during which said switch is controlled to switch said dc power at a frequency which substantially coincides with a resonant frequency of operation of said RDFC such that said RDFC supplies power from said dc output, and a second, reduced power operational mode during which a drive to said switch is controlled to increase a proportion of time during which said switch is off.

FIG. 1 (which is taken from U.S. Pat. No. 4,688,160) shows an example of a forward power converter comprising a dc input 101, 102 coupled to the primary winding 109 of a transformer 110. The primary winding 109 is connected in series with a switching device 105, here a bipolar transistor, which switches on and off, during an on period building up magnetising flux in the primary winding 109, which drives a current in a secondary winding 111 of the transformer. Unlike a so-called flyback converter, in a forward converter the primary and secondary windings have matched polarities, as indicated by the dots on the windings in FIG. 1. The output from the transformer 110 is rectified by a rectifier 114 and smoothed by a smoothing capacitor 119 to provide a dc output 121, 122. When switch 105 is off the core of the transformer is "reset" allowing the magnetising flux to return to its initial state. In the example of FIG. 1 (U.S. Pat. No. 4,688,160) this is performed by resonant action between the magnetising inductance of transformer 110 and a capacitor 113 shunting diode 114, returning energy to the input voltage source.
The circuit of FIG. 1 includes a large output choke 117 between rectifier 114 and smoothing capacitor 119, and a freewheeling or "flyback" diode 115 across the series combination of choke 117 and smoothing capacitor 119. This is because when the switch 105 is turned off, because the primary and secondary windings have the same sense, rectifier 114 immediately becomes non-conducting. The function of the freewheeling diode 115 is to allow the choke 117 to maintain a continuous output current into output node "X" when switch 105 is off by providing a path for this current.
FIG. 1 shows a conventional, continuous forward converter. There are many other prior art documents describing such converters, including, for example, U.S. Pat. Nos. 4,415,959; 6,760,236; 6,304,463; 6,252,781; EP0 074 399; and the reference design SLUA276 for the Texas Instruments UCC38C42. In some of these later circuits the secondary side diodes are replaced by synchronous rectifiers embodied in MOS transistors. Other background prior art can be found in U.S. Pat. No. 4,788,634 which describes a resonant forward converter in which natural self-inductance of the transformer in parallel with the transformer provides a resonant "ring" so that the switching circuit can be self-resonant; and U.S. 2005/0270809 (WO 2004/057745) which describes use of an auxiliary transformer in a current limiting circuit.
We have previously described, in our earlier patent applications GB0610422.8 filed 26 May 2006 and U.S. Ser. No. 11/449,486 filed 8 Jun. 2006, how improved operation such as improved regulation and start-up may be achieved by use of switch control in a discontinuous current flow mode. More particularly we have previously described an RDFC for converting an input dc voltage to an output dc voltage, the converter comprising: first and second dc inputs; a transformer having primary and secondary windings with matched polarities; a controllable switch for switching power from the dc inputs through the primary winding of the transformer, the controllable switch and the primary winding of the transformer being coupled in series between the first and second dc voltage inputs; first and second dc voltage outputs; a rectifier coupled to the secondary winding of the transformer, the rectifier and the secondary winding of the transformer being coupled in series between the first and second dc voltage outputs; a smoothing capacitor having a first connection coupled to receive dc power from the rectifier at a first connection node, the first connection node being coupled to the first dc voltage output, the smoothing capacitor having a second connection coupled to the second dc voltage output; and a controller having an output coupled to the controllable switch and being configured to control the switch such that a voltage waveform on the secondary winding has a first portion during which the switch is on and current flows into the first connection node, and second substantially resonant portion during which the switch, and preferably also the rectifier, is off; and wherein substantially no current flows into the first connection node during the second portion of the voltage waveform.
We now describe further control techniques for RDFCs.