A method for etching a tungsten containing layer 25 on a substrate 10 substantially anisotropically, with good etching selectivity, and without forming excessive passivating deposits on the etched features. In the method, the substrate 10 is placed in a plasma zone 55, and process gas comprising SF.sub.6, CHF.sub.3, and N.sub.2, is introduced into the plasma zone. A plasma is formed from the process gas to anisotropically etch the tungsten containing layer 22. Preferably, the plasma is formed using combined inductive and capacitive plasma operated at a predefined inductive:capacitive power ratio.

The present invention relates to a method for etching tungsten containing material on a substrate.
In integrated circuit fabrication, refractory metals, such as for example tungsten, tantalum, titanium, molybdenum, and their silicides, are used to form high density, high speed, electrically conductive interconnect lines and/or contact plugs for electrically connecting active semiconducting devices formed on silicon or gallium arsenide substrates. In a typical process, a blanket tungsten layer is deposited over an underlying titanium, titanium-nitride, titanium-tungsten, which serves as an barrier or adhesion layer. This is followed by a masking step in which patterned photoresist features are formed over the tungsten layer. To form interconnect lines on the substrate, an etch step is used to remove the tungsten material from the regions not covered by the photoresist features. Tungsten layers can also be used for filling openings to form electrically conducting contact plugs below interconnect wiring layers, by chemical vapor deposition of a blanket tungsten layer that fills the openings, followed by etching of the blanket tungsten layer to form the desired configuration of interconnect lines and/or plugs. Tungsten is desirable for both interconnect lines and contact plugs because (i) tungsten has a higher melting temperature of about 3410.degree. C. compared to aluminum which melts at 660.degree. C., which allows high temperature processing of the substrate; (ii) tungsten exhibits reduced electromigration or diffusion when applied over a silicon layer, (iii) tungsten reacts with silicon at temperatures exceeding 600.degree.-700.degree. C., whereas aluminum reacts with silicon at lower temperatures of 250.degree. C., (iv) tungsten deposition generally provides more uniform filling of high aspect ratio contact plugs, better step coverage, and reduced formation of electrical discontinuities that cause shorts or breaks.
Conventional processes for etching tungsten containing layers use a capacitive RIE plasma of halogen-containing gases, and more typically fluorinated gases, such as CF.sub.4, SF.sub.6, CBrF.sub.3, and NF. One problem with conventional etching processes lies in their inability to anisotropically etch tungsten containing layers to provide features having substantially vertical sidewalls which are not inwardly or outwardly tapered. Excessive etching at the sidewalls of the etched features results in the undesirable inwardly or outwardly sloped sidewalls.
Conventional tungsten etch methods that provide increased anisotropic etching use gases such as CBr, NF.sub.3, or CHF.sub.3 to form thick passivating deposits on the sidewalls of the etched features to reduce horizontal etching, as described in J. Vac. Sci. Technol. B, page 3272 (1985). However, these methods often result in etched features which have wider dimensions at the base due to the increased thickness of the passivating film that forms on the freshly etched sidewalls of the features as the etch process proceeds to completion. In yet another method, gas mixtures of SF.sub.6 /CBrF.sub.3 or SF.sub.6 /CHF.sub.3 are used to reduce undercutting, but these mixtures nonetheless yield isotropic profiles with substantial undercutting at the base of the etched feature, as for example, disclosed in Tennant, et al., J. Vac. Sci. Technol. B, page 71836 (1989). In yet another etching method, as described in U.S. Pat. No. 4,992,136 to Tachi, et al., the tungsten film is etched using (I) an etchant gas such Cl.sub.2 or SF.sub.6 ; and (ii) a passivating film forming halogen gas containing C or Si to form deposits on the surface of the substrate during etching, such as CCl.sub.4, CF.sub.4, CHF.sub.3, CHCl.sub.3, SiF.sub.4, or SiCl.sub.4. However, this method generally provides tapered angles for the sidewalls of the etched features because it is difficult to precisely control the ratio of the etchant gas to the film forming gas during the etching process, particularly towards the completion of the etching process when a high concentration of volatile passivating polymeric species is formed in the etchant chamber.
Conventional etching processes also often fail to maintain the critical dimensions of the etched features, which are predefined and desirable dimensions of the etched features, used to determine the electrical properties of the etched features, in the design of integrated circuits. The critical dimensions are those dimensions that have a significant effect on the electrical properties of the etched features. In modern integrated circuits, the line widths of interconnect lines and diameters of contact plugs are becoming increasingly smaller to levels below 0.25 microns, to accommodate higher circuit densities. Because the electrical resistance of these features is proportional to the cross-sectional area of the etched features, it is important to maintain consistent and uniform dimensions without variations of across an etched feature or between different etched features. Tapering cross-sections, cross-sectional profiles that vary as a function of the spacing between the features, or other variations in the profile of the features is no longer acceptable in modern integrated circuits. The critical dimensions are typically measured as a ratio or difference between the width W.sub.r of the resist features and the width W.sub.e of the resultant etched features. The closer the width of the etched feature to that of the resist feature the more predictable and reliable are the electrical properties of the etched feature.
Thus, it is desirable to have a process for etching tungsten-containing layers which exhibits anisotropic etching and provides etched features having substantially straight sidewalls. It is further desirable for the etching process to provide etched features having consistent and reproducible critical dimensions. It is also desirable for the etching process to exhibit reduced and more controllable formation of passivating film deposits on the sidewalls of the etched features. It is further desirable for the etching process to have a large processing window tolerant of process fluctuations and provide a high process throughput.

Method for anisotropically etching tungsten using SF.sub.6, CHF.sub.3, and N.sub.2


By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.

1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of an interlayer dielectric between and over circuit elements including line elements, such as gate electrodes, polysilicon interconnect lines and the like that create a pronounced surface topography for subsequent manufacturing processes.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein the circuit elements are usually formed in and on a semiconductor layer by performing a plurality of processes, such as lithography processes, etch processes, implantation processes, deposition processes, anneal processes and the like. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, MOS technology based on silicon is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost effectiveness. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, i.e., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline silicon or silicon-containing layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode that comprises a line-like portion and is formed above the channel region and separated therefrom by a thin insulating layer.
Typically, the circuit elements, such as the MOS transistors, capacitors, resistors and the like, are formed in a common layer, which will be referred to hereinafter as a device layer, whereas the "wiring," i.e., the electrical connection of circuit elements according to the circuit design, may be accomplished only to a certain degree by means of polysilicon lines and the like within the device layer so that a plurality of additional "wiring" layers formed over the device layer may be required. These wiring layers include metal lines embedded into an appropriate dielectric material, such as silicon dioxide, silicon nitride and the like, or, in very advanced devices, low-k materials having a permittivity of 3.0 or less are used. The metal lines and the surrounding dielectric material will hereinafter be referred to as a metallization layer. Between two adjacent metallization layers and also between the device layer and the first metallization layer, respective interlayer dielectrics are formed through which metal-filled openings are formed to establish the electrical connection between metal lines or between circuit elements and metal lines.
In typical applications, the interlayer dielectric separating the device layer from the first metallization layer is essentially formed from silicon dioxide that is deposited by well-established plasma enhanced chemical vapor deposition (PECVD) techniques, which enable the formation of a smooth and dense silicon dioxide film with sufficient conformality at moderately high deposition rates. Upon further device scaling resulting in gate lengths of MOS transistors on the order of less than 50 nm also the lateral dimensions of the metal lines and the vias have to be adapted to the reduced critical dimensions in the device layer. For example, the contact elements formed in the interlayer dielectric separating the device layer from the first metallization layer may have to be formed with dimensions of less than 100 nm. On the other hand, a pronounced surface topography may have been created during the preceding fabrication of the circuit elements, such as the gate electrode structures, which may extend from the basic semiconductor layer with a height of approximately 100 nm and more, even for advanced transistors of the 60 nm technology. Hence, the interlayer dielectric material may have to be provided such that the height levels of the gate electrode structures are at least leveled in other device regions while extra height for forming the contacts may also have to be taken into consideration. Moreover, the manufacturing flow for forming the contact elements may also result in a varying amount of material loss of the interlayer dielectric, depending on process fluctuations. For these reasons, the initial thickness of the interlayer dielectric material may have to additionally provide sufficient process margins when implementing a respective manufacturing flow in a volume production environment. On the other hand, the aspect ratio for patterning and refilling the contact openings may be restricted by technological constraints so that, for given critical dimensions of the contact elements, the thickness of the interlayer dielectric material may not be arbitrarily set to a target height that would accommodate all the process tolerances of the manufacturing processes involved, as will be explained in more detail with reference to FIGS. 1a-1d.
FIG. 1a schematically illustrates a top view of a portion of a semiconductor device 100. The semiconductor device 100 comprises a substrate (not shown in FIG. 1a) above which is formed a semiconductor layer (not shown) in and above which circuit elements, such as a transistor and the like, are formed. For convenience, a circuit element in the form of a transistor 150 is illustrated. The transistor 150 may comprise a gate electrode structure 151, sidewalls of which may be covered by a spacer element 152. Laterally adjacent to the gate electrode structure 151, drain and source regions 153 are provided which, in addition to a channel region (not shown), may be located below the gate electrode structure 151 and may represent an active region in the corresponding semiconductor layer. The active region may be bordered by an isolation structure 102, above which also a portion of the gate electrode structure 151 may be positioned, thereby defining a contact region 154 that is in contact with a contact plug or contact element 1 10. Similarly, one or more contact elements 111 may be provided so as to connect to the drain and/or source regions 153, wherein, for convenience, only one such contact element 111 is illustrated. It should be appreciated that the contact elements 110, 111 are typically formed in an appropriate interlayer dielectric material which for convenience is not shown in FIG. 1a.
FIG. 1b schematically illustrates a cross-sectional view along the line 1b as shown in FIG. 1a, wherein the semiconductor device 100 is illustrated in a manufacturing stage in which the contact elements 110, 111 are not yet formed. As shown, the semiconductor device 100 comprises a substrate 101, which represents any appropriate carrier material, such as a silicon substrate, a silicon-on-insulator (SOI) substrate and the like. A silicon-based semiconductor layer 103 is formed above the substrate 101, and the isolation structure 102, for instance in the form of a trench isolation, defines an active region 104 in which are positioned the drain and source regions 153, i.e., respective dopant concentrations, so as to define respective PN junctions with the remaining portion of the active region 104. Furthermore, a gate insulation layer 156 is formed on the semiconductor material of the active region 104, thereby isolating the gate electrode structure 151 from the active region 104. Moreover, metal silicide regions 155 may be formed in the drain and source regions 153, thereby defining a contact region thereof. Similarly, the metal silicide 155 may also be formed on the gate electrode structure 151 including the contact portion 154 (FIG. 1a), thereby also defining a respective contact region for the gate electrode structure 151. Furthermore, the semiconductor device comprises an interlayer dielectric material 105 which typically comprises two or more dielectric layers, such as the layers 105A and 105B, wherein the former one may represent a contact etch stop layer comprised of silicon nitride and the latter one may represent a silicon dioxide material.
In advanced applications, the etch stop layer 105A may additionally act as a strain-inducing material for generating a desired type of strain in the active region 104. Therefore, the layer 105A may be formed so as to have a high internal stress level, while the thickness thereof is selected such that a high mount of stressed material may be positioned in the vicinity of the transistor 150. However, the thickness of the layer 105A is restricted by the gap fill capabilities of plasma enhanced deposition techniques for forming the highly stressed silicon nitride material that is usually employed for the layer 105A. For example, the thickness of the layer 105A may be restricted to less than approximately 100 nm in sophisticated devices. Furthermore, the thickness of the interlayer dielectric material 105 is selected so as to obtain a desired height level above the active region 104 and the isolation structure 102 and to provide a sufficient distance between the gate electrode structure 151 and a first metallization layer still to be formed, while also taking into consideration a material loss during the further manufacturing flow for forming the contact elements 110, 111 (FIG. 1a) and the first metallization layer. On the other hand, the thickness of material 105 and thus of the layer 105B may not exceed a certain limit in order to respect the aspect ratio restrictions for patterning and filling the contact elements 110, 111.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. After forming the circuit element 150 on the basis of well-established techniques in accordance with design rules of the respective technology node, which includes forming the appropriate gate insulation layer 156 and patterning the same along with the gate electrode structure 151 by sophisticated lithography and etch techniques. The drain and source regions 153 may be formed by ion implantation, using the spacer structure 152 as an appropriate implantation mask. After any anneal cycles, the metal silicide regions 155 are formed, followed by the deposition of the etch stop layer 105A, typically by PECVD, since PECVD of silicon nitride may be accomplished at moderately low temperatures of less than approximately 600° C., which is compatible with preceding manufacturing processes and materials, such as metal silicides 155 and the like. As previously discussed, the ongoing shrinkage of feature sizes also entails that a distance between neighboring circuit elements in densely packed device regions is reduced and may be less than approximately 150 nm in currently manufactured CPUs of the 65 nm technology node. Hence, any deposition techniques for forming a dielectric layer for embedding the gate electrode structure 151, which may have a height of approximately 100-150 nm, have to meet the requirements of an appropriate fill capability so as to reliably and completely fill the empty spaces between the neighboring circuit elements. Moreover, the process parameters of the PECVD process for the deposition of the silicon nitride material of the layer 105A in a highly stressed state may be selected so as to obtain the desired stress level rather than obtaining an optimum fill behavior. Therefore, for well-established PECVD process recipes for silicon nitride, the layer 105A may be deposited in a more or less conformal fashion only with a thickness of approximately 100 nm or less.
Thereafter, the silicon dioxide layer 105B is deposited, which is typically done by PECVD on the basis of precursors TEOS (tetra-ethyl-ortho-silicate) and oxygen, since PECVD allows the deposition of silicon dioxide in a moderately conformal manner—yet with less gap filling qualities compared to thermal CVD—with relatively high mechanical stability at temperatures below 600° C. at high deposition rates, which provides a high production yield. After deposition, the silicon dioxide layer 105B has a certain topography caused by the underlying structure of the gate electrode structure 151, which may jeopardize subsequent manufacturing processes, such as a photolithography step for forming contact openings for the contact elements 110, 111. Consequently, the standard process flow requires that the silicon dioxide layer 105B be planarized, typically by chemical mechanical polishing (CMP), wherein excess material of the silicon dioxide layer 105B is removed by chemical and mechanical interaction with a slurry and a polishing pad to finally obtain a substantially planarized surface 105S of the silicon dioxide layer 105B. The CMP process itself is a highly complex process and requires sophisticated process recipes, wherein the removal rate significantly depends on the characteristics of the silicon dioxide layer 105B, such as density, mechanical stress, water contents and the like. Due to the complexity of the CMP process and due to any fluctuations in the preceding processes, such as the deposition of the layer 105B, the finally obtained height 105H of the layer 105B above the gate electrode structure 151 may also vary during volume production processes. Moreover, the height 105H may have to also accommodate further material losses in subsequent processes, while, on the other hand, a critical height above the active region should not be exceeded, since here the high aspect ratio contact elements 111 are to be formed so that extra height in this area may increase the probability of creating contact failures.
FIG. 1c schematically illustrates the device 100 in a further advanced manufacturing stage. As shown, the contact elements 110 (not shown in this cross-sectional view) and 111 are formed in the interlayer dielectric material 105 and typically comprise a barrier material 111A, for instance in the form of a titanium liner and a titanium nitride liner, while the actual fill material 111B may be provided in the form of a tungsten material.
The contact elements 110, 111 may be formed by well-established techniques including deposition processes for forming an anti-reflective coating (ARC) material and patterning the same by photolithography to obtain an etch mask for forming contact openings in the layers 105B and 105A. Thereafter, the etch mask is removed and the barrier material 111A and the fill material 111B are deposited. During the preceding sequence, that is, the patterning of the contact openings and the filling thereof, the process yield may depend on the aspect ratio of the contact openings, as previously explained. Next, excess material of the fill material 111B is removed, for instance by CMP. However, during the patterning of the contact openings and the removal of the excess material, a further material loss of the layer 105B may occur, as indicated by 105L. This additional reduction in height 105L may be approximately 100 nm and may need to be taken into consideration when selecting the initial target height of the layer 105, thereby further contributing to an increased aspect ratio of the contact element 111 and at a lesser extent of the contact element 110.
Consequently, the contact element 111 connecting to the drain or source region 153 may have a moderately high aspect ratio, since the lateral size thereof is substantially restricted by the lateral dimension of the drain and source regions 153, while the depth of the contact element 111 is determined by the thickness of the interlayer dielectric material 105. On the other hand, the contact element 110 only has to extend down to the top surface of the gate electrode structure 151, i.e., to the contact portion 154 (FIG. 1a), while also the lateral dimension of the contact element 110 may be different compared to the element 111, depending on the size and shape of the contact portion 154. The contact elements 110, 111 typically comprise a barrier material in the form of a titanium liner, followed by a titanium nitride liner, while the actual fill material may be provided in the form of a tungsten material.
FIG. 1d schematically illustrates the device 100 with a metallization layer formed above the interlayer dielectric material 105. The metallization layer, which is the first metallization layer of the device 100, typically comprises an etch stop layer 123, for instance in the form of silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, on which may be formed an appropriate dielectric material 124, such as a low-k dielectric material having a relative permittivity of 3.0 or less. Moreover, respective metal lines 121, 122 are formed in the dielectric material 124 and connect to the contact elements 110, 111, respectively. The metal lines 121, 122 may comprise a copper-containing metal in combination with an appropriate barrier material, such as a material comprising tantalum, tantalum nitride and the like. Finally, a cap layer 126 is typically provided to confine the copper material in the metal lines 121, 122, which may be accomplished on the basis of dielectric materials such as silicon nitride, silicon carbide and the like.
The metallization layer may be formed by depositing the etch stop layer 123 followed by the deposition of the dielectric material 124. Next, respective trenches are formed in the dielectric material 124 according to well-established single damascene strategies. Next, the metal lines 121, 122 may be formed by depositing a barrier layer and filling in a copper-based material, for instance on the basis of electroplating, which may be preceded by the deposition of a copper seed layer. Finally, any excess material may be removed, for instance by CMP, and the cap layer 126 may be deposited. During the patterning of the trenches, the reduced height 105R may need to be within specified tolerances so as to ensure a reliable patterning process. However, due to the preceding process fluctuations, in particular the CMP processes for planarizing the layer 105B, in combination with the material loss 105L and the stringent requirements with respect to the aspect ratio of the contact elements 110, 111, the required minimum height 105R may be difficult to be achieved in sophisticated applications, such as the formation of devices of the 65 nm or 45 nm technology.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Method of forming an interlayer dielectric material having different removal rates during CMP


An optical-disc apparatus comprising: a laser-light source; an objective lens; an aberration-correction lens to be moved in an optical-axis direction according to a cover-layer thickness of an optical disc; a stepping motor; a driving unit to generate a driving pulse for the motor; a storage unit to store current-position information of the aberration-correction lens based on the number of the pulse; and a control unit to control the driving unit so that the aberration-correction lens is moved between a first position set in a mechanical-movable range of the aberration-correction lens and a second position set on the objective-lens side relative to the first position, the driving unit being controlled so that the aberration-correction lens is moved to the second position when stop of disc rotation occurs, and is moved to a start position between the first-and-second positions according to the thickness based on the information when the stop is cancelled.

1. Field of the Invention
The present invention relates to an optical disc apparatus that controls a lens driving mechanism for driving an aberration correction lens in an optical axis direction according to a thickness of a cover layer of an optical disc.
2. Description of the Related Art
As an optical disc, a so-called multilayer optical disc is known such as Blu-ray Disc and DVD (Digital Versatile Disc), in which a recording layer is formed in a multilayered form. In such a multilayered disc, spherical aberration occurs in laser light converging to a recording layer due to a difference in thickness of a cover layer from a laser-light incident face to the recording layer among recording layers. Thus, especially in a multilayer optical disc such as Blu-ray Disc having improved recording density, the spherical aberration causes a failure in recording and reproducing, and thus, a lens driving mechanism is provided that is capable of driving an aberration correction lens in an optical axis direction according to the thickness of the cover layer of the optical disc in an optical pickup supporting the multilayer optical disc.
An optical disc apparatus including an optical pickup supporting a multilayered optical disc controls the lens driving mechanism so that the aberration correction lens is displaced in the optical axis direction corresponding to a recording layer for which recording and reproducing for the multilayer disc is performed.
The lens driving mechanism employs a stepping motor as a driving source for the aberration correction lens in general, and is configured such that a driving pulse for driving the stepping motor is generated from a motor driving circuit included in the optical disc apparatus so that the aberration correction lens is displaced in the optical axis direction. Also, lens control means for controlling the motor driving circuit is included in the optical disc apparatus, and the motor driving circuit is controlled by the lens control means to generate the driving pulse for driving the stepping motor.
The optical disc apparatus needs to grasp a displacement position of the aberration correction lens in order to control the aberration correction lens of the lens driving mechanism. The optical pickup includes a position detection element such as a photo interrupter as shown in Japanese Patent Laid-Open Publication No. 2007-328875, for example, so as to be capable of detecting that the aberration correction lens is displaced to a reference position, and measures a distance from the reference position, to control the displacement position of the aberration correction lens.
As mentioned above, if the optical pickup is configured including a position detection element for detecting a reference position of the aberration correction lens, the position of the aberration correction lens can be controlled based on the reference position.
However, provision of the position detection element in the lens driving mechanism involves an increase in the number of components and of assembling processes, which is disadvantageous in terms of cost. Thus, a lens driving mechanism without the position detection element is required, however, if there is no position detection element, it is necessary that a reference position of the aberration correction lens is set to one of mechanical movable limits of the aberration correction lens in the lens driving mechanism and that the aberration correction lens is reliably pressed onto the one of the mechanical movable limits of the lens driving mechanism to be displaced to the reference position.
If the aberration correction lens is pressed onto the mechanical movable limit of the lens driving mechanism, a mechanical load is applied to the lens driving mechanism, which causes deterioration in durability of the lens driving mechanism. The mechanical load of the lens driving mechanism is in proportion to a length of a time period during which the aberration correction lens is pressed onto the mechanical movable limit of the lens driving mechanism and to magnitude in kinetic energy of the pressing. Thus, when the aberration correction lens is returned to the reference position, it is necessary to reduce the length of the time period during which the aberration correction lens is pressed onto the mechanical movable limit of the lens driving mechanism as much as possible and to reduce the kinetic energy of the pressing as much as possible.


For enlarging the application range of samples capable of being treated, decreasing the amount of samples used, preventing deterioration of samples by a change with the passage of time and preventing mixing of samples by diffusion, a micro fluidics system according to the present invention comprises a sample server which stores plural samples and which has sample efflux portions, a microchip for feeding samples to a treating portion through plural sample introducing portions communicating with the sample efflux portions and further through a microchannel, allowing the samples to be subjected to a predetermined treatment, and a sample feeder for feeding the samples stored in the sample server to the sample introducing portions through the sample efflux portions. The sample feeder comprises valves for opening and closing communication paths between the sample efflux portions of the sample server and the sample introducing portions of the microchip and pressurizing devices for pressurizing the samples stored in the sample server and pushing them out into the sample introducing portions in an open condition of the valves.

Integration techniques for performing chemical reactions in a very small space are being spotlighted from the standpoint of speed-up of chemical reactions, as well as reaction and analysis using a very small amount of sample. In a microchemical system using a microchip, which is one of chemical reaction integrating techniques, there are provided an inlet port for introducing a sample into the microchip and a microchannel connected to the inlet port. Within the microchannel there are performed such sample treatments as reaction, separation, extraction, detection, mixing, synthesis, and analysis. As examples of reactions performed in the microchemical system there are diazotization reaction, nitration reaction and antigen-antibody reaction. As examples of extraction and separation there are solvent extraction, electrophoretic separation and column separation.
In an electrophoretic apparatus described in Patent Literature 1, a plate member is formed integrally by bonding first and second substrates, a groove for analysis provided with a buffer sump and a groove for sample injection are formed in both end portions of the first substrate, a through hole is formed in the second substrate at a position opposed to the buffer sump in the first substrate, and an electrode film for the application of voltage is formed on an inner wall of the through hole and also around both sides of the through hole. In this electrophoretic apparatus, connection is made through the electrode film to a high voltage source installed in the body of the apparatus to effect the application of voltage, allowing migration to take place.
Another conventional micro fluidics system has been proposed for example in Japanese Patent Laid-Open No. 2003-114229 (Patent Literature 2) in which a sample is conveyed to a microchip or a microplate with use of a syringe pump.
A measuring analysis equipment using a microchip in Patent Literature 2 has a microchip, the microchip being provided with a first very small channel for allowing a sample to flow therethrough, a second very small channel for allowing a marker substance to flow therethrough, a very small reaction channel formed by a combination of the first and second channels, and a reactive site provided in the reaction channel and with a specific binding substance fixed thereto. A syringe pump is connected through a silicon tube to the first and second channels in the microchip and both sample and marker substance are fed from the syringe pump.
Patent Literature 1: Japanese Patent Laid-Open No. H8(1996)-178897
Patent Literature 2: Japanese Patent Laid-Open No. 2003-114229

Micro fluidics system and treating method using same


A digitally controllable valve has a main valve member mounted on a diaphragm for movement sealing and exposing a main valve seat. A flow restriction on the main valve member varies the flow rate as a function of displacement of the main valve member from the main valve seat. Pressure in a reservoir above the diaphragm is controlled by two pilot valves respectively connected to the inlet and outlet ports of the main valve, one of which has fluid passageway with a larger minimum cross sectional area than the other. Both pilots communicate with the reservoir through a single common bleed opening which has an area less than the minimum cross sectional areas of pilot valve flow passageways.

This invention relates to a valve for controlling the flow rate of a fluid in response to a digital electrical signal. Such valves are used for blending and mixing liquids, e.g., in the dispensing of gasoline.
A digitally controllable valve has a main diaphragm valve connected to two pilot solenoid valves. The pilot valves are independently opened and closed to control the volume in the chamber immediately over the main diaphragm or piston.
To obtain constant volume rate of primary flow, i.e., flow through the seat of the main valve, both pilot valves are closed via their respective solenoids and the outlet pilot valve connected to the outlet port of the main valve is pulsed open to gradually relieve the fluid pressure from behind the diaphragm. In response to the pulsing, the diaphragm moves up by a controlled distance depending upon the width of the pulse and the number of pulses applied, and fluid is allowed to escape from behind the main diaphragm. By this method, the diaphragm can be incrementally raised off of the main valve seat to allow controlled opening in digital stages. To close the main valve, the outlet pilot valve is closed and the inlet pilot valve is opened by pulsing its solenoid. This now restores fluid above the diaphragm to digitally lower the diaphragm in controlled increments.
In such digitally controllable valves, a main valve member mounted on a diaphragm is movable within an opening in a main valve seat communicating with a main valve outlet port to define a variable cross sectional passageway through which fluid can flow from the main valve inlet port to its outlet port. The cross sectional area of the passageway is controlled by raising and lowering the main valve member from a sealing position in engagement with the main valve seat.
When the main valve member is in engagement with the main valve seat, fluid flow from the inlet port to the outlet port through the main valve seat is prevented. As the main valve member is lifted off of the main valve seat, fluid from the inlet port flows through the passageway between the main valve member and seat. The greater the displacement of the main valve member from the main valve seat, the larger is the passageway, and hence the rate of flow.
It is also known in the prior art to connect each of the inlet and outlet ports of the main valve to a reservoir on a side of the diaphragm opposite the main valve seat, through respective inlet and outlet solenoid pilot valves to control the fluid pressure above the diaphragm. The pilot valves are controlled by electrical power supplies which produce voltage pulses of width and frequency selected to incrementally raise and lower the main valve member to achieve a desired flow rate versus time profile. In certain applications, e.g., in blending and mixing valves used in the gasoline dispensing industry, it is desirable to be able to increase and decrease flow rates symmetrically, that is, to have the flow rate of a one constituent of a mixture through one valve increase at the same rate that the flow rate of another constituent fluid passed through another valve decreases so that the net flow rate of the blended mixture remains constant.
Referring to FIG. 1 there is shown a prior art, digitally controllable valve 1 having a main valve 3, an inlet solenoid pilot valve 5, and an outlet pilot solenoid valve 7. Pressure above a diaphragm 9 is controlled through two bleed passageways 11, 13 respectively connected to an outlet port of the inlet pilot valve 5 and an inlet port of the outlet pilot valve 7. Fluid enters the region 8 above the diaphragm 9 from the inlet pilot valve 5 and exits that region 8 through the outlet pilot valve 7. During a "low flow" mode of operation, both the inlet and outlet valves 5, 7 are opened and the main valve 3 closes to shunt all fluid flow through the pilot valves 5, 7.
Closure of the main valve 3 in response to the opening of both pilot valves 5, 7 is achieved by making the minimum cross sectional area of fluid flow through the inlet valve greater than the minimum cross sectional area of fluid flow through the outlet valve. This can be accomplished by making the diameter of the the inlet valve seat opening greater than the diameter of the outlet valve seat opening.
The result is that fluid from the inlet pilot valve 5 enters the region 8 above the diaphragm 9 faster than it can exit causing an increase in pressure above the diaphragm 9 which urges the diaphragm 9 to engage and seal a main valve seat 15 thereby preventing fluid flow within the main valve 3.
The introduction of this incongruence between the inlet and outlet pilot valves 5, 7 prevents symmetrical operation of the digitally controllable valve 1 for increasing and decreasing flow rate. That is, if two identical digitally controllable valves used to blend two constituent fluids of a mixture are energized by the same signal, one in an increasing flow rate mode and the other in a decreasing flow rate mode, the magnitudes of the rates of increasing and decreasing flow of the respective constituents will be unequal and the net flow rate of the blend will vary.
In one of the two identical digitally controllable valves 1 which is dispensing the constituent fluid with an increasing flow rate, its inlet valve is closed to prevent entry of fluid into the region 8 above the diaphragm 9 and the outlet valve is opened to enable the fluid above the diaphragm 9 to exit through the outlet port thereby causing the main valve member to move away from the main valve seat to increase the rate of flow. A desired flow rate vs. time profile is achieved by energizing the solenoid coil of the outlet pilot valve 7 with a train of voltage pulses having a corresponding pulse width and frequency.
In the other of the two identical digitally controllable valves 1 which is dispensing its constituent fluid with a decreasing flow rate, its inlet valve is opened to permit entry of fluid into the region 8 above the diaphragm 9 and its outlet valve is closed to prevent the fluid above the diaphragm 9 from exiting through the outlet port thereby causing the valve member to move toward from the valve seat to decrease the rate of flow. It is desired to achieve a complementary profile with respect to the increasing flow rate of the other constituent, that is, to have the flow rate decrease in accordance with a profile identical to but 180 degrees out of phase with the flow rate vs. time profile of the increasing flow rate constituent fluid. Due to the incongruence in the flow path dimensions of the valves 5, 7, this cannot be achieved by pulsing the outlet pilot valve 7 of one digitally controllable valve 1 for increasing the flow rate of its constituent with the same signal used to pulse the inlet pilot valve 5 of the other digitally controllable valve 1 for decreasing the flow crate of the its constituent fluid.
Hence in prior art digitally controllable valves, the achievement of complementary increasing and decreasing flow rate profiles has required that the electrical signals used to increase flow rate be altered with respect to those used to decrease flow rate to compensate for the incongruence between the bleed passageways leading from above the diaphragm 9 to the inlet and outlet pilot valves 5, 7. Such compensation requires duplication of hardware and/or use of complex circuitry and is difficult to achieve.


In a data transmission method of the present invention, when transmission data are converted into the characters and the characters are transmitted as transmission signals in accordance with inputted data and a data transmission instruction, the interval between the data groups after the character conversion is broadened and then the characters are transmitted in a case where it is judged that the interval between the data groups after the character conversion is shorter than the interval between the data groups before the character conversion. This ensures communication devices to stably transmit and receive the data group even when the interval between the data groups after the character conversion is different from the interval between the data groups before the character conversion due to timing caused by the character conversion of the data.

In recent years, in accordance with digitalization of information technology, high-speed serial communication of digital signals (hereinafter referred to as digital communication) has been widely used in, for example, data transmission between LSIs (large-scale integration), wireless communication, and optical fiber communication.
In the digital communication, it is required to send timing information in addition to transmission data so as to correctly sample data. Furthermore, most of the high-speed serial communication does not transmit the timing information via an extra line other than lines for transmitting data, to reduce the number of communication lines. Instead, coding is used with providing redundancy to the data, so as to ensure the data to be transited within a constant period.
In 8B10B coding as an example of the coding, a transmitting end converts 8-bit data and device state information into 10-bit characters and transmits the 10-bit characters, and then a receiving end converts back the received 10-bit characters into the 8-bit data and the device state information.
The transmitting end converts the data and the device information into the characters in accordance with timings shown in FIG. 12, for example.
More specifically, in FIG. 12, in the case where a cycle of a clock 1200 for operating a system is one-fourth of a cycle of transmission characters, when a data transmission instruction 1202 demands transmission and data 1210, 1220, and 1230 in a data group 1201 are transmitted, the data 1210, 1220 and 1230 are converted into the characters in accordance with timings of character groups 1203 through 1206.
Here, characters 1211 to 1214 are converted from the data 1210, characters 1221 to 1224 are converted from the data 1220, and characters 1231 to 1234 are converted from the data 1230.
However, when the technique is carried out, an interval between the data groups may change due to timing when the data is converted into the characters. This may occur when the interval between the data groups becomes a value that cannot be divided by a time unit of the characters. For example, when the character unit is 80 ns, the interval between the character groups, which are converted from the data group, becomes 640 ns or 720 ns, in a case where a closest value of the character unit, namely the interval between the data groups (before the character conversion) is 700 ns. Then, when the character unit is 640 ns, a receiving device may not be able to capture the data group.
Specifically, as shown in FIG. 13, in the case where a cycle of a clock 1300 for operating the system is one-fourth of a cycle of the transmission characters, when the data transmission instruction 1302 demands transmission and data 1310, 1320 and 1330 in the data group 1301 are transmitted, in which an interval between the data 1310 and the data 1320 is seven cycles of the clock, an interval between characters 1311 to 1313 converted from the data 1310 and characters 1321 to 1323 converted from the data 1320 becomes eight cycles of the clock in transmission character groups 1303, 1304 and 1305, whereas an interval between the data 1314 converted from the data 1310 and the data 1324 converted from the data 1320 becomes four cycles of the clock in a transmission character group 1306, after the character conversion is carried out.
As described above, in the serial communication in which the device state information and the data group are transmitted and received per character unit, the interval between the data groups may be changed.
In such a case, it does not matter when the interval between the data groups after the character conversion becomes identical with or longer than the interval between the data groups before the character conversion. However, when the interval between the data groups after the character conversion becomes smaller than a constant value, due to timing caused by the character conversion, (a) a receiving device or (b) the other device to which the receiving device has transmitted the received data group via a channel in which a communication mode is not specified, cannot capture the data group.
Therefore, the conventional transmission method in which the data are converted into the characters may cause a problem that the receiving device cannot stably receive the data group after the character conversion, in other words, the transmitting device and the receiving device cannot stably communicate with each other (cannot transmit and receive the data group).

Data transmission method, transmission circuit, and communication device


A sheet conveying apparatus for feeding sheets or sheet bundles of differing thickness and a sheet sorting apparatus using the same includes a rotatable belt convey member, and a sponge roller arranged in an opposed relation to the rotatable belt convey member. Preferably, the sheet feeding apparatus further includes a shaft-to-shaft spacer for ensuring a minimum shaft-to-shaft distance between the rotatable belt convey member and the sponge roller, and a pressurizing device for urging the sponge roller and the rotatable belt convey member against each other.

1. Field of the Invention
The present invention relates to a sheet feeding apparatus and a sheet sorting apparatus having such a sheet feeding apparatus, and more particularly, it relates to a sheet sorting apparatus which is connected to a copying machine having a reading apparatus, a facsimile machine (communication system), a printer connected to a computer, and a binding apparatus (stapler, glueing apparatus) to sort sheets or sheet bundles.
2. Related Background Art
In some conventional sheet or sheet bundle feeding apparatuses incorporated into a sheet sorting apparatus or an image forming apparatus, a thickness of a sheet bundle being fed is detected, and an upper roller is separated from a lower roller in accordance with the detected thickness so that the sheet bundle can be conveyed by the pair of upper and lower rollers.
However, in the above conventional case, since the thickness of the sheet bundle being fed must be detected and the upper roller must be separated from the lower roller in accordance with the detected thickness, the apparatus becomes very complex and expensive.

Sheet conveying apparatus and sheet sorting apparatus using the same


An electrical connector comprises an insulative housing, a plurality of terminals assembled to the insulative housing and a pair of fastening elements assembled to the insulative housing. The insulative housing comprises an elongated base portion and a pair of retaining slots respectively disposed at two sides thereof. The base portion defines a mating face and an engaging face opposite to the mating face. A pair of fastening elements are assembled to the pair of retaining slots of the insulative housing, each fastening element comprises a fixing portion received in the retaining slot and a resilient arm disposed outside of the retaining slot and opposite to the fixing portion.

1. Field of the Invention
The present invention relates to an electrical connector, and particularly to an electrical connector mounting on a print circuit board.
2. Description of the Prior Art
An electrical connector is usually required to establish a electrical connection between a printed circuit board (PCB) and an electronic device, such as a hard disk drive. Please refer to US patent application publication number 2006/0099836 A1 applied by Ho, Ho discloses an electrical connector adapted to a PCB. Said electrical connector comprises an elongated insulating housing, a plurality of terminals received in the insulating housing and a pair of gaskets positioned at two lateral sides of the insulating housing corresponding to a pair of holes of the PCB. The PCB is usually thin, and accordingly easier to decrease the structural intensity for defining a pair of holes. Differently, U.S. Pat. No. 6,767,235 discloses an electrical connector and introduce a method for preventing destroying the PCB. The insulating housing respectively defines a pair of locking arms at two lateral sides, and therefore a pair of retaining slots can accommodate the PCB. However, the electrical connector is also small to avoid consuming too much space. Accordingly, the locking arms are provided with small form factor. When the PCB is inserted into the retaining slots, the locking arms are also liable to be destroyed, furthermore plastic scraps may be produced to dirty the terminals. Reliable electrical connection will be affected.
Further more, some other methods are employed to overcome the defects, but all fail.
Hence, an improved electrical connector is desired to overcome the disadvantages of the prior art.

Electrical connector mounted on edge of PCB


A method of manufacturing a lighting module comprises: mounting one or more light emitting diode (LED) packages on a circuit board to define a lighting unit; and injection overmolding the entire lighting unit except the one or more LED packages using a single type of overmolding material. A lighting module comprises: one or more LED packages mounted on a circuit board; and an injection overmolding sealing the circuit board, the injection overmolding not having openings corresponding to piece holding pins, the injection overmolding not covering at least a light emitting portion of the one or more LED packages.

The following relates to the optoelectronic arts. It finds particular application in illuminated signage. However, the following will find more general application in conjunction with illumination generally, and in lighting applications such as track lighting, illumination of pathways, and so forth.
Lighting units incorporating light emitting diodes mounted on circuit boards are known. In some known embodiments, these devices include a flexible electrical power cord and a plurality of modules attached to the cord in spaced apart fashion, with each module including a main body supporting one or more light emitting diode (LED) packages. These flexible lighting strips find application in various settings, such as illumination of channel lettering for outdoor signage, lighting of curved walkways, and so forth.
Although such flexible lighting strips are known, useful improvements continue to be sought after to enhance manufacturability, ease of installation, reliability and robustness of the devices. Reliability and robustness, for example, is of concern for all applications, and is of particular concern for outdoor applications in which the LED lighting strip may be exposed to rain, snow, large temperature swings, and other environmental hardships. Ease of installation is also of concern for all applications, and is of particular concern for the outdoor signage industry which represents a sizable national and global market for such flexible lighting strips. For example, flexible lighting strips incorporating light emitting diodes are placed in channel letter housings to form illuminated lettering for demarcating buildings, businesses, and so forth.
The following discloses improvements in flexible lighting strips including light emitting diodes.


Provided are a charge and discharge control circuit capable of reducing a circuit size, and a battery device. In a charger reverse connection detection circuit (116), a comparison circuit or the like is not used, and two NMOS transistors are used, whereby circuit sizes of the reverse connection detection circuit (116) and a charge and discharge control circuit (110) are reduced. Accordingly, a consumption current is reduced, and a manufacturing cost is also reduced.

1. Field of the Invention
The present invention relates to a charge and discharge control circuit which controls charge and discharge of a battery, and to a battery device.
2. Description of the Related Art Recently, various portable electronic devices have become widespread. Those portable electronic devices are usually driven by a battery device onto which a battery is mounted.
The battery is connected to the portable electronic device when the portable electronic device is used, and the battery is connected to a charger when the battery is charged. Here, as a dangerous condition of the battery, there exists a state of a reverse-connected charger, in which the charger is connected to the battery with its polarities being reversed to those of the battery when the battery is charged.
As measures against this, there is proposed a technology in which, when the charger is connected to the battery with its polarities being reversed to those of the battery, and accordingly a voltage of a detection terminal becomes higher than a power supply voltage and a comparison circuit detects the above, discharge of the battery is stopped (for example, see JP 2006-210026 A).
However, the comparison circuit is used in such a case as described above, which correspondingly increases a circuit size. Accordingly, a consumption current is increased, and the manufacturing cost is also increased.

Charge and discharge control circuit and battery device


Systems, apparatus, and methods for selectively, preferentially, and/or actively removing or trapping SO3 from un-oxidized sulfur constituents in an exhaust gas effluent produced by an internal combustion engine are disclosed. Also disclosed are embodiments for regenerating an SO3 trap.

The amount of sulfur in diesel fuel can vary greatly depending on the market in which the fuel is sold and the regulatory requirements in the markets. Sulfur in diesel fuel can adsorb/absorb onto aftertreatment system components and reduce their performance. In aftertreatment systems in which there is no active regeneration of a diesel particulate filter, the exhaust temperature often is not high enough to remove the adsorbed sulfur to restore performance of the aftertreatment component. In addition, for systems which include thermal particulate filter regeneration, the need to regenerate the particulate filter due to sulfur adsorption on aftertreatment system components decreases efficiency and fuel economy. Furthermore, systems which include sulfur traps that accumulate sulfur during operation may require frequent replacement of the sulfur trap due to the high sulfur accumulation on the trap. Therefore there remains a need for further improvements in this technology area.


A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.

1. Field of the Invention
The invention relates generally to semiconductor fin structures. More particularly, the invention relates to semiconductor fin structures with enhanced performance.
2. Description of the Related Art
Semiconductor circuits typically include both active semiconductor devices, such as but not limited to transistors and diodes, as well as passive devices, such as but not limited to resistors and capacitors. As semiconductor technology has advanced over several decades, both the active semiconductor devices and the passive devices have conventionally been scaled to increasingly smaller dimensions to reduce costs.
In an effort to provide for continued scaling of semiconductor structures to continuously smaller dimensions while maintaining or enhancing semiconductor device performance, the design and fabrication of semiconductor fin devices and semiconductor fin structures has recently evolved within the semiconductor fabrication art. Semiconductor fin devices and semiconductor fin structures, and in particular finFET devices and finFET structures, typically comprise vertical semiconductor channel structures that are fabricated using a semiconductor fin (i.e., including a vertical semiconductor surface rather than a planar semiconductor surface relative to a plane of a semiconductor substrate) as a channel region for the semiconductor fin devices and the semiconductor fin structures. Within the context of a finFET structure, a gate dielectric is located upon at least one vertical surface of the semiconductor fin. An inverted U shaped gate electrode is then located over the gate dielectric and the semiconductor fin. Since the sidewall surfaces, and sometimes also the top surface, of the semiconductor fin primarily comprise a channel region of the finFET structure, a finFET structure may in general may be scaled with increased channel dimensions in a vertical direction, to provide a constant or enhanced channel area of the finFET structure while decreasing an aerial surface area requirement of the finFET structure. finFET structures certainly provide advantages within semiconductor device fabrication and semiconductor structure fabrication since finFET structures allow for constant or increased channel region areas within finFET structures while using decreased semiconductor substrate areas when fabricating the finFET structures.
Various finFET structures having desirable properties, and methods for fabricating those finFET structures, are known in the semiconductor fabrication art.
For example, Fried et al., in U.S. Pat. No. 6,664,582, teaches a finFET structure integrated with a fin-capacitor structure to provide a semiconductor fin memory structure. By integrating the finFET structure with the fin-capacitor structure, the semiconductor fin memory structure may be fabricated with improved semiconductor fin memory structure density without overly increasing fabrication cost and complexity of the semiconductor fin memory structure.
In addition, Joshi et al., in U.S. Pub. No. 2005/0017377 and U.S. Pat. No. 6,921,982, teaches a semiconductor fin structure, such as a finFET structure, that includes a semiconductor fin that includes a semiconductor channel comprising a semiconductor channel core layer having a semiconductor channel envelope layer laminated thereto that has a different lattice structure than the semiconductor channel core layer. The different lattice structures for the semiconductor channel core layer and the semiconductor channel envelope layer provide a lattice mismatch therebetween that in turn introduces a strain into the semiconductor channel within the semiconductor fin structure.
Further, Zhu et al., in U.S. Pub. No. 2005/0239242, teaches a semiconductor fin structure, such as a finFET structure, that includes a plurality of stacked semiconductor fins. The plurality of stacked semiconductor fins within the semiconductor fin structure allows for improved circuit density while accommodating mobility differences within n-finFET and p-finFET devices that may be fabricated using the plurality of stacked semiconductor fins within the context of a single semiconductor substrate.
Still further, Fischer et al., in U.S. Pub. No. 2006/0022248, teaches a semiconductor fin structure, such as a finFET structure, having a gate that controls only a central region of a semiconductor fin within the semiconductor fin structure. Such gate control over only a limited portion of the semiconductor fin minimizes undesirable leakage paths within a semiconductor fin device that comprises the semiconductor fin structure.
Finally, Manger in U.S. Pat. No. 7,074,660, teaches a finFET structure, and a method for fabricating the finFET structure, that allows for an enhanced aerial density of a plurality of finFET devices within the finFET structure. The foregoing enhanced aerial density of the finFET devices within the finFET structure is provided by using a non-photolithographic method for fabricating a plurality of contacts within the plurality of finFET devices.
Semiconductor fin devices and structures, such as in particular finFET devices and structures, are certain to become increasingly prominent as semiconductor technology advances. Thus, desirable are semiconductor fin devices and structures having enhanced performance and enhanced functionality, and methods for fabrication thereof.

Method for fabrication of fin memory structure

International Business Machines Corporation


A method for forming a structured tungsten layer and a method for forming a semiconductor device using the same. A first tungsten layer is formed with an atomic layer deposition (ALD) method. A second tungsten layer is formed on the first tungsten layer with a chemical vapor deposition (CVD) method. A third tungsten layer is formed on the second tungsten layer with the ALD method to complete the structured tungsten layer.

1. Field of the Invention
The present invention relates to a semiconductor manufacturing method. More particularly, the present invention relates to methods for forming a structured tungsten layer and forming a semiconductor device using the same.
2. Description of the Related Art
In a semiconductor device, plugs and interconnections are typically formed of low resistance material, e.g., metals such as aluminum, copper or tungsten. Tungsten may exhibit good step coverage and, accordingly, the use of tungsten has increased as semiconductor devices have become more highly integrated and critical dimensions have been reduced. The use of tungsten also has other advantages as a result of its various other properties, e.g., a relatively high melting point of more than 3400° C. and a strong resistance to electromigration.
In a semiconductor device, a tungsten layer is typically formed using a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. Forming a tungsten layer for interconnections or contact plugs by ALD may require significant process time, which may result in reduced manufacturing throughput. Therefore, the CVD method may be preferred, because this method typically can be carried out in less time.
However, the CVD method typically exhibits poorer step coverage than the ALD method. In order to accommodate the various deficiencies in these methods, tungsten layers have been formed using ALD to provide nucleation, and then forming a bulk layer of tungsten to a desired thickness using CVD. However, the resulting tungsten layer may have an upper surface that is very rough and nonuniform, as illustrated in FIG. 1.
If a tungsten layer having a nonuniform upper surface is formed using this conventional process, various defects may result. For example, where subsequent processes are performed, particles may remain at recessed regions of the rough upper surface, which may give rise to various problems. In addition, if another interconnection or conductive plug is formed during a subsequent process on the tungsten layer produced by this conventional method, voids may be formed on the upper surface that can cause problems, e.g., contact failures, a rise in interfacial resistance, etc. Further, the problems caused by the rough upper surface may become more serious as semiconductor devices become more highly integrated.

Methods for forming a structured tungsten layer and forming a semiconductor device using the same


Implantable access port for removal and/or return of fluids to a patient, comprising an internal conduit connectable at its proximal end to the access port and at its distal end to a vascular structure of the patient; an external conduit connectable at its proximal end to the access port and at its distal end to an extracorporeal device; and a transcutaneous coupling member destined to be anchored in a tissue of the patient and comprising a first valve system operable to be in an open or closed configuration; the coupling member further comprises a second valve system removably connectable to the first valve system and operable to be in an open or closed configuration, such as to establish fluid communication between the internal and external conduits when the first and second valve systems are connected and in open configuration.

Access to a patient's lumen can be established by a variety of temporary and permanently implanted devices. However, despite several types of lumen access ports and devices proposed over recent years, body lumen access remains one of the most problematic areas in the treatment of patients requiring long-term access. Most simply, temporary access can be provided by the direct percutaneous introduction of a needle through the patient's skin and into a blood vessel. While such a direct approach is relatively straightforward and suitable for applications such as intravenous feeding, short term intravenous drug delivery and other applications which are limited in time, they are not suitable for hemodialysis and other extracorporeal procedures that must be repeated periodically and often for the patient's lifetime.
Haemodialysis patients commonly undergo a placement of one of the two, or both, widely accepted long-term vascular access options during the term of their treatment. It is estimated that 50% of hospitalization time of haemodialysis patients is related to problems of access to the vascular system of the human body.
On the one hand, WO 2005/023336 discloses a surgical placement of an arteriovenous synthetic graft connecting a patient's adjacent peripheral artery and vein to divert some of the arterial blood flow through the graft. The other is an arteriovenous fistula, a direct surgical connection between adjacent artery and vein with no synthetic conduit used. In both cases, the blood circulation is accessed with two needles inserted through the skin into either the synthetic graft in the former case, or the venous portion of an arteriovenous fistula in the latter scenario. Needle stick injuries and infections contribute to the loss of these types of accesses.
US 2006/0047249, by Shubayev and Elyav, proposes a percutaneous vascular access system. This system consists of a cylindrical device body having a pair of hollow nipples extending from the exterior to the interior and a rotatable inner core with two positions to open and close the connections. However, the fixation of such a device to the skin or other soft tissue of the body, i.e. as a tissue anchor according to US 2006/0047249, raises a number of problems, such as the danger of displacement during use caused by body movements or exposure to mechanic stress.
Bone implanted access devices have also be proposed. For example, WO 2007/051339 concerns an access port comprising a central cylindrical portion, and external and internal canal communicating through a valve. Here, the access port contains only one fluid canal and is destined to be implanted in a tooth-supporting bone.


A heat dissipation device includes a base for contacting an electronic device. Two first heat pipes are arranged on and thermally engaged with the base for absorbing heat from the electronic device and spread the heat to the base. Each of the two first heat pipes is sinuous and defines two U-shaped portions on the base. Two second heat pipes are thermally engaged with the base for absorbing heat from the electronic device and spreading the heat to the base. Each of the two second heat pipes has a first section located at a corresponding one of the two U-shaped portions on the base. A fin set is located on the base for dissipating heat in the base to ambient air.

1. Field of the Invention
The present invention relates to heat dissipation devices for use in removing heat from electronic devices, and more particularly to a heat dissipation device incorporating heat pipes for improving heat dissipation efficiency of the heat dissipation device.
2. Description of Related Art
During operation of an electronic device such as a computer central processing unit (CPU) mounted on a printed circuit board, a large amount of heat is often produced. The heat must be quickly removed from the CPU to prevent it from becoming unstable or being damaged. Typically, a heat dissipation device is attached to an outer surface of the CPU to absorb heat from the CPU. The heat absorbed by the heat dissipation device is then dissipated to ambient air.
Conventionally, a heat dissipation device comprises a solid metal base attached on the CPU, and a plurality of fins arranged on the base. The base is intimately attached to the CPU thereby absorbing the heat generated by the CPU. Most of the heat accumulated at the base is transferred firstly to the fins and then dissipates away from the fins. However, as electronics technology continues to advance, increasing amounts of heat are being generated by powerful state-of-the-art CPUs. As a result, many conventional heat dissipation devices are no longer able to efficiently remove heat from these CPUs.
In order to overcome the above set out problems, a type of heat dissipation device illustrated as follows can be used. The heat dissipation device comprises a base for absorbing heat from a heat generating electronic device, a heat pipe thermally combined to the base, and a plurality of fins arranged on the base. Generally, the heat pipe is linear. The base defines a corresponding groove substantially in a center thereof receiving the heat pipe therein. In use, the base contacts the electronic device and absorbs heat from the electronic device. The heat in the base is absorbed by the heat pipe, and the heat pipe transfers the heat from the center to other parts of the base. The heat in the base spreads to the fins to be dissipated to ambient air. However, the heat pipe is straight, which results in a thermal contact area between the base and the heat pipe is considerably small. Consequently, the heat in the center of the base cannot be transmitted to other parts of the base rapidly and evenly. The heat generated by the electronic device accumulates in the center of the base and the electronic device. Normal functions and abilities of the electronic device are adversely affected. Therefore, the heat dissipation device needs to be improved.
What is needed, therefore, is a heat dissipation device has a large heat dissipation capacity for an electronic device.

Heat dissipation device with multiple heat pipes

Fu Zhun Precision Industry (Shen Zhen) Co., Ltd.


The invention relates to a circuit board testing method, wherein an array of several circuits of a circuit board are short-circuited and further circuits are short-circuit tested by applying a high test voltage relative to said array of circuits, as a result of which the number of tests, which are normally highly time-intensive due to the high voltages, is drastically reduced since the further circuits do not need to be tested discretely relative to each circuit of the circuit array.

After circuit boards have been manufactured but prior to the population of the boards with discrete electrical components and integrated circuits, it is common to test the circuits in the boards to ensure they have been properly formed.
Known devices for testing unpopulated circuit boards are generally divided into two groups: 1) devices using an adapter that contacts simultaneously to all circuit test points of the circuit board; and 2) so-called finger testing devices or finger testers that sequentially scan individual test points of the circuit boards using two or more test fingers.
Irrespective of the type of device involved, the individual circuits of the boards are tested for open-circuits and shorts. In open-circuit testing, the testing device determines whether an open circuit condition exists between two or more test point when the board's specifications dictate that the test points should be electrically connected. In short-circuit testing, the testing device determines whether an electrical connection exists between two or more test points when the board's specifications dictates that no electrical connection should exist. Typically, short circuit testing includes detection of both low and high impedance shorts.
Generally, both short-circuit and open-circuit testing are laborious and time-intensive processes. The presence or not of a short-circuit between each nominally discrete circuit must be determined, and each branch of a nominally single circuit must be tested for an open-circuit. In many modern circuit boards having a large number of separate and/or highly branched circuits, a high number of individual tests must be performed.
Attempts have been made to optimize the individual tests and to minimize the number needed to validate a given unpopulated circuit board. For example, short-circuit tests are performed with elevated voltages. Circuit boards thus tested tend to have high long-term reliability since the high voltage testing tends to exposed any transient short between the individual circuits. Testing only with conventional low test voltages make it nearly impossible to detect pseudo-shorts resulting from crosstalk between two circuits.


A production apparatus ensures wireless communication without interference. An antenna portion 310 at a robotic arm includes a transmitting antenna portion 311 having a plurality of transmitting antennas 321 to 328 and a receiving antenna portion 312 having a plurality of receiving antennas 331 to 338. A transmitting side switcher circuit 361 changes over a transmitting antenna to be connected to a transmitter 351 among the plurality of transmitting antennas 321 to 328 in conjunction with an attitude information of the robotic arm, and changes an effective direction of a directional characteristic of the transmitting antenna portion 311. A receiving side switcher circuit 362 changes over a receiving antenna to be connected to a receiver 352 among the plurality of receiving antennas 331 to 338 in conjunction with the attitude information of the robotic arm and changes the effective direction of the directional characteristic of the receiving antenna portion 312.

1. Field of the Invention
The present invention relates to a production apparatus which is provided with a robotic arm.
2. Description of the Related Art
In recent years, an assembly production apparatus is demanded which achieves an assembly operation by a robotic arm in place of the assembly operation by a human hand. In the assembly operation by the human hand, in order to efficiently cope with production having a wide variety of products in small quantities, a human cell production system is introduced which removes a conveyor, conveys a workpiece by a human hand, and is responsible for a fixed process; and the human cell production system is rearranged according to a production item. A robot cell is a cell in which one human cell in this human cell production system is replaced with the assembly production apparatus by the robotic arm, and there is a production apparatus described in Japanese Patent Application Laid-Open No. 2011-240443, for instance.
The robotic arm of these production apparatuses has a tool such as a camera and a hand provided at the tip portion thereof, and control signals and image signals to be transmitted to the tool and the hand are usually transmitted/received thereto/therefrom, through cables built into the robotic arm.
However, the cables which are built into the robotic arm are exposed to a severe moving condition. Among the cables, a high-speed communication line which is used for the control and transmission of an image needs a shield and the like, and accordingly has such a drawback that a durability life is short.
In addition, there is the case where the camera or the like becomes unnecessary depending on an assembly process, and is required to be capable of being easily removed. Usually, in such a case, an image communication cable of the camera is routed from the outside of the robotic arm, and accordingly when the robot cell is rearranged, there have been such drawbacks that a complicated operation such as routing of a cable is needed, and a lead time for a start of the apparatus becomes long.
On the other hand, a method is known which improves the drawbacks by abolishing the image communication cable and exchanging such a high-speed signal through a wireless communication in a production apparatus described in Japanese Patent Application Laid-Open No. 2006-105782, for instance.
However, when the wireless communication is performed in the above described production apparatus such as the robot cell, the apparatus results in performing a large number of wireless communications in an extremely narrow area, and accordingly frequency channel for preventing electromagnetic waves from causing interference between adjacent production apparatuses becomes insufficient.
In recent years, in particular, a tool control signal of a camera, a robot hand and the like which are used in FA has been increasingly required to increase the speed, and in order to cope with the increase, a wireless unit is required to take measures of changing the frequency to a high band for securing the band, and the like.
In millimeter wave communication by a band of 60 GHz which is often used in high-speed wireless communication of an image, for instance, the number of channels which can be legally permitted is only four channels. In such a case, when there are four or more other production apparatuses which are adjacent to the production apparatus, there has been the case where the production apparatuses cannot be discriminated by the frequencies.
For this reason, when the wireless communication is heavily used in the production apparatus such as the robot cell, which has been described above, the interference of the communication occurs among the adjacent production apparatuses, and there have been problems that an error occurs due to a great decrease of a transmission speed of the wireless communication and an increase in a waiting time of the wireless unit, and that the production apparatus stops.
An object of the present invention is to provide a production apparatus which can stably perform wireless communication while avoiding the interference of communication with other production apparatuses.


A method for imaging a tooth surface, the method executed at least in part on a computer, directs an excitation signal toward the tooth from a scan head and obtains a depth-resolved response signal emanating from the tooth, wherein the response signal encodes tooth surface structure information. Liquid and tooth surfaces are segmented from the depth-resolved response signal. The tooth surface structure information is adjusted based on the segmented liquid. A 3D image of the tooth is reconstructed according to the depth-resolved response signal and the adjusted tooth surface structure information. The 3D image content is displayed, stored, or transmitted.

Structured light imaging has been used effectively for surface contour imaging of solid, highly opaque objects and has been used for imaging the surface contours for various portions of the human body and for obtaining detailed data about skin structure. In structured light imaging, a pattern of lines or other features is projected toward the surface of an object from a given angle. The projected pattern from the surface is then viewed from another angle as a contour image, taking advantage of triangulation in order to analyze surface information based on the appearance of contour lines. Phase shifting, in which the projected pattern is incrementally shifted spatially for obtaining additional measurements at the new locations, is typically applied as part of structured light projection imaging, used in order to complete the contour mapping of the surface and to increase overall resolution in the contour image.
Surface contour information can be particularly useful for assessment of tooth condition and is helpful for various types of dental procedures, such as for restorative dentistry. A number of techniques have been developed for obtaining surface contour information from various types of objects in medical, industrial, and other applications. Optical 3-dimensional (3D) measurement methods provide shape and depth information using light directed onto a surface in various ways. Among types of imaging methods used for contour imaging are those that generate a series of light patterns and use focus or triangulation to detect changes in surface shape over the illuminated area.
Accurate characterization of the surface contour for teeth and other intraoral structures can be compromised due to the effects of fluids. Water, saliva, blood, and other fluids that can collect on and around the teeth can cause difficulties for reflective imaging systems. FIG. 1 shows the effect of light refraction in the presence of fluid. Light projected from a projector P will be refracted by a fluid F and partially reflected at the air-fluid interface, surface FS. Thus, only a portion of the projected light impinges onto the tooth surface S. Similarly the backscattered light from the tooth surface S is again refracted at the fluid-air interface and captured by the camera C at another angle. Back-ray tracing of the projection beam and captured light beam locates an intersection point which is shifted toward the imaging system, causing image distortion. In FIG. 1, a dimension d shows the shift distance of reconstructed 3D data, appearing to be a real point on the tooth surface.
In addition to dimensional inaccuracy, reflection from the fluid can produce shining spots on images, saturated due to high reflection levels. The corresponding points cannot be used for point cloud reconstruction.
Thus, there is a need for methods and apparatus that surmount these problems and provide accurate contour imaging data for intraoral surface characterization.

Intraoral 3D scanner with fluid segmentation


In one embodiment, a semiconductor device having a die attach pad, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. The die attach pad may be sandwiched between the semiconductor die and the die attach pad. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock structure formed integrally with the die attach pad. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed.

Semiconductor devices may be implemented using various packaging technologies such as a plastic leaded chip carrier (herein after PLCC) package, a ball grid array package (herein after BOA), a pin grid array package (herein after PGA), a quad flat pack (herein after QFP), a printed circuit board (herein after PCB) package and so on. Certain packages, for example PLCC packages in light-emitting devices, may comprise a lead frame over a molded polymer material such as Polyphthalamide (herein after PPA), Polyamide or Epoxy resin encapsulant like MG 97. For surface mount type, leads extending from the lead frame may be bent so that the semiconductor devices can be soldered on a substrate without through-holes. One of the most popular semiconductor devices may be opto-electronic device. One characteristic of opto-electronic devices may be the feature of having a light source die or a radiation source die. Example of opto-electronic devices may be opto-couplers, light emitting devices, proximity sensors, encoders and other similar devices having a radiation source.
One way many semiconductor devices fail reliability test may be due to delamination of encapsulant or epoxy material surrounding a semiconductor die. After going through hundreds or thousands of temperature cycles, some semiconductor dies may be lifted-up from the die attach pad, causing an open circuit. One explanation of the failure may be due to delamination of the epoxy material. Further, the failure rate may be higher for industrial or automotive use semiconductor devices, which may be required to operate at wide range of temperatures. Additionally, the failure rate for opto-electronic devices may be relatively higher due to the use of substantially transparent epoxy as encapsulant body. Most epoxy used in opto-electronic devices may be susceptible to delamination especially. The result may be that the entire transparent encapsulant body, as well as the light source die may be lifted up from the die attach pad more easily, compared to non-optics types of devices.

Semiconductor device with an interlocking structure

Avago Technologies General IP (Singapore) Pte. Ltd.


In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

1) Field of Invention
The invention relates to stitching (strapping) methods of forming high-density Metal/polysilicon Oxide Nitride Oxide Silicon (MONOS) memory arrays with reduced bit line resistance, reduced control gate resistance and reduced word gate resistance using three-level metal lines, resulting in high density MONOS memory arrays with high performance.
2) Description of Prior Art and Background
Twin MONOS structures were introduced in the U.S. Pat. No. 6,255,166, and U.S. patent application Ser. Nos. 09/861,489 and 09/595,059 by Seiki Ogura et al. and also various array fabrication methods of the twin MONOS memory array were introduced in U.S. Pat. Nos. 6,177,318 and 6,248,633 B1 and U.S. patent application Ser. No. 09/994,084 filed on Nov. 21, 2001.
The twin ballistic MONOS memory cell, illustrated in FIG. 1A, may be arranged into a bit diffusion array as follows: each memory cell contains two nitride regions 031 which comprise storage elements for one word gate 040, and half a source diffusion and half a bit diffusion (003). The diffusion junctions are shared by two adjacent storage elements. Control gates can be defined separately (042) or shared together (043) over the same diffusion (003). The control gate is electrically isolated from the underlying diffusion junctions. Diffusions are shared between cells and run in parallel to the sidewall control gates (042), and perpendicular to the word line (041). The diffusion lines become bit lines.
In a conventional MOSFET memory, a transistor structure consisting of one polysilicon gate between source and drain diffusions is used and word gate polysilicon line and diffusion bit lines are orthogonally placed. When the memory array gets large, the bit line (BL) and word gate line (WG) become long. The word line resistance due to the series of word gates is high in large memory devices. In order to reduce word line resistance, it is necessary to connect the word line periodically to a metal line that runs in parallel to the poly word lines. This is referred to as a "stitched" or "strapped" word line. Also the bit diffusion line can be sub-arrayed and the bit line can be "stitched" by a conductive metal line. In a typical memory, each polysilicon word line is stitched to a metal word line which runs on top of each poly word line, and each diffusion line, which runs orthogonally to the word lines is stitched by another layer of metal line.
However, in the high-density twin MONOS cell shown in FIG. 1A, the transistor consists of three gates between source and drain diffusions. Three resistive layers of control gate and word gate and bit diffusion may need to be stitched to reduce resistance and to achieve the target performance. For higher density, the polysilicon control gate lines and diffusion bit lines may run in parallel to and on top of each other. If the cell is metal-pitch limited and requires stitching, that means that two additional layers, of metal lines have to run on top of and contact to the two resistive layers. This is a layout and process challenge, as it is not possible to stitch two resistive layers to two respective metal layers when the set of the composite four lines are running on top of each other within the minimum metal pitch.

Stitch and select implementation in twin MONOS array


A method for screening substances for their ability to reduce malodours from emanations from an animal, said method comprising determining the effect of said substances on the C-S lyase activity of bacteria that emit volatile sulphuric compounds (VSCs), by contacting a test substance with a sample comprising said bacteria or a supernatant obtainable from a culture of said bacteria in the presence of a substrate for a C-S lyase, detecting the levels of thiol production from said bacteria, and comparing the results with those obtained from similar bacteria in the absence of said substance.

In order to ensure good animal welfare in particular amongst domestic pets, it is important to ensure that a positive connection exists between pet and owner. The occurrence of unpleasant odours emanating from the animal, in particular in the form of bad breath or halitosis, but also in connection with highly malodourous faecal matter, can be detrimental to such relationships. In fact, canine oral malodour is considered to be a barrier for pet ownership.
There are a number of products on the market which aim to improve animal oral health. These are primarily designed to be efficacious against plaque or tartar on the tooth surface, or along the gum line. These may, as a consequence, have some impact on bad breath of the animal. However, it would be desirable to have or to develop products which specifically target malodour, in particular oral malodour. Indeed, there is evidence that the compounds responsible for oral malodour can be toxic to tissues and contribute to the pathogenesis of periodontal disease (Milella, 2015 J Vet Dent. 32(2): 99-102). Desirably, such products would be designed to target the root cause of the malodours and not merely provide a masking effect.
Since sensitivity to malodours will be variable from one individual to another, in order to develop such products, it is necessary to provide a scientific basis for determining efficacy which is not subjective in nature, and which is amenable to use in high-throughput screening.
Bacteria found in the oral cavity or in faecal matter of companion animals such as dogs and cats, is known to be different to that found in humans and it has been recognised that cognisance has to be taken of this when developing products to counter periodontal disease of such animals (see Holcombe et al. PLoS ONE, 2014, 9(12) p. e113744).
The leading cause of bad breath or halitosis in humans has been reported as being volatile sulphur compounds (VSCs), produced by oral bacteria, and in particular gram negative bacteria, which thrive predominantly at the dorsum of the tongue. Attempts to counter this have focused on the use of antimicrobial compounds or substances which target these particular bacteria (Greenberg et al., J. Agric. Food Chem. 2007, 55, 9465-9469).
It has been reported that it is also VSCs which give drive the perception of oral malodour in companion animals (Culham 1998 J Vet Dent 15(4): 165-168). Such VSCs may include the products of sulfuric amino acid breakdown, including hydrogen sulphide and the sulphydryl anion as well as methyl mercaptan.
There have been no reported studies to identify the specific types of bacteria that give rise to malodour in the oral cavity of companion animals. Since the bacterial population found in such animals is different to that found in humans, there is no reason to believe that the VSC producing bacteria will be the same as those found in humans. As a result, compounds which may be effective to combat malodour in humans may not be effective for administration to animals.
It is important therefore to develop methods for identifying compounds that may be used to address this problem in an efficient and effective manner.
A screening method for the identification of compounds that inhibit the C-S lyase activity of specifically Staphylococcus species, isolated from human skin has been reported previously (Egert et al., Letter in Applied Microbiology, (2013), 57, 534-539). In that case, a homogenate produced by lysing the bacteria under highly stringent conditions was tested for its ability to produce VSCs. However, this method was specific for a particular bacterial species not found in the mouth of a companion animal. Furthermore, the method was not used in a high throughput screen. For such screens, a consistent and readily available starting material is a pre-requisite and therefore the use of a homogenate, which needs to be produced in a batch process, and may be variable from batch to batch, would not be desirable. Compounds tested were intended for cosmetic use, and therefore may not be acceptable for oral administration.