A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2 (e.g., 32, 64 or 128 bits per word). However, at least one stack cache associated with the CPU (and preferably integrated with the CPU on the same semiconductor circuit or in the same chip set) is a tagged memory where each data word of the stack cache has an associated tag. Whenever the stack cache overflows with data, at least a portion of the contents of the stack cache are stored in a previously established location in main memory so as to make room for storing additional data in the stack cache. In this stack cache swap out operation, the data values and tags in N evaluation stack entries of the evaluation stack cache are copied to the previously established main memory location. The N tags in the N copied evaluation stack entries are stored into a first predefined portion of the previously established main memory location, and the N data values in the N copied evaluation stack entries are stored into a second predefined portion of the previously established main memory location. During a cache fill operation, the N tags and data values of a stack block are copied from their respective main memory positions into the tag and data portions of a stack cache block.

Basic Explanation of Garbage Collection
Garbage collection is a complex topic that has been the subject of hundreds of technical articles and at least one text book. The following is a simplified explanation of dynamic memory allocation and garbage collection. For a more complete explanation of basic garbage collection technology, see U.S. Pat. No. 5,088,036, and Richard Jones and Rafael Lins, "Garbage Collection," John Wiley & Sons Ltd., 1996, both of which are incorporated by reference as background information.
Referring to FIG. 1, there is shown a typical multitasking computer system 100 that has a CPU 102, user interface 106, and memory 108 (including both fast random access memory and slower non-volatile memory). The memory 108 stores an operating system 110 and one or more mutator tasks 112 (also called processes or threads). Each active task in the system is assigned a portion of the computer's memory, including space for storing the application level code 112 executed by the task, space for storing a program stack 114, and a heap 116 that is used for dynamic memory allocation.
The CPU 102 includes an instruction cache 120 for providing instructions to an instruction decoder and execution logic 122. The CPU also includes a stack cache 124 for storing in high speed cache memory a portion of the program stack 114, and a set of registers 126 for storing data values, object references 128 and the like. The program stack 114, including the portion in the stack cache 124, is used to temporarily store various data structures and parameters, including activation records (sometimes called "frames") 130 that are pushed on the program stack each time a method or other procedure is invoked.
During garbage collection, the program stack 114, and the registers 126 in the CPU 102 are typically used to locate a "root set" of object references or pointers used by the mutator task 112. A root set locator procedure in the garbage collector will typically generate and store a root set list 132 of the located root set object references.
It should be understood that FIG. 1 depicts only a simplified representation of a CPU 102 and the items stored in memory. Also, it should be understood that multiple processes may be executing simultaneously in a computer system, each with its own address space that includes the same types of items as shown in the memory 108 of FIG. 1.
For the purposes of this description, the terms "task", "mutator", "mutator thread", "thread" and "process" are used interchangeably. Tasks and programs are sometimes called mutators because they change or "mutate" the contents of the heap 116.
The term "object" is herein defined to mean any data structure created by a program or process.
The terms "reference" and "object reference" are used interchangeably to describe a data structure that includes a pointer to an object. While the term "pointer" or "object pointer" are sometimes used interchangeably with "reference" and "object reference", object references may include information in addition to a pointer. An object reference may be direct or indirect. A direct object reference directly points to an object header, while an indirect object reference points to an object handle. In this document the term "object reference" refers to both types.
The term "stack cache overflow" is defined for the purpose of this document to mean either that the relevant stack cache has become full and the CPU is requesting to write additional entries to it, or that the number of entries in the stack cache equals or exceeds a predefined or programmable "high water mark" (or equivalently, the number of unused entries in the stack cache falls below a predefined or programmable value).
The term "stack cache underflow" is defined for the purpose of this document to mean either that the relevant stack cache has become empty and the CPU is requesting further stack cache entries from it, or that the number of used entries in the stack cache falls below a predefined or programmable "low water mark" (or equivalently, the number of unused entries in the stack cache exceeds a predefined or programmable value).
The term "in-band memory tagging" refers to storing stack cache tags in-band in memory, as a header word preceeding N datum words. The term "out-band memory tagging" refers to storing stack cache tags in a header for N datum words in an alternate location in memory from the location used to store the N datum words.
When the mutator task 112 associated with the heap 116 needs space for storing an array or other program "object", a Memory Allocator routine 140 in the operating system is called. The memory allocator 140 responds by allocating a block of unused memory in the heap 116 to the task. Additional requests for memory will result in the allocation of additional memory blocks. Clearly, if the task continues to ask for more memory, all the space in the heap 116 will eventually be used and the task will fail for lack of memory. Therefore space must be restored by either explicit actions of the program, or some other mechanism.
It is well known that most tasks "abandon" much of the memory space that is allocated to them. Typically, the task stores many program objects in allocated memory blocks, and discards all references to many of those objects after it has finished processing them because it will never need to access those objects again. An object for which there are no references (sometimes called pointers) is often termed an "inaccessible object", and the memory space it occupies is "inaccessible" to the task that once used it.
The solution to this problem is to recover blocks of memory space in the heap 116 that are no longer being used by the task. Garbage collection is the term used to refer to automatic methods of recovering unused memory in the heap 116. The garbage collector generally gathers and recovers unused memory upon the occurrence of a predefined event, such as the expiration of a predefined time period, or usage of a certain amount of the available heap. Thus, FIG. 1 shows that the operation system 110 includes a garbage collector 142.
Thus, the purpose of the garbage collector 142 is to recover unused or abandoned portions of memory in the heap 116 so that the task using the heap will not run out of memory.
While there are a number of different garbage collection methodologies, the easiest one to explain is the Stop and Copy garbage collection technique. In this scheme the heap is divided into two halves, also called semi-spaces, and the program uses only one semi-space at a time. Stop and Copy garbage collectors reclaim unused memory and compact the program accessible memory used by a task by copying all "accessible objects" in the current semi-space to a contiguous block of memory in the other semi-space, and changing all references to the accessible objects so as to point to the new copy of these objects. An accessible object is any object (i.e., block of memory) that is referenced, directly or indirectly, by the "roots" or "root set" of the task. Typically, the "root set" of a task with respect to garbage collection is a set of object references stored in known locations, in the program stack 114 and registers 126 used by the task, which point to objects used by a task. Many of those objects, in turn, will contain references to other objects used by the task. The chain, or directed graph, of object references emanating from the root set indirectly points to all of the accessible objects in the heap.
The entire set of objects referenced by these object references (pointers) is called the set of accessible objects. Inaccessible objects are all objects not referenced by the set of object references derived from the root set.
By copying all accessible objects to a new contiguous block of memory in the heap, and then using the new copy of the objects in place of the old copy, the Stop and Copy garbage collector eliminates all unused memory blocks in the heap. It also "compacts" the memory storage used by the task so that there are no "holes" between accessible objects. Compaction is a desirable property because it puts all of the memory available for allocation to a task in a contiguous block, which eliminates the need to keep track of numerous small blocks of unallocated memory. Compaction also improves virtual memory performance.
Also shown in FIG. 1 are aspects of a computer system that is set up to execute "Java.TM." (a trademark of Sun Microsystems, Inc.) bytecode programs. In particular, the operating system of such a system includes:
a bytecode program verifier 144 for verifying whether or not a specified Java bytecode program satisfies certain predefined integrity criteria; PA1 a class loader 146, which loads object classes into a user's address space and utilizes the bytecode program verifier 144 to verify the integrity of the methods associated with each loaded object class; and PA1 a bytecode program interpreter (not shown) for executing Java bytecode programs. If the instruction decoder and execution logic 122 is designed to execute Java bytecode instructions, a bytecode program interpreter is not needed.
Furthermore, in a computer system set up to execute Java bytecode programs, memory 108 will include at least one class repository 150, for locally storing object classes 152 in use and/or available for use by users of the computer system 100. The heap 116 acts as an object repository for storing objects, which are instances of objects of the object classes stored in the class repository 150.
The present invention is equally applicable to systems using incremental garbage collection, which is a collection of techniques for performing garbage collection in a manner that is interleaved in small increments with mutator functions. Incremental garbage collection is used primarily in systems that require real-time system performance. In most copying versions of incremental garbage collection, every time an existing object is accessed, the existing object is copied from old space to new space unless the object has already been moved to new space during the current collection cycle. There are also non-copying and non-compacting versions of incremental garbage collection. Incremental garbage collection reduces the length of any single system pause caused by garbage collection, but may increase latency in the execution of individual mutator task instructions. The procedure or set of instructions used for performing incremental garbage collection are sometimes called "read barrier" instructions, since they are typically performed in conjunction with object field read instructions. Incremental collection may also be performed using write barrier instructions, which are typically performed in conjunction with object reference write instructions.
The present invention is also equally applicable to: any garbage collection system in which the evaluation stack is part of the root set, and to any tracing garbage collection system.
When a computer system supports multithreading, it is possible for two or more threads of execution to share a single address space. In such systems, each thread of execution is typically considered to be a separate mutator task, and each has its own stack and register set.
In computer systems that use tagged memory to facilitate efficient garbage collection, every word of memory has a corresponding tag that specifies whether or not the value stored in the memory word is an object reference. Of course, in such systems it is necessary that the CPU be able to determine, while it is executing each instruction that changes the contents of any memory location, stack location or register, whether or not the value being written is an object reference. For this reason the instructions used by such computer systems are generally sufficiently data type specific that all instructions, other than instructions which copy values from one memory location to another, that can write an object reference, are only used to write object reference values (i.e., they are data type specific for handling only object reference data).
The identification of object references in the program stack is a tedious time consuming task in non-tagged memory based computers. Further, making a CPU or operating system compatible with non-tagged memory is usually considered to be desirable because virtually all desktop and workstation computers use memory with a standardized word width, such as 32, 64 or 128 bits per word. Also, updating an explicit main memory tag can incur expensive read-modify-write cycle operations, thus reducing available memory bandwidth.
Prior to the present invention there has been an implicit assumption that if tagged main memory was not available, then cache memory inside the CPU should be untagged since it was assumed that there was no point in tagging one without the other. However, given the well known advantages of using tagged memory for garbage collection, the present invention provides a system and method for using tagged stack cache memory inside a computer's CPU while using conventional untagged main memory outside the CPU.
One last point of background information is that the prior art provides a number of examples, other than object reference marking, in which the tagging of memory is useful. It is beyond the scope of this document to explain the details of such systems, because the preferred embodiment of the present invention is specifically addressed at making root set location efficient in object oriented computer systems that use automatic garbage collection for storage management. However, suffice it to say that most aspects of the present invention are applicable to any computer system or operating system that uses conventional, untagged main memory, but where using tagged cache memory in the CPU would be desirable.

System and method for swapping blocks of tagged stack entries between a tagged stack cache and an untagged main memory storage


An exemplary LED package includes a dielectric plate, a heat conductor, a first planar electrode and a second planar electrode, a LED chip, and metal wires. The dielectric plate comprises a receiving groove defined therein. The heat conductor is positioned in the dielectric plate opposite to the receiving groove, and the heat conductor comprises a holding portion exposed on bottom of the receiving groove. The first and second planar electrodes are respectively received in the dielectric plate extending to the receiving groove and are spaced from the heat conductor. The first and second electrodes are respectively electrically connected to the LED chip by the metal wires. The LED chip is mounted on the holding portion of the heat conductor.

1. Technical Field
The disclosure relates to light emitting diode (LED) packages with high heat-dissipation efficiency.
2. Description of Related Art
Light emitting diodes, and specifically the electrical and optical characteristics and lifespan thereof, are easily influenced by temperature. High working temperatures can deteriorate internal quantum efficiency of the LED and shorten the lifespan thereof. Furthermore, resistance of the semiconductor generates a negative temperature coefficient and tends to be reduced with an increase in the working temperature. Such reduced resistance correspondingly results in stronger current at given voltages as well as the generation of excessive heat. If the excessive heat is not effectively dissipated, heat accumulation can lead to deterioration of the LED.
Referring to FIG. 14, a typical light source device 10 includes a shell 11, a light source module 12, and a cover 13. The light source module 12 is received in the shell 11. The cover 13 is located on and protects the light source module 12. The light source module 12 includes a printed circuit board 121, a circuit layer 122, a number of lighting elements 123 (such as light emitting diodes), and an encapsulant 124. The circuit layer 122 and lighting elements 123 are mounted on the printed circuit board 121. The lighting elements 123 are electrically connected to the circuit layer 122. The encapsulant 124 is positioned on the printed circuit board 121 to package the lighting elements 123. While excessive heat from lighting elements 123 is dissipated through the encapsulant 124 and the printed circuit board 121, thermal conductivity thereof is less than optimal, such that the excessive heat is not effectively dissipated.
Therefore, there is room for improvement within the art.

LED package and light source device using same


A computer system includes at least one mother board and a number of control cards monitored by the motherboard via an I2C bus. Each control card has a unique ID. The computer system connects one of the control cards to the I2C bus using a card control device installed in each of the control cards to monitor each of the control cards via the single I2C bus.

1. Technical Field
Embodiments of the present disclosure relate to apparatuses for controlling control cards of computer systems, and particularly to a card control device and a control card of a computer system having the card control device.
2. Description of Related Art
Motherboards of computers often have a plurality of control cards, such as an audio card, a graphics card, and a network card, installed. To control the control cards of the motherboard, a plurality of inter-integrated circuits (I2C) buses are used to connect the control cards to the motherboard. In addition, a CPU of the motherboard reads data of each control card in real-time via the I2C buses to monitor a working state of the control cards, which consumes a lot of CPU resources. Therefore, there is room for improvement in the art.

Card control device and control card of computer system having card control device


A steering assist system provides differential thrusts by two or more marine propulsion devices in order to create a more effective turning moment on a marine vessel. The differential thrusts can be selected as a function of the magnitude of turn commanded by an operator of the marine vessel and, in addition, as a function of the speed of the marine vessel at the time when the turning command is received.

1. Field of the Invention
The present invention generally relates to a steering assist system and, more particularly, to a method for assisting the steering of a marine vessel which has two or more marine propulsion devices.
2. Description of the Related Art
Various techniques have been used in the past to assist the steering of a marine vessel or watercraft through the control of the thrust generated by a marine propulsion device associated with the marine vessel or watercraft. In addition, it is generally known that the manipulation of the trim tabs of a marine vessel can assist is in vessel control and, in certain applications, in the steering system of a marine vessel or watercraft.
U.S. Pat. No. 6,174,210, which issued to Spade et al. on Jan. 16, 2001, describes a watercraft control mechanism comprising a steerable propulsion source, a steering controller for controlling the steerable propulsion source, a linking member connected to the steerable propulsion source, and at least one tab connected to the linking member. The tab is movable between an inoperative position and an operative position whereby the tab can be angled such that, in the operative position and when the watercraft is traveling upright in water in a substantially forward direction, a volume of water impinges on a top surface of the tab, thereby creating a downward and rearward force on the watercraft.
U.S. Pat. No. 6,405,669, which issued to Rheault et al. on Jun. 18, 2002, describes a watercraft with steer response engine speed controller. The control system provides thrust for steering control in a watercraft that is powered by a propulsion unit. The steering control system is applicable to various types of watercraft, including boats and personal watercraft, that are powered by inboard jet propulsion systems or outboard engines. The system is activated by the steering helm assembly and/or an electronic control mechanism.
U.S. Pat. No. 6,428,371, which issued to Michel et al. on Aug. 6, 2002, describes a watercraft with steer responsive engine speed controller. The controller generates thrust when the steerable propulsion unit is turned beyond a predetermined angular threshold. Turning the steering wheel beyond the threshold causes the speed controller to increase engine speed so that the propulsion unit produces thrust at least equal to the minimal propulsive force needed to effectively steer the watercraft.
U.S. Pat. No. 6,524,146, which issued to Spade et al. on Feb. 25, 2003, describes a watercraft having auxiliary steering. A control mechanism for a watercraft includes a selectively movable flap connected to an actuator, which moves the flap into and out of the flow of water to affect steering, deceleration and trimming. The flap is recessed with respect to the lower surface of the hull so that it does not create drag at high speeds. The flap may be a portion of the ride plate, may be disposed in a recess in the bottom of the hull, or may be disposed on the stern above the bottom of the hull.
U.S. Pat. No. 6,561,860, which issued to Colyvas on May 13, 2003, describes a maneuvering enhancer for twin outboard motor boats. An adjustable length bar is used to replace a rigid bar, the one connecting the two outboards or the two outdrives of a boat, for steering purposes, said adjustable bar being electrically operated through a switch on the boat's dashboard, said switch having two operating positions, one to keep propellers creating two parallel thrusts, and a second to shift the propellers to create a vee configuration, by which the boat's maneuverability will be enhanced.
U.S. Pat. No. 6,997,763, which issued to Kaji on Feb. 14, 2006, describes a running control device. A running control device for a watercraft controls propulsion force and tilt angle of a propulsion device relative to the hull of the watercraft. The running control device also sets an optimum trim angle automatically. The running control device includes a propulsion force control section that controls the propulsion force of the propulsion device. The running control device also includes a tilt angle control section that controls the tilt angle of the propulsion device. A target propulsion force calculation module responds to first input information to calculate a target propulsion force. An amount-of-operation calculation module responds to second input information to calculate an amount of operation of the propulsion device to produce the target propulsion force. The tilt angle control section includes a tilt angle calculation module that determines the tilt angle based on the propulsion force.
The patents described above are hereby expressly incorporated by reference in the description of the present invention.

Method for assisting a steering system with the use of differential thrusts


In order to provide an inverter apparatus and a solar power generation apparatus in which when a main AC power system (5) has suffered, e.g., a power failure, the operation mode of an inverter (2) in the tie operation with the main AC power system (5) can be easily and safely switched from the tie operation mode to the self-support operation mode, and electric power can be supplied to a load (4) directly using normal indoor wiring, the open/closed state of a switch (3) for opening/closing a connection between the output terminal of the inverter (2) and the main AC power system (5) is detected, and the self-support operation of the inverter (2) is started when the open state of the switch (3) is detected.

1. Field of the Invention
The present invention relates to an inverter apparatus for converting DC electric power into AC electric power, and a solar power generation apparatus using such inverter apparatus and, more particularly, to an inverter apparatus which has two modes, i.e., a tie operation mode with a main AC power system such as a commercial AC power system, and a self-support operation mode set upon power failure of the main AC power system, and a solar power generation apparatus.
2. Description of the Related Art
Solar power generation apparatuses are reconsidered as emergency power supplies in cases of disasters such as earthquakes. Such solar power generation apparatus comprises an inverter for converting DC electric power supplied from a solar cell into AC electric power and supplying it to consumer loads, and a switch for connecting the output from the inverter to a main AC power system such as a commercial AC power system or the like. When electric power supplied from the solar cell is insufficient for customer consumption power, the short electric power is received from the main AC power system; when electric power supplied from the solar cell exceeds customer consumption power, excess electric power is supplied to the main AC power system.
A control system of such inverter monitors the voltage waveform of the main AC power system, and ON/OFF-drives the individual switching elements of the inverter to obtain a voltage waveform corresponding to the instantaneous value and polarity of the voltage. In this inverter, when the main AC power system is cut off owing to a disaster, trouble, maintenance, or the like, a protection circuit immediately works to turn off the individual switching elements. Even when a breaker is used as the switch, the protection circuit works before the breaker opens. As a result, when the main AC power system has suffered a power failure or outage, the solar power generation apparatus itself fails to operate.
Therefore, in order to use the solar power generation apparatus using the inverter as an emergency power supply in disasters, the inverter must have a self-support operation function. For example, solar power generation apparatuses shown in FIGS. 6 and 7 are available. In FIGS. 6 and 7, reference numeral 1 denotes a solar panel built by a solar cell array; 2, an inverter; 3, a switch; 4, a consumer load; and 5, a main AC power system. Also, reference numeral 21 denotes a controller for the inverter 2; 22, an AC output switch; 23, an outlet for a self-support operation; and 24, a cord for connecting the outlet 23 and the consumer load 4.
In the system shown in FIG. 6, when the main AC power system 5 has suffered a power failure or outage, since the switch 3 is not always opened, as described above, if the self-support operation of the inverter 2 is inadvertently started, electric power is supplied to the main AC power system 5, and the inverter 2 may stop owing to an overload. Or the inverter 2 may cause an electric shock accident in the main AC power system 5. In order to solve these problems, the switch 3 must be manually opened, and thereafter, the self-support operation of the inverter 2 must be manually started.
In the system shown in FIG. 7, since the self-support operation outlet 23 alone of the inverter 2 can be used during the self-support operation, the load 4 to which electric power need be supplied must be brought to a position in the vicinity of the inverter 2 or electric power must be supplied to the load 4 via the cord 24.

Inverter apparatus and solar power generation apparatus


A method and apparatus for forming a length of tubing into a curved, unbalanced and non-uniform shape continuously bends the tubing and then changes the cross-sectional shape along the length of the tubing to eliminate springback and provide a stable part with shape retention The apparatus includes relatively movable upper and lower half die shoes A form post, a forming steel subassembly, a plurality of slides and driver posts are positioned on the shoes in juxtaposed relationship. A clamp holds a length of tubing against the form post. Movement of the die shoes towards each other shifts the slides to continuously bend the tube about the form post. After the bending operation, the cross-sectional shape of the tubing is changed from a generally circular shape towards an oval or generally rectangular shape. A pressure is applied to induce stresses which eliminate springback and provide a stable part.

The present invention relates to a method and apparatus for creating complex, unbalanced and non-uniform shaped structures.
A wide variety of products in the office furniture industry are presently manufactured which can be described as having complex, unbalanced and non-uniform shapes. Chairs, tables and the like employ parts with shapes dictated, in part, by structural as well as aesthetic and ornamental considerations incorporated into the article by the designer. Chair arms, for example, must have sufficient strength to provide adequate arm support. The arms also perform an ornamental function and, hence, may have a complex, non-uniform shape.
Heretofore, complexly configured structures have been manufactured using a variety of techniques. The parts may be cast from metal or molded from engineering plastics. Casting techniques suffer from inherent problems related to cost, material waste, labor and quality control. Porosity and material shrinkage, for example, may result in shape changes, surface defects and the like. Generally, complexly configured cast articles must have additional machining operations performed on them so that the desired shape and tolerances are obtained.
In many instances, configured structural parts such as automotive framing and chair components may be formed by welding together sheet metal stamped parts. The resulting structures have a closed, looped configuration in cross-section and provide the needed strength without many of the disadvantages of casting processes. Welding of the stamped parts can, however, cause heat warpage and shape changes. Weld splatter can have an adverse effect on surface finish. In addition, blanking and trimming operations associated with stamped parts result in significant process scrap.
The use of tubing having a closed loop cross-section which may be circular, oval or rectangular to form structural parts has been proposed. Tubing can be bent, flared, swedged, drawn and sized and, hence, formed into a wide variety of shaped parts. The specific shapes and areas where tubing could be used have been inherently limited, however, by known manufacturing processes. Formation of tubing into various shapes through bending operations may be limited by shape changes caused by uncontrolled weld seam location, heat distortion caused during welding operations and material springback. Springback, that is, the elastic recovery of the material from which the part is made, causes the shaped part to move back toward an original prebent configuration.
Various processes have been proposed to form parts or to bend tubing to compensate for such springback and material deformation. An example of one such method and apparatus may be found in U.S. Pat. No. 3,821,525 entitled METHOD AND APPARATUS FOR AUTOMATICALLY COMPENSATED TUBE BENDING and which issued on Jun. 28, 1974, to Eaton et al. As set forth therein, in order to bend a tube to a desired bend angle, it was necessary to "overbend" the tube initially so that, when released, it would spring back to the desired bend angle. Springback makes maintenance of required tolerances and the part configuration extremely difficult. Normal tube bending processes required incremental steps or stages and required the tube or bending tools to be moved during the forming process. Portions of the tube between bend points tended to return to original straight conditions. In order to compensate for springback, a machine is disclosed in the aforementioned patent which includes a carriage assembly having a rotating collet chuck for selectively gripping the end of a length of tubing. The tube is longitudinally moved with respect to a bend die. The tube is moved to the desired position by the carriage and a clamp die and bent. A wiper die and pressure die grip a portion of the tube behind the bend to provide controlled elongation of the tube around the bend. An automatic controller or computer and sensors indicate the position of the bend die, carriage and collet chuck. The controller generates operating commands and receives inputs from conventional sources. The system attempts to predetermine the proper degree of overbend and fixed and radial compensation to provide a tube having a desired shape.
An example of another method and apparatus is disclosed in U.S. Pat. No. 4,854,150 entitled METHOD OF BENDING AND FORMING HEATED TUBULAR WORKPIECES and issued on Aug. 8, 1989 to Brown et al. The method and apparatus disclosed therein forms a tube into a desired shape through controlled heating, forging and bending followed by quenching. The process results in a permanent form. A tubular bar or workpiece is heated and held against a forming anvil by clamping structure. The heated tubular bar is bent by a plurality of forming rollers around the anvils. An hydraulic system and a plurality of actuators control the positioning of the forming rollers. Heating and quenching steps are used for configuration stability.
A need exists for a method and apparatus which is capable of forming or creating complex, unbalanced and non-uniform shaped structures from tubing in an efficient, cost effective manner and which results in stable parts having complete shape retention, acceptable tolerances and no memory or springback.

Method for forming tubing into curved, unbalanced and non-uniform shapes


The invention provides a human human adipophilin-like protein (HALP) and polynucleotides which identify and encode HALP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for treating disorders associated with expression of HALP.

Lipids comprise a class of hydrophobic macromolecules that include fatty acids and cholesterol. These ubiquitous molecules function as a major source of cellular energy and constitute a primary component of cell membranes. In addition, lipids function in many signaling pathways as components of hormones and other intracellular messengers. Animal cells store fatty acids in the form of triacylglycerols, which consist of three chains held in ester linkage with one molecule of glycerol. Triacylglycerols, along with cholesterol, are transported through the bloodstream in the form of lipoprotein emulsions. These emulsions contain a variety of apolipoproteins which associate with and permit lipids to be transported in an aqueous environment. Adipocytes store excess triacylglycerol in the cytoplasm as large lipid globules which may occupy up to ninety-five percent of the cell volume.
Adipocyte differentiation has been studied using a variety of cultured adipogenic cell lines that terminally differentiate into adipocytes upon reaching confluence or stimulation with an appropriate agent. These studies have led to the discovery of a 50-kDa membrane-associated protein, adipose differentiation-related protein (ADRP), that serves as an early marker for preadipocyte differentiation (Jiang, H. P. and Serrero, G. (1992) Proc. Natl. Acad. Sci. 89: 7856-7860). ADRP has also been found in milk-secreting cells where it is associated with the surface of fat droplets. A human homolog of ADRP, adipophilin, has been reported, and its protein sequence is highly conserved in mouse, rat, and cow (Heid, H. W. et al. (1996) Biochem. J. 320: 1025-1030). Thus, ADRP is suggested to be associated with fat globule formation in different cell types.
ADRP expression correlates strongly with differentiation of preadipocytes in culture and the formation of fat globules. In stimulated preadipocytes, ADRP expression begins one day earlier than other known markers of adipocyte differentiation, e.g., fatty-acid binding protein and lipoprotein lipase. ADRP mRNA expression increases 100-fold within a day after induction, and continues to increase during adipocyte differentiation. ADRP expression is stimulated by addition of accelerators of differentiation, e.g., dexamethasone, to adipogenic cells. Conversely, ADRP expression is inhibited by addition of inhibitors of differentiation, e.g., transforming growth factor beta and tumor necrosis factor (Jiang, H. P. et al. (1992) Cell Growth Differ. 3: 21-30). ADRP expression can also be induced in rat liver tissue by treatment with etomoxir, an irreversible inhibitor of carnitine palmitoyltransferase I; induced ADRP expression levels correlate with accumulation of lipid droplets in the liver (Steiner, S. et al. (1996) Biochem. Biophys. Res. Commun. 218:777-782).
The subcellular localization of ADRP in both adipocytes and milk secreting cells indicates that although ADRP lacks a predicted signal sequence or transmembrane domain, it nevertheless appears to be associated with lipid droplets in both cell types. (Jiang and Serrero, supra; Heid et al., supra). In milk secreting cells, ADRP was identified as a major constituent of milk-lipid-globule-membrane (MLGM). Another major component of MLGM, butyrophilin, binds tightly to ADRP (Heid et al., supra).
ADRP and its human homolog, adipophilin, share significant sequence homology with perilipin, a hormonally-regulated phosphoprotein that surrounds lipid storage droplets in adipocytes where it is the predominant cAMP-dependent protein kinase substrate. In differentiating preadipocytes, perilipin expression appears at the onset of triacylglycerol accumulation and transcript level increases in parallel with lipid accumulation. (Greenberg A. S. et al. (1991) Clin. Res. 39: 287A). Thus, the related proteins adipophilin, ADRP, and perilipin appear to be members of a distinct set of proteins that associate with lipid globules and function in lipid metabolism (Greenberg A. S. et al. (1993) Proc. Natl. Acad. Sci. 90: 12035-12039).
Many human diseases such as atherosclerosis, hyperlipidemia, obesity, and diabetes have been related either directly or indirectly to abnormalities in lipid metabolism. In addition, a neurodegenerative disorder, Alzheimer's disease, has been related to abnormal lipid metabolism via its genetic linkage with apolipoprotein E (apoE). Apo(E) is a component of very low density lipoproteins that plays a role in neuronal repair and remodeling (Weisgraber, K. H. and Mahley, R. W. (1996) FASEB J. 10: 1485-1494).
The discovery of a new human adipophilin-like protein and the polynucleotides encoding it satisfies a need in the art by providing new compositions which are useful in the diagnosis, prevention and treatment of disorders of lipid metabolism, neurodegenerative disorders, and cancer.

Polynucleotides encoding a human adipophilin protein homolog


A method of fabricating a test probe includes a first conductive providing operation in which a first conductive member formed of a conductive metal material is provided, the first conductive member including a probe portion that has a probe shape and is formed in an upper portion of the first conductive member by a micro-electromechanical systems (MEMS) process, a second conductive member providing operation in which a second conductive member formed of a conductive metal material is provided, the second conductive member having an insertion portion formed in an upper portion of the second conductive member for inserting the first conductive member to be coupled to the insertion portion, an insertion operation in which the first conductive member is inserted into the insertion portion of the second conductive member, and a fixing and coupling operation in which the first conducive member is fixedly coupled to the second conductive member by deforming a part of the second conductive member.

In general, to test electrical properties of a semiconductor device, a stable electrical connection between the semiconductor device and test equipment (not shown) is essential. A test socket is typically used to connect between a semiconductor and test equipment.
The test socket enables bidirectional exchange of electric signals between a terminal of a semiconductor device that is a device to be tested and a pad of the test equipment. To this end, a test probe such as a pogo pin is used as a contact device in the test socket. The pogo pin with a spring inside may facilitate connection between the semi-conductor device and the test equipment and buffer mechanical shocks generated when the semiconductor device and the test equipment are connected to each other. Accordingly, the pogo pin has been widely used for most test sockets.
FIG. 1 is a cross-sectional view of a test probe used for a test socket, according to a related art. Referring to FIG. 1, a test probe according to a related art includes a barrel 20, an upper pin member 10 having a test probe portion 12 and capable of slidably moving in the barrel 20, a lower pin member 40 formed in a lower end portion of the barrel 20. A compression coil spring 30 is accommodated in the barrel 20 so as to elastically support the upper pin member 10.
When a device to be tested (not shown), such as a microchip, is tested in the above structure, a microchip is placed on top of a test socket and a pressing device (not shown) presses downwardly the microchip so that the microchip contacts a tip of the test probe portion 12 of the upper pin member 10.

Test probe for test and fabrication method thereof


A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command.

Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible storage values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal storage value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in "Introduction to Flash Memory," Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in "Multilevel Flash Cells and their Trade-Offs," Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in "Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?" Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in "A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate", Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in "Future Memory Technology including Emerging New Memories," Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Analog memory cells are commonly read by comparing their storage values to one or more read thresholds. Some known methods and systems read analog memory cells using multiple read thresholds. For example, PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method for operating a memory device. The method includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells of the memory device. Second analog values are then read from the respective memory cells. A distortion present in the second analog values is estimated, and error correction metrics are computed responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data. In some embodiments, the error correction metrics are computed by combining multiple instances of the second storage values, which are obtained by using respective different sets of read thresholds.
PCT International Publication WO 2008/053472, whose disclosure is incorporated herein by reference, describes a method for operating a memory. The method includes storing data, which is encoded with an ECC, in analog memory cells of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values.
The two PCT Publications cited above are assigned to the assignee of the present patent application and were published after the priority date of the present patent application.

Reading analog memory cells using built-in multi-threshold commands


A snapping fabrics comprising of: a micro-fibriform loop fabric, fabricated by complex, spun micro-fiber and splinted thereafter to recover smaller fiber, all of the fibers forming the micro-fibriform loops between the inter-weaving or inter-knitting nodes; a fibriform hook fabric, fabricated by blended spun yarn or synthetic fiber and having a hairiness treatment applied thereafter to form the fibriform hooks for hooking said micro-fibriform loops of said micro-fibriform loop fabrics respectively.

1. Field of the Invention
The present invention is relating to snapping fabrics, especially to a fabric combination having the similar snapping effect of traditional VELCRO.
2. The Relating Prior Art
VELCRO, a leading brand of hook and loop fabric, as a conventional snapping or gripping fabrics can be found in our living environment and widely used in garment, leather goods, shoes, diaper, helmet, etc. The major reason is that the VELCRO is convenient in snapping.
However, there are some unsatisfied drawbacks in using VELCRO, for example, VELCRO is stiff in texture, has a certain thickness and is difficult to produced directly connected to the fabric. Normally, it should be by sewing or other ways to attach or connect the VELCRO on the articles which using said VELCRO. Therefore, if the articles using VELCRO requires to be soft in texture or less thick than the thickness of VELCRO, due to the texture of VELCRO material, the VELCRO is difficult to meet such requirements.
Taiwan Utility Model Publication No. 479,477 is relating to thin base fabrics having a snapping surface knitted by a single filament. It disclosed a snapping fabric with a base fabric which formed by each weft filament being knitted to become a node then each adjacent nodes being interlocked to form a pair of inlay, then, by interlocking continuous nodes to form the strips of combining the base warp tissues. That means, the base fabrics of said snapping fabrics is made by single filament, under special knitting for to the curving floating circles thereby providing a thinner VELCRO. The fact prevents the trouble caused by the thickness of VELCRO.
Beside the above-mentioned thickness issue, there is still a problem of unintended adherence. The reason is that the loops of convention snapping fabrics are too large in dimension which providing the opportunity of small things to insert through or fall within the loops.


A method of and an apparatus for molding resin to seal electronic parts are adapted to use molding units to seal with molded resin materials electronic parts that are mounted on lead frames. Additional molding units are detachably mounted with respect to an already provided first molding unit in the molding apparatus, so that the number of the molding units can be arbitrarily adjusted. In this manner, the method and apparatus can be easily reconfigured or rearranged to be adapted to mass production or small production runs of the same or different types of molded parts. By simultaneously carrying out various process steps, the overall process time is reduced.

1. Field of the Invention
The present invention relates to a method of and an apparatus for molding resin to seal electronic parts, such as ICs, LSIs, diodes or capacitors which are mounted on lead frames with a resin material.
2. Description of the Background Art
In general, electronic parts are sealed with molded resin by transfer molding, through a resin molding/sealing apparatus having the following basic structure and operation.
Such a resin molding/sealing apparatus comprises a mold having fixed and movable mold sections which are opposed to each other, resin material supply pots arranged in the mold, plungers mounted on the pots for pressurizing resin, cavities provided in mold surfaces of the fixed and movable mold sections respectively to face each other, and resin passages provided between the pots and the cavities.
Resin tablets are supplied in the pots while electronic parts mounted on lead frames are supplied and set in prescribed positions of the cavities, and the mold is closed. The resin tablets provided in the pots are heated and pressurized so that the resin materials melted in the pots are injected and charged into the cavities provided on side positions of the pots through the resin passages respectively. Thus, the resin is molded to seal the electronic parts engaged in the cavities respectively.
When a mold for mass production is employed for the aforementioned apparatus, this leads to the following problems. For example, the mold for mass production is inevitably increased in weight and size, and is hard to handle while it is difficult to maintain the mold in uniform working accuracy. Thus, portions of the mold differ from each other in resin molding conditions. Particularly in manufacturing products such as electronic parts that are to be sealed with molded resin with requirements for high quality and high reliability, the cavities may be partially charged with no resin, or voids or defective parts may be formed in the interior and the exterior of the sealed compacts due to such difference in resin molding/sealing conditions, to extremely reduce the quality of the products. In order to maintain the mold in uniform accuracy, further, the mold and the apparatus are increased in cost.
Further, resin flashes adhere to the mold surfaces in such a large quantity that the overall molding time is increased since it takes time to remove the resin flashes, leading to extreme reduction of productivity.
In addition, a mold for mass production that is to be mounted on the aforementioned conventional apparatus is inevitably restricted in size and production quantity since it is necessary to also take the size of a mold closing mechanism or the like into consideration in this case.
The mold provided in the aforementioned conventional apparatus is generally adapted to simultaneously mold the same type of compacts. In order to mold different types of compacts, therefore, it is necessary to exchange the mold which is mounted on the molding apparatus itself. In order to simultaneously mold different types of compacts by the same molding apparatus, further, it is necessary to change the layout of the mold itself or to simultaneously mount different types of molds on the apparatus.
When the mold which is mounted on the molding apparatus itself is frequently changed for molding different types of compacts, however, the mold exchange operation is troublesome and reduces productivity. When the layout of the mold which is mounted on the molding apparatus itself is changed to be capable of simultaneously molding different types of compacts, the design of the mold is complicated and the usage of the mold is restricted to the layout, leading to inferiority in general and increased cost for the mold and the molding apparatus.
When a plurality of molds of different types are simultaneously mounted on the molding apparatus, the molds themselves must be miniaturized due to restriction of spaces for receiving the same, leading to complicated design of the molds and reduction in productivity. If a plurality of molding apparatuses are employed independently of each other in correspondence to the number of different types of compacts for solving this problem, for example, the cost for the production equipment is disadvantageously increased.
In a conventional method of molding resin to seal electronic parts, on the other hand, a step of supplying unsealed lead frames into prescribed positions of cavities provided in a mold, a step of supplying resin tablets into pots provided in the mold, a step of taking out the sealed lead frames from the mold to the exterior thereof, and a step of cleaning mold surfaces of the mold after resin molding/sealing are generally successively carried out independently of each other.
In such a conventional method of molding resin to seal electronic parts, therefore, the overall molding time is so increased that productivity is extremely reduced.

Apparatus for molding resin to seal electronic parts


Embodiments of the present invention provide differential pair amplifier circuits including cross-coupled cascode transistors. Other embodiments may be described and claimed.

High performance trans impedance amplifier (TIA) circuits are important building blocks for high speed data communication, such as optical chip-to-chip links at data rates beyond 20 gigabits per second (Gb/s). In order to achieve the best possible gain/bandwidth performance in complementary metal oxide semiconductor (CMOS) receivers for chip-to-chip optical interconnects, inductive peaking is generally used to extend the bandwidth and resonate out parasitic capacitance. Additional gain is often obtained by introducing larger input devices or larger resistive loads, which may reduce bandwidth. Alternatively, additional gain stages may be introduced, which consume additional power. Furthermore, as CMOS scales further into the nanometer gate length range, the transconductance and drain resistance may be reduced, which may lead to a decrease in gain.

Amplifier circuit with cross-coupled cascode transistors


A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping >10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

FIELD OF THE INVENTION
The invention relates to a capacitor in a semiconductor configuration, in particular a DRAM configuration, having an electrode structure which contains a plurality of spaced-apart elements that are electrically connected to one another by a connecting structure, a capacitor dielectric, and a counterelectrode. The invention also relates to a process for producing a capacitor in a semiconductor configuration.
A multiplicity of integrated circuits require capacitors. Examples, besides the typical one of a dynamic memory cell, are analog/digital or digital/analog converters and filter circuits. Provisions are needed for reducing the intrinsically great amount of space that a capacitor requires, particularly with the miniaturization of structures involved in the increased scale of integration or since chip area has to be economized upon. A typical example may be considered to be the dynamic semiconductor memory, in which the required area of the usually used single-transistor memory cell is reduced from one memory generation to another with increasing memory density. At the same time, the minimum capacitance of the memory capacitor must be preserved.
In dynamic semiconductor configurations, a single-transistor memory cell includes a readout transistor and a capacitor. By triggering the readout transistor through a word line, the information, that is the electric charge, stored in the capacitor can be read out through a bit line. The memory capacitor must have a minimum capacitance in order to provide reliable storage of the charge and simultaneous capability of distinguishing the read-out information. The lower limit for the capacitance of the memory capacitor is currently considered to be 20 fF. In order to attain that capacitor capacitance, the thickness of the dielectric must be as small as possible and the area of the capacitor as large as possible.
While up to the 1 Mbit memory generation, it has been possible to realize both the readout transistor and the capacitor in the form of planar components, from the 4 Mbit memory generation on configurations are known in which the capacitor is disposed in a trench (trench capacitor). The electrodes of the capacitor are disposed along the surface of the trench. Overall, that yields an effective surface area of the capacitor which is increased as compared with a planar configuration on the surface of the substrate.
A further option for increasing the capacitance with an unchanged changed or reduced space requirement for the capacitor is to construct the capacitor as a stacked capacitor. Through the word lines, a polysilicon structure, for instance a crown structure or a cylinder, is formed that is contacted with the substrate. The polysilicon structure forms a memory node that is provided with the capacitor dielectric and the capacitor plate or so-called cell plate. That concept has the advantage of being compatible with a logic process.
The free space above the substrate surface is used for the capacitor. The entire cell surface can be covered with the polysilicon structure, as long as the structures of adjacent memory cells are isolated from one another. Known configurations along those lines are the fin stacked capacitor and the crown stacked capacitor.
A semiconductor memory configuration with a stacked capacitor as the memory capacitor is known from Published European Patent Application 0 415 530 A1. The stacked capacitor includes a polysilicon structure with a plurality of polysilicon layers, stacked substantially parallel to each other and joined together through at least one lateral support. The lateral support is produced with the aid of a polysilicon layer that is subsequently etched back, so that a substantially upright land remains that joins the polysilicon layers which are stacked one above the other. The structure is formed by alternatingly depositing polysilicon layers and silicon oxide layers, which are etchable selectively to them, on the surface of the substrate, by structuring those layers, by producing the lateral supports on at least one side of the structure, and by selective etching out of the silicon oxide layers. The polysilicon structures are arsenic-doped. Next, silicon oxide is formed by thermal oxidation as the capacitor dielectric, over which the cell plate of doped polysilicon is deposited. In a capacitor with stacked electrode layers which is known from U.S. Pat. No. 5,240,871, variously rapidly etching isolation layers are applied over a polysilicon layer. The isolation layers are then structured and etched, producing a support framework. Subsequently, doped polysilicon is deposited and then a silicon nitride layer, followed by the formation of the cell plate.

Capacitor in a semiconductor configuration and process for its production


A system and method are disclosed for improving hard drive actuator lead attachment. In one embodiment, an actuator board is coupled to an actuator flexible cable by a bonding agent, such as an anisotropic conductive film (ACF). In one embodiment, an actuator flexible cable is coupled to one or more actuator coil leads, such as by solder bump bonding, and the flexible cable/actuator coil coupling is embedded in an actuator frame, such as by polymer injection molding.

The present invention relates to hard disk drives. More specifically, the invention relates to a system and method for improving the electrical connection of a hard drive actuator coil lead.
FIG. 1 provides an illustration of a typical hard disk drive. Hard disk drive storage devices typically include a rotating disk 10 mounted for rotation by a spindle motor. The slider 1 is attached via a flexure to a load beam 2 supported by an actuator arm 3. The slider 1 'flies' over the surface of the magnetic disk 10 at a high velocity reading data from and writing data to concentric data tracks on the disk 10. The head/slider 1 is positioned radially by an actuator 20, comprising an actuator coil 13 housed in an actuator frame 8.
In typical hard disk drives, electrical control signals are communicated to the voice coil motor (actuator 20) by a head stack assembly (HSA) flexible circuit 9. Typically, the HSA flexible circuit 9 also communicates read/write data to the head(s) 1. The flexible circuit 9 attaches to the actuator coil 13 via an actuator board 7, containing a preamplifier chip 11 (mounted to the actuator arm 3).
FIG. 2 provides a more detailed view of a hard disk drive arm as is typical in the art. The actuator board 7 is usually electrically coupled to the actuator coil 13 by one or more actuator coil leads 18 attached typically by soldering or ultrasonic bonding 20. It can be difficult to get a good solder bond on non-rigid surfaces, such as on a polymer substrate, and thus, solderless bonding techniques, such as in U.S. Pat. No. 4,970,365 and U.S. Pat. No. 5,298,715, have been suggested. Further, removing adhesive or solder flux contamination presents a problem (as described below) necessitating solderless bonding techniques.
FIG. 3 illustrates a typical technique of solderless lead bonding as provided by U.S. Pat. No. 4,970,365. A laser/ultrasonic-assisted thermal compression technique is utilized where laser (or ultrasonic) energy is used for attaching fine pitch components to non-rigid substrates. Typically, the laser/ultrasonic energy is used to pulse heat a fine-point capillary tip 22, placed in forced intimate contact with a lead 16 and pad 14.
There are disadvantages associated with the above method of bonding. For example, such methods provide poor bonding strength, and thus, the reliability and durability of such bonds are lacking. A bond defect can cause degraded performance or failure of the head stack assembly. The nature of this type of bonding prevents rework or salvage of the bonded components. Further, laser/ultrasonic-assisted thermal compression techniques require costly, high precision equipment. Also, cleaning flux, which is necessary for effective soldering is difficult and costly. Further, solder, which consists primarily of tin, can cause component contamination. During soldering, such as soldering coil leads 18 to the connection pads on an actuator board 7 (See FIG. 2), tin may splash out causing damage to surrounding electrical components and/or disk media.
It is therefore desirable to have a system and method for improving the electrical connection of the hard drive actuator coil that avoids the above-mentioned problems, as well as having additional benefits.

System and method for improving hard drive actuator lead attachment


A pressurized water reactor plant includes a reactor vessel (1), a reactor coolant pump (5) having an inlet connected by coolant pipe (2) to an outlet of the reactor vessel, a steam generator (10) having an inlet connected by a high-temperature side pipe (4) to the outlet of the pump (5) and an outlet connected by low-temperature side pipe (6) to an inlet of the reactor vessel. The steam generator has a horizontally extending shell (11) in the interior of which are horizontal U-shaped tube bundles (30) supported on tube support plates (20) and a pair of separator plates (18) which divide the interior of the shell into downcomer space (19). A partition plate (21) divides the interior of the shell into a U-shaped tube region (16) and a straight tube region (17). A moisture separator (27) is disposed above the heat transfer tubes (15) and a drain pipe (28) extends therefrom for draining impurities from the moisture separator to the U-shaped tube region (16) to which blowdown pipe (26) is connected.

The present invention relates to a pressurized water reactor plant and, more particularly, the arrangement of various components constituting a primary reactor cooling system therefore.
FIG. 9 shows a typical arrangement of components, such as a reactor vessel and steam generator, constituting a primary cooling system of a conventional pressurized water reactor plant. A high-temperature side pipe 2 of the primary cooling system, which pipe is connected to the outlet nozzle 1a of a reactor vessel 1, communicates with the high-temperature side water chamber 3a of a vertical type steam generator 3. A substantially U-shaped pipe 4, referred to as crossover leg hereinafter, communicating with the low-temperature side water chamber 3b of the steam generator 3 is connected to the suction port 5a of a reactor coolant pump 5. The discharge port 5b of the pump is connected to a low-temperature side pipe (not shown) communicating with the inlet nozzle 1b of the reactor vessel 1.
In such a design that the installations or components are connected as described above, the bottom of the U-shaped pipe (crossover leg) lies below the upper portion of a nuclear core 7 in the reactor vessel 1 as seen from FIG. 9.
The applicant previously proposed a pressurized water reactor plant employing a horizontal type steam generator instead of the vertical type steam generator so that the steam generator can be used not only for generating steam in normal operation but also as a heat exchanger for removing decay heat in a core during a loss of coolant accident (Japanese Patent Application No. 401077/1990, European Patent Application No. 90117428.4)
As seen from FIG. 10, the pressurized water reactor plant disclosed in Japanese Patent Application No. 401077/1990 comprises a condensate tank T1 which is disposed above a secondary cooling system and communicates with the second cooling system via a pipe having a valve, a pressure reducing valve V1 connected to the secondary cooling system, and a gravity flow tank T2 which is partially disposed above a low-temperature side pipe P1 and a high-temperature side pipe P2 of the primary cooling system. Further, the gravity flow tank T2 communicates with a reactor vessel 1 via the pipe P3 provided with a valve V2. Steam generators 3' are installed extending horizontally and have a vent pipe P4 connected to the high-temperature side water chamber. The gravity flow tank T2 has a water capacity sufficient to submerge at least the high-temperature side and low-temperature side pipes P2 and P1 under discharged water when the valve V2, which is disposed in the pipe P3 connected to the gravity flow tank T2, is opened.
In the pressurized water reactor plant mentioned above during a normal reactor operation, the primary coolant which enters the reactor vessel 1 through the low-temperature side pipe P1 connected to the inlet nozzle of the reactor vessel 1 is heated in the nuclear core 7, and flows out of the outlet nozzle of the reactor vessel 1. Then, the primary coolant thus heated passes through the high-temperature side pipe P2, and reaches the low-temperature side water chamber after flowing through the high-temperature side water chamber of the steam generator 3' and the inside of U-shaped heat transfer tubes. Thereafter the primary coolant is pumped by a coolant pump 5, into the reactor vessel 1 again.
While, in the arrangement of the pressurized water reactor plant described above, the natural circulation flow of the reactor coolant through the heat transfer tubes is not prevented (or is sustained), as described in the specification of the above patent application, during a reduced pressure condition in the primary cooling system, which follows from an accident of coolant loss, such that major postulated design basis accident such as core melting by decay heat can be prevented, because the steam generator 3' is installed laterally extending and the high-temperature side water chamber therein is provided with a pipe P4 having a valve. In order to remove the decay heat through heat exchange with a secondary coolant or feedwater in the steam generator 3' by using gravity circulation, the pressure in the secondary cooling line is decreased by operating the pressure reducing valve V1 connected to the secondary cooling system, and the water in the condensate tank T1 is poured into the secondary cooling system under head difference by opening the valve of condensate tank T1 disposed above the secondary cooling systems. Thus the water poured into the secondary cooling system is heat exchanged with the primary coolant flowing through the heat transfer pipe under natural circulation thereby removing the decay heat generated in the nuclear core 7 of the steam generators 3'. Since the steam generator 3' is one of essential components of the primary cooling system, the use of this component eliminates the need for additional equipment, thereby enabling simplification of facility and improvement in economy. Also, since the steam generator 3' is originally designed to remove heat generated in the nuclear core during a normal operation, it has an excellent and sufficient cooling capacity.
Therefore, the invention disclosed in Japanese Patent Application No. 401077/1990 can provide a passive core decay heat removing system which can remove decay heat in a substantially passive manner with the minimum use of active components of high reliability such as valves.
In the improved pressurized water nuclear power plant described above, however, the bottom of the crossover leg, that is the low-temperature side pipe P1 connecting the low-temperature side water chamber of the steam generator 3' and the reactor coolant pump 5, remains below the upper portion of the nuclear core 7 as shown in FIG. 10.
For this reason, in the conventional pressurized water reactor plant, a water stagnant or staying in the crossover leg tends to increase a back pressure in a core when a pipe breaking accident of smaller scale occurs at the outlet side of the reactor coolant pump 5. Such a rise in the back pressure tends to block a supply of water into a nuclear core, when an emergency core cooling water is poured into the primary cooling system, reducing the cooling of the nuclear core.


The ribbon cartridge includes a re-inker assembly having a pair of idler rollers defining a nip therebetween through which the print ribbon is advanced. The idler rollers have teeth intermeshing one with the other and with the print ribbon therebetween such that the idler rollers are positively driven when the ribbon is advanced. One of the idler rollers lies in contact with a re-inker roller or wick for transferring ink from the re-inker roller or wick to the print ribbon as the ribbon passes through the nip of the idler rollers.

In commercial high speed printers, ribbon cartridges are typically consumable items discarded after use and replaced with fresh cartridges. To extend the life of the print ribbon within the cartridge, various systems have been employed. For example, re-inking systems for applying fresh ink to the print ribbon have been utilized. While various types of re-inker systems are known, such systems conventionally advance the print ribbon against a re-inker roller or an idler roller having a smooth surface in contact with the re-inker roller. Thus, the drive mechanism for advancing the ribbon from a ribbon exit arm of the cartridge across the span in opposition to the print head and for entry into the entrance arm of the cartridge must also advance the ribbon past the idler roller in contact with the re-inker roller or with the re-inker roller per se. In the typical system employing a re-inker roller, substantial tension on the ribbon is required such that the ribbon can frictionally bear against and drive the idler roller which in turn must also drive the re-inker roller or directly engage and drive the re-inker roller. This assures that a fresh supply of ink is readily available for transfer to the ribbon and also ensures that the ink transfer actually occurs. A substantial portion of the ribbon must therefore wrap about the idler roller or re-inker roller in order to rotate the roller and ensure ink transfer to the ribbon. This higher tension required on the ribbon in order to rotate the re-inker roller is undesirable because such increased tension on the print ribbon causes problems in the drive mechanism. Additionally, it will be appreciated that the print ribbon as it leaves the storage chamber within the cartridge is drawn about various corners which increase the frictional drag on the print ribbon, exacerbating the already undesirable increased tension on the ribbon caused by the need to rotate the re-inker roller. In certain systems, the re-inker assembly also fails because of slippage between the print ribbon and the idler roller resulting in failure of the ink to transfer to the print ribbon.

Print ribbon cartridge with re-inker assembly


Methods and devices for configuring transmit antenna mode for a user equipment that can transmit in the uplink using at least two transmit antennas are provided. In accordance with embodiment a transmit antenna mode of the user equipment can be configured in response to a measured transmit antenna imbalance. Methods and devices for configuring transmit antenna mode for a user equipment that can transmit in the uplink using at least two transmit antennas are provided. In accordance with embodiment a transmit antenna mode of the user equipment can be configured in response to a measured transmit antenna imbalance.

Multiple-antenna technology is widely used in wireless communication systems such as cellular radio systems. For Long Term Evolution (LTE), Downlink (DL) Multiple Input Multiple Output (MIMO) was standardized by third generation partnership project (3 GPP) in release 8 (Rel 8 ). For Wideband Code Division Multiple Access (WCDMA) High Speed Packet Access (HSPA) evolution, downlink 2 by 2 MIMO was specified in Release 7 (Rel 7 ). The introduction of uplink multiple-antenna technology is being discussed in 3 GPP, including Uplink Transmit Diversity (ULTD) in WCDMA and uplink (UL) MIMO in LTE. With ULTD or UL MIMO, there will be at least 2 transmit (TX) antennas in the User Equipment (UE).
Known examples of ULTD include Switch Antenna Transmit Diversity (SATD) and Beam Forming Transmit Diversity (BFTD). For SATD, the UE transmits on the transmit (TX) antenna with better estimated uplink quality in terms of e.g. received Dedicated Physical Control Channel (DPCCH) power or DPCCH Signal to Interference plus Noise Ratio (SINR). For BFTD, the UE transmits on both TX antennas with an estimated weight factor to maximize received power or SINR. The ULTD technology can improve the system capacity and coverage, and save the UE battery consumption in most cases. There are two types of ULTD modes, Open Loop ULTD (OLTD) and Closed Loop ULTD (CLTD). In the latter case there is specific downlink feedback channel from the radio base station, Node B, to UE carrying the pre-coding vector or the information to assist the generation of pre-coding vectors of ULTD. For OLTD, there is no OLTD-specific downlink feedback channel from Node B to UE to support the ULTD operation. For CLTD, in order for the Node B to generate the desired pre-coding information to the UE over the specific downlink feedback channel, the Node B should also monitor the uplink channels. Traditionally the pre-coding vector is generated in the radio base station (Node B) side and sent to the UE. Alternatively the Node B can also send only the channel state information to UE, which in turn can autonomously create the pre-coding vector. Antenna imbalance is one key factor that impacts the system performance of OLTD, CLTD and UL MIMO.
OLTD for WCDMA-HSPA
For WCDMA-OLTD, the UE does the transmit adaptation of the 2 transmit antennas based on the available existing information. Algorithms for open loop SATD and for open loop BF are described in 3GPP Technical Report TR 25.863, "Uplink Tx Diversity for HSPA Study Item Technical Report".
In case of SATD, there are two TX antennas and single full-power power amplifier in the UE. With the scheme described in TR 25.863, the UE selects the TX antenna according to the TPC statistic as follows:    1. Let TPC command DOWN be represented by −1 and TPC command UP by +1. Then let the UE accumulate all received TPC commands.    2. At each frame border the accumulated TPC sum is compared with 0. If the sum is larger than 0 the transmit antenna is switched.    3. If the same transmit antenna has been used for x consecutive frames the UE automatically switches antenna. x can be referred as the forced switch circle and determined according to the radio environments.    4. Every time an antenna switch occurs the accumulated TPC sum is reset to 0.
In case of BFTD, there are two power amplifiers in the UE side. With the algorithm described in 3GPP R1-102931, Concept of UL Closed Loop Transmit Diversity, the UE adjusts the beam by adjusting the phase bias between two antennas based on the received TPCs in accordance with the following:                A. The phase offset, δ, can be 48 degrees, ε can be 12 degrees.        B. Let TPC command DOWN be represented by −1 and TPC command UP by +1.                    1. Initial relative phase between two transmitters Δφ=−δ/2 for the first slot (#1 slot). ε is kept zero until two TPC commands become available to the UE.            2. Apply relative phase for the next slot Δφ=Δφ+δ            3. Determine new relative phase:                            a. if TPC1>TPC2, Δφ=Δφ+ε                b. if TPC2>TPC1, Δφ=Δφ−ε                c. otherwise, no change                                                Note that TPC1 and TPC2 correspond to slot (1,2 ),(3,4 ),. . . ,(i*2 −1 , i*2 ), where i=1 to n.                    4. Apply relative phase for the next slot Δφ=Δφ−δ            5. Go to step 2
A UL OLTD capable UE can be configured in default mode (fixed single TX antenna), OLTD mode (open loop SATD or BFTD).
CLTD in HSPA
CLTD was proposed in 3GPP RAN1-61 conference. The uplink closed loop transmit diversity scheme is based on the explicit uplink channel estimation and Channel Status Information (CSI) feedback was proposed. With this proposal, the network controls of the UE behavior and the adaptation of the transmit weights in a quickly. The simulation results show that the average throughput gain reaches 14% in Pedestrian A channel (3 km/h) and up to 10% in Vehicular A (30 km/h) channel. Overall CLTD can be a valuable complement that should be further considered for improving the HSPA uplink.
A UL CLTD UE can be configured in default TX antenna mode, open loop BFTD Mode and close loop BFTD mode.
UL MIMO in HSPA
For LTE, UL MIMO comprising of up to 4 transmit antennas in the UE is being specified, see RP-091430, UL multiple antenna transmission for LTE, work item, RAN#46. For WCDMA-HSPA, UL MIMO can be proposed naturally in 3GPP by companies after UL beam-forming is standardized since there is no hardware update for ULBF UE to support UL MIMO. In the current WCDMA-HSPA Node B, there are two receiver antennas. In the future, there can be even more receiver antennas and more advanced receiver technology that can be deployed in the network side, which means that there can be even larger gain from UL MIMO. For instance, the advanced receivers such as enhanced receiver Type 3 and interference cancellation technology can be deployed in the Node B side when the related cost is decreased to an acceptable level.
A UL MIMO capable UE can be configured in default single TX antenna mode, open loop BFTD Mode, close loop BFTD mode and UL MIMO mode.
There is a constant desire to improve upon existing transmission schemes. This is also true for configuration of uplink transmit diversity. Hence, there exist a need for an improved configuration of uplink transmit diversity

Methods and devices for configuring antenna mode for uplink communication


In the present method of programming and erasing the resistive memory devices of a memory device array, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices whose state is to be changed from the previous state.

1. Technical Field
This invention relates generally to memory devices, and more particularly, to resistive memory device operation.
2. Background Art
FIG. 1 illustrates a type of resistive memory device 30 known as an ion motion resistive memory device. The memory device 30 includes an electrode 32 (for example copper), a copper sulfide layer 34 on the electrode 32, an active layer 36, for example a copper oxide layer, on the layer 34, and an electrode 38 (for example titanium) on the active layer 36. Initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 38, while a positive voltage is applied to electrode 32, so that an electrical potential Vpg (the "programming" electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the forward direction of the memory device 30 (see FIG. 2, a plot of memory device current vs. electrical potential applied across the memory device 30). This potential is sufficient to cause copper ions to be attracted from the layer 34 toward the electrode 38 and into the active layer 36 (A) so that conductive filaments are formed, causing the active layer 36 (and the overall memory device 30) to be in a (forward) low-resistance or conductive state. Upon removal of such potential (B), the ions drawn into the active layer 36 during the programming step remain therein, so that the active layer 36 (and memory device 30) remain in a conductive or low-resistance state.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the "read" electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the forward direction of the memory device 30. This electrical potential is less than the electrical potential Vpg applied across the memory device for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device, a positive voltage is applied to the electrode 38, while the electrode 32 is held at ground, so that an electrical potential Ver (the "erase" electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the reverse direction of the memory device 30. This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the layer 34 (C), causing the active layer 36 (and the overall memory device 30) to be in a high-resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory device 30.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the forward direction of the memory device 30, as described above. With the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state. A resistive memory array typically includes a large number of these memory devices 30, each of which can be individually read, programmed and erased.
As will be noted from the above description and FIG. 2, relatively low current is required for reading the state of the memory device 30 (desirable to apply low voltage so as to avoid disturb into another state), while substantially higher currents are required for programming and erasing the device 30. In turn, architecture for proving such high currents is required.
Additionally, typically, in a conventional flash memory array, a two-command approach is undertaken, wherein, upon a first command, a whole page of data is erased, and then upon a second command data is written into the array. It would be desirable to provide an approach wherein, upon a single command, erasing and programming is undertaken on only those the memory devices wherein a change of state is required from the previous state, i.e., those memory devices whose state is not to be changed from the previous state are left in that state and do not undergo an erase or program operation.
Therefore, what is needed is a method of meeting the high current needs in programming and erasing the memory devices of resistive memory devices, meanwhile using a single command and changing the state of only those memory devices wherein a change of state is required.

Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices


An immobilized substrate surface is chemically modified by manipulating an nzyme which is immobilized to a solid surface. Modifications include (1) chemical dissection of a substrate surface such as by chemical hydrolysis, (2) chemical synthesis on a substrate surface, and (3) chemical patterning of a substrate surface. The enzyme may be coupled to colloidal beads or particles, locally flat solid surfaces including planar, textured planar, cylindrical and spherical surfaces or arbitrary predefined shapes, or scanning probe microscope probes. In the patterning applications, colloidal particles containing the enzyme can be confined to desired regions of the substrate surface by various techniques which control the movement of the particles. The particles can be confined to tunnels or channels in a patterned polymer mold on top of the substrate surface. The enzyme can also be immobilized onto the surface of a raised pattern and this patterned surface can then be placed in contact with the immobilized substrate.

1. Field of the Invention
This invention relates to an enzyme-substrate system where both the enzyme and substrate are immobilized to solid surfaces and the immobilized enzyme is manipulated such that it can chemically modify the immobilized substrate surface.
2. Description of the Previously Published Art
Many approaches exist for immobilization of enzymes on solid surfaces. Enzymes have been covalently immobilized on chromatography supports for use as a chemically active chromatography column for detecting and/or modifying enzyme substrates passing through the column as described by P. Jadaud et al, J. Chromotography, 476, 165-174 (1989). Alternatively, immobilized enzymes have been used in assays for calorimetric detection of analytes such as the ELISA assay as described by D. J. Reen, Methods in Molecular Biology, 32, 461-6 (1994). As a result of these two technologies, a wide variety of immobilization chemistries have been developed which may be used to maximize the activity of the immobilized enzyme in question. Thus, the art of enzyme immobilization is a mature technique which provides a strong base on which to build this new technology.
In a manner similar to enzyme immobilization, the immobilization of enzyme substrate materials which are capable of reacting with enzymes such as peptides, proteins, lipids, carbohydrates and nucleic acids has been widely studied by many and the following three are just illustrative of that work: Vandenberg et al, J. Colloid Interface Sci, 143, 327-335 (1991); H. Lang et al, Langmuir, 10, 197-210 (1994); and S. Britland et al, Biotechnol. Prog., 8, 155-160 (1992). There have also been several reports which described solution enzyme modification of (solid surface) immobilized substrates as exemplified by T. E. Wilson et al, Langmuir, 10, 1512-1516 (1994) and I. H. Hagestam et al, J. Chromotography, 351, 239-248 (1986). There are no reports, however, indicating that solution phase enzymes have been used to make chemical patterns on substrate surfaces.
Many techniques have been developed for modification and patterning of solid surfaces. These range from conventional lithography utilizing photoresists (including electron and ion beams) as described in the book Semiconductor Lithography by W. Moreau, Plenum Press, New York, (1988); patterning of self-assembled monolayer and silane ultrathin films as described by J. M. Calvert, J. Vac. Sci. Technol., B11, 2155-2163 (1993) and A. Kumar et al, Langmuir, 10, 1498-1511 (1994); and a variety of patterning approaches using scanning probe microscopes as described in The Technology of Proximal Probe Lithography, C. R. K. Marrian, Ed, SPIE Volume IS10, SPEE Press, Bellingham, Wash. (1993). Some of these approaches do exhibit a degree of chemical selectivity (mainly by absorbing photons of specific energy) as seen by the Moreau and Calvert publications, however, none show the spectrum of chemical selectivity possible with enzyme controlled modification. In addition, conventional photoresist patterning requires harsh chemical conditions (organic solvents, elevated temperature) to develop the patterns. Both conventional photoresist and ultrathin film resists require intense photon sources or electron/ion sources to carry out the patterning.
3. Objects of the Invention
It is an object of this invention to provide chemically specific modification of surfaces in a controlled manner.
It is a further object of this invention to provide chemically specific modification of surfaces based on enzyme based catalysis chemistry which uses environmentally benign reaction conditions.
It is a further object of this invention to provide chemical dissection of a surface where the catalytic reactants can be quickly and easily recovered via filtration without fouling the system or the surface.
It is a further object of this invention to provide chemical dissection of a surface by chemical hydrolysis.
It is a further object of this invention to provide chemical modification of a surface where several enzymes could be used on the same substrate to carry out different types of chemically specific modifications.
It is a further object of this invention to provide for a complex series of chemical steps that can be carried on a surface without introduction of harsh solvents or conditions.
It is a further object of this invention to conduct environmentally friendly surface synthesis via enzyme catalyzed chemical reactions.
It is a further object of this invention to provide chemically specific synthesis of surfaces based on enzyme based catalysis chemistry which uses environmentally benign reaction conditions.
It is a further object of this invention to provide chemically-specific patterning and modification of surfaces.
It is a further object of this invention to create complex chemical patterns on a surface.
It is a further object of this invention to provide chemically specific patterning and modification of surfaces based on enzyme based catalysis chemistry which uses environmentally benign reaction conditions.
It is a further object of this invention to create complex chemical patterns on a surface without the use of harsh solvents or conditions.
It is a further object of this invention to create complex chemical patterns on a surface with an enzyme scheme which takes place in an aqueous environment without the need for harsh conditions like organic solvents, high energy beams, or extreme temperature.
It is a further object of this invention to conduct chemical patterning to take place with high chemical selectivity and without ancillary damage to surrounding surface components or the solid substrate material.
It is a further object of this invention to manipulate the position of a single bead coated with immobilized enzymes for high resolution patterning of substrate surfaces.
It is a further object of this invention to place immobilized enzymes on a solid surface which would then be used as a chemical stamp to allow rapid reproduction of a complex pattern on many substrate surfaces.
These and further objects of the invention will become apparent as the description of the invention proceeds.

Chemically specific patterning on solid surfaces using surface immobilized enzymes

The United States of America as represented by the Secretary of the Navy