A dynamic random access memory comprises a CBR refresh detection unit for detecting a commencement of a CBR refreshing cycle and a control signal generation unit for deactivating data output during the CBR cycle, both of the CBR refresh detection unit and the control signal generation unit being supplied with a /RAS signal and a /CAS signal simultaneously, wherein the dynamic random access memory further comprises a CBR refresh control unit supplied with an output of the CBR refresh detection unit and further with an output of the control signal generation unit for producing a control signal during the CBR refreshing cycle such that the control signal is produced in response to the leading edge of the /RAS signal and terminated in response to the trailing edge of the /CAS signal. Thereby, an output buffer circuit is controlled in response to the output of the control signal generation unit and the control signal of the CBR refresh control unit to set the output buffer circuit in the high impedance state during the CBR refreshing cycle.

The present invention generally relates to memory devices, and more particularly to a dynamic random access memory having an improved operational stability.
Dynamic random access memories store information in a memory cell capacitor in the form of electric charges. The device has a simple semiconductor structure and can be fabricated easily with a very large integration density. Thus, dynamic random access memories are particularly suitable for realizing high-speed, large capacity storage devices.
In dynamic random access memories, it is well known that a refreshing procedure is necessary for maintaining the information. In the refreshing process, the memory cell capacitor is re-charged in compensation for the loss of electric charges that may be caused by the leakage current or other various reasons such as reading. More specifically, the information stored in the memory cell capacitor is detected by a sense amplifier and the sense amplifier re-writes the information into the memory cell capacitor in the form of electric charges.
Typically, such a refreshing cycle is activated by providing a predetermined time relationship between the /RAS signal used for activating the row address selection and the /CAS signal used for activating the column address selection. More specifically, the timing of the /CAS signal is advanced with respect to the timing of the /RAS signal at the beginning of the refreshing cycle, while the end of the refreshing cycle is marked by the trailing edge of the /CAS signal or /RAS signal. Such a procedure is known as CBR (CAS-before-RAS) process. During the refreshing cycle, the output of the memory device is held at a high impedance state such that no output of information occurs. Thus, conventional dynamic random access memories require a complex control system at the peripheral part thereof for effecting the refreshing cycle.
FIG. 1 shows the construction of a conventional dynamic random access memory in the form of a block diagram.
Referring to FIG. 1, the dynamic random access memory includes a row address buffer circuit 1 supplied with multiple-bit address data A0-An for latching the same and a row decoder 2 that selects a word line from a memory cell array 3 based upon the address data latched in the address buffer circuit 1. As usual, the memory cell array 3 includes a number of memory cells 3a arranged in rows and columns, wherein a number of word lines are provided, extending in the row direction. Further, a number of bit lines are provided, extending in the column direction. Further, the illustrated device includes a column address buffer circuit 4 supplied with multiple-bit address data A0-An for latching the same and a column decoder 5 that selects one of the bit lines from the memory cell array 3 based upon the address data latched in the address buffer circuit 4.
In the dynamic random access memories in general, the address data A0-An are supplied to the address buffers 1 and 2 with an address-multiplexing sequence such that the row address data is supplied first and the column address data is supplied after the row address data. Further, in order to distinguish the timing of the row address data and the column address data, a /RAS (row address strobe) signal and a /CAS (column address strobe) signal are supplied externally. In the illustrated example, the /RAS signal is supplied to a RAS control circuit 15 via an input pad 14, while the /CAS signal is supplied to a CAS control circuit 15 via another input pad 16.
Once a word line and a bit line are selected, the data stored in the memory cell at the intersection of the selected word line and the selected bit line is detected by a sense amplifier that is provided in a sense amplifier array 6, and the data thus detected is transferred to an output buffer circuit 8 via a column gate array 7. When writing data, on the other hand, a write enable signal /WE is supplied to a write clock generator 13 via an input pad 12, and a write clock produced by the write clock generator 13 activates an input buffer circuit 11. Thereby, input data D.sub.in supplied to an input pad 10 is transferred to the sense amplifier array 6 from the buffer amplifier 11 and is written into the selected memory cell via the column gate array 7.
There, the CAS control circuit 17 not only controls the column decoder 5 but also the write clock generator 13 as well as the output buffer circuit 8 such that the output buffer circuit 8 and the write clock generator 13 are enabled in the normal write cycle. More particularly, the CAS control circuit 17 controls the output buffer circuit 8 such that the output impedance of the circuit 8 becomes high during the refreshing cycle.
In such a control operation of the CAS control circuit 17, various thresholding processes are included to discriminate the logic level of the /RAS signal and the /CAS signal. Conventionally, there has been a problem in that, depending on the sharpness of the leading and trailing edges of the /RAS signal and the /CAS signal, the timing of enabling and disabling of the buffer circuit 8 may be changed. In the worst case, such a deviation in the operational timing can lead to a premature enabling of the buffer circuit 8 while the refreshing cycle is still continuing. Hereinafter, this problem will be examined in detail with reference to FIG. 2 showing a part 18 of the circuit of FIG. 1.
Referring to FIG. 2, the circuit 18 includes a first stage circuit 19 for producing a control signal S100 the waveform of which is shown in FIGS. 4(A) and 4(B), in response to the /RAS signal and with a predetermined timing relative to the /RAS signal. The control signal S100 is supplied on the one hand to a circuit 20 that produces a control signal S101 shown in FIGS. 6(A)-6(D) and on the other hand to a circuit 22 that produces a control signal S103 shown in FIGS. 9(A)-9(F), wherein the control signal S103 is supplied from the circuit 20 to an address control circuit 21A together with the control signal S100, and the address control circuit 21A activates the column address buffer circuit 4 and the column decoder 5. The circuit 22, on the other hand, controls the output buffer circuit 8 by the control signal S103 that is supplied to an output control circuit 25.
Further, the circuit 19 supplies the control signal S100 to a circuit 23A that is provided for detecting the commencement of a refreshing cycle, and the circuit 23A supplies an output control signal S121 to a control circuit 24A that produces an output control signal S102 for controlling the output control circuit 25. Thus, the output control circuit 25 is supplied with the control signals S103 and S102 respectively from the circuits 22 and 24A and further with the control signal S100 from the circuit 19, and controls the operation of the output buffer circuit 8 such that the output buffer circuit 8, is at a high impedance state during the refreshing cycle.
FIG. 3 shows the construction of the circuit 19 and FIGS. 4(A) and 4(B) show the timing of producing the output signal S100 in response to the /RAS signal.
Referring to FIG. 3, the circuit 19 includes inverters 26 and 27 connected in series to the input pad 14 such that the /RAS signal supplied to the input pad 14 is delayed by a predetermined time interval that is determined by the number of stages of the inverters. In the illustrated example, two inverters 26 and 27 are used. Thereby, the output control signal S100 is produced in response to the /RAS signal with a predetermined delay therefrom.
FIG. 5 shows the construction of the circuit 20, wherein the circuit 19 is illustrated together by a broken line.
Referring to FIG. 5, the circuit 20 includes a NOR gate 28 and an inverter 29 cascaded with each other, wherein the output signal S100 of the circuit 19 is supplied to a first input terminal of the NOR gate 28 and the /CAS signal at the input pad 16 is supplied to a second input terminal of the NOR gate 28. The output of the NOR gate 28 is inverted in the inverter 29 and forms the output control signal S101 with a timing as indicated in FIG. 6(D). Thus, the signal S101 is at a low level state when both the signal S100 and /CAS have the low level state.
FIG. 7 shows the construction of the address control circuit 21A, wherein it will be noted that the address control circuit 21A includes a circuit 21a that in turn is formed of inverters 211 and 212 cascaded with each other, and the output of the circuit 21a is supplied to the address buffer circuit 4 that includes transistors 4a-4d connected in series between two power supply voltage sources wherein the transistors 4a and 4b are formed of a P-channel MOS transistor while the transistors 4c and 4d are formed of an N-channel MOS transistor. The output of the circuit 21a is supplied directly to the gate of the transistor 4d and further to the gate of the transistor 4a after inversion by an inverter 4e. Further, an address signal An is supplied to the gate of the transistors 4b and 4c after inversion in an inverted 4f. The output of the transistor circuit is obtained at an intermediate node between the transistors 4b and 4c and is latched by a latch circuit formed of inverters 4g and 4h. The output of the address buffer circuit 4 is then supplied to the column decoder 5 that is formed of a multiple input NAND gate 5a and an inverter 5b cascaded thereto, wherein the address data of other address bits such as A.sub.n-1, . . . A.sub.0 are supplied to the gate 5a. The output of the inverter 5b is outputted on the column line CL as usual.
FIG. 8 shows the construction of the circuit 22 for producing the control signal S103 for controlling the activation of the output buffer circuit 8, wherein the circuit 22 includes a NAND gate 30, a NOR gate 21 and inverters 32 and 33 connected to form a flip-flop circuit, wherein the NAND gate 30 and the inverter 32 are connected in series to produce an signal S02, and the signal S02 thus produced is supplied to the NOR gate 31 that is connected in series to the inverter 33. The inverter 33 in turn produces a signal S01 that is fed back to the NAND gate 30. Further, the control signal S100 is supplied to the NAND gate 30 from the circuit 19 in response to the /RAS, while the /CAS signal is supplied from the input pad 16 to the NOR gate 31. Thus, the output signal S103 is produced by the signal S01 that has passed consecutively through inverters 34 and 35 that in turn are provided for the timing adjustment.
FIGS. 9(A)-9(F) show the operation of the circuit 22, a timing control circuit for producing the output control signal S103 in response to the /RAS and /CAS signals represented in FIGS. 9(A) and 9(B) as well as the signal S100 represented in FIG. 9(C), wherein it will be noted that the signal S01 undergoes a transition to the low level state in response to the leading edge of the /CAS signal and an opposite transition to the high level state in response to the trailing edge of the same /CAS signal, provided that the level of the signal S02 is held at the low level state in correspondence to the normal read cycle of the dynamic random access memory. On the other hand, when the level of the signal S02 is high in correspondence to the initial period of the refreshing cycle, the signal S01 does not undergo a transition immediately to the low level state even when the /CAS signal has undergone a transition to the low level state. Only when the signal S02 has undergone a transition to the low level state in correspondence to the transition of the /RAS signal that in turn occurs in correspondence to the refreshing cycle, the signal S01 undergoes a transition to the low level state. The signal S01 further undergoes another transition to the high level state in correspondence to the transition of the /CAS signal to the high level state.
On the other hand, the signal S02 experiences a transition to the low level state in the normal read cycle in response to the transition of the /RAS signal, and hence the signal S100 also experiences a transition to the low level state, irrespective of the state of the signal S01, wherein the low level state of the signal S02 continues until the signal S01 undergoes a transition to the high level state. Further, in the refreshing cycle, the signal S02 undergoes a transition to the low level state in response to the leading edge of the /RAS signal and maintains the low level state until the /RAS signal returns to the high level state.
In correspondence to the signal S01, the output control signal S103 is produced as indicated in FIG. 9(F), as a signal identically shaped as signal S01 but delayed therefrom by the timing of the inverters 34 and 35. The control signal S103 thereafter supplied to the circuit 25 for controlling the output buffer circuit 25, as already noted, wherein the output buffer circuit 8 is activated in response to the low level interval of the signal S103, while the same output buffer circuit 8 is deactivated in response to the high level state of the signal S103. During the high level state of the control signal S103, the output buffer circuit 8 exhibits a high output impedance state.
Next, the circuit 23A of FIG. 2 for detecting the CBR refreshing cycle will be described with reference to FIG. 10.
Referring to FIG. 10, the circuit 23A includes an inverter 23a, a NAND gate 23b connected in series to the inverter 23a for receiving an output signal U01 therefrom along a first path, an inverter 23c interposed in another path extending from the inverter 23a to the NAND gate 23b, an inverter 23d connected to the NAND gate 23b for inverting an output signal U02 of the gate 23b to produce an output signal U03, a NAND gate 23e supplied with the signal U03 and the signal S101 via an inverter 23f wherein the inverter 23f produces an output signal U07 as a logic inversion of the signal S101. Thereby, the NAND gate 23e produces an output signal U05, and the signal U05 is supplied to a NAND gate 23g that forms a flip-flop circuit together with another NAND gate 23h to which the output signal U07 of the inverter 23f is supplied. In the flip-flop circuit, the NAND gate 23g produces an output signal U06 that is supplied to the NAND gate 23h, and the NAND gate 23h produces an output control signal S121 that indicates the commencement of the CBR refreshing cycle.
Next, the operation of the circuit 23A will be described in detail with reference to FIGS. 11(A)-11(K), wherein FIGS. 11(A)-11(C) represent the signals /RAS, /CAS and S100, respectively.
It will be noted that the signal U01 experiences a transition to the high level state in correspondence to the leading edge of the signal s100 and returns to the low level state in response to the trailing edge of the signal S100, wherein the leading edge and trailing edge of the signal S100 correspond to the leading edge and trailing edge of the /RAS signal. Further, the signal U02 causes a momentary transition to the low level state in correspondence to the leading edge of the signal U01. Further, the signal U03 is produced as a logic inversion of the signal U02, and the signal U07 is produced as a logic inversion of the signal S101.
Further, the signal U05 experiences a transition to the low level state in response to the leading edge of the signal S100 and a transition to the high level state in response to the trailing edge of the /CAS signal or the trailing edge of the /RAS signal, whichever comes first. Thus, when the trailing edge of the /CAS signal, comes before the trailing edge of the /RAS signal as indicated in the drawing by "A," the signal U05 is reset in response to the trailing edge of the /CAS signal. In addition when the trailing edge of the /RAS signal appears before the trailing edge of the /CAS signal, as indicated by "B," the signal U05 is reset in response to the trailing edge of the /RAS signal. Further, the signal U06 experiences a transition to the high level state in response to the leading edge of the signal U05 and a transition to the low level state in response to the trailing edge of the signal U05. Thereafter, the output signal S121 is obtained in correspondence to the signal U06.
It should be noted in FIGS. 11(A)-11(K) that the signal S121 is not produced in the normal read write cycle. This is because the signal S101 takes a high level state in the normal read cycle when the signal U03 has caused the transition in response to the signal S100. In other words, the signal S121 is produced only when the /CAS signal has preceded the /RAS signal. Further, the signal S121 is reset by the trailing edge of the /CAS signal, or /RAS signal whichever appears first.
Next, the construction of the CBR control circuit 24A will be described with reference to FIG. 12.
Referring to FIG. 12, the circuit 24A includes a number of inverters 24a-24f cascaded in series, and the inverter 24f supplies an output signal to a NAND gate 24g. Further, an output V01 of the inverter 24c included in the cascaded inverters is supplied directly to the NAND gate 24g as another input signal, and the NAND gate 24g produces an output signal V02 as a result of the logic combination of the output of the inverter 24f and the output of the inverter 24c. The output of the NAND gate 24g in turn is supplied to a NAND gate 24h that forms a flip-flop circuit together with a NAND gate 24i, wherein the NAND gate 24i is supplied with an output signal V03 that is produced by an inverter 24g in response to the control signal S101. In the flip-flop circuit, the NAND gate 24h produces the output signal S102 and the signal S102 thus produced is fed back to the NAND gate 24i. The NAND gate 24i in turn produces an output signal V04 and supplies the same to the NAND gate 24h.
FIGS. 13(A)-13(J) show the operation of the CBR control circuit 24A, wherein FIGS. 13(A) and 13(B) show the waveform of /RAS signal and /CAS signal, while FIG. 13(C) shows the waveform of the signal S100 and FIG. 13(D) shows the waveform of the signal S121. Further, FIG. 13(E) shows the waveform of the signal S101. In addition, FIGS. 13(F)-13(I) show the waveform of the signals V01-V04, respectively, and FIG. 13(J) shows the waveform of the signal S102.
Referring to the drawings, the signals S100, S121 and S101 are produced with the timing sequence already described, and the signal V01 is produced as a logic inversion of the signal S121 with a predetermined delay therefrom. Further, the signal V02 is produced in correspondence to the leading edge of the signal V01 and continues for an interval determined by the delay caused by the inverters 24d-24g. The signal V03 is produced as a logic inversion of the signal S101. Moreover, the signal V04 is produced in response to the signals V03 and S102 and undergoes a transition to the low level state in response to the leading edge of the signal S102. Further, the signal S102 is produced in response to the leading edge of the signals V02 and V04. There, the signal V04 maintains the low level state until the signals V03 and S102 undergoes a transition to the low level state. Similarly, the signal S102 maintains the high level state until the signal V04 causes a transition to the low level state.
As indicated in FIGS. 13(A)-13(J), the trailing edge of the signals S102 is determined by the timing of the trailing edge of the /CAS signal or the /RAS signal whichever comes first. Thus, as indicated in "A" in FIGS. 13(A)-13(J), the control signal S102 is reset in response to the timing of the trailing edge of the /CAS signal when the /CAS signal ends before the /RAS signal. Similarly, the reset of the control signal S102 occurs in response to the trailing edge of the /RAS signal, as indicated by "B" in the figures in the case when the trailing edge of the /RAS signal causes before the trailing edge of the /CAS signal.
Next, the circuit 25 for controlling the output buffer circuit 8 in response to the control signals S100, S102 and S103 will be described with reference to FIG. 14.
Referring to FIG. 14, the circuit 25 includes an inverter 25a supplied with the output control signal S100 for inverting the same to produce an output signal W01, wherein the signal W01 is supplied to a NAND gate 25b. Further, inverter 25c is supplied with the control signal S102 and produces a signal W02 as a logic inversion thereof. The signals W01 and W02 are supplied to a NAND gate 25b, wherein the NAND gate 25b produces an output signal W03 and supplies the same to an inverter 25d that produces an output signal W04 as a logic inversion of the signal W03. The signal W04 is then supplied to another NAND gate 25e that is further supplied with a signal W05 from an inverter 25f as a logic inversion of the signal S103. Thereby, the NAND gate 25e produces an output that is passed through an inverter 25g to form a control signal S111. The signal S103 is further supplied to a NOR gate 25h that is also supplied with the same signal S103 but with a delay caused by inverters 25i and 25j, wherein the gate 25h produces a control signal S112.
The control signals S111 and S112 are used for controlling the output buffer circuit 8 of which construction is shown in FIG. 15.
Referring to FIG. 15, the circuit 15 includes a NAND gate 8a supplied with the control signals S111 and S112 to produce a signal X01 which is inverted subsequently by an inverter 8b to produce a signal X02. The signal X02 in turn is supplied to a transfer gate 8c formed of an N-channel MOS transistor and causes a transfer of data S141 outputted from a sense amplifier in the sense amplifier array 6 to a NAND gate 8d as a signal X11 in response to the high level state of the signal X02. The NAND gate 8d is supplied with the signal S112 in addition to the signal X11 and produces a signal X12 that is latched by a flip-flop circuit formed by the gate 8d and a feedback path 8e. The output signal X12 of the gate 8d is supplied to a gate of an N-channel MOS transistor 8g for controlling the conduction thereof.
Further, the data S141 is supplied to another transfer gate 8i after passing through an inverter 8h, wherein the transfer gate 8i is formed of an N-channel MOS transistor similarly to the transistor 8c and is activated in response to the control signal X02 from the inverter 8b. Thus, the data that has passed through the transfer gate 8i is represented as a signal X21, wherein the signal X21 is supplied to a NAND gate 8j which is also supplied with the control signal S112. Again, the NAND gate 8j has a feedback path provided by an inverter 8k and forms a flip-flop circuit for latching the signal X21. The NAND gate 8j thereby produces an output signal X22 that is inverted subsequently in an inverter 81 with respect to the logic state thereof to form a signal X23 that is supplied to a gate of another N-channel MOS transistor 8m. There, the transistors 8g and 8m are connected in series between the voltage sources Vcc and Vss, and the output of the buffer circuit 8 is obtained at the output pad 9 that is connected to an intermediate node between the transistors 8g and 8m.
It should be noted that the low level state of the signal S111 causes a turning off of transfer gate transistors 8c and 8i, and the flip-flop circuit formed of the circuits 8c and 8e as well as the flip-flop circuit formed of the circuits 8j and 8k continue outputting the signals X12 and X22, provided that the signal S112 takes the high level state. When the signal S111 is in the high level state, on the other hand, the data signal S141 is supplied to the flip-flop circuits and is latched therein.
When the signal S112 has caused a transition to the low level state, on the other hand, the data latching by the flip-flop circuit is deactivated and the output signals X12 and X22 are both urged to the high level state. Thereby, the transistors 8g and 8m are both turned off and the output of the buffer circuit 8 takes the high impedance state. In summary, the output buffer circuit 8 outputs data when the signal S112 is in the high level state. When the signal S112 is in the low level state, the buffer circuit 8 shows the high impedance state.
Next, the operation of the circuit 25 will be described with reference to FIGS. 16(A)-16(L), wherein FIGS. 16(A) and 16(B) show the /RAS signal and the /CAS signal respectively, FIGS. 16(C)-16(E) show the control signals S100, S102 and S103 respectively, FIGS. 16(F)-16(J) show the signals W01, W02, W03, W04 and W05 respectively, and FIGS. 16(K) and 16(L) show the signals S111 and S112, respectively.
Referring to FIGS. 16(A)-16(L), the signal W01 corresponds to the signal S100 and undergoes a transition to the high level state and a transition to the low level state in response to the leading edge and the trailing edge of the signal S100. Similarly, the signal W02 corresponds to the signal S102 and undergoes a transition in response thereto. The signal W03 thereby causes a transition in response to the signal W01 and exhibits a low level state in the normal read cycle in correspondence to the high level state of the signal W01. Further, the signal W03 causes a momentary transition to the low level state in the CBR refreshing cycle in response to the interval after the signal W01 has undergone a transition to the high level state but before the signal W02 changes to the low level state. In response the signal W03, the signal W04 is produced as a logic inversion. Referring to FIGS. 16(H) and 16(I), it will be noted that the momentary transition of the signal W03 and hence the signal W04 occurs twice, the first during the interval in which the /CAS signal is low and the second during the interval after the /CAS signal has returned to the high level state.
The signal W05 represents a logic inversion of the signal S103 and controls the gate 25e such that the signal W04 is selectively passed therethrough in response to the high level interval of the signal W05. Thereby, the signal W04 that has passed through the gate 25e is passed further through the inverter 25g to form the signal S111. There, it will be noted that the signal S111 includes a high level state in correspondence to the /CAS signal in the normal read cycle and a momentary high level state in the CBR refreshing cycle in correspondence to the high level state of the signals W03 and W04. It should be noted that the signal S111 causes a latch operation of the output buffer circuit 8 in response to the low level state, while the latch is released in response to the high level state of the signal S111.
The signal S112 in turn is produced in response to the transition of the signal S103 that in turn is caused by the transition of the /CAS signal in the normal read cycle. In the CBR refreshing cycle, on the other hand, the signal S103 undergoes a transition to the low level state in response to the leading edge of the /RAS signal and a subsequent transition to the high level state in response to the trailing edge of the /CAS signal. Thereby, the signal S112 is also activated to the high level state in response to the leading edge of the /RAS signal and deactivated to the low level state in response to the trailing edge of the /CAS signal.
Referring to FIGS. 16(K) and 16(L) again, it will be noted that there exists a moment wherein the signals S111 and S112 are both high in the normal read cycle and the data output occurs in response to such a timing sequence wherein the signals S111 and S112 are both high. On the other hand, such a state does not exist in the refreshing cycle. There, the signal S111 causes a transition to the high level state momentarily in correspondence to the signals W03 and W04 before the signal S112 undergoes a transition to the high level state. However, such a transition of the signal S111 during in the low level interval of the signal S112 does not cause the data output and the output buffer circuit 8 remains in the high impedance state. When the signal S112 has caused a transition to the high level state subsequently to the momentary transition of the signal S111, on the other hand, the signal S111 is low in the high level interval of the signal S112, and the signals X12 and X22 are latched at the low level state. Thereby, the transistors 8g and 8m are both turned off and the output of the buffer circuit 8 is held also at the high impedance sate. Therefore, data output is prohibited during the refreshing cycle of the device.
On the other hand, there is a possibility that the signal S102 experiences a premature transition to the low level state when the /CAS signal rises gradually. Hereinafter, the problem of the conventional circuit described heretofore will be examined with reference to FIGS. 17(A)-17(L) showing the waveform of the signals shown in FIGS. 16(A)-16(L) for the case where the /CAS signal rises slowly as indicated in FIG. 17(B). Such a slow rise of the /CAS signal may be caused for example by the parasitic capacitance of the wiring used for transferring the /CAS.
It is important to note that the signal S111 undergoes a transition to the high level state in response to the leading edge of the signal W04, provided that the signal W05 maintains the high level state. See the circuit diagram of FIG. 14. There, such a transition of the signal W04 to the high level state can be induced not only in response to the leading edge of the /RAS signal but also in response to the trailing edge of the /CAS signal, as already noted in FIG. 16(I). In the normal operation of the device as represented in FIGS. 16(A)-16(L), it will be noted that the high level state of the signal W04 occurring in response to the trailing edge of the /CAS signal does not cause the output of the signal S111 because of the low level state of the signal W05. In the example of FIGS. 17(A)-17(L) on the other hand, the output of the signal S111 occurs because of the premature transition of the signal S102 in response to the gradual increase of the /CAS signal level, as shown in FIGS. 17(B) and 17(D). Therefore, an unwanted data output occurs during the CBR refreshing cycle and the operational specification of the dynamic random memory device for maintaining the output the output buffer amplifier at the high impedance state during the refreshing cycle is no longer satisfied.
The foregoing analysis of operation of various parts of the memory device of FIG. 2 indicates that the cause of the undesirably result is attributed to the independently conducted thresholding operation for detecting the trailing edge of the /CAS signal in the circuit 24A and in the circuit 22. Thus, the circuit 24A produces the signal S102 based upon the signal S101 that in turn is produced in the circuit 20, while the signal S103 is produces in the circuit 22. Therefore, when the signals S102 and S103 are produced based upon the same thresholding operation of the /CAS signal, the deviation of timing between the signal S102 and the signal S103 would be eliminated and the problem of undesirable data output during the CBR refreshing cycle will also be eliminated.

Dynamic random access memory having an improved operational stability


Methods and systems are provided which generate hard and soft values from signal samples of a differentially encoded signal by estimating channel coefficients associated with the received signal and determining metrics for each possible symbol pair which indicate the probability of a possible coherent symbol pair being encoded in the signal samples using the estimated channel coefficients and the signal samples. Soft values associated with differential bits or differential symbols encoded in the samples of the signal are then generated based on the determined metrics.

The present invention relates generally to radiotelephones and more particularly to the coherent demodulation of differentially encoded quadrature phase shift keying (DQPSK) signals.
The performance of receivers in wireless radio communications systems may degrade severely due to multipath fading. Although anti-fading techniques, like antenna diversity, equalization, and adaptive array processing, may be very effective in improving the performance of the receiver, forward error correction (FEC) techniques may be necessary to achieve acceptable voice and data transmission in wireless communication systems. FEC techniques provide redundancy by adding extra bits to the actual information bits, which allows the decoder to detect and correct errors. In the receiver, the decoding process can be performed by either using hard information values or soft information values, which are provided by the demodulator. Decoding using soft information values improves the receiver performance over decoding using hard information values. Therefore, to improve decoder performance, it may be important to provide accurate soft information from the demodulation process.
The U.S. digital cellular system (IS-136) uses xcfx80/4 shifted-DQPSK as a modulation scheme. Differential encoding of the transmitted signals allows both coherent and differential demodulation of the received signal. Although differential demodulators may not be complex to implement, it is widely accepted that the performance of differential detectors degrades rapidly in the presence of Inter-Symbol Interference (ISI) which may be caused by multi-path propagation. Therefore, coherent demodulators with equalizers are commonly used in many receivers. Such a receiver is described in U.S. Pat. No. 5,285,480 to Chennakeshu et al., entitled ADAPTIVE MSLE-VA RECEIVER FOR DIGITAL CELLULAR RADIO.
FIG. 1 depicts a block diagram of a xcfx80/4 shifted-DQPSK system with a conventional differential demodulator receiver. The transmitter 105 includes encoder 101 and differential modulator 102. Information bits are encoded in encoder 101 to produce coded bits. The coded bits are differentially modulated in differential modulator 102 to produce a differentially modulated signal, which is provided to antenna 104 for transmission. The transmitted signal reaches the radio receiver after passing through a propagation medium (e.g., a mobile radio channel). The transmitted signal plus any noise are received at the receiver antenna 106 and the received signal provided to receiver 114. The received signal is processed by the radio processor 108 which amplifies, mixes, filters, samples and quantizes the received signal to produce a baseband signal. A differential demodulator 110 demodulates the received signal and provides symbol or bit values to the decoder 112 which decodes the encoded bits and which may detect and correct possible errors in the received signal. As discussed above, the output of the demodulator 110 is preferably soft values which may provide higher performance in decoding.
Differential encoding of the transmitted signals allows both coherent and differential demodulation of the received signal. FIG. 2 shows a block diagram of a known apparatus for differential demodulation of the DQPSK modulated signals. The differential detector uses received samples to get hard and/or soft decision values. The present received sample is coupled to the multiplier 203. The present received sample is also fed into a delay 201. The delay 201 is coupled to a conjugate operator 202, and the output of the conjugate operator 202 is coupled to the multiplier 203.
In operation, the present received sample and the delayed and conjugated received sample are multiplied to undo the effect of the differential encoder at the transmitter. The real 204 and imaginary 205 part of the output of the multiplier provide the soft bit values corresponding to the two bits sent in one, di-bit symbol. Also, the hard values can be obtained by taking the sign 206 and 207 of the soft values as desired.
FIG. 3 shows a block diagram of a known apparatus for coherent demodulation of the DQPSK modulated signals. The coherent receiver utilizes channel estimation unit 302 which estimates the amplitude and phase of the mobile radio channel. These channel estimates are passed to the coherent QPSK demodulator 301 where the estimates of the QPSK symbols are generated. The channel parameters can be estimated using the known data sequences which are periodically inserted into the transmitted information sequences. In systems where the channel parameters change over the transmission of two consecutive known data sequences, like the U.S. digital cellular system (IS-136), it is desirable to adapt the channel parameters during the transmission of unknown data sequences. Such an adaptive coherent receiver is described in U.S. Pat. No. 5,285,480 to Chennakeshu et al. entitled ADAPTIVE MLSE-VA RECEIVER FOR DIGITAL CELLULAR RADIO.
The output values of the coherent QPSK demodulator 301, which are the hard coherent symbols, are passed through a differential detector 303 to undo the effect of the differential encoder in the transmitter. The outputs of the differential detector are the hard decision values corresponding to the transmitted information bits.
A semi-coherent demodulation of the DQPSK modulated signals is described in U.S. Pat. No. 5,706,313 to Blasiak et al. entitled SOFT DECISION DIGITAL COMMUNICATION AND METHOD AND APPARATUS in which only the phase and frequency offset are estimated using the received signal. After compensating the phase and frequency offset, the likelihood of each possible QPSK symbol value for each sample is calculated. Therefore, a likelihood vector for each sample is obtained and this likelihood vector is provided to the decoder. The decoder uses the likelihood vectors to estimate the transmitted symbol values.
Another conventional method for the soft decoding of differentially encoded QPSK signal is described in U.S. Pat. No. 5,754,600 to Rahnema entitled METHOD AND APPARATUS FOR OPTIMUM SOFT-DECISION VITERBI DECODING OF CONVOLUTIONAL DIFFERENTIAL ENCODED QPSK DATA IN COHERENT DETECTION. In this apparatus the differential and Viterbi decoders are integrated, i.e., differential decoding is part of the convolutional decoding process.
Soft information for maximum likelihood sequence estimation (MLSE) for frequency selective fading channels has been extensively studied, for example as described in J. Hagenauer and P. Hoeher, xe2x80x9cA Viterbi algorithm with soft-decision outputs and its applicationsxe2x80x9d, Proceeding of IEEE Globecom Conference, pp. 47.1.1-47.1.7, Dallas, Tex., USA, November 1989. These techniques have been extended to xcfx80/4 shifted-DQPSK systems for example as described in Jong Park, Stephan B. Wicker and Henry L. Owen, xe2x80x9cSoft Output Equalization Techniques for xcfx80/4 DQPSK Mobile Radioxe2x80x9d, IEEE International Conference on Communications, pp. 1503-1507, Dallas, Tex., USA, 1997. However, relatively little work has been directed towards soft information generation for coherent detection of xcfx80/4 shifted-DQPSK in non-ISI channels, i.e. channels without significant inter-symbol interference (ISI). A suboptimal approach is given that requires exponentiation and logarithm operation in Yow-Jong Liu, Mark Wallace and John W. Ketchum, xe2x80x9cA Soft-Output Bidirectional Decision Feedback Equalization Technique for TDMA Cellular Radioxe2x80x9d, IEEE Journal on selected areas in commun., Vol. 11, No. 7, September 1993. This approach does not consider all possible symbol values in determining a soft value and, further, does not result in a unique solution.
In light of the above discussion, a need exists for improved performance in soft value determination for coherent demodulation of differentially encoded signals for non-ISI channels.
In view of the above discussion, it is an object of the present invention to provide accurate soft values for differentially encoded information.
A further object of the present invention is to provide soft values in a manner which does not require complex implementation.
Still another object of the present invention is to provide soft values from coherent detection of differentially encoded bits or symbols.
These and other objects of the present invention are provided by methods and systems which generate soft values from signal samples of a differentially encoded signal by estimating channel coefficients associated with the signal and determining metrics for each possible combination of current and previous coherent symbol values which indicate the probability of a possible differential bit value being encoded in the signal using the estimated channel coefficients and the signal samples. Soft values associated with a bit or symbol encoded in the signal are then generated based on the determined metrics.
The use of each potential current and previous coherent symbol value in determining a combined metric provides metrics which take into account the probability of each potential symbol value. Thus, by utilizing metrics associated with each potential symbol value, an accurate soft value may be obtained.
In a further embodiment of the present invention, determining a soft value is done by summing the metrics for each possible current and previous coherent symbol value that corresponds to a first differential bit value to provide a first value metric sum and summing the metrics for each possible current and previous symbol value corresponding to a second differential bit value to provide a second value metric sum. The first value metric sum may be divided by the second value metric sum to provide a ratio of probabilities of the differential bit value being the first value and differential bit value being the second value. Further, the metrics may be exponentiated and the exponentiated metrics summed for each possible symbol pair corresponding to a first bit value to provide a first value metric sum. The exponentiated metrics are also summed for each possible symbol pair corresponding to a second bit value to provide a second value metric sum. Also, the logarithm of the ratio of probabilities may be taken to provide the soft value for the bit.
Furthermore, where the differentially encoded signal is received at a plurality of antennas and channel coefficients associated with each of the plurality of antennas are estimated, metrics may be determined for each possible coherent symbol value which indicate the probability of a possible symbol value being encoded in the signal using the estimated channel coefficients and the signal for each antenna. In such a case, each metric is a sum of metrics for each antenna. Also, an impairment correlation may be determined for the plurality of antennas. Metrics may then be determined for each possible symbol value which indicate the probability of a possible coherent symbol value being encoded in the signal using the estimated channel coefficients, the impairment correlation and the signal for each antenna. A noise power associated with the received signal may be determined and the metrics determined based in part on the noise power.
In a particular embodiment, a detected value is determined from the signal samples and the channel coefficients. The detected values may be bit values for symbols encoded in the differentially encoded signal. Furthermore, the determined soft values may be associated the detected bit values.
Preferably, the signal samples are generated by a radiotelephone receiving and processing a differentially encoded signal.
In another embodiment of the present invention, soft values are generated from signal samples by estimating channel coefficients associated with the received signal and determining metrics for each possible coherent symbol value which indicate the probability of a possible symbol value being encoded in the signal samples of the signal using the estimated channel coefficients and the signal samples of the received signal. The maximum of the combined metrics for each possible current and previous symbol value corresponding to first bit value is determined to provide a first maximum metric value. The maximum metric of the combined metrics for each possible current and previous symbol value corresponding to a second bit value is also determined to provide a second minimum metric value. The second maximum metric value is then subtracted from the first maximum metric value to provide a difference of log likelihoods of the bit value being the first bit value and the bit value being the second bit value. By selecting the maximum values the complexity of the soft value determination may be reduced as the exponentiation and logarithm need not be determined.
In still another embodiment of the present invention, soft values are generated from signal samples by estimating channel coefficients associated with the signal and determining metrics for detected coherent symbol values which indicate the probability of the possible symbol values being encoded in the signal using the estimated channel coefficients and the signal samples of the signal. A detected term is determined from the metrics associated with the detected symbols which provides a first value metric corresponding to the detected differential bit. A second value metric, which corresponds to the non-detected bit, is obtained by obtaining the two different metric values by either flipping the current detected coherent symbol value or the previous detected coherent symbol value and keeping the other coherent symbol value as the detected value and selecting the maximum metric value among these two values. This alternative embodiment may further reduce the complexity of the soft value determination by basing the soft value determination on a detected symbol value.

Information generation for coherent demodulation of differentially encoded signals


A terminator apparatus used with a SCSI bus line controls the voltage level of a notch occurring in data and/or control signals transferred on the bus line. The terminator apparatus includes a termination network, a current switching device, and a programmed monitoring circuit. The termination network generates a first current. The current switching device generates a second current. The monitoring circuit controls a programmed length of time that the second current is generated. The current switching device is responsive to the monitoring circuit for disconnecting the second current when the programmed length of time has been exceeded. The second current serves to raise the voltage level of the notch occurring in the signal lines when they are deasserted so as to prevent erroneous data from being transferred.

This invention relates generally to terminator devices and more particularly, it relates to an improved terminator apparatus used with a SCSI (acronym for small computer system interface) bus line for controlling the voltage level of a notch occurring in data and/or control signals transferred on the bus line so as to prevent erroneous data from being transferred.
One application where reliable data transfer becomes important is in the field of data transmission on a fully loaded SCSI bus line for communication between a plurality of data transceivers and a central processing unit (CPU) in a small computer. Typically, control signals REQ and ACK on respective request and acknowledge signal lines are used to perform a "handshake" so as to transfer the data back and forth between a target (i.e., a disk drive) and an initiator (i.e., a host computer). Each of the control signals REQ and ACK is essentially a plurality of pulses having either a high logic value or a low logic value. When the control signal REQ or ACK is asserted, it is at the low logic value. When the control signal REQ or ACK is deasserted, it is at the high logic value.
In operation, when the control signal REQ on the request line makes the transition from the asserted condition to the deasserted condition (i.e., low-to-high transition), there exists a condition on the SCSI bus line which can cause the corruption of data. At the rising edge of the control signal REQ, there will appear what is referred to as a "notch." This notch is typically accompanied by a reflection caused by stub drive cabling. The combined effect of the notch and the stub reflection will cause the rising edge of the control signal REQ to reverse its direction and "double back" before reaching the deassertion level (i.e., +2.0 volts). If this reversing control signal REQ falls below the +1.5 volt level, it may result in a "double trigger" and be interpreted as a valid request signal (i.e., another assertion), thereby causing erroneous data to be transferred.
As is generally well known in the art of computer equipment manufacturing, a termination device is typically connected to each end of an OR-WIRED SCSI bus line for supplying a fixed supply voltage with a predetermined impedance. In FIG. 1, there is shown prior art termination networks 10 and 12 connected to the respective ends of the OR-WIRED SCSI bus line 14. The termination network 10 or 12 of FIG. 1 is sometimes referred to as a "220/330 terminator." Each of the termination networks 10, 12 includes a voltage divider formed of two resistors T1 and T2 connected in series. One end of the resistor T1 is connected to an input power supply voltage TERMPWR, which is typically at +4.75 volts. One end of the resistor T2 is connected to a ground potential GND, which is typically at zero volts. The junction of the resistors T1 and T2 for the termination network 10 is connected to one end of the bus line 14, and the junction of the resistors T1 and T2 for the termination network 12 is connected to the other end of the bus line. For the SCSI bus line, the value of the resistors T1 and T2 are shown to be 220.OMEGA. and 330.OMEGA. respectively so as to provide approximately + 2.85 volts at the junction points J1 and J2 when the bus line is not active.
The OR-WIRED SCSI bus line 14 has a plurality of transceivers 16a, 16b, and 16c which are connected thereto by respective signal lines 18a, 18b, and 18c. Each of the transceivers 16a-16c includes a controller driver 20 having an open collector output (i.e., NAND logic gate type 7438) and a receiving device 22 (i.e., Schmitt trigger input type 7414). When the controller driver 20 is turned off, the signal line (i.e., line 18a) is at a high or logic "1" level which has a voltage value of approximately +2.85 volts. When the controller driver 20 is turned on, the signal line is at a low or logic "0" level since the open collector output device will pull the voltage value on the signal line down to approximately zero volts (i.e., 0.2 volts through the driver transistor Q1). For example, the signal line 18a may be used for the control signal REQ, and the signal line 18b may be used for the control signal ACK.
In FIG. 2, there is shown another prior art termination network 10a. This alternative arrangement of FIG. 2 is sometimes referred to as a "110 regulated terminator." The termination network 10a includes a voltage regulator 24 for receiving the voltage TERMPWR on line Vin and for generating a regulated voltage on line Vout of approximately +2.85 volts with 110 ohms resistors to the respective 18 signal lines DB(0)-DB(7), DB(P), ATN, BSY, ACK, RST, MSG, SEL, C/D, REQ and I/O.
The principal unsolved problem of the prior art termination networks 10 or 10a was that neither one had the capability of raising the notch above the critical "double trigger" area (between +1.5 volts and +2.0 volts). As can be seen from the curve A of FIG. 5, the signal line in the 220/330 terminator has a notch N1 occurring at approximately +1.0 volts. Similarly, there is shown in the curve B of FIG. 5 that the signal line in the 110 regulated terminator has a notch N2 occurring at approximately +1.4 volts. Thus, these prior art termination networks did not teach how the notch could be raised above the critical area.
Further, it is also generally known that the voltage level of the notch is determined by the cable impedance and the amount of current present in the bus line 14a when it is released or deasserted by the respective controller driver 20. While the SCSI specification defines cable impedance to be "no less than 90 ohms," twisted pair or "round cable" impedance is seldom found to be greater than 90 ohms and may be as low as 45 ohms.
Even though these controller drivers 20 have the capability of sinking more current, a problem occurs referred to as "metal migration" when sinking high current over prolonged periods of time. This situation arises when the request control signal (REQ) is asserted, (low logic level) and the system fails to respond with the associated acknowledge control signal (ACK). In other words, the control signal REQ is being constantly asserted and does not deassert itself. Thus, this will cause the system to "hang" until the error is cleared up by deasserting the control signal REQ. If the unattended system hangs over an extended holiday weekend, this situation could last for many days without being corrected.
There is also known in the prior art of a terminator design which utilizes a diode clamping technique for raising the level of the notch by providing current in excess of the 24 mA. However, this prior art technique suffers from the disadvantage that this extra current is uncontrolled and may vary between 24 mA to 45 mA. Further, this extra current will be provided to the controller driver indefinitely when the system "hangs" and thus may result in the destruction of the costly controller driver.
Accordingly, there has arisen a need in the computer equipment industry for an improved terminator apparatus for raising the level of the notch occurring in the data and/or control signals on the SCSI bus line so as to provide reliable and accurate data transmission. Further, it would be expedient that the terminator apparatus be capable of being incorporated internally into conventional termination networks or can be connected externally to existing systems having conventional termination networks.

Signal line increased current kicker terminator apparatus


An imaging system includes a radiation source (108) configured to rotate about an examination region (106) and emit radiation that traverses the examination region. The imaging system further includes an array of radiation sensitive pixels (112) configured to detect radiation traversing the examination region and output a signal indicative of the detected radiation. The array of radiation sensitive pixels is disposed opposite the radiation source, across the examination region. The imaging system further includes a rigid flux filter device (130) disposed in the examination region between the radiation source and the radiation sensitive detector array of photon counting pixels. The rigid flux filter device is configured to filter the radiation traversing the examination region and incident thereon. The radiation leaving the rigid flux filter device has a predetermined flux.

A computed tomography scanner includes an x-ray tube that emits an x-ray beam. A portion of the x-ray beam traverses a subject or object located in a field of view of an examination region and is attenuated as a function of the radio density of the subject or object. Another sub-portion of the x-ray beam traverses the field of view of the examination region without traversing the subject or object. A detector array detects the radiation traversing the field of view and produces a signal indicative thereof. A reconstructor reconstructs the signal, producing volumetric image data.
A beam shaper has been positioned in the path of the x-ray beam between the x-ray tube and the examination region. The beam shaper has been referred to as a bowtie filter as its general physical shape resembles a bowtie. The beam shaper is shaped so as to attenuate the beam to a greater degree at a periphery of the beam. This makes the beam shaper well-suited for reducing the flux at the periphery in connection with direct conversion photon counting detectors, which suffer from insufficient count rate capabilities at the higher flux rates.
Unfortunately, for objects or portions of a subject (e.g., the extremities like the legs and arms) with no (or low) attenuating structure between attenuating structures (e.g., the space between the legs), the beam shaper is not well-suited for direct conversion photon counting detectors. This is because, for example, the beam shaper does not reduce the flux at this more central region enough. As a result, some centrally located detector elements of the detector array may receive and detect excessive flux, which can degrade image quality in the reconstructed volumetric image data.
This can be seen in FIG. 10 in connection with objects 1002 and 1004 separated by a gap 1006. In FIG. 10, an emitted beam 1008 is filtered by a beam shaper 1010, which is thicker at peripheral regions 1012 and thinner at a central region 1014, producing a filtered beam 1016, which is filtered to a greater degree at peripheral regions 1018 and to a lesser degree at a central region 1020. A region 1022 of a detector array 1024, which is proximate to the gap 1006, represents a region of a detector array 1024 which receives excessive flux.

X-ray flux reducer for a photon counting detector


A sense amplifier includes cross-coupled latch has a PMOS bias transistor for selectively connecting the cross-coupled latch to a supply voltage and has an NMOS bias transistor for selectively connecting the cross-coupled latch to ground potential. The conductivity of the PMOS bias transistor is controlled by a first bias signal having a magnitude dependent upon the supply voltage and, in a similar manner, the conductivity of the NMOS bias transistor is controlled by a second bias signal also having a magnitude dependent upon the supply voltage. When the supply voltage exceeds a predetermined level, the first and second bias signals are of respective magnitudes so as to slowly turn on the PMOS and NMOS bias signals. In this manner, the current flow is gradually increased to the sense circuit at high voltages, thereby minimizing noise and power consumption. When, on the other hand, the supply voltage drops below the predetermined level, the first and second bias signals are of respective magnitudes so as to rapidly turn on the PMOS and NMOS bias transistor potential. In this manner, current flow to the sense circuit is maximized at low supply voltages, thereby improving speeds at low supply voltages.

1. Field of Invention
This invention relates generally to memory arrays and specifically to sense amplifiers of a DRAM array.
2. Description of Related Art
Dynamic RAM (DRAM) constitutes the main memory of most personal computers and accounts for nearly 70% of the global semiconductor memory market. Since DRAM is less expensive and much slower than Static RAM (SRAM), system optimization requires a precise balance between DRAM's cost savings and DRAM's slower speeds. For example, while typical microprocessor speeds exceed 300 Mhz, DRAM speed is typically less than 100 Mhz. Thus, system optimization may be increased by increasing DRAM speed.
Further, DRAMs involve a tradeoff between supply voltage and speed. While higher supply voltages result in faster charging times, and thus greater DRAM speeds, fast charging times at high supply voltages result not only in increased power consumption but also in supply voltage fluctuations. These fluctuations in the supply voltage, in turn, may result in read speed fluctuation and even erroneous data interpretation. It is therefore desirable to compensate for these supply voltage fluctuations.
For example, a conventional DRAM 10 is shown in FIG. 1 as including a DRAM cell array 20 having a plurality of DRAM cells arranged in n+1 columns by m+1 rows. The cells in the DRAM array 20 are well known and are thus not shown in FIG. 1 for simplicity. The cells in a common row are coupled to an associated word line WL, and the cells in a common column are coupled to associated complementary bit lines BL and BL. A plurality of sense circuits 30 are coupled between respective pairs of the complementary bit lines BL and BL and a sense logic circuit 40. A PMOS bias transistor MP1 selectively couples the sense circuits 30 to V.sub.cc in response to an enable signal Pbias, and an NMOS bias transistor MN1 selectively couples the sense circuits 30 to ground potential in response to an enable signal Nbias.
Referring to FIG. 2, the sense circuits 30 include a cross coupled latch formed by two CMOS inverters connected between the bias transistors MN1 and MP1. The input terminal of the first CMOS inverter, which is formed by an NMOS transistor MN2 and a PMOS transistor MP2, is coupled to the output terminal of the second CMOS inverter, which is formed by an NMOS transistor MN3 and a PMOS transistor MP3, and to the bit line BL, i.e., node N1. The input terminal of the second CMOS inverter is coupled to the output terminal of the first CMOS inverter and to the complementary bit line BL, i.e., node N2.
The cells within the array 20 represent binary information by the presence or absence of charge therein. Thus, for instance, a cell within the array 20 represents a binary "1" when there is charge stored therein and, conversely, represents a binary "0" when there is no charge stored therein. Cells are selected for read operations in a well known manner using row address strobe (RAS) and column address strobe (CAS) signals. Specifically, the row address of a cell desired to be read is clocked into the DRAM 10 on the falling edge of the RAS signal. In response thereto, suitable row decoders (not shown) enable the word line WL corresponding to the received row address. Column addresses are clocked into the DRAM 10 on the falling edge of the CAS signal, thereby facilitating the latching of binary cell data from the selected row of cells into the sense circuits 30.
The sense circuits 30 are enabled on the falling edge of the RAS signal by driving signal Pbias to logic low, e.g., ground potential, and driving signal Nbias to logic high, e.g., V.sub.cc. The low Pbias signal turns on PMOS bias transistor MP1 and thereby couples the sources of PMOS transistors MP2 and MP3 to V.sub.cc, while the high Nbias signal turns on the NMOS bias transistor MN1 and thereby couples the sources of NMOS transistors MN2 and MN3 to ground potential. In order to avoid creating a short circuit between V.sub.cc and ground potential, signals Pbias and Nbias are not simultaneously enabled.
During read operations, a differential voltage develops across the complementary bit lines BL and BL associated with cells in the selected row. The polarity of this differential voltage depends upon the binary state of the cell, i.e., upon the presence or absence of charge therein. For instance, if a cell is charged, thereby representing a binary "1", its bit line BL is at a first voltage and its complementary bit line BL is at a second voltage, where the first voltage is greater than the threshold voltage of the CMOS inverters within the sense circuits 30 (V.sub.T), and the second voltage is less than V.sub.T. Conversely, if a cell is uncharged, thereby representing a binary "0", its bit line BL is at the second voltage and its complementary bit line BL is at the first voltage.
Once the sense circuits 30 are enabled, the differential voltage across the complementary bit line pairs BL and BL drives the cross-coupled latch within the associated sense circuit 30 to a corresponding binary state. For instance, if the selected cell is charged, i.e., representing a "1", the first voltage on the bit line BL turns on NMOS transistor MN2 and turns off PMOS transistor MP2, thereby driving node N2, and thus the complementary bit line BL, low to ground potential. The low potential at node N2, in turn, turns on PMOS transistor MP3 and turns off NMOS transistor MN3, thereby driving node N1, and thus the bit line BL, high to V.sub.cc. Conversely, if the selected cell is uncharged, the sense circuit 30 associated therewith drives the corresponding complementary bit lines BL and BL to ground potential and V.sub.cc, respectively.
The differential voltages developed across the complementary bit lines BL and BL via the sense circuits 30 are decoded and then sensed in a well known manner in the logic sense circuit 40 which, in turn, provides an output signal OUT indicative of the binary state of the selected DRAM cell.
As mentioned above, the sense circuits 30 are simultaneously enabled by turning on the PMOS bias transistor MP1 and then the NMOS bias transistor MN1. Since typical DRAM arrays typically include 1024 or more columns, simultaneously enabling 1024 or more of the sense circuits 30 sources large currents from the supply voltage V.sub.cc. These large currents sourced from V.sub.cc result not only in undesirable power consumption but also in unwanted noise. If sufficiently large, voltage supply noise may invalidate data and even damage associated logic.
Further, the current sourced to the sense circuits 30 may pull down the supply voltage V.sub.cc by as much as 20%. For instance, where V.sub.cc is a 3.0 volt supply, the simultaneous enabling of the sense circuits 30 may pull V.sub.cc down to 2.3 volts. Such fluctuations in V.sub.cc result in several problems, including data corruption, ground bounce, logic damage, junction breakdown, and so on.
In order to minimize supply voltage fluctuations resulting from enabling the sense circuits 30, additional PMOS bias transistors MP1(x) may be coupled between V.sub.cc and the sense circuits 30 and additional NMOS bias transistors MN1(x) may be coupled between ground potential and the sense circuits 30, as shown, for instance, in FIG. 3. Here, the bias transistors MP1(x) and MN1(x) are smaller in size, and thus current carrying capacity, than the respective bias transistors MP1 and MN1 shown in FIGS. 1 and 2. Further, buffer delays 32 are added in the Pbias and Nbias signal paths, as shown in FIG. 3, such that the bias transistors MP1(x) and MN1(x) are turned on in a sequential manner by respective signals Pbias and Nbias. In this manner, current sourced from V.sub.cc to the sense circuits 30 is gradually increased to a maximum value. As a result, power consumption and supply voltage noise resulting from current flow to the sense circuits 30 of FIG. 3 is reduced, as compared to that of FIG. 1.
However, replacing bias transistors MP1 and MN1 (FIG. 1) with numerous smaller respective bias transistors MP1(x) and MN1(x) (FIG. 3) undesirably degrades DRAM read speeds at low V.sub.cc. For instance, where V.sub.cc is 2.7 volts, each of the bias transistors MP1(x) of FIG. 3 charges the cross-coupled latches within the sense circuits 30 to only 2.7 volts, as compared to 4 volts when a 4 volt V.sub.cc is utilized. As a result, gradually increasing current sourced from V.sub.cc to sense circuits 30 at low V.sub.cc in the manner described above with respect to FIG. 3 requires longer charge times. Thus, although advantageously reducing power consumption and noise at high V.sub.cc, introducing delays into the Pbias and Nbias signal paths as illustrated in FIG. 3 will, at low V.sub.cc, undesirably limit DRAM read speed.


The pivoting stirrup system includes a foot support having a rear end, a front end, a first sidewall extending upwardly from a first side of the foot support and a second sidewall extending upwardly from a second side of the foot support, a first member pivotally connected to the first sidewall and a second member pivotally connected to the second sidewall. The first member and the second member are pivotally connected to a forward portion of the respective sidewalls. A first fastener extends through the first member and the first sidewall with a first bushing positioned upon the first fastener and a second fastener extends through the second member and the second sidewall with a second bushing positioned upon the second fastener.

1. Field of the Invention
The present invention relates generally to a stirrup and more specifically it relates to a pivoting stirrup system for increasing the comfort and safety for a rider.
2. Description of the Related Art
Any discussion of the related art throughout the specification should in no way be considered as an admission that such related art is widely known or forms part of common general knowledge in the field.
Saddles typically include a pair of stirrups for a rider of an animal (e.g. horse). The rider uses the stirrups for mounting the animal, support during riding and for dismounting the animal. Conventional stirrups are comprised of a foot support having a pair of support members extending upwardly from the foot support forming a U-shaped structure that is pivotally attached at an upper end to a strap that is attached to the saddle.
One of the problems with conventional stirrups is that the foot support is relatively narrow from front to back making them uncomfortable for riders over extended periods of time. Another problem is that the foot support of the stirrup itself does not pivot during mounting, riding or dismounting thereby making it difficult to mount and dismount along with uncomfortable for extended periods of riding since the foot support has little movement, if any, with respect to the support members that extend upwardly to the strap of the saddle. Another problem encountered by riders with conventional stirrups is that during dismounting the animal their foot may get caught in the stirrup since the foot support portion of the stirrup does not pivot resulting in physical harm to the rider particularly if the animal moves forwardly during the dismount.
Because of the inherent problems with the related art, there is a need for a new and improved pivoting stirrup system for increasing the comfort and safety for a rider.


A health monitoring system is disclosed. According to one embodiment, the health monitoring system includes a first server configured to receive a first set of information from a monitoring device, wherein the first set of information includes a health condition reading of a subscriber, and wherein the first server is configured to process the first set of information and transmit a second set of information to the monitoring device and/or a telecommunications device, wherein the second set of information includes medical treatment information and/or medical advice concerning the subscriber. The health monitoring system also includes a database in communication with the first server and configured to store a third set of information therein, wherein the third set of information includes emergency contact information, one or more health conditions of the subscriber, monitoring time intervals, and/or numerical ranges defining acceptable health conditions and medical alert conditions.

In the medical industry, it is common practice to utilize instruments and devices to monitor the health condition of patients. The health condition of a patient may be defined by measuring and recording a quantifiable parameter such as, for example, pulse, blood pressure, blood sugar, and cholesterol and then comparing the recorded measurement against a predefined range that a physician may establish for each patient. If the recorded measurement is within the predefined range, the patient's health may be considered satisfactory. In contrast, a recorded measurement that falls outside the predefined range may cause a physician to further explore the nonconforming reading and ultimately prescribe medical treatment.
Generally, the instruments and devices that are capable of monitoring a patient's health are located at doctors' offices, hospitals, or other medical facilities, and thus require patients to travel from their residence or workplace to monitor their particular health condition(s). However, many people such as, for example, elderly individuals, have health conditions that necessitate constant monitoring. In addition, the inconvenience and expense of doctor/hospital visits may also prevent individuals from monitoring their particular condition and thus prevent such individuals from maintaining good health.

Systems, methods, and devices for health monitoring


A method of cleaning metal surfaces by using a composition of citric acid, a hydroxycarboxylic acid salt, a nonionic surfactant and a coupling agent is used for cleaning metal surfaces and methods of using the same.

Cleaning treatments are employed in a variety of metal forming and coating processes. Cleaning operations remove oil and debris and precede conversion coating or other coating operations. Satisfactory treatment of such metals requires that any dirt and lubricants on the metals (from the forming, drawing and ironing operations) be removed. Both alkaline and acid cleaners are employed in the metal cleaning area.
In cleaning aluminum, both alkaline and acid cleaners provide effective cleaning, but present serious problems. Acid etching and cleaning with, for example, strong acids like sulfuric acid with hydrofluoric acid produce clean mirror bright surfaces. However, the use of acids for cleaning present safety and effluent disposal problems and also requires stainless steel equipment. For these reasons, alkaline cleaning and etching processes are favored in the aluminum processing industry. However, alkaline cleaners also produce effluent disposal problems.
An alkaline cleaning and etching process for aluminum is disclosed in U.S. Pat. No. 4,477,290 to Carroll et al. The low temperature alkaline cleaning and etching solution for aluminum disclosed comprises alkaline metal hydroxides and a chelating agent at temperatures of from 80 to 130.degree. F. No other ingredients such as wetting agents which would cause foaming problems are required.
U.S. Pat. No. 4,521,332 to Milora discloses a highly alkaline aqueous cleaning dispersion for strip steel which comprises sodium hydroxide, a bulking agent such as sodium carbonate and a poly(acrylic acid) dispersing agent.


A drive unit includes an engine and a transmission having a variable transmission ratio. An instantaneous setpoint power output quantity of the drive unit is determined from an intended power output. The setpoint power output quantity is a function of the instantaneous transmission ratio of the transmission at least for a given intended power output.

A drive unit having an engine and a transmission having a variable transmission ratio is present, for example, in today's typical motor vehicles. Transmissions having a plurality of driving positions, i.e., gears, are used as transmissions. The intended power output may be expressed, for example, by the angular position of a gas pedal and normally corresponds to an intended torque. The setpoint power output quantity may be the setpoint output torque of the drive unit which is to act upon the wheels of the motor vehicle. The actual output torque is generated by appropriate control and/or regulation on the basis of the setpoint output torque. It is understood that here and hereinafter the term "intended power output" means not only a desired power output or a desired torque, but also further quantities which affect the operation of the internal combustion engine.
In automatic transmissions, for reasons of comfort, it is desirable that, when shifting from one driving position or one gear to another without changing the intended power output, the output torque applied to the wheels of the motor vehicle is not also changed to avoid a "shifting jolt." German Published Patent Application No. 43 33 899, for example, describes a method for achieving this object. German Published Patent Application No. 42 04 401 also describes a method for avoiding the shifting jolt when shifting gears.
However, consistent implementation of this method in certain situations may result in more power being generated than necessary for operating the vehicle when the driver intends to stop the vehicle. The reason for this is that the minimum possible output torque of the drive unit varies abruptly from one gear to another. This minimum possible output torque—a braking torque in most operating situations of a motor vehicle—may therefore not be achieved if an abrupt torque jump is to be completely suppressed in shifting gears. In other words, after shifting, possibly more fuel is injected than absolutely necessary, even if the driver does not step on the gas pedal. To nevertheless brake the vehicle as desired, the driver would have to actuate the brake, which in turn increases its wear.


A door apparatus of a fixing unit includes a guide door hinged to one side of a frame of the fixing unit, so that the guide door can be opened horizontally, securing enough space for removing a jammed sheet. The frame comprises a plurality of bent plates formed at the one side thereof, each of the bent plates having a hinge hole, and the guide door comprises a plurality of extending plates formed at one side thereof, extending horizontally with respect to the bent plates, each of the extending plates having a hinge pin. The hinge pins are inserted into the hinge holes. Further, the door apparatus includes a U-shaped lock having a fixed end and a free end, formed on the opposite side of the guide door such that an outer side of the free end elastically contacts an inner face of the other side of the frame. Further, the door apparatus includes a catch formed at a specified portion of the free end, slanted so as to insert smoothly into a receiving hole formed at a corresponding portion of the another side of the frame, so that the catch is inserted into the receiving hole to lock the guide door to the frame.

1. Field of the Invention
The present invention relates to the class of devices for performing electrophotography, and more particularly, to the class of devices known as fixing units which are used in electrophotographic devices.
2. Description of the Related Art
Electrophotographic devices are widely used in applications such as photocopying, laser printing and facsimile printing. An electrophotographic image forming apparatus is composed of a sheet feeding unit for feeding recording sheets one by one, an image forming unit for forming an image on the fed sheet with a toner, a fixing unit for fixing the toner on the sheet, and a sheet discharging unit for discharging the sheet with the toner fixed thereon. Further, the fixing unit is composed of a heating roller for melting toner particles covering a latent image on the sheet and a pressure roller for pressing the melted toner particles on the sheet, rotating in contact with the heating roller. It is often necessary for the user to access the fixing unit, especially in the case of a jammed sheet.
In one example of a fixing unit, a guide door is positioned where the sheet exits the rollers to help guide the sheet from the rollers. The guide door is hinged to open to allow access to the rollers in the event of a jammed sheet. The hinge axis of the guide door is parallel to the axis of the heating and pressure rollers, and the guide door moves vertically relative to the rollers and the frame. Upon opening the guide door around its hinge axis, there is not enough space for the user to have full access to the rollers. Therefore, it might be difficult for the user to completely remove the pieces of the jammed sheet.
This general arrangement of a guide door opening vertically relative to the rollers is illustrated in fixing devices seen, for example, in the following U.S. Patents. U.S. Pat. No. 4,598,990, is to Kusumoto et al., entitled Toner Image Fixing Device, describes a toner fixing device which is hinged on a shaft member to lift the supporting frame holding the heating to fixing roller. In this device an entire portion of the frame must be lifted to access the rollers as the hinge axis is parallel to the rollers. U.S. Pat. No. 4,756,687, to Cabrera et al., entitled Roller Fuser Jam Clearance Mechanism, describes a fixing unit with a handle for moving a sheet guide from the rollers. All of the movement of the parts occurs along axes parallel to the rollers, and the rollers are not fully accessible when open.
U.S. Pat. No. 4,806,970, to Nakatomi et al., entitled Recording Apparatus Having An Accessible Housing, describes a laser printer having a fixing unit, where the entire upper cover of the printer, containing many components, is hinged parallel to the rollers and must be lifted to access the interior. This patent also shows an upper frame of the fixing unit, hinged along an axis parallel to the rollers, which is rotated up to access the fixing unit. Even when the upper frame of the fixing unit is rotated up, it still does not provide full access to the rollers. U.S. Pat. No. 4,965,640, to Watarai et al., entitled Image Forming Apparatus Including Detachable Toner Fixing Unit, describes a fixing unit in which the entire upper frame, hinged parallel to the rollers, is lifted to access the fixing unit. Opening the frame loosens the contact between the rollers, but actual access to the rollers is limited. U.S. Pat. No. 5,045,887, to Nakamura, Fixing Device With A Selectively Movable Cover, describes a fixing device with a cover which rotates vertically to separate the heating and pressure rollers. The cover is hinged parallel to the rollers and does not open so as to give full access to the rollers. U.S. Pat. No. 5,179,415, to Ikematsu et al., entitled Electro-Photographic Printing Apparatus Comprising A Toner Fixing Unit, describes a fixing unit in which a sub-frame containing the pressure roller rotates away from the frame containing the heating roller to allow removal of jammed sheets. The subframe has a hinge axis parallel to the axis of the rollers. This arrangement does not allow access to the rollers while the rollers are together, however.
Based on my observation of the art, then, I have discovered that what is needed is a guide door for a fixing unit which allows full access to the rollers of the unit, especially to remove jammed sheets. Specifically, what is needed is a guide door which does not open vertically with respect to the fixing unit, and which is easy to open and close.


The present disclosure refers to a plurality of process employed for optimization of Zero-PGM washcoat and overcoat loadings on metallic substrates. According to an embodiment a substantial increase in conversion of HC and CO may be achieved by optimizing the total washcoat and overcoat loadings of the catalyst. According to another embodiment, the present disclosure may provide solutions to determine the optimum total washcoat and overcoat loadings for minimizing washcoat adhesion loss. As a result, may increase the conversion of HC and CO from discharge of exhaust gases from internal combustion engines, optimizing performance of Zero-PGM catalyst systems.

1. Field of the Disclosure
The present disclosure relates generally to ZPGM catalytic systems, and more particularly to optimization of Zero-PGM washcoat, and overcoat loadings on metallic substrates.
2. Background Information
The behavior of catalyst systems may be controlled primarily by the properties of washcoat, and overcoat loadings. The catalyst materials produced by conventional methods may fail to provide a catalyst layer having good adhesion and cohesion properties. Another drawback may be achieving the proper adhesion of a washcoat to a substrate and/or adhesion of a washcoat to an overcoat. A plurality of factors may affect the adhesion of a washcoat to a substrate and/or of an overcoat to a washcoat, which may include, but are not limited to employing a suitable substrate dimension and cell density, washcoat and overcoat particle size, suitable formulation, and optimized loading of washcoat and overcoat.
For example, the washcoat adhesion, surface area, reactivity, porosity, thermal conductivity, and mechanical integrity of the washcoat at elevated temperatures may be considered. The washcoat and overcoat loadings processes employed by conventional methods, may fail to provide a catalyst layer, for producing good washcoat adhesion and cohesion properties. Therefore, there is a need to address these drawbacks, and other shortcomings associated with traditional catalyst materials and processes.
For the foregoing reasons, may be highly desirable to have a process for optimization of washcoat and overcoat loadings on metallic substrates, which may produce improvements for washcoat adhesion, and enhanced performance of HC and CO conversion for controlling exhaust emissions, achieving similar or better efficiency than existing oxidation catalysts systems.

Optimization of Zero-PGM washcoat and overcoat loadings on metallic substrate


To shield a frame area 203b, a frame-like shield member 501 is superimposed over an LCD 203 while being separated from the LCD 203 by a distance L. The distance L satisfiesL<2×(B−A)×f/D where f is a focal length of an optical system, D is a human pupil diameter determined statistically in advance, B is a width of the frame area, and A is a value determined statistically in advance as a width which will not be able to be shielded on a side of the frame area to be shielded by a side of the shield member.

1. Field of the Invention
The present invention relates to a head-mounted display which displays a video before the eyes of an observer.
2. Description of the Related Art
Recently, head-mounted video displays have been developed which enlarge video displayed on video display devices such as liquid crystal displays, display it before the eyes of an observer, and thereby allow the observer to watch large-screen video.
In a video display disclosed in Japanese Patent Laid-Open No. 11-174988, a pair of LCDs 3 corresponding to the left and right eyes of an observer are placed on the left and right inside an outer frame 2 of a device body 1 as shown in FIG. 6, where the LCDs 3 are two-dimensional video display devices. Backlights 4 are placed behind the respective LCDs 3 to illuminate the LCDs 3 and a pair of prisms 5 are placed below the LCDs 3 to project enlarged video from the LCDs 3 to both eyes E. The video displayed on the LCDs 3 is projected to both eyes E of the observer M along respective observation optical axes L and projected in front of both eyes E by being enlarged when passing through the prisms 5.
To provide a wide viewing angle to the observer, it is necessary to increase magnification of the prism. However, increases in the magnification of the prism make it difficult to maintain optical performance, resulting in marked chromatic aberration, field curvature, and other optical aberrations. Attempts to correct such aberrations properly result in a complicated, bulky optical system, making it difficult to mount the video display properly on the observer.
To deal with such situations, As being disclosed in Japanese Patent Laid-Open No. 5-127660, a technique, for adding distortion to video data before display by processing a video signal to be displayed so that the distortion will be cancelled out after passage through an optical system, is disclosed.
Also, an example disclosed in Japanese Patent Laid-Open No. 8-149393 proposes a configuration for displaying a black frame in peripheral portions to cancel out distortion in shape even though no distortion is added to video to be displayed.
Although this configuration does not eliminate distortion in the displayed video, four sides of the peripheral frame appear to be straight and four corners appear to be square, reducing a sense of image distortion felt by the observer.
Also, Japanese Patent Laid-Open No. 2004-268638 discloses a configuration for a vehicle-mounted video display which projects video onto a front window of a vehicle, wherein frame members are arranged in such a way as to cancel out distortion caused by the front window. Also, with this configuration, although the displayed video remains distorted, four sides of the frame appear to be straight and four corners appear to be square, reducing a sense of image distortion felt by the observer.
However, with the technique disclosed in Japanese Patent Laid-Open No. 5-127660, video distorted by the optical system is observed outside a video-display area. Thus, the technique has a problem in that edges of the video-display area are distorted, resulting in degradation of video quality.
Also, the technique disclosed in Japanese Patent Laid-Open No. 8-149393, has a problem in that a corrective frame shape is displayed in the peripheral portions, reducing the number of display elements actually used for the video, which in turn results in low video resolution.
Also, the technique disclosed in Japanese Patent Laid-Open No. 2004-268638 presents a cost problem because frame members must be shaped to fit the front window of the vehicle on which the frame members are mounted, making it necessary to prepare multiple shapes.
On the other hand, if a visual field other than the video observed by the observer is darkened, the observer can view the video standing out in the visual field as if on a screen of a movie theater, increasing the quality of the observed video.
To provide such video, Japanese Patent No. 3485689 discloses a method for placing a viewing frame in front of a video display device to allow the observer to view video standing out in the visual field fitted entirely in a black frame as if on a screen of a movie theater.
However, with the technique disclosed in Japanese Patent No. 3485689, an aperture of the viewing frame is smaller than an effective display area of the liquid crystal display element, and consequently part of the video displayed on the liquid crystal display element is hidden by the viewing frame. With a configuration in which part of displayed video is hidden by the viewing frame in this way, the entire video is not shown to the observer. Take, for example, a PC monitor screen or the like; there can be a problem if part of video is not displayed. Also, Japanese Patent Laid-Open No. 5-127660 mentions nothing about positioning of viewing frames on the left and right display devices, and thus presents a problem of discrepancy between left and right video display areas.

Head-mounted display and head-mounted video display


A system and a method using that system is provided for establishing a secure communication channel between a vehicle and a mobile device. The method may include providing at least one unique mobile device identifier and at least one unique vehicle telematics unit identifier associated with the mobile device identifier to a call center. At least one of the two identifiers may be provided to a wireless service provider. Two private keys may be generated—a first private key based on the at least one unique mobile identifier and a second private key based on the at least one unique vehicle telematics unit identifier. The first private key may be provided to the mobile device within a first cryptographic envelope signed with a first cryptographic key. And the second private key may be provided to the vehicle telematics unit within a second cryptographic envelope signed with a second cryptographic key.

Transport Layer Security (TLS) is a known technology used in digital networks to establish and carry out secure communication between two entities. The communicating entities can be devices such as computers or other electronic apparatuses capable of digital communication, and the two entities may be communicating as peers or in a client/server configuration. TLS is implemented using digital certificates which, through public key cryptography (i.e., using public key infrastructure, PKI) and a common trusted entity, enable one or both of the communicating entities to authenticate the other and enable the two entities to exchange information confidentially. Secure Socket Layers (SSL) is an earlier form or predecessor of TLS that has been widely used over the Internet.
TLS is commonly used in TCP/IP networks using X.509 digital certificates which are typically issued by a trusted third party certificate authority (CA) and signed with the CA's private key. The holder (subject) of the certificate can then use it to authenticate itself to other entities. The associated CA public key is distributed to those entities as a part of a self-signed certificate. Authentication of a received digital certificate then involves using the CA's public key to decrypt the digital signature and compare the result to the contents actually contained in the certificate. More specifically, when the certificate is originally signed, a hash is performed of the certificate's contents and the result is encrypted using the CA's private key. This encrypted result is used as the digital signature and is appended to the certificate. Then, to authenticate, a recipient of the certificate uses the public key to decrypt the hash, and then compares this decrypted hash result with its own hash of the received certificate data items that it takes using the same hash function. If the two results match, then this indicates that the contents of the certificate are authentic. That authenticated content includes the certificate holder's (subject's) identity and public key so that the recipient of the certificate can now know that the identity is authentic and can communicate confidentially with the subject using its public key.

Securing a command path between a vehicle and personal wireless device


A recording device is disclosed which has a push switch and no display. A menu item is sequentially changed out of a plurality of menu items, which are arranged in a specific order, by operating the push switch. Sub-pluralities of menu items are sequentially skipped based on the continuous operation of the push switch to quickly arrive at a desired menu item, without the need to select each and every menu item in sequential order.

The present invention relates to a recording device that has an operating unit, and to a control method for this recording device.
Recording devices that are controlled using a hierarchical menu structure are known from the literature. See, for example, Japanese Unexamined Patent Appl. Pub. JP-A-2006-91987. The recording device described in JP-A-2006-91987 has an LCD or other type of display, and operating switches including input buttons, key switches, and cursor keys. The user uses the operating switches to change the selected menu item, and confirms the selected menu item on the display device.
There is a need to improve the operability of the operating switches of a recording device such as described above in which various operations are selected by manipulating an operating switch.