The present invention relates to a decorative belt loop pin for the decorating of an article of clothing and for the securement of a belt to an article of clothing. The belt loop pin comprises a rectangularly shaped frame having a central internal opening of rectangular shape. A front member is arranged to receive a decorative panel thereon. A rear member has an upper end and a lower end, the upper end having an upper standoff thereon, the lower end having a lower standoff thereon. The upper standoff has an elongated securement pin hingedly attached thereto. The lower standoff has a securement grasping member thereon. The internal opening of the rectangular frame crtically has a minimum length of about one inch, and a minimum width of about at least three-eighths of an inch, to permit a belt to be readily passed therethrough.

1. Field of the Invention
This invention relates to functional jewelry and more particularly to a decorative pin which functions as a belt loop.
2. Prior Art
Current customs of dress and clothing often omit belt loops on slacks, pants, and skirts or dresses. It may be desirable to add a number of belt loops on any of those articles of clothing, or to be able to adjust them as necessary. Those articles of clothing which do have belt loops, may have their belt loops which are too loose, or they may break.
It is an object of the present invention however, to provide a decorative belt loop pin, which may be utilized on an article of clothing at the discretion of the wearer.
It is an object of the present invention, to provide a decorative belt loop pin, which will readily accommodate most typical belts without jamming or breaking.
It is yet a further object of the present invention, in one embodiment thereof, to provide a belt loop pin which is flexible so as to flex or yield with the width of the belt, when the wearer is bending or moving.
It is still yet a further object of the present invention, to provide a belt loop pin which will not dig into the sides of the wearer or make the wearer uncomfortable.


A three-dimensional strategy game is formed of four circular discs supported in vertically spaced apart relationship by peripherally spaced vertical posts. Each disc is provided with four concentric bands, and a plurality of station detents are located in each band on radial lines disposed 90.degree. apart. The detents are configured to seat game piece balls, and the posts are formed of hollow tubes configured to receive the balls for storage. A side opening at the bottom of each tube allows removal of the bottommost ball for play. The method of play is to place game piece balls in detents on one or more of the four discs to form a sequence of straight lines, circles or spirals, with the player producing or discovering a sequence being the winner of the game.

This invention relates to strategy games, and more particularly to a three-dimensional game which enables a plurality of players to devise strategies to arrange a plurality of game pieces in any one of a variety of sequence patterns on one or more levels of the game.
Three-dimensional games have been provided heretofore. Typical of these are the games disclosed in U.S. Pat. Nos. 4,883,278; 4,204,685; 4,184,685; 3,884,474; and 3,464,701. None of these patents provides the structural arrangement by which this invention affords the variety of sequence patterns by which the game is successfully played.


According to the present invention, an adaptive and efficient MAC protocol for wireless access to an ATM network is capable of supporting any type of ATM service class with associated Quality of Services parameters. An ATM cell-switched architecture is utilized in which several ATM Mobile Terminals within a given geographic cell (small cells covering a range of several tens of meters) communicate with an ATM Access Point using radio frequency channels, which is connected to an infrastructure ATM network by the means of conventional ATM links. Mobile Terminals can operate both indoor and outdoor with limited range and have wireless access to the Access Points on the ATM network.

Recently the ATM and wireless technologies have gained a high visibility as they provide efficient and economical answers to requirements raised by new telecommunication services and by new end-user behaviors.
ATM has been recognized as the common base on which different types of services an ATM network can provide. The ATM technology can efficiently combine the transmission of speech, video, hi-fi sound (what is commonly called the multimedia traffic) and computer data into the wired network. Furthermore ATM has proven to scale well from very high speed network infrastructure (the information highways) to customer premises networks. One of the great advantages of the ATM technology is the fact that it can guarantee some level of service when an ATM connection is set up. Such guarantees can correspond to transmission rate, transmission latency and information loss. Such guarantees can be achieved mainly because the ATM architecture assumes that the transmission media are almost error free.
Wireless technology is currently becoming more and more successful as it allows mobile end-users to remain connected to their network and applications while being freed from a wired attachment. Different approaches are currently proposed for wireless communications: they differentiate by the services and the coverage they provide. Wireless Wide Area Networks (WAN) like the so-called GSM provide nation-wide coverage to the end-user, with modem equivalent transmission speeds. Wireless Data Packet networks provide nation-wide coverage to the end-user, with the so-called X.25 like transmission services. Finally Wireless Local Area Networks (LAN) provide establishment wide coverage with conventional LAN (e.g. Ethernet) equivalent communication services.
The combination of Wireless transmission with ATM technology is a new trend whose objective is to take advantage of both technologies, and for example to allow a mobile user to access an ATM network infrastructure while taking full advantage of all the facilities available with wired access to the ATM network. Since the main characteristics of each technology are very different, even incompatible, such a combination raises technical problems, as described hereinafter.
ATM technology characteristics
The ATM technology, as currently defined by standardization bodies such as the ATM Forum, and as currently implemented by commercial products, is characterized by the following main aspects:
1) Very short data granularity: in ATM network, all the traffic is carried within so-called ATM cells corresponding to a 53 bytes long structure made of a header field (5 bytes) and a payload field (48 data-bytes). PA1 2) The ATM cells are used either for control and signaling traffic or for information bearer traffic. Full duplex (FDX) links: on each ATM port, it is possible to simultaneously receive and transmit information. PA1 3) Point-to-point links: the media on which ATM cells are transmitted can only connect a pair of ATM stations. Although some ATM concentrator products can give the appearance of multidrop link, the ATM links have a point-to-point topology. PA1 4) Almost error free transmission: the transmission technologies currently used in ATM networks (e.g. over fiber or cable) provide typical bit error rate (BER) below 10.sup.-9. This capability is the main reason for permitting error recovery mechanisms within the ATM end stations and not within the ATM network.
In addition to these aspects, the ATM architecture further introduces the concept of ATM Service Class traffic parameters including Quality of Service (QoS) parameters to allow specifying, at ATM connection set-up, a traffic contract between the ATM end-point and the ATM network. These concepts formalize the characteristics of the user traffic so that each element of the ATM network involved in the end-to-end ATM connection may on one side reserve the necessary resources to provide the required service, and on the other side behave accordingly to the traffic contract. These concepts are summarized in the following table.
TABLE 1 __________________________________________________________________________ ATM Layer Services Categories Attribute CBR rt-VBR nrt-VBR ABR UBR Parameter __________________________________________________________________________ CLR Specified Specified Specified Specified Unspecified QoS peak-to-peak CDV Specified Specified Unspecified Unspecified Unspecified QoS Mean CTD Unspecified Unspecified Specified Unspecified Unspecified QoS Max. CTD Specified Specified Unspecified Unspecified Unspecified QoS PCR and CDVT Specified Specified Specified Specified Specified Traffic SCR and BT N/A Specified Specified N/A N/A Traffic MCR N/A N/A N/A Specified N/A Traffic Flow Control No No No Yes No __________________________________________________________________________ CBR: Constant Bit Rate rtVBR: real time Variable Bit Rate nrtVBR: non real time Variable Bit Rate ABR: Available Bit Rate UBR: Unspecified Bit Rate CLR: Cell Loss Rate CDV: Cell Delay Variation CTD: Cell Transfer Delay PCR: Peak Cell Rate CDVT: Cell Delay Variation Tolerance SCR: Sustainable Cell Rate BT: Burst Tolerance MCR: Minimum Cell Rate N/A: Not applicable
Finally, the channel should at least provide a capacity of 20 to 25 Mbps, in order to meet the throughput requirements of expected ATM applications. IBM Publication GG24-43300-00 entitled `Asynchronous Transfer Mode, Technical Overview` presents a broad overview of the ATM concept and details the ATM technology characteristics.
Wireless technology characteristics
The wireless transmissions are characterized by the following main aspects:
1) Poor efficiency to transmit short packets: before transmission of any piece of data over a radio channel, the transmitter must first issue a so-called Physical header which typically correspond to a significant portion of the bandwidth. In order to decrease the associated overhead, the piece of data which is transmitted next must be sufficiently large. For instance with conventional WLAN products, a frame of 1500 bytes (or more) follows the physical header.
2) Half Duplex (HDX) links: the only way to allow FDX operation over a radio channel is first to duplicate the radio modem transceiver (one part dedicated to transmission, the other to reception), and second to split by some means the frequency band into two sub-bands, each of them being used for a one-way transmission. Such an approach is quite expensive and also raises some technical difficulties such as the saturation of the receiving antenna by the emitting one. As a result the only technically and economically viable approach is to rely on a single radio transceiver piece of hardware, and to use the radio channel in HDX mode.
3) Broadcast transmission: the nature of the electromagnetic waves transmission is such that any receiver within range of a transmitter beam can get enough energy to receive information sent by the transmitter. Thus the wireless channel topology must be seen as point-to-multipoint. The use of directional antennas may reduce the reception area and thus the population of potential receivers, but it prevents any mobility of wireless stations. This last limitation is unacceptable for a wireless ATM network aimed to provide mobility support to mobile end-users. As a result, the wireless radio channel must be seen as a multidrop link.
4) High error rate: wireless transmission channels are characterized by poor quality figures. Typically the bit error rates observed on such wireless channels may be as bad as 10.sup.-3 or 10.sup.-4 : they are by far higher than what is assumed by ATM networks.
The `Mobile Communications Handbook` by Jerry D. Gibson, CRC IEEE Press, 1996, ISBN 0-8493-8573-3, gives an extensive description of the wireless technology. From the aforementioned points, it clearly appears that the wireless and ATM technologies significantly differ on important transmission characteristics which are resumed hereafter:
1) The ATM cells are so short that they would induce poor transmission efficiency if they were sent individually over the radio channel, as it is performed over conventional ATM transmission media. Radio transmissions cannot economically provide Full Duplex transmissions which are commonly used on ATM networks.
2) The topology of radio transmissions are not equivalent to the ones found in ATM networks.
3) The bit error rates observed over radio channels are by far worse that the ones assumed by the ATM architecture.
Some known techniques intend to address the technical challenges previously introduced, and may fill the gap between the wireless and the ATM technologies.
A first solution based on high speed point-to-point radio links may meet the requirements of a Wireless ATM network in terms of channel capacity, but cannot provide a satisfying answer to other needs. The main limitation is the point-to-point topology preventing wireless end-user to be mobile. In addition, the scheduling policies commonly used on such radio links have not been built to meet the QoS requirements of ATM connections.
Others solutions based on the conventional WLAN techniques are to some extent in line with some requirements of wireless access to an ATM network, but cannot address all of them. As far as the channel capacity is concerned, some techniques, as the one developed by the ETSI RES 10 , committee (the so-called HIPERLAN standard) provide a throughput which may be sufficient for some ATM scenarios. Concerning the channel topology and usage (FDX vs HDX), the U.S. Pat. No.: 5,384,777 to Ahmadi et al provides some techniques for defining a Wireless ATM network, but this solution suffers from important limitations. The most important one is the fact that the used traffic scheduling policy gives a solution to the support of conventional LAN traffic, but cannot guarantee at all the QoS requirements imposed by any type of ATM traffic. In addition to this limitation, the design point of traditional wireless LAN products is optimized for conventional LAN traffic based on large packets: 1.5 Kbytes or more) and therefore presents very poor efficiency figures if packets are replaced by ATM cells.
Therefore, it appears that the conventional wireless LAN technology does not fulfil the requirements of a wireless access to an ATM network.
Accordingly, it would be desirable to be able to provide a method capable of supporting any type of ATM service class with associated QoS parameters in a communication system providing a wireless access to an ATM network.
Furthermore, it would be desirable to be able to provide a system coordinating and optimizing the wireless channel bandwidth which is shared by all Mobile Terminals within a cell in a fair, flexible and ATM compatible manner and to achieve a high throughput.

Method and apparatus for providing wireless access to an ATM network


The wireless anti-lockout system automatically unlocks a driver's side door when the driver locks the car keys within the car. The anti-lockout system includes door-lock and trunk-lock sensors, a key chain transponder, transponder sensors and an occupant presence sensor. When the doors and trunk are locked, the key chain transponder is detected in the car, and an occupant is not detected, signals are sent to a microprocessor, which alerts a door lock control to unlock the driver's side door and activates an alarm. Additional sensors may be added. The system may include a transmission sensor and a driver detection sensor, so that when a driver is not detected, or when the transmission gear is in park or neutral, in addition to the other three signal conditions, the door lock control unlocks the driver's side door and an alarm is activated.

1. Field of the Invention
The present invention relates to automobile lockout protection devices, and particularly to a wireless anti-lockout system that prevents drivers from locking their keys in their vehicles.
2. Description of the Related Art
Multiple systems for preventing keys from being locked in a car exist to alert the driver to the condition. Alarms or horns have been used to alert the driver that a key has been left in the ignition, and some systems allow the doors of the automobile to be unlocked.
While many of these systems provide an alarm or unlock the door if the key is left in the ignition or left in the car when the doors are locked, many systems do not protect against the unnecessary opening of the car doors or activation of an alarm. These systems do not, however, determine a number of things, such as whether the doors are locked, the occupant is in the car and the keys are anywhere in the car. Additional safety features, such as whether a driver is located in the automobile or if the transmission is out of park or neutral, are not included. It would be desirable to have a system that determines if anyone is in the car, if the keys are located anywhere in the car, if a driver is detected, and if the transmission is out of park or neutral.
Thus, a wireless anti-key locking device solving the aforementioned problems is desired.


A semiconductor device comprising a graphene layer, a graphene oxide layer overlaying the graphene layer, and a high-k dielectric layer overlaying the graphene oxide layer is provided, as well as a method for producing the same. The method results in a graphene chemical functionalization that efficiently and uniformly seeds ALD growth, preserves the underlying graphene structure, and achieves desirable dielectric properties such as low leakage current and high capacitance.

An important step in the development of top-gated graphene-based field-effect transistors (FETs) is the growth of high dielectric constant (high-k) materials to act as the gate insulator. For optimal performance, these dielectric thin films should be ultrathin, conformal, and pinhole-free with minimal disorder or traps at the dielectric graphene interface. A very suitable method for controlled deposition of ultrathin homogeneous films is Atomic Layer Deposition (ALD). However, ALD of thin films on graphene is not easy because there is no surface functional group or defect on the inert graphene surface, which are needed for chemical surface reactions the conventional ALD processes are based on.
Several surface treatment methods have been pursued so far to improve the uniformity of gate dielectric growth on graphene by atomic layer deposition (ALD), including the deposition and oxidation of metal films (Fallahazad, B.; Kim, S.; Colombo, L.; Tutuc, E., Dielectric thickness dependence of carrier mobility in graphene with HfO2 top dielectric. Appl Phys Lett 2010, 97 (12)), functionalization of graphene via ozone (Lee, B. K.; Park, S. Y.; Kim, H. C.; Cho, K.; Vogel, E. M.; Kim, M. J.; Wallace, R. M.; Kim, J. Y., Conformal Al2O3 dielectric layer deposited by atomic layer deposition for graphene-based nanoelectronics. Appl Phys Lett 2008, 92 (20)), and the spin-coating of polymer films as seeding layers (Farmer, D. B.; Chiu, H. Y.; Lin, Y. M.; Jenkins, K. A.; Xia, F. N.; Avouris, P., Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors. Nano Lett 2009, 9 (12), 4474-4478). Although these methods possess advantages compared to ALD dielectric deposition directly on pristine graphene, important issues remain unresolved. For example, graphene surface pretreatments that involve an oxidizing treatment generally lead to surface damage of the graphene and degradation of its electronic properties. Furthermore, polymer and oxidized metal seeding layers decrease the total capacitance of the gate dielectric layer due to increased gate thickness and a reduced effective k-value.

Katholieke Universiteit Leuven, K.U.LEUVEN R&D


A sampling circuit for testing an integrated circuit receives several signals from points of interest in the integrated circuit, digitizes them, and determines whether the digitized signal is above or below a threshold. By sampling the signal at different phases of a system clock signal, a determination can be made of when during the system clock signal the signal at a point of interest changed state. Circuits are provided for making minimal impact on the circuit being observed. Circuits are also provided for clocking the observed signal so that it can be compared to other observed signals.

When new integrated circuit chips are being developed and tested, it is desirable to access internal nodes within the chip for measuring voltages, observing waveforms, or observing delays at the nodes. In the past, when internal features were larger, it was possible to place a probe on any internal node and measure the voltage or waveform. But with significant shrinkage, internal probing of a line within the integrated circuit is no longer possible, so probe pads are needed. And with the increase of complexity, there are many places to probe and it is not practical to place probe pads everywhere you want to observe a signal. E-beam probing of internal nodes is also possible, but expensive and time-consuming, so most circuits, at least in test chips, are designed to include circuits to bring one of several signals to a probe pad for observation.
Sample and Hold
For testing periodic signals, sampling oscilloscopes can illustrate the waveform of a periodic signal by taking successive samples from different parts of successive cycles of the periodic signal to generate and display a composite graph to illustrate the waveform. The paper "Applications of On-Chip Samplers for Test and Measurement of Integrated Circuits" by Ron Ho, Bharadwaj Amrutur, Ken Mai, Bennett Wilburn, Toshihiko Mori, and Mark Horowitz, Stanford University, ©1998 IEEE, describes a system that includes a circuit inside the chip to iteratively look at a selected point in the chip over successive cycles, sampling later and later points of the cycle in successive cycles, and putting that sampled signal on an oscilloscope to see the waveform. This method shows noise coupling or other glitches, and is thus ideal for looking at the particular internal point in the chip. But it requires taking many sample points, and manually observing an oscilloscope, and thus it is a time consuming method. Also, as signals and clocks get faster and faster, the difference between the signal clock and sample clock must get smaller and smaller. To accurately represent the rise time of, say, 10 picoseconds in a 1 nanosecond signal cycle will require on the order of 1000 samples to give 1 picosecond resolution. So if the signal clock is 1 gigahertz, the sample clock may need to be 1.001 gigahertz to give the 1000 samples. And this is difficult to achieve, requiring expensive frequency control. Also, it requires human manipulation. This method can not be implemented automatically by a tester computer. It would be desirable to use a testing method that could be implemented automatically by a tester computer, and would not require elaborate circuitry within the chip to produce accurate results.


Implementations of the disclosure provide for secret keys management in a virtualized data-center. In one implementation, a system is provided. The system comprises a memory to store secret key data and a processing device coupled to the memory. The processing device is to identify authentication information provided by a user, the authentication information comprising access information associated with a data storage domain, receive a secret key to access the data storage domain in view of the authentication information, wherein the secret key comprises a universally unique identifier (UUID), and register the secret key, wherein to register the secret key, the processing device to store a data structure in volatile memory indicating an association between the UUID of the secret key and the hypervisor.

The virtualization of a data center results in an abstraction of a physical system to consolidate the data center infrastructure and increase operational efficiencies. A virtual machine (VM) may be a software-based emulation of computer hardware. For example, the VM may operate based on computer architecture and functions of computer hardware resources associated with hard disks or other such memory.

Secret keys management in a virtualized data-center


A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

Demands for increased performance and complexity for integrated circuits have led to the circuits including both CMOS transistors for high packing density and bipolar transistors for high power and speed. Such BiCMOS circuits provide particular advantages for mixed mode (analog plus digital) integrated circuits which can combine the low noise characteristics of bipolar transistors in analog subcircuits and still use well known CMOS digital subcircuits. See for example, R. Haken et al, "BiCMOS Processes for Digital and Analog Devices," Semiconductor International 96 (June 1989).
However, analog circuits typically will operate with both positive and negative power supplies and at higher voltages than the single power supply digital circuit. For example, digital CMOS circuits typically operate between 0 and +5 volts, whereas analog circuits may operate with -5 volts, +5 volts. Further, analog circuits benefit from the use of CMOS transistors in addition to bipolar transistors; thus a mixed mode BiCMOS circuit may have CMOS transistors operating between 0 and +5 volts plus other CMOS transistors operating between -5 and +5 volts. But to achieve maximum performance from the digital (low voltage) NMOS transistors the source and drain implant doses are maximized to the extent where hot electron failures begin to appear. And using the same source and drain implant doses for the analog (high voltage) NMOS transistors will result in failure due to the higher operating voltages of the analog transistors. Thus there is a problem of a tradeoff between digital NMOS transistor performance and analog NMOS transistor performance in BiCMOS integrated circuits.
In BiCMOS processes the photomask count is typically high, and increasing the number of photomasks to obtain additional devices is only used as a last resort. Thus for a BiCMOS process which provides both NPN and PNP transistors, the implant to form the base of the PNP transistors seems to be a candidate for simultaneous formation of the source and drain (or just drain in the asymmetrical case) of the high voltage NMOS transistors because the implant dose for base is most similar to that used in a lightly doped drain of a high voltage NMOS transistor. However, to achieve a PNP transistor of reasonable performance, the base implant must be of fairly high energy to provide a satisfactory base width due to the encroachment of the faster diffusing boron dopants forming the P+emitter. But if upwards of 1 MeV energy for the base implant is not available, then a higher dose must be used. Then the high voltage NMOS transistor becomes prone to hot electron degradation as well as low snapback holding voltage.
The present invention provides BiCMOS processes and devices with low voltage and high voltage NMOS transistors having differing drain (and source) dopings but without an additional photomask. Rather, the high voltage NMOS transistors have a compensated lightly doped drain formed by use of both the NPN transistor base implant and the PNP transistor base implant. Because a boron implant can be deeper and diffuse more quickly, it is generally true that the NPN base implant dose will be less than but of the same order of magnitude as the PNP base implant dose. The combination of the two base implants yields a drain (and source) which is N type and more lightly doped than the PNP base alone. Hence, such high voltage NMOS transistors should have greater hot electron immunity and snapback holding voltage. Ohmic contact to the lightly doped drain (and source) may be by use of the low voltage NMOS transistor source/drain implant or the NPN transistor emitter implant and offset from the high voltage NMOS transistor gate.


The exemplary embodiments disclose a system and method, a computer program product, and a computer system for naming a digital file. The exemplary embodiments may include detecting a user saving an unnamed digital file to a digital folder, extracting one or more first features from data collected from one or more named digital files within the digital folder, generating one or more models correlating the extracted one or more first features with one or more names of the one or more named digital files, extracting one or more second features from the unnamed digital file, and determining a name for the unnamed digital file based on applying the one or more models to the extracted one or more second features.

The exemplary embodiments relate generally to digital files, and more particularly to naming digital files based on data.
It can be very difficult for a person to individually name multiple digital files. It can also be very difficult for the person to implement consistent naming nomenclature across a large number of digital files. The person may need to consider a lot of information about the digital files in naming them appropriately based on a naming nomenclature.

International Business Machines Corporation


A heat exchanger tube for effecting a heat exchange between a fluid inside the heat exchanger tube and another fluid flowing outside the heat exchanger tube, which is provided with a first kind of spiral grooves and a second kind of spiral grooves, each being formed on an outer surface of the heat exchanger tube. The twisting direction of the first kind of spiral grooves in relative to the axis of the heat exchanger tube is the same as that of the second kind of spiral grooves but differs in helix angle from each other with helix angles of the first kind of spiral grooves and the second kind of spiral grooves falling within the range of 3.degree. to 80.degree. in relative to the axis of the heat exchanger tube.

This invention relates to a heat exchanger tube which can be employed in an absorber, regenerator or evaporator of an absorption refrigerator for producing cold water or of an absorption heat pump for air-conditioner. This invention also relates to a method of manufacturing such a heat exchanger.
The absorber of an absorption refrigerator or of an absorption heat pump for air-conditioner is generally composed of many a number of heat exchanger tubes which are horizontally arranged in rows and in multistage. This group of heat exchanger tubes are adapted to be sprayed from the top thereof with an absorption liquid such as an aqueous solution of lithium bromide.
During the time this sprayed absorption liquid flows down along the outer surfaces of the heat exchanger tubes, the vapor of refrigerant generated from an evaporator is absorbed by the absorption liquid and at the same time the heat generated in the absorption reaction is transferred through heat exchange to a cooling water flowing in the heat exchanger tubes. Therefore, it is imperative for improving the performance of the absorber to promote the phenomenon of mass transfer in this process of absorbing the vapor of refrigerant.
At the moment when an aqueous solution of lithium bromide absorbs the vapor of refrigerant, a mass transfer as shown in FIG. 1 takes place at an interface between the absorption liquid A and the refrigerant vapor B. Namely, at the surface layer Aa of the absorption liquid A, i.e. at the interface layer between the absorption liquid A and the refrigerant vapor B, the concentration of the absorption liquid A becomes thinner as compared with that of inner layer Ab of the absorption liquid A which is close to the surface of the heat exchanger tube C. Accordingly, if the absorption of the refrigerant vapor B is to be promoted, the turbulence of the absorption liquid A on the heat exchanger tube C is required.
Because of this, in case of the absorption refrigerator or the absorption heat pump for air-conditioner which is actually used now by making use of an aqueous solution of lithium bromide, a surfactant such as n-octyl alcohol or 2-ethyl-1-hexanol is added at a concentration of several tens to several hundreds ppm to an aqueous solution of lithium bromide so as to cause a turbulence action (which is called Marangoni convection) in the absorption liquid in the aforementioned process of refrigerant vapor absorption. Namely, a method of improving the refrigerant vapor absorption capacity of the absorption liquid by making the most of this Marangoni convection is generally adopted now.
Accordingly, it is now desired, in view of improving the performance of the heat exchanger tube of an absorber, to effectively promote the turbulence by way of Marangoni convection of an absorption liquid layer on the outer surface of the heat exchanger tube, which would be generated as mentioned above as the absorption liquid absorbs the refrigerant vapor.
A heat exchanger tube which is designed to promote the turbulent action in the absorption liquid has been proposed by Japanese Utility Model Unexamined Publication S/57-100161. The heat exchanger tube disclosed in this Japanese Utility Model Unexamined Publication S/57-100161 is worked such that fine spiral grooves are formed on the outer surface thereof. The purpose of providing the spiral grooves is to allow an absorption liquid to flow along the spiral grooves so as to spread the flow of the absorption liquid on the surface of the heat exchanger tube and at the same time to promote the turbulence in the absorption liquid layer by the irregular surface which has been effected by these spiral grooves.
Another example of heat exchanger tube which is also designed to promote the turbulent action in the absorption liquid has been proposed by Japanese Utility Model Unexamined Publication S/64-35368. The heat exchanger tube disclosed in this Japanese Utility Model Unexamined Publication S/64-35368 is provided on the outer surface thereof with fine spiral grooves, i.e. a first kind of spiral grooves and a second kind of spiral grooves twisted in a direction opposite to that of the first kind of spiral grooves, thus forming protrusions which are formed by the intercrossing of these two sets of spiral grooves. The purpose of providing two sets of spiral grooves is to allow an absorption liquid to impinge against the protrusions formed by the intercrossing of these grooves so as to promote the turbulence in the absorption liquid.
In the case of the heat exchanger tube described in this Japanese Utility Model Unexamined Publication S/57-100161, it is certainly possible as shown in FIG. 2A to spread the flow of the absorption liquid layer on the surface of the heat exchanger tube C1 due to the presence of the spiral grooves V1. However, since the spiral grooves V1 is linear, the turbulence of the absorption liquid to be obtained would be insufficient.
On the other hand, in the case of the heat exchanger tube described in the Japanese Utility Model Unexamined Publication S/64-35368, the absorption liquid layer A2 is impinged upon a protrusion E1 thereby to generate a turbulence. However, since these two sets of spiral grooves V2 and V3 are twisted in an opposite direction from each other in relative to longitudinal direction of the tube and hence intercrossed with each other, the turbulence of absorption liquid layer A2 generated by the protrusion E1 is caused to collide with the turbulence of absorption liquid layer A3 generated by the protrusion E2 disposed next to the protrusion E1. As a result, it is impossible to maintain the turbulence of the absorption liquid layers A2 and A3 along the longitudinal direction of the tube, thereby making it difficult to effectively promote the turbulence of the absorption liquid. Therefore, it is difficult to maintain the turbulence of the absorption liquid layers A2 and A3 on the surface of the heat exchanger tube C2 for a long period of time.
On the other hand, in the case of an absorption refrigerator or an absorption type hot and cold water generator, a cold water is produced by taking the latent heat of vaporization of a refrigerant from a water to be cooled when the refrigerant is vaporized from an evaporator. The vaporized refrigerant from the evaporator is then absorbed by an absorption liquid in an absorber so as to be turned back to a liquid state while releasing the latent heat of vaporization and the heat of dilution.
Since the absorption of refrigerant becomes more difficult with a rise in temperature of an absorption liquid, the absorption liquid is required to be cooled by the surface of a heat exchanger tube, thereby inhibiting the absorption liquid from heated excessively by the latent heat of vaporization and the heat of dilution.
Generally, the ordinary absorber is constructed such that many a number of heat exchanger tubes are arranged horizontally or vertically and an absorption liquid is allowed to flow down along the surfaces of these heat exchanger tubes in which a cooling water is circulated. The heat exchanger tube is generally constructed of a plain tube unless there is any special requirement to employ a high performance heat exchanger tube for the purpose of enhancing the performance of the tube.
For improving the performance of heat exchanger tube in an absorber, the following countermeasures are required to be taken.
(1) To increase the heat exchange area;
(2) To minimize the non-uniformity in concentration between the upper layer and the lower layer of the absorption liquid layer, which is caused from the absorption of vapor by the surface of the running absorption liquid and the resultant thinning in concentration of the absorption liquid; and
(3) To promote the interfacial turbulence of the absorption liquid flowing down along the surface of the heat exchanger tube.
One example of such a high performance heat exchanger tube is proposed in Japanese Utility Model Unexamined Publication S/57-100161, wherein many a number of fine spiral grooves are formed on the outer surface of the heat exchanger tube. Another example of such a high performance heat exchanger tube is proposed in Japanese Utility Model Application S/58-51671, wherein many a number of fine spiral grooves of the same depth intercrossing with each other are formed on the outer surface of the heat exchanger tube. Still another example of such a high performance heat exchanger tube is proposed in Japanese Utility Model Unexamined Publication H/1-73663, wherein many a number of fine spiral grooves which are intercrossed with each other are formed on the outer surfaces of only the end portions of the heat exchanger tube.
It is admitted that the performance of a heat exchanger tube can be improved by forming many a number of fine spiral grooves on the outer surface of the heat exchanger tube; by forming many a number of fine spiral grooves on the outer surface of the heat exchanger tube in such a manner that these spiral grooves intercross with each other; or by forming many a number of intercrossed fine spiral grooves on the outer surfaces of only the end portions of the heat exchanger tube.
However, the method of forming many a number of fine spiral grooves in the same depth and in the same direction on the outer surface of the heat exchanger tube, as well as the method of forming many a number of intercrossed fine spiral grooves on the outer surfaces of only the end portions of the heat exchanger tube, as disclosed in Japanese Utility Model Unexamined Publications S/57-100161 and H/1-73663, are accompanied with a problem that the flow of the absorption liquid on the surface of the heat exchanger tube becomes unidirectional so that it is difficult to achieve a sufficient interfacial turbulence of the absorption liquid, which is one of the aforementioned requirements to improve the performance of heat exchanger tube.
On the other hand, the method of forming many a number of fine spiral grooves of the same depth on the outer surface of the heat exchanger tube in such a manner that these grooves intercross with each other as suggested in Japanese Utility Model Application S/58-51671 is also accompanied with a problem that since the flow of the absorption liquid simply runs down along the bottom of the spiral groove, the spread of the flow of the absorption liquid in the longitudinal direction of the heat exchanger tube is not so promoted, and it is difficult to minimize the non-uniformity in concentration between the upper layer and the lower layer of the absorption liquid layer.
Because of these reasons, the improvement in heat exchange property of the absorber is still insufficient even if the aforementioned heat exchanger tubes are substituted for the plain tube.

Heat exchanger tube and method for manufacturing the same


A memory data protection system is disclosed, which comprises a memory circuit, a protection contents indicating section which stores a security bit and a protection bit, a protection function circuit which determines permission/prohibition of reading of data from the memory circuit and permission/prohibition of writing of data to the memory circuit in accordance with the security bit and the protection bit, and a protection function locking/unlocking circuit which makes the protection function circuit in a lock state to forcibly prohibit reading of data from the memory circuit and writing of data into the memory circuit in a time period from when a power supply is turned on till when the protection function circuit completes reading of the security bit and the protection bit from the protection contents indicating section into data buses, and after lapse of the time period, the protection function locking/unlocking circuit unlocks the lock state.

1. Field of the Invention
The present invention relates to a data protection system that controls security and/or protection of contents that are stored in a nonvolatile semiconductor memory. Particularly, the present invention relates to a circuit that controls a security function and/or a protection function, and that is applied to a nonvolatile semiconductor memory chip or a nonvolatile semiconductor memory mixed logic chip such as a microcomputer chip.
2. Description of the Related Art
A microcomputer system that is loaded with a flash memory has a function of controlling security and protection of storage contents of the nonvolatile semiconductor memory, in order to secure confidentiality of the contents stored in the nonvolatile memory and safe operation of the microcomputer system.
FIG. 13 is a block diagram that shows a part of a conventional example of a nonvolatile semiconductor memory that is loaded with security and protection functions.
The nonvolatile semiconductor memory comprises a memory circuit 10 having a nonvolatile (NV) memory matrix, a voltage detecting circuit (VDECT) 11, an oscillation circuit (OSC) 12 for generating a clock signal CLK, a security bit/protection bit storing circuit (SECPRT bit) 13, a read/write control circuit (R/W_CNT) 14 for the memory circuit, and a data bus (DB) 15.
FIG. 14 shows a circuit configuration of the SECPRT bit 13 in the nonvolatile semiconductor memory shown in FIG. 13.
The SECPRTbit 13 comprises an NV memory cell 131 that stores the security bit SEC therein and an NV memory cell 132 that stores the protection bit PRT therein.
Upon receiving an output enable control signal OE and a security command SECCMD that are supplied from the microcomputer system controller, the SECPRTbit 13 outputs a security bit SEC to a data bus DB1, and upon receiving a write enable control signal WE and a protection command PRTCMD that are supplied from the microcomputer system controller, the SECPRTbit 13 outputs a protection bit PRT to a data bus DB 0.
FIG. 15 shows a circuit configuration of the R/W_CNT 14 in the nonvolatile semiconductor memory shown in FIG. 13.
Upon receiving the security bit SEC outputted from the SECPRTbit 13, and a chip enable control signal CE and the output enable control signal OE that are supplied from the microcomputer system controller, the R/W_CNT 14 generates a read control signal RD, and upon receiving the protection bit PRT outputted from the SECPRTbit 13, and the chip enable control signal CE and a write enable control signal WE that are supplied from the microcomputer system controller, the R/W_CNT 14 generates a write control signal WR of the memory circuit 10.
FIG. 16 is a timing chart that shows an operation example at the time of turning on the nonvolatile semiconductor memory shown in FIG. 13.
When the power supply is turned on, the nonvolatile semiconductor memory shown in FIG. 13 determines permission or prohibition of reading from and writing into the memory circuit 10, based on a state of a security bit SEC and a state of a protection bit PRT within the SECPRT bit 13.
In other words, when the security bit SEC is "1" (a LOCK state), the memory prohibits reading from the memory circuit 10, and when the security bit SEC is "0" (an UNLOCK state), the memory permits reading from the memory circuit 10.
When the protection bit PRT is "1" (a LOCK state), the memory prohibits writing to the memory circuit 10, and when the protection bit PRT is "0" (an UNLOCK state), the memory permits writing to the memory circuit 10.
However, if the security bit SEC stored in the SECPRT bit 13 is "0" (the UNLOCK state) at the time when the power supply is turned on in the state that a chip enable control signal CE is "1", a read control signal RD that is output from the R/W_CNT 14 becomes "1". Therefore, data in the memory circuit 10 is erroneously read into the data bus DB (31: 0) 15.
That is, immediately after the power supply is turned on, a malfunction of the memory occurs that the data is read out. At the time of turning on the power supply, the reading of the security bit SEC becomes unstable. Therefore, there is a problem that the security function is lowered, and the data stored in the memory circuit 10 is leaked out.
If the protection bit PRT stored in the SECPRT bit 13 is "0" (the UNLOCK state) at the time when the power supply is turned on in the state that the chip enable control signal CE is "1", a write control signal WR that is output from the R/W_CNT 14 becomes "1". Therefore, data in the data bus DB (31: 0) 15 is erroneously written into the memory circuit 10. As a result, program data is destructed, and the system does not work.
As explained above, according to the conventional nonvolatile semiconductor memory or a conventional microcomputer system that is loaded with the nonvolatile semiconductor memory, data is read out erroneously from the memory and data is written erroneously into the memory, immediately after the turning on of the power supply. As a result, program data is destructed, and the system does not work.


The present invention provides an acoustic vibration analyzing apparatus for carrying out acoustic vibration analysis by picking up data of sounds generated due to rotation of a plurality of gears and data of the number of revolutions of a gear selected from a plurality of gears when a transmission of a vehicle having the plurality of gears operates. The acoustic vibration analyzing apparatus comprises an acoustic vibration calculation portion for analyzing acoustic data in terms of frequency, an order calculation portion for calculating an order in compliance with the specifications of a plurality of gears, a speed calculation portion for calculating the speed of a vehicle, and a display unit for displaying acoustic pressure levels with the order and vehicle speed associated therewith.

As an apparatus equipped with a rotating body such as a gear is run, there are cases in which continuous sounds continuously generated regardless of running state, non-continuous sounds generated in a particular running state, and vibrations not accompanying any sound are generated. Of these sounds and vibrations, teeth-contacting sounds generated due to rotation of gears with their teeth engaged with each other, and sounds generated from the rolling surface of a bearing (hereinafter, these sounds are called abnormal sounds) may be listed as non-continuous sounds. Conventionally, for the purpose of preventing such abnormal sounds from being generated, sensory inspection is carried out by an operator, or an apparatus for analyzing such abnormal sounds is developed.
An analyzing apparatus disclosed in Japanese Published Examined Patent Application No. 2596081 (pages 2 and 3, and FIG. 1) measures vibrations generated in response to rotation speeds in a predetermined range while varying the rotation speeds of gears, and picks up signals in a frequency range determined in response to the rotation speed and number of teeth of gears among signals obtained by analyzing the frequencies in connection with the vibrations. In accordance with the analyzing apparatus, the maximum value of abnormal noise is extracted.
Another analyzing apparatus, disclosed in Japanese Published Unexamined Patent Application No. 2002-257685 (paragraphs 0015 and 0016, and FIG. 4) simultaneously measures unevenness of rotation speeds when gears rotate, and acoustic pressure of sounds generated from the gears, and compares the waveforms of the respective signals. In accordance with the analyzing apparatus, it can be distinguished whether sounds being generated from a gear transmission having gears are resulting from gears or from other factors.
Still another analyzing apparatus, disclosed in Japanese Published Unexamined Patent Application No. 2001-194221 (paragraphs 0029 and 0030, and FIG. 13) picks up running sounds as data by attaching a sound collecting microphone and a recorder to a motorcycle, and identifies sounds of an already known volume, degree or order, whose ratio is comparatively high, among all sounds, using an order filter. In accordance with the analyzing apparatus, evaluation can be carried out based on the order of the sounds.
Incidentally, with conventional analyzing apparatuses, it is impossible to identify a place from which abnormal sounds being generated, if there is a plurality of rotating bodies. Also, even if an attempt is made to identify a place at which abnormal sounds being generated by way of sensory inspection, unevenness in results of sensory inspection is liable to occur because such a inspection is based on the sensitivity of a human being, and it is difficult to investigate the correlation between the results of the sensory inspection and the actually measured results. In particular, in a unit such as a transmission of an automobile, in which gears are disposed multi-axially on a rotating shaft, or multi-axial rotating shafts are incorporated, a number of places may be guessed to be the place where abnormal sounds are occurring, and it is difficult to identify the place of occurrence of the abnormal sounds.
In addition, with the conventional apparatuses, evaluation is carried out based on the elapsed time during a number of revolutions of a rotating body, and since the actual vehicle speed is different from the rotation speed of the rotating body when an object to be inspected such as an automobile moves, it is difficult to investigate the correlation of the results measured.
Further, in judgment based on maximum value as in the analyzing apparatus described in Japanese Published Examined Patent Application No. 2596081, if the volume of the abnormal sounds is low, it is not possible to detect the frequency even if it can be sensed by a human being.
The present invention has been developed to solve the above-described problems and shortcomings, and it is therefore an object of the invention to provide an analyzing apparatus that is capable of reliably distinguishing factors of sound generation and places thereof. Also, it is an object of the invention to provide an analyzing apparatus that is capable of reliably distinguishing factors of vibration generation even if vibrations are measured instead of sounds.

Acoustic vibration analyzing apparatus and acoustic vibration analyzing method, program for analyzing acoustic vibration, and recording medium, readable by computer, on which program for analyzing acoustic vibration is stored


An unwinding apparatus supports a reel (60) of web material (22) which is to be unwound and directed into a printing unit (14) having a front/operator side and a rear/gear side. The unwinding apparatus comprises a frame (16) including a rear side part (28) located at the rear side of the printing press (14), and front side parts (24, 26) located at the front side of the printing press (14). The front side parts (24, 26) define an opening in the frame (16). Guide and locating bars (38) on the frame (16) extend from the rear side part (28) to the front side parts (24, 16) of the frame (16). The apparatus further comprises a movable reel cartridge (18) having front and rear cartridge frame parts (64, 66) for supporting the reel (60) of web material (22). The reel cartridge (18) is movable through the opening in the frame (16) and onto the guide and locating bars (38) to locate the reel (60) in its operating position.

U.S. Pat. No. 4,433,816 discloses a wire spool support in which a full wire spool is supported on a rack. The wire is guided over several spools for processing. The steadfastness of the rack is especially critical during high unwinding speeds. A continuing trouble free unwinding is not guaranteed at all unwinding speeds.
German Utility Model 89 12 231.3 discloses a swingable unwinding device for large reels. A stand built of two plates is swingably fastened on a base plate and accepts the shaft of a reel. The base plate is not displaceably mounted.
Also, a printing unit in a printing press can be supported above a respective individual unwinding unit. A reel of web material loaded into the unwinding unit is unwound upwardly from the unwinding unit into the printing unit. Depending upon the layout of printing units in the printing press, there may not be sufficient room adjacent to the unwinding unit for loading and unloading of the reel.


An image processing system includes an input unit, a selecting unit, a determining unit and a control unit. The input unit inputs one of a color image and a monochrome image, and the selecting unit selects either a normal recording mode for recording an image on a recording material at a predetermined recording density, and a decimation recording mode for recording the image on the recording material at a recording density lower than that of the normal recording mode. The determining unit determines if the input image is a color image or a monochrome image, and the control unit changes to the normal recording mode, when the decimation recording mode is selected and the input image is determined to be a color image.

1. Field of the Invention
The present invention relates to image processing apparatuses and image processing methods, and more particularly relates to an image processing apparatus and an image processing method suitable for a facsimile apparatus or the like including a recording unit using an ink-jet recording system.
2. Description of the Related Art
Recently, color facsimile communication has been standardized by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T), and facsimile apparatuses for compressing and communicating a color image in a Joint Photographic Experts Group (JPEG) compression system are well known. A recording unit in this type of facsimile apparatus is provided with a recorder using a laser beam system or using an ink jet system. In particular, facsimile apparatuses with a recording unit using the ink jet system capable of recording color images at low cost are widely disseminated.
Image recording apparatuses using laser systems, and particularly those using ink jet systems, have ink droplets of uniform size for recording a solid black portion when recording a thin line. The conventional image recording apparatuses are disadvantageous in that ink droplets of a size adequate for clearly recording the thin line are excessive for recording the solid black portion. Although it may depend on the quality of the paper or on the recording environment, an ink droplet for one dot tends to bleed in the paper, thus printing on an area larger than the target resolution of one dot. This problem is caused by characteristics of ink-jet recording, and the excessive ink noticeably accumulates in the black solid portion.
Due to the excessive amount of ink, an image, immediately after being printed, is output which is black and wet due to the ink. This may cause smearing which may spoil a next page, and the ink may soil a user. The excessive ink may also cause the paper to kink and crinkle. This causes waste not only of ink for recording but also of power consumption for recording.
Accordingly, there has been proposed an apparatus for decimating recording dots so as to conserve ink to be used and to reduce power consumption during recording, and to provide countermeasures against black-wetting and smearing. The user can set the apparatus to perform decimation, thus reducing ink consumption and the operating cost.
Decimation includes two types of processing. One is unconditional decimation for unconditionally zigzag-converting black pixels into white pixels. The other is reference-conditional decimation, as disclosed in Japanese Laid-Open Patent No. 8-130637, for referring to states of pixels adjacent to a pixel to be decimated and for determining whether to decimate the pixel.
Hitherto, once the user has set the apparatus in a decimation recording mode, the apparatus always performs decimation regardless of the type of image to be recorded, whether it is a monochrome character image, a monochrome halftone image, or a color image.
The monochrome halftone image and the color image are images obtained by printing beautifully pictures and photographs. When a subject-copy image is read and converted into recording data, that is, binary data, halftoning, such as error diffusion processing, is performed.
For example, when multi-valued color image data obtained by reading a color subject copy is converted into a binary color image, color-difference data generated by peripheral conversion is added to the multi-valued color data. Subsequently, the added data is converted into a predetermined single color by comparison.
When the recording unit decimates and records the processed recording data, gray scaling and overall color balance are lost, thus providing the user with an undesirable output image.
Since the monochrome halftone image is binarized by error diffusion processing, the image will lose gray scaling when decimated and the image quality becomes substantially degraded.

Image processing apparatus and method selectively utilizing lower than normal image recording density


A method of applying device preferences to network traffic includes establishing first DNS settings of a first device and establishing second DNS settings of a second device. The first DNS settings are associated with one or more first name servers. The second DNS settings are associated with one or more second name servers. The method also includes transmitting, from the first device, at least a portion of a first DNS query and a public IP address to the first name server. The method further includes transmitting, from the second device, at least a portion of a second DNS query and the public IP address to the second name server.

The Domain Name System (DNS) is a hierarchical naming system for computers, services, or any resource participating in the internet. Using DNS, it is possible to associate various information with domain names assigned to internet participants. The analogy has been made that the DNS serves as the "phone book" for the internet by translating human-friendly computer hostnames into IP addresses.
Domain name registration is conducted under a Shared Registration System (SRS), which was created by Network Solutions, Inc. in 1999 to provide a registry through which multiple, globally diverse registrars could register domain names. The term "registry" refers to the entity responsible for managing allocation of domain names within a particular name space, such as a top level domain (TLD). VeriSign, Inc. is currently the largest registry in the world, managing millions of digital identities associated with the .com, .net, and .edu TLDs.
Name servers are operated as part of the DNS in order to translate humanly memorable domain names (e.g., www.verisign.com) and hostnames into the corresponding numeric Internet Protocol (IP) addresses. This function is also referred to as domain name resolution. Although great benefits are available through the internet, malicious software (also referred to as malware) is present on some sites and other sites attempt to acquire sensitive information such as usernames, passwords and the like by a technique known as phishing.
In order to protect users against malware and phishing sites, blacklists (also referred to as block lists) have been developed as a basic access control mechanism that allows a user to access websites except for those listed on the blacklist. Whitelists are utilized to guarantee a user access to sites that are known to be reliable. Despite the benefits provided by blacklists and whitelists, there is a need in the art for improved methods and systems for increasing the security and reliability of internet services.

This patent is subject to a terminal disclaimer.

Method and system for partitioning recursive name servers


The current application provides for exogenous immune receptors that do not require any additional selection marker genes and/or any additional silicide genes. The disclosure allows for the production of engineered T cells that can be enriched for in an untouched manner, i.e., the engineered T cells do not require any interaction with any outside agent and can be selected for by eliminating T cells that express the endogenous alpha beta T cell receptor. Engineered T cells with an exogenous immune receptor are provided that can be differentiated from endogenous T cell receptor and now can be eliminated, i.e., depleted, with a selective antibody that specifically targets the exogenous immune receptor.

Adoptive transfer of T cells with engineered anti-tumor specificity or anti-pathogen specificity are under development. In such strategies, an exogenous immune receptor such as an alpha beta T cell receptor, or a gamma delta T cell receptor, or a chimeric antigen receptor having a particular anti-tumor specificity, or a particular anti-pathogen specificity, is transferred to either autologous T cells from a patient or, e.g., in case of an allogeneic stem cell transplantation into a patient, in corresponding allogeneic T cells. For example, a leukemic patient that is undergoing blood stem cell transplantation will, during the treatment, also be lympho-depleted. Hence, such a patient may also benefit from, e.g., infusion of donor T cells that have been engineered to express a specific anti-leukemic T cell receptor.
Although clinical trials have established the value of adoptive transfer of TCR-engineered cells in cancer patients, clinical benefit of such strategies is generally observed only in a portion of the patients. One explanation for the observed limited efficacy of TCR-engineered T cells is a suboptimal surface expression of therapeutic TCRs caused by competition for CD3 components between the newly introduced and endogenous TCRs (Provasi et al., Nat. Med. 2012 May; 18(5):807-15). Moreover, application of such strategies in an allogeneic setting, for example, allogeneic stem cell transplantation, is hampered by serious safety concerns, as non-engineered T cells that express endogenous alpha beta T cell receptors may induce unwanted side effects such as, e.g., graft-versus-host disease in an allogeneic stem cell transplantation setting. Hence, strategies to select for engineered T cells have been developed that are focused on a positive selection of engineered T cells. Strategies that exist today aim at including surrogate gene markers such as, e.g., a neomycin gene, or, e.g., a fluorescent protein or some other additional gene that allows a positive selection of transduced or transfected cells. However, such strategies have further safety concerns in that they require the inclusion of usually large foreign genes that can be immunogenic in addition to the adoptive transfer of an exogenous immune receptor with a desired specificity.
In addition, it has also been recognized in the art that because of the fact that genetically engineered cells are infused into patients, that it may be beneficial to selectively eliminate these cells from a patient in case of an adverse event. Hence, engineered T cells often also further comprise, in addition to the exogenous immune receptor, genes that allow selective elimination of the engineered T cells. Such genes include, e.g., silicide genes that, upon administration of an agent to the patient, selectively kills the cells with the suicide gene such as HSV-TK (reviewed in Bondanza et al., Blood 107:1828-1836 (2006).
Hence, in the art, strategies for engineering T cells and for use in subjects, such as in the treatment of humans, have focused on including additional genes in engineered T cells that allow for selection of the engineered cells for use in the subjects and/or that allow for depletion of engineered T cells from subjects being treated with the engineered T cells.

Use of antibodies for enrichment of engineered T cells with exogenous immune receptors and antibodies for use in depletion of engineered T cells


A remote control device remotely controlled by a remote operation device includes an operation screen transmission portion to transmit an operation screen to the remote operation device; and a changed area decision portion to decide on an area in a second operation screen that is different from a first operation screen, as a changed area, in a stage before the operation screen transmission portion transmits the second operation screen subsequently to the first operation screen. The operation screen transmission portion includes a supplemental information transmission portion to transmit supplemental information including a command to display the changed area in full screen, together with the second operation screen.

1. Field of the Invention
The present invention relates to a remote control device remotely controlled by a remote operation device, a screen transmission control method and a screen transmission control program executed by the remote control device, a remote operation device remotely controlling a remote control device, and a screen display control method and a screen display control program executed by the remote operation device.
2. Description of the Related Art
Recent image forming apparatuses come up with touch panels. Touch panels facilitate the operation of enlarging, reducing, or scrolling a screen appearing on the display.
For example, Japanese Patent Laid-Open No. 2007-293511 discloses an input device with a touch panel which has a display screen for displaying an operation unit and detection means for detecting a touch on the display screen. The input device includes: state switching means for switching between a first state in which an operation on the operation unit appearing on the display screen is accepted if the detection means detects a touch on the display screen and a second state in which an operation for partially or entirely moving a display content on the display screen is accepted without accepting an operation on the operation unit; and a switching operation unit for accepting an operation of switching the states by the state switching means. In this device, when an input from a user is accepted using the touch panel, the display content on the display screen of the touch panel can be moved through a drag operation on the touch panel.
Image forming apparatuses can display, for example, a popup screen, a pull-down menu screen, and a balloon screen, which are superimposed on the currently displayed screen in order to enhance the user's operability. The size of the popup screen and other screens is often so small that the user has to make an operation of enlarging the area in order to view the content of the popup screen. A scroll operation is sometimes required in order to display the area of the popup screen. The operation is cumbersome accordingly.

Remote control device, remote operation device, screen transmission control method, and non-transitory computer-readable recording medium encoded with screen display control program


A topical opioid paradigm was developed to determine analgesic peripheral effects of morphine. Topical morphine as well as peptides such as [D-Ala2,MePhe4,Gly(ol)5]enkephalin (DAMGO) produced a potent, dose-dependent analgesia using the radiant heat tailflick assay. The topical drugs potentiated systemic agents, similar to the previously established synergy between peripheral and central sites of action. Local tolerance was rapidly produced by repeated daily topical exposure to morphine. Topical morphine tolerance was effectively blocked by the N-Methyl-D-Aspartate (NMDA) receptors antagonist MK801 and ketamine given either systemically or topically. NMDA receptor antagonists reversed pre-existing morphine tolerance. The activity of topical NMDA antagonists to block local morphine tolerance suggests that peripheral NMDA receptors mediate topical morphine tolerance. Morphine was cross tolerant to [D-Ala2,MePhe4,Gly(ol)5]enkephalin (DAMGO), but not to morphine-6β-glucuronide, implying different mechanisms of action. These observations have great importance in the design and use of opioids clinically. Topical pharmaceutical compositions comprising an analgesic that functions through an opiate receptor and an NMDA receptor antagonist for producing analgesia without inducing tolerance are described.

Morphine is a potent mu opioid receptor agonist with important central sites of action (Reisine and Pasternak, 1996). Peripheral mechanisms also have been reported and their importance is becoming increasing appreciated (Stein et al., 1995; Barber and Gottschlich, 1992; Joris et al., 1987; Junien and Wettstein, 1992). Peripheral analgesics have a number of potential advantages in the clinical treatment of pain, particularly the limitation of side-effects such as constipation and sedation which are typically seen with systemic administration. Given locally into the tail, morphine and other opioids are effective analgesics, working either alone peripherally or synergistically at central sites (Kolesnikov et al., 1996). In many respects, these studies are similar to clinical investigations (Stein, 1993; Dahl et al., 1990; Dalsgaard et al., 1994; Heard et al., 1992; Joris et al., 1987; Khoury et al., 1992; Mays et al., 1987; Raja el al., 1992). Peripheral mechanisms also have been implicated in systemic morphine tolerance (KQlesnikov et al., 1996). Early studies reported that systemic morphine tolerance does not alter the sensitivity to morphine given either spinally or supraspinally (Roerig et al., 1984). Although we also found potency to remain unchanged for spinal or supraspinal morphine following chronic morphine dosing, a profound reduction in its potency peripherally was observed (Kolesnikov et al., 1996).

Topical compositions comprising an opioid analgesic and an NMDA antagonist


A method of helping to secure an infant in a child's car seat and to prevent slouching of the infant in the car seat includes the step of placing a cushion having a unitary tube shaped structure into the car seat and placing an infant into the car seat where the tube-shaped structure has an upside-down U-shape including two legs with two axial ends and a base portion where the two legs are joined together. The base portion is located at the top of the back surface of the car seat and the two axial ends of the legs are located at the free edge of the seat surface of the car seat. The cushion legs engage the side walls of the car seat. The method includes the step of placing the infant into the car seat so that the infant is surrounded by the cushion base portion and legs to reduce the surface area of the car seat for the infant to occupy in order to help to minimize slouching of the infant in the car seat.

Many states have laws requiring that children be restrained in a car seat while in an operating vehicle. Child car seat manufacturers have developed two different standard types and sizes of car seats to assure parents that not only are their children safe but that they are compliant with the state laws. The first standard type car seat is the infant carrier which is typically used with infants who weigh up to 20 pounds. The second standard type car seat is the front facing toddler support which is for toddlers who weigh from 20 pounds to 50 pounds. Unfortunately, the toddler support car seat due to its larger dimensions cannot accommodate newborns or very small infants, including premature infants and prematurely discharged newborns. The infant carrier, which is smaller than the toddler support, is also often too large to accommodate newborn or premature infants.
Infants who are too small to properly fit in a car seat can flop back and forth while in the car seat. Newborn or prematurely born infants, when placed into a car seat, are commonly forced into a seated orientation in which either the head is slumped or slouched or their entire bodies are slouched over since their bodies are not large enough to cover the surface area of the car seat. This not only affects the comfort of the child but also his or her safety and health.
Much of the surface area of the car seat between the body of the infant and the side walls of the car seat is left unoccupied. Even when the infant is secured by the safety belt which is part of the car seat structure, the infant is not supported at its lateral sides of its body and at its head and neck by the seat belt. The safety of the infant may be compromised in this situation.
Moreover, infants can be uncomfortable in such a slumped or slouched over orientation. A slumped or slouched over orientation can negatively affect the infant's breathing. Studies have shown that premature infants have significant decreases in oxygen saturation while restrained in a car seat with 30% experiencing hypoxia, bradycardia, sleep apnea or some combination of those conditions.
The decrease in oxygen saturation is directly related to the degree to which the infant is slumped or slouched over in the car seat; the more slumped or slouched over is the infant, the greater the physiological risk, the less slumped or slouched over is the infant, the lesser the physiological risk. This occurs because the more slumped or slouched over the infant is, either forward or sideways, the greater the risk of airway obstruction in the infant.
Infant slouching or slumping occurs for two basic reasons, low birth weight infants cannot resist the gravitational effects if their bodies are in a too upright position, and standard sized child car seats do not provide the necessary support and orientation for these infants to prevent the gravitational effects. These effects can cause slouching or slumping since most infants do not have the physical maturation or strength of the back to maintain an upright position.
Accordingly, there exists a need for a child's car seat cushion that helps to support the child in a physiologically and physically beneficial orientation when the child is too small for the car seat by minimizing or preventing the child from slouching or slumping. There also exists a need for a child's car seat cushion that helps to secure the child who is too small to fit in standard size car seats in such car seats in order to help protect the child from injury during a vehicle crash event or sudden vehicle movement.


A feeding technique for a storage unit is provided, in which power can be supplied from an optimum power source depending on an operation mode of a cache memory, the stable switching of feeding paths can be performed, and the feeding with high voltage accuracy and small voltage variation can be achieved. For its achievement, the feeding system in the RAID system including a hard disk drive, a disk adaptor, a channel adaptor, and a cache memory is provided. The feeding system includes a DC-DC power source to supply, to the cache memory, the voltage for a normal operation mode in which the data is written/read to/from the cache memory, and a DC-DC power source to supply, to the cache memory, the voltage for a backup operation mode in which the data stored in the cache memory is retained, and the power sources are switched during the feeding depending on the operation mode of the cache memory.

The present invention relates to a storage unit and, particularly, to a technique effectively applied to a feeding technique for a RAID (Redundant Array of Inexpensive Disk) system in which storage devices are arrayed so as to have redundancy.
According to the examination by the inventor of this invention, the techniques as follows are known in the conventional RAID system and the feeding technique for the RAID system.
The conventional RAID system examined by the present inventor comprises: a hard disk drive for storing data; a disk adaptor for controlling the writing/reading of data to/from the hard disk drive; a channel adaptor for controlling an interface with a host CPU; a cache memory for temporarily storing the data written/read between the host CPU and the hard disk drive; a cache switch for shifting the writing/reading of data to the cache memory; a shared memory for storing configuration information of the entire unit and information for managing the progress of operation; an AC-DC power source, a DC-DC power source, and a battery for a feeding system; and the like.
In this conventional RAID system, the writing data from the host CPU is once written to the cache memory and then stored in the hard disk drive. At this time, it is unnecessary to immediately write, to the hard disk drive, the data stored in the cache memory, and the writing may be done depending on operational conditions of the RAID system. Even if the data writing from the cache memory to the hard disk drive is not done, the data temporarily stored in the cache memory from the host CPU may be accessed. Furthermore, there is an advantage of the fact that since an access speed of the cache memory is faster than that of the hard disk drive, a high-speed data access can be done from the host CPU. In the RAID system, the cache memory with larger capacity is more preferable from the viewpoint of the data access performance.
Therefore, the conventional RAID system uses a large number of DRAMs (Dynamic Random Access Memories) because the DRAM has the large memory capacity and is effective in cost. The DRAM used for the cache memory is inferior to a SRAM (Static Random Access Memory) in the access speed, but is advantageous in memory capacity and the cost. Also, the DRAM is advantageous over the flash memory in both of the cost and storage capacity. In contrast, since the DRAM is a volatile memory, it is necessary to always supply a power source voltage in order to store (retain) the data and also a refresh operation (regular recharging operation for the inner capacitor) unique to the DRAM is indispensable.
As described above, since the DRAM is a volatile memory, when power failures such as blackouts occur under the condition that the data in the cache memory is not yet stored in the hard disk drive, the data in the cache memory (data not yet written in the hard disk drive) is volatilized (data lost) due to the stop of the feeding to the cache memory. Therefore, the function to prevent the volatilization of the data in the cache memory, for example, the function to switch the power source to the battery power source and continue the feeding to the cache memory during the blackout is needed in the power source feeding system of the RAID.
For example, from the viewpoint of the reliability of the stored data, it is essentially desirable that the system is stopped after the data not yet written to the hard disk drive in the cache memory is stored into the hard disk drive even when the power failures such as the blackouts occur. However, a high-cost power system such as UPS (Uninterruptable Power Supply) is required for its achievement.
Therefore, in the conventional system, a battery backup system for the cache memory data is adopted as a method of preventing data loss at low cost. In this battery backup system, the battery is used only for the feeding to the cache memory during the blackout failures, and once the cache memory (DRAM) is switched to the backup operation mode, the data access is inhibited and the power consumption thereof is reduced. Accordingly, the low-cost lead storage battery can sufficiently cover the battery performance and the power capacity. Also, the system may be used even in a mounting space capable of mounting on a device.
As described above, the feeding system in the conventional RAID system examined by the inventor uses, for example, a feeding path as described in a document of Japanese Patent Laid-Open No. 2001-290608. More specifically, the document discloses a technique provided with two systems such as a normal feeding system in which the AC voltage of commercial power source is converted to the DC voltage and the converted DC voltage is converted to a voltage necessary for the normal operation of the cache memory and the converted voltage is supplied to the cache memory, and a battery feeding system, employed at the time of occurrence of the power failures such as the blackouts, in which a voltage of the battery is converted to the minimum voltage necessary for the backup operation of the cache memory and the converted voltage is supplied to the cache memory.
As a result of the examination by the inventor about the feeding system of the conventional RAID system, the followings have been shown.
For example, the feeding system in the conventional RAID system examined by the inventor has a configuration as shown in FIG. 9. An example of the configuration and operation of the feeding system in the conventional RAID system examined by the inventor will be described with reference to FIG. 9.
As shown in FIG. 9, a feeding system 61 in the conventional RAID system examined by the inventor is connected to a host CPU 2 and a commercial power source 3 and is composed of: a cache memory (CACHE) 62; a hard disk drive (HDD) 11; a disk adaptor (DKA) 12; a channel adaptor (CHA) 13; a cache switch (CSW) 15; AC-DC power sources (1) 63 to (4) 66; a battery 67; DC-DC power sources (1) 68 and (2) 69; and the like.
In the configuration of this feeding system 61, the path from the AC-DC power source (2) 64 through the switch (SW1) to the memory 71 and the path from the battery 67 through the DC-DC power source (2) 69 and the switch (SW2) to the memory 71 are provided. The former is the feeding system for the normal operation mode and the latter is the feeding system for the backup operation mode. In addition, the power from the AC-DC power source (1) 63 is supplied to the cache memory 62, the disk adaptor 12, the channel adaptor 13, and the cache switch 15, and the power from the AC-DC power source (4) 66 is supplied to the hard disk drive 11. Note that the battery 67 is always charged through the AC-DC power source (3) 65 and the DC-DC power source (1) 68.
In the above-described feeding system 61, the AC-DC power sources (1) 63 to (4) 66 are usually used to supply the power to the whole RAID system, and the AC-DC power source (2) 64 is usually used to supply the power to the cache memory 62. In this case, the switch (SW1) is in a turn-on state. When the blackout occurs in this state, the AC-DC power sources (1) 63 to (4) 66 are stopped. However, a power source switching control circuit 72 turns on the switch (SW2) simultaneously with the detection of the reduction in output voltages of the AC-DC power source (2) 64, and the power is temporarily supplied from both of the battery 67 (DC-DC power source (2) 69) and the AC-DC power source (2) 64. Then, the switch (SW1) is turned off and finally the feeding path is completely switched to that from the battery 67. Therefore, the feeding to the cache memory 62 is not stopped, and loss of the data not yet written to the hard disk drive 11 is not generated.
However, since the operation voltage of the DRAM of the memory 71 used in the cache memory 62 is, for example, 3.3 V±10% in the above-described feeding system 61, the switching of the feeding path is started when the output voltage of the AC-DC power source (2) 64 is reduced to, for example, 3.3 V−7%. In this switching of the feeding path, it is necessary that the mode of the cache memory 62 is changed to the backup operation mode to reduce current consumption to a level adequate to the feeding ability of the battery 67 in a short time when the feeding voltage is reduced from −7% to −10% (μS order). Therefore, in the conventional feeding system 61, it is necessary to adopt a highly sensitive circuit configuration, as a series of control circuits used to monitor the feeding voltage and switch the feeding path, and thus the mounting technique to cope with such an external factor as noise is indispensable.
Also, in the conventional feeding system 61, when the instantaneous blackout beyond the endurance of the AC-DC power sources (1) 63 to (4) 66 occurs, the cache memory 62 is inevitably turned into the backup operation mode (in the state where the cache memory 62 cannot be used). Therefore, the operation of the device is substantially stopped though the data loss is not generated. For its recovery, the assist of engineers is necessary. As described above, the feeding system 61 in the conventional RAID system leaves room to be improved in the endurance for blackout.
The problems as shown above can be solved by the improvement of the endurance for instantaneous blackout of the feeding system, and if the endurance for instantaneous blackout can be improved, the data in the cache memory can be stored also into the hard disk drive (destaging process) even at the time of the blackout or the instantaneous blackout. As a result, it becomes possible to establish the RAID system with higher reliability. However, it is thought that the data backup of the cache memory is still necessary even if the endurance for blackout is improved and a destaging process thereof can be performed. This is because there is the possibility of exceeding the endurance limit for blackout when the data storage process is repeatedly performed due to the failure of the hard disk drive during the is destaging process. Therefore, it is necessary to switch the destaging process to the data backup process for the data in the cache memory in such a case.

Storage unit having normal and backup power sources for use in retaining data when normal power fails


Computer system, method and program for graphically representing network intrusions. Source icons are displayed in rows in a first column. The source icons represent source IP addresses from which intrusions were sent. Destination icons are displayed in rows in a second column. The destination icons represent destination IP addresses to which the intrusions were sent. The destination icons that receive intrusions from a same source icon are clustered together in the graphical representation across from the same source icon. An arrow is displayed from each of the source icons pointing to each of the destination icons to which each source icon sent an intrusion, such that there are “N” arrows from each source icon to “N” destination icons to which each source icon sent at least one intrusion.

Networks such as the Internet, Local Area Network, Extranets and Intranets are common today. Networks typically comprise communication media, routers, network switches, firewalls. Computers such as client computers and servers are connected to networks.
Network security is important, especially when the network and the computers on the network are connected to the Internet. There are various types of malicious "intrusions" that can jeopardize a network. Examples of malicious intrusions are viruses, worms, denial of service attacks, and buffer overflow attacks.
There are various known techniques to protect against such intrusions. A firewall at the gateway to the network or within a computer can block (a) messages containing a known electronic signature of a virus or worm, (b) all messages from source IP addresses known from experience to be malicious, (c) messages containing words characteristic of spam, (d) some or all messages from source IP addresses which are sending an unusually large number of messages to the same destination IP address, (e) all messages sent from a source IP address to a destination IP address which should not receive messages from this source, (f) entire networks which are known to be malicious and (g) entire countries for which there is no legitimate reason to allow network traffic. While these techniques are generally effective, some of the techniques require an identification, compilation and analysis of likely sources of the intrusions, their destinations, known malicious ports and attack signatures in order to determine the proper corrective action. It was known to provide a table which lists for each destination IP address the source IP addresses of messages sent to this destination IP address, to help identify malicious attacks. While these techniques are accurate and comprehensive in the information they present, there is typically too much data for a human to readily and effectively analyze when presented in this form.
Accordingly, an object of the present invention is to visually present intrusion data in a manner which a human can readily and effectively analyze.
Another object of the present invention is to visually present intrusion data in a manner which a human can readily and effectively analyze for the purpose of determining proper corrective action.

System, method and program product for visually presenting data describing network intrusions