In a memory testing device of a construction wherein various pieces of pattern data output from a pattern generator are taken out in a desired order and converted into a test pattern signal having a real waveform for application to each pin of a memory under test, the pattern selector provided for each I/O pin of the memory under test comprises plural registers having stored therein pattern selection control signals that designate patterns to be selected, a first multiplexer for selecting that one of the registers designated by a register selection control signal PJ generated by the pattern generator, and a second multiplexer that is controlled by the pattern selection control signal selected by the first multiplexer to select a pattern from the pattern data output from the pattern generator.

The present invention relates to a memory testing device for large-capacity semiconductor memories such as those called flash memories.
As one possible solution to the problem of increased number of pins with the growth in memory capacity, there is now proposed a memory that uses I/O pins both as primarily intended data input/output pins and as command input pins, address input pins and so forth. As shown in FIG. 1, such a memory has, in addition to, for example, eight input/output pins I/O-1 to I/O-8, a command input control pin P.sub.CLE, an address input control pin P.sub.ALE, a write control pin P.sub.WE, a write inhibit control pin P.sub.WP, a chip selection control pin P.sub.CE and a read control pin P.sub.RE.
An address signal of a total of 8.times.3=24 bits can be input into the memory by applying it to the eight input/output pins I/O-1 to I/O-8 over three cycle periods, for instance. With the 24-bit address signal, it is possible to access a memory area having a storage capacity of 16 Mbits or so. Furthermore, an address signal of 8.times.4=32 bits can be input by applying it to the input/output pins over four cycle periods--this means that a memory area of an about 4-Gbit storage capacity can be accessed.
By time sharing the same pins and inputting thereinto an address signal over plural cycle periods as mentioned above, the memory capacity can be enlarged without increasing the number of pins. Hence, it is possible to construct memories of the same package structure but having different storage capacities.
FIG. 2 shows an example of operation timing of this kind of memory. Row D shows a sequence of signals that are applied to the input/output pins I/O-1 to I/O-8. This signal sequence is headed by a command signal C0 to C7, which is followed by an address signal A0 to A21 and by data DAT.
To input the command signal C0 to C7, the address signal A0 to A21 and the data DAT into the memory in distinction from one another, the command input control pin P.sub.CLE and the address input control pin P.sub.ALE are provided. By making H-logic a command input control signal CLE for input to the command input control pin P.sub.CLE as shown in Row D, the command signal C0 to C7 is read into the memory. When an address input control signal ALE for input to the address input control pin P.sub.ALE is held H-logic as shown in Row B, signals applied to the input/output pins I/O-1 to I/O-7 are read as the address signal A0 to A21 into the memory, by which an access is made to an address desired to write data or address to read out data. FIG. 2 shows the cases where the 22-bit address signal A0 to A21 is supplied for three cycle periods to access a memory of a 4-Mbyte storage capacity and where the data DAT.sub.1 to DAT.sub.n is applied to the input/output pins I/O-1 to I/O-8 on a time sharing basis to write the data into the memory.
FIG. 3 shows in detail examples of signals that are applied to the input/output terminals I/O-1 to I/O-8. In cycle 1 eight bits of the command signal C0 to C7 is applied to the input/output pins I/O-1 to I/O-7. In cycle 2 the first eight bits A0 to A7 of the address signal are provided. This address signal will hereinafter be referred to as a column address signal (or X address). In cycle 3 eight bits A8 to A15 of the address signal are provided. The address signal will hereinafter be referred to as a NAND address signal (or Y address). In cycle 4 six bits A16 to A21 of the address signal are provided. This address signal will hereinafter be referred to as a block address (or Z address). The address signal A0 to A21 is followed by respective bits D0 to D7 forming the data DAT.sub.1.
As described above, in the case of a memory of the type using the input/output pins both as data input/output pins and as input pins such as address input pins and command input pins, it is necessary to supply different kinds of signals to each of the input/output pins I/O-1 to I/O-8 as shown in FIG. 3. This is a requirement that a memory testing device for this kind of memories is also required to meet; namely, to test this kind of memories, a command signal, an address signal and data need to be input to input/output pins I/O-1 to I/O-8.
As depicted in FIG. 4, the memory testing device is basically made up of: a pattern generator 11; pattern select means 12 that selects various kinds of pattern signals output from the pattern generator 11 to take out pattern data to be provided to each pin;a formatter 13 for converting the pattern data, taken out by the pattern select means 12, to a pattern signal having a real waveform; a driver 14 for applying the pattern signal, generated by the formatter 13, to a memory under test MUT; a level comparator 15 that decides and takes in the logical level of a signal read out of the memory MUT; a logical comparator 16 for comparing the logical level, decided by the level comparator 15, with expectation data; a failure analysis memory 17 which, when a mismatch is detected by the logical comparator 16, that is, when a defective cell is detected in the memory MUT, stores at the address of the defective cell a logical value indicating its defectiveness and reads out and uses the stored value for a failure analysis; a timing signal generator 18 for applying timing signals to the pattern generator 11, the pattern select means 12, the formatter 13, the driver 14, the level comparator 15 and the logical comparator 16; and a tester processor 10 that governs the whole memory testing device.
In FIG. 3, the pattern selector 12, the formatter 13, the driver 14 and the level comparator 15 are each represented by one block, but in practice, each block has channels of the same number as that of pins of the memory MUT so that the pattern signal is fed to each pin.
Conventionally, a control signal that is provided under the control of a program in the tester processor 10 is applied via a data bus DBUS and a control bus CBUS to the pattern selector 12, which selects the pattern signal to be applied to each pin of the memory MUT. Hence, in the case of selecting different kinds of signals such as the command signal, the address signal and the data for each of the input/output pins I/O-1 to I/O-8 as described above, the contents of the program in the tester processor 10 is complex and the preparation of such a program requires much labor and complicated work, and hence it is highly expensive. This will be described below.
In the tester processor 10 there is provided a bus register 10R, in which a pin condition PD of the memory under test is set. The pin condition for the pins I/O-1 to I/O-8 is described, for example, as follows: EQU PD1-8=IN1,XOR,ACLK1,BCLK1,CCLK1,SDM,RDSM<X0-7,Y0-7,D0-7>
IN1 sets the pins I/O-1 to 1/O-8 in an input mode, XOR, ACLK1, BCLK1 and CCLK1 designate waveform combining logic and the kind of clock for use in the formatter 13, SDM designates the generation of the Y address for two successive cycles and RDSM designates the kind of data. <X0-7,YO-7,DO-7> designates the kind of pattern (X address, Y address, data) that is applied to the pins I/O-1 to I/O-8. Since the present invention is related particularly to the kind of pattern mentioned last, the pin condition will hereinafter be expressed merely as PD=<A,B,C,D> That is, in the case of the memory MUT in the example of FIG. 1, a description of a pin condition PD1-8 on the pins I/O-1 . . . , I/O-8 as PD1-8=<X0-7,Y0-7,C0-7,D0-7>, for example, indicates that when the X address is provided to the memory MUT, addresses XO, . . . , X7 are fed to the pins I/O-1, . . . , I/O-8, respectively, and that when the Y address is provided to the memory MUT, addresses Y0, . . . , Y7 are fed to the pins I/O-1, . . . , I/O-8, respectively. The same goes for the cases of commands C0, . . . , C7 and data D0, . . . , D7 are provided to the memory MUT.
In the conventional memory testing device, the description of the pin condition is limited to only three kinds of information because of restrictions on the hardware structure of the device. However, to test recent flash memories of large address sizes, it is necessary to apply the command c, the X address, the Y address, the Z address and the data D to the I/O pins I/O-1 to I/O-8 in a desired sequence as referred to previously with reference to FIG. 2. To meet this requirement, in the prior art, PD1-8=<T0-7,Z0-7,C0-7,D0-7>, for instance, is set as the pin condition in the bus register and prior to the generation of the Y address, for example, in a program for the pattern generation by the pattern generator (an instruction sequence), a multiplexer is controlled to generate the X address X0-7 of one cycle by interruption as described later on. This will be described below with reference to FIG. 5.
FIG. 5 shows, in simplified form, the pattern generator 11 in the conventional memory testing device of FIG. 4 and the formatter 13 provided corresponding to one I/O pin of the MUT. A sequence controller 11A of the pattern generator 11 provides an address of an instruction memory 11B, where an instruction to be executed is described, to an instruction address field 11B1 and generates the next address, following a sequence instruction described at that address. When the address is provided to the instruction address field 11B1 of the instruction memory 11B, instructions/data described in a sequence instruction field 11B2, a test address field 11B3, a test data field 11B4, an MUT field 11B5 and a control field 11B6 corresponding to that address are read out and the instructions are executed, by which data is set. As the result of this, sequence control instructions (INC, NOP, JUMP, etc.) for proceeding to an instruction address to be executed next, described in the sequence instruction field 11B2, are provided to the sequence controller 11A, then addresses in X-, Y- and Z-address calculators 11CX, 11CY and 11CZ of an calculation part 11C are calculated following a calculation instruction in the test address field 11B3, then data in the test data field 11B4 are output to data registers 11D1 and 11D2, then a MUT control signal C in the MUT field 11B5 is output, and selection control signals for a multiplexer 11E and the pattern selector 12 in the control field 11B6 are output. In this way, the pattern generator 11 generates, more than 100 kinds of patterns that are bit sequences of respective pattern data of an address pattern (22 bits, for example,) a data pattern (32 bits, for instance), a command pattern (8 bits, for instance) and so forth, and all the patterns are provided to the pattern selector 12 corresponding to each pin of the MUT.
In FIG. 5 there is shown only one pattern selector 12, but it is provided corresponding to each pin of the MUT. Each pattern selector 12 selects and outputs test patterns of address, data and command that are provided to the corresponding pin of the MUT via the formatter 13 and the driver 14. As indicated by the broken line, the pattern selector 12 also selects and outputs respective bits of expectation data set in the data register 11D2 for logical comparison with data read out of the MUT, but since this is not directly related to the present invention, no description will be given.
A multiplexer 12G of each pattern selector 12 determines which pattern is to be currently applied to the corresponding I/O pin, the X address, Y address, Z address, command C or data D, and which one of the eight I/O pins the pattern selector 12 corresponds to, based on a select signal (X, Y, Z, C, or D) from the control field 11B6 written in a register 12R and the pin condition PD provided from a path register 10R.
Conventionally, the address size of the memory under test is small, for example, 16-bit or less, so that in the case of inputting the address via the pin I/O-1 to I/O-8, for instance, a two-cycle address write (i.e. a write of the X address X0, . . . ,X7 and a write of the Y address Y0, . . . ,Y7) is enough; hence, the pin condition that is preset in the path register 10R needs only to be four kinds of data such as PD=<X0-7,Y0-7,C0-7,D0-7>. However, some of recent flash memories have address sizes larger than 16 bits, in which case the two-cycle address write is not enough to store all address bits. Therefore, the conventional testing device cannot be used to test such large-capacity memories. To settle this problem, it is necessary in the prior art that the description of the pin condition in the bus register set, for example, PD=<Y0-7,Z0-7,C0-7,D0-7>, about four kinds of data as mentioned above and that an instruction step to be stored in the instruction memory 11B be described so that the pattern generator 11 causes an interruption of one cycle for each Y address generating step and controls its multiplexer 11E (see FIG. 5) with the interruption cycle to select and output the X address. Hence, the preparation of the instruction program for the pattern generation is time-consuming accordingly.


The present invention provides a method, system and apparatus for robotic refueling of satellites. The system may include a dedicated refueling satellite launched directly from either earth, or alternatively it could be launched from another larger mother spacecraft or space station in which the refueling satellite is ferried into space in the case of the larger space craft or it may be stored on the space station until needed from which it can be launched. The system includes a robotic arm, suitable tools which can be affixed to the end effector of the robotic arm required for accessing, opening and closing the fuel fill valve on the satellite being serviced, storage and retrieval stations on a tool caddy on which the tools and various fuel fill valve caps are stored. The system is under teleoperation by a remotely located operator, for example located on earth, in the mother station or in the space station. Cameras are included focussed on the robotic arm and end effector and images are transmitted to the operator to allow the operator to direct and control the refueling procedure. The system may also be configured to be operated autonomously under computer control.

Many geosynchronous orbit communication satellites currently in operation were designed with a finite amount of fuel and were not designed for the possibility of being refueled. The design philosophy relied upon replacement of the satellites after they had exhausted the on-board fuel supply. In view of the expense of replacing satellites, it would be very advantageous to be able to refuel communication satellites which are either near their end of life, or have suffered an infant propulsion system failure, thereby extending their operational life by several years.
In many incidents, at the end of a satellite's 10 to 15 year life all of its subsystems are still functional and it is only the depletion of the carefully budgeted fuel load that drives retirement of the satellite. Using a current economic model, the ability to refuel 10 to 12 of these end of life satellites in one mission, would extend their useful life by 3 to 5 years and thereby delay the need to outlay the $150-$250 M to launch a replacement. Some satellites suffer from primary propulsion system failures soon after they are launched. In these cases the entire book value must be written off and compensation paid to the operator by the space insurer. The satellite becomes an asset of the space insurer and will eventually have to be disposed of in a graveyard orbit. If one of these assets can be refueled, extending its life by 5 to 10 years, most of the value of the spacecraft can be recovered.
The key technical difficulty is that these satellites were not designed for robotic servicing, and it is not generally accepted that such missions are technically possible. Specifically, most satellites are designed with fuel fill and drain valves that were intended to be filled once prior to launch and never opened or manipulated again. Thus, accessing these fill and drain valves remotely presents several major challenges and would involve several operations, each of which is difficult to accomplish robotically including: cutting and removal of the protective thermal blankets, removal of several lockwires hand wrapped around the valves, unthreading and removing outer and inner valve caps, mating the fuel fill line to the valve nozzle, mechanically actuating the valve, and when refueling is complete, replacing the inner valve cap.
On-orbit servicing has been the subject of much study over the past thirty years. The idea of maintaining space assets rather than disposing of and replacing them has attracted a variety of ideas and programs. So far the concept has only found a home in the manned space program where some success can be attributed to the Hubble Space Telescope repair missions, Palapa-B2 and Westar rescue missions and the assembly and maintenance of the International Space Station.
Robotic capture and servicing of existing geostationary spacecraft has never been demonstrated. Over the past decade several of the key technologies required for orbital servicing have matured. These include autonomous rendezvous (ETS-VII (1998), XSS-11 (2005), DART (2006), Orbital Express (2007), autonomous docking (ETS-VII, Soyuz, Orbital Express), ground based robotic tele-operation (ETS-VII, SSRMS (2005), Orbital Express), and on orbit fluid transfer (ISS). However a gap exists in the technologies required to service or re-fuel an un-prepared satellite in orbit. An unprepared satellite is defined here as a spacecraft that was not designed to be manipulated or repaired by a robotic system. Some advances have been made in the technologies required to dock with an unprepared satellite, and both DLR (German Aerospace Center) and MDA have demonstrated through various R&D efforts that docking to a GEO communication satellite via the spacecraft's apogee kick motor is a viable docking option.
To date there have been no technologies disclosed that can solve the problem of accessing the fuel system of an unprepared satellite for the purpose of replenishing station keeping fuel. The majority of satellites in orbit today were not designed with orbital refueling in mind and access to the fuel system is designed to be accessed by a human on earth before launch. The technologies required to access the target spacecraft's fuel system for the purposes of refueling still have a very low technology readiness level, and are generally considered to be the main obstacle to a successful servicing mission.
United States Patent Publication No. 2006/0151671 (Kosmos) discloses an actuator arm mounted on a spacecraft designed as a servicing manipulator for use within a spacecraft service bay and includes an actuator arm connected to a base using flexible connection tapes.
United States Patent Publication No. 2006/0151671 discloses a servicing communication architecture in which the communication between a ground station and the servicing satellite is carried out via the communication system of the client satellites communication links. Also disclosed is a general servicing architecture in which target satellites are captured and returned to a servicing spacecraft. Within this servicing spacecraft it is proposed that any required servicing operations could be conducted.
The publication "On-Orbit Servicing by "HERMES On-Orbit-Servicing System, Policy Robust Planning", C. Kosmos, American Institute of Aeronautics and Astronautics, SpaceOps 2006 conference proceedings", pp 1 to 6, Apr. 26, 2006, discloses a satellite refueling architecture that requires each satellite to be serviced to have a custom quick disconnect (QD) coupling attached to its service valve before launch. A preliminary design for a valve access tool used to access this valve is also presented.
Therefore, it would be very advantageous to provide a satellite refueling system for earth-based controlled refueling of unprepared satellites.


A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.

1. Technical Field
The present invention relates generally to memory design evaluation circuits, and more particularly to a memory circuit having a mimicking cell that accurately reflects internal state changes of a memory cell.
2. Description of the Related Art
Storage cell speed, circuit area and environmental operating ranges, e.g., supply voltage and temperature range, are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memory (SRAM) cells are used in processor caches and external storage to provide fast access to data and program instructions. Static storage cells are also used within processors and other digital circuits for storing values internally, for example, in processor registers.
With processor cycle frequencies reaching well above 4 Ghz, development of SHAM cells that can store and provide access to stored values within that period has become necessary. However, actually measuring the internal writeability and write timing margins of memory cells presents a challenge. In a typical storage cell, there is no mechanism for determining writeability and write timing margin, except for empirical evaluation performed by reading the cells after performing write operations under various conditions. If a probe is used to attempt to measure the internal result and timing of a write operation, the probe alters the timing of the cell, yielding incorrect results.
Memory cell transition times involving bitline read operations, sometimes in combination with write operations, have been evaluated using ring oscillator circuits or cascaded cell delay circuits wherein a large number of cells are cascaded. A ring oscillator may be formed with feedback of an output of the last cell to an input of the first cell, or a one-shot delay may be measured through the cascade of cells. The frequency at which the ring oscillator operates or the one-shot delay indicates the transition time performance, which provides some measure of ultimate operating frequency and access times. Typically, the cell design is then changed in subsequent design iterations having parameters adjusted in response to the results of the ring oscillator test.
However, present ring oscillator circuits and other delay-oriented circuits for performing delay tests typically either are not applied on production dies or they do not test the actual storage cells under wordline loading conditions identical to placement of the cells within an array. Further, write cycle measurements are not measured independently, since the inclusion of a cell in the oscillator ring or delay line requires that the cell value will be read in some manner to provide input to the next cell.
It is therefore desirable to provide a test circuit and method for accurately measuring wordline transition times under the complete row loading conditions of an actual array. It would further be desirable to measure access (pass) transistor drive time and internal write state/write timing of a storage cell under actual loading conditions. It is further desirable to provide such a test circuit that can be integrated within a production storage device.

Method for evaluating storage cell design using a wordline timing and cell access detection circuit

International Business Machines Corporation


A reaction of perfluoroolefins with bis(silyl) ethers to produce novel partially fluorinated and perfluorinated copolymers and macrocyclic compounds is disclosed.

1. Field of the Invention
Polymers with high levels of fluorine have novel properties including chemical and thermal resistance.
This invention provides a novel route to fluorinated polyethers by reacting perfluoroolefins with bis(silyl) ethers in the presence of a catalyst to produce partially fluorinated and perfluorinated copolymers and macrocyclic compounds, partially fluorinated bis(vinyl) ethers and perfluorinated bis(alkyl) ethers. The compositions of this invention are useful in vapor phase soldering, as lubricants and as heat stable oils and greases.
2. Technical Background
Hans R. Kricheldorf and Gerhard Bier, Journal of Polymer Science, Polymer Chemistry Edition, Vol. 21, 2283-2289 (1983) disclose the condensation polymerizations of bis(4-fluorphenyl) sulfone with the bis trimethylsilyl derivatives of bisphenol-A, 4,4'-dihydroxydiphenyl, 4,4'-dihydroxydiphenyl sulfone, 1,5-dihydroxynaphthalene, 3-hydroxybenzoic acid, and 4-hydroxybenzoic acid. These polycondensations were only successful when potassium or cesium fluoride was used as a catalyst.
Hans R. Kricheldorf and Gerhard Bier, Polymer, Vol. 25, 1151 (1984) disclose the bulk condensations of 4,4'-difluorobenzophenone and various silylated bisphenols at 220.degree. C.-320.degree. C. with cesium fluoride as a catalyst.
U.S. Pat. No. 4,474,932 discloses and claims a process for the preparation of aromatic ethers or polyethers by reacting aromatic fluorine compounds, in which one or more fluorine substituents are attached to an aromatic nucleus, with trialkylsilyl derivatives of phenols, in which one or more trialkylsilyl groups are attached to the residue of a mono or polyphenol, or by reacting trialkylsilyl derivatives of fluorophenols with elimination of trialkylfluorosilane.
D. G. Saunders, Systhesis; No. 5, Communications, 377 (1988) disloses the reaction of aryl silyl ethers with alkyl halide, or activated aryl halide, and tetrabutylammonium fluoride, to give alkyl aryl ethers or diaryl ethers, respectively. Alkyl silyl ethers under the same or related reaction conditions give mainly the corresponding alcohol, and only very low yields of the ether.
U.S. Pat. No. 3,549,606 claims fluoroalkyl ether polymers of alicyclic fluoroolefins comprised of repeating units of the structure: ##STR1## wherein n=1-7, y is at least 2 and m is a number from 1-12.
U.S. Pat. No. 3,497,563 claims ethers of the formula: ##STR2## wherein:
E is selected from the group consisting of hydrogen, fluorine and --CH.sub.2 OH and may be --CH.sub.2 OH only when T, G and Z are halogen;
G is selected from the group consisting of fluorine and --OCH.sub.2 (CF.sub.2).sub.m D and is fluorine when T is --CH.sub.2 (CF.sub.2).sub.n D;
T is selected from the group consisting of bromine, chlorine and --OCH.sub.2 (CF.sub.2).sub.m D and is a halogen when G and Z are --OCH.sub.2 (CF.sub.2).sub.m D;
Z is selected from the group consisting of fluorine and --OCH.sub.2 (CF.sub.2).sub.m D and is fluorine when T is --OCH.sub.2 (CF.sub.2).sub.m D;
D is selected from the group consisting of hydrogen and fluorine; and
n is a number from 1-7 and each m expression is a number from 1 to 12. That invention also claims a method for producing an unsaturated fluorine containing alicyclic ether by reacting cyclic olefin of the formula: ##STR3## where L is selected from the group consisting of fluorine, bromine and chlorine with a fluoroalkanol, in the presence of an alkali metal hydroxide.

Reaction of perfluoroolefins with Bis (Silyl) ethers to produce fluorinated compounds


A reversible electrical box assembly for mounting an electrical fixture on a ceiling. The electrical box assembly includes a hollow body having a sidewall. The sidewall includes two ends and a center. A flange extends outwards from the sidewall at a location offset from the center thereby dividing the sidewall into a long and short sidewall. A panel is provided for closing either of the ends of the hollow body. The panel can be secured to either the long sidewall or to the short sidewall to create an opposing sidewall of an appropriate length for extending through the ceiling covering at the job site.

Building codes typically call for thicker ceilings in residential construction versus commercial construction. Ceilings in residential buildings typically include one half-inch thickness of drywall whereas commercial buildings typically include two ⅝-inch thicknesses of drywall. Conventional ceiling boxes, which are commonly used for mounting light fixtures or other electrical devices to an overhead surface, typically include a sidewall of a fixed length to accommodate a specified thickness of drywall. When mounted to an overhead support, the fixed length sidewall positions the lower edge of the electrical box roughly even with the lower surface of the drywall, at which level it will be in position to accept the connection of an electrical device thereto.
Unfortunately, as a result of having a fixed length sidewall, a supplier must stock at least two sizes of ceiling box to accommodate both residential and commercial construction requirements. Stocking more than one version of ceiling box therefore decreases inventory space and increases inventory-carrying costs.
What is needed is a ceiling electrical box that can be used for both residential and commercial construction, thereby reduced stocking requirements and providing installers with a more versatile box for satisfying both residential and commercial building needs.

Reversible electrical box for residential and commercial ceiling construction


An image-displaying device includes an image output section, an image data generation section, and a display section. The image output section outputs output data corresponding to an image of a subject. The image data generation section converts the output data to image data by each line and converts image data of a line in a first period. The display section displays the image data the line in a horizontal synchronization period of the display section. The first period is shorter than the horizontal synchronization period.

Technical Field
The present invention relates to an image-displaying device and a display control circuit for displaying an image of a subject on a display section.
Related Art
There are known in the art image-capturing devices for displaying on a liquid crystal display an image captured using an image-capturing sensor. A variety of techniques have been developed in order to prevent the image of the subject on the liquid crystal display from being displayed with any delay. For example, in Japanese Laid-Open Patent Application Publication No. 2007-243615, there is disclosed a technique whereby, in an image-capturing device comprising a VRAM for recording image signals corresponding to a single frame, an image signal is read and displayed on a liquid crystal display before an image signal corresponding to a single frame has been completely written to the VRAM. Specifically, there is described a configuration in which the display of images on the liquid crystal display is commenced at a playback timing that is delayed by a time ΔT with respect to a drive timing at which the image-capturing sensor is driven.

This patent is subject to a terminal disclaimer.

Image-displaying device and display control circuit


A method and system of providing copy protection of video analog and digital signals and the like, wherein the signals are transmitted via a digital delivery network, and may comprise, for example, pay-per-view (PPV) program materials protected by copyrights of respective program rights holders. The right holders authorize video service providers (3) to apply copy protection to the program material. The copy protection process is supplied to the rights holders or the service providers (3) by a copy protection process licensor. The video service providers (3) supply suitable copy protection control software via respective control and billing (tracking) centers to generate commands which activate, control and reconfigure the copy protection process being applied to the programs being transmitted. A set-top box (10) is provided to each consumer and contains a copy protection circuit which is adapted to apply selected anticopy waveforms to the video signal corresponding to the program material in response to the commands from the service providers (3). Usage data pertinent to each consumer is returned by the set-top box (10) to the service providers (3), which then report the copy protection usage to the respective rights holders and process licensor.

1. Field of the Invention
This disclosure is directed to a method of controlling copy protection in digital video networks where it is desired to copy protect an analog or digital video output signal associated with a digital video network.
2. Background of the Invention
Various well known copy protection schemes for video signals include that disclosed in U.S. Pat. No. 4,631,603, John 0. Ryan, Dec. 23, 1986 and assigned to Macrovision Corporation, incorporated by reference, directed to modifying an analog video signal to inhibit making of acceptable video recordings therefrom. This discloses adding a plurality of pulse pairs to the otherwise unused lines of a video signal vertical blanking interval, each pulse pair being a negative-going pulse followed closely by a positive-going pulse. The effect is to confuse AGC (automatic gain control circuitry) of a VCR (video cassette recorder) recording such a signal, so that the recorded signal is unviewable due to the presence of an excessively dark picture when the recorded signal is played back.
Another analog video protection scheme is disclosed in U.S. Pat. No. 4,914,694 issued Apr. 3, 1990, to Leonard, and assigned to Eidak Corp., incorporated by reference. The Eidak system (see Abstract) increases or decreases the length of each video field from the standard length, either by changing the time duration of the respective horizontal line intervals in each field while keeping a constant, standard number of lines per frame, or by changing the number of horizontal line intervals which constitute a frame while maintaining the standard duration of each line interval.
These video protection systems modify the video signal to be recorded (for instance on tape) or to be broadcast (for instance protected pay-per-view television programs) to make copying by ordinary VCRs difficult or impossible. When a video tape on which is recorded the copy protected video signal is played back for viewing using a VCR, the copy protection process is essentially transparent, i.e., it does not interfere with viewing. However, any attempt made to copy the video signal from the tape using a second VCR to record the output of the first (playback) VCR yields a picture degraded to some extent, depending on the efficacy of the particular copy protection system. These present video copy protection systems protect only analog video signals, which are the type of video signals broadcast and recorded using current consumer video technology.
Some digital and hybrid solutions to the copy protection problem were solved by U.S. Pat. No. 5,315,448, issued May 24, 1994, issued to Ryan and assigned to Macrovision Corporation, incorporated by reference. This patent is directed to copy protection for use with digital signal recording where it is desired to copy protect both an analog and digital signal associated with a digital VCR, and any signal material where the original source material is not copy protectable.
FIG. 1 of U.S. Pat. No. 5,315,448, in its upper left portion, illustrates an analog video signal indicated by "A" supplied at input terminal 12 which in turn is coupled to an ACP (anti-copy process) detector 26 and an analog to digital converter 16. When an analog (NTSC) video signal is received at terminal 12, upon detecting the presence of a copy protection signal ACP detector 26 generates a disable recording control signal on line 28. The control signal then disables (for instance) the analog to digital converter. Alternatively, the analog video signal at terminal 12 is converted to the desired digital format at converter 16, which provides a digital video signal "D" at its output.
A fundamental revolution is under way that will dramatically affect the delivery of home entertainment. Consumers will soon have hundreds of viewing options from which to choose because of advances in digital compression technologies and the associated reduction in costs accompanying each advance. Because of the increased number of channels more channels will be allocated for pay-per-view (PPV). The increased number of PPV channels will mean video service providers (VSP), also known as PPV providers or system operators, can provide a greater number of movies and more start times, ultimately changing the way many consumers purchase and view movies in their homes. Already, market research experts are predicting that the pay-per-view business will rival today's videocassette rental and sell-through business within 3-5 years.
Even with such a positive outlook for the future of PPV, the full benefits to the consumer of PPV programming may be delayed unless new digital video networks can protect PPV program copyrights. Rights owners are concerned that when digital programming is delivered to the home any digital set-top box will be able to produce a commercial quality video when recorded by a consumer VCR.

Method and apparatus for providing copy protection using a transmittal mode command


A resonating power transfer system for wireless vehicle lights. A power source supplies a direct electric current to a transmitting power module. A resonator control board and oscillating electric circuit converts the direct electric current into an alternating electric current. A source resonator coil generates an oscillating magnetic field in response to receiving the alternating electric current. A user controller includes a wireless communication transmitter transmits a wireless data signal to a wireless communication receiver. A wireless LED light device includes a receiving resonator coil and a set of LED lights. The receiving resonator coil generates an electric current in a presence of the oscillating magnetic field. The electric current powers the set of LED lights. The wireless communication receiver receives the wireless data signal from the wireless communication transmitter. An LED controller performs a control function on the set of LED lights in response to receiving the data signal.

1. Field of the Invention
The illustrative embodiments relate generally to wireless power transfer, and more particularly, to a method, system, and apparatus for a resonating power transfer system for wireless auxiliary vehicle LED lights.
2. Background Art
An auxiliary vehicle light emitting diode (hereinafter "LED") light is a supplemental LED light or emergency warning LED light that a user may attach to an interior or exterior of a vehicle. Examples of auxiliary vehicle LED lights include, for example and without limitation, a LED dash light, a LED deck light, an emergency LED light bar, a beacon LED light, a LED hideaway light, a LED visor light, a LED mini light bar, and other add-on emergency LED warning light and supplemental vehicle LED lights.
Typically, a user must disassemble multiple parts of the vehicle in order to attach and wire the auxiliary vehicle LED light to the vehicle battery or other vehicle power source, such as a cigarette lighter. Upon completion of the installation and wiring process, the user must reassemble each of the disassembled parts of the vehicle correctly.
For example, installing auxiliary lights on a front grill of a vehicle may require removing the car bumper and drilling holes in the car frame to mount the front grill light. This is a time-consuming and labor-intensive process.
Moreover, the process of installing auxiliary vehicle LED lights frequently results in undesirable cords and wires running from the auxiliary vehicle LED light and the cigarette lighter or vehicle battery. These electrical wires are unsightly, cumbersome, and may distract the driver or passengers within the vehicle.
Thus, the process for installing auxiliary vehicle LED lights in a vehicle is a labor intensive, time-consuming, and arduous process that may result in permanent undesirable modifications to the vehicle and unsightly electrical wires within view of vehicle occupants.

Resonating power transfer for auxiliary vehicle lights


A log debarking chain flail apparatus 10 is illustrated in FIGS. 1 and 2 removing bark from a log 12. The apparatus includes two opposing flail assemblies 18 and 20 having a plurality of chain flails 22 that extend radially outward as the assembly is rotated. Each of the chain flails include a plurality of chain links extending from an inner end 22a to an outer end 22b in which each of the links has a longitudinal segment 46. A tooth 50 is formed on one or more of the longitudinal segments 46 for scraping and/or cutting the bark from the exterior 14 of the log 12.

Chain flails have been used for many years in forestry equipment for removing bank from tree logs and tree trunks.
Apparently, one of the earlier debarking apparatus used for removing bark from tree trunks is disclosed in the F. E. Hummel U.S. Pat. No. 1,670,723 granted May 22, 1928. Such an apparatus shows the use of flail cylinders that are rotated to move flexible chain flail elements into the path and along the surface of the logs or slabs to remove the bark.
Such systems have been particularly useful in removing bark from logs or trunks that are subsequently cut into chips for use in the making of wood pulp products.
The use of chain flails for removing bark has been quite effective particularly for removing bark from softwoods. However, chain flails have had erratic performance for removing bark from the trunks and logs of hardwood trees and from trees that have suffered fire damage in forest fires. Wood chip manufacturers have been particularly conscious of the need to remove as much bark as possible to minimize the amount of bark in the pulp chips in order to obtain the highest prices possible from the wood pulp manufacturer. If a load of wood chips has too high a percentage of chips containing bark, then the chip receives a considerably lower price. Consequently, there has been a substantial need in the market for devices that improve the performance of removing bark from logs and trunks particularly hardwood logs or those that have been subjected to fire damage.
The principal object and advantage of this invention is to provide a chain flail that significantly increases the performance of chain flails in removing bark from logs and trunks particularly hardwood logs and logs that have been subjected to fire damage.
These and other objectives and advantages of this invention will become apparent upon reading the following detailed description of a preferred embodiment.


Aspects of the subject disclosure may include, for example, detecting network traffic of a traffic flow at a traffic controller of a first portion of a software-defined network, wherein the detected network traffic is based on a service of a number of services. A source of the detected network traffic is identified based on the detected traffic, wherein the traffic flow is between a subscriber device and a service platform. The service is identified based on the detected network traffic, and a service requirement is determined based on the identifying of the service. A virtual network function of a plurality of virtual network functions is selected based on the source of the network traffic and the service requirement, and a traffic flow is facilitated between the subscriber device and the service platform by way of the virtual network function. Other embodiments are disclosed.

According to recent trends, individual consumers and families are adopting greater numbers and varieties of network accessible devices and applications that can be used in and around the home. The devices include wired and wireless devices that access network resources according to one or more access technologies. Some examples of access technologies include, cable, fiber, digital subscriber lines (DSL), wireless local area network (LAN), e.g., WiFi, Bluetooth, and mobile cellular, e.g., 3G, 4G.
The devices and applications can be used to access one or more network accessible services, such as broadcast media, voice, messaging, Internet services, and the like. A common residential configuration provides a home or residential gateway device that connects a residential LAN with another network outside of the home, such as an access network and/or a wide area network (WAN), e.g., the Internet. Access to a WAN can be provided via the access network, which can be provided by a carrier service provider, employing transport technologies, such as cable, fiber or DSL.
The term home or residential gateway was originally used to distinguish inexpensive networking devices designated for use in home environments from similar devices used in corporate LAN environments, which traditionally offered a greater array of capabilities. The residential gateway device may include one or more of a cable modem, a DSL modem, a wired router and a wireless access point, a wireless router, a network switch, a Voice over Internet Protocol (VoIP) analog telephone adapter, and the like. Wireless access point and/or router can implement one or more of the IEEE 802.11 wireless protocols.

Method and system for dynamically distributing and controlling a virtual gateway


An electrode system is provided for insertion into an ossified cochlea. The electrode system includes a first electrode array and a second electrode array, both of which are electrically connected to a suitable implantable cochlear stimulator (ICS). Each of the two electrode arrays has a plurality of spaced-apart electrode contacts along one side or surface thereof, e.g., eight to twelve electrode contacts on the first electrode array, and six to ten electrode contacts on the second electrode array. A tunnel is drilled through the ossified portion of the cochlea into which the first electrode array is snugly inserted. The second electrode array is inserted into the cochlea near the second turn thereof. Where the cochlea is fully ossified, a second tunnel is drilled through the ossified portion at the second turn. A positioner may be used with the second electrode array in order to position its electrode contacts against the modiolar wall of the cochlea. The first and second electrodes may be inserted into the scala tympani and/or the scala vestibuli of the cochlea.

The present invention relates to implantable stimulation devices, e.g., cochlear prosthesis used to electrically stimulate the auditory nerve, and more particularly to an electrode array for use within an ossified cochlea in conjunction with a cochlear stimulation system.
Hearing loss, which may be due to many different causes, is igenerally of two types: conductive and sensorineural. Of these, conductive hearing loss occurs where the normal mechanical pathways for sound to reach the hair cells in the cochlea are impeded, for example, by damage to the ossicles. Conductive hearing loss may often be helped by use of conventional hearing aids, which amplify sound so that acoustic information does reach the cochlea and the hair cells. Some types of conductive hearing loss are also amenable to alleviation by surgical procedures.
In many people who are profoundly deaf, however, the reason for their deafness is sensorineural hearing loss. This type of hearing loss is due to the absence or the destruction of the hair cells in the cochlea which are needed to transduce acoustic signals into auditory nerve impulses. These people are unable to derive any benefit from conventional. hearing aid systems, no matter how loud the acoustic stimulus is made, because their mechanisms for transducing sound energy into auditory nerve impulses have been damaged. Thus, in the absence of properly functioning hair cells, there is no way auditory nerve impulses can be generated directly from sounds.
To overcome sensorineural deafness, there have been developed numerous cochlear implant systemsxe2x80x94or cochlear prosthesisxe2x80x94which seek to bypass the hair cells in the cochlear (the hair cells are located in the vicinity of the radially outer wall of the cochlea) by presenting electrical stimulation to the auditory nerve fibers directly, leading to the perception of sound in the brain and an at least partial restoration of hearing function. The common denominator in most of these cochlear prosthesis systems has been the implantation into the cochlea of electrodes which are responsive to suitable external source of electrical stimuli and which are intended to transmit those stimuli to the ganglion cells and thereby to the auditory nerve fibers.
A cochlear prosthesis operates by direct electrical stimulation of the auditory nerve cells, bypassing the defective cochlear hair cells that normally transduce acoustic energy into electrical activity in such nerve cells. In addition to stimulating the nerve cells, the electronic circuitry and the electrode array of the cochlear prosthesis performs the function of the separating the acoustic signal into a number of parallel channels of information, each representing the intensity of a narrow band of frequencies within the acoustic spectrum. Ideally, each channel of information would be conveyed selectively to the subset of auditory nerve cells that normally transmitted information about that frequency band to the brain. Those nerve cells are arranged in an orderly tonotopic sequence, from high frequencies at the basal end of the cochlear spiral to progressively lower frequencies towards the apex. In practice, this goal tends to be difficult to realize because of the anatomy of the cochlea.
Over the past several years, a consensus has generally emerged that the scala tympani, one of the three parallel ducts that, in parallel, make up the spiral-shaped cochlea, provides the best location for implantation of an electrode array used with a cochlear prosthesis. The electrode array to be implanted in this site typically consists of a thin, elongated, flexible carrier containing several longitudinally disposed and separately connected stimulating electrode contacts, perhaps 6-30 in number. In a non-ossified cochlea, such electrode array is pushed into the scala tympani duct to a depth of about 20-30 mm via a surgical opening made in the round window at the basal end of the duct.
Ossification is the formation of bone tissue. An ossified cochlea is thus a cochlea wherein the scala tympani duct, and/or other ducts within the cochlea, are filled completely or partially with bone growth tissue. Needless to say, it is not possible to insert an electrode into an ossified cochlea using conventional insertion techniques because the bone growth tissue blocks such insertion. Thus, there is a need for an effective cochlear electrode system which can be used for patients with ossification, whether such ossification only extends to the first turn of the scala tympani duct (partial ossified cochlea) or whether the ossification fills the entire scala tympani duct (fully ossified cochlea).
The present invention addresses the above and other needs by providing an electrode system for insertion into an ossified cochlea. Heretofore, there have been no electrode systems of which applicants are aware that have satisfactorily been useable with an ossified cochlea. Thus, heretofore, those patients having an ossified cochlea have not been able to benefit from implantation of a cochlear prosthesis.
The electrode system of the present invention includes a first electrode array and a second electrode array, both of which are electrically connected to a suitable implantable cochlear stimulator (ICS). Each of the two electrode arrays has a plurality of spaced-apart electrode contacts thereon, e.g., eight to twelve electrode contacts on the first electrode array, and six to eight electrode contacts on the second electrode array.
Where the cochlea is partially ossified, e.g., only up through the first turn of the scala tympani duct, a straight tunnel is drilled through the bone formation in the ossified scala tympani. This tunnel typically has a diameter of approximately 2 mm and a length of about 8-10 mm. The first electrode array is then inserted into this straight tunnel. The second electrode array is then placed through an additional cochleostomy drilled at the beginning of the second turn of the cochlea. An electrode positioner of the type disclosed in applicant Kuzma""s copending patent application, Ser. No. 09/140,034, filed Aug. 26, 1998, incorporated herein by reference, may be used with this second electrode in order to assure that the second electrode hugs the modiolus of the cochlea as much as possible.
Where the cochlea is completely ossified, e.g., ossified through the second turn of the cochlea, a second tunnel is drilled through the ossification at the second turn of the cochlea, and the second electrode is inserted into this second tunnel. As needed, an electrode positioner may be inserted with the second-electrode in order to assure that the second electrode hugs the modiolus of the electrode.
For some patients, depending upon the degree of ossification, it may be desirable to insert the one or the two electrodes into a tunnel drilled in the ossified scala tympani, as described above, and to insert the other of the two electrodes into the scala vestibule.
It is thus an object of the present invention to provide an electrode system that may be used within an ossified cochlea.
It is an additional object of the invention to provide such an electrode system that, when used with a cochlear stimulation system, affords a patient having an ossified cochlea the opportunity to hearxe2x80x94an opportunity which heretofore has not been possible.


A thermal transfer recording sheet comprising a support having thereon a thermal transfer image-receiving layer, said support comprising a thermoplastic resin film containing from 3 to 60% by weight of a petroleum resin, where the thermoplastic resin film is preferably a microvoid-containing film, and the thermal transfer recording sheet exhibits excellent surface smoothness and, in case of a microvoid-containing support, also exhibits excellent cushioning properties so that the recording sheet has improved contact with a thermal head to provide a transferred image rich in gradation and which does not curl even after thermal recording.

Thermal transfer recording is generally carried out by heating a transfer recording material comprising a support having thereon a color forming layer containing a sublimable or vaporizable dye to sublime or vaporize the dye and transferring the dye to an image-receiving sheet to form a dye image.
More specifically, as shown in the FIGURE of the accompanying drawing, transfer recording material 1 and image-receiving sheet 2 composed of image-receiving layer 6 and support 7 are interposed between drum 8 and heating source 3, and color forming layer 5 of transfer recording material 1 is heated from a side of support 4 opposite to the side on which the color former layer 5 is present using an electrically-controlled heat source, such as a thermal head to sublime or vaporize the dye present in color forming layer 5. The sublimed or vaporized dye is thus transferred to image-receiving layer 6 to achieve thermal transfer recording.
The material forming image-receiving layer 6 is selected depending on the kind of the color former to be transferred thereto. For example, in using a heat-fusible color former, support 7 by itself can serve as an image-receiving layer. In using a sublimable disperse dye as a color former, a coated layer comprising a high molecular weight polymer, such as polyesters, may be used as an image-receiving layer.
However, conventional image-receiving recording sheet 2 has a surface roughness of from 5 to 15 .mu.m or a thickness variation of from 10 to 20 .mu.m per mm due to the thickness unevenness or surface roughness of support 7. This roughness or unevenness may be reduced by super-calendering to some extent but the extent is limited, and a roughness of from 3 to 5 .mu.m or unevenness of 10 .mu.m or more per mm still remains on the supercalendered surface. As a result, accurate dye transfer corresponding to image signals cannot be achieved even with sublimable color formers, and even less so with heat-fusible color formers. As a result, the resulting image suffers from defects, such as dot disappearance or deficiency, and roughness in intermediate tone.
Currently employed supports for the image-receiving layer include paper, opaque synthetic paper comprising a stretched film of a propylene resin containing an inorganic fine powder (see U.S. Pat. No. 4,318,950, JP-B-46-40794, the term "JP-B" as used herein means an "examined published Japanese patent application"), and coated synthetic paper comprising a transparent polyethylene terephthalate film or a transparent polyolefin film having coated thereon an inorganic compound, e.g., silica or calcium carbonate, dispersed in a binder to increase the whiteness and dyeability.
Considering after-use characteristics of an image-receiving recording sheet with a transferred dye image as to, for example, copying suitability, pencil writability, and record preservability, it is accepted that a synthetic paper comprising a void-containing stretched film of a polyolefin resin containing an inorganic fine powder is preferred as a support from the standpoint of strength, dimensional stability, and contact with a printing head, as disclosed in JP-A-60-245593, JP-A-61-112693 and JP-A-63-193836 (the term "JP-A" as used herein means an "unexamined published Japanese patent application").
In this type of synthetic paper obtained by stretching a polyolefin resin film, microvoids are formed in the film by stretching the film at a temperature lower than the melting point of the polyolefin resin so as to achieve opacity, softness to the feel, intimate contact with a printing head, and smoothness in paper feeding or discharge.
The surface temperature of an image-receiving sheet on transfer recording reaches, momentarily, 190.degree. to 200.degree. C. However, the melting point of the polyolefin resin film is 167.degree. C. or less, which is considerably lower than that of polyethylene terephthalate or a polyamide (240.degree. to 255.degree. C.). As a result, the image-receiving recording sheet with a transferred dye image thereon tends to curl inward due to the heat involved in transfer recording as disclosed in JP-A-60-245593 and JP-A-61-283593.
In order to prevent curling, a polyolefin resin film may be laminated with other base resin film and the stretching temperature can be set in the vicinity of the melting point of the base resin. In this case, however, the base resin has reduced opacity and reduced softness to the feel.


The present invention relates to a process for preparing a porphyrin of formula (I), optionally in the form of a salt with an alkali metal and/or in the form of a metal complex:

1. Field of the Invention
The present invention relates to a novel process for preparing porphyrin derivatives, such as protoporphyrin (IX), and also to intermediates for the synthesis of these compounds.
2. Summary of the Related Art
Certain porphyrins are known and used for their biological or medical properties. By way of example, mention may be made of the following porphyrins of formula:
                in which:        Ra═—CH═CH2, then named protoporphyrin IX,        Ra═—CH2CH3, then named mesoporphyrin,        Ra═—CH(OH)CH3, then named hematoporphyrin,        Ra═H, then named deuteroporphyrin,        Ra═—CH2CH2COORb with Rb being a hydrogen atom or a methyl, ethyl, n-propyl or i-propyl group, then named coproporphyrin III,        Ra═—C(O)CH3, then named diacetyldeuteroporphyrin.
These porphyrins can be used in the form of salts, for example of a salt with an alkali metal at the two acid functions, such as a sodium salt.
It is also possible, depending on the applications, for these porphyrins to be used in a complexed form, for example complexed with a metal such as Fe, or alternatively a metal salt such as FeCl or FeOH. The complex of protoporphyrin IX with Fe is called heme, that with FeOH is called hematin and that with FeCl is called hemin.
These porphyrins are most commonly prepared by hemisynthesis, which poses the problem of impurities of animal origin, in particular, that may be present. For certain applications, for example in the case of protoporphyrin (IX), or of its sodium salt, which may be used in cell culture media, the desire is to provide a completely synthetic preparation process which uses only products of synthetic origin. Certain processes of preparation by chemical synthesis of these compounds have already been proposed. The publications in J C S Perkin I, 1974, 1771-1781 and 1188-1194, for example, describe the preparation of protoporphyrin IX. A known method for preparing protoporphyrin, to which reference is made in these publications, is referred to as the MacDonald process and consists in coupling, in the presence of a metal cation M+ such as Zn2+ or Fe3+, the following two pyrromethanes (A) and (B):
                so as to give a porphodimethane structure (C):
                which must subsequently be oxidized so as to form the metalated porphyrin (D):

Such a method is in particular described in Science of Synthesis Houben-Weyl, vol. 17, 1081-1235 and in The porphyrin Handbook, vol. 1, synthesis and Chemistry, Academic Press, Boston, 2000.
It is subsequently necessary to demetalize the porphyrin, in the presence of sulfuric acid, if said porphyrin must be used in free form. The latter step in particular is not quantitative and the porphyrin obtained does not have a satisfactory degree of purity. The high —C(O)CH3 function must also be converted to —CH═CH2.

Process for preparing porphyrin derivatives, such as protoporphyrin (IX) and synthesis intermediates

Abstract: in which:                R and R′ are as defined in claim 1,comprising:        a step of condensation, in an acidic medium, between a dipyrromethane of formula (II):

Abstract: in which R′b is as defined above for (I),and a dipyrromethane of formula (III):

Abstract: in which R″ is as defined in claim 1, and also the compounds of formula (III).


A display application rotates content to provide a perspective view along the z-axis during a scroll action as a feedback to a user indicating a scroll action has reached a beginning or an end of available content. Determined direction and speed and/or acceleration of the scroll action is applied to move content and rotate it based on: a tilt angle proportional to the speed and/or acceleration and a rotation axis perpendicular to the direction. Additional content is displayed in the perspective view based on the tilt angle. And, the tilt angle is adjusted to rotate the content in response to reaching an end of the content during the scroll action or upon detecting a subsequent scroll action.

Mobile computing has transformed media consumption across markets. Miniaturization across product generations has enabled more functionality to be accomplished by smaller devices. A modern smartphone has more computing capacity than a desktop computer a few years ago. Mature product processes have also enabled advances in technology to be integrated to automated production of mobile devices seamlessly. Extensive automation has led to inexpensive components. Inexpensive components have enabled manufacturing of inexpensive mobile devices providing functionality on the go.
Screen real estate is a substantial factor in content presentation within mobile computing. Minimal screen size in mobile devices may limit content presentation and force partitioning and formatting of content to suit the physical limitations. Dynamic orientation changes also force content providers to consider presentation formatting to suit device orientation. Formatting in landscape and portrait modes become crucial for content consumption through mobile devices in order to accommodate users constantly shifting their content consumption habits.
In legacy solutions, content applications provide scroll bars for users to bring to view content that does not fit on a screen. In mobile solutions, scroll bars utilize limited screen real estate. Additionally, content displayed on a screen is presented in a constant size during a scroll action in legacy implementations. Present solutions also are limited in responding to reaching an end of the content during a scroll action. Some solutions simply stop moving the content in response to reaching an end. Others use a spring effect to notify the user that no additional content exists. No present solution adequately solves issues of presenting richer content during scrolling or proper notification about reaching an end of the content.

Providing content rotation during scroll action


An aspect of the present invention relates to a method of manufacturing a vinyl polymer, which comprises: mixing a first liquid and a second liquid to conduct an addition reaction, wherein the first liquid has been obtained by reacting a sulfonic acid group-containing compound selected from the group consisting of taurine, N-methyl taurine, and meta-aminobenzenesulfonic acid with an alkali metal hydroxide in methanol, the second liquid comprises a vinyl polymer having an intramolecular epoxy group in a ketone solvent, and the addition reaction incorporates a sulfonic acid alkali metal salt group onto a side chain of the vinyl polymer.

1. Field of the Invention
The present invention relates to a vinyl polymer and to a method of manufacturing the same. More particularly, the present invention relates to a vinyl polymer that is suitable as a binder in a particulate magnetic recording medium, and to a method of manufacturing the same.
Still further, the present invention relates to a binder composition for a magnetic recording medium containing the above vinyl polymer, and to a magnetic recording medium and method of manufacturing the same.
2. Discussion of the Background
In recent years, means of transmitting information at high speed have become highly developed, permitting the transmission of data and images consisting of huge amounts of information. With advances in data transmission techniques, higher density recording capability has been demanded in recording media and recording and reproduction devices for recording, reproducing, and storing information.
Employing microparticulate magnetic powder, dispersing the microparticulate powder to a high degree, and increasing the smoothness of the surface of the magnetic layer are effective ways of achieving good electromagnetic characteristics in the high-density recording region. The method of incorporating a sulfonic acid (salt) group such as a SO3Na group into the binder is a known means of increasing the dispersibility of a microparticulate magnetic powder. In the present specification and the present invention, the term "sulfonic acid (salt) group" is used to include sulfonic acid groups and salts of sulfonic acid groups.
As methods of incorporating a sulfonic acid (salt) group into a vinyl polymer that is widely employed as a binder in magnetic recording media, Japanese Examined Patent Publication (KOKOKU) Heisei No. 1-26627 (Reference 1) proposes the combined use of starting material monomers in the form of a monomer containing a sulfonic acid (salt) group and a monomer containing an epoxy group, and using an addition reaction to incorporate the monomer containing the sulfonic acid (salt) group onto the monomer containing the epoxy group. Japanese Unexamined Patent Publication (KOKAI) Showa No. 60-238306 (Reference 2) proposes the method of introducing a sulfonic acid (salt) group by conducting an addition reaction with an epoxy group-containing vinyl chloride polymer in a water-based solvent. The contents of References 1 and 2 as well as their English language family member U.S. Pat. No. 4,707,411 are expressly incorporated herein by reference in their entirety.
The vinyl polymers obtained by the methods described in References 1 and 2 have sulfonic acid (salt) groups in the form of adsorbed functional groups as side chains. When these adsorb to the surface of the magnetic powder, it becomes possible to prevent aggregation of the magnetic powder and decreased dispersibility. However, the methods described in References 1 and 2 present the following problems in terms of synthesis.
As is described in Reference 1, when an addition reaction is conducted on a monomer containing an epoxy group, a bifunctional monomer is produced. When it is used in a polymerization reaction, a vinyl polymer with a multidimensional crosslinked structure is obtained that in turn causes gelling during polymerization and the like, making it difficult to control the reaction.
Reference 2 describes conducting a sulfonic acid (salt) group addition reaction in an aqueous system. However, in cases where crosslinking using an isocyanate curing agent is employed in the magnetic recording medium to increase the coating strength and the like, and a large amount of water is present, the isocyanate curing agent crosslinks with the water, compromising reactivity with the binder. Thus, it becomes difficult to obtain a strong coating despite using an isocyanate curing agent. Accordingly, binder resins that have been synthesized in an aqueous system such as that described in Reference 2 are not employed to prepare coating liquids for forming magnetic recording media as is, but require a drying step or the like, such as is done in Examples in Reference 2, to remove the water.
As set forth above, the methods of manufacturing vinyl polymers containing sulfonic acid (salt) groups that have been previously proposed present problems in terms of synthesis.


Spectrum data of white neutrons having different spectrum shapes, and SEE counts obtained by a white neutron method using this multiple spectrum data, are stored. A computing section reads out the spectrum data, divides the data into energy groups, and calculates and stores a total flux of each energy group. Furthermore, the computing section reads out the SEE counts with respect to each of the spectrum data and the total flux of each energy group, substitutes the SEE counts and the total flux into a simultaneous equation, and calculates the SEE cross section for each of the energy groups. Subsequently, the computing section calculates parameters which determine a formula of the approximate function of the SEE cross section as a function of energy, so that computed values of error counts obtained by integration of multiple spectra and the approximate function sufficiently match the actual measured values thereof.

The present invention relates to a semiconductor device error evaluation support technique, and more particularly, it relates to a technique to calculate, as a function of neutron energy, a rate of error occurrence in the semiconductor device, the error being caused by neutrons.
In recent years, remarkable progress is made on high integration of semiconductor device such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Concurrent with the high integration of semiconductor device in these years, a trend for reduction in size of a memory cell is in progress. Accordingly, electrostatic capacitance becomes smaller, and it is increasingly difficult to keep high reliability against soft errors, which are generally caused by alpha rays, neutron beams or the like (for example, see F. J. Ziegler, IBM J. Res. Develop., Vol. 40, No. 1, 1996, pp. 19-29, hereinafter referred to as "Non-patent Document 1"). Here, the term "soft error" means a phenomenon that information stored in a memory cell is inverted. For example, it indicates a phenomenon that electric charge generated in a semiconductor memory device due to alpha rays, neutron beams or the like is collected in a storage node (a diffusion layer part to hold data), under the influence of an electric field substantially associated with PN junction, and information "1" written in the memory cell is rewritten by information "zero".
Soft errors are temporal non-destructive events, but there is also a concern for hard errors (destructive events) to increase concurrent with a finer structure and higher integration of the semiconductor device (for example, see IEEE Transactions on Nuclear Science, Vol. 45, No. 6, pp. 2492-2499 (1998), IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2373-2379 (2000), and IEEE Transactions on Nuclear Science, Vol. 47, No. 6, pp. 2640-2647 (2000), which will be referred to as "Non-patent Documents 2, 3 and 4", respectively). It is to be noted that an error (event) caused by the incidence of one particle, such as an ion and neutron, into the semiconductor device, is referred to as "SEE (Single Event Effect)".
By the way, soft errors caused by alpha rays were recognized at the end 1970's. The alpha rays are emitted from radioactive isotopes such as uranium (U) and thorium (Th), which are contained in minute quantities in a wiring material or in a packaging material constituting the semiconductor device. In 1980's, following solutions were suggested in order to enhance resistivity against the soft errors caused by the alpha rays. With the following solutions, it is thought that almost all the soft error problems caused by the alpha rays have been solved.
Solution 1:
Highly purified Materials used for the semiconductor device.
Solution 2:
Shielding alpha rays from the packaging material such as a polyimide layer or the like.
Solution 3:
Increasing or keeping electrostatic capacitance of memory devices high enough.
Solution 4:
Contrive a well structure of the semiconductor device by installing a barrier layer or the like against generated carrier.
In the meantime, possibility of soft errors caused by cosmic ray neutrons was pointed out at the end 1970's around the same time when the soft errors caused by the alpha rays were found. A principle of the soft errors caused by cosmic ray neutrons will be explained in the following.
A neutron arriving to the ground is a secondary neutron with an extremely high energy at the order of several MeV to GeV, which has been generated by a reaction between the high-energy cosmic ray and atomic nucleus such as oxygen, contained in the air. FIG. 14 is an illustration to schematically explain the principle of the soft errors caused by the cosmic ray neutrons, and it shows a cross sectional structure of a general semiconductor device (DRAM).
As illustrated, when the cosmic ray neutron 1 with high energy comes into the semiconductor device, it enters an atomic nucleus of an atom constituting the semiconductor device with a certain probability. Then, within an extremely short period of time, a cascade of elastic scattering takes place between the cosmic ray neutron and intra-nucleus nucleons (neutron and proton), and as a result, a nucleon having sufficient kinetic energy against the nucleus potential is emitted out of the nucleus. After all the releasable nucleons have been emitted, other nucleons and leptons such as deuteron and helium "evaporate" out of the nucleus, using the sum of the remaining kinetic energy as excitation energy. The above serial processing is called as nuclear spallation reaction (1a). For example, a proton and secondary ions 2 having all the atomic numbers from alpha particle up to 29Si (in which 28Si spins out of the lattice position, keeping the neutron absorbed therein) are generated from 28Si atomic nucleus.
Next, the secondary ion 2 generates electron hole pairs 6a in the number corresponding to its energy, and simultaneously moves within the semiconductor device. When the secondary ion 2 passes through a storage node 3, which is a diffusion layer part holding data, an electric charge generated within the field outside the storage node 3 flows along the electric field. Therefore, the charge is collected into the storage node 3. An area to which the charge is collected in the storage node 3 is referred to as a charge collection area. It is to be noted here that the electric field includes a depletion layer 4 positioned outside the storage node 3, and an area 6 called funneling, positioned within the well area 5 including the storage node 3, the area 6 being generated by extension of the electric field of the depletion layer 4.
The semiconductor device as shown in FIG. 14 represents a DRAM where a capacitor 7 is added onto the storage node 3. In many cases, the DRAM has a triple well structure, in which a lower circumference of the storage node 3 (in general, it is n-type semiconductor) is covered with a well 5 being a semiconductor having opposite polarity, and the outside thereof is surrounded by a substrate 8 being a semiconductor having the same polarity as that of the storage node 3. In other words, PN junction is found on both sides, i.e., on the storage node 3 side and on the substrate 8 side, and when the secondary ion 2 penetrates into the storage node 3, the well 5 and the substrate 8, funneling extends also from the PN junction on the substrate 8 side. Therefore, almost half of the generated electric charge is collected into the storage node 3 via the depletion layer 4, and the remaining half is collected into the substrate 8 via the depletion layer 4a. Therefore, for example, if the secondary ion 2 penetrates into the storage node 3, the well 5 and the substrate 8, and consequently electric charge is collected into the storage node 3 where data "1" is stored, the data "1" stored in the storage node 3 is reversed to data "0" when the collected electric charge exceeds a certain amount (referred to as "critical charge").
The principle of the soft errors caused by the cosmic ray neutrons is basically the same as the case of the alpha ray-induced soft errors. However, in the case where the soft errors are caused by a high energy neutron, it is principally different from the case of the alpha ray-induced error in the following points.
Difference 1:
Energy of generated secondary ions is high.
Difference 2:
Scattering directions of the secondary ions are isotropic.
Here, the above Difference 1 indicates that the electric charge amount generated within the semiconductor device is large, compared to the case of the alpha rays. Therefore, soft errors may easily occur in a semiconductor device in which the storage node 3 has a small critical charge. In addition, the above Difference 2 indicates a possibility that the secondary ions 2 may scatter into all the directions from the storage node 3. Therefore, a polyimide shielding (chip coating) conventionally used as a countermeasure against the alpha ray-induced soft errors is not sufficient as a countermeasure against the neutron-induced soft errors.
In the meantime, it is expected that finer structure and lower operational voltage of a semiconductor device will proceed further in the future without halt for the sake of achieving considerable increase in capacity and lower power consumption. However, as an obstacle in the move towards finer structure and lower operational voltage of the semiconductor device, an issue in terms of how to keep electrostatic capacitance held by the storage node in order to maintain the critical charge at a high level can be mentioned.
As the critical charge becomes smaller, resistivity against the soft errors caused by cosmic ray neutrons becomes lower. In view of this situation, a primary importance has conventionally been placed on keeping a certain critical charge high by enlarging the electrostatic capacitance of the storage node, and it is considered to be one of "common practices" in structural design of semiconductor device. As is well known, in DRAM, a condenser is made within a device, so as to keep electrostatic capacitance high. However, due to a decrease in cell area concurrent with the finer structure, a high conductivity material such as Ta2O5 is employed for the condenser. Employing such an expensive material and developing an adaptation process for the material have resulted in a high cost and spending manpower. In the case of SRAM, generally, a condenser is not made within the device, unlike the case of DRAM. Concurrent with finer structure of the device, the electrostatic capacitance of the storage node is kept decreased, and this situation leaves constraint on replacing material of interlayer insulation film to be a lower dielectric constant material.
On the other hand, since spacing between parasitic transistors becomes smaller as the structure becomes finer, a parasitic thyristor is turned on, thereby causing hard errors, which are reported as a way of example, such as latch up allowing a large current to flow, and SEGR (Single Event Gate Rupture) where the secondary ions remarkably increase an electrostatic field in the proximity of a gate oxide, resulting in a destroy of the oxide film. This may place a constraint on making a gate oxide film further thinner, which is required for finer structure and lower operational voltage of the semiconductor device.
Considering the problems above, it is important to evaluate errors caused by cosmic ray neutrons in a semiconductor device, and to reflect the evaluation result on designing the semiconductor device. Table 1 shows experimental methods to evaluate error resistivity of the semiconductor device.
TABLE 1CLASSIFICATION OFADVANTAGES/METHODSFEATURESDISADVANTAGESNEUTRONFIELDDevicePeriod forIRRADIATIONTESTINGresistivity candeviceMETHODbe directlyevaluation isevaluated.long.Obtainingdata from awide range andwith precisionis difficult.WHITESpectrum similarLimitedNEUTRONto that of cosmicfacility forMETHODray neutron isuse (e.g.used, and deviceLANSCE, RCNP).resistivity canbe evaluatedwithin a shortperiod.(QUASI-)(Quasi-)LimitedMONO-ENERGY)mono-energyfacility forNEUTRONneutron is used.use (e.g. TSL,METHODSpectrum ofTohoku Univ.cosmic rayCylic., RCNP).neutrons isLow fluxsuperimposed forTailintegration andcorrection isdevicenecessary.resistivity isevaluated.Usable as a basisfor a wide rangeof evaluation.PROTON IRRADIATIONDosimetry isEquivalencyMETHODeasier thanwith neutronneutron.irradiationhas not beenverified yet.HEAVY ION IRRADIATIONEvaluate a deviceOverallMETHODfor earthevaluation ofsatellitesecondary ionSuitable forincludingquantification ofunstableinfluence bynuclide is notindividualpossible.secondary ions
As shown in Table 1, there are experimental methods to evaluate error resistivity of semiconductor device, such as a neutron irradiation method to obtain an error rate by irradiating neutrons onto the semiconductor device, a proton irradiation method to obtain an error rate by irradiating protons instead of neutrons onto the semiconductor device, and a heavy ion irradiation method to obtain an error rate by irradiating heavy ions onto the semiconductor device, the heavy ions being generated by nuclear reaction between neutrons and atomic nuclei of the semiconductor device material.
Here, a general index to evaluate the error resistivity is called SEE (Single Event Effect) cross section (in the case of soft errors, it is called SEU (Single Event Upset) cross section). In general, it is defined by the following equation as a function of incident particle energy E.
                              σ                                (            E            )                          =                                                            N                err                                                          (                E                )                                                                    ϕ                                                  (                  E                  )                                                                          T                irr                                              =                                                    N                err                                                          (                E                )                                                    ψ                                            (                E                )                                                                        [                  EQUATION                                                              1                ]
Here, Φ(E) denotes the number of neutrons incident to a unit area within a unit time (Flux), Tirr denotes an irradiating time, Ψ(E) denotes total number (Fluence) of neutrons incident to the unit area within the irradiating time Tirr, Nerr(E) denotes the number of errors occurred with respect to one device. Nerr(E) may also be defined as the number of errors occurred with respect to one bit. Here, σ(E) denotes the SEE cross section in which an error rate is expressed as an area, the error being generated by one neutron having energy E incident on the semiconductor device.
FIG. 15 shows a relationship between neutron energy (MeV) in a semiconductor device (SRAM) and SEE cross section (cm2). As understood from the graph indicated by the reference numeral 16, neutron energy E has a threshold value Eth in association with a threshold of nuclear spallation reaction. In other words, there is no possibility that an error in the semiconductor device occurs against a neutron having energy smaller than the threshold value Eth. Typically, the SEE cross section σ(E) is saturated with a value σ∞, which is in the higher energy side of the neutron energy E. It is to be noted that there is another report example where the SEE cross section is not saturated in the higher energy side of the neutron energy E, but it is rather reduced. Typically, the unit of flux Φ(E) is "number of incident particles/cm2/s", and the unit of the fluence Ψ(E) is "number of incident particles/cm2. When the error rate SER (Single Event Error) in the environment, where the semiconductor device is actually used, is represented by a unit of FIT (Failure In Time), the SER is defined by the EQUATION 2 utilizing the SEE cross section σ(E). Here, when one error occurs every 109 hours, it is defined as "1 FIT".
                              SER                                (            FIT            )                          =                  3.6          ×                      10            12                                                        ∫                              E                th                            ∞                                                                  σ                                                  (                  E                  )                                                                                ⅆ                                      ϕ                                                              (                      E                      )                                                                                ⅆ                  E                                                                                ⅆ                E                                                                        [                  EQUATION                                                              2                ]
In the meantime, the proton irradiation method, as one of the above experimental methods to evaluate an error resistivity of the semiconductor device as shown in Table 1, is based on the premise that the proton and the neutron are a kind of twin particles being different only in isotopic spin, and the nuclear reaction for the two is physically equivalent except the Coulomb barrier. However, in practice, there is not much data showing that the proton and the neutron give the same error rate. Therefore, it is not possible to say that whether or not the error evaluation method using the proton is equivalent to the method using the neutron has already been verified. The heavy ion irradiation method is suitable for a physical mechanism study. However, when the neutrons and Si atomic nuclei, for example, are subjected to nuclear reaction, several dozen of nuclides are generated, including radioactive isotopes with a short life. Therefore, in fact, it is impossible to evaluate an actual error rate against the cosmic ray neutrons.
With the reasons as described above, it is thought that neutron irradiation method is suitable for evaluating an error rate of the semiconductor device caused by the cosmic ray neutrons. Here, as shown in Table 1, the neutron irradiation method is classified into field testing, white neutron method, (quasi-) mono-energy neutron method. The field testing is a method in which the semiconductor devices are placed on the ground to be operated thereon and errors caused by actual cosmic ray neutrons are directly measured. The white neutron method is a method which irradiates high-speed protons onto a tungsten block and the like, generates white neutrons having a spectrum with a shape analogous to a shape of cosmic ray neutron spectrum, and applies the white neutrons to the semiconductor device to measure errors (see International Electron Devices Meeting, San Francisco, Calif., Dec. 6-9, 1998, pp. 367-370 (1998), and Nuclear Science and Engineering, Vol. 106, pp. 208-218 (1990), which will be referred to as "Non-patent Documents 5 and 6", respectively). The (quasi-) mono-energy neutron method is a method which irradiates high-speed protons to an Li plate, generates (quasi-) mono-energy neutrons, and measures errors by applying thus generated neutrons to the semiconductor device (for example, see International Conference on Information Technology and Application, Bathurst, No. 273-21 (2002), which will be referred to as "Non-patent Document 7).
The field testing as one of the neutron irradiation methods requires a period from at least half a year to one year or longer in order to obtain data statistically meaningful, even if around 1,000 units of semiconductor devices are used. In addition, cost for this method is expensive. Therefore, even if the field testing is necessary for simulation or verifying accelerating test, it is not practical to carry out this method for all the semiconductor devices prior to mass production thereof.
With the reasons as described above, it is thought that the white neutron method or the (quasi-) mono-energy neutron method is suitable for evaluating the error rate in the semiconductor device caused by the cosmic ray neutrons, those methods using neutrons outputted from an accelerator.

Method for evaluating semiconductor device error and system for supporting the same


A system for selectively supplying air between separate plena of a gas turbine engine includes a gas turbine engine, a door, and a bi-metallic door actuator. The gas turbine engine comprises at least a first plenum and a second plenum, and has an opening between the first plenum and the second plenum. The is door mounted in the gas turbine engine and is movable between a closed position, in which air is prevented from flowing through the opening, and an open position, in which air may flow though the opening. The bi-metallic door actuator is coupled to the door and is configured to selectively move the door between the closed position and the open position.

In the field of gas turbine technology a great deal of effort has been, and continues to be, directed toward improving thermodynamic efficiency by operating gas turbine engines at ever increasing temperatures. These temperatures may exceed the temperatures that some materials within the turbine engine structure can normally tolerate. As such, cooling air may be provided to various turbine engine components using cooling air extracted from other parts of the engine. For example, in some gas turbine engines cooling air is extracted from a plenum at the discharge of the compressor, and is then directed to certain portions of the turbine.
For some gas turbine engines, the air that is extracted from the engine for turbine cooling may be at temperatures that require the air to be cooled before being directed to the turbine. In some turbofan gas turbine propulsion engines, a portion of the fan air flowing in the bypass duct may be continuously redirected and used to cool the extracted turbine cooling air. During some operational levels of the turbofan engine, fan air is not needed to adequately cool the extracted air, resulting in parasitic losses. Thus, there has been a long-felt need for a system that will controllably direct fan air to adequately cool air that is extracted for turbine cooling air, while substantially reducing, if not eliminating, parasitic engine losses. However, heretofore such systems have not been implemented due to the relatively complex, heavy, and costly actuation schemes associated therewith.
Hence, there is a need for a system that will controllably direct fan air (and other sources of air in a gas turbine engine) to various pneumatic loads that does not rely on relatively complex, heavy, and costly actuators or actuator controls. The present invention addresses at least this need.

Bi-metallic actuator for selectively controlling air flow between plena in a gas turbine engine


A gear assembly including a first gear including a rim and a plurality of teeth. The plurality of teeth is configured to contact one or more of another plurality of teeth. A non-axisymmetric structure is defined at the rim. The non-axisymmetric structure is a non-contacting structure of the gear assembly.

Mechanical and electro-mechanical systems, such as turbine engines including industrial and aviation gas turbines and wind turbines, include gear assemblies to change an input or output rotational speed between two or more shafts such as to optimize turbine engine efficiency and performance. However, non-constant transmission of motion between mating gears is known to be a significant source of undesired excitation gear assembly vibrations. Such vibrations may deteriorate overall system performance, such as via limiting operational speeds or requiring additional dampers to attenuate excitation which may increase system weight, thereby otherwise decreasing system performance and efficiency.
While it is known to optimize engaging gear tooth geometry to minimize excitation effects, this approach is limited due to bending stresses at the teeth, desired contact patterns that influence efficiency and noise, and overall constraints on gear size and geometry. As such, there is a need for a gear and gear assembly that reduces undesired excitations that may reduce gear assembly and turbine engine performance.