There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.

1. Field of the Invention
This invention relates generally to non-volatile memory devices having a floating gate . More particularly, the present invention relates to a new and novel reading circuitry and method for performing program verify, erase verify and over-erase-correction verify operations on a selected memory core cell in an array of EPROM, EEPROM, or Flash EEPROM memory core cells which uses only a single reference cell so as to reduce the amount of trimming time required during manufacturing.
2. Description of the Prior Art
As is generally well-known in the art, non-volatile memory devices using a floating gate for the storage of charges thereon such as EPROMs (electrically programmable read-only memories), EEFROMs (electrically, erasable programmable read only memories) or Flash EEPROMs have emerged in recent years. In such a conventional Flash EEPROM memory device, a plurality of such one-transistor memory may be formed on a P-type semiconductor substrate in which each cell is comprised of an n+ drain region and an n+ source region both formed integrally within the substrate. A relatively thin gate dielectric layer is interposed between a top surface of the substrate and a conductive polysilicon floating gate. A polysilicon control gate is insulatively supported above the floating gate by a second dielectric layer. A channel region in the substrate separates the drain and source regions.
As is well-known, the charge of the floating gate of the one-transistor cell is dependent upon the number of electrons contained in the floating gate. During the programming mode, electrons are added to the floating gate of the cell so as to increase its threshold voltage. The term xe2x80x9cthresholdxe2x80x9d refers to a gate-to-source voltage that must be applied between the gate and the source of the cell in order to cause it to conduct. During the erase mode, electrons are removed from the floating gate of the cell so as to decrease its threshold voltage. In programmed state, the threshold voltage of a cell is typically set at greater than +6.5 volts, while the threshold voltage of a cell in an erased state is typically limited below +3.0 volts.
In order to determine whether the cell has been programmed or not, the cell is read by applying a small positive voltage to the control gate between the +3.0 and +6.5 volt range, typically +5.0 volts, with the source region held at a ground potential (0 volts) and the drain held at a potential between +1 to +2 volts. If the transistor cell conducts or is turned-on, a current will flow through the transistor representing a xe2x80x9c1xe2x80x9d bit or erased state. On the other hand, if the transistor cell does not conduct or is turned-off no current will flow through the transistor representing a xe2x80x9cxe2x80x9d bit or programmed state.
FIG. 1 is a simplified functional block diagram of a conventional semiconductor integrated memory circuit device 100 which includes a Flash EEPROM memory array 102 formed of a plurality of memory core cells MC11-NCnm (each being formed as described above). The plurality of memory cells NC11-MCnm are arranged in an nxc3x97m matrix on a single integrated circuit chip. Each of the memory cells is comprised of one of the array core transistors QP11 through QPnm which function as a memory transistor for storing data xe2x80x9c1xe2x80x9d or xe2x80x9cxe2x80x9d therein. Each of the core transistors has its drain connected to one of the plurality of bit lines BL-BLM. All of the sources of the array core transistors are connected to a common array ground potential VSS. Each of the core transistors also has its control gate connected to one of the plurality of word lines WL-WLN.
The memory circuit device 100 further includes a row address decoder 104, a column address decoder 106, and a Y-pass gate circuit 108. The row address decoder 104 selects one of the corresponding word lines WL-WLn in the memory core cell array 102 in response to row address signals Ai. At the same time, the column decoder 106 selects one of the corresponding bit lines Bl-BLm in response to column address signals Aj. The Y-pass gate circuit 108 connects the corresponding array bit lines to a sensing or reading circuitry 110.
In order to determine the state of a selected memory core cell, the reading circuitry 110 includes a sense amplifier functioning as a comparator which receives a core current signal from a bit line on its one input and receives a reference current signal from a reference line on its other input. In this manner, the core current signal corresponding to a core current is compared with the reference current signal corresponding to a reference current from a reference cell. The result on the output of the comparator indicates whether the selected memory core cell is storing a xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
With reference to FIG. 2 of the drawings, there is shown a simplified schematic circuit diagram of certain portions of the memory circuit device 100 of FIG. 1 to explain how the program verify, erase verify, and over-erase-correction verify states of one selected array core transistor QP is determined. In particular, the reading or sensing circuitry 110 of FIG. 2 includes a comparator 120, a reference resistor 122 having a resistance value R2, a sense resistor 124 having a resistance value R1, a core transistor QP, and a plurality of reference transistors QR1-QR4. The comparator 120 is actually one of the sense amplifiers of FIG. 1.
The reference resistor 122 has its one end connected to a supply potential or voltage VCC, which is typically at +1.0 volts, and its other end connected to the non-inverting input of the comparator 120 at node A. The node A is also coupled to the drains of the reference transistors QR1-QR4 via the reference cell line REF and corresponding switches S1-S4. One end of the sense resistor 124 is also connected to the supply potential VCC, and the other end thereof is connected to the inverting input of the comparator 120 at node B. The node B is also connected to the drain of the core transistor QP via the selected bit line BL. As can be seen, the gates of the core transistor QP and the reference transistors QR1-QR4 are connected together and receive the same control gate voltage VG_SENSE via the selected word line WL.
During a normal Read mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR1 having a read threshold voltage RD_VT by closing the switch S1. During a program verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR2 having a program verify threshold voltage PGM_VT by closing the switch S2. During an erase-verify mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR3 having an erase-verify threshold voltage ERS_VT by closing the switch S3. During an over-erase-correction mode of operation, in order to read the selected core cell in the memory array, the core current ICELL from the selected core cell QP is compared with the reference current IREF from the reference cell QR4 having an over-erase-correction threshold voltage OEC_VT by closing the switch S4.
The various threshold voltages for the four reference cells QR1-QR4 are required to satisfy the following condition:
OEC_VT less than ERSxe2x80x94VT less than RDxe2x80x94VT less than PGMxe2x80x94VT
As will be noted from FIG. 3, the reference cell current from the four respective reference cells QR1-QR4 (each having a different reference threshold voltage) are plotted as a function of the control gate bias VG applied to the respective reference cells. Since the reference cells are identical to the array core cells, the plotted IDS curves A-D are parallel to each other and are also parallel to the IDS curve of an array core cell. Thus, the plotted curves A-D are only separated from one another by the differences in values of the their threshold voltages.
In order to determine whether the selected core cell QP is erase verified, the reference cell QR3 having the threshold ERS_VT will be used by closing the switch S3. When a bias voltage VG_SENSE is applied to the control gates of both the selected core cell QP and the reference cell QR3, the comparator 120 will effectively compare the core cell current ICELL with the reference cell current ERS_IREF. In order for the comparator to output a logic xe2x80x9c1xe2x80x9d indicative of the selected core cell QP being erase-verified, the core cell current ICELL is required to be larger than the reference cell current ERS_IREF.
With reference still to FIG. 3, it can be seen that if the core cell current ICELL is larger than the reference cell current ERS_IREF, then it will be also indeed larger than the reference cell current RD_IREF. Therefore, a selected core cell QP that has passed erase verify will likewise cause the comparator to output a logic xe2x80x9c1xe2x80x9d during the normal Read mode of operation where the reference cell QR1 having the threshold voltage RD_VT will be used by closing the switch S1 in order to produce the corresponding reference current RD_IREF. In other words, the core cell current ICELL will be greater than the reference cell current RD_IREF, which is less than the reference current ERS_IREF, since it is greater than the reference current ERS_IREF.
Based upon a similar analogy, in order to determine whether the selected core cell QP is program verified, the reference cell QR2 having the threshold PGM_VT will be used by closing the switch S2. When a bias voltage VG_SENSE is applied to the control gates of both the selected core cell QP and the reference cell QR3, the comparator 120 will effectively compare the core cell current ICELL with the reference cell current PGM_IREF. In order for the comparator to output a logic xe2x80x9c0xe2x80x9d indicative of the selected core cell QP being program-verified, the core cell current ICELL is required to be smaller than the reference cell current PGM_IREF.
With reference again to FIG. 3, it can be seen that if the core cell current ICELL is smaller than the reference current PGM_IREF, then it will be also indeed smaller than the reference cell current RD_IREF. Therefore, a selected core cell QP that has passed program verify will likewise cause the comparator to output a logic xe2x80x9c0xe2x80x9d during the normal Read mode of operation where the reference cell QR1 having the threshold voltage RD_VT will be used by closing the switch S1 in order to produce the corresponding reference current RD_IREF. In other words, the core cell ICELL will be smaller than the reference cell current RD_IREF, which is greater than the reference current PGM_IREF, since it is smaller than the reference current PGM_IREF.
In order to determine whether the selected core cell is over-erase-correction verified, the reference cell QR4 having a threshold voltage OEC_VT will be used by closing the switch S4. As will be noted from FIG. 3, in order to produce a current greater than zero when the bias voltage VG_SENSE=0V is being applied during the over-erase-correction verify mode of operation, it is required that the threshold voltage OEC_VT of the reference cell QR4 be set at less than 0V (negatively).
This prior reading circuitry 110 of FIG. 2 suffers from the disadvantages of several drawbacks. Firstly, in conjunction with the performing of the reading, erase verify, program verify, and over-erase-correction verify operations in the array of Flash EEPROM memory cells, there is required the task of trimming (programming) and verifying the threshold voltage of each of the four reference cells QR1-QR4. This trimming procedure involves the cycle of applying a program pulse to the reference cell, program verifying the reference cell, and applying another program pulse which is repeated over and over until the particular reference cell has been successfully trimmed to the different desired threshold voltages (e.g.,RD_VT, PGM_VT, ERS_VT, or OEC_VT). Thus, the trimming (setting) process is a very difficult and time-consuming task performed during fabrication of the memory devices which will increase the labor costs.
Secondly, the trimming of the reference cell QR4 to a negative threshold voltage is not desirable or convenient since it will create additional problems, such as requiring a negative supply voltage and/or other special testing equipment. Thirdly, since each reference cell (except for cell QR1) is storing either a positive or negative charge on its floating gate, they are unstable or susceptible to charge loss when there is a disturb. As a result, their threshold voltages will tend to change and thus the associated reference current IREF will be varied. It will be noted that the threshold voltage RD_VT of the reference cell QR1 is typically set near a neutral threshold voltage of UV_VT, which is defined as when there is neither a positive or negative charge added to the floating gate of the cell. Therefore, the closer the threshold voltage of the reference cell is to the neutral threshold voltage UV_VT, the more stable it will be.
Accordingly, there has been discovered by the inventor a new and novel reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of Flash EEPROM memory cells which overcomes the prior art problems. This is accomplished in the present invention by utilizing a single reference cell whose control gate bias voltage is varied to produce different reference current values.
Accordingly, it is a general object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which overcomes the disadvantages of the prior art.
It is an object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells so as to reduce the amount of trimming time required during manufacturing.
It is another object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which includes a single reference cell transistor having a fixed threshold voltage and whose control gate bias voltage is varied to produce different reference current values.
It is still another object of the present invention to provide an improved reading circuitry and method for performing program verify, erase verify, and over-erase-correction verify operations on a selected memory core cell in an array of flash EEPROM memory core cells which includes means for generating a core cell drain current, means for generating reference currents corresponding to predetermined modes of operation, and comparator means for comparing the drain current and the reference currents in order to determine whether the selected core cell has passed program verify, erase verify, and over-erase-correction verify.
In a preferred embodiment of the present invention, there is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations.
A comparator is used for comparing a sensed voltage corresponding to the core cell drain current and a reference voltage corresponding to one of the different reference currents. The comparator generates an output signal which is at a high logic when the sensed voltage is less than the reference voltage and which is at a low logic level when the sensed voltage is higher than the reference voltage.


A lens barrel including a surface wave motor to generate surface waves to drive a photographic optical system. The surface wave motor includes a fixed member to generate surface waves to drive the moving member which drives the photographic optical system. An externally operated manual operation unit drives the photographic optical system upon manual operation thereof. A roller is mounted in a freely rotatable state on the fixed member, and is in compressive contact with the manual operation unit via an intermediate ring. When a mode selection switch is set to a manual focus adjustment mode, the fixed member comes into compressive contact with a rotary element, and is rotatable integrally with a cam ring. By rotating a rotation ratio setting ring in a circumferential direction, a large diameter portion of the roller comes into contact with a changeover ring, and a small diameter portion of the roller to comes into contact with a changeover ring. Accordingly, the ratio of the rotation angles of the fixed member and the hand-operated ring can be changed in two steps. As a result, when the hand-operated ring is rotated during photography, the focus adjustment optical system for focus adjustment can be driven quickly or slowly for easy operability of manual focus adjustment.

1. Field of the Invention
The present invention relates to a lens barrel including a surface wave motor to drive a photographic lens, and, more particularly, the present invention relates to a lens barrel having a surface wave motor and a rotation angle conversion device to transmit a rotation angle of a hand-operated unit to a rotation angle of a fixed member of the surface wave motor.
2. Description of the Related Art
A lens barrel having a built-in surface wave motor is known, for example, as disclosed in Japanese Laid-Open Patent Publication JP-A-8-98191. The lens barrel having a built-in surface wave motor disclosed in JP-A-8-98191 includes a photographic optical system, a fixed member, a hand-operated member, a fixed tube and a mode selection member. The fixed member and the hand-operated member are integrally coupled such that rotation with respect to the fixed tube is possible. The mode selection member is an electrical switch to select a mode of focus adjustment.
In operation of the known lens barrel, when a manual focus adjustment mode is selected by the mode selection member, a moving member and the fixed member of the surface wave motor become integral, and the photographic optical system is driven by rotation coupled to the manual operation of the hand-operated member. Because of the relationship between the fixed member and the moving member, when in the manual focus adjustment mode, the contact surface of the moving member and the fixed member does not become damaged, and is capable of driving the photographic optical system. Moreover, when an automatic focus adjustment mode is selected by the mode selection member, the fixed member is fixed relative to the fixed tube, and the photographic optical system is moved by the rotation of the moving member.
FIG. 3 is a cross-sectional diagram of a prior art lens barrel having a built-in surface wave motor. FIG. 4 is a partial side view diagram, seen externally of the lens barrel in an axial direction, of a roller of a prior art lens barrel having a built-in surface wave motor. FIG. 5 is a cross-sectional diagram of an electrical power supply unit of a prior art lens barrel having a built-in surface wave motor. FIG. 6 is a schematic block diagram of a prior art lens barrel having a built-in surface wave motor.
Furthermore, the state of the lens barrel shown in FIG. 3 is in an automatic focus adjustment mode. The mode changeover switch 20 sets the automatic focus adjustment mode, in which the optical system L2, L3 for performing focus adjustment is driven by the rotational force of the surface wave motor Mo (FIG. 6).
As shown in FIG. 3, the optical system L2, L3 for performing focus adjustment is supported by a lens support tube 2, and performs focus adjustment by movement in the optical axis direction. The lens support tube 2 is located in the internal circumference of a central middle diameter portion 1a of a fixed barrel 1, and is fitted movably in the optical axis direction. A projecting pin 3 is mounted in the outer circumference of the lens support tube 2. The projecting pin 3 passes through a guide groove which is parallel to the optical axis and is disposed in the central middle diameter portion 1a of the fixed barrel 1. The front end of the projecting pin 3 engages a cam groove 4a disposed in the inner circumferential surface of a cam ring 4.
The inner circumferential portion of the cam ring 4 fits onto the outer circumferential portion of the central middle diameter portion 1a of the fixed barrel 1. A circular circumferential groove 4b is formed in the inner circumferential surface of the cam ring 4. A projecting pin 5, mounted on the outer circumferential surface of the central middle diameter portion 1a, fits, in a freely movable state, into the circular circumferential groove 4b. Because of the above arrangement, the cam ring 4 is immovable in the optical axis direction, and is rotatable in only a predetermined angular range centered on the optical axis. Moreover, a distance scale (not shown) is displayed on the right-hand side large diameter circumferential portion 4c of the cam ring 4.
A fixed element 6 of the surface wave motor Mo rotates with the optical axis as center, and generates surface waves. An inner circumferential portion of the fixed element 6 fits into an outer circumferential portion of a central small diameter portion 1c of the fixed barrel 1. A plurality of rotation shafts 26 having rotary axial lines in a direction at right angles to the optical axis are mounted in the outer circumferential surface of the fixed member 6. Freely rotatable rollers 25 are mounted on the rotary shafts 26.
A rotary element 9 of the surface wave motor Mo generates a drive force to drive the focus adjustment optical system L2, L3, rotating centered on the optical axis by the surface wave generated by the fixed element 6. The rotary element 9 is in frictional contact with the fixed element 6, and rotates freely relative to the fixed element 6 via a bearing 12. An engagement groove 9a is disposed in the left-hand side of the rotary element 9, and engages with a cooperating projection 4d disposed in the right-hand side, large diameter inner circumferential portion 4c of the cam ring 4. Because of the arrangement of the engagement groove 9a and cooperating projection 4d, when the fixed element 6 generates surface waves, the rotary element 9 and the cam ring 4 rotate integrally, centered on the optical axis, as a result of the surface wave. Moreover, a biasing member 14 places the rotary element 9 in frictional contact with the fixed element 6 via a disc 13.
A hand-operated ring 10 drives the focus adjustment optical system L2, L3 in the optical axis direction by an external operation by the photographer. The hand-operated ring 10 has its two ends respectively fitted into a large diameter portion 1d and a left-hand large diameter portion 1e of the fixed barrel 1. The hand-operated ring 10 is immovable in the optical axis direction, and is freely rotatable centered on the optical axis. An intermediate ring 7, formed of transparent synthetic resin, is rotatably disposed in an inner circumferential portion of the hand-operated ring 10.
A biasing member 11 presses on the fixed element 6 via the roller 25, and confers a predetermined frictional torque on the inner circumferential surface of the large diameter portion 1d of the fixed barrel 1, such that the fixed element 6 does not easily rotate when in the automatic focus adjustment mode. As shown in FIG. 3, the biasing member 11 is disposed between the central small diameter portion 1c of the fixed barrel 1 and the fixed element 6.
A biasing member 27 is disposed between the hand-operated ring 10 and the intermediate ring 7 in the inner circumferential surface of the large diameter portion 1d of the fixed barrel 1. The biasing member 27 presses the intermediate ring 7 via the roller 25, and causes frictional contact between biasing member 27, intermediate ring 7 and roller 25.
The roller 25 transmits the rotation angle of the hand-operated ring 10 to the rotation angle of the fixed element 6 (cam ring 4) of the surface wave motor Mo at an optional ratio. The roller 25 has an inner ring of metal and has an outer circumference covered with rubber. As shown in FIG. 4, the roller 25 is formed in two portions, with a large diameter portion 25a having a diameter Db at its outer circumferential surface, and a small diameter portion 25b having a diameter Db' (Db>Db'). The outer circumferential surface of the roller 25 has a difference in diameter, changing in its external diameter in the axial direction of the rotary shaft 26. The small diameter portion 25b, having diameter Db', contacts the side surface of the intermediate ring 7, and the large diameter portion 25a, having diameter Db, contacts the side surface of the large diameter portion 1d of the fixed barrel 1.
Accordingly, when the hand-operated ring 10 is rotated, the roller 25 rotates between the intermediate ring 7 and the large diameter portion 1d of the fixed barrel 1, and the fixed element 6 rotates centered on the optical axis on the outer circumference of the central small diameter portion 1c of the fixed barrel 1. At this time, the ratio Rr of the fixed element 6 (cam ring 4) relative to the rotation angle of the intermediate ring 7 is represented by the following Equation (1), in accordance with the principle of planetary gear devices. EQU Rr=(Db.multidot.Dc)/(Da.multidot.Db'+Db.multidot.Dc) Eq. (1)
In Equation (1), Da is the diameter of the region of contact of the roller 25 with the fixed barrel 1; and, Dc is the diameter of the region of contact of the roller 25 and the intermediate ring 7.
As shown in FIG. 3, a window member 8 allows the distance scale which is displayed on the right-hand, large diameter, circumferential portion 4c of the cam ring 4 to be read out through the intermediate ring 7 made of transparent synthetic resin. The window 8 is disposed in the large diameter portion 1d of the fixed barrel 1, and is made of transparent synthetic resin.
A glass epoxy plate 15 is fixed to the fixed element 6. As shown in FIG. 5, conductive portions 15a having an annular form are disposed along the whole circumference of the fixed element 6. Because of the arrangement of the conductive portions 15a, brushes 16 slide on the conductive portions 15a, and electrical connection is possible with respect to the fixed element 6, regardless of the angular position of the fixed element 6. Furthermore, the glass epoxy plate 15 has through holes 15b disposed in positions offset from the conductive annular portions 15a. The conductive portions 15a make electrical contact with the fixed element 6 from its back surface through the conductive portions of the back surface of the glass epoxy plate 15.
A pressure plate 17 fixes the brushes 16 in a brush fixing plate 18. The brush fixing plate 18 is fixed by small screws 19 to the fixed barrel 1.
As shown in FIG. 3, the mode changeover switch 20 is slidably disposed on the fixed barrel 1, and is a switch which slides in the direction M to set the manual focus adjustment mode and slides in the direction A to set the automatic focus adjustment mode. The mode changeover switch 20 corresponds to the mode selection unit 31 shown in FIG. 6, and generates electrical signals according to the respective mode. When the mode of operation is changed to the automatic focus adjustment mode, the power supply unit 100 supplies electric power to the surface wave motor Mo.
As shown in FIG. 3, a changeover plate 21 is fixed to the changeover switch 20 by a small screw 23. A plate spring 22 is fixed to the fixed barrel 1 by a small screw 24. The plate spring 22 is disengageable in plural engagement grooves 6a located in the outer circumferential portion of the fixed element 6.
When the mode changeover switch 20 slides in the M direction to change to the manual focus adjustment mode, the changeover plate 21 moves at the same time. The changeover plate 21 then presses the plate spring 22 downward, as shown by the dotted lines FIG. 3, the plate spring 22 separates from the engagement grooves 6a of the fixed element 6, and the hand-operated ring 10 is rotatable.
When the mode changeover switch 20 slides in the A direction to change to the automatic focus adjustment mode, the changeover plate 21 moves at the same time. The plate spring 22 then returns to the initial state, as shown by the full lines in the FIG. 3, and engages with the engagement grooves 6a of the fixed element 6. As a result, the hand-operated ring 10 is prevented from rotating.
Furthermore, by setting A as the frictional torque of the fixed element 6 and the rotary element 9, B as the frictional torque of the fixed barrel 1 and the fixed element 6, and C as the torque which is necessary to drive the lens support tube 2, the condition C<B<A is satisfied.
The operation of a prior art lens barrel having a built-in surface wave motor will now be described below. The automatic focus adjustment mode will be described first.
As shown by the full lines in FIG. 3, when the prior art lens barrel is in the automatic focus adjustment mode, the mode changeover switch 20 is in the A position, and the engagement grooves 6a of the fixed element 6 and the plate spring 22 are in engagement. Because of the engagement between the engagement grooves 6a and the plate spring 22, rotation of the hand-operated ring 10 is prevented, and the fixed element 6 is also in a state in which it cannot rotate.
Power is supplied to the surface wave motor Mo by a control mechanism (not shown in FIG. 3) corresponding to the power supply unit 100 shown in FIG. 6, to generate surface traveling waves in the fixed element 6, thereby causing the rotary element 9 to rotate in the circumferential direction. The left-hand side engagement groove 9a of the rotary element 9 engages with the engagement projection 4d disposed in the cam ring 4. When the rotary element 9 rotates, the rotary element 9 and the cam ring 4 rotate integrally. Then, when the cam ring 4 rotates, the lens support tube 2 moves along the optical axis, and performs the focus adjustment of the focus adjustment optical system L1, L2.
The manual focus adjustment mode will now be described below. When the lens barrel is in the manual focus adjustment mode, the mode changeover switch 20 slides in the M direction in FIG. 3. By moving the mode changeover switch 20 in the M direction, the electrical power supply to the surface wave motor Mo is cut off.
When the mode changeover switch 20 slides in the M direction, the changeover plate 21 fixed to the mode changeover switch 20 moves at the same time, and presses down the plate spring 22, which is fixed to the fixed barrel 1. By pressing the plate spring 22 downward, the plate spring 22 separates from the engagement grooves 6a in the outer circumferential portion of the fixed element 6.
When the engagement grooves 6a and the plate spring 22 are separated, the hand-operated ring 10 is rotatable. Furthermore, because the electric power supply to the surface wave motor Mo is cut off, the surface wave motor Mo does not drive, and the fixed element 6 and the rotary element 9 are in a state in which they are forcibly pressed by the biasing member 14.
Furthermore, because the frictional torque A of the fixed element 6 and the rotary element 9, and the torque required to drive the lens support tube 2, satisfy the condition C<A, the fixed element 6 and the rotary element 9 rotate integrally via the intermediate ring 7 when the hand-operated ring 10 rotates.
When the rotary element 9 rotates, the rotary element 9 and the cam ring 4 rotate integrally because the engagement groove 9a of the left-hand side of the rotary element 9 is engaged with the engagement projection 4d on the cam ring 4. When the cam ring 4 rotates, the lens support tube 2 moves in the optical axis direction, and the focus adjustment optical system L2, L3 performs focus adjustment.
When the prior art lens barrel having a built-in surface wave motor is in the automatic focus adjustment mode, the mode changeover switch 20 is in the A position, and the engagement grooves 6a in the outer circumferential portion of the fixed element 6 are engaged with the plate spring 22. Because of the engagement of the engagement grooves 6a and plate spring 22, the hand-operated ring 10 is prevented from rotating, and the fixed element 6 is also in a state in which it cannot rotate.
However, even when the engagement grooves 6a and the plate spring 22 are not engaged, the frictional torque B of the fixed barrel 1 and the fixed element 6, and the torque required to drive the lens support tube 2, satisfy the condition C<B. Because of this, the changeover between the automatic focus adjustment mode and the manual focus adjustment mode can be performed in a simple manner according to whether or not electric power is supplied to the surface wave motor Mo.
Accordingly, optional photographic ranges are stored, and after having photographed according to separate photographic ranges, during photography in the automatic focus adjustment mode, a "go-home" photographic function drives the lens to the stored photographic range. When manual focus adjustment is performed, the hand-operated ring 10 is rotated, instantaneously changing over to the manual focus adjustment mode, and mechanical changeover becomes unnecessary. Because of this, it is easy to include a mechanism for rapidly performing a changeover of these functions or modes.
In the prior art lens barrel having a built-in surface wave motor, when Da and Dc in Equation (1) are about equal, the rotation ratio Rr can be set to an optional value by changing the ratio of Db and Db'. Moreover, when Da and Dc are not equal, the rotation ratio Rr can be set to an optional value in the same manner by adjusting all the parameters from Da through Dc. Accordingly, in the prior art lens barrel having a built-in surface wave motor, the angle through which the hand-operated ring 10 is required to rotate, from the .infin. position of the photographic range to the close position, can be set to a sufficient magnitude to perform a delicate manual adjustment, independently of the angle through which the cam ring 4 is rotatable.
However, even though all the parameters from Da through Dc can be adjusted, once the values are set in a manufactured product, it is then impossible to successfully change these values later. Accordingly, the rotation ratio cannot be altered during photography according to the photographic conditions, thus limiting the freedom of focus adjustment.


Various systems and methods for low power multi-rate data paths are disclosed. As one example, a semiconductor device that includes a multi-rate data path is discussed. The multi-rate data path includes at least two register circuits with an output of one of the register circuits electrically coupled to an input of the other register circuit via a combinational logic block. In addition, the semiconductor device includes a control circuit that is operable to modify the rate at which the multi-rate data path operates by selectably bypassing at least one of the register circuits.

The present invention is related to systems and methods for power reduction in a semiconductor device.
Semiconductor designs often include a number of pipelined data paths that are exemplified in FIGS. 1a-1b. In particular, a pipelined data path 100 is shown in FIG. 1a, and a timing diagram 101 depicting operation of data path 100 is shown in FIG. 1b. As shown, pipelined data path 100 includes a number of D flip-flops 110 each separated by a combinational logic block 120. Each of D flip-flops 110 is fed by a D input 130 and a clock input 140, and each includes an output 115. In operation, output 115 is changed to reflect input 130 of the respective D flip-flop each time a rising edge of clock input 140 is received.
To operate properly, a preceding output must stabilize and propagate through the intervening combinational logic before the subsequent rising edge of the clock is received at the input of the subsequent flip-flop. As a particular example, output 115a of flip-flop 110a must switch to reflect input 130a (depicted as a value 131) on a rising edge 141 of clock input 140, and output 115a must propagate through combinational logic 120a and stabilize as input 130b (depicted as a value 133) before a subsequent rising edge 143 of clock input 140. Thus, for the design to operate properly, a period 150 of clock input 140 must be greater than a delay time 160 that includes the time to switch the preceding flip-flop, and to propagate through the intervening combinational logic.
Further, where it is desirable to minimize gate count and power dissipation, delay time 160 is designed to be very close to period 150. This approach can be used to minimize the number of pipeline stages, and thus the number of flip-flops used in a particular design. However, such an approach limits operational efficiencies that may be achieved in multi-rate systems. Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for power reductions in semiconductor devices.

Systems and methods for low power multi-rate data paths


Provided is an apparatus and method for exfoliation of graphene, comprising a chamber which has a through-hole formed at one surface thereof; a cylinder which receives graphite and a volatile material to be vaporized at room temperature and has an opening to be corresponding to the through-hole of the chamber, and which is disposed at an outside of the chamber; a clamp which is disposed in the chamber to pass through the through-hole of the chamber and thus selectively seal the opening of the cylinder; and an operation mechanism which is connected with the clamp and moves the clamp so that the opening of the cylinder is selectively sealed by the clamp. Therefore, it is not necessary to use an acid like sulfuric acid, and it is also not necessary to perform a thermal treatment process for removing sulfuric acid.

1. Field of the Invention
The present invention relates to an apparatus and method for exfoliation of graphene, and more particularly to an apparatus and method for exfoliation of graphene, in which graphene can be prepared by expanding graphite without a chemical treatment process using a strong acid like sulfuric acid and a thermal treatment process at a high temperature.
2. Description of Related Art
In general, graphite is a stack of two-dimensional graphene sheets having a layer structure in which carbon atoms are linked to one another in a hexagonal shape. Graphene is a representative flat single layer sheet in which three carbon atoms linked by an sp2 hybrid orbital bond are packed in a honeycomb crystal lattice.
In graphite, the carbon atoms in graphene are strongly linked to each other by a covalent bond, but graphenes are linked by a van-der-waals bond which is much weaker than the covalent bond.
Graphene is a single layer of graphite that is a (0001) plane of graphite. In graphite, since the bond between graphenes is weak, as described above, graphene has a very thin two-dimensional structure having a thickness of about 4 Å.
It has been found recently that graphene has very useful properties which are different from those of existing materials.
The most noteworthy property is that when electrons move in graphene, the electrons move as if the mass of the electrons is zero. This means that the electrons move at a speed at which light travels in vacuum, i.e., the speed of light. Further, another property is that graphene exhibits an abnormal half-integer quantum hall effect with respect to electrons and holes.
Moreover, the electron mobility of graphene known until the present is as high as about 20,000 to 50,000 cm2/Vs. Above all things, in case of carbon nanotubes which are similar to graphene, since production yield is very low if they undergo refinement after synthesis, the price of final product is too high even though the synthesis is performed by using a cheap material, but in case of graphite, it has an advantage in that the price thereof is very low. And in case of single-wall carbon nanotubes, the metallic and semiconductor properties vary according to chirality and diameter thereof, and also even if the semiconductor property is same, all of band-gaps thereof are different from one another. Therefore, each of the single-wall carbon nanotubes should undergo separation, which is difficult, in order to use a particular semiconductor property and a particular metallic property thereof.
On the other hand, in case of graphene, since the electrical properties thereof vary according to the crystalline directivity of graphene having a given thickness, a user can provide an electrical property in a direction which the user elects, and thus can easily design a device. Such electrical properties of graphene can be effectively used in carbon-based electric or electromagnetic devices and the like.
Due to such excellent properties of graphene, graphene receives attention as a substitute for next generation silicon and ITO (Indium Tin Oxide) transparent electrode and the like.
Many methods of manufacturing graphene have been continuously reported since 2004. Among them, there has been a method in which strong sulfuric acid or dangerous CIF3 is filled between layers of graphite and then treated at a high temperature so as to expand the graphite.
In this method, after a space between graphenes is expanded by pressure generated when volatile molecules such as sulfuric acid filled between graphenes, a thermal treatment process at a high temperature (of about 1,000° C.) has to be performed to remove various hydrophilic functional groups existing on the surface of graphite.
However, in this method, since a strong acid like sulfuric acid should be used and the thermal treatment process at a high temperature should be also performed, there is a problem that the above-mentioned excellent properties of graphene are deteriorated when graphite is exfoliated into graphene.
Moreover, when disposing of used sulfuric acid, environmental problems may be occurred, and the manufacturing cost thereof is increased due to the complicated thermal treatment process.

Apparatus and method for exfoliation of graphene

UNIST-ACADEMY INDUSTRY RESEARCH CORPORATION


A self-monitored controlled optical component system may include an electrostrictive actuator, a capacitor matched in capacitance to the electrostrictive actuator, a current source connected to the electrostrictive actuator and to the capacitor that supplies an electric current to the electrostrictive actuator and to the capacitor, an optical element connected to be moved by the electrostrictive actuator, and a comparator connected to receive a first output current from the electrostrictive actuator and a second output current from the capacitor, and output a differenced sensoriactuator signal proportional to the difference between the first output current and the second output current, the sensoriactuator signal representing a current associated with movement of the optical element by the electrostrictive actuator.

Controlled optical component systems include an optical component, such as a mirror, that is controlled by an actuator. The actuator may be an electrostrictive actuator, which may include a dielectric that changes its shape under application of an applied electric field. A common form of electrostrictive actuator is a piezoelectric actuator. In some applications, the electrostrictive actuator may take the form of a piezoelectric stack actuator ("PZT"), which is a stack of individual piezoelectric actuators. The purpose of the stack is to magnify the displacement effect of the individual piezoelectric actuator in response to the applied electric field. The mirror may be bonded to the end of the PZT so that it moves when the PZT is actuated.
Such optical component systems may comprise the only moving part of a laser, such as a Frequency Addition Source of Optical Radiation (FASOR) sodium guidestar laser. The optical component systems are used to actively control the laser cavity dimensions.
A problem inherent in such controlled optical component systems is that, in the event of a laser system malfunction, it is necessary to completely dismantle the controlled optical component system in order to determine the cause of the malfunction. Accordingly, there is a need for a self-monitoring controlled optical component system that provides an indication of the nature of a malfunction without need of dissembling the controlled optical component system, or removing the controlled optical component from the system, such as a laser, in which it is mounted.

Laser with a self-monitoring controlled optical component system


A blood measuring apparatus includes: a first chamber which includes a first wall provided with an aperture and in which diluted blood is contained; a second chamber which includes the first wall, a second wall opposed to the first wall and a peripheral wall and in which diluting solution is contained, the first and second chambers communicating with each other through the aperture; first and second electrodes which are disposed in the first and second chambers, respectively; a measuring unit which performs a blood measurement by causing a current to flow between the first and second electrodes; a diluting solution supplying unit which supplies diluting solution along a part of the peripheral wall which is adjacent to a peripheral edge of the first wall; and a sucking unit which sucks the diluting solution from the second wall.

The present invention relates to a blood measuring apparatus which performs a blood measurement by using the electrical resistance method.
A related-art blood measuring apparatus is configured as shown in FIG. 5. An aperture 73 configured by a minute hole is disposed between a first chamber 71 and a second chamber 72. An electrode 74 is disposed in the first chamber 71, and an electrode 75 is disposed in the second chamber 72. Diluted blood is contained in the first chamber 71, and a diluting solution is contained in the second chamber 72.
In the related-art blood measuring apparatus in the above-described state, a minute current is caused to flow between the electrodes 74 and 75 through the aperture 73, a resistance change due to blood cells existing between the electrodes 74 and 75 is captured as a change in potential, and a blood measurement (blood cell count) is performed based on the potential change.
The diluted blood which flows from the first chamber 71 into the second chamber 72 through the aperture 73 is carried at an approximately constant distance after flowing into the second chamber 72, by a flow current which is directed toward the aperture 73, and then recirculates to the sensing region due to the electrodes 74 and 75. Therefore, recirculating blood cells exist in the sensing region, and hence it is impossible to capture a resistance change due to only blood cells passing through the aperture 73, so that there is a possibility that the counting operation is erroneously performed.
Moreover, a dead water region where liquid does not flow is produced in the vicinity of the aperture 73. Therefore, air bubbles adhere to a wall portion constituting the sensing region where the aperture 73 is included, and the adhering state of bubbles is varied by a pressure change or a change in liquid flowing state, thereby producing a problem in that such a variation may cause noises during the measurement.
As a related-art technique for, in the blood cell counting measurement, preventing a situation where an error is caused by re-detection due to vortex flow which is formed immediately after the passage through a minute hole, from occurring, there is the back sheath technique (see the right column of page 1 of JP-A-61-159134). When the technique is employed, however, the structure of an apparatus is complicated.


A vehicle power shift transmission (PST) is controlled by a transmission control system which implements a control method. The PST is part of the driveline of the vehicle and is shifted by an actuating mechanism. The driveline includes an engine, the PST, a clutch, a synchronized shift transmission that can be shifted by a shift lever and driven vehicle wheels. In order to simplify the operator's tasks, during the shift of the synchronized shift transmission the gear of the PST is automatically shifted so that the resulting difference in the gear ratio of the complete transmission before and after the shift is minimized. The gear of the PST is selected and shifted automatically so that the rotational speeds on both sides of the clutch differ as little as possible.

The invention relates to a control system and method for controlling a power shift transmission of a utility vehicle, such as an agricultural tractor.
It is known to provide an agricultural tractor with a power shift transmission which can be shifted under load. The driveline for such a vehicle typically includes an engine, a power shift transmission controlled by actuating mechanism, a clutch, a synchronized transmission that can be shifted by a shift lever, and driven vehicle wheels.
Commercially available agricultural tractors, such as John Deere tractors in the 6000 series, have drivelines which are driven by an internal combustion engine and which include a shifted multi-speed transmission, a reversing unit, a clutch, an optional creeper transmission, a shifted range transmission, a rear axle differential and the driven rear wheels. The shifted multi-speed transmission is configured as a power shift transmission, (also called a partial power shift transmission) and includes planetary gear sets with clutches and brakes. Such a transmission may be shifted under load. Gear shift control signals are transmitted from a gearshift lever to a control unit which controls an actuating mechanism which causes the power shift transmission to shift. The range shift transmission is a fully synchronized shifted transmission whose ranges can be actuated by a range shift lever. A direction control lever is used for the shifting of the reversing unit between forward and reverse directions. This known driveline has a smooth succession of gear ratios and makes possible shifting under load within a selected range of gear ratios. The operator must manipulate two gearshift levers in order to utilize the smooth succession of gear ratios and adjust the gear ratio of the power shift transmission during a shift of the range transmission for many gear ratio combinations.

Transmission shift control system and method


An apparatus includes a platform positioned on the pallet, the platform having a load bearing surface including a first portion and a second portion. The second portion is movable relative to the first, such that the second portion overlies the first portion. A method of unloading articles from a pallet including arranging the loaded pallet with the second portion of the platform in the second position, unloading articles from the first portion of the platform, shifting the second portion of the platform to the second position, and unloading articles from the second portion of the platform. A method of loading articles on a pallet, including arranging the pallet with the second portion of the platform in the second position, loading articles onto the second portion of the platform, shifting the second portion of the platform to the first position, and loading articles onto the first portion of the platform.

Technical Field
The present disclosure relates to a method and apparatus for pick transfers of articles supported by a pallet.
Brief Discussion of Related Art
Pallets are used in transporting and storing articles. In particular, items to be shipped or stored are stacked and/or bound together into a large contiguous volume on a pallet. The pallet supports the items above the floor or other surface on which the items rest, while providing space beneath the items such that a mechanical device (e.g., pallet jack, forklift) as known in the art can lift the pallet, and the articles on it, to be moved.
Frequently, pallets of articles are stored in warehouses, stacked on pallet racks for efficiency of space. A manual picker will approach the pallet and remove some quantity of items from the pallet as they are needed, leaving the remainder. When articles are stored on the pallet in pallet racks, there are many difficulties for pickers inherent in picking articles not directly in front of them at the point of pick, for example, toward the back of the pallet and the rack. In part due to tight spacing of pallet racks, as a particular pallet is emptied of its contents, the picker must bend and reach to retrieve items, for example from the back of the pallet. These difficulties include pickers experiencing significant stress to the shoulders, upper back and lower back when picking the hard to reach articles by having to bend over, reach a great distance and/or pull out layers of articles. These bending and reaching motions can be a common cause of musculoskeletal injury to the picker. In addition to the human cost of such injuries to the worker, any worker lost-time injuries cost the employer in lost employee productivity, higher employee turnover, higher workers compensation insurance rates, just to name a few. In high-density storage applications, articles, pallets, etc. are stacked off the floor in racks that require a picker be lifted to the level of the items by a lift, for example by forklift, in order to access the articles. For safety, the picker must be tethered to the forklift to prevent a fall. This tether interferes with the picker's ability to reach into a pallet for items, reducing the pickers' level of productivity. Allowing the picker to access articles without reaching from or leaving the lift would improve productivity.
Many prior art methods for addressing these concerns did so by providing additional space about the top and/or sides of the pallet and articles and/or by providing access to same from additional and/or all sides. These prior art solutions, come with a significant cost, in that they generally reduce warehouse storage density and may require that existing racks be redesigned.


Torsional oscillations of the drillstring will lead to frequency modulation (FM) of the signal from a vibratory source (e.g., the bit). This results, in the frequency domain, in sidebands being present around a detected excitation frequency. In accordance with the present invention, it has been discovered that these sidebands may be used in advantageous methods for optimizing drillstring and drilling performance. In a first embodiment of this invention, these sidebands are used to discriminate between downhole and surface vibrational sources. Once the location of the drillstring vibration is determined, appropriate action may be taken to optimize drilling and drillstring performance. In a second embodiment of this invention, the sidebands are used to determine the rotary speed of BHA (bottom hole assembly) components. Using the method of this second embodiment, minimum and maximum rotary speeds of a given BHA component is determined as a function of the excitation frequency, the frequency of torsional oscillation and the modulation index. Once the minimum and maximum rotary speeds of the BHA components are determined, adjustments can be made to alter the rotary speeds and thereby enhance or optimize drilling and drillstring performance. This method is particularly well suited for use in those applications where torsional oscillations are not recognizable in the time domain, but are better recognized in the frequency domain.

This invention relates generally to methods and techniques for the analysis of vibration data in oil and gas well drilling. More particularly, this invention relates to the use of frequency modulation sidebands observed from detected frequency domain vibration data for (1) discriminating between surface and downhole vibratory sources and (2) the determination of the rotary speed of bottom-hole-assembly (BHA) components.
During drilling, various sources excite the drillstring. The amplitude of the resultant drillstring vibrations will depend on the level (severity) of the excitation, the system damping and the proximity of the excitation frequency to a natural frequency of the drillstring. When the frequency of any of the excitation sources is a natural frequency of the drillstring (axial, torsional or lateral) then the string resonates. Vibration levels are generally highest at resonance, but high level vibrations may exist in the drillstring, independent of drillstring resonance, whenever a high level of excitation is present.
Torsional vibration often manifests itself as a stick/slip action of the bottomhole assembly (BHA). Indicators of these downhole vibrations can be monitored at or near the surface. This stick/slip phenomenon is described in a paper entitled "A Study of Slip-Stick Motion of the Bit" by A. Kyllingstad and G. W. Halsey, Society of Petroleum Engineers (SPE) Paper 16659, Sep. 1987. As discussed in that paper, torsional oscillations are caused by alternating slipping and sticking of the bottom hole assembly (BHA) as it rotates in the borehole. This phenomenon is associated with a large amplitude, sinusoidial and often saw-tooth like variation in the applied torque. The term slip-stick motion refers to the belief that the amplitude of the torsional oscillations becomes so large that the drillcollar section periodically comes to a complete stop and does not come free until enough torque is built up in the drillstring to overcome the static friction.
Drilling with large amplitude vibrations will result in accelerated drillstring fatigue. A recent study of drillstring failures indicated that fatigue was the primary cause of the examined failures (see Hill, T. H.; Seshadri, P. V.; Durham, K. S., "A Unified Approach to Drillstring Failure Prevention," SPE/IAOC 22002, Mar. 1991, Amsterdam). Most current efforts aimed at understanding and controlling drillstring vibrations focus on the failure of drillstring components. However, during drilling, the drillstring transfers power from the surface to the bit and high amplitude drillstring vibrations may represent a loss, or waste, of drilling energy. Therefore, high levels of vibration not only result in drillstring component failures but can also result in sub-optimum drill rates.
The avoidance of high vibration levels can be attempted in two ways: (a) the BHA can be modeled and a harmonic analysis performed to predict the operating conditions, weight-on-bit (WOB) and rotary speed (RPM), which avoid resonant conditions or (b) the vibrations can be directly monitored while drilling to determine the optimum operating conditions (WOB, RPM and pump rate).
The use of modelling analysis is limited by the number of unknowns that occur in real-time drilling operation. In addition, most models focus on drillstring resonance frequencies, and estimate bit rotary speeds which will avoid exicting these frequencies ("critical speed" analysis). Therefore, they do not take into account high level excitations independent of this resonance analysis.
There is a continuing need for improved methods of using drillstring vibration data to enhance or optimize drilling performance and/or drillstring performance. For example, there is a need for a method to locate the source (e.g., surface or downhole source) of drillstring vibration so that corrective action may be taken to prevent drillstring fatigue and less than optimum drilling rates. In addition, there is a continuing need for methods of using drillstring vibration data to determine the rotary speed of BHA components to enhance or optimize the life of the BHA components and the drilling performance.

Methods for analysis of drillstring vibration using torsionally induced frequency modulation


Processes for the production of tantalum alloys are disclosed. The processes use aluminothermic reactions to reduce tantalum pentoxide to tantalum metal.

Tantalum is a hard, ductile, acid-resistant, and highly conductive metal with a density of 16.65 g/cm3. Tantalum has a high melting point temperature of 3020° C. Tantalum is often used as an alloy additive and is frequently combined with niobium to increase niobium's corrosion resistance properties. When mixed with metals such as niobium, tantalum has excellent resistance to a wide variety of corrosive environments, including mineral acids, most organic acids, liquid metals, and most salts. Tantalum is used for products in the aerospace, chemical processing, medical, superconducting, and electronics markets, among others.


A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.

1. Field of the Invention
The present invention relates to a semiconductor chip having a through-electrode extending thicknesswise therethrough and a production method for the semiconductor chip, and to a semiconductor device including a plurality of semiconductor chips stacked one on another and each having a through-electrode extending thicknesswise therethrough and a production method for the semiconductor device.
2. Description of Related Art
A multichip module (MCM) is conventionally known as a semiconductor device which includes a plurality of semiconductor chips. In the conventional multichip module, the plurality of semiconductor chips are arranged on an insulative wiring board horizontally parallel to the wiring board. In this case, the multichip module has a greater footprint, i.e., takes a greater area when the multichip module is mounted on a second wiring board.
In this connection, an attempt is made to reduce the footprint of a semiconductor device by stacking a plurality of semiconductor chips on a wiring board in the semiconductor device. In this semiconductor device, the semiconductor chips each include a through-electrode extending thicknesswise therethrough, and vertical electrical connection of the semiconductor chips is typically achieved via the through-electrodes of the respective semiconductor chips.
FIGS. 17(a) to 17(f) are schematic sectional views for explaining a first conventional method for producing semiconductor chips each having a through-electrode.
A hard mask 103 of silicon oxide (SiO2) is formed on one surface (hereinafter referred to as "front surface") of a semiconductor wafer (hereinafter referred to simply as "wafer") W provided with functional devices 101. The hard mask 103 has openings 103a which each expose a predetermined portion of the functional device 101 and a portion of the wafer W on a lateral side of the functional device 101.
Where the wafer W has a diameter of 8 inches, the wafer W has a thickness of about 725 μm. Where the wafer W has a diameter of 6 inches, the wafer W has a thickness of about 625 μm.
In turn, front side recesses 102 are each formed in the portion of the wafer W exposed in the opening 103a on the lateral side of the functional device 101 by reactive ion etching (RIE). The front side recesses 102 each have a depth of about 70 μm, for example. Then, insulation films 104 of silicon oxide each having a pattern which exposes the predetermined portion of the functional device 101 are formed on exposed interior surfaces of the openings 103a and the front side recesses 102 by a CVD (chemical vapor deposition) method.
After seed layers 105 such as of copper are formed on the insulation films 104 and on the inner peripheral surfaces of the openings 103a, a metal material 106 of copper is deposited in the openings 103a and the front side recesses 102 by a plating process employing the seed layers 105 as a seed. The metal material 106 is electrically connected to the predetermined portions of the functional devices 101.
Subsequently, the front surface of the resulting wafer W, i.e., the surface of the wafer W provided with the metal material 106, is polished (ground) by a CMP (chemical mechanical polishing) method, whereby the surface of the hard mask 103 becomes flush with the surfaces of the resulting metal material portions 106. In turn, a front side insulation film 107 having openings which each expose the surface of the metal material portion 106 above the front side recess 102 is formed on the front surface of the resulting wafer W, and bumps 108 are each formed on the exposed surface of the metal material portion 106 as shown in FIG. 17(a).
In turn, a base not shown is bonded onto the front surface of the resulting wafer W, and a surface (hereinafter referred to as "rear surface") of the wafer W opposite from the front surface is mechanically polished, whereby the thickness of the wafer W is reduced to about 55 μm. Thus, the metal material portions 106 are exposed to the rear surface of the wafer W. A part of the metal material portion 106 in the front side recess 102 serves as a through-electrode 109. The other part of the metal material portion 106 serves as an interconnection member 110 which electrically connects the through-electrode 109 to the functional device 101 as shown in FIG. 17(b).
A polishing-damage layer having polishing marks and damaged by the polishing is present in the rear surface of the wafer W. For removal of the polishing-damage layer, the rear surface of the wafer W is dry-etched by about 5 μm. At this time, the through-electrodes 109, the seed layers 105 and the insulation films 104 are barely etched thereby to project from the rear surface of the wafer W as shown in FIG. 17(c). After this step, the resulting wafer W has a thickness of about 50 μm.
Subsequently, a rear side insulation film 111 of silicon oxide is formed over the rear surface of the wafer W (see FIG. 17(d)), and portions of the rear side insulation film 111 covering the through-electrodes 109, the seed layers 105 and the insulation films 104 are polished away, whereby the through-electrodes 109, the seed layers 105 and the insulation films 104 are exposed (see FIG. 17(e)). Then, bumps 112 are each formed on the exposed surface of the through-electrode 109 and the seed layer 105 on the rear surface of the wafer W (see FIG. 17(f)). Thereafter, the wafer W is diced to provide the semiconductor chips each having the through-electrode 109.
FIGS. 18(a) to 18(f) are schematic sectional views for explaining a second conventional method for producing semiconductor chips each having a through-electrode. This production method is disclosed in International Publication Pamphlet WO98/19337. In FIGS. 18(a) to 18(f), components corresponding to those shown in FIGS. 17(a) to 17(f) are denoted by the same reference characters as in FIGS. 17(a) to 17(f), and no explanation will be given thereto.
First, the step of forming the bumps 108 on the front surface of the wafer W and the steps precedent thereto are performed in the same manner as in the first conventional production method (see FIG. 18(a)). The front side recesses 102 each have a depth of about 70 μm as in the first conventional production method. In turn, the rear surface of the wafer W is mechanically polished, whereby the thickness of the wafer W is reduced to about 80 μm. Therefore, the front side recesses 102 do not penetrate through the wafer W at this stage, so that about 10-μm thick wafer portions are present between the metal material portions 106 in the front side recesses 102 and the rear surface of the wafer W as shown in FIG. 18(b).
Then, the rear surface of the wafer W is dry-etched by about 30 μm. This step is performed in such a manner that the insulation films 104 are etched at a lower etching rate than the wafer W. Thus, the polishing-damage layer is removed, and the metal material portions 106 each covered with the seed layer 105 and the insulation film 104 project by about 20 μm from the rear surface of the wafer W as shown in FIG. 18(c).
In turn, an insulation film 115 of silicon oxide is formed over the rear surface of the wafer W (see FIG. 18(d)), and the insulation films 115, 104 and the seed layers 105 are partly removed from the rear surface of the wafer W, whereby the metal material portions 106 are exposed to the rear surface of the wafer W. Thus, a part of the metal material portion 106 in the front side recess 102 serves as a through-electrode 117, and the other part of the metal material portion 106 serves as an interconnection member 118 which electrically connects the through-electrode 117 to the functional device 101 as shown in FIG. 18(e).
Subsequently, bumps 116 are each formed on the exposed surface of the through-electrode 117 and the seed layer 105 on the rear surface of the wafer W. Thereafter, the wafer W is diced to provide the semiconductor chips each having the through-electrode 117.
The semiconductor chips produced by either of the aforesaid production methods are vertically stacked with the bump 108 of one of each adjacent pair of the semiconductor chips being connected to the bump 112 or 116 of the other semiconductor chip, whereby the semiconductor chips are electrically connected to one another. Thus, the interconnection length can be reduced. The semiconductor device has a reduced footprint on a wiring board or the like.
In the first conventional production method, the through-electrodes 109 (metal material portions 106) are partly polished together with the wafer W when the rear surface of the wafer W is polished (see FIG. 17(b)). This results in contamination of the wafer W with copper of the metal material 106, thereby deteriorating the characteristics of the semiconductor chips. The copper is diffused to a great depth of the wafer W, and remains in the wafer W even after the removal of the polishing-damage layer (FIG. 17(c)).
The through-holes (front side recesses 102) are required to have a size (width) of about 10 μm, for example, due to tighter process rules. In this case, however, the depth of the front side recesses 102 cannot be increased to about 70 μm or greater. Therefore, the thickness of the wafer W should be reduced to 70 μm or smaller (to about 50 μm in the aforesaid example) in order to assuredly expose the metal material portions 106 (through-electrodes 109) to the rear surface. Therefore, the resulting semiconductor chips (semiconductor substrates provided by dicing the wafer W) each have a thickness of 70 μm or smaller (about 50 μm in the aforesaid example).
However, where the thickness of the semiconductor chips is reduced to 100 μm or smaller, the rigidity of the semiconductor chips is drastically reduced. When the semiconductor chips each having a smaller thickness are stacked to be assembled into a semiconductor device, the semiconductor chips are liable to warp, so that the semiconductor chips cannot properly be connected to each other or to the wiring board.
In the second production method, the metal material portions 106 (through-electrodes 117) are not exposed when the rear surface of the wafer W is polished for the thickness reduction of the wafer W. Therefore, the wafer W is free from contamination with copper. However, the semiconductor chips produced by the second method each have a reduced rigidity like those produced by the first method, because the thickness of the wafer W is finally reduced to 70 μm or smaller (to about 50 μm in the aforesaid example). Therefore, inconvenience occurs in assembling the semiconductor chips into a semiconductor device.

Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device


The invention relates to an interconnection network and an integrated circuit and a method for manufacturing the same. Furthermore, the invention relates to a method for signal transfer between semiconductor structures. The invention is characterized in that a signal of a first semiconductor structure is supplied to a transmitter, which generates from the signal a plasmon wave, and couples the latter into a waveguide. The plasmons fed through the waveguide are received by a receiver, converted to an electric signal and forwarded to a second semiconductor structure.

The invention relates to an interconnection network between semiconductor structures, comprising a waveguide for the transfer of a signal between the semiconductor structures, a transmitter to receive the signal of a first semiconductor structure and to couple the signal into the waveguide, and a receiver to receive the signal from the waveguide and forward it to a second semiconductor structure. Such interconnection networks are used on integrated circuits in order to transfer any of a data signal, a command signals or a clock signal between different semiconductor structures. These semiconductor structures can, as an example, comprise storage cells or computing structures.
A conventional interconnection network between different semiconductor structures on integrated circuits is manufactured by use of resistive conductors. For this purpose an appropriate sub-region of the surface of the semiconductor is metalized with aluminum, gold or copper. Electric signals can be coupled to one end of said metalized areas and are received at the other end. However what is disadvantageous here is that such an interconnect has an electric capacity and a resistance, which must be recharged each time a signal is transmitted. Since the current available for recharging this capacity is limited by the electrical resistance of the circuitry, signal delays arise in the integrated circuit. On an integrated circuit featuring a structure size of 65 nm, this delay is a factor of 5 larger than the gate delays of the arithmetic unit or the storage device.
In order to reduce these delays it is known to introduce additional transistors as signal repeaters and amplifiers. For this purpose however additional circuit elements are required on the integrated circuit, which increase the susceptibility to defects, the current consumption and the manufacturing costs of the integrated circuit.
It is known to introduce optical interconnections between semiconductor structures to solve this problem. In this case the signal processing is possible at the velocity of light and thus independently of charge carrier drift velocities and capacitances. However the level of effort required is several times greater. The electrical signals generated on the semiconductor structures must be converted into optical signals first. For this purpose special opto-electronic circuit elements are required, which by reason of the indirect band gap of a silicon die cannot be manufactured in silicon technology of known art. At the endpoint of the optical waveguide this optical signal must then be converted with the same level of effort back into an electrical signal. Furthermore, efficient optical elements require geometrical dimensions of the same order as the wavelength of the light used. However, CMOS structures commercially used at the present time already have structure sizes of 90 nm or less. No semiconductor elements are available as transmitter diodes for radiation at a 90 nm wavelength.
The object of the invention is therefore to transfer the electrical signals of a first semiconductor structure to a second semiconductor structure without having to undertake a conversion of the electrical signal into an optical signal and without the delay induced by the capacity and the resistance of a conventional interconnecting network.

Interconnection network between semiconductor structures, integrated circuit and method for transmitting signals

Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.


Disclosed are systems and methods for debugging program code using a computing system. The disclosed method includes designating a control point in a software application subject to a debugging procedure, and then executing the program code for the software application as a guest application executing within a virtual machine. Upon detection of a virtualization event, the hardware processor transfers program control to a hypervisor which then determines whether the virtualization event corresponds to the designated control point based on an execution state of the guest application. If so, the virtualization event handler may generate a debugging event that is used by a debugger.

Debugging code, especially system-level code, is a difficult task. Currently, using popular debugging software such as GNU Debugger (GDB), LLDB Debugger, WinDBG, a user is limited with breakpoints, including hardware breakpoints, watchpoints, and tracing using breakpoints or trace flags (hardware-assisted). However, such software-emulated and hardware-assisted techniques have their limitations. Software breakpoints require modification of program code to insert special breakpoint instructions (e.g., "bp" or "bu" commands), which can be unacceptable in some cases. Hardware breakpoints require the use of specialized registers (e.g., "dr" registers) in the processor architecture and therefore have a limited number of hardware breakpoints (e.g., 4 breakpoints in x86 architecture, 2 breakpoints in ARM-based architectures). Watchpoints are a special breakpoint that stops execution of an application whenever the value of a given expression changes or whenever a specified condition is true (without specifying where it might occur). However, a limited number of watchpoints work if only the software developer is able to guess access item size (e.g., byte, 32-bit, or 64-bit). Hardware-assisted tracing cannot trace certain commands (e.g., IRET, POP SS, LSS, call and task gates, and any other privilege ring switching). There is also a hardware limitation to skip tracing events, after stack segment modification, and such technique is used as an anti-debugging trick.

System and method for virtualization-assisted debugging


A card connector includes a housing that houses a card provided with a terminal member, a connecting terminal and a cover member. The connecting member is attached to the housing that connects with the terminal member of the card. The cover member is connected to the housing and forms a card housing space between the housing, and is attached to a substrate.

The Present Disclosure relates, generally, to a card connector, and more particularly, to a card connector that can rapidly remove the heat generated by the card with a simple construction, a small size, easy manufacturing and low cost. Additionally, the card connector should be able to securely hold the card with a simple construction, a small size, easy manufacturing, low cost and excellent reliability.
Conventional electronic devices are generally provided with a card connector in order to use various memory cards. Further, conventional card connectors generally have a push/push structure from a perspective of easy handling, so as to press-in a memory card to insert and remove the card. An example is illustrated at Japanese Patent Application No. 2009-146701, the content of which is fully incorporated in its entirety herein.
FIG. 11 illustrates a conventional card connector, in which 811 is a housing for a card connector composed of an insulating material, and is provided with a plurality of connecting terminals 851 composed of metal. Further, 861 is a card connector shell composed of a metallic sheet, and which is mounted on the upper side of the housing 811. Furthermore, a memory card 901 is inserted between the shell 861 and the housing 811, and contacts the connecting terminal 851 that corresponds to a contact pad 951 of the memory card 901.
In the example illustrated, the card connector is of a push/push type which has a guide mechanism to eject the memory card 901. The guide mechanism is provided with a slide member 821 engaged with the memory card 901 such that it slides with the memory card 901, and also a coil spring 881 that biases the slide member 821 in the direction of ejecting the memory card 901.
Moreover, a cam groove of the heart cam mechanism is formed on the upper surface of the slide member 821, and one end of a pin member 871 of the heart cam mechanism is engaged with the cam groove. In addition, the pin member 871 is held by being biased downward from the top by a leaf spring 865 of the shell 861. Further, the slide member 821 is provided with a lever 822, where an engaging part 823 is engaged with an engaging recess part 912 of the memory card 901.
When the memory card 901 is pushed into the housing 811, the memory card 901 is pressed in the inward direction (upper right direction in the drawing) of the housing 811. Subsequently, the engaging recess part 912 of the memory card 901 is engaged with the engaging part 823 of the lever 822 of the slide member 821, and the slide member 821 resists the repulsive force of the coil spring 881 and moves in the inward direction of the housing 811 with the memory card 901. Then, when the slide member 821 stops due to one end of the pin member 871 being latched to the cam groove of the heart cam mechanism by an operation of the heart cam mechanism, the memory card 901 also stops in an inserted state within the housing 811.
When the memory card 901 is removed from the housing 811, the state where one end of the pin member 871 is latched to the cam groove of the heart cam mechanism is released by being pushed. Accordingly, the slide member 821 is freed and moves in the near side direction (left lower direction in the drawing) with the memory card 901 due to the force exhibited by the coil spring 881 so that the memory card 901 is ejected from the housing 811.
However, strategies for heat dissipation have not been sufficiently implemented in conventional card connectors. In recent years, in conjunction with smaller electronic devices with higher performance, efforts have been made to reduce the size of the memory card 901 together with increasing the capacity of the memory card 901 and increasing the speed of the transfer rate for the input and output of data by the memory card 901. Therefore, because the component mounting density has increased within electronic devices thereby reducing open spaces, regardless of the increase in heat generated by the memory card 901, ventilation conditions around the card connector have worsened, thereby reducing the ability for heat dissipation and thus the temperature of the memory card 901 increases. Accordingly, although the temperature increase can be prevented in the memory card 901 by arranging a cooling device, such would require increasing the size of the electronic device as well as the cost.


An apparatus may comprise a plasma deposition unit, a movement system, and a mesh system. The plasma deposition unit may be configured to generate a plasma. The movement system may be configured to move a substrate under the plasma deposition unit. The mesh system may be located between the plasma deposition unit and the substrate in which a mesh may comprise a number of materials for deposition onto the substrate and in which the plasma passing through the mesh may cause a portion of the number of materials from the mesh to be deposited onto the substrate.

1. Field
The present disclosure relates generally to fabricating devices and, in particular, to depositing materials onto substrates.
2. Background
In the deposition of layers of material to form thin films and/or coatings for the manufacturing of durable and multifunctional layers, a layer of material may be deposited on a substrate as part of the process. Thin film deposition may be relevant to the manufacturing of devices. These devices may include, for example, without limitation, semiconductor circuits and computer displays. These thin films may be a part of the electronic operational functions of the device or may be used as protection layers for erosion and/or abrasion.
A layer of material also may be deposited in forming optical coatings on optics. These optical coatings may offer, for example, without limitation, anti-reflective and/or anti-icing properties.
The deposition of materials onto substrates may be performed in a number of different ways. For example, the materials may be deposited using physical vapor deposition, chemical vapor deposition, electrochemical deposition, molecular beam epitaxy, and other types of deposition.
Some forms of deposition may use plasma. For example, chemical vapor deposition may be implemented using plasma. This type of deposition may be referred to as plasma-enhanced chemical vapor deposition, plasma vapor deposition, atmospheric plasma deposition, and/or open air plasma deposition.
When using plasma to deposit a layer of material, the deposition of material onto the substrate may occur in vacuum and/or atmospheric conditions. Substrates may be coated with various materials, such as, for example, without limitation, oxides, metals, polymers, and other suitable types of materials.
Typically, plasma deposition systems have been developed using vacuum conditions. However, using plasma deposition under vacuum conditions may require additional bulky, expensive equipment and complexity to obtain the appropriate vacuum conditions for depositing materials onto the substrate.
Interest in atmospheric deposition systems may rely on cost effectiveness and the versatility of this type of deposition technique. These systems may be designed in mobile modular structures for use in field-related applications outside of a laboratory or plant.
Atmospheric deposition systems may also be referred to as open-air deposition systems. With atmospheric conditions, bulky and costly vacuum pumps and other equipment for providing vacuum environments may be avoided.
These types of deposition systems, however, still may not provide as much throughput as desired for processing substrates. Also, these systems may not provide as much control as desired in depositing material onto a substrate.
Therefore, it would be advantageous to have a method and apparatus that takes into account at least some of the issues discussed above, as well as possibly other issues.


A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor gas, such as a platinum precursor gas, having organic compounds to improve step coverage is introduced into a chemical vapor deposition chamber. A reactant is also introduced into the chamber that reacts with residue organic compounds on the conductive element so as to remove the organic compounds from the nucleating sites to thereby permit more efficient subsequent chemical vapor deposition of conductive elements.

1. Field of the Invention
The present invention relates to semiconductor processing and, in particular, concerns a metalorganic chemical vapor deposition (MOCVD) technique for forming component layers, such as platinum layers, in a manner that results in more efficient deposition of the component layer onto the surface of a semiconductor device.
2. Description of the Related Art
Semiconductor processing techniques have become increasingly more complex as a result of the increasing density and smaller sizes of semiconductor devices. One particular problem that occurs with smaller sized semiconductor devices is that it is often difficult to form components, such as conductors, vias and electrodes, that conformally cover the contours of the semiconductor device. For example, a typical device formed by semiconductor processing is a capacitor. Typically, a capacitor is formed in an opening in an isolation layer of a semiconductor device and has two electrodes that are positioned within the opening with a dielectric separating the electrodes so as to cover both the side walls and the bottom floor of the opening. It will be appreciated that as the openings become smaller and smaller in size, it is increasingly more difficult to have the electrode formed so as to uniformly cover the side walls and bottom walls of the opening. Three dimensional capacitors are but one example of a device that is increasingly more difficult to fabricate due to decreasing device dimensions leading to difficulties with conformal covering of the device surface. Other devices in which this problem occurs include vias, electrodes and conductive lines.
To address the particular problems associated with forming electrodes and other conductive elements on 3-dimensional surfaces, various techniques using various materials have been developed. One particularly common technique for forming three dimensional conductive elements, vias and lines in semiconductor applications is to use Chemical Vapor Deposition (CVD) techniques to deposit a conductive material, such as platinum (Pt), within an opening formed to contain a 3-dimensional conductive element.
For example, platinum is viewed as an ideal electrode material for high-K capacitors in DRAM applications due to its relatively high work function. This high work function forms an increased energy barrier inhibiting leakage migration of charge carriers between electrodes through an intervening dielectric. Moreover, platinum is also generally not oxidizable such that the electrode's resistivity is not increased as a result of exposure to oxygen containing compounds contained within the semiconductor environment.
Further, platinum is also strongly favored for formation of electrodes and 3-dimensional semiconductor structures, such as capacitors, conductors, vias and the like, due to its particularly advantageous step coverage when applied using chemical vapor deposition (CVD) techniques. In particular, platinum can be used to coat 3-dimensional structures through chemical vapor deposition such that the vertical side walls and the horizontal bottom surfaces are adequately covered by the deposited platinum.
Typically, a platinum precursor and other reactants are introduced into the CVD chamber and the platinum carried by a precursor gas is then deposited onto the surface of the semiconductor substrate through thermal decomposition or reaction with another reactant gas, such as O2, N2O, or H2. The platinum is carried in the precursor gas, that often comprises an organic compound. The platinum atom is bonded to the organic compound to permit the platinum atoms to be transferred in the gas phase. This enables the Pt to be conformally deposited over the surface of the wafer as the organic compound facilitates improved step coverage.
In the prior art, there is generally only a single deposition step such that the precursor gas and other reactant gas(es) are flowed into the CVD chamber until enough platinum, carried by the precursor gas, has been deposited on the exposed surface to form an electrode or other conductive element of a desired thickness. However, current CVD platinum deposition techniques have particularly low deposition efficiency such that the deposition rate is very slow, on the order of 1 Angstrom per second. In order to obtain a 300 Angstrom film, the deposition time is therefore usually several minutes. The relatively slow deposition rate creates inefficiencies in the manufacturing of semiconductor devices.
Moreover, the platinum precursor gas used for deposition is particularly expensive, on the order of $100 per gram. It has been observed that typical CVD platinum deposition techniques result in enormous waste of this expensive platinum precursor gas as only a small proportion of the platinum carried by the precursor gas is actually being deposited on the semiconductor wafer positioned in the CVD chamber. Hence, not only are current CVD platinum deposition techniques slow, they are also particularly inefficient in delivering platinum to the wafer. This results in considerable waste of expensive material and increases the cost of manufacturing semiconductor devices that require 3-dimensional conductive structures, like electrodes or conductors.
Further, the deposition process also results in the possible deposition of hydrocarbon byproducts on the surface of the semiconductor device which can become incorporated into or adsorbed onto the surface of the deposited film contaminating the film and inhibiting further deposition. In particular, the deposition of platinum in one typical process proceeds by the formula:(C5H5)Pt(CH3)3+H2→Pt (film)+CH4+other hydrocarbonsThe other hydrocarbons may not be volatile enough at the deposition temperature and thus stay on the surface of the film following deposition. This can result in contamination of the film and inhibit further deposition of the platinum film.
From the foregoing, it will be appreciated that there is a need for an improved technique for depositing conductive materials onto a semiconductor surface such that good step coverage can be obtained without a significant increase in the cost of manufacturing the semiconductor device. To this end, there is a need for a more efficient way of depositing conductive material, such as platinum, in a manner that results in more efficient deposition of the material with less waste of the precursor material used to form the material.

This patent is subject to a terminal disclaimer.

Technique for high efficiency metalorganic chemical vapor deposition


A handlebar attachment that can be clamped onto the existing handlebar of a bicycle or the like. The handlebar attachment permits the rider of the bicycle to assume an improved aerodynamic position while riding and places the rider in a position for permitting increased lung air intake. The attachment includes hand area elements, sliding elements and joint element for joining the hand area elements and the sliding elements. The assembly is attachable to existing handlebars with adjustable clamps.

Bicycle designers, manufacturers and users are aware of the complexity of bicycle construction and the changes that have been made recently in the handlebar construction and position on bicycles. Bicycle riders are continuously trying to improve their aerodynamic position while riding a bicycle and to improve their stamina while riding. To that end the handlebars of bicycles have been formed to place the rider in a riding position that minimizes the frontal area of the rider. Other handlebar constructions have attempted to place the rider in a position that is both comfortable and efficient in rider performance. Some of these handlebar and handlebar attachments are shown and described in the following U.S. Pat. Nos.:
4,750,754, issued Jun. 14, 1988 to D. C. Lennon, PA0 4,829,847, issued May 16, 1989 to D. Modolo, PA0 4,873,886, issued Oct. 17, 1989 to R. Renner, PA0 4,878,397, issued Nov. 7, 1989 to D. C. Lennon, PA0 5,000,469, issued Mar. 19, 1991 to C. J. Smith.
Some of the above listed patents are particularly adapted for riders of racing bicycles and are intended for use on riding surfaces that are reasonably smooth and uniform. Some of the bicycling enthusiasts prefer to ride bicycles on less formalized riding surfaces even to the extremes of riding on mountain paths and other rough surfaces. A bicycle adapted for such rough riding should provide the rider with efficient operating posture and position as well as provide for a restfull and comfortable position. Bicycle riders wish to assume the most efficient aerodynamic position while positioning the body in a posture that will permit the maximum of energy transfer to the bicycle pedals. Also important to the rider's efficiency in operating the bicycle is the positioning of the rider in a posture that will permit the rider to intake a maximum of air while breathing to extend the rider's stamina while riding.
While others have suggested forming the handlebar and/or attachments to the handlebar in forms that are intended to accomplish the positioning of the rider, none have provided for easily adjustable elements that accomplish all of the desired rider positioning and at least one of the attachments available to bicycle riders is a continuous loop or U-shaped design that does not allow an elbows-out, natural hand/wrist alignment for optimum steering control and the continuous loop design is not a compact, unobstrucive design.

Clamp-on aerodynamic bicycle handlebar attachment