The device with vacuum bag for pressure therapy solves the problem of accurate measuring of the under-pressure created in the vacuum bag and the problem of appropriate adjustment of the liner clothing to individual patients. he device with vacuum bag for pressure therapy according to the invention consists of a vacuum bag, specially designed liner clothing, and a control and measuring unit, situated in a housing, including a pressure gauge, which has direct connection to the vacuum bag through a tube. The air is sucked out from the bag through tubes attached on the one side to six connections on the vacuum bag and on the other side to connections provided on the housing. The liner clothing consists of several pieces designed for different parts of the body. The liner clothing pieces are made of two layers of porous fabric sewn together with longitudinal seams. The pockets made in this way are filled with granulated material, which enables close fitting of the liner clothing to the body, when the under-pressure is created in the vacuum bag, as the air between the particles is sucked out, too. The liner clothing pieces are bound together by means of VELCRO® brand fasteners.

The technical problem solved by the device, which is the subject of the present invention is a design and construction of accurate measuring of the under-pressure in the vacuum bag and a design and construction of special liner clothing for the user of the device. The accuracy of the measurement of the current value of the under-pressure in the vacuum bag depends on the position and distance of the pressure gauge. To ensure appropriate accuracy the pressure gauge should measure the under-pressure directly, therefore a direct physical link should be establish between the interior of the bag and the measuring instrument. The liner clothing to be put on by the patient before he/she puts on the vacuum bag should fit close to the body in order to create equal treatment conditions within the entire vacuum bag. Due to various body contours it is hard to achieve consistency of under-pressure in known devices as rigid felt is used as a liner. Consequently, all body parts in the bag cannot be treated under identical conditions. The technical problem to be solved is, therefore, how to achieve even conditions within the entire vacuum bag although the liner clothing is equal for all users, i.e. for small, tall, thin and fat patients. It is clear that the liner clothing should be flexible enough to fit well to different body shapes.

Device with vacuum bag for pressure therapy


An active pixel sensor of the present invention includes photo diodes with at least five side such as six sides arranged in a honeycomb structure with sharing of a floating diffusion (FD) region for increased fill factor. In addition, with sharing of transistor devices by multiple photo diodes, the fill factor is advantageously maximized.

This application claims priority to Korean Patent Application No. 2004-102363, filed on Dec. 7, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to optical image sensors, and more particularly, to an active pixel sensor with photo diodes arranged in a honeycomb structure.
2. Description of the Related Art
Imaging systems implemented with complementary metal-oxide semiconductor (CMOS) technology have reduced cost and power compared to conventional charge-coupled device (CCD) imagers. To generate video or still images, various techniques replacing CCD sensors have been developed. Such various techniques are largely divided into passive pixel sensors and active pixel sensors according to whether signal amplification is performed in each pixel or in a support circuit. Passive pixel sensors have advantages of a simple pixel and a high optical fill factor. Active pixel sensors include an amplifier in each pixel to enhance signal transmission and signal sensitivity and thus have a low optical fill factor.
FIG. 1 illustrates a conventional active pixel sensor. A pixel 100 includes a photo diode 101, a transmission transistor 102, a floating diffusion (FD) region, a reset transistor 103, an amplifying transistor 104, and a row selection transistor 105. Since these many elements are included in the pixel 100, a fill factor is low.
Therefore, a pixel architecture with increased fill factor is desired for an active pixel sensor.

Active pixel sensor having honeycomb structure


The reservoir system includes a heater coil having electrical leads adapted to be coupled to a voltage source. The heater coil is adapted to generate heat in correspondence with a heater voltage provided by the voltage source. A reservoir material layer is adapted to regulate pressure of a gas disposed within the gaseous-discharge device in accordance with temperature of the reservoir material. Heat is transferred from the heater coil to the reservoir material through a series of thermally conductive layers in which each of the layers have different thermal conductivity and coefficients of expansion. As a result, the thermal path resistance between the heater coil and the reservoir material layer increases as temperature of the heater coil increases so that the reservoir material increases in temperature at a slower rate than the heater coil.

1. Field of the Invention
The present invention relates to switching systems utilizing gaseous discharge effects to conduct large amounts of electric current, and more particularly, to an improved hydrogen reservoir for use in thyratrons and other types of gaseous-discharge devices.
2. Description of Related Art
It is well known in the art to utilize gaseous discharge effects to conduct large amounts of electric current. For example, a thyratron is a type of electric switch that rapidly conducts electric current between a cathode and an anode by use of a controlled gaseous discharge. A grid is disposed between the cathode and anode. When a suitable positive voltage pulse is applied to the grid, a plasma forms in the region defined between the grid and the cathode. The anode voltage produces an electric field that penetrates the grid and attracts the electrons migrating from the cathode via the plasma. The electric field subsequently causes electrical breakdown between the cathode and the anode through the grid, and in so doing, electric current is conducted through the device. Thus, thyratrons have the ability to stand-off high voltage levels while in the non-conductive "off" state, and to conduct high current levels while in the conductive "on" state. Moreover, the switching between the off and on states can be made to occur very rapidly, i.e., in sub-microsecond time scales.
In thyratrons and other types of gaseous-discharge devices, hydrogen is the medium of ionization that allows the device to conduct large amounts of current in short periods of time. It is well known that hydrogen gas is depleted during electrical discharges. To replenish the depleted hydrogen, reservoirs are used to provide a supply of hydrogen for the thyratrons and maintain the hydrogen equilibrium pressure within the devices. Alternatively, gaseous-discharge devices may also utilize deuterium as an ionization medium, and it should therefore be appreciated that this description applies to systems utilizing either hydrogen or deuterium reservoirs.
The stabilization of the hydrogen equilibrium pressure within certain defined limits is critical to the overall performance of the gaseous-discharge device. For example, if the equilibrium pressure is too low, the anode heat dissipation may be too great causing the device to experience a "red" anode and burn a hole through the envelope of the device. Further, low equilibrium pressure could also result in "trigger failure," a condition in which the thyratron fails to go into the conductive state after the triggering positive voltage pulse is applied to the grid. Conversely, if the equilibrium pressure is too high, the voltage stand-off limit may be exceeded causing undesired voltage breakdown between the cathode and the anode. In such a situation, the device may experience uncontrolled current runaway or a "latch-up" condition.
The repetitive pulse rate at which a gaseous-discharge device may be switched is the reciprocal of the high voltage recovery time of the device. A recovery condition results from the diffusion of hydrogen ions formed during current conduction into the side walls of the device, followed by recombination of the ionized hydrogen with electrons. The recovery time is therefore the time required to "open" the switch, or the time duration of de-ionization process until a subsequent application of high voltage between the cathode and anode is possible without re-conduction through the grid. The lower the hydrogen equilibrium pressure, the faster de-ionization can occur and the faster the device recovery time.
A typical hydrogen reservoir for a gaseous-discharge device comprises a heater circuit coupled to a reservoir material, in which the reservoir material controls the hydrogen pressure in accordance with changes in temperature by the heater circuit. The reservoir material forms interstitial hydrides which adsorb/absorb hydrogen as well as release hydrogen as the temperature of the reservoir material is varied. Temperature and pressure are therefore variables that are controlled by the voltage applied to the heater circuit. During manufacture, the gaseous-discharge device is back-filled with hydrogen following high temperature processing of the device to exhaust undesirable impurities. At a set input voltage of the reservoir heater, the pressure of the device is increased by filling the device with hydrogen until a desired equilibrium pressure is reached. Thereafter, during operation of the device, the hydrogen pressure is controlled by varying the heater input voltage.
The recovery time of the gaseous-discharge device depends on the relationship between the de-ionization rate and the reservoir system parameters. By changing the input voltage applied to the reservoir heater circuit, and therefore the temperature of the reservoir, the hydrogen pressure is adjusted to achieve a desired recovery rate. An important parameter of such reservoir systems is the operating range between the minimum and maximum reservoir heater voltage. These limits are determined by various factors, including the external electrical system parameters, the device geometry, and the rate of pressure change of the reservoir with the input voltage. Assuming that the electrical system parameters and grid geometry are constants, then the acceptable operating range of the device is purely a function of pressure and temperature.
If the reservoir system has a high pressure (P) variation with respect to the reservoir heater temperature (T) variation (dP/dT), the operating range will be rather small. Furthermore, with a high dP/dT, the pressure changes drastically with correspondingly small changes in the reservoir input voltage (V). This is particularly undesirable since the device can experience unstable operation from temperature fluctuations that occur due to uncontrolled line voltage shifts. Conversely, if the reservoir system has a low dP/dT, the operating range will be relatively large. The ratio of change in pressure to change in voltage (dP/dV) corresponds generally to dP/dT, and for an ideal reservoir heater in which temperature changes linearly with input voltage, the terms are considered to be equivalent.
Ideally, the reservoir will not vary significantly in temperature during device operation when set at any given heater voltage, but in practice this is difficult to achieve. As known in the art, the reservoir material typically comprises barium, zirconium, tantalum, or titanium; however, titanium is the most frequently utilized. The titanium reservoir material may be provided in one of two forms: (1) sintered, powdered titanium hydride in a container; or (2) solid titanium. As illustrated graphically in FIG. 7, solid titanium reservoirs have relatively high dP/dV, though they are simpler and thus less costly. Sintered titanium hydride reservoirs have generally lower dP/dV than solid titanium reservoirs, and therefore provide greater operating range and stability, but are costly to manufacture.
Another significant disadvantage of prior art hydrogen reservoirs is that there is often an initial pressure swing opposite to the direction which normally results from a change in reservoir input voltage. Particularly, when the voltage on the reservoir heater is increased, there may be an initial drop in hydrogen pressure before the reservoir stabilizes to the new temperature and begins to increase the hydrogen pressure. Similarly, there may be an initial increase in hydrogen pressure when the reservoir voltage is decreased. The initial pressure swing can have catastrophic effects to the operation of a gaseous-discharge device. For example, if a gaseous-discharge device is operating at an upper limit of anode temperature and the reservoir voltage is increased to raise the equilibrium pressure, the initial drop in hydrogen pressure could result in a red anode condition. To date, the cause of the opposite pressure swing phenomenon is not completely understood, and it is therefore highly desirable to provide a reservoir structure that does not exhibit such characteristics.
One approach to regulating the dP/dV relationship is to use an additional device known as a barretter. The barretter is an electrical component coupled in series with the reservoir system, and controls the dP/dV by regulating the input voltage provided to the reservoir heater. Despite the advantages of improved stability, adding a barretter to a reservoir system increases the complexity and cost of the system, and in certain small device applications the additional element could be simply prohibitive. Moreover, the barretter requires a longer warm-up time than the associated reservoir system, rendering the device impractical for applications in which a fast start is required.
Thus, a reservoir system for a gaseous-discharge device having uniformly low dP/dV characteristics across an operating range of the device without increasing the cost and complexity of the reservoir system would be highly desirable.

Thermo-quiescent reservoir system for a gaseous-discharge device


A bi-crystal heterostructure includes a first, substantially uniaxial, crystal layer; a second, substantially uniaxial, crystal layer positioned adjacent to the first crystal layer, and wherein the first and second crystal layers have mutually opposite rotations of their respective principal cross-sectional axes of a degree sufficient to impart negative refractivity in the heterostructure; a conductive metal strip positioned between the crystal layers and having a principal longitudinal axis sufficiently aligned with an unrotated principal axis of each of the first and second crystal layers to permit unidirectional electromagnetic wave propagation in the conductive metal strip; and a lossy metal strip positioned between the crystal layers and having a principal axis positioned substantially parallel to the principal axis of the conductive metal strip. Alternatively, one or both of the crystal layers can be replaced with a ferroelectric crystal with an associated static bias voltage source for imparting the uniaxial property to achieve the said crystal layers mutually opposite axes rotations. The conductive metal strip when wired with connectors at each end and positioned in an electrical circuit, e.g. an rf transmitting system, operates as an electrical isolator, substantially blocking signals in one direction while transmitting in the opposite direction.

The conventional isolator does its job, if it is a field displacement isolator, by having the incoming field signal sent down the device, being guided by a metallic strip, and leaving the via the right port, with little or no attenuation. Referring now to FIG. 1, a conventional isolator 10 uses as a substrate 12a ferrite ceramic material. On a middle surface (not illustrated) of the ferrite substrate is a conductive metal strip (not illustrated), e.g. gold, typically of uniform width and relatively thin compared to the substrate 12 thickness. The conductive strip is what guides the signal, e.g. in the form of microwave energy, through isolator 10. Off to one side of the conductive strip is another strip (not illustrated) typically of a thin material, but unlike the conductive strip it is poorly conductive and very lossy. When the signal is inputted to a right port 14 and exiting on a left port on the side opposite the right port (not illustrated), the electromagnetic field distribution overlaps the lossy strip. The lossy strip is sampled by the signal, and attenuated, and as the energy flows through the device, it gets absorbed increasingly, so that as it approaches the left port 16, almost no signal amplitude remains. The electromagnetic field distribution is asymmetric, and that is why when the signal flows in the opposite direction, the fields do not see the lossy strip. Conventional isolators are described in F. J. Rosenbaum, Integrated Ferrimagnetic Devices, in Advances in Microwaves 8, 203 (Academic Press, New, 1974). J. D. Adam et al., IEEE Trans. Microwave Th. & Tech. 50, 721 (2002). M. E. Hines, IEEE Trans. Microwave Th. & Tech. 19, 442(1971). F. N. Bradley, Materials for Magnetic Functions (Hayden, N.Y. 1971). P. J. B. Clarricoats, Microwave Ferrites (Wiley, N.Y., 1961). R. F. Soohoo, Theory & Applications of Ferrites (Prentice-Hall, N.J., 1960). To summarize these references regarding the bias field, for principal axis static bias H0 field, asymmetry occurs in a direction normal to H0 and propagation direction kp. Edge guided microstrip isolator uses H0{circumflex over (x)}, earlier waveguide structure used H0ŷ.
Although conventional ferrite isolators work well, and are widely used in the various frequency bands throughout the microwave and millimeter wavelength regions, there are several severe drawbacks. One—they must employ static bias magnetic fields on the order of several thousand gauss (many tesla). To make these fields requires the use of either large magnets or large coils with circulating current, which are substantially larger than the other circuit elements and the device itself that actually propagates, controls and directs the signals. Two—both magnets and coil arrangements require what are termed magnetic circuits to direct the magnetic bias fields flow where desired in order to apply a static bias field to the ferrite material. This is because the effective action of the ferrite occurs when an external magnetic field lines up the precessing magnetic spin moments associated with the magnetic atoms in the ceramic material. Such isolator devices therefore rely on the spin precession effect found in ceramic ferrites. Three—the biasing magnets or coils add substantial additional weight and size to the device in the overall structure of conventional isolators. Magnetic circuits also add a substantial amount of weight and size. Four—finally, a substantial part of the cost of a conventional isolator is from the high quality low loss ferrite material, the entire magnetic circuit, and the magnets or coils.
There is, therefore, a need for an electronic isolator that is smaller and less expensive than existing conventional devices.

Bi-crystal heterostructure electronic isolator

The United States of America as represented by the Secretary of the Navy


A phosphor and a light emitting device are provided. The phosphor comprises a composition having a formula of AaSi5OtNn:EuZ. A is selected from the group consisting of Be, Mg, Ca, Sr and Ba. 1.7<a<2.5. 0≦t<1, 7<n<9. 0.001<z<0.3. The phosphor has Mo of 10 ppm-500 ppm.

1. Field of the Invention
The invention relates in general to a phosphor and a light emitting device comprising the same, and particularly a phosphor comprising a composition formula of AaSi5OtNn:EuZ and a light emitting device comprising the same.
2. Description of the Related Art
In recent years, a light emitting device utilizing a semiconductor for emitting light has been intensively used. In particular, a light emitting diode (LED) has been developed successfully. Compared to a conventional light emitting equipment, such as a cold cathode fluorescent lamp and an incandescent lamp, the light emitting device utilizing the light emitting diode has advantages of higher emitting efficiency, smaller volumes, lower power consumption, and lower cost. Therefore, such light emitting device is used as various light sources. A semiconductor light emitting device comprises a semiconductor light emitting element and a phosphor. The phosphor can absorb and convert light emitted from the semiconductor light emitting element. The light emitted directly from the semiconductor light emitting element and light converted and emitted from the phosphor can be mixed for use. The light emitting device can be used in various applications, such as a fluorescent light, a car lighting, a display device, and a backlight for a liquid crystal display. A white light emitting device is used extensively. The current white light emitting device is formed by using YAG phosphor (Y3Al5O12:Ce) having the element cerium as an active center with a semiconductor light emitting element for emitting a blue light. However, the chromaticity coordinates of the mixed lights from the Y3Al5O12:Ce phosphor and the blue-light semiconductor light emitting element is on a junction line between the chromaticity coordinates of the blue-light semiconductor light emitting element and the Y3Al5O12:Ce phosphor. Therefore, the emitted mixed light is a white light lacking a red light, and is insufficient for color rendering property and color saturation property. In addition, the Y3Al5O12:Ce phosphor has a major excitation spectrum area inconsistent with the light emitting region of the semiconductor light emitting element, thus the phosphor generates poor conversion efficiency of the excited light. It is not easy to obtain a white light source for high brightness. For solving the problem of poor color hue and low brightness, it is developed to mix the YAG:Ce phosphor with a phosphor for emitting a red light, and improve quality of the red light phosphor, for increasing luminous brightness.
However, a phosphor absorbing a blue light and converting it into a red light is rare. The materials of development researches are focused on nitride and oxynitride phosphors. The known phosphors comprise Sr2Si5N8:Eu using the element Eu as the active center, CaAlSiN3:Eu, and sialon phosphor having a formula of MzSi12−(m+n)Alm+nOnN16−n:Eu. However, luminous brightness of the Sr2Si5N8:Eu phosphor is poor, and thus an application of the phosphor is limited and not wide. The sialon phosphor has adequate durability, but luminous brightness of which is poor, thus the phosphor is not popular. The CaAlSiN3:Eu phosphor has better durability, and, compared to the sialon phosphor, has better brightness, however, there is still a demand for further increasing the luminous brightness for the phosphor for a light emitting device exhibiting higher light emitting efficiency.


A substrate support and method for reducing the migration of a conductive material is provided. In one embodiment, a support includes a chuck body having a support side and a backside. A guard electrode is disposed within the chuck body proximate the backside of the chuck body. In another aspect, a method for reducing the migration of a conductive material is provided. In one embodiment, the method includes the steps of disposing a guard electrode proximate a backside of the substrate support and applying a voltage to the guard electrode.

1. Field of Invention
The present invention relates generally to a method and apparatus for use in a semiconductor wafer processing system. More specifically, the inventive apparatus and method relates to a semiconductor substrate support having a guard electrode that reduces the amount of free electrons on the backside surface of the support.
2. Background of Prior Art
Brazing is a well known and commonly used method of fastening components in a semiconductor wafer processing system. Such brazing is useful in a semiconductor pedestal assembly for attaching metal components to a ceramic wafer support (i.e., an electrostatic chuck, a ceramic body, a heater and the like) in instances where a vacuum-tight seal is required to maintain the isolation of a process environment from a non-process environment. One such electrostatic chuck is disclosed in commonly assigned U.S. Pat. No. 5,511,799, issued Apr. 30, 1996, and is hereby incorporated by reference.
Patent ""799 discloses a sealing device useful in semiconductor processing and is disclosed as being particularly useful for creating two separate atmospheres or environments within a semiconductor processing chamber. The first environment (i.e., process environment) is typically maintained in a vacuum condition during wafer processing. The second environment (i.e., non-process or backside environment) is filled with a heat transfer medium. The heat transfer medium is typically an inert gas or vented atmospheric air. The presence of the heat transfer medium in the backside environment enhances and assists in heat exchange between a semiconductor wafer and a substrate support. Patent ""799 teaches a method which enables the ceramic components of the pedestal to be brazed to the metallic components of the pedestal while retaining an air-tight integrity over a wide range of temperatures.
One class of materials that is commonly used for brazing the above described electrostatic chuck components comprises silver and silver alloys. The silver alloy braze has proven generally to have good durability and reliability over time. However, in some instances while under harsh operating conditions within the semiconductor processing system, the silver, or silver component of the braze, has been found to separate and migrate from the brazed joint. If the brazed joint is in the proximity of other electrical connectors on the backside in the electrostatic chuck, the silver which has separated from the braze creates an undesired conductive path that shorts these electrical connectors or deteriorates the performance of the effected electrical circuits.
More specifically, the silver component of the braze alloy forms an oxide when exposed to environments containing oxygen. At chuck operating temperatures (i.e., above 300xc2x0 C.), the silver oxide becomes unstable, breaks down and releases silver ions. The silver ions are relatively mobile in the electric field that exists proximate the electrical connectors. As such, the silver ions tend to move along the electric field lines between the connectors, growing outwards from a positively biased component such as a terminal. Under these conditions, the silver ions readily adopt free electrons creating a silver precipitate. The precipitated silver accumulates about the positive terminals and migrates towards objects having an opposite polarity.
As the ceramic substrates that generally comprise an electrostatic chuck exhibit a drop in bulk resistivity (increase in conductivity) when heated, electrons are liberated within the ceramic material and eventually move towards the backside of the electrostatic chuck. These electrons passing through the ceramic chuck bond with the silver ions. After long periods of time and repeated exposures of the brazed joint to high temperatures in the environment containing oxygen, the amount of silver becomes significant. The significant amounts of precipitated silver forms dendrites. These dendrites generally form at terminals on a circuit having the highest potential, and fan out across the backside of the electrostatic chuck towards ground (and other lower potential objects) creating a substantially conductive path. Substantially conductive meaning that although the path is comprised of discreet particles, or droplets, of silver, the proximity of the droplets to each other coupled with the voltage potential allows for charge transfer (arcing) and current flow. When enough precipitated silver becomes aligned between these terminals, the conductive path reduces the gap between the terminals to the point that arcing occurs. In extreme circumstances, the shorting of the electrodes residing within the chuck occurs.
Therefore, there is a need for a method and apparatus for reducing the migration of conductive material.
One aspect of the present invention generally provides a substrate support. In one embodiment, a substrate support includes a chuck body having a support side and a backside. A guard electrode is disposed within the chuck body proximate the backside of the chuck body. Another embodiment of the invention provides a substrate support including a chuck body having a support side and a backside. A guard electrode is disposed within the chuck body for attracting electrons proximate the backside of the chuck body.
In another aspect of the invention, a method for reducing the migration of conductive material on a substrate support is provided. In one embodiment, a method for reducing the migration of conductive material on a substrate support comprises disposing a guard electrode proximate a backside of the substrate support and applying a voltage to the guard electrode.

Method and apparatus for reducing migration of conductive material on a component


Method and composition for vaccination of a pig against swine dysentary caused by T. hyodysenteriae infection characterized by parenteral, preferably intramuscular, administration to the pigs of a live strain or of an oxygen-treated, non-viable strain of T.hyodysenteriae.

1. Field of the Invention
This invention relates to the immunisation of pigs against swine dysentery, and in particular it relates to a vaccine for the control of this disease.
2. Discussion of Related Art
An anaerobic spirocheate, Treponema hyodysenteriae, has been isolated and identified as the primary aetiological agent of swine dysentery, a mucoid, haemorrhagic diarrhoea of swine that is worldwide in distribution. The organism has a predeliction for the large intestine (colon) of swine where it proliferates, in the presence of other anaerobic bacteria, and produces a mucoid, haemorrhagic to necrotic degeneration of large portions of the large intestine. There is extensive invasion of the epithelia and lamnia propria of the tissue and the spirochaetes are clearly obvious, under light or electron microscopy, aligned along the necrotic tissue.
There is virtually no information available on the immune response of pigs to T.hyodysenteriae infection although it has been demonstrated that pigs that have recovered from swine dysentery are refractory to further challenge.
Several attempts have been made to develop an effective swine dysentery vaccine. U.S. Pat. No. 4,100,272 describes a vaccine comprising chemically killed cells of a virulent (pathogenic) isolate of Treponema hyodysenteriae for parenteral administration, whilst U.S. Pat. No. 4,152,413 describes a similar vaccine comprising killed cells of a virulent isolate for oral adminstration. U.S. Pat. Nos. 4,152,415 and 4,469,672 describe modification of the oral vaccination procedure which include the step of parenterally administering the vaccine prior to the oral administration thereof.
International Publication No. W085/03875 discloses a modified vaccination regime which comprises parenteral administration of a priming dose of a killed vaccine, and at about the same time or thereafter the oral administration of a live, avirulent or non-pathogenic strain of T.hyodysenteriae.
It will be apparent that in these prior vaccination attempts, killed virulent strains of T.hyodysenteriae have been used and the cells have been treated with fixative chemicals such as formaldehyde. In all instances, the killed vaccine has been administered either alone by injection or orally, or by injection in conjunction will; oral administration of a killed virulent strain or a live avirulent strain. The rationale of the oral administration of the avirulent strain is to stimulate the local immunity of the large intestine, and presumably to stimulate an IgA response.

Royal Melbourne Institute of Technology Limited


A real-time clock (RTC) power supply device in which a power supply of a RTC is connected to a capacitor having a large capacity. The power supply of a computer system charges the capacitors by RC charging when the computer is booted. After the computer is turned off, the power stored in the capacitor is provided to the RTC, the time of power consumption by the cell is decreased, and the life of the cell is extended. The RTC power supply device comprises a first diode, a filter capacitor, a charging loop, and a battery branch.

On a computer mother board, a RTC(Real-Time Clock)is provided to maintain the data stored in a CMOS on the mother board. Generally, electrical power is provided to a RTC by a battery arranged on the mother board. The battery can be a lithium cell, a nickel/hydrogen cell or a nickel/cadmium cell, an exterior cell box, or a RTC module of with an internal cell. The only method of extending the life of the power supply is to use a battery having excellent efficiency. Although the power consumption of the CMOS is low, the battery's power will eventually be used up. According to statistics, if a computer has never been turned on, the life the battery is from about a half year to one year. But in fact, the normal service life of a lithium cell is 10 years. When the power of the battery is too low or is used up, the data in the CMOS cannot be maintained, and thus, the computer cannot be. The battery must then be changed. A regular user may not know the function or existence of the battery. When the computer cannot be smoothly booted, the user probably thinks the quality of the computer is bad. A computer repair technicians is called to repair the computer. Frequently the results of repairing the computer is to replace the battery with a new one because the electrical capacity of the old battery is depleted. After a new battery is mounted, the data in the CMOS must be set anew, which will bother the user and increase maintenance cost. The method of providing power to the RTC should be improved.


A semiconductor device having an IC (Integrated Circuit) chip packaged on a circuit board, and a cap for hermetically sealing the chip. The cap is bonded to the circuit board at the edges of an open end thereof and bonded to the chip at the underside or bottom thereof. To accurately position the chip on the circuit board, the circuit board is provided with a groove or a shoulder in a position where it faces the edges of the open end of the cap. After the chip has been positioned on the circuit board, the cap is bonded to the circuit board via the groove or the shoulder.

The present invention relates to a semiconductor device having an IC (Integrated Circuit) chip and a cap hermetically sealing the IC chip.
Semiconductor devices of the kind described include one disclosed in IEICE TRANSACTIONS, VOL. E74, NO. 8 August 1991, page 2333, FIG. 2. The semiconductor device taught in this document has a TAB (Tape Automated Bonding) IC chip provided with TAB leads. The IC chip is packaged on a circuit board face down via a buffer implemented by silicone rubber and is connected to the board via the TAB leads. A cap is seam-welded to the circuit board along the edges of the open end thereof and is bonded to the top of the chip at the bottom or underside thereof, thereby hermetically sealing the chip. The silicone rubber intervening between the chip and the circuit board absorbs irregularity in the height and inclination of the chip when the chip is packaged on the circuit board. Specifically, the silicone rubber maintains the thickness of bond between the cap and the chip constant. However, when it comes to flip chip packaging for producing signals from the entire surface of an IC chip via bumps or micropin packaging for doing so via input/output micropins, it is not practicable to protect the bonding portion by silicon rubber or similar elastic material from below the chip. The flip chip packaging scheme and micropin packaging scheme are essential in coping with the increasing number of signals associated with an IC chip.
To eliminate the above problem, the IC chip may be bonded to solder bumps provided on a thin film formed on the circuit board and hermetically sealed by the cap, as proposed in the 41st ECTC Papers, 1991, page 704, FIG. 1. To absorb the irregularity in the configuration of the cap and the irregularity in the packaging height of the chip, a cap having prescribed dimensions is selected after the packaging of the chip, or the thickness of the solder is changed. Therefore, this type of semiconductor device is not practicable unless different kinds of caps are prepared beforehand, resulting in the increase in cost and the decrease in yield.
Further, when the irregularity in the height of the semiconductor device and the irregularity in the packaging height of the chip are not adjusted, there also occurs irregularities in the thickness of the adhesive for bonding the chip and cap, i.e., the adhesive intervening between the top of the chip and the bottom of the cap. For example, as the adhesive becomes thick, the thermal resistance from the chip or heat source to the top of the cap, i.e., a heat radiation surface increases to degrade the cooling effect. Moreover, the increase in the thickness of the adhesive makes it difficult to remove voids from the adhesive. This also increases the thermal resistance and causes cracks to occur due to thermal stresses, degrading the reliability and quality. In addition, when the cap and circuit board are soldered to each other, the solder is apt to fly apart onto the signal leads and circuit board in the event of connection. It is likely that this part of the solder melts due to heat in the event of repair to short-circuit the portions where the chip and circuit board are connected.

Semiconductor device package having locating mechanism for properly positioning semiconductor device within package


Systems/techniques that can facilitate video/animated QR codes are provided. In various aspects, a processor can identify a QR code. In various instances, the processor can decompose the QR code into a static fragment and a plurality of dynamic fragments. The static fragment can be a portion of the QR code that contains sufficient information to facilitate an online transaction, whereas the plurality of dynamic fragments can be a plurality of portions of the QR code that collectively contain sufficient information to facilitate an offline transaction. In various instances, the processor can sequentially render a plurality of frames on an electronic display, where each frame depicts the static fragment and a corresponding one of the plurality of dynamic fragments. Accordingly, a point-of-sale device can facilitate an online transaction by scanning one frame rendered by the processor, and/or can facilitate an offline transaction by scanning all frames rendered by the processor.

There exist two types of electronic financial transactions that utilize quick response (QR) codes: online transactions and offline transactions. In an online transaction, a QR code can contain a smaller amount of information, meaning that the QR code is easier to scan. On the other hand, in an offline transaction, a QR code typically needs to include a larger amount of information, thus causing the QR code to be more difficult to scan. A transaction in which a client device presents a QR code to a merchant device is inherently unidirectional, meaning that the merchant device does not have an opportunity to inform the client device whether it will perform an online transaction or an offline transaction. Accordingly, the client device does not know which type of QR code to present to the merchant device: a smaller and easily-scanned QR code for online transactions, or a more substantive and harder-to-scan QR code for offline transactions. If the client device presents the smaller and easily-scanned QR code when the merchant device is expecting to perform an offline transaction, the merchant device cannot establish trust with the client device. Similarly, if the client device presents the more substantive and harder-to-scan QR code when the merchant device is expecting to perform an online transaction, the merchant device can experience technical difficulties and/or otherwise be unable to properly scan the presented QR code.
Systems and/or techniques that can ameliorate one or more of these technical issues are desirable.


An insulator film provided on a region for arranging a Zener diode has a plurality of groove portions successively arranged in a direction D1 of extension of each semiconductor region forming the diode. Each groove potion extends in a width direction D2 of each semiconductor region, and has a depth T3. Each semiconductor region is arranged on the upper surface of the insulator film. Therefore, it follows that each semiconductor region has a plurality of irregular shapes arranged in the direction D1 of extension and the Zener diode has a peripheral length not only in the transverse direction D1 but also in a vertical direction D3, so that a p-n junction area in the Zener diode is increased. Thus, parasitic resistance of an input protection Zener diode is reduced for improving a gate insulator film protective function of the diode.

1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a technique effective for forming an input protection circuit of a MOS structure device.
2. Description of the Background Art
A MOS structure semiconductor element having a gate oxide film represented by a power MOSFET (metal oxide semiconductor field-effect transistor) or an IGBT (insulated gate bipolar transistor) requires an input protection circuit for protecting the semiconductor element against a surge current or static electricity, as well known in the art. When a surge current or static electricity flows into a gate electrode of the MOS structure semiconductor element, remarkable deterioration is readily caused on the electrostatic characteristic of a gate insulator film of the MOS structure semiconductor element. In general, therefore, a bidirectional Zener diode is provided between a gate electrode and a source electrode of a power MOSFET as the aforementioned input protection circuit, as shown in an equivalent circuit of FIG. 39. Such a countermeasure is disclosed in the description of paragraph [0002] and FIG. 4 in Japanese Patent Application Laid-Open Gazette No. 7-321305 (1995), for example.
FIG. 40 is a top plan view showing the layout of a semiconductor device having a plurality of MOS structure semiconductor elements and an input protection circuit therefor, which is also employed in later description of an embodiment 1 of the present invention and modifications thereof.
FIG. 41 is a top plan view schematically showing an input protection Zener diode forming region hatched in FIG. 40 among regions formed on the upper surface of a base layer of the aforementioned semiconductor device in an enlarged manner. The input protection Zener diode forming region is hereinafter referred to as a first region, and a region formed with a MOS transistor structure having a gate electrode and a main electrode is referred to as a second region. The definition of these regions also applies to later description of the embodiment 1, an embodiment 2 and modifications thereof. As shown in FIG. 41, a Zener diode is formed by alternately forming p-type semiconductor layers and n-type semiconductor layers in the form of rings.
FIG. 42 is a longitudinal sectional view of the Zener diode taken along the line I-II in FIG. 41. FIG. 43 is a longitudinal sectional view of an n-type diffusion region (n-type semiconductor layer) of the Zener diode taken along the line III-IV in FIG. 41.
As shown in FIGS. 41 to 43, an n-type second semiconductor substrate 2 containing low-concentration n-type impurities is formed on an n-type first semiconductor substrate 1 containing high-concentration n-type impurities by epitaxy. The substrates 1 and 2 form an n-type base semiconductor layer. Further, an insulator film 3 of an oxide film or the like is formed on the base semiconductor layer (1, 2). An input protection circuit is formed on a base layer defined by the base semiconductor layer (1, 2) and the insulator film 3 by the following manufacturing method: A polysilicon layer 4 is formed on the base layer, for successively forming an n-type semiconductor layer 4b1 having a square cross-sectional or planar shape, a p-type semiconductor layer 4a1 having a ring cross-sectional shape, a ring-shaped n-type semiconductor layer 4b2, a ring-shaped p-type semiconductor layer 4a2 and a ring-shaped n-type semiconductor layer 4b3 in the polysilicon layer 4 to enclose a gate pad formed after formation of the Zener diode. Thus, a bidirectional Zener diode having a plurality of p-n junction surfaces is formed as the input protection circuit.
Thereafter the Zener diode is overcoated with an interlayer isolation film 5, and contact holes 6a and 6b are provided on portions located immediately above the innermost n-type semiconductor layer 4b1 and the outermost n-type semiconductor layer 4b3 of the ring-shaped Zener diode respectively for bringing the n-type semiconductor layers 4b1 and 4b3 into ohmic contact with a gate electrode layer 7a and a source electrode layer 7b through the contact holes 6a and 6b respectively. Thereafter another interlayer isolation film (not shown) is formed on the gate electrode layer 7a and the source electrode layer 7b and an opening is formed in part of this interlayer isolation film located on the gate electrode layer 7a, thereby partially exposing the gate electrode layer 7a. The exposed part of the gate electrode 7a defines the aforementioned gate pad.
A reverse withstand voltage of the aforementioned Zener diode is set to a desired value by adjusting the number of the p-type and n-type semiconductor layers forming the Zener diode or adjusting the impurity concentrations of the p-type and n-type semiconductor layers.
For example, Japanese Patent Application Laid-Open Gazettes Nos. 7-321305 (1995), 8-288525 (1996) and 9-97901 (1997) disclose a Zener diode having a structure corresponding to such a longitudinal sectional structure.
The input protection circuit having the aforementioned structure protects the gate insulator film of the MOS structure semiconductor element against a surge current or static electricity. However, the effect of the conventional input protection circuit for protecting the gate insulator film cannot still be said sufficient since the value of parasitic resistance of the diode in the conventional input protection circuit is unignorably large due to the specification of the apparatus. Consider that surge takes place, for example. Also when feeding a surge current from the gate electrode toward the source electrode through the aforementioned diode at this time, a voltage determined by the product of the parasitic resistance value of the diode and the surge current is applied across the diode, to cause remarkable deterioration in characteristics of the gate oxide film as the case may be. In other words, it follows that characteristic deterioration of the gate oxide film readily takes place as the parasitic resistance value of the diode is increased regardless of the surge current flowing to the diode, to remarkably damage the function of the diode serving as the input protection circuit.
Such a problem is caused also when static electricity is generated in the MOS structure semiconductor element.
It is well known that the parasitic resistance value of the diode is inversely proportionate to the peripheral length (corresponding to the length of the diode or each semiconductor region shown in FIG. 41 in a peripheral direction PD) of the diode and the thickness of the polysilicon layer in each p-n junction surface and proportionate to the width (corresponding to the length in a direction perpendicular to the peripheral direction PD) of each semiconductor region in the diode.
Therefore, the peripheral length of the diode or the thickness of the polysilicon layer may be increased or the width of each semiconductor region may be reduced thereby reducing the parasitic resistance value of the diode and improving the function of the diode serving as the input protection circuit.
When simply increasing the peripheral length of the diode, however, a new problem arises to enlarge the chip size. When the area occupied by the diode itself, inclusive of the area occupied by the gate pad, is increased, the peripheral length of the diode is also increased in response thereto, while activation regions of the MOS transistors are narrowed to result in such a problem that the number of the MOS transistors cannot be increased to a necessary level. Occurrence of such a problem is serious particularly in a semiconductor device originally having a small chip size.
While increase of the thickness of the polysilicon films employed for the diode brings reduction of manufacturability, while such a structural restriction results from increase of the thickness of the polysilicon layers that each semiconductor region must be elongated along the width in order to cope with increase of transverse diffusion of p-type and n-type impurities in the diode.
When narrowing the widths of the p-type and n-type semiconductor regions in the diode, further, it follows that voltage resistance is deteriorated due to reach-through, and hence this countermeasure cannot be preferable either.
According to a first aspect of the present invention, a semiconductor device comprises a base layer and a diode arranged on an upper surface of the base layer, while the diode comprises a plurality of semiconductor regions extending in a first direction respectively and successively forming p-n junctions in a second direction perpendicular to the first direction, the conductivity type of a first semiconductor region located on the side of a first end in the second direction among the plurality of semiconductor regions of the diode is equal to the conductivity type of a second semiconductor region located on the side of a second end opposed to the first end, and the interface between the base layer and the diode in the upper surface of the base layer comprises a plurality of groove portions having a depth in a third direction perpendicular to the first direction and the second direction, extending in the second direction and successively arranged in the first direction.
According to a second aspect of the present invention, at least one of the plurality of semiconductor regions of the diode comprises an irregular portion having an irregular shape defined by the plurality of groove portions of the interface.
According to a third aspect of the present invention, at least one of the plurality of semiconductor regions of the diode comprises an upper surface having a flat portion opposed to a bottom surface of each of the plurality of groove portions of the interface in the third direction.
According to a fourth aspect of the present invention, the base layer comprises a base semiconductor layer of a prescribed conductivity type and an insulator film arranged on an upper surface of the base semiconductor layer, and the insulator film comprises an upper surface opposed to an interface between the base semiconductor layer and the insulator film in the third direction and corresponding to the interface between the base layer and the diode.
According to a fifth aspect of the present invention, each of the plurality of groove portions is defined as a first groove portion, and the interface between the base semiconductor layer and the insulator film comprises a plurality of second groove portions each opposed to the first groove portion.
According to a sixth aspect of the present invention, a first thickness of the insulator film arranged on a portion of the interface between the base semiconductor layer and the insulator film held between two adjacent second groove portions among the plurality of second groove portions in the third direction is larger than a second thickness of the insulator film arranged on a bottom surface of each of the plurality of second groove portions in the third direction.
According to the sixth aspect, the parasitic resistance of the diode can be further reduced, and the protective function for the gate insulator film can be further improved.
According to a seventh aspect of the present invention, the prescribed conductivity type of the base semiconductor layer is a first conductivity type, and the base layer further comprises a plurality of semiconductor well regions of a second conductivity type extending from a portion located under a bottom surface of each of the plurality of groove portions in the interface between the base semiconductor layer and the insulator film into the base semiconductor layer.
According to the seventh aspect, the voltage resistance of the semiconductor device can be improved.
According to an eighth aspect of the present invention, the semiconductor device further comprises a MOS transistor structure, comprising a gate electrode and a main electrode, arranged on a second region in the upper surface of the base layer when defining a portion of the upper surface of the base layer provided with the diode as a first region, while the first semiconductor region is electrically connected with the gate electrode and the second semiconductor region is electrically connected with the main electrode.
According to a ninth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of forming an insulator film on a semiconductor substrate, forming an irregular portion on the insulator film, forming a semiconductor film on the insulator film comprising the irregular potion and alternately forming a p-type semiconductor region and an n-type semiconductor region in the semiconductor film in prescribed order thereby forming a diode of a multilayer structure.
According to the first, second, third, fourth, eighth and ninth aspects, the diode can have a peripheral length not only in the transverse direction but also in the vertical direction although the area occupied by the diode as viewed from above is identical to that of the prior art, whereby the peripheral length of the diode is increased, the area of a p-n junction surface is responsively increased, the sectional area of a path for a surge current is increased, and parasitic resistance is remarkably reduced. Therefore, a clamping effect of the diode is increased to improve surge resistance, and the function of protecting the gate insulator film is improved.
According to a tenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of forming an irregular portion on a semiconductor substrate, forming an insulator film on a surface of the semiconductor substrate comprising the irregular portion, forming a semiconductor film on the insulator film and alternately forming a p-type semiconductor region and an n-type semiconductor region in the semiconductor film in prescribed order thereby forming a diode of a multilayer structure.
According to the fifth and tenth aspects, the parasitic resistance of the diode can be further reduced, and the protective function for the gate insulator film can be further improved.
An object of the present invention is to provide a semiconductor device capable of reducing the area of a Zener diode for an input protection circuit and improving an input protection function.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor device having diode for input protection circuit of MOS structure device

Ryoden Semiconductor System Engineering Corporation


A described bottom hole assembly includes a drill bit arranged at a distal end of a drill string and rotatable about a first central axis, the drill bit exhibiting a first unbalance force acting laterally on the drill bit at a first angular orientation, a first unbalance force marking physically applied to the drill bit and corresponding to the first unbalance force, a tool arranged axially from the drill bit, the tool exhibiting a second unbalance force acting laterally on the tool at a second angular orientation, and a second unbalance force marking physically applied to the tool and corresponding to the second unbalance force, wherein an angular offset between the first and second unbalance forces markings is able to be manipulated in order to obtain a minimized or desired tandem resulting unbalance force.

The present disclosure relates to earth penetrating drilling equipment and, more particularly, to physically marking drilling equipment and drilling equipment assemblies such that tandem drilling components may be intelligently coupled.
Wellbores are formed in subterranean formations for various purposes including, for example, the extraction of oil and gas and the extraction of geothermal heat. Such wellbores are typically formed using one or more drill bits, such as fixed-cutter bits (i.e., drag bits), roller-cone bits (i.e., rock bits), diamond-impregnated bits, and hybrid bits, which may include, for example, both fixed cutters and rolling cutters. The drill bit is coupled either directly or indirectly to an end of a drill string, which encompasses a series of elongated tubular segments connected end-to-end that extends into the wellbore from a surface location. Various tools and components, including the drill bit, are often arranged or otherwise coupled at the distal end of the drill string at the bottom of the wellbore. This assembly of tools and components is commonly referred to as a bottom hole assembly (BHA).
In order to form the wellbore, the drill bit is rotated and its associated cutters or abrasive structures cut, crush, shear, and/or abrade away the formation materials, thereby facilitating the advancement of the drill bit into subterranean formations. In some cases, the drill bit is rotated within the wellbore by rotating the drill string from the surface while drilling fluid is pumped from the surface to the drill bit. The drilling fluid exits the drill string at the drill bit and serves to cool the drill bit and flush drilling particulates back to the surface. In other cases, however, the drill bit may be rotated using a downhole motor (e.g., a mud motor) powered by the drilling fluid pumped from the surface.
To enlarge the diameter of the wellbore, a reamer device (also referred to as a hole opening device or a hole opener) may be used in conjunction with the drill bit as part of the BHA. The reamer is typically axially-offset uphole from the drill bit along the length of the BHA and exhibits a diameter greater than that of the drill bit. While typically arranged concentric with the drill bit, some reamers can be radially offset from the drill bit. Reamers can also be of fixed or variable geometry. In operation, the drill bit operates as a pilot bit to form a pilot bore in the subterranean formation, and the reamer follows the drill bit through the pilot bore to enlarge the diameter of the wellbore as the BHA advances into the formation.
Each of these drilling components (i.e., the drill bit and the reamer) can be designed to have as little cutting and mass imbalance forces as possible, since such imbalances can result in inefficient drilling and unwanted vibration propagating through the drill string during drilling. These imbalance forces include a component force that urges each drilling component laterally during drilling, thereby resulting in lateral vibrations. While the design of each drilling component endeavors to minimize these unbalance forces, such imbalances are present in practically all drill bits and reamers. When such drilling components are used in tandem along the BHA, their respective unbalanced forces can cooperatively amplify the vibrations in the drill string, thereby further reducing drilling efficiencies and potentially increasing equipment damage.

Unbalance force identifiers and balancing methods for drilling equipment assemblies


The present invention relates generally to methods and materials pertaining to assays, for example immunoassays, for biomarkers in body fluids e.g. blood. The invention also relates to diagnostic or screening methods for infections, and methods of differentiating between infectious and non-infectious conditions in mammals, particularly equines, for monitoring response to anti-infective/antibiotic therapy. The invention further relates to a test fluid collection system adapted to permit dilution and analysis of the collected test fluid. The invention further relates to monitoring exertional rhabdomyolysis in equines, and assay devices for all these things.

Within the animal kingdom, horses are considered to be elite athletes due to their unique physiology. Since sport horses are required to perform at an extremely high level, even small changes in health can be detrimental to their performance and may have the potential to negate months of a costly training program. Further training of horses in which a decline in performance is noted may lead to rapid degeneration in certain circumstances and therefore an indication of the cause of ill health should be rapidly investigated. The detection of such changes is often challenging and requires the utilization of equipment and skill which are typically only provided in a laboratory setting.
Common causes of poor performance that may be managed at the horse's side by the veterinarian and the trainer include effects of the musculoskeletal system, the respiratory system, inflammation (such as general inflammation or infectious inflammation) and other illness. Conditions affecting the musculoskeletal and respiratory systems are of particular interest as breakdown in the physiology of these systems has been identified as the main cause of disruption and interruption of thoroughbred racing competitions (Wisher et al. 1996).
In many cases, the lack of clearly visible symptoms means that the specific body system affected cannot be determined, while in others the point at which the onset of symptoms becomes notable is already beyond the threshold where an intervention can be used to preserve the performance of the horse.
There is therefore a need for the rapid pre- or post-symptomatic detection and early stage diagnosis of clinical and sub-clinical infectious conditions such as those resulting in inflammation, and to distinguish such conditions from other inflammatory conditions so that appropriate treatment can be given. Early stage diagnosis in such situations may be enhanced by maintaining a careful and precise history supported by scientific evaluation of the affected body systems.
In addition, when a problem is known or suspected with the horse, there is a need for regular monitoring of the severity of the problem, and the response to intervention(s), such as response to antibiotic or anti-infective treatment, or monitoring severity of exertional rhabdomyolysis to avoid musculoskeletal damage and over-exertion.
Further, there is a need for pre-performance screening for competitions and for official veterinary inspections. Furthermore there would be a benefit in screening newborns for infection.
There are a number of devices which are available for point of care testing however these devices are tools solely for the use of the veterinarian and are not designed to facilitate use by other equine professionals such as the trainer. Nor are they designed for diagnosis of equine disease or ER specifically. Examples of such instruments include those disclosed in U.S. Pat. Nos. 5,096,669 and 5,122,284. U.S. Pat. No. 5,096,669, incorporated herein by reference, discloses a system comprising a disposable device and handheld reader which can perform a variety of electrochemical measurements on blood or other fluids. The system has found use in the human clinical setting and has subsequently been adapted for veterinary use. U.S. Pat. No. 5,122,284, incorporated herein by reference, describes a benchtop analyser which requires the insertion of disk based cartridges containing a predetermined panel of tests. The device is developed for use of veterinary professionals and its size makes it most useful as a benchtop unit rather than a complete point of care testing device.
WO2013/088429 relates to a method and assay for eliminating the hook effect in the detection of a target analyte such as an acute phase protein in a bodily fluid in which the target analyte comprises a member of a specific binding pair comprising applying the sample to a solid phase carrier material, generating a signal in accordance with downstream movement of the labelled first or second members and the target analyte to bind with the complimentary immobilised first or second members, and detecting the presence of the target analyte in accordance with the signal generated at the complimentary immobilised first or second members.

Method of diluting a metred quantity of a test fluid for analysis


A system and method for managing experience information are disclosed. The system and method allow an organization to manage a plurality of issues and the organization's responsiveness to those issues. Moreover, the system and method allow an experience database to be populated with past issues and appropriate responses to those issues. When the organization receives an incoming issue from a source, the incoming issue may be compared against the experience. If a similar experience issue is found in the database, the corresponding appropriate response for the selected experience issue stored in the database may be forwarded to the source in near real time.

Responsiveness to customer issues and needs has become increasingly important to most modern businesses. Many, if not most, large customer driven organizations maintain a staff of customer service personnel. These staffs may include trouble shooters who can provide technical guidance as well as logistic specialist who can identify why a product was not shipped on time or why a product did not arrive on time.
Typically, as organizations increase in size, the number of customer issues received and the number of customer service personnel responding to those issues also increase. Unfortunately, the increased number of issues and personnel tend to make maintaining a record of customer issues and appropriate responses to those issues more difficult. This may be especially true for multi-national organizations.
At present, conventional data management tools for electronically tracking and reporting customer issues and appropriate responses are inadequate. Customer issue data, if collected at all, is collected in an inconsistent fashion and is, generally, difficult to share cross-functionally or globally. Moreover, the information gleaned from inconsistently collected data cannot confidently be treated as accurate.
Conventional techniques for managing customer issues and experiences include manually inputting an issue and an appropriate response for that issue into a spreadsheet (e.g., an Excel spreadsheet). This technique is inadequate for a number of reasons.
For example, requiring customer service personnel to fill out spreadsheets is labor intensive and time consuming. Additionally, conventional techniques often yield inconsistent and unreliable information. Other shortcomings include storage of data in a format, which often cannot be easily searched or interrogated. As a result, customer service personnel generally find it difficult to identify past issues and resolution data when working to solve a current issue that is similar to a past issue. Moreover, it may be difficult to generate trend reports necessary to identify areas in which the organization has seen either a significant improvement or a significant decline in performance.

System and method for managing customer experience information


The invention controls irregular wear in the shoulder land portions and reduces the occurrence of cracking in the shoulder grooves of a pneumatic tire. To that end, the groove wall surface (17a) on the shoulder land portion (19) side of the shoulder groove (17) has an inclined surface consisting of a first inclined part (171) inclined toward the equatorial plane of the tire at an inclination angle θ1, which is constant along the circumference of the tire, and a second inclined part (172) further inclined from the first inclined part (171) toward the equatorial plane of the tire and reaching the groove bottom (17b) of the shoulder groove (17) at an angle α with respect to the first inclined part (171), which varies along the circumference of the tire. Also, the inclination angles of the first and second inclined parts (171, 172) are set such that the maximum value αmax and the minimum value αmin of the angle α satisfy (D−d) (tan αmax−tan αmin)≧2.5 where D is the depth from the tread face to the bottom of the shoulder groove (17), d is the depth from the tread face to the boundary position between the first inclined part (171) and the second inclined part (172), αmax is the maximum value of the angle α, and αmin is the minimum value of the angle α.

Pneumatic tires having riblike land portions in the shoulder regions (shoulder land portions) continuously along the circumference of the tire, such as heavy-duty pneumatic tires, are subject to heavy loads on the shoulder land portions when the vehicle accelerates, decelerates, or makes turns. A conventional problem with such pneumatic tires, therefore, has been the frequent occurrence of irregular wear in the shoulder land portions or cracking in the shoulder grooves.
In a proposed method for controlling irregular wear in the shoulder land portions, the inclination of the wall surface of the shoulder land portion facing a shoulder groove, for instance, is varied at predetermined intervals along the circumference of the tire (see Patent Document 1, for instance).
On the other hand, proposed methods for reducing the occurrence of cracking in shoulder grooves have relied on enlargement of the groove bottom radius of shoulder grooves, provision on the wall surface facing the shoulder groove of the shoulder land portion a first inclined part inclining toward the groove center from the perpendicular line from the tread face of the shoulder land portion and a second inclined part inclining further inclining toward the groove center from the first inclined part, and the like so as to raise the rigidity of the shoulder land portions (see Patent Documents 2 and 3, for instance).

Pneumatic tire with tread having shoulder circumferential grooves


A method for manufacturing heat-radiative substrates on which semiconductor devices such as ICs and transistors are mounted and packages using the substrates, wherein a plurality of CuW or CuMo composite materials obtained by the infiltration method or the mixed powder sintering method are joined together with Cu interposed therebetween. Accordingly, the remaining empty holes within the CuW or CuMo materials are filled sufficiently with Cu, allowing high-quality packages having a successful thermal characteristic to be obtained.

1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor-mounting heat-radiative substrates in which a plurality of CuW or CuMo composite metal alloys having different compositions are joined together with Cu interposed therebetween and further relates to semiconductor packages using the substrates.
2. Description of the Prior Art
In the last few years, an increase in operating speed and degree of integration of ICs, transistors and the like as well as an increase in their capacity has involved increasing amounts of heat generated by semiconductor devices. As a result of this, it matters to a great extent how generated heat is eliminated and the devices are cooled to accomplish successful operation thereof. In terms of cooling devices, there is a similar problem also in parts related to semiconductor lasers. In order to solve this problem, composite materials formed of combinations of Cu and W, or Cu and Mo have recently come into practical use as heat-radiative substrates for mounting devices in packages in which semiconductors are accommodated.
These composite materials are manufactured by some methods, for example, (a) in which Cu melted in a reducing atmosphere is infiltrated into a porous product obtained by sintering W or Mo powder (as disclosed in Japanese Patent Laid-Open Publication No. 59-21032), and (b) in which W or Mo powder is mixed with Cu powder and moreover the result is sintered in a reducing atmosphere (hereinafter, referred to as mixed powder sintering method).
FIGS. 7 and 8 are sectional views showing typical constructions of conventional IC ceramic packages in which the above-described composite materials are used as heat-radiative substrates; and FIGS. 9 and 10 are sectional views showing constructions of such packages for use with transistors.
In FIGS. 7 and 8, designations are as follows: 21 denotes a substrate composed of CuW or CuMo; 22 denotes a multi-laminated ceramic substrate composed of, for example, Al.sub.2 O.sub.3 layers; 23 denotes an Si semiconductor device mounted on the substrate 21; 24 denotes a covar (Fe--29%Ni--17%Co) lead wire; 25 denotes a bonding wire; and 26 denotes a package composed of covar or Al.sub.2 O.sub.3.
The construction shown in FIG. 8 is such that the Si semiconductor device 23 mounting portion 21a of the substrate 21 is higher than the construction in FIG. 7. Accordingly, the terminal mounting portion 27 of the multi-laminated ceramic substrate 22 can be flush with the Si semiconductor device 23, thus advantageous for mounting devices.
The number of laminates of ceramic substrates is recently increasing with increasing capacity of ICs: the demand for such constructions is therefore increasing more and more.
Conventional transistor-oriented packages are now described, referring to FIGS. 9 and 10. In FIG. 9, on a BeO circuit substrate 28 in the center of a CuW or CuMo substrate 21 there is mounted an Si semiconductor device 23. In FIG. 10, on the other hand, as is the usual case for use with FETs (Field Effect Transistors) employing GaAs transistors as devices 29, a GaAs transistor device 29 is directly mounted to a protrusive portion 21b provided on a CuW or CuMo heat-radiative substrate 21 having a good heat conductivity and the device can be wired with a circuit 31 provided on an insulating ceramic substrate 30 in the vicinity of the device so as to be flush with the circuit, which type of construction is thus preferred.
The substrates 21 used in the packages shown in FIG. 7 and FIG. 9 out of the above-described ones are simple flat plates which do not involve much difficulty in manufacture thereof, whereas the stepped substrates partly having protrusions 21a and 21b as shown in FIG. 8 and FIG. 10 involve various problems on manufacture thereof.
These stepped substrates are manufactured, in general, by leaving protrusive portions on a sheet of flat plate and removing the remains thereof by cutting or grinding.
This method, however, is wasteful in material to be cut and, what is more, burdened with cost for cutting tools due to the fact that its substrate material is of combination of Cu, which is a soft material, and W or Mo, which is a hard, difficult-to-cut material, and therefore the cutting tools are unavoidably subject to intermittent cutting, with the result of their greatly worn edges, which requires cutting tools to be frequently exchanged to obtain high precision and suppress any after-processing machining distortions.
On the other hand, it is possible to provide these stepped substrates by taking the above-described methods, that is, by the infiltration method (a) that Cu is infiltrated into a stepped, sintered product of W or Mo or by the mixed powder sintering method (b) that mixed powder of W or Mo and Cu is molded into a stepped shape and then sintered. However, these methods are accompanied by the following problems.
The substrate 21 used for a package having such a configuration as shown in FIG. 8 is shaped as shown in FIG. 11, where the surface 33 brazed to the ceramic substrate 22 is larger in area than the surface 32 on which the semiconductor device 23 is mounted. The surface 33 is often required to be as thin as 0.3 to 0.5 mm, normally.
Accordingly, in manufacturing such substrates by cutting off a flat plate so as to leave a protrusive portion thereof, the area of the part to be cut off is large and, when the edge of the cutting tool is worn, the mounting surface 33 is deformed due to machining distortion in cutting, thus often encountering an obstacle in brazing it with the ceramic substrate 22.
Some other methods may be available to manufacture these substrates. For example, one method is that W or Mo powder is molded by die-pressing into a stepped shape similar to the foregoing one and Cu is infiltrated into a porous product obtained by sintering the molding result (the infiltration method). Another is that mixed powder of W or Mo powder and Cu powder is molded by die-pressing into a stepped shape similar to the foregoing one and the result is sintered (the mixed powder sintering method). However, as described above, in the shape of FIG. 11, the surface 33 to be brazed with the ceramic substrate 22 is thin such that a die-pressing result having the same density as the semiconductor-device mounting surface 32 is difficult to obtain. Moreover, even if a die-pressing result having the same density is obtained, the brazed surface 33, which forms the thin-wall portion of the die-pressing result, is low in strength, thus difficult to treat.
In addition, in order to obtain composite materials having no defects (empty holes). high-temperature treatment over the melting temperature of Cu is necessitated as the baking temperature. In order to fill empty holes sufficiently with Cu, excessive Cu needs to be added for baking, which causes the baking result to be covered in its surface with Cu. Accordingly, some countermeasure must be taken to remove the resulting Cu, requiring labor equivalent to that in manufacturing the substrates from flat plates by cutting.
Next, the heat-radiative substrate 21 used for transistor-oriented packages, having a sectional configuration as shown in FIG. 10, is shaped as shown in FIG. 12, where the protrusive portion 21b on which the GaAs transistor device 29 is mounted is much smaller than the flat portion 34.
Therefore, it is difficult to manufacture a die for press-forming such a protrusive portion and to charge powder into the die for die-pressing, involving some problems in manufacturing.
As a method for manufacturing such a stepped substrate, such one is available that the protrusive portion and the flat portion are separately prepared, subjected to Ni plating (to ensure the wetting of brazed material in brazing), and brazed along with the ceramic portion in manufacturing ceramic packages to obtain packages such as shown in FIG. 13. However, in this case, it is difficult to take a constant interval of a semiconductor-device mounting substrate 35 to a ceramic portion 36, and moreover, due to empty holes remaining within a brazing material 37 which is the joint surface between the substrates 35 and 36 and due to the intervening brazing material 37 having a low heat conductivity, heat conduction will adversely be affected. This will cause quality deviations of packages, disadvantageously.

Method for manufacturing semiconductor-mounting heat-radiative substrates and semiconductor package using the same


A polishing composition is shown which includes (1) a polishing media particle; (2) a film forming binder for suspending the particle and forming a temporary film on an exposed surface of the workpiece, the temporary film being dissolvable in a subsequently applied polishing wash, whereby the polishing media particle is freed to polish the workpiece; (3) a solvent for suspending the polishing media particle in the film forming binder to facilitate forming the temporary film; and (4) a wetting agent to improve the wettability of the composition on the exposed surface of the workpiece.

1. Technical Field
The present invention relates generally to compositions used for polishing and planarizing the surfaces of various workpieces, such as the surfaces of semiconductors.
2. Description of the Related Art
Compositions useful for polishing the surfaces of various workpieces are well known in the art. Conventional polishing compositions, which are used for polishing the surfaces of semiconductors, glass, crystal, metal and ceramic workpieces, generally comprise aqueous slurries of an appropriate abrasive agent or particle or mixtures of such particles. Commonly utilized abrasive agents include cerium oxide, aluminum oxide, zirconium oxide, tin oxide, silicon dioxide, titanium oxide, etc. Polishing compositions utilizing such agents are generally used by first applying the composition to a polishing pad or to the surface to be polished. The polishing pad is then applied to the surface, which causes the abrasive particles contained within the composition to mechanically abrade the surface, thus effecting the polishing action. However, such conventional polishing compositions used in the general polishing arts cannot produce the highly specular and planar surfaces required in semiconductor and microelectronic component technology. Moreover, conventional polishing compositions have demonstrated disadvantages, such as poor polishing rates and poor surface quality, in polishing other workpieces. For example, the surfaces of glass, metals and semiconductors polished with such compositions demonstrate various defects such as haze, stains, scratches, undulations, undercuts, mesas, etc.
Attempts have been made in the prior art to improve the existing, commercially useful polishing compositions. Two methods of attaining improvement in these areas include (1) the combination of various abrasives; and (2) adding various adjuvants to the compositions.
Examples of combinations of abrasive particles include combinations of, e.g., cerium oxide and a rare earth pyrosilicate. Examples of the use of adjuvants in polishing compositions include the use of salts such as potassium chloride or ammonium chloride or combinations of such salts to promote the polishing effectiveness of the metal surface by the abrasive agent. However, even the addition of cooperating abrasive agents or the addition of adjuvant materials, has failed to produce completely satisfactory polishing compositions capable of producing the planarized surfaces needed in modern semiconductor and microelectronics technology.
To provide superior results, special chemical mechanical polish (CMP) compositions must be used to polish or planarize the surface of prepared semiconductor workpieces. Such compositions must produce an extremely flat and level surface with a high quality polish, i.e., a planar surface. However, unlike conventional polishing to provide a planar surface, the polishing action must be restricted to the level surface of the workpiece and must not affect the topography, morphology and/or structures below the surface. Only such selective polishing action will produce the desired planar surface. Conventional polishing compositions are not suited for such procedures as they merely produce uneven, undulating surfaces by abrading certain regions on, below and within the surface of the workpiece. It has proven difficult, if not impossible, to use conventional polishing products to obtain smooth defect-free surfaces wherein the polishing composition does not adversely affect the underlying structure of the workpiece.
Even where specially designed CMP compositions are applied as an aqueous slurry to the workpiece, other shortcomings exist such as a high consumption rate of slurry, as well as shortcomings in the delivery of slurry to the center of the semiconductor wafer, via the polishing pad, while polishing the surface of the wafer flat. The polishing pad used also deforms to the surface of the wafer, preventing 100% perfect planarization from being achieved. Another problem with the prior art processes is that the CMP operation upon an oxide has no end point capability and therefore is dependent upon knowing and controlling the removal rate such that the operation can be timed to control the degree of planarization.
Accordingly, it can be seen that a long felt need exists for polishing compositions which provide improved polishing activity at improved rates and which will produce planar and defect-free surfaces, particularly in modern semiconductor and microelectronics applications.

Polishing composition for CMP operations


An exit bar for securing a door has a housing adapted for mounting to a door. A push pad for receiving a push force is mounted to the housing. A latch extends from the housing to releasably latch the door to which the exit bar is mounted. A link system links the push pad to the latch so that a push force exerted on the push pad releases the latch. An electromagnetic lock disposed in the housing locks the link system to prevent releasing of the latch. The electromagnetic lock employs an electromagnet and a movable armature to lock the link system. The exit bar further delays unlocking the link system for a preestablished delay time after the push pad has been pushed.

This invention relates to the field of door security systems. More specifically, this invention relates to the use of a push or exit bar for securing a doorway.
Push bars or exit bars which allow egress through a doorway while limiting ingress are well-known components of door security and emergency systems. The conventional exit bar is mounted on the interior side of the door to be secured and is oriented generally horizontally across the face of the door. A push force on the bar toward the door face operates a door latch to permit opening of the door. Conventional exit bars typically employ a mechanical linkage to actuate the latch mechanism for unlatching the door. Exit bars may also employ mechanical locks to secure the door from opening. A handle can be additionally provided on the exterior face of the door to allow ingress under certain circumstances. Exit bars have also been connected with alarm systems to warn security personnel of a door opening.
Conventional exit bar systems while enjoying great popularity have also exhibited a number of deficiencies. For example, to secure an exit bar from operating the associated latch may require individually manually locking each bar. For most applications, it is generally undesirable for safety reasons to permanently lock exit bars. Even when a building has low occupancy, there may be times when for emergency reasons, exit doors should not be secured in a permanent fashion that would inhibit egress.
During periods of high traffic levels through a doorway, mechanical latch mechanisms of a conventional exit bar can experience a high rate of wear. To reduce wear on mechanical latch components, some conventional exit bars may be manually locked in a dogged position wherein the latches remain in a retracted state. However, each bar must be directly manually dogged and undogged at the site of the door.
Similar problems arise with regard to exit bar systems that employ an auxiliary outside handle to allow selective ingress to a secured area. The operative mode of these outside handles must be generally individually manually changed by visiting the exit bar installation to set the desired mode.
In more advanced systems, alarms have been connected to exit bars to generate audible or visible indications when an egress is attempted. These alarms are generally not sophisticated in distinguishing between permitted and unpermitted egresses. In health care facilities, alarms may also be used to indicate attempts by patients to egress the facility. Such alarms are particularly important in facilities where patients may need monitoring or assistance in egressing. For example, in facilities caring for patients lacking full mental or physical competence, such as nursing homes or child care facilities, egress for some individuals should be prevented in other than emergency situations. However, a deficiency of many conventional exit bars is to allow immediate egress even when the exit bar is combined with an alarm. This may permit unauthorized personnel or patients to immediately exit a secured area.
Attempts have been made to combine exit bars with various forms of door locking and security systems to overcome some of the above-mentioned problems. Such hybrid systems, however, tend to result in excessive costs and complexity. Such combination lock systems may require mounting not only the exit bar, but also mounting an auxiliary lock system to the secured door.
Exit bars further can exhibit a deficiency common to many electronic lock systems. Typically, a large number of wires are required to be installed across the hinge connecting the door and door frame in order to provide a large number of functions for the exit bar. A single function may require two or three individual wires. The electrical connections across the hinge often necessitate special hardware and cable covers to hold the wires. These special materials can increase installation costs and reduce operating reliability.

Electromagnetically managed latching exit bar


A communications system between LANs of different types constituted of a backbone LAN (1) and a plurality of branch LANs (7, 7') connected to said backbone LAN (1) through a node (2A, 2B, 2C, 2D). A branch LAN frame (30) delivered from a terminal (8, 9, 10, 15, 18, 21) is incorporated into a backbone LAN frame (40) in the node (2A, 2B, 2C, 2D), and in response to the incorporation, the address of the adjoining node on the downstream side of its own node is given to the backbone LAN frame (40), and thus, the backbone LAN frame (40) is transmitted through the backbone LAN (1). Each node (2A, 2B, 2C, 2D), when the address in the backbone LAN frame (40) agrees with its own address, separates the branch LAN frame (30) from the backbone LAN frame (40).

With the progress of the information society, communications networks are playing the role of the nervous system of a wide variety of social and economical activities and great importance is placed especially on their reliability. Lately, there are increasing demands for a backbone LAN capable of accommodating medium- arid small-scale branch LANs and integrated processing of data, voice, and image, and some backbone LANs to meet such demands are being produced as multiple-media backbone LANs.
On the other hand, high speed data transfer between host computers has come to be demanded with the progress of horizontal distribution of computer processing. To meet such demand, a token ring LAN having a channel interface capable of being directly incorporated into a host computer is made available. Accordingly, as a means for achieving high-speed transfer within a multiple-media backbone LAN, it becomes necessary to have branch LANs such as token ring LANs incorporated in the multiple-media backbone LAN.
Conventionally, when a plurality of branch LANs such as token ring LANs have to be connected to a backbone LAN, the connection between these LANs has been achieved in general by means of a bridge function whereby a small loop is connected to a large loop through a node.
When communications are made between branch LANs connected as described above, one branch LAN sends a token ring frame to the backbone LAN. Then, the node of the backbone LAN reads the address data in the token ring frame and retrieves the address of the node to which the branch LAN located at the read address is connected, puts the address into the backbone LAN frame, and incorporates the token ring frame into the backbone LAN frame, arid thereupon, sends the backbone LAN frame to the destination node. The node at the destination separates the token ring frame from the backbone LAN frame and transmits the token ring frame to the terminal unit having its address concurring with the address in the token ring frame.
In the above described conventional communications system between LANs of different types, since the communication is performed such that the node reads the address data of the destination of the token ring frame, retrieves the node with which the terminal having that address is connected, and puts the address of that node into the backbone LAN frame, the node is heavily loaded, and this has been a cause impairing high-speed large-capacity communications between branch LANs. Hence, even if the transmission capacity of the backbone LAN is 100 Mbps, for example, throughput at 100 Mbps has not been attainable. Thus, there has been a problem that the capacity of the node is insufficient to attain high-speed large-capacity communications between host computers connected to each of the branch LANs.
Accordingly, an object of the present invention is to provide a communications system between LANs of different types capable of overcoming the above described problem in the prior art arid properly achieving high-speed large-capacity communications between branch LANs by way of a backbone LAN.

Communications system between LAN's of different types