A technique for monitoring optical power in a fiber array unit having a plurality of optical transmission waveguides terminating at an edge thereof for carrying optical signals to and/or from a PLC. A tapping filter is placed within a slit formed in the substrate and interrupting the transmission channels, thereby tapping at least some of the optical power from the channels and directing the tapped optical power toward respective photodetector channels for detection, while allowing other optical power to continue transmission in the at least one channel of the fiber array unit.

Conventional optical channel monitoring in planar waveguide circuits (PLCs) used for fiber-optic communication is usually implemented separately outside of the PLC product packaging; resulting in more complex integration of optical channel monitoring within an optical network. If the optical channel monitoring function is integrated into the PLC components, special PLC design is necessary, and the entire PLC component package should be hermetically sealed to protect against any moisture-related reliability concerns typically associated with semiconductor photodetector devices.
For example, if external optical channel monitors are considered, they require separate packaging from the PLC packaging; and optical path connection via optical fiber splicing, or other optical connectorization external to the PLC and fiber array units (FAU) which provide the fiber connection to the PLC along the PLC chip edge(s). The size of entire packaging will be increased, and optical connection paths also increase. Photodetectors as well as low-loss, zero-slope fused coupler components are necessary, requiring at least two fused splicing operations. This results in higher costs, larger size, and tedious assembly.
Power monitor detector chips inside the PLC packaging, attached directly to monitor waveguides along the edge of PLC chips, are also possible. However, this requires specially-designed PLCs, with dedicated monitoring channel waveguides (tapped on-chip from the operational waveguides) to drive the power monitor detectors attached to the chip. The detectors are separate from the fiber array unit(s) (FAUs) which always require attachment to the operational waveguides along the edge of the chip for network functionality. In this case, conventional off-the-shelf PLC chips cannot be utilized, because they usually will not have separate monitor waveguides. Also, the separate optical power monitor detector chips require anti-moisture environmental protection to provide long-term reliability. Special techniques are necessary to attach the detector chips to the edge of the PLC chip, aligned with the monitor waveguides. And, the entire PLC packaging still requires hermetic packaging which increases the packaging costs dramatically.
The present invention addresses these problems, by providing a power monitoring function, integral to the fiber array unit, requiring no special PLC re-designs, and facilitating hermetic sealing.

Fiber array unit with integrated optical power monitor


A USB connector includes a plug comprising an insulative member, a mating member, a first conductor assembly, two elongate flexible members, a metal case member comprising inner and outer pieces, and a plastic housing for enclosing the case member and comprising upper and lower shells; and a jack comprising a shield shell, an insulative unit, and a second conductor assembly. The flexible long member includes a U-shaped member formed by bending its one end, a claw at the other long end, a toothed member at one end, a protuberance proximate the U-shaped member opposite the toothed member, and a flexible arm extended between the claw and the protuberance. Inserting the arms through the insulative member will sandwich either claw between a latch and the shield shell, rest the arms on grooves, fasten the protuberances in slots, and fasten the toothed members in tunnels for assembling a main portion of the plug.

1. Field of Invention
The present invention relates to electrical connectors and more particularly to a mini-USB (Universal Serial Bus) connector having an improved, enhanced latching arrangement for insuring a reliable electrical connection of plug and jack thereof.
2. Description of Related Art
Reliable securing of an electrical connector in a port or to a mated connector is very important. For example, a mini-USB connector comprises a projection (or so-called plug) and a port (or so-called jack). Each of the plug and jack comprises an insulative body, a conductor assembly in the body, and a metal housing for enclosing the body.
However, the coupled plug and jack tend to become loose because for example the plug, attached to a cable, is provided externally to a coupled device and is thus subject to disengagement by pulling the cable. This can cause a poor electrical contact. However, the mini-USB connector incorporating the conventional construction cannot ensure a reliable connection because a resilient member of the plug may suffer elastic fatigue after a predetermined number of times of use and the coupling of the plug and jack may be compromised by inadvertently pulling the cable.
U.S. Pat. No. 6,902,432 describes a USB connector for interconnecting a computer and a peripheral and comprises a jack fixed to a circuit board and a plug provided at an end of a cable extended from the peripheral. The jack comprises a shield shell including a tongue having a V-shaped bent end on a top face, two grooves adjacent both sides of the tongue, and two cantilever shield contacts having a V-shaped bent end formed in the grooves. The plug comprises a housing body, a shield case projected from a front end of the housing body, and a rear electrical wire electrically connected to the shield case through the housing body. The housing body comprises a top hinged push member. The shield case comprises a top depression and two parallel flexible pieces spaced from the depression. Either flexible piece has a claw at its open end. The flexible pieces can be pressed down by two bottom projections at a front end of the push member by pressing the push member. In response to inserting the plug into the jack and electrically connecting the plug terminal to the jack terminal, the claws are fastened by the ends of the shield contacts and the end of the tongue is inserted in the depression.
The patent, however, is still somewhat complex in constructions. Thus, continuing improvements in the exploitation of USB connector are constantly being sought.


A steel band for a hose clamp has a main body and at least one pair of end portions, wherein each one of the end portions has at least one slotted hole receiving a clamping screw with a screw head. The end portions are bent to form loops. Each loop has first and second legs. First and second clamping members are inserted into the loops, respectively. The first and second clamping members have a substantially cylindrical periphery. The first clamping member has a transverse bore without thread receiving a threaded shaft of the clamping screw allowing free movement of the threaded shaft. The second clamping member has a transverse threaded bore engaging the threaded shaft of the clamping screw. The first and second legs are connected to one another near the free end of the first leg by a positive-locking connection.

1. Field of the Invention
The invention relates to a steel band for a hose clamp, the steel band comprising at least one pair of end portions which are provided with at least one closed longitudinal slot for guiding therethrough a clamping screw having a head and are bent to form loops. The legs of each loop, in the vicinity of the free end of one leg, are connected to one another and are provided for receiving one of two clamping members, respectively, which clamping members, at least over a portion of their periphery, are cylindrically shaped. One of the clamping members has a transverse opening without a thread for freely guiding therethrough the threaded shaft of the clamping screw, and the other clamping member has a transverse opening with a thread for engaging the threaded shaft of the clamping screw.
2. Description of the Related Art
In such a band for a hose clamp of the aforementioned kind as disclosed, for example, in any of the German patents DE 198 22 915 C1, DE 37 29 372 C2, DE 37 10 852 C1, DE 198 00 283 C1 or the German published patent application DE 39 26 626 A1, the legs of the loop are connected to one another by spot welding. In order to be able to manufacture such a welding connection in a permanent way, the band 1 for a hose clamp is comprised of stainless steel. Stainless-steel is an expensive material. In spite of this, there is still the risk of corrosion at the welding locations. A pre-galvanized band for a hose clamp which is, for example, coated with an alloy of aluminum and zinc, would be less expensive. However, a band for a hose clamp which is treated in this way cannot be welded.
It is an object of the present invention to provide a band for a hose clamp of the aforementioned kind which, while providing high stability under load of the loops in response to the clamping forces, can be manufactured less expensively and more easily.
In accordance with the present invention, this is achieved in that the connection of the legs of each loop is a positive-locking connection.
With such a configuration of the connection it is no longer necessary to employ welding. Also, it is no longer necessary to use stainless steel for the steel band. Instead, low-grade, inexpensive steel can be used which can be made corrosion-resistant by providing a coating.
The positive-locking connection of the legs of the loop can be realized in a simple way in that one leg of the loop is provided with projections projecting away from the plane of that one leg, wherein the projections project into holes of the other leg of the loop, and in that the one leg having the projections of each loop rests against the radially inner side of the band for a hose clamp in an area of the band forming a substantially circular clamp portion. In this connection, the holes can be produced simultaneously with the band for a hose clamp being cut to size from a longer material band by stamping. The projections can be formed in a simple way out of the band for a hose clamp and can be inserted into the holes. The end portion of the radially inner leg of the loop provided with the projections is then pressed during tightening of the hose clamp against the. inner side of the other leg of the loop. This provides an additional frictional connection between the legs of the loop which increases the stability and strength of the connection of the legs of the loop..
Preferably, it is ensured that one leg of each loop is provided with tabs cut out of the band for a hose clamp and bent out of the plane of that one leg, which tabs project through the holes of the other leg of the loop and are bent onto one side of the other leg of the loop. In this connection, producing the tabs and the holes can be carried out simultaneously with the step of cutting to size the band for a hose clamp from the longer material band by stamping. The connection of the tabs and the holes with a corresponding deformation of the tabs can also be realized in a simple way as known and conventional in the art.
Moreover, it is beneficial when at least one pair of tabs is provided whose tabs are bent in opposite directions relative to one another in a direction away from the longitudinal center axis of the band for a hose clamp to the longitudinal edges of the band for a hose clamp. In this configuration the tabs are then loaded as a result of resting against the edges of the holes only by transverse forces and not by bending stress. The positive-locking connection in this way can withstand even higher loads.
Preferably, it is ensured that the holes are wider transverse to the longitudinal direction of the band for a hose clamp than the band for a hose clamp is thick and that the tabs of each pair of tabs extend at a slant to the plane of the band from their base to the side of the leg onto which they are bent. In this configuration, a relatively large contact surface area between the edges of the holes and the tabs is provided in comparison to a configuration in which the edges of the holes and the tabs are crossing, one another at a right angle.
A further advantageous configuration resides in that each of the end portions of the legs of the loop provided with tabs is cut back to a reduced width in comparison to the main body of the band for a hose clamp up to the base of the tabs so that the band for a hose clamp has transverse edges and so that in a center plane of the band for a hose clamp perpendicular to the plane of the band, in the vicinity of the holes of each hole pair receiving a tab pair, a concave bead extends in the longitudinal direction of the band for a hose clamp. A backwardly bent end of the leg of the loop engages in a flush arrangement the hollow space of the bead. In this connection, a substantially continuous transition between the transverse edges of the end portion of the radially inwardly positioned leg of the loop having the tabs and the inner side of the remainder or main body of the band for a hose clamp is provided. When using a hose clamp provided with a band according to the invention for securing a hose on a pipe socket, the risk of a step-like transition of the inner diameter of the clamp hose occurring in the area of the transverse edges is substantially prevented so that a substantially uniform clamping force exerted by the clamp is realized about the circumference of the hose and, accordingly, a high sealing action of the connection between the hose and the pipe socket is ensured. At the same time, damage to the hose by such edges is prevented.
This configuration can be embodied in such a way that the bead extends between the holes of each pair of holes receiving a pair of tabs and that the material of the radially outer leg of the loop, when the band for a hose clamp is formed to the hose clamp, projects radially inwardly relative to the contour of the bead and the hose clamp in an area adjacent to the longitudinal sides of the bead, wherein the material of the outer leg of the loop projects at the transverse edges by the thickness of the band for a hose clamp and from these transverse edges, when viewed in the longitudinal direction of the bead, projects with a decreasing amount up to the contour of the bead.
An embodiment that is especially advantageous and long-lived comprises at least one of the projections embodied in the form of a rim hole which is riveted or upended at the side of the other leg.
As an alternative, the projections can be cup-shaped or nose-shaped and/or the projections can be the tabs.


An integrated structural system for a vehicle is provided. The integrated structural system includes a molded duct system configured to guide airflow having a first section and a second section and configured to operably attach a vehicle component thereto. The integrated structural system also includes a metal structure integrated with the molded duct system by means for integrating the metal structure with the molded duct system forming an integrated structural load path assembly. The integrated structural load path assembly is configured as a load bearing area to distribute a load of the vehicle component operably attached thereto. The means for integrating the metal structure with said molded duct system include, but not limited to, at least one of, sonic welding, heat staking, insert molding, and gluing.

Typically, a steering assembly of a vehicle includes a steering column extending between a steering mechanism, for example, a steering wheel, and a torque distribution mechanism. The steering column is designed to translate rotation of the steering wheel by a vehicle operator to the torque distribution mechanism which correspondingly positions the wheels of the vehicle in accordance with the position of the steering wheel, thus steering the vehicle.
It is desired that the steering column be of a sufficient compressive, shear, and torsional strength to endure the above described usage. The steering column designed as such can have a substantial mass and thus must be properly supported within the vehicle for effective functioning of the vehicle steering assembly.
Accordingly, the steering column is supported by attachment to a cross-car structural beam located within the vehicle. The load resulting from the weight of the steering column and other loads encountered during vehicle usage are distributed through the cross-car structural beam to side walls of the vehicle and/or to other parts of the vehicle where the cross-car structural beam is mounted thereto. The weight of the steering column is thereby conveyed, through the side walls and/or other vehicle parts, to a steel frame of the vehicle. Other parts of the vehicle which lend to the structural support system include, for example, a vehicle body, a front-of-dash, etc.
The cross-car structural beam is generally a load-bearing member that is also used to support an instrument panel assembly and a heating ventilation and air conditioning (HVAC) structural duct system, both located about the beam. The structural beam further serves as a reaction surface for occupant protection devices such as air bags or knee bolsters.
The steering column is typically attached to the cross-car structural beam directly or by a steering column support structure. The steering column support structure is composed of a metal or a composite and is attached at a first end to the cross-car structural beam and at a second end to the steering column.
The steering column support structure must support the load of the steering column and other loads associated with vehicle usage and effectively distribute the loads to the cross-car structural beam for distribution to the side walls of the vehicle.
Typically, the steering column structural support is mechanically attached at the first end to a load bearing area of the cross-car structural beam. The load bearing area is generally a portion of the cross-car structural beam and may be located, more specifically, at an underside of the beam. The steering column structural support is attached to the load bearing area by one or more threaded bolts and secured with fasteners such as nuts.
Lightweight air duct assemblies are composed of a molded plastic or a molded plastic composite and are mounted to the rigid cross-car structural beam. A metal-to-plastic interface between the nut/bolt arrangement and the air duct tends to degrade the plastic of the air duct. Hence, the overall attachment of the steering column and the cross-car structural beam is degraded. Thus, the use of extra parts, such as washers and the like, must be employed to preserve the plastic of the structural air duct.
The attachment of the steering column structural support and the cross-car structural beam using the nut/bolt arrangement must be performed manually and requires the handling of several parts and tools, thus valuable labor time is consumed and extra expense incurred.
Accordingly, it is desirable to have a structural attachment system for attaching, inter alia, a steering column to a cross-car structural beam that is light weight, simple to manufacture and assemble, provides an effective and efficient means to provide HVAC ducting and allow attachment of other components without the addition of separate brackets and additional hardware. Thus, a structural attachment system having less parts and assembly, more strength, and increased packaging space is desirable.

Structural hybrid attachment system and method


Provided is an apparatus of digitally controlling a plant pot including a case coupled to the outer circumference of the pot, a moisture sensor drawn from the case, for detecting moisture in soil contained in the pot, a liquid crystal display (LCD) installed in the case, for displaying a text or icons, an audio output portion for outputting a voice message, a message storage portion for storing an orderer's message and controlling messages, a data input/output portion connected to a personal computer, for inputting/outputting message data, a key input portion for inputting key signals through a key pad such as a power key or a record key, a battery for supplying power to each circuit block, and a controller for performing a plant pot controlling program, reading a message stored in the message storage portion in response to the moisture sensor and a signal from the key input portion to output a voice to the audio output portion, displaying the name of a plant planted on the pot and information for controlling the plant on the LCD in the form of a text, displaying the current control state of the plant pot in the form of an icon, and downloading the message data from the personal computer through the data input/output portion or uploading the control state data to the personal computer.

In general, delivery of plant pots as congratulatory gifts in celebration of opening for business or other events is prevalent.
Up to date, delivery of a congratulatory plant pot has been made in such a manner that a sender's name was written on a ribbon put on the plant pot and a recipient found out the sender's name written on the ribbon. Thus, the sender must express his/her intention of sending a plant spot over the telephone prior to delivery of the same. In any event where the sender could not communicate the recipient, the sender must offer his/her congratulations over the telephone even after delivery.
After finishing a congratulatory event, the ribbon put on the plant pot must be removed. If the ribbon is removed, it is difficult to know who sent the plant pot, which is then inattentively taken care of. Thus, the plant set on the plant pot may be withered to death due to inattentive care.
Also, ordinary people tend to be ignorant of kinds of plants and characteristics thereof, except for several well-known plants, and they do not know how to cultivate the plants, leading to lack of affection for the plants or inattentive care of the same.

Apparatus and method for digitally controlling plant pot, and method for ordering plant pot delivering on-line


A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.

1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to a method of making integrated circuits and integrated circuits utilising local interconnect conductors.
2. Description of the Prior Art
It is known to make and provide integrated circuits formed from processes involving multiple stages of lithography, deposition, etching, implantation etc. Advances in these processes have permitted device geometries to reduce thereby increasing the circuit density achievable and reducing cost. Recent production geometries have used devices with feature sizes of 45 nm. Projected future devices are expected to have sizes of 32 nm followed by 22 nm. As these device geometries become smaller, it is becoming increasingly difficult to form the patterns on the integrated circuit during manufacture necessary to create the desired circuit elements. In particular, if it is desired to produce lithographic shapes (patterns) including non-rectilinear shapes, then the accuracy and reliability with which such shapes can be produced is a significant difficulty in producing such integrated circuits. Rectilinear shapes are easier to reliably form. However, it is difficult to make the required connections and circuits using only rectilinear shapes when producing a circuit cell library for forming integrated circuits.
Another factor limiting the density with which circuit elements may be formed upon an integrated circuit is illustrated with reference to FIGS. 1 and 2 of the accompanying drawings. FIG. 1 illustrates a transistor 2 formed using a diffusion region 4 within a substrate 5 over which are formed a gate electrode 6 (a polysilicon channel) separated by a gate insulator layer 8 from the diffusion region 4. A source connection conductor 10 and a drain connection conductor 12 serve to provide a source electrode and a drain electrode contacting the diffusion region 4. The gate electrode 6 is provided with a gate connection conductor 14. The source connection conductor 10, the drain connection conductor 12 and the gate connection conductor 14 all extend through an insulator layer 16 toward Metal1 layer connections 18, 20, 22.
When manufacturing the transistor 2 illustrated in FIG. 1 it would be normal to form the diffusion region 4 in the substrate 6 and then deposit the gate insulator layer 8 and the gate electrode 6 over the diffusion region 4. The insulator layer 16 would then be formed covering the gate electrode 16 and the diffusion region 4 before a source opening, a drain opening and a gate opening were etched through the insulating layer 16 to respectively reach the diffusion region 4 to provide the source access, the diffusion region 4 to provide the drain access and the upper surface of the gate electrode 6 to provide gate access. The source opening, the drain opening and the gate opening are then filled with connection conductor material, such as tungsten, in a deposition step. Subsequently the Metal1 connections 18, 20, 22 are formed over the source connection conductor 10, the drain connection conductor 12 and the gate connection conductor 14 so as to provide electrical connections to other portions of the integrated circuit concerned.
As illustrated in FIG. 1, the etch depth required in order to etch the source opening and the drain opening is significantly greater than the etch depth required to etch the gate opening. The etching process used to etch through the insulating layer 16 will remove material of the insulator layer, but will not remove the gate electrode 6 to any significant degree. Accordingly, providing the alignment of the gate opening is accurately over the gate electrode 6, then the etching of the gate opening will stop when it reaches the upper surface of the gate electrode 6. The etching of the source opening and the drain opening will continue until the surface of the diffusion region 4 is reached. However, if the alignment of the etching of the gate opening is not sufficiently accurate, it is possible that the gate opening may continue down the side of the gate electrode 6 and reach the diffusion region 4. In this case, when the gate connection conductor 14 is then deposited in the gate opening, it will create a short circuit past the gate insulator layer rendering the transistor 2 non operative. It will be appreciated that in a modern integrated circuit containing many millions of transistors, if only a few of these transistors are incorrectly formed, then the entire integrated circuit may not function properly. Accordingly, the alignment of the gate opening over the gate electrode 6 is a source of failure which is conventionally addressed by the arrangement illustrated in FIG. 2. FIG. 2 illustrates a plan view of the transistor 2 shown in FIG. 1. As is illustrated in FIG. 2, the gate opening and the subsequently formed gate connection conductor 14 are offset so that they do not overlie the diffusion region 4. Thus, any misalignment in the etching of the gate opening may cause an excessively deep gate opening to be formed, but this gate opening will not reach the diffusion region 4 and accordingly cannot cause a short circuit past the gate insulating layer 8. Thus, a common design rule when forming circuit cells for integrated circuits is that the gate opening where the gate connection will be formed must not overlie the diffusion region 4. Whilst this approach avoids the short circuit problem discussed above, it reduces the density achievable for circuit elements within the final integrated circuit.

Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region


A portable storage enclosure is presented. The enclosure is a substantially rectangular enclosure formed of wood, having fixed ends and sides. The enclosure may have a back formed of slats held by grooves in the ends and/or sides. The enclosure has two sliding doors, each configured with an aperture, so that the apertures may be used both to manipulate the doors, and as handles to lift and transport the enclosure. The sliding doors have two closed positions, so that the apertures are oriented together at the center of the enclosure, or apart at the ends of the enclosure. The enclosure may also have handles on the ends and/or sides to facilitate carrying the enclosure in several orientations.

People bring many items to a tail-gate party, including, but not limited to, food, beverages, and games. There are several devices used for transporting such items, such as plastic coolers, paper and cloth shopping bags, and wooden crates. However, some of these devices, such as plastic coolers, have negative environmental impacts, both in their production, and in their disposal. For example, plastic coolers are typically formed of petroleum products, requiring drilling and refining. Such plastics are typically not biodegradable. Cloth and paper bags and picnic baskets may not be sturdy enough to transport heavier items. While wooden crates may be more stable and sturdy than bags and baskets, they may also be more difficult to open and close, and may also be unwieldy to transport.
Besides practical concerns, the abovementioned solutions are not particularly visually appealing. Tailgating is taken very seriously by many people who may wish to provide a more upscale atmosphere than created by plastic coolers, crates and shopping bags. There is therefore an unmet need in the industry to address the abovementioned shortcomings.

Portable storage enclosure with sliding doors


A slip-resistant magnetic sheath includes a hollow sleeve that can be fit onto the screwdriver's shank. A magnetic part positioned at least on one end of the hollow sleeve, provides auxiliary attraction to improve the connection between the shank and the screw with a fastening rim and groove set correspondingly on the sleeve of the magnetic sheath and the shank. The groove allows the fastening rim to move within a pre-set distance so that the magnetic sheath can slide within certain distance and not fall off the shank. The invention installed on an electrical screwdriver can effectively address the slipping problem caused by shocking. The forceful magnetic attraction of the magnetic sheath can prevent the screws from slipping and therefore improve working efficiency.

Due to the loose connection between the screwdriver head and the groove of the screw, traditional screwdrivers (such as a cross screwdriver and straight screwdriver) often lose screws while screwing and therefore affect the effectiveness of work. Though the screwdrivers might be magnetized, the magnetic force is too weak and short to solve the problem for good. In a fast developing world, efficiency is deemed to be the most important. Electrical screwdrivers have become an indispensable tool. However, it shocks so severe that the screws often fall off the screwdriver and causes much inconvenience to the users and accordingly affects efficiency.
Therefore, a new invention is called for to solve above problems.
In light of this, drawing on years' experience in the design and manufacturing of relevant products, this inventor proposes a practical invention after careful design and evaluation to achieve above purpose.

Slip-resistant magnetic sheath for a screwdriver


In a method of assembling an enhanced media content narrative, a navigation grid is initially defined by program name, chapter name and sub-chapter names. The grid is populated with program element file names, and the content is associated with the element file names in each chapter/sub-chapter. An automated toolbar is created for the grid matrix and combined with introductory content to provide an enhanced media content narrative for playback by a viewer.

1. Field
Example embodiments relate in general to a method of assembling an enhanced media content narrative.
2. Related Art
In the inventor's co-pending '721 application, the example system and method formats content, such as for intra-program navigation, in a completely different way—a displayed row-by-column navigation grid matrix that has a formatted organization between chapters (forming columns) and sub-chapters (forming rows and related to or tied to the columns). The chapter/sub-chapter organization of the navigation grid facilitates a user's ability to select their own navigation path through many selectable alternative scenes (that are not fixed or tied to a particular decision). The user selections can be stored in a desired sequence as a digital file, to be played back as a modified version of the video program being viewed.
DVR technologies such as TiVo® permit viewers to move back and forth along a linear collection of scenes. The example navigation grid allows viewers to move between the scenes, behind the scenes, and beyond the scenes. The example methodology described in the '721 application gives producers the ability to use all the content, and provide audiences with richer, niche entertainment.
After a program is edited into shorter subject-specific clips, clips can be identified and arranged in the navigation grid in the aforementioned chapter and sub-chapter format. In an example, chapters can be specific storylines, event, or characters. In an example, sub-chapters can establish time progression and evolution. Each row of the grid represents a sub-chapter of selectable elements that are common to all columns, and each column represents a chapter having designated sub-chapters therein that are tied to the respective chapter.

Method of assembling an enhanced media content narrative


An alignment logic together with an MFI extractor are adapted to compensate for differential delays. The MFI extractor extracts the MFI disposed in the path overhead of each constituent time-slot. The alignment logic uses the extracted MFI to align corresponding data words (i.e., data words that are transmitted during the same time period) at the receiving end of virtually concatenated channels and that occupy different time-slots of the same channel. To perform alignment, the alignment logic stores each data word in a RAM location that is defined by an associated MFI. The data words so stored are aligned when read sequentially from their stored locations. The synchronization logic in the alignment logic synchronizes all the constituent time-slots.

The present invention relates to communications network, and more particularly to concatenation of channels in a communications network.
Demand for high performance communication networks capable of transporting multiple types of data, such as text, audio and video data, is on the rise. To carry greater amount of data over existing communication channels, such as fiber-optic communication channels, network carriers are increasingly using high bandwidth technologies, such as wave division multiplexing (WDM) and optical carrier (OC) level 48. Such communication networks rely upon high-performance packet switches, such as asynchronous transfer mode (ATM) switches, frame relay switches and internet protocol (IP) routers which route the incoming packets to their desired destinations.
A commonly known standard referred to as synchronous optical network (SONET) defines a synchronous frame structure for transmitting signals using time division multiplexing. The basic building block of a SONET frame, commonly referred to as synchronous transport signal-1 (STS-1) includes 810 bytes that are transmitted every 125 μsec. Therefore a SONET channel carrying STS-1 frames (i.e., an STS-1 pipe) has a bit rate of 51.84 Mb/s, which has a corresponding optical signal referred to as OC-1.
Many STS-1 pipes may be contiguously concatenated to achieve higher bandwidths. For example, three STS-1 pipes may be contiguously concatenated to transmit three STS-1 frames, thus to achieve a bit rate of 155.52 Mb/s. In the following, the designation −Nc (N is an integer) appended to STS indicates the number of STS-1 pipes that are contiguously concatenated. For example, STS-3c indicates contiguous concatenation of three STS-1 pipes. In a similar manner, STS-12c indicates contiguous concatenation of twelve STS-1 pipes.
STS-1 or STS-Nc frames transported over contiguously concatenated pipes travel as a single unit with the granularity of the larger concatenated pipes. For example, in a STS-12c traffic—which signifies concatenation of 12 STS-1 pipes—adding or dropping of data by add/drop multiplexers are carried out at 12c granularity. The higher granularity simplifies such tasks as error control, performance control and error monitoring of the contiguously concatenated data. Many smaller pipes may be concatenated to form a larger pipe. For example, to form a STS-12c pipe, either twelve STS-1 or four STS-3c may be concatenated. In contiguous concatenation, data carried in time-slots associated with the smaller pipes travel through the same paths and thus have substantially similar propagation delays. For example, all STS-1 frames of a contiguously concatenated STS-12c travel through the same path.
The number of pipes that may be contiguously concatenated is typically limited to integer multiples of four STS-3c pipes, e.g. STS-12c, STS-48c, STS-192c, etc. Consequently, if a user desires to transmit data at, e.g., five times the bandwidth of an STS-1 pipe (i.e., at STS-5c), the user is required to use a STS-12c pipe or higher. This results in inefficient and wasteful use of bandwidth and thus increases cost. Furthermore, many of networking devices currently deployed, such as add/drop multiplexers, only operate at the STS-1 or STS-3c levels. Therefore, even if, for example, STS-12c is allowed by the standards, because associated frames of such a pipe travel together as a bundle, every networking device disposed between the transmitting and the receiving end of such a pipe is required to process these frames at the 12-c level. Therefore, to the extent that many of the currently deployed networking devices are adapted to operate at STS-1 or STS-3c levels only, they are unable to handle STS-12c data frames, thus rendering such concatenated pipes ineffective.
To more efficiently utilize the SONET/SDH bandwidth, virtual concatenation has been developed. Virtual concatenation is defined, in part, by the ANSI T1-X1.5, which is an evolving standard. In accordance with the virtual concatenation, any number of smaller STS-1 or STS-3c pipes may be grouped together to form a larger pipe. For example, three STS-1 pipes may be virtually concatenated to form a STS-1-3v pipe. In the following, it is understood that −Nv (N is an integer) appended to either STS-1 or STS-3c designates the number of respective channels that are virtually concatenated. For example, STS-1-12v designates virtual concatenation of twelve STS-1 pipes. Similarly, STS-3c-16v designates virtual concatenation of sixteen STS-3c pipes.
In virtual concatenation, data carried in time-slots associated with the smaller pipes may travel through different paths with different propagation delays. Synchronization is maintained between the transmitting end and the receiving end such that the virtually concatenated channels appear as contiguously concatenated channels. Because virtual concatenation enables concatenation of any number of smaller pipes, it overcomes some of the above described problems associated with contiguously concatenated pipes. For example, virtual concatenation enables forming a STS-1-5v pipe which, as described above, does not have a contiguously concatenated counterpart pipe, i.e., there is no STS-5c pipe. Moreover, because in virtual concatenation, the basic building blocks STS-1 or STS-3c, i.e., the frames with the lowest granularity, are not bundled together, they are readily supported by currently deployed networking devices.
Data bytes transmitted through virtually concatenated channels are originally aligned across their constituent time-slots. However, data belonging to different time-slots may be transmitted through different paths with different delays. Therefore, data bytes are typically not aligned when received by a receiver. FIG. 1 shows data bytes associated with three time-slots 1, 2 and 3 as transmitted and received across one channel. As seen from FIG. 1, data bytes D1, D2, D3, D4, D5, D6, D7 . . . of each of time-slots 1, 2 and 3 are aligned when transmitted at the transmitter end. However, due to differential delays, while time-slot 1 receives data bytes D4, D5, D6 and D7, . . . time-slot 2 receives data bytes D1, D2, D3 and D4, and time-slot 3 receives data bytes D6, D7, D8 and D9 Note that, for example, data byte D1 of time-slot 2 is aligned with data byte D4 of time-slot 1 and data byte D6 of time-slot 3. Therefore, as seen from FIG. 1, the data bytes associated with time-slots 1, 2 and 3 are not aligned when received by a receiver.


The invention relates to a composition comprising: a) a propylene homopolymer or propylene-ethylene copolymer having an ethylene content of at most 1.5 wt % based on the weight of the propylene-ethylene copolymer, said a propylene homopolymer or propylene-ethylene copolymer having: i) a Mw/Mn in the range of 4.0 to 12, wherein Mw stands for the weight average molecular weight and Mn stands for the number average molecular weight and wherein Mw and Mn are measured according to ASTM D6474-12; ii) an XS in the range from 1.0 to 8.0 wt %, wherein XS stands for the amount of xylene solubles which are measured according to ASTM D 492-10; and iii) a melt flow rate in the range of 1 to 10 dg/minas measured according to ISO1133:2011(2.16 kg/230° C.); b) a first additive, being one or more tocopherols and/or one or more tocotrienols; and c) a second additive, being an organic acid scavenger. The invention moreover relates to a biaxially oriented polypropylene (BOPP) film comprising said composition, to a process for the preparation of a biaxially oriented polypropylene (BOPP) film and to the use of the composition for the preparation of an article, preferably a BOPP film.

For many applications, biaxially oriented polymer films are required. Biaxially oriented polymer films are usually prepared from reheating an unoriented polymer film to a temperature at which the crystals are partially melted and subsequently stretching it into the desired shape. The stretched film is cooled, which reforms the crystals and thereby locking the orientation into place. The properties of biaxially oriented polymer film are highly dependent on the orientation of the polymer chains.
For many biaxially oriented polymer film applications, polypropylene is the material of choice. The polypropylene chosen for such process has to meet the properties required in the end product (the biaxially oriented polypropylene film) as well as the properties required for manufacturing the film and during the stretching process. BOPP films are also known as oriented polypropylene films, and are used in a wide variety of applications, such as packaging and capacitor films.
BOPP films may be produced through a simultaneous or sequential biaxial stretching process, in which films are cold drawn in two consecutive steps at two different temperatures. However, a commercial one step biaxial stretching technique also exists, which allows the production of uniform and highly oriented films at high speed while minimizing energy and production line breaks occurring during deformation. The trend towards using the faster production lines makes it necessary to develop new polymeric compositions that resist the stress encountered during processing without loss of mechanical and optical properties. Depending on the end-use, polypropylene intended for the production of BOPP films, the so-called BOPP grades, therefore has to meet some important challenges.
CN101597401 discloses a BOPP grade having high permeability, high rigidity (stiffness), excellent transparency and gloss for cigarette packaging film without affecting the processing performance is obtained by including a nucleating agent consisting of 2,2-methylene-bis (4,6-di-t-butyl phenoxy) phosphate.
For BOPP grades, a good processability is important as well as good aesthetic performance, especially for the many packaging applications. There is also an increasing demand (and more strict regulation) for increasingly pure BOPP grades comprising less additives or more bio-inspired additives. For the purpose of the invention, with bio-inspired is meant synthetically produced mimicking a natural source or obtained from a natural source.

This patent is subject to a terminal disclaimer.

Polypropylene composition for use in BOPP application, a process for preparing BOPP films and said BOPP film


A semiconductor memory device comprises an input unit inputting an address and data; a storage unit storing data and a FAT; an address conversion unit converting the address; an access unit accessing the storage unit according to the converted address; a detection unit detecting a format of the FAT; and an alteration unit altering conversion rules in the address conversion unit according to the detection.

1. Field of the Invention
The present invention relates to a semiconductor memory device and an operation method thereof.
2. Description of the Related Art
Various devices have become compatible with the memory card in these years. For example, the memory card is used for cellular phones to store camera-taken images, music, and video, backup of built-in memory, and the like. And, the memory card is being made to have a larger capacity. An 32-GB memory card having a capacity larger than that of DVD is already on the market, and the memory card is being advanced to have larger capacities. The large-capacity memory card stores various kinds of user data (for example, personally shot image data, copyright-protected music and video data, and personal information).
Formatting is generally used to erase all user data in the memory card. The formatting includes full formatting and quick formatting. The full formatting erases the whole user data in the memory card. Meanwhile, the quick formatting erases data of an area (for example, FAT1 area) managing the file system of the user data to disable the access to the user data. As a result, there is provided the same effect as the erase of the user data itself.
Since the full formatting of a large capacity memory card requires a considerable time, the quick formatting is usually used, and the users also often select the quick formatting. And, there is also a host device which is compatible with quick formatting only.
According to the quick formatting, the user data can be read because the user data itself is remained in the memory card. For example, there is commercially available software which restores the erased data if data in the memory card is accidentally erased.
SSD (Solid State Drive), in which a hard disc is replaced with NAND type flash memories, has been developing as new memory devices.
In order to prevent data that is recorded on a recording medium from unwanted outflow, there is disclosed a technology of recording data by encrypting the data, performing address conversion of a designated address, and recording the data by using the converted address (JP-A No. 2004-152440).
Even if the data is encrypted, however, the data might be decoded by analyzing the encrypted data if the data could be fetched as it was.

Semiconductor memory device and operation method thereof


A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; receiving one or more error indications for the detected sequence, each of the one or more error indications identifying one of the data bits of the detected sequence that may have an erroneous value; detecting errors in the detected sequence based on the error detection code bits in the detected sequence; and generating a candidate sequence based on the detected sequence and the one or more error indications when errors are detected in the detected sequence.

The present invention relates generally to error correction for digital data. More particularly, the present invention relates to the use of error detection codes to correct errors in digital data.
FIG. 1 shows a conventional write channel 100 for writing data to a hard disk 102. Write channel 100 comprises a cyclic redundancy check (CRC) encoder 104, a Reed-Solomon (RS) encoder 106, and a channel encoder 108.
FIG. 2 shows a conventional write process 200 for write channel 100 of FIG. 1. CRC encoder 104 encodes user data u (step 202) using a CRC code to create CRC codeword bc, which comprises user data u and CRC bits c. RS encoder 106 encodes CRC codeword bc (step 204) using a RS code to create RS codeword brs, which comprises user data u, CRC bits c, and RS bits r. Channel encoder 108 encodes RS codeword brs (step 206) using a channel code such as a run-length limited (RLL) code to create channel codeword brll, which is written to disk 102 (step 208).
FIG. 3 shows a conventional permuted write channel 300 for writing data to a hard disk 302. Write channel 300 comprises a CRC encoder 304, a RS encoder 306, channel encoders 308 and 310, and a multiplexer 312.
FIG. 4 shows a conventional write process 400 for permuted write channel 300 of FIG. 3. Channel encoder 308 encodes user data u (step 402) using a channel code such as a RLL code to create channel codeword br1. CRC encoder 304 encodes channel codeword br1 (step 404) using a CRC code to create CRC codeword bc, which comprises channel codeword br1 and CRC bits c. RS encoder 306 encodes CRC codeword bc (step 406) using a RS code to create RS bits r.
Both RS encoder 306 and CRC encoder 304 are systematic encoders. Therefore, the RLL constraints in br1 are preserved after the CRC and RS encoding. The CRC bits c and RS bits r are then encoded by channel encoder 310 (step 408) to ensure good RLL properties in those bits, thereby generating channel codeword br2. Multiplexer 312 codewords br1 and br2 as channel codeword bd before writing the channel codeword bd to disk 302 (step 410).
The purpose of the CRC code in conventional systems is to detect any remaining error after the RS decoding when reading the data back from the disk. The CRC encoder calculates the CRC bits c based on the user data u and a pre-selected generating polynomial. In the read channel, if the CRC bits c agree with the data bits after RS decoding, the RS decoding result is considered correct. Otherwise, a RS decoding error flag is raised.
FIG. 5 shows a conventional read channel 500 that can be used to read data from a hard disk 502 that was written by a conventional write channel such as write channel 100 of FIG. 1. Read channel 500 comprises a channel detector 504, a channel decoder 506, a RS decoder 508, and a CRC decoder 510.
FIG. 6 shows a conventional read process 600 for read channel 500 of FIG. 5. Channel detector 504 receives a signal from disk 502. For example, the signal can be produced by a head moving over data recorded on hard disk 502. Channel detector 504 produces a detected sequence of digital data (step 602), sometimes referred to as "hard decisions," based on the signal received from hard disk 502, according to conventional techniques such as Viterbi detection.
Channel decoder 506 decodes the detected sequence (step 604) according to a channel code, which often includes a run-length limited (RLL) code and a parity code. RS decoder 508 decodes the output of channel decoder 506 (step 606). CRC decoder 510 decodes the output of RS decoder 508 (step 608).
FIG. 7 shows a conventional permuted read channel 700 that can be used to read data from a hard disk 502 that was written by a conventional permuted write channel such as write channel 300 of FIG. 3. Read channel 700 comprises a channel detector 504, channel decoders 506 and 706, a RS decoder 508, and a CRC decoder 510.
FIG. 8 shows a conventional read process 800 for read channel 500 of FIG. 5. Channel detector 504 receives a signal from disk 502. For example, the signal can be produced by a head moving over data recorded on hard disk 502. Channel detector 504 produces a detected sequence of digital data (step 802), sometimes referred to as "hard decisions," based on the signal received from hard disk 502, according to conventional techniques such as Viterbi detection.
Channel decoder 506 decodes the detected sequence (step 804) according to a channel code, which often includes a run-length limited (RLL) code and a parity code. RS decoder 508 decodes the output of channel decoder 506 (step 806). CRC decoder 510 decodes the output of RS decoder 508 (step 808). Channel decoder 506 decodes the output of CRC decoder 510 according to the channel code (step 810).
In a conventional permuted read channel 700 (FIG. 7), channel decoder 706 decodes the channel detector output according to the channel code, such as parity code, and it also decodes CRC/RS bits according to RLL codes, i.e., restore c and r from br2 (FIG. 3); channel decoder 506 decodes RLL codes only.

Error correction using error detection codes


An ultrasonic driving device includes a protection module that receives a first drive signal from a signal generating module, detects an operating current of an output module, and provides the first drive signal to the output module when the detected operating current is smaller than a threshold current value. The output module adjusts the first drive signal received from the protection module to result in a second drive signal. The protection module stops providing the first drive signal to the output module such that the output module ceases to generate the second drive signal when the detected operating current is not smaller than the threshold current value. An ultrasonic transducer is connected to the output module so as to receive the second drive signal therefrom and so as to output ultrasounds, the frequency of which corresponds to that of the second drive signal.

1. Field of the Invention
The invention relates to a driving device, more particularly to an ultrasonic driving device with current limiting protection.
2. Description of the Related Art
Ultrasonic cleaners are cleaning devices that use ultrasounds (above 20 kHz) to excite a cleaning liquid in which articles to be cleaned are immersed.
FIG. 1 illustrates an ultrasonic driving device 3 employed in a conventional ultrasonic cleaner. The ultrasonic driving device 3 includes a signal generating module 31, an output module 32, an ultrasonic transducer 33, and a high voltage source module 34. The signal generating module 31 provides an alternating current first drive signal (Vd1).
The high voltage source module 34 receives a first alternating current power signal (Vac1) from a commercial power source, and adjusts the voltage of the first alternating current power signal (Vac1) to result in a second alternating current power signal (Vac2).
The output module 32 receives the first drive signal (Vd1) and the second alternating current power signal (Vac2), and adjusts the amplitude of the first drive signal (Vd1) to result in a second drive signal (Vd2) that is provided to the ultrasonic transducer 33.
The ultrasonic transducer 33 is immersed in a cleaning liquid and is responsive to the second drive signal (Vd2) to produce ultrasounds, the frequency of which corresponds to that of the second drive signal (Vd2). The amplitude of the second drive signal (Vd2) is normally within the range of 200-500 volts so as to be able to drive the ultrasonic transducer 33 to produce the ultrasounds.
The ultrasounds produced by the ultrasonic transducer 33 in the cleaning liquid result in ultrasonic vibrations that correspond in frequency to the ultrasounds. Due to the viscosity of the cleaning liquid, the ultrasonic vibrations generate microscopic cavitation bubbles in the cleaning liquid. When the microscopic cavitation bubbles break upon contact with surfaces of an article immersed in the cleaning liquid, the energy released thereby can clean debris from the surfaces of the immersed article.
However, since the ultrasonic transducer 33 is disposed in the cleaning liquid, if an electric leak is present in the ultrasonic transducer 33 due to degradation of or damage to the ultrasonic transducer 33, the user is exposed to the risk of being electrocuted when removing the cleaned article from the cleaning liquid. Moreover, when the ultrasonic transducer 33 is damaged, a large electric current can flow therethrough and can damage the output module 32. The prior art is devoid of any mechanism that can prevent the output module 32 from providing the second drive signal (Vd2) to the ultrasonic transducer 33 when an excessively large current flows through the ultrasonic transducer 33.
In addition, since the amplitude of the second drive signal (Vd2) should be within the range of 200-500 volts so as to be able to drive the ultrasonic transducer 33 to produce the ultrasounds, the output module 32 includes numerous power components to achieve the desired voltage range for the second drive signal (Vd2). Since the power components are likely to break down during use, there is also a need in the art to limit electric current supplied by the high voltage source module 34 to the output module 32 in the case of abnormal operating conditions.

Ultrasonic driving device with current limiting protection


Disclosed is a dyeing method using a laser beam. The method can dye transparent resins such as plastic lens well. Also disclosed is a dyeing apparatus. The dyeing method comprises heating a plastic lens having a dye-coated surface to fix the dye on the surface of the plastic lens. The method comprises the step of applying a laser beam with a wavelength, which is less likely to be absorbed in the dye but it absorbed in the plastic lens, onto the surface of the plastic lens through the dye.

As a method of dyeing a transparent resin body such as a plastic lens, there has been conventionally known a lens dyeing method achieved by dipping a lens in a dyeing solution for a predetermined time (a dip dyeing method). This method has been heretofore used but has disadvantages such as poor working environments and difficulty in dyeing a high refractive lens and a polycarbonate resin lens (Refractive index (power): 1.59). The polycarbonate resin lens is hard to break and assures high safety. Accordingly, this lens is widely used for spectacles lenses in U.S.A.
To dye the polycarbonate lens, the present inventors proposed a dyeing method achieved by applying (outputting) dyeing inks containing sublimable dyes to a base body such as paper by use of an inkjet printer, placing this base body without contact with a lens under vacuum, thereby ejecting the sublimable dyes toward the lens (hereinafter, referred to as a vapor deposition transfer dyeing method) (e.g., see Patent Literature 1). In this method, the lens is heated in an oven to fix the dye to a lens surface. The vapor deposition transfer dyeing method disclosed in Patent Literature 1 can dye a high refractive lens and a polycarbonate resin lens, which is more advantageous than the dip dyeing method.
On the other hand, there has been known a method of dyeing by previously applying sublimable dyes or inks containing the sublimable dyes to an object to be dyed and then irradiating a laser beam having a wavelength in a visible range to the object to be dyed (see Patent Literature 2).


An embodied step-up toroidal transformer (100). The step-up toroidal transformer (100) includes a plurality of coil segments (102, 104, 106, 108). Each primary coil segment (102, 104, 106, 108) is separately comprised of a plurality of turns of an elongated conductor coiled around a toroidal shaped core (120). The plurality of primary coil segments (102, 104, 106, 108) are collectively disposed around a circumference defined by the toroidal shaped core (120). Each of the plurality of primary coil segments (102, 104, 106, 108) is electrically connected in parallel across a first primary input terminal (128) and a second primary input terminal (130). The step-up toroidal transformer (100) also includes a secondary winding (126) formed from a plurality of turns of a second elongated conductor coiled around the toroidal shaped core (136).

1. Statement of the Technical Field
The inventive arrangements relate generally to transformers and more particularly to embedded toroidal transformers.
2. Description of the Related Art
Embedded toroidal transformers are known in the art. For example, U.S. Patent Application Publication No. 2005/0212642 to Pleskach discloses an embedded toroidal transformer in a ceramic substrate. The transformer includes a ceramic substrate comprised of a plurality of ceramic tape layers. At least a first one of the ceramic tape layers is layered between a plurality of second ceramic tape layers. The first ceramic tape layer can have a larger permeability value as compared to the second ceramic tape layers. In addition, one or more conductive coils are disposed within the plurality of ceramic tape layers. The conductive coil is of toroidal shape, having a central axis oriented transverse to the ceramic tape layers. Moreover, the conductive coil includes a plurality of turns about a region defining a ceramic toroidal core, wherein the ceramic toroidal core is intersected by the first ceramic tape layer.
Until now, only "step-down" and "one-to-one" toroidal transformers have been successfully embedded in a substrate. However, there are many applications where it is desirable to provide a "step-up" voltage response. In this regard, there have been various attempts at creating a functional step-up transformer. One problem with such embedded toroidal designs lies in that the magnetic flux induced by a primary input coil fails to effectively couple to the secondary output coils. This problem is largely due to the fact that induced magnetic flux in the secondary winding proves difficult to be constrained by metallic vias/traces. Therefore, what is needed is a novel embedded toroidal transformer design that can increase the voltage that is induced in a secondary winding. The novel design should achieve this by containing the magnetic flux that is formed in the secondary. At the same time, the step-up transformer design should not increase the x-y plane size of the toroidal footprint or require any additional machining or post processing steps.


An apparatus, includes a search unit which searches a critical signal path from a plurality of candidate signal paths connecting a first terminal and a second terminal, the critical signal path including the most strict delay limit in the plurality of candidate signal paths, and a display control unit which controls a display device for displaying an information regarding to a circuit element, the circuit element including the critical signal path.

1. Field of the Invention
The present invention relates to a floor plan editing apparatus for semiconductor integrated circuits.
2. Description of Related Art
In designing a layout of a semiconductor integrated circuit, a floor planning is performed. "Floor planning" refers to determination of a layout of main component parts, such as hierarchical modules, which are portions of a semiconductor integrated circuit, terminals of the hierarchical modules, hard macros and terminals of the hard macros dialogically, performed by a designer using a graphical interface (GUI) of a computer before determination of a layout of components (logic gate elements and sequential circuits) of the semiconductor integrated circuit. An apparatus for supporting such an operation may be referred to as a "floor plan editing apparatus".
When a designer lays out a semiconductor integrated circuit by using the floor plan editing apparatus, floor planning of the semiconductor integrated circuit may be performed in the floor plan editing apparatus.
In the process of the floor planning, the shapes of hierarchical modules, a disposition of the hierarchical modules and positions of terminals are determined so as to avoid a state where the number of wiring lines between the hierarchical modules is so large that wiring with respect to the hierarchical modules in a wiring step performed after the floor planning becomes impossible, and a state where a wiring distance is so large that a delay time in transmission of signals becomes excessively long. Also, a disposition of hard macros, positions of terminals of the hierarchical module and distances between the hard macros may be determined so as to avoid a state where the terminal of one of the hierarchical modules or a terminal of one of the hard macros becomes so close to a terminal, which is connected with the terminal of the hierarchical modules or the terminal of the hard macros, that wiring process becomes impossible due to congestion of wiring, and a state where the wiring distance is so large that an unnecessary space may be made.
The floor plan editing apparatus enables the designer to easily recognize visually, for example, connection relationships, the number of wiring lines and the wiring distances between the hierarchical modules and the hard macros. The floor plan editing apparatus displays data which includes terminals and wirings (paths) between the terminals. The floor plan editing apparatus generates the data on the basis of circuit connection information (net nest) representing, for example, connection relationships, the number of wiring lines and a wiring distance between the terminals of the hierarchical modules, between terminals of the hierarchical modules and the hard macros and between the terminals of hard macros. Paths of the display data are displayed as line segments such as straight lines. Such display data is called a "rat's nest" or "fly-lines". For example, display of the rat's nest is described in Non-Patent Document 1.
In many cases, the terminals of the semiconductor integrated circuit may be connected to each other via a plurality of logic gate elements and a plurality of sequential circuits disposed in paths, particularly in paths between the terminals of the hierarchical modules and the terminals of hard macros and between the terminals of hard macros.
In Patent Document 1, when one or more the logic gate elements or the sequential circuits are disposed in a path between two terminals, the rat's nest showing the two terminals, the path and the logic elements and the sequential circuits, is displayed.
A designer may consider a delay in transmission of signals between terminals via the path to examine suitable positions for arranging the hierarchical modules and the hard macros on a chip. For example, a designer may examine suitable positions at which the terminals of the hierarchical modules and the terminals of the hard macros are disposed on a chip after considering whether or not the delay between the terminals may be within one clock cycle. However, when the designer lays out a semiconductor integrated circuit by using the floor plan editing apparatus in the related art, the floor plan editing apparatus only displays the rat's nest. It is difficult to examine the suitable positions at which the terminals of the hierarchical modules and the terminals of the hard macros based on only the rat's nest. Therefore, there is a need for enabling examination of the suitable positions at which the terminals of the hierarchical modules and the hard macros are disposed on the chip.
Related arts will be described below.
Japanese Patent Laid-Open No. 2006-293701, as the above-mentioned Patent Document 1, discloses a net display program for displaying connections between components to be mounted on a substrate. With the net display program, the computer executes a process of recognizing a plurality of components designated in components displayed on a screen, another process of tracing, in a direction in which an electrical signal propagates or in a direction in which the electrical signal is propagated, a connection destination with respect to a signal line connected to a terminal of a first component which is optionally one of the designated components, and another process of connecting, by a connection line, the first component and a designated second component different from the first component if a terminal of the second component is included in the traced signal line, and displaying the connection line.
Japanese Patent Laid-Open No. 2006-301961 discloses an automatic floor planning method (Patent Document 2). According to the automatic floor planning method, in designing a hierarchical layout of a semiconductor integrated circuit constituted by one (or more) black box block having at least block boundary input and output information and having a shape and area set in advance, and one (or more) white box block having information on constituent elements in the block and connections of the constituent elements as well as block boundary input and output information, the shapes and areas of the blocks are determined on the basis of the results of flat disposition made by developing and disposing a hierarchical structure.
The automatic floor planning method includes making the flat disposition by setting a polygonal shape, a circular shape or an elliptic shape in the black box block as a core region of the black box block and by permitting, with respect to a region other than the core region, overlapping between the positions at which the internal constituent elements of the black box block and the hierarchy-developed white box block are disposed, checking an overlap between the positions at which the internal constituent elements of the black box block and the white box block are disposed, and changing the shape and area of the black box block according to the overlap, and sequentially repeating the above-mentioned steps until a set condition is satisfied.
Japanese Patent Laid-Open No. 11-213029 discloses a register transfer level logical description hardware performance evaluation apparatus (Patent Document 3). The register transfer level logical description hardware performance evaluation apparatus has a register transfer level logical description input thereto, and makes a predictive evaluation of LSI hardware performance. This apparatus is provided with block area estimation means for determining the size of each of the blocks and the relative positional relationships between the blocks on the basis of the logical description, path delay computation means for obtaining net delays on the basis of information on the relative positional relationships between the blocks by considering three-dimensional capacities, power consumption computation means for computing power consumption, and inter-system evaluation means for displaying tradeoffs in evaluation values by the above-described means with respect a plurality of register transfer level logical descriptions.
Japanese Patent Laid-Open No. 10-340291 discloses a method of making a logical simulation model (Patent Document 4). The method of making a logical simulation model includes logical combination means for extracting a logical block from verified logic circuit information and optimizing the logic of the logic block, and delay information preparation means for extracting timing information from the logic circuit information, and erasing redundant processing by determining at the time of preparing a model an element operation sequence on the basis of the connection relationships between combination circuits and sequential elements while considering an asynchronous loop, whereby high-speed simulation is made possible.
Japanese Patent Laid-Open No. 2003-223479 discloses a circuit designing apparatus (Patent Document 5). The circuit designing apparatus is provided with a logic designing unit which performs logic designing with respect to a circuit to be designed, a disposition unit which disposes cells on the basis of the results of logic designing performed by the logic designing unit, and a wiring unit which performs wiring between the cells disposed by the disposition unit. A path tracing unit performs path tracing from one or more tracing start pins with respect to the results of disposition by the disposition unit or the results of wiring by the wiring unit, and a delay value computation unit, when pass tracing is performed by the path tracing unit, computes the maximum or minimum of totalized delay values from the one or more tracing start pins to pins of the cells to be disposed, through which paths extend. A gate stage number computation unit, in a state where a unit delay value is assigned to all the cells to be designed and where 0 is assigned as a delay value to all nets between the cells, after logic designing by the logic designing unit, makes the delay value computation unit compute the maximum or minimum of the totalized delay values while path tracing is being performed by the path tracing unit with respect to the results of logic designing performed by the logic designing unit. The gate stage number computation unit also computes the numbers of gate stages between sequential circuit cells or between input and output pins and the sequential circuit cells in the circuit to be designed on the basis of the maximum or minimum of the total delay values.
Japanese Patent Laid-Open No. 2005-228124 discloses a method of generating hierarchical blocks in a semiconductor integrated circuit design (Patent Document 6). In the method of generating hierarchical blocks in a semiconductor integrated circuit design, a plurality of hierarchical blocks are generated using a computer from circuit information in which logical hierarchy information about a semiconductor integrated circuit is held. This hierarchical block generating method includes a circuit structure extraction step of inputting circuit information in which logical hierarchy information about the semiconductor integrated circuit is held, and extracting a circuit structure from the input circuit information with respect to logical hierarchical layers in the semiconductor integrated circuit. Also included is a hierarchical block generation step of generating a plurality of hierarchical blocks by combining the logical hierarchical layers on the basis of the circuit structure of the logical hierarchical layers and outputting the structure of the generated hierarchical blocks.    [Non-Patent Document 1] "Blast Plan Pro" published from Magma Design Automation, Co., Ltd., catalog page 2, [online], 2005, [by search on Jun. 25, 2007], Internet <URL:http://www.magma-da.co.jp/product/image_pr/PDF/PanPro200506.pdf>    [Patent Document 1] Japanese Patent Laid-Open No. 2006-293701    [Patent Document 2] Japanese Patent Laid-Open No. 2006-301961    [Patent Document 3] Japanese Patent Laid-Open No. 11-213029    [Patent Document 4] Japanese Patent Laid-Open No. 10-340291    [Patent Document 5] Japanese Patent Laid-Open No. 2003-223479    [Patent Document 6] Japanese Patent Laid-Open No. 2005-228124

Apparatus and method for circuit layout using longest path and shortest path search elements


A video editing project includes multiple assets, such as animated three-dimensional geometries and streaming video clips. Assets are rendered during associated timespans in a timeline. Video clips are streamed from sources while the project is rendered, rather than in advance. Rendered video data is played in real-time during rendering. Rendering the project may further involve rendering assets in a three-dimensional space. Streaming video clip(s) may be mapped to a geometry. Effects or transformations may be applied the video clip(s) in real-time during rendering and playback. Non-destructive, non-linear editing techniques are described—edits are specified for assets without changing the assets at their sources or having to download and modify a working copy. The editor may support live editing of the project during the real-time playback. The video editor may be, for example, a web browser-based application requiring no direct software installation by the user, and streaming media from remote servers.

The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
With the proliferation of smart phones, digital cameras, and other portable devices capable of capturing images and video, an ever-increasing amount of digital media data is being captured each year. Due to the limited storage capacities of portable devices, much of this media data is either quickly discarded or uploaded to cloud-based servers in largely unedited forms that are not ideal for sharing with others. Many cloud-based video services offer server-based editing tools for video uploaded to their systems, though these services are typically quite limited and require extensive computing resources such as large video rendering farms on the part of the video service provider.
Some consumers store their media data on personal storage servers. Utilizing high-power personal computing systems, such consumers may even edit their media data using any of a number of non-linear video editing software applications. However, many consumers find the process of editing their video data locally to be cumbersome, or lack a suitably-powered system for editing their media data, particularly if that media data is in a higher definition format.
Meanwhile, for power users who wish to create highly-customized media projects, most video editing software applications are limited to a small, canned set of special effects and animations. Those capable of higher-levels of customization are often difficult to use and limited to supporting locally stored media in only a handful of formats. Such tools may also require long rendering times to visualize effects, or large rendering farms to output video in a manageable amount of time.
Moreover, many video editing software applications lack the ability to easily share and reuse media data in the cloud. For instance, if a user wishes to create and share a video that includes clips from an Internet-based media stream, the media stream must typically be downloaded, processed, and re-encoded, which greatly increases the resources necessary to create and share the video.

Real-time playback of an edited sequence of remote media and three-dimensional assets


In accordance with the present invention, repeated patterns are produced beforehand without dividing patterns included in design pattern data. The repeated pattern data are used to produce a mask for partial full electron beam exposure. This insures a resist pattern free from connection errors on the boundaries between the repeated pattern areas. The invention therefore obviates connection errors of about 0.02 .mu.m to 0.03 .mu.m heretofore occurring at each time of a partial simultaneous electron beam shot, and thereby enhances the dimensional accuracy of a resist pattern produced by electron beam exposure.

The present invention relates to a mask data generating method and a mask for an electron beam exposure system, particularly an electron beam exposure system of the type exposing a plurality of desired patterns collectively in a large scale memory or similar semiconductor integrated circuit (IC).
Today, even patterns as fine as 0.2 .mu.m to 0.3 .mu.m or so are applied to semiconductor IC quantity production lines. In parallel with the decreasing pattern size, not only photolithography using ultraviolet rays and X-ray lithography using X-rays but also electron beam lithography using an electron beam are attracting increasing attention. However, a known electron beam exposure system has a problem that the throughput is far lower than the throughput available with an optical aligner using a stepper, as taught in "High Throughput Electron Beam Lithography System", Hitachi Review, Vol. 76, No. 7 (1994-7). A simultaneous electron beam exposing method is capable of improving the minimum fabricating dimensions and enhancing the throughput. This kind of exposing method uses a mask for an electron beam exposure system is formed with a desired pattern beforehand. The mask promotes efficient exposure especially when a number of identical patterns are sequentially exposed like the memory cells of a large scale memory.
It is a common practice with the simultaneous electron beam exposing method to produce a mask formed with a desired pattern in the from of an aperture. The mask is located in the vicinity of the optical axis of an electron beam. An electron beam is radiated via the aperture in order to transfer the desired pattern to a silicon (Si) wafer. To increase the throughput of an exposure system, it has been customary to determine the size of the aperture on the basis of, among various repeated pattern areas included in design data, the size of a repeated pattern area closest to the maximum shot or radiation area.
Japanese Patent Laid-Open Publication No. 5-343304, for example, discloses a method of extracting out of design data a repeated pattern having the maximum size applicable to a partial simultaneous electron beam exposure system. This method implements efficient extraction by executing the extraction with consecutive mask patterns in parallel. However, the problem is that a repeated pattern closest in size to the largest area which a partial simultaneous electron beam exposure system can shoot is simply extracted. Specifically, assume that this method is applied to, e.g., a device separation pattern or a capacity pattern of a DRAM (Dynamic Random Access Memory). Then, even when the desired pattern is smaller in size than the maximum shot, patterns extending over the boundary between nearby shots is divided. By the division, a mask pattern for the exposure system is extracted. Assume that the above mask pattern is used to produce a mask for the exposure system and then effect partial simultaneous electron beam exposure. Then, connection errors occur at each time of exposure, due to the deviations of the patterns divided on the boundaries of the repeated pattern areas. Consequently, resist patterns transferred from the mask to the wafer are low in dimensional accuracy. Moreover, because the matching of the repeated patterns must be taken into consideration, the mask pattern extracting procedure is complicated.
There is an increasing demand for dimensional accuracy of less than .+-.0.02 .mu.m for a designed pattern dimension of 0.2 .mu.m in order to implement high integration and fine configuration of devices. It is therefore necessary to reduce the deterioration of dimensional accuracy ascribable to the connection errors discussed above.
Technologies relating to the present invention are also disclosed in. e.g., Japanese Patent Laid-Open Publication No. 5-136036.

Mask data generating method and mask for an electron beam exposure system


A system and method for processing applications for loans secured by real estate, wherein an applicant is prompted for one or more parameters of a requested loan and for data regarding the applicant, data regarding the applicant's credit is accessed based on data provided by the applicant, predetermined rules are applied to the received data, it is automatically determined whether to approve the loan based on the results of the application of the predetermined rules to the received data, if the loan is approved, one or more terms of the loan are automatically determined based on the results of the application of the predetermined rules to the received data, and the applicant is informed whether the loan was approved and one or more terms of the loan, if approved.

The application process for secured loans has traditionally been a protracted and inefficient process. The applicant would meet with a salesman who would provisionally offer a loan to the applicant, without knowing whether the loan would meet the lender's underwriting standards. If the applicant decided to accept the loan, the salesman would then request that the applicant complete an application and submit certain documents, such as an appraisal of any collateral to be offered as security. The salesman would then route all of the paperwork to the lender's processing department, where additional documents, such as credit reports, might be requested. Eventually, the documents would be forwarded to an underwriter, who would then determine whether the requested loan met the lender's underwriting standards and if any further documentation was necessary. If the loan did not meet the lender's underwriting standards, the underwriter and the salesman might negotiate the changes to the terms of the loan that would be necessary to meet these standards. After the underwriter and the salesman agreed on terms, it would be necessary for the salesman and the applicant to negotiate with respect to the terms agreed on by the underwriter and the salesman. Any changes agreed to by the applicant and the salesman might require further negotiations between the salesman and the underwriter, et cetera.
This process was inefficient from both the applicant's point of view and the lender's point of view. For the applicant, the protracted nature of the process both delayed the applicant's receipt of the loan proceeds and complicated efforts to compare the terms offered by multiple lenders. For the lender, the involvement of multiple employees with a single loan application dramatically increased the number of man hours necessary to complete a loan, thereby decreasing the lender's profit margins. Moreover, the lack of knowledge of the salesman of the lender's underwriting standards tended to result in the salesman's offer of terms unacceptable to the lender, resulting in further delays.
It is therefore an object of the present invention to provide a system and method for automating the process of processing a loan application so as to decrease the costs incurred by a lender in processing a loan application.
It is a further object of the present invention to provide a system and method for automatically determining whether proposed loan terms meet a lender's underwriting standards.

System and method for automatically processing loan applications


An insulating substrate to which intermediate portions or conductive pastes constituting the intermediate portions are disposed, a front surface protective member to which front surface patterns are formed, and a back surface protective member to which back surface patterns are formed are prepared. A laminated body, to which first end portions or conductive pastes constituting the first end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the front surface patterns, and second end portions or conductive pastes constituting the second end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the back surface patterns, is constituted. Then, thermoelectric conversion elements are formed by integrating the laminated body.

Conventionally, a thermoelectric converter that has a plurality of thermoelectric conversion elements disposed between first and the second substrates disposed facing each other, and the plurality of thermoelectric conversion elements are connected with a front surface pattern formed on the first substrate and a back surface pattern formed on the second substrate has been proposed in a Patent Document 1, for example.
Specifically, among sectional areas of the thermoelectric conversion elements in the thermoelectric converter in a plane parallel to planes of the first and the second substrates, a sectional area of an end portion connected to the back surface pattern is configured to be larger than an area of an end portion connected to the front surface pattern and an area of an intermediate portion connecting the respective end portions.
According to this, effects of a thermoelectric conversion occurring at an interface between the back surface pattern and the thermoelectric conversion element can be increased as compared with a case where the thermoelectric conversion element is fixed to the sectional area of the intermediate portion. Further, a thermal resistance of the thermoelectric conversion element is suppressed from being reduced as compared with a case where the thermoelectric conversion element is fixed to the sectional area of the end portion of the back surface pattern side, and the temperature difference between the first and the second substrates can be suppressed from being reduced.
Such a thermoelectric converter is manufactured as follows. First, a thermoelectric conductor block is disposed on the second substrate to which the back surface pattern is formed. Thereafter, a plurality of thermoelectric conversion elements are formed by separating the thermoelectric conductor block from the second substrate side and an opposite side by using a dicing cutter or the like. At this time, a tapered cutter of which a width of a cutting portion is continuously narrowed from both sides toward a distal end is used as the dicing cutter. Thereby, when cutting the thermoelectric conductor block, the thermoelectric conversion element of which the sectional area of the end portion of the back surface pattern side is larger than the sectional area of the end portion of the front surface pattern side and the sectional area the intermediate portion side can be formed. Then, by disposing the first substrate to which the front surface pattern is formed on the opposite side of the second substrate to sandwich each thermoelectric conversion element, the thermoelectric converter is manufactured.

Manufacturing method of thermoelectric converter


The invention encompasses isoindoline compounds, pharmaceutical compositions comprising them, and methods of their use for the treatment, prevention or management of various diseases and disorders. Examples include, but are not limited to, cancer, inflammatory bowel disease and myelodysplastic syndrome.

Isoindoline derivatives are reportedly useful in the treatment, prevention and management of various disorders or diseases. For example, U.S. Pat. No. 6,667,316, which is incorporated herein in its entirety by reference, discloses a genus of compounds that decrease the levels of Tumor Necrosis Factor alpha (TNF-α) and inhibit phosphodiesterases (PDEs). However, a continuing need exists for compounds effective in treating, preventing and/or managing various disorders and diseases mediated by TNF-α and PDEs.

Isoindoline compounds and methods of making and using the same


A drywall corner piece with flange surfaces forming a near right angle forming a cup for fitting over drywall corners where the web sections of the flanges have at least one strain relief channel allowing the piece to flex to different angles.

1. Field of the Invention
The present invention relates generally to the field of drywall trim and corners and more particularly to expandable drywall 3-way and 2-way outside and inside corner pieces.
2. Description of the Prior Art
Drywall corners are used to finish drywall seams both for interior and exterior use. A particular problem with finishing outside corners is the end termination. Prior art endcaps are closed and will not expand to fit arbitrary corners. A similar situation holds for interior corners.
What is badly needed is a drywall corner or cap that contains strain relief channels so that it can expand and snap fit over a drywall outside corner.


An organopolysiloxane composition for bonding to magnesium alloys comprises (A) 100 parts by weight of an organopolysiloxane of the following general formula (1) and/or (2)

This invention relates to an organopolysiloxane composition for bonding to magnesium alloys which is cured at room temperature into a cured product having an excellent bonding property to magnesium alloys.
In recent years, magnesium alloys, typically AZ-31, AZ-91 and the like, have distinct features of lightweight and high strength, a good corrosion resistance, good designing properties and good recycling properties, and have been frequently used in information electronic devices such as mobile phones, digital video recorders, digital cameras, liquid crystal projectors, plasma displays, personal computers, MD players, DVD recorders and the like, and also in transport machine parts such as electric components, vehicle oil pans, intake manifolds, lock housing parts, steering upper brackets, steering wheels and the like. Organopolysiloxane compositions for bonding to magnesium alloys exhibiting good self-adhesiveness to these members are now needed.
However, magnesium alloys are adherends which are difficult to bond. Eventually, chemical conversion treatment is essential for bonding. Sealing members or adhesives exhibiting good self-adhesiveness without the conversion treatment have been never studied. More particularly, only several types of organopolysiloxane compositions having self-adhesiveness to magnesium alloys have been proposed up to now. JP-A 2003-535152 discloses a composition comprising a curable silicone and an amino group-containing silane adhesion promoter serving as a filler. JP-A 2002-309219 has proposed a composition comprising a silicone oil and a curing agent composed of an inorganic compound containing a metal element whose tendency of ionization is smaller than that of magnesium. However, the former composition is not satisfactory with respect to the effectiveness of the amino group-containing silane adhesion promoters such as γ-aminopropyltrialkoxysilane, trialkoxypropylethylenediamine and the like. With the latter, limitation is placed on the type of filler used, thus lacking in the freedom for material designing.

Organopolysiloxane composition for bonding to magnesium alloy

Abstract: wherein R may be the same or different and represents a substituted or unsubstituted monovalent hydrocarbon group having 1 to 10 carbon atoms, and n is an integer of at least 10, X represents an oxygen atom or an alkylene group having 2 to 5 carbon atoms, and m independently represents an integer of 0 or 1, (B) 0.1 to 50 parts by weight of an organosilicon compound having at least three hydrolyzable groups bonded to silicon atoms in one molecule and/or a partial hydrolyzate thereof, and (C) 0.1 to 15 parts by weight of an acidic silane coupling agent.