A method in which incoming RF signals to a given node of a wireless network are detected in real-time by using a comparison circuit for comparing a signal which is indicative of the strength of an incoming RF signal with a prescribed threshold level. The output of the comparison circuit is coupled to an input of the digital signal processor (e.g., microprocessor) of the node. The microprocessor is preferably programmed to check this input prior to attempting to transmit data thus minimizing the chances of a collision occuring due to overlapping data transmitting and receiving operations. Preferably, the prescribed threshold level utilized in the comparison circuit of a given node can be selectively varied in order to thereby selectively vary the size of the cell in which the given node resides. In this connection, the neighborhood or cell sizes in which the individual nodes in the network reside are preferably adaptively varied in such a manner as to maximize the data throughput of the entire network. Also disclosed is an individual network node for a wireless network and a wireless network which have the capability of implementing the above-described method.

The present invention relates generally to wireless local area networks (W-LANs), and more particularly, to a real-time carrier sense multiple access (CSMA) method having the capability to adaptively vary cell sizes and a wireless network for implementing the same.
A network which consists of a plurality of network or individual nodes which communicate with each other and with a network control node (also referred to as a xe2x80x9cmainxe2x80x9d or xe2x80x9ccentralxe2x80x9d node) via wireless (radio or RF) links is generally referred to as a wireless (radio or RF) network. In wireless, multihop networks, each node includes a node controller which includes a digital signal processing device (e.g., a microprocessor) and an RF transceiver. Data is communicated (transferred) between the individual nodes and the control node by a technique known as xe2x80x9choppingxe2x80x9d, in which individual units of data are transferred from the control node to a destination node and from an origin (source/sender) node to the control node by being hopped (relayed or retransmitted/rebroadcast) by one or more intermediate nodes in accordance with a network routing protocol, in all instances in which the destination or origin node does not have a direct communication link with the control node. Each of the nodes which hops or relays a packet to one or more other nodes in the network is commonly referred to as a xe2x80x9crepeater nodexe2x80x9d. or simply. xe2x80x9crepeaterxe2x80x9d. The destination node generally acknowledges receipt of a data packet from the control node by returning an acknowledgement data packet to the control node via one or more repeaters in a similar fashion.
Various logical units of data can be utilized, including packets, frames, or cells. However, for convenience of illustration of a presently preferred embodiment of the present invention, the units of data employed will be xe2x80x9cpacketsxe2x80x9d typically ranging in size from about 5-1000 bytes. In this regard, the term xe2x80x9cpacketsxe2x80x9d as used herein is intended to encompass all logical units of data, including frames or cells. Generally, packet-hopping data communications are carried out under the control of the control node, which is typically a computer on which resides the data communications control software. The packet-hopping data transfer scheme enables a reduction in the cost of the RF transceivers and compliance with FCC Part 15 requirements.
Such wireless, packet-hopping networks are particularly suitable for controlling one or more functions or systems of a building, e.g.. the lighting, HVAC, and/or security systems of the building, because a wireless network offers a low-cost, indoor communication infrastructure that does not require new lines to be added to the existing structure in order to carry the network information. Further, such networks can support additional systems installed in the building, such as paging and personal communications systems (PCSs).
The control node of such building control networks is typically a building computer. The individual nodes and the building computer run different software programs which are complementary, and which together constitute the system control software. The individual nodes are typically distributed throughout the building to monitor the status/value of prescribed parameters of the building system being controlled, and to produce control signals in response to commands issued by the building computer to adjust the prescribed parameters as required. It is important that the building computer be able to send and receive data to and from each node in the network in order to properly monitor the status/value of the prescribed parameters, and to issue commands to adjust the status/value of the prescribed parameters as required, in accordance with the system control software.
An exemplary building control network is an automatic or intelligent lighting control system which monitors lighting levels, occupancy status, energy consumption as a function of time, and/or other lighting parameters of each room and/or area of the building, within the network, i.e., each room and/or area of the building which is equipped with a lighting module(s) linked to a node controller (also referred to as a xe2x80x9cwall unitxe2x80x9d) which includes an RF transceiver, a digital signal processing device (e.g., microcontroller or microprocessor), and control circuitry to signal the lights to change brightness levels. Each lighting module and its associated node controller together constitute a node in the network which is under the control/management of the building computer.
In such an intelligent lighting, control system, each of the lighting modules is preferably individually programmable (e.g., by building occupants), via its associated wall unit, to provide direct control of the setting of the dimming, ballast thereof, and thus, direct control of the lighting level of the lamp(s) thereof. In this regard, each of the nodes includes one or more sensors (e.g., occupancy status, daylight (ambient lighting), and dimming/lighting level sensors) which provide sensor feedback data to the digital signal processing device (e.g., a microprocessor) of the node controller, which is programmed to analyze (process) the sensor feedback data and to generate control signals for adjusting the lighting level of the monitored lamp(s) associated therewith, as required, to achieve the programmed local lighting conditions.
The sensor feedback data is also transmitted by each node in the network to the building computer, when requested by the building computer to do so, or when the local lighting conditions change. The building computer analyzes (processes) the sensor feedback data in accordance with lighting system control software loaded therein, and sends control data (commands) to the individual nodes, as required, in order to adjust the lighting levels of the monitored rooms/areas of the building in accordance with the lighting system control software, e.g., to optimize the energy efficiency of the lighting system, and thereby override the programmed lighting levels provided by the individual lighting modules. Thus, in addition to being individually programmable and being capable of independent operation, the distributed modules are functionally integrated into a single building-wide network under the control of the building computer.
Data communications in such networks are generally between the building computer and the individual nodes, and vice versa, over a common communications channel (i.e., a shared channel). In order to minimize simultaneous transmissions of packets over the common network channel, a channel access protocol is utilized. The most common channel access protocol is the carrier sense multiple access (CSMA) protocol, according to which each node, prior to transmitting a packet, waits for a random delay period, and then senses the channel to determine whether it is available (xe2x80x9cclearxe2x80x9d) or unavailable (xe2x80x9cbusyxe2x80x9d). If the channel is sensed to be clear it transmits the packet, and if the channel is sensed to be busy, it waits for another random delay period before sensing the status of the channel again before making a further attempt to transmit the packet.
The microcontroller or microprocessor used in the nodes of wireless networks such as the ones described above to typically have a serial interface which is addressed one byte at a time (i.e., in a byte-wise manner) by the processor itself. Thus, the processor can detect an incoming signal only after an entire byte has been received. As such, true real-time detection of incoming signals is not possible. There will always be a one-byte delay between the time that an incoming signal is received and the time that the incoming signal is detected.
Generally, once the first byte of information has been received, a bit flag is set informing the processor that data is incoming (i.e., is being received). In a topical network operating at 9600 baud, bytes are clocked in at 1 ms intervals, so that a processor having a clock rate of 2 MHz may perform as many as 500 instructions in the 1 ms interval between the time that an incoming signal is received and the time that the incoming signal is detected. If any one of these instructions invokes the transmitter of the RF transceiver of the node to begin transmitting data during, this 1 ms interval, a conflict or collision will occur between the data being transmitted and the data being, received, whether or not the incoming data is intended for the node. Such collisions obviously degrade the data throughput of the network, and thus, constitute a significant drawback of presently available wireless networks.
The term xe2x80x9cneighborhoodxe2x80x9d or xe2x80x9ccellxe2x80x9d as used herein shall mean the domain which encompasses a given node and all other nodes from which the given node can receive an RF signal having sufficient strength to require the given node to wait for completion of receipt of the RF signal, prior to initiating its own data transmissions, e.g., in accordance with a CSMA protocol. In the presently available wireless networks, the individual nodes in the network are each configured at the time of network installation and initialization to operate within a predefined cell size. Obviously, if the cell size is made too small, the the node can become isolated from the rest of the network, whereas if the cell size is made too large, the data throughput of the network can be significantly degraded by forcing the node to wait even when it could communicate without causing a collision to occur. Thus, the presently available wireless networks lack the capability to actively or dynamically control cell sizes in the network, e.g., under system software control, which constitutes a significant shortcoming of the presently available wireless networks.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a real-time carrier sense multiple access (CSMA) method having the capability to adaptively vary cell sizes, and a wireless network for implementing the same. The present invention fulfills this need in the art.
The present invention encompasses method in which incoming RF signals to a given node of a wireless network are detected in real-time by using a comparison circuit for comparing a signal which is indicative of the strength of an incoming RF signal with a prescribed threshold level. The output of the comparison circuit is coupled to an input of the digital signal processor (e.g., microprocessor) of the node. The microprocessor is preferably programmed to check this input prior to attempting to transmit data, thus minimizing the chances of a collision occuring due to overlapping data transmitting and receiving operations. In the presently preferred embodiment of the present invention, the output of the comparison circuit is applied to both an interrupt enable pin and an RF channel status sensing input pin of the microprocessor, whereby the microprocessor is programmed to invoke a random delay prior to transmitting or re-transmitting data (in accordance with a CSMA protocol), in response to a logic high level output of the comparison circuit.
In accordance with another aspect of the present invention, the prescribed threshold level utilized in the comparison circuit of a given node is selectively varied in order to thereby selectively vary the size of the cell in which the given node resides. Preferably, the threshold level is automatically controlled in accordance with a prescribed algorithm via network commands issued by the network control node (e.g., building computer) of the network and/or in accordance with a software program which resides in each node. In this connection, the neighborhood or cell sizes in which the individual nodes in the network reside are preferably adaptively varied in such a manner as to maximize the data throughput of the network.
The present invention also encompasses an individual network node for a wireless network and a wireless network which have the capability of implementing the above-described method of the present invention.

Real-time CSMA method having the capability to adaptively vary cell sizes and a wireless network for implementing the same


A cable system is disclosed including a central cable; an inner membrane having a higher minimum bend radius than the central cable and surrounding the cable, thereby forming an inner chamber around the central cable, the inner chamber containing a gas or at least one chemical; and an outer membrane surrounding the inner membrane and forming an outer chamber around the inner chamber, the outer chamber comprising a gas or at least one chemical. When the minimum bend radius of the inner membrane is exceeded, the inner membrane fractures or breaks, and the gas or at least one chemical from the inner chamber enters the outer chamber to create a chemiluminescence reaction, color, or smell.

The present invention relates to a cable system and to methods for preventing undue or unwanted bending of a cable.
Modern high bandwidth networking cables, for example fiber-optic cables, have strict limitations on their so-called bend radius. For example, with reference to FIG. 1, a minimum bend radius 100 for an unshielded cable may be about 8 times the cable diameter and a minimum bend radius of a shielded cable may be about 12 times the cable diameter. The minimum bend radius is the radius beyond which a cable should not be bent without risking damage to the integrity of the cable. The minimum bend radius sometimes appears in fine print on the outside of a cable. However, these cables are thicker than ever, and more and more cables are being stuffed into a fixed amount of space around data center racks, in the plenum, or on raised cable guides. Thus, it is inevitable that installers will sometimes try to over-bend the cables and, in the process, compromise the quality or even destroy the cables.
There is therefore a need for cables with strict bend width limitations and methods whereby installers are clearly notified as soon as they attempt to over-bend cables.

System for preventing undue bending of cables

International Business Machines Corporation


A process and apparatus for the recovery of ethane, ethylene, propane, propylene, and heavier hydrocarbons from a liquefied natural gas (LNG) stream is disclosed. The LNG feed stream is divided into two portions. The first portion is supplied to a fractionation column at an upper mid-column feed point. The second portion is directed in heat exchange relation with a warmer distillation stream rising from the fractionation stages of the column, whereby this portion of the LNG feed stream is partially heated and the distillation stream is totally condensed. The condensed distillation stream is divided into a “lean” LNG product stream and a reflux stream, whereupon the reflux stream is supplied to the column at a top column feed position. The partially heated portion of the LNG feed stream is heated further to partially or totally vaporize it and thereafter supplied to the column at a lower mid-column feed position. The quantities and temperatures of the feeds to the column are effective to maintain the column overhead temperature at a temperature whereby the major portion of the desired components is recovered in the bottom liquid product from the column.

This invention relates to a process for the separation of ethane and heavier hydrocarbons or propane and heavier hydrocarbons from liquefied natural gas, hereinafter referred to as LNG, to provide a volatile methane-rich lean LNG stream and a less volatile natural gas liquids (NGL) or liquefied petroleum gas (LPG) stream. The applicants claim the benefits under Title 35, United States Code, Section 119(e) of prior U.S. Provisional Application Nos. 60/584,668 which was filed on Jul. 1, 2004, 60/646,903 which was filed on Jan. 24, 2005, Ser. No. 60/669,642 which was filed on Apr. 8, 2005, and Ser. No. 60/671,930 which was filed on Apr. 15, 2005.
As an alternative to transportation in pipelines, natural gas at remote locations is sometimes liquefied and transported in special LNG tankers to appropriate LNG receiving and storage terminals. The LNG can then be re-vaporized and used as a gaseous fuel in the same fashion as natural gas. Although LNG usually has a major proportion of methane, i.e., methane comprises at least 50 mole percent of the LNG, it also contains relatively lesser amounts of heavier hydrocarbons such as ethane, propane, butanes, and the like, as well as nitrogen. It is often necessary to separate some or all of the heavier hydrocarbons from the methane in the LNG so that the gaseous fuel resulting from vaporizing the LNG conforms to pipeline specifications for heating value. In addition, it is often also desirable to separate the heavier hydrocarbons from the methane because these hydrocarbons have a higher value as liquid products (for use as petrochemical feedstocks, as an example) than their value as fuel.
Although there are many processes which may be used to separate ethane and heavier hydrocarbons from LNG, these processes often must compromise between high recovery, low utility costs, and process simplicity (and hence low capital investment). U.S. Pat. Nos. 2,952,984; 3,837,172; and 5,114,451 and co-pending application Ser. No. 10/675,785 describe relevant LNG processes capable of ethane or propane recovery while producing the lean LNG as a vapor stream that is thereafter compressed to delivery pressure to enter a gas distribution network. However, lower utility costs may be possible if the lean LNG is instead produced as a liquid stream that can be pumped (rather than compressed) to the delivery pressure of the gas distribution network, with the lean LNG subsequently vaporized using a low level source of external heat or other means. U.S. Patent Application Publication No. US 2003/0158458 A1 describes such a process.
The present invention is generally concerned with the recovery of ethylene, ethane, propylene, propane, and heavier hydrocarbons from such LNG streams. It uses a novel process arrangement to allow high ethane or high propane recovery while keeping the processing equipment simple and the capital investment low. Further, the present invention offers a reduction in the utilities (power and heat) required to process the LNG to give lower operating cost than the prior art processes. A typical analysis of an LNG stream to be processed in accordance with this invention would be, in approximate mole percent, 86.7% methane, 8.9% ethane and other C2 components, 2.9% propane and other C3 components, and 1.0% butanes plus, with the balance made up of nitrogen.
In the following explanation of the above figures, tables are provided summarizing flow rates calculated for representative process conditions. In the tables appearing herein, the values for flow rates (in moles per hour) have been rounded to the nearest whole number for convenience. The total stream rates shown in the tables include all non-hydrocarbon components and hence are generally larger than the sum of the stream flow rates for the hydrocarbon components. Temperatures indicated are approximate values rounded to the nearest degree. It should also be noted that the process design calculations performed for the purpose of comparing the processes depicted in the figures are based on the assumption of no heat leak from (or to) the surroundings to (or from) the process. The quality of commercially available insulating materials makes this a very reasonable assumption and one that is typically made by those skilled in the art.
For convenience, process parameters are reported in both the traditional British units and in the units of the Système International d'Unités (SI). The molar flow rates given in the tables may be interpreted as either pound moles per hour or kilogram moles per hour. The energy consumptions reported as horsepower (HP) and/or thousand British Thermal Units per hour (MBTU/Hr) correspond to the stated molar flow rates in pound moles per hour. The energy consumptions reported as kilowatts (kW) correspond to the stated molar flow rates in kilogram moles per hour.


This invention provides a method for controlling soilborne fungal disease in cultivated field plants such as a peanut crop. Field crop soil is treated with a free-flowing granular fungicide composition which can be applied by aerial means with minimal settling on plant foliage. The granular fungicide composition comprises ammonium bicarbonate and a solid surfactant ingredient, and is effective against soilborne fungi such as a Sclerotinia, Rhizoctonia, Pythium, Fusarium, Phytophthora or Verticillium species.

The control of phytopathogenic fungi is of great economic importance since fungal growth on plants or on parts of plants inhibits production of root, stem, foliage, fruit or seed, and the overall quality of a cultivated crop. About 25 percent of all fungal diseases in agriculture and horticulture are caused by powdery mildew phytopathogens.
Because of the vast economic ramifications of fungal propagation in agricultural and horticultural cultivations, a broad spectrum of fungicidal and fungistatic products have been developed for general and specific applications.
Of background interest with respect to the present invention embodiments are fungicide compositions which contain an inorganic bicarbonate and an optional carbonate compound. It is known that bicarbonate and carbonate compounds exhibit fungicidal properties for agricultural purposes.
Phytopathology, 48, 169 (1931) by R. H. Marloth describes studies involving the physiology of fungi. The reference reports studies which demonstrate that sodium and potassium bicarbonate and carbonate salts are toxic to fungi such as Penicillium italicum and Penicillium digitatum.
U.S. Pat. No. 1,560,558 discloses the use of salts such as lithium carbonate, sodium carbonate, sodium bicarbonate, potassium bicarbonate, potassium carbonate and ammonium bicarbonate as fungicide ingredients.
U.S. Pat. No. 4,599,233 describes a fungicide composition which consists of sodium bicarbonate in combination with a surface active food emulsifier such as sorbitan monostearate.
Japanese patent 53118523 describes the combination of sodium bicarbonate and lecithin as an active agent for the control of agricultural and fruit storage fungus diseases.
Japanese patent 56043207 describes a biocidal composition containing sodium bicarbonate and a polyglycerol fatty acid ester. The biocide controls Penicillium digitatum on oranges, Sphaerotheca fuligenea on cucumbers, Piricularia oryzae on rice, and mosaic virus on tomatoes.
Japanese patent 60097909 describes a soil fungicide prepared by admixing slaked lime with sodium bicarbonate, potassium bicarbonate, boric acid and phenolphthalein.
German patent DE 2927994 describes a fungicide which consists of sodium bicarbonate incorporated into a food-compatible surfactant such as saccharose laurate.
Japanese patent 57062208 describes horticultural fungicides in which the addition of sodium bicarbonate to polyoxin or thiophanatemethyl increases the fungicidal activity of the organic biocide against Botrytis cinerea on cucumbers.
Japanese patent 58023609 describes an agricultural fungicide composed of a mixture of sodium bicarbonate or potassium bicarbonate with cupric hydroxide, basic copper carbonate or basic copper sulfate. The combination of ingredients exhibits a synergistic fungicidal effect against cucumber early blight, tomato wilt, rice sheath blight, rice blast and citrus canker.
Of particular interest with respect to the present invention is the control of soilborne phytopathogenic fungi. Soilborne diseases are of significant economic importance to peanut industries in Oklahoma and other areas of the United States. These diseases include Sclerotinia blight (Sclerotinia minor Jagger), southern blight (Schlerotium rolfsii sacc.) and pod rot (Pythium myriotylum and Rhizoctonia solani Kuehn).
Fungicides are the common means of soilborne disease management in peanut crops. Because of increasing environmental and health related concerns, the use of organic pesticides is becoming increasingly tenuous, and there is substantial incentive to investigate the development of new fungicide products.
Ammonium bicarbonate has been applied by chemical spray application equipment to peanut field crops for control of Sclerotinia blight. Under the application conditions, the ammonium bicarbonate was phytotoxic, as evidenced by a reduction in peanut yield Peanut Science, 17, 28 (1990)!.
There is a continuing need for improved methods for providing preventive and curative fungicidal activity for the protection of cultivated plants with a minimum of phytotoxic side effects.
Accordingly, it is an object of this invention to provide a fungicide composition which can be applied effectively to cultivated plants, and which is within acceptable limits with respect to environmental and health concerns.
It is another object of this invention to provide a method of controlling fungi in cultivated field crops with a minimum of phytotoxic side effects.
It is a further object of this invention to provide a method for controlling soilborne Sclerotinia blight and other diseases in peanut crops by means of an ecologically safe inorganic fungicide with an acceptable degree of phytotoxic side effects.
Other objects and advantages of the present invention shall become apparent from the accompanying description and examples.

Control of soilborne fungi in cultivated crops


A method for supporting low-level aircraft flights in which a warning is provided for the pilot upon a reliable recognition of wire-like obstacles, even during extreme environmental influences, such as clutter, or even when such obstacles are seen against the sky. The method is performed upon the collection of information on the topography of the surrounding terrain by at least one sensor located on the aircraft, such information representing raw data, based upon which an image-like representation is calculated, such representation including a pixel quantity with pixels P(i, j) in columns j and lines i, which image-like representation is evaluated by calculating altitude values in a geodetic coordinate system using the flight condition from the aircraft, evaluating pixel quantity by comparing each pixel P(l, j) to threshold values or ranges of values, evaluating the image-like representation and highlighting each pixel as a picture element if any of various cases is present.

1. Field of the Invention
The invention relates to a method for supporting low-level flights in which an obstacle warning is provided for the pilot, whereby information on the topography of the surrounding terrain is collected by at least one sensor located on the aircraft, whereby the information represents raw data, and whereby an image-like representation is calculated from the overall raw data.
2. Description of Background and Relevant Information
Overhead lines and wires can constitute a significant hazard to low-flying aircraft such as helicopters, for example, due to the operational spectrum of applications, i.e., the wide range of applications in which such aircraft are called-upon to operate. In contrast with relatively large solid obstacles, such as, e.g., mountainsides or valley walls, large buildings, edges of forests, or dense groups of trees, there are other obstacles, particularly overhead lines, i.e., cables and wires, e.g., which characterized by their very low visual contrast to their surroundings. This can mean that pilots of such aircraft risk not recognizing such line obstacles until very late, giving rise to critical flight situations.
Sensors based upon laser scanning or imaging radar technology can provide obstacle information in the form of distance images, i.e., image matrices of distance measurement pixels. The problem lies in the development of a method for recognizing lines or line pixels in these distance images that can be performed in real time so that the pilot can be adequately warned about such objects in a targeted manner.
Methods for recognizing lines, such as cables or wires, by means of the Hough transform are known from DE 100 55 572 C2 and U.S. Pat. No. 6,747,576 B2. These methods are aimed at recognizing the line as an entire object and are correspondingly complex and time-intensive in terms of computing. The capacity of conventional processors is too small to carry out the calculations of these methods in real time.
Other methods recognize line pixels solely by searching for sudden changes in the distance value of a pixel compared with those adjacent to it within the column in the distance image. A method of this type is known from DE 198 28 318 C2 and UK Patent Application Publication No. 2 341 506 A. Since it must also be possible to recognize lines when seen against the sky—where there are no valid distance measurement values—a pixel must also be classified as a line pixel when it is surrounded in the column by adjacent pixels with invalid distance values. However, invalid measurement pixels do not occur only when the sensor faces towards the sky, they also occur sporadically, through solar radiation and particularly often through reflections on smooth surfaces, such as, e.g., bodies of water, asphalt streets and squares, take-off or landing runways or helicopter landing airfields. With the method according to DE 198 28 318 C2 these invalid measurement pixels lead to incorrect interpretations of measurement pixels as line pixels, the accumulation of which in particular in the area of take-off and landing runways or with bodies of water considerably restricts the reliability of this method. This has negative effects on the operational applicability in an obstacle warning system for low-flying aircraft.


A set of one and two-dimensional transforms is constructed subject to certain range limited constraints to provide a computationally efficient transform implementation, such as for use in image and video coding. The constraints can include that the transform has a scaled integer implementation, provides perfect or near perfect reconstruction, has a DCT-like basis, is limited to coefficient within a range for representation in n-bits (e.g., n is 16 bits), has basis functions that are close in norm, and provides sufficient headroom for overflow of the range. A set of transforms is constructed with this procedure having an implementation within a 16-bit integer range for efficient computation using integer matrix multiplication operations.

Transform coding is a compression technique used in many audio, image and video compression systems. Uncompressed digital image and video is typically represented or captured as samples of picture elements or colors at locations in an image or video frame arranged in a two dimensional grid. For example, a typical format for images consists of a stream of 24-bit color picture element samples arranged as a grid. Each sample is a number representing color components at a pixel location in the grid within a color space, such as RGB, or YIQ, among others. Various image and video systems may use various different color, spatial and time resolutions of sampling.
Uncompressed digital image and video signals can consume considerable storage and transmission capacity. Transform coding reduces the size of digital images and video by transforming the spatial-domain representation of the signal into a frequency-domain (or other like transform domain) representation, and then reducing resolution of certain generally less perceptible frequency components of the transform-domain representation. This generally produces much less perceptible degradation of the digital signal compared to reducing color or spatial resolution of images or video in the spatial domain.
More specifically, a typical transform coding technique divides the uncompressed digital image's pixels into fixed-size two dimensional blocks, each block possibly overlapping with other blocks. A linear transform that does spatial-frequency analysis is applied to each block, which converts the spaced samples within the block to a set of frequency (or transform) coefficients generally representing the strength of the digital signal in corresponding frequency bands over the block interval. For compression, the transform coefficients may be selectively quantized (i.e., reduced in resolution, such as by dropping least significant bits of the coefficient values or otherwise mapping values in a higher resolution number set to a lower resolution), and also entropy or variable-length coded into a compressed data stream. At decoding, the transform coefficients will inversely transform to nearly reconstruct the original color/spatial sampled image/video signal.
Many image and video compression systems, such as MPEG and Windows Media, among others, utilize transforms based on the Discrete Cosine Transform (DCT). The DCT is known to have favorable energy compaction properties that result in near-optimal data compression. In these compression systems, the inverse DCT (IDCT) is employed in the reconstruction loops in both the encoder and the decoder of the compression system for reconstructing individual image blocks. An exemplary implementation of the IDCT is described in "IEEE Standard Specification for the Implementations of 8×8 Inverse Discrete Cosine Transform," IEEE Std. 1180-1990, Dec. 6, 1990.
A drawback to the IDCT transform as defined in the IEEE Std. 1180-1990 is that calculation of the transform involves matrix multiplication of 64-bit floating point numbers, which is computationally expensive. This can limit performance of the image or video compression system, particularly in streaming media and like media playback applications, where the IDCT is performed on large amounts of compressed data on a real-time basis or under other like time constraints.

2-D transforms for image and video coding


A user is assisted in a real-world environment. An assistance engine receives at least one context from the user. The assistance engine also receives a video stream of the real-world environment. The assistance engine performs an optical character recognition process on the video stream based upon the at least one context. The assistance engine generates a response for the user. A microphone on a head-mounted device receives the context from the user. A camera on the head-mounted device captures the video stream of the real-world environment. A speaker on the head-mounted device communicates the response to the user. The user may move in the real-world environment based upon the response to improve the optical character recognition process.

The present disclosure relates to identifying text in a real-world environment, and more specifically, to a head-mounted device coupled to an assistive engine to provide a user with environmental information that is derived from text depictions.
Head-mounted devices operate by connecting to a processing engine to perform various tasks for a user wearing the device. They may provide visual depictions and are used in virtual reality scenarios to provide users with experiences separate from their environments. Head-mounted devices may also provide users with augmented reality scenarios (e.g., playing music in a user's ears, visually displaying email or map directions into a part of a user's field of vision).

Interactive text recognition by a head-mounted device


Provided are formulations of a stable commercial paroxetine tablet comprising paroxetine hydrochloride anhydrous, povidone, copovidone or HPMC as a binder, and an HCl free/non-hygroscopic filler, prepared by the wet granulation method.

Paroxetine, trans (−)-3-[(1,3-benzodioxol-5-yloxy)methyl]-4-(4-fluorophenyl) piperidine, is a serotonin re-uptake inhibitor, and has the following molecular formula:

Paroxetine, disclosed in U.S. Pat. No. 4,007,196 (incorporated herein by reference), is an orally administered antidepressant for the treatment of depression, social anxiety disorders, obsessive compulsive disorder, panic disorder, generalized anxiety disorder and posttraumatic stress disorder. Other syndromes such as pre-menstrual syndrome (PMS) and male sexual dysfunction can also be treated with paroxetine. Paroxetine is marketed as Paxil®, and in some countries as Seroxat® by GlaxoSmithKline.
Paxil® is prescribed as oral dosage tablets containing 10 mg, 20 mg, 30 mg and 40 mg of the base equivalent of paroxetine hydrochloride. Paxil® tablets include paroxetine hydrochloride hemihydrate, dibasic calcium phosphate dihydrate, hydroxypropyl methylcellulose, magnesium stearate, polyethylene glycols, polysorbate 80, sodium starch glycolate, titanium dioxide and one or more of the following: D&C Red No. 30, D&C Yellow No. 10, FD&C Blue No. 2, FD&C Yellow No. 6.
Paxil® is also available as an oral suspension with a dosage of 10 mg of the base equivalent of paroxetine hydrochloride in a 5 mL suspension containing paroxetine hydrochloride hemihydrate, polacrilin potassium, microcrystalline cellulose, propylene glycol, glycerin, sorbitol, methyl paraben, propyl paraben, sodium citrate dihydrate, citric acid anhydrous, sodium saccharin, flavorings, FD&C Yellow No. 6 and simethicone emulsion, USP.
Although Paxil® and Seroxat® contain HPMC, it is believed that HPMC is a component of the coating in these tablets, which are probably manufactured by a direct compression method. It is believed that these tablets do not contain a binder.
Paroxetine hydrochloride exists in two solid state pseudopolymorph forms differentiated by their degree of hydration. See e.g. U.S. Pat. No. 4,721,723, incorporated herein by reference. Form I is a non hygroscopic hemihydrate and is thermodynamically more stable. Form II is a hygroscopic anhydrate. Form II converts to Form I if seed crystals of Form I are present, when exposed to humid conditions, or if subject to compression.
Commercial paroxetine tablets, such as Paxil® and Seroxat® contain paroxetine as paroxetine hydrochloride (HCl) hemihydrate. According to U.S. Pat. No. 6,113,944, having the earliest priority date of Jun. 30, 1998, a tablet containing paroxetine hydrochloride anhydrous does not exist on the market.
A potential problem with paroxetine hydrochloride anhydrous tablets is the hygroscopic nature of the anhydrous form. U.S. Pat. No. 6,113,944 discloses formulating paroxetine hydrochloride anhydrous into tablets in the absence of water, i.e., dry admixing. WO 02/069969 discloses a certain formulation of paroxetine hydrochloride anhydrous prepared by wet granulation WO 02/069969 provides only one example, which uses microcrystalline cellulose as a filler and copovidone as a binder. WO 02/069969 also discloses that microcrystalline cellulose acts as the perfect excipient. According to WO 02/069969, "[I]t is surprising that in the present invention microcrystalline cellulose acts as a perfect [excipient]." However, microcrystalline cellulose may not be such a perfect excipient.
There is a need for new formulations of paroxetine hydrochloride anhydrous and processes for their preparation.

This patent is subject to a terminal disclaimer.

Stable pharmaceutical formulation of paroxetine hydrochloride anhydrous and a process for preparation thereof


In a method for monitoring a thermodynamic process in an installation, in which image material (5) of the process is produced and the image material (5) is subjected to image evaluation, an eigen value problem approach is used, at least in large part, for automatic image evaluation.

In a known method for monitoring a thermodynamic process in an installation, in which images of the process are produced and subjected to image evaluation, first specific features for image evaluation are defined which appear to be promising to the operator of the installation for modeling the process. For example, one defines specific moments and then reproduces the image material on this, necessarily reduced, system of functions. The selected features, and only these, are then examined and used for creating a process model. Optionally, only parts of the information contained in the image material are extracted and used.

Method for monitoring a thermodynamic process


A bicycle component actuating device is provided with a base member, a first user operating member and a locking member. The base member includes a tube mounting structure having a tube receiving bore with a center mounting axis. The first user operating member is rotatably mounted relative to the base member for rotation between a first operating position and a second operating position about a rotational axis that is parallel to and offset from the center mounting axis of the tube mounting structure. The locking member is movably mounted relative to the base member for selective movement between a locking position to lock the first user operating member in the second operating position and a releasing position to release the first operating member from the second operating position.

1. Field of the Invention
This invention generally relates to a bicycle component actuating device for operating a bicycle component. More specifically, the present invention relates to a bicycle component actuating device that has a pair of operating members that are conveniently located for a user.
2. Background Information
Bicycling is becoming an increasingly more popular form of recreation as well as a means of transportation. Moreover, bicycling has become a very popular competitive sport for both amateurs and professionals. Whether the bicycle is used for recreation, transportation or competition, the bicycle industry is constantly improving the various components of the bicycle. In the past, most bicycles had rigid frames which typically transmitted the shocks resulting from rough riding surfaces directly to the rider. In other words, most bicycles were not provided with any front or rear suspension. Recently, bicycles, especially mountain bikes (MTB) and all terrain bikes (ATB), have been outfitted with front and/or rear suspension assemblies to absorb the shocks transmitted to the rider when riding on a rough road.
In these bicycles with suspensions, it is sometimes desirable to be able to quickly adjust or lockout the suspension as needed and/or desired. Thus, there have been proposals to provide a suspension actuating device on the handlebar of the bicycle so that the rider can adjust or lockout the suspension as needed and or desired while riding. Three examples of actuating devices for bicycle suspensions are disclosed in U.S. Pat. No. 6,767,024, U.S. Patent Publication No. 2005/0103149 and U.S. Patent Publication No. 2005/0252330. While these actuating devices are functional, it is desirable to provide an actuating device that is simple to operate with distinct operating motions for switching between a first operating position (e.g., a first suspension setting position) and a second operating position (e.g., a second suspension setting position).
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved bicycle component actuating device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.


A high-heeled shoe having a sole and a heel of at least 4 cm height provided thereto, wherein the heel is provided with a damping element. The damping element has different effective damping cross sections along the heel's longitudinal axis and/or is freely deformable in at least one direction perpendicular to the heel's longitudinal axis.

These heels require a specific type of damping due to the enhanced load and pressure conditions. A research study among almost 2,000 women published in the technical journal Arthritis Rheum. (15 Oct. 2009; 61(10):1352-1358) shows that in most cases heel or ankle pains are the result of wearing high-heeled shoes in the past. This is one of the 20 most frequent reasons for consulting a doctor for women at the age of 65 to 74 years.


An electrically writable and erasable read-only memory cell arrangement fabricated in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. A cell array with memory cells is provided on a main surface of the semiconductor substrate. Each memory cell comprises an MOS transistor, vertical to the main surface and comprising, in addition to the source/drain region and a channel region arranged in-between, a first dielectric, a floating gate, a second dielectric and a control gate. A plurality of essentially parallel strip-shaped trenches are provided in the cell array. The vertical MOS transistors are arranged on the flanks of the trenches. The memory cells are in each case arranged on opposite flanks of the trenches.

Many applications require read-only memory cell arrangements with electrically writable and electrically erasable silicon-technology read-only memory cells, so-called EEPROMs. The stored data remain in these EEPROM arrangements even in the absence of a supply voltage.
From the technical point of view, these memory cells are usually produced by an MOS transistor which has, on the channel region, a first dielectric, a floating gate, a second dielectric and a control gate. If a charge is stored on the floating gate, then this charge affects the threshold voltage of the MOS transistor. In such a memory cell arrangement, the state "charge on the floating gate" is assigned to a first logic value, and the state "no charge on the floating gate" is assigned to a second logic value. The information is written into the memory cells by using a Fowler-Nordheim tunnelling current or by a "hot electron" current, by which electrons are injected onto the floating gate. The information is erased by a tunnelling current through the first dielectric. At least eight EEPROM transistors are connected to one another the other in series in a NAND arrangement.
The MOS transistors are designed as planar MOS transistors and are arranged in a planar cell architecture. The minimum area required for a memory cell is therefore equal to 4F.sup.2, F being the smallest producible structure size in the respective technology. EEPROM arrangements of this type are currently offered for maximum data volumes of 32 Mbit.
JP-A 3-1574 proposes an electrically writable and erasable read-only memory cell arrangement which comprises, as memory cells, MOS transistors which are vertical to a main surface of a semiconductor substrate and have a floating gate and a control gate. Essentially parallel strip-shaped trenches are provided in the substrate. The vertical MOS transistors are arranged on the flanks of the trenches. In this case, the memory cells are in each case arranged on opposite flanks of the trenches. Strip-shaped doped regions, which comprise the source and drain regions of the MOS transistors, extend in each case at the trench bottom and on the main surface between neighboring trenches. These strip-shaped doped regions are produced by masked implantation after the trenches have been formed. Because of the unavoidable alignment inaccuracy when masking steps are used, the packing density which can be achieved in this memory cell arrangement is limited.
US-A 5 049 956 discloses an electrically writable and erasable memory cell arrangement which comprises vertical MOS transistors, with floating gate and control gate, arranged in point-like trenches. A continuous doped layer, which acts as a common source region for all the MOS transistors, is provided at the bottom of the trenches. In order to increase the coupling capacitance, the floating gates protrude above the surface of the substrate.
Larger volumes of data can currently be stored in readable and erasable form only in dynamic memory cell arrangements (DRAM) or on magnetic data carriers. A DRAM continuously requires a supply voltage in order to retain the stored data. In contrast, magnetic data carriers are based on mechanical systems with rotating storage media.
The object of the invention is to provide a method for the production of a read-only memory cell arrangement which can be produced with a low area requirement per memory cell.

Method of producing a read-only storage cell arrangement


A robot picking system includes a robot that picks up a work in a first stocker accommodating a plurality of works, a control device that controls an operation of the robot, and an image acquiring device that acquires image data including information related to the plurality of works. The control device includes a candidate data generating unit that generates candidate data including information of candidate works that are candidates of a picking-up target using the image data, and a target work selecting unit that selects a target work that is a picking-up target from the candidate works using the candidate data.

1. Field
The present disclosure relates to a robot picking system, a control device and a method of manufacturing a workpiece.
2. Description of the Related Art
There is a picking technique of taking out a corresponding work from a stocker in which works having the same shape such as bolts are randomly accommodated and holding the corresponding work. A robot picking system using a picking technique is disclosed in JP 2011-183537 A. The robot picking system inspects a holding state of a work taken out by a robot, and supplies only works in which an inspection result satisfies a certain condition to a next process.

Robot picking system, control device, and method of manufacturing a workpiece


Optimizations are provided for generating passthrough visualizations for Head Mounted Displays. The interpupil distance of a user wearing a head-mounted device is determined and a stereo camera pair with a left and right camera is used to capture raw images. The center-line perspectives of the images captured by the left camera have non-parallel alignments with respect to center-line perspectives of any images captured by the right camera. After the raw images are captured, various camera distortion corrections are applied to the images to create corrected images. Epipolar transforms are then applied to the corrected images to create transformed images having parallel center-line perspectives. Thereafter, a depth map is generated of the transformed images. Finally, left and right passthrough visualizations are generated and rendered by reprojecting the transformed left and right images.

Virtual-reality computer systems have recently received significant interest because of their ability to create immersive experiences and environments for users. Many virtual-reality computer systems use one or more on-body devices, such as a head-mounted device ("HMD") to render a virtual environment to a user. Conventional virtual-reality systems completely obstruct the actual world and display only the virtual environment to the user through the HMD. As a result, a user is completely immersed within the virtual environment and may not be aware of his/her real-world surroundings.
Continued advances in hardware capabilities and rendering technologies have greatly increased the realism of virtual objects displayed within a virtual-reality environment. For example, in virtual-reality environments, virtual objects can be placed within the virtual world in such a way as to give the impression that the user is completely immersed in a new world as opposed to his/her actual environment. As the user moves around within the real world, the virtual-reality environment automatically updates so that the user is provided with the proper perspective and view of the virtual objects. This virtual-reality environment is often referred to as a computer-generated scene, or simply a "scene." As used herein, "virtual-reality environment," "computer-generated scene," or simply "scene" are interchangeable terms that relate to an experience in which virtual content is projected in a virtual environment.
As discussed earlier, a virtual-reality head-mounted device completely obstructs a user's ability to see his/her real-world environment. In some situations, however, it is desirable for the user to view his/her real-world environment while still wearing the head-mounted device. To address this need, some VR systems have been developed to generate a "passthrough" visualization of that user's real-world environment. This passthrough visualization is rendered on the HMD of the head-mounted device so the user can view his/her real-world environment without having to remove the head-mounted device. To that end, cameras mounted on the user's head-mounted device capture visualizations of the user's real-word surroundings, and those visualizations are then projected onto the HMD so the user can view the real world without having to take off the head-mounted device.
While some technologies are available for generating passthrough visualizations, the current technologies are seriously lacking. In particular, the current technology is very costly because it requires new hardware (i.e., cameras) to be installed on the head-mounted device to capture the user's real-world surroundings. Furthermore, the current technology fails to optimize its passthrough visualizations to maximize the user's comfort when perceiving those visualizations. To clarify, each user perceives his/her environment in a different manner due to differences in body composition (e.g., distance between a person's eyes). The current passthrough technology fails to account for these body composition differences when generating its passthrough visualizations. To summarize, while some passthrough technologies have been developed, these technologies fail to accommodate the needs of many users.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.

IPD correction and reprojection for accurate mixed reality object placement


A new cultivar of Gaillardia, ‘Jazzy Wheeler’, characterized by its large inflorescences with ray florets that exhibit yellow-orange centers and yellow tips, its numerous blooms produced throughout the growing season, and its dwarf, spreading habit and reliably perennial plant habit with hardiness in U.S.D.A. Zones 3 to 9.

The present invention relates to a new and distinct cultivar of Gaillardia plant, botanically known as Gaillardia aristata 'Jazzy Wheeler' and will be referred to hereinafter by its cultivar name, 'Jazzy Wheeler'.
'Jazzy Wheeler' was derived from a controlled breeding program conducted by the Inventor at a nursery in Schwamstedt, Germany. The breeding program focuses on obtaining new cultivars of Gaillardia with compact and floriferous plant habit in a range of flower colors. 'Jazzy Wheeler' was selected in 2006 by the Inventor as a single unique plant derived from a cross made in 2005 between unnamed plants from his breeding program with the female parent identified with accession No. G04051 and the male parent identified with accession No. G04045.
Asexual reproduction of the new cultivar was first accomplished via stem cuttings in Lisse, The Netherlands in 2006. The characteristics of this cultivar have been determined to be stable and are reproduced true to type in successive generations.


A method and apparatus is provided to utilize the configurability of a programmable logic device (PLD), so as to reduce the complexity of special test equipment (STE) fixtures that are required to test the PLD. The output drivers of certain I/O buffers of the PLD that are not under test may be configured to exhibit a particular impedance magnitude. The impedance magnitude of the output drivers that are not under test may then be used to supply the reference impedance that is required by the digitally controlled impedance (DCI) controllers of the I/O buffers that are under test. The DCI controllers may then correctly configure the impedance magnitude of the respective I/O buffers under test, so as to test the functionality of the controlled impedance buffers for I/O standards that require controlled impedance.

PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more "function blocks" connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Due to their high degree of configurability, FPGAs are ideally suited for the implementation of one or more I/O interfaces that are capable of supporting a large number of input/output (I/O) interface standards. For example, many modern processing systems operate according to the peripheral component interconnect (PCI) standard, which among other features, defines a specification for attaching peripheral devices to a computer mother board. In other examples, modern processing systems may also utilize the high speed transceiver logic (HSTL) standard for data transfers to and from memory, and/or the low-voltage differential signaling (LVDS) standard for backplane communications.
Some of the I/O standards that may be supported by an FPGA also require a controlled impedance at the respective input and output terminals of the I/O buffers, so as to maintain signal integrity despite the increasingly faster edge rates that must be supported by the I/O buffer. Discrete resistors have traditionally been employed to provide such a controlled impedance, but the amount of circuit board area required by the discrete resistors is prohibitive, especially in light of the fact that modern FPGAs contain many banks of I/O buffers. In addition, locating each resistor in close proximity to each I/O buffer, as required to optimize impedance control, may be physically impossible.
Digitally controlled impedance (DCI) may, therefore, be employed to configure the I/O buffer with on-die termination impedance, thus obviating the need for external resistors. The DCI controller adjusts the output impedance, or the input termination impedance, to appropriately match the characteristic impedance of the transmission medium. In particular, a DCI controller is implemented for each bank of I/O buffers, whereby the DCI controller adjusts the impedance of each I/O buffer within the bank of I/O buffers to be proportional to the impedance magnitude of external reference resistors that are connected to impedance reference pins of each I/O bank. As such, each I/O buffer exhibits the correct input/output impedance that may be required by the controlled impedance I/O standard that may be supported by the I/O buffer.
In order to test controlled impedance I/O standards for each I/O bank, traditional test methodologies require that a pair of discrete resistors be connected to the impedance reference pins of each I/O bank under test. Such resistor connections are typically implemented within special test equipment (STE) fixtures, whereby the STE fixtures facilitate the testing of multiple FPGAs simultaneously, by providing all I/O and power connections that are required for each test scenario.
Since each I/O bank of each FPGA is configurable, however, an I/O bank may be configured to support a controlled impedance I/O standard, such as HSTL, during a first test scenario, but may be re-configured to support a non-controlled impedance I/O standard, such as PCI, during a second test scenario. As such, the STE fixture is further required to employ switching means, such as relays, to connect the discrete resistors to the impedance reference pins of each I/O bank that is to be tested during the first test scenario. The STE fixture is then required to disconnect the discrete resistors from the impedance reference pins of each I/O bank that is to be tested during the second test scenario.
STE fixtures are often configured as multi-site testers, whereby multiple FPGAs are tested simultaneously. As such, the complexity of the STE fixture is necessarily exacerbated when the STE fixture is required to support the testing of both controlled and non-controlled impedance I/O standards for each I/O buffer of each FPGA under test. Efforts continue, therefore, to utilize the configurability of the FPGA to reduce the complexity of the STE fixture without sacrificing test support for controlled impedance I/O standards.

Method and apparatus for testing a controlled impedance buffer


A method and a system for managing an online shop use an instant messaging system to allow an auxiliary account to log in and manage an online shop of a primary account user. The primary account user creates an online shop in an online shop server, and associates itself with one or more auxiliary accounts in an instant messaging system. Upon authorization by primary account user to allow an auxiliary account to manage the online shop, the system records an authorization relation between the auxiliary account and the primary account. The authorization relation may be recorded in the instant messaging system. Based on the recorded authorization relation, the system allows a user of the authorized auxiliary account to manage the online shop system through the instant messaging system. An instant messaging server serving for this purpose is also disclosed.

The present disclosure relates to the fields of electronic commerce technologies, and particularly to methods and systems for managing an online shop.
In an existing e-commerce system, a user may open a shop on the Internet, log in and manage the online shop through a registered account. Through this account for logging in and managing the online shop, the user may also log in an instant messaging system (IM), such as AliWangWang, to communicate with a buyer, and create one or more auxiliary accounts with corresponding passwords in the instant messaging system. Users of the auxiliary accounts can also communicate with buyers who conduct businesses with the online shop.
If a user creates an account for an online shop, the account is saved in an online shop server, such as a server at the e-commerce site TaoBao.com. As the user logs in a related instant messaging server such as AliWangWang associated with TaoBao.com, the instant messaging server requests the online shop server of TaoBao.com to check the user's account name and password, and allows the user to log into AliWangWang upon successful verification. On the other hand, since an auxiliary account is created on the instant messaging system AliWangWang and is only saved in an IM server of AliWangWang, a user of the auxiliary account is unable to log into the online shop server of TaoBao.com.
In general, if one or more auxiliary accounts are created from an account S, the account S is referred to be "primary account", while the auxiliary accounts may serve the primary account. Users of these auxiliary accounts, however, are only allowed to log into IM, but not into the online shop system. As a result, the users of the auxiliary accounts in the existing systems cannot log in and manage the online shop established by a primary account user.

Managing online shop using instant messaging system


An interface detecting circuit and interface detecting method are provided, whereby operations can be carried out depending on peripheral devices connected to USB terminals, and whereby the system can be simplified and software load can be reduced. A pull-down resistor is connected to an ID terminal of a Mini-A receptacle of a peripheral device, the voltage generated by the pull-down resistor, which is pulled down by the ID terminal of the Mini-A receptacle of the peripheral device, and a pull-up resistor, which is pulled up by the ID terminal of a Mini-B receptacle of a device, is detected in an analog fashion, using a detecting section comprised of comparators, and, via a logic section, a logic output is subjected to noise cancellation in a filter section and is memorized in a register section. The operations of other devices are determined according to the states memorized in the register section.

1. Field of the Invention
The present invention relates to an interface detecting circuit mounted in electronic devices such as mobile devices and an interface detecting method. More particularly, in an interface system, in which a device and the host are connected through a USB (Universal Serial BUS) cable, the present invention relates to an interface detecting circuit and interface detecting method for detecting the type of the host and the connecting state on the device side.
2. Description of the Related Art
The USB has been widely used as a general-purpose interface. The USB is a standard specification, which is standardized by USB-IF (USB Implementers Forum) and a serious bus for connecting host devices such personal computers with peripheral devices such as a mouse and a keyboard. The USB offers features of allowing peripheral devices such as a keyboard, mouse, modem and joy stick to connect with a personal computer through a single interface and making the connection simple utilizing less costly parts.
A well-known USB connector apparatus has a USB plug (Series A Plug) and a USB socket (Series A Receptacle) to connect with the USB plug (Series A Plug).
The USB plug is provided on an end of a cable to connect with a memory medium such as a portable disk, MP3 player and a recording pen and formed by covering a substrate section (which may be referred to as "base section"), in which a plurality of connecting terminals are fixed on the surface thereof covered with a ring-like metallic casing layer.
This substrate section is provided inside the metallic casing layer such that it is in a firm contact with the bottom surface of the casing layer and a connection nipping layer for use in connecting to the USB socket (Series A Receptacle) is possessed between the surface of the substrate section and the top face of the casing layer.
On the other hand, the USB socket, to which the USB plug is to be connected, has a metallic casing which is fitted to the outside of the casing layer of the USB plug and a nipping plate section (projecting plate section) the periphery of which is covered with a casing and which is inserted into the connection nipping layer of the USB plug so that it is nipped between the casing layer and the plate section. Contact pins to connect with the connecting terminals are disposed on the bottom side of the nipping plate section, so that, if the USB plug is connected to the USB socket, the contact pins are connected to the connecting terminals.
The plurality of the connecting terminals which are connected when the USB plug is inserted into the USB socket (Series A Receptacle) are terminals for VCC power circuit, GND power circuit, D+data transmission circuit and D−data transmission circuit. The D+data transmission circuit terminal and the D−data transmission circuit terminal are used for data transmission, and the VCC power circuit terminal and the GND power circuit terminal can receive a working current supplied by the USB host or the power supplying device.
Hereinafter, the terminals for the VCC power circuit, GND power circuit, D+data transmission circuit and D−data transmission circuit will be referred to as USB terminals and will be, collectively, referred to as USB terminal parts.
Because the USB (Series A) connector apparatus includes only four USB terminals, it can be considered to transmit a larger amount of information by increasing the number of terminals for signal transmission.
For example, between connecting terminals on the top face of the plate part of a USB plug of some USB connector, other connecting terminal for transmitting another signal is provided, and a contact pin is formed at a position matching the other connecting terminal of the substrate part of the USB plug to be connected on a USB socket nipping plate.
The USB employs a protocol of master/slave and devices using the USB interface have the relationship host and device. Usually, when connecting peripheral devices, it is necessary to provide at least one of the peripheral devices with a function as the host.
USB-OTB (USB On-The-Go), which allows the device side to supply electricity when the peripheral devices are connected, has been released, so that the peripheral device is operated as dual-role device which can serves as a device or a host. However, the function of SRP (Session Request Protocol) or HNP (Host Negotiation Protocol) is required to operate the USB-OTG thereby leading to increase in cost on the fields of software and hardware.
Patent Document 1 has disclosed a USB interface system in which the device and the host are connected through the USB cable such that the GND voltage of the ID terminal of the Mini-A receptacle is detected on the device side while electricity is supplied to the host side.
FIG. 1 is a diagram showing the configuration of the USB interface system described in Patent Document 1.
Referring to FIG. 1, USB interface system 10 includes peripheral device (hereinafter referred to as host) 11, which implements the function of the USB host, device (hereinafter simply "device") 12 which take the function of the USB device and USB cable 13 for connecting these.
According to USB2.0, the USB is constituted of a VBUS as a power line, D+line as a plus side data line, D−terminal as minus side data line, ground (GND) line and ID line for use in distinguishing a host or a device in the dual role device. Supply of electricity to a peripheral device on one side is carried out through the VBUS line. By transferring data serially on a pair of data lines constituted of the D+line and D−line, high speed data transfer is achieved.
Host 11 is controlled by a host controller (not shown), so that all processing generated in bus are started by the host. Host 11 includes Mini-A receptacle 14, which is a connector specialized for the host. Mini Mini-A plug 15 of the USB cable 13 can be inserted into Mini-A receptacle 14.
Device 12 includes a USB device controller (not shown). Because data transfer is controlled by a host controller, even if data is sent from the device side, no data can be sent unless the host gives a right of use of the bus to the device. Device 12 includes Mini-B receptacle 16, which is a connector specialized for the device. Mini-B plug 17 of the USB cable can be inserted into Mini-B receptacle 16. In the meantime, the device that performs the role of the device will be referred to as "B device".
USB cable 13 has a directivity and includes Mini-A plug 15 on one end and Mini-b plug 17 on the other end. Different shapes of the connectors on both ends of the cable prevent the USB hosts or USB devices to connect with each other by mistake.
While a USB connector of a conventional full size (standard) is provided with four terminals, these new connectors (plug and receptacle) have five terminals. That is, they have an ID terminal as well as the VBUS terminal, D+terminal, D−terminal and GND terminal. The ID terminal is used to, when a plug is inserted into a dual role device having the Mini-AB receptacle, distinguish whether it is Mini-A plug or Mini-B plug. Because in an ordinary USB cable based on USB-OTG, the ID terminal of the Mini-A plug is short-circuited by the GND line and the ID terminal of the Mini-B plug is open, which the Mini-A plug or the Mini-B plug has been connected can be determined by measuring the voltage level of the ID terminal.
In USB cable 13, the ID terminals of Mini-A plug 15 and Mini-B plug 17 are connected straightly through the ID line. The ID terminal of Mini-A receptacle 14 on the host side is connected to the GND line. Thus, if host 11 and device 12 are connected by USB cable 13, the ID terminal on device 12 side is connected to the GND line.
The ID terminal on device 12 side is pulled up. That is, the ID terminal is connected to a power supply Vcc through the pull-up resistor Rp and maintained at a predetermined voltage level ("H" level). Device 12 has power supplying section 18 for supplying electricity to the VBUS terminal. Power supply section 18 monitors the voltage level of the ID terminal and when it detects that the voltage level has dropped to a predetermined level ("L" level), starts supply of electricity.
In the system having the above-described configuration, if host 11 and device 12 are connected by USB cable 13, the ID terminal on device side 12 is short-circuited by the GND line so that the voltage level of the ID terminal drops. If power supply section 18 detects that the voltage level of the ID terminal is dropped from "H" to "L", it starts supply of electricity to the VBUS terminal, so that electricity is supplied to host 11 through the VBUS line of USB cable 13.
Patent Document 1: Japanese Patent Application Laid-Open No. 2005-25405
However, such a conventional USB interface system has following problems.
A mobile telephone having the USB terminal needs to connect with every kind of the peripheral device for the reason for diversification and multi-functionalization of the mobile telephone and as a result, the mobile telephone on the device side cannot meet demands from every kind of the peripheral device unless other function than the power supply function of the conventional technique is employed. More specifically, if a headphone is connected to the mobile telephone, signals necessary for the headphone need to be sent through the USB cable. If the mobile telephone is connected to a personal computer, it needs to be operated as a UART (Universal Asynchronous Receiver Transmitter) through the USB cable. Further, the USB terminal needs charging function, and the mobile telephone is demanded to implement adequate operations according to the charging apparatus connected to the USB terminal.
For example, if a Low-power hub is connected to the USB terminal, the mobile telephone on the device side needs to be charged with a charging current of 100 mA or less, and if a High-power hub is connected, it needs to be charged with a charging current of 200 mA or more.

Interface detecting circuit and interface detecting method


The present invention relates a method for epitaxial growth of a second group III-V crystal having a second lattice constant over a first group III-V crystal having a first lattice constant, wherein strain relaxation associated with lattice-mismatched epitaxy is suppressed and thus dislocation defects do not form. In the first step, the surface of the first group III-V crystal (substrate) is cleansed by desorption of surface oxides. In the second step, a layer of condensed group-V species is condensed on the surface of the first group III-V crystal. In the third step, a mono-layer of constituent group-III atoms is deposited over the layer of condensed group-V species in order for the layer of constituent group-III atoms to retain the condensed group-V layer. Subsequently, the mono-layer of group-III atoms is annealed at a higher temperature. In the fourth step, bulk of the second group III-V crystal is grown with the condensed group-V layer accommodating the strain build-up which occurs during the bulk growth.

An obstacle in realizing next-generation microelectronic and optoelectronic devices and optimal integration of these devices is found in lattice mismatches between different crystals of group III-V semiconductor materials. Generally, the lattice mismatch between a substrate and an epitaxial over-layer induces strains within the over-layer. This may lead to strain relaxation which can result in formation of material defects such as dislocations within the crystalline structure of the over-layer. FIG. 1 illustrates a mismatched over-layer 1 epitaxially grown over a substrate 2, the boundary between the over-layer 1 and the substrate 2 being indicated with reference numeral 4. As shown in FIG. 1, the lattice constant associated with the over-layer 1 is different from the lattice constant associated with the substrate 2, hence the term "mismatched over-layer". Strain relaxation due to lattice mismatch is accommodated by the formation of mismatch dislocations 3 within the crystal. Defects within a crystal generally degrade the performance of devices made from the crystal, because such defects can scatter movement of carriers (electrons and holes) and can act as carrier traps and/or recombination centers. It is thus useful to provide means for growing a crystal over-layer which has different lattice constant from the substrate on which the over-layer is grown, in such a fashion that strain relaxation does not occur and mismatch dislocations do not form. FIG. 2 is an example of this, in which the structure of over-layer 1 is preserved and no mismatch dislocations are formed.
In the prior art, two main approaches are used to address the lattice mismatch problem and the strain relaxation it causes:                1) In a first approach, defects are confined in thick relaxed buffers so that the top active layer of a device can be of a different lattice constant from that of the substrate and is as defect free as possible.        2) In a second approach, thin compliant solid layers are bonded to foreign substrates and re-growth is performed.
However, these approaches still present performance degradation problems. A buffer layer of defects degrades the quality of the active layer on top of the buffer layer used for a device. In addition, thick buffer layers are not very suitable for device fabrication because high mesa or deep isolation implants are then necessary for device isolation, and can result in high leakage currents and low wafer yields. Further, procedures for implementing the second approach are rather complicated due to problems associated with wafer bonding, fabrication of thin layers (tens of Å in thickness) and re-growth on surfaces contaminated in the wafer-bonding and fabrication processes.
Hence, there is a need for a method of growing a crystal over a substrate such that mismatch dislocations are prevented from appearing within the crystal, even though the crystal and the substrate have different lattice constants.

Epitaxy with compliant layers of group-V species


A radius dresser is provided including a base removably secured to a recipient surface. Also included is a cutting tip holder rotatable and radially slidable with respect to the base. The holder is selectively fixed with respect to the base. The holder has a cutting tip situated along a radius which remains along a direction in which the cutting tip holder is slidable.

1. Field of the Invention
The present invention relates to radius and angle dressers and more particularly pertains to a new quick set radius dresser for making a dressing radius on grinding wheels faster and easier.
2. Description of the Prior Art
The use of radius and angle dressers is known in the prior art. More specifically, radius and angle dressers heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art dressers include U.S. Pat. No. 4,180,046; U.S. Pat. No. 4,274,231; U.S. Pat. No. 5,038,746; U.S. Pat. No. 5,003,730; U.S. Pat. No. 4,299,196; and U.S. Pat. No. 4,073,281.
In these respects, the quick set radius dresser according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of making a dressing radius on grinding wheels faster and easier.


The invention relates to an arrangement for fastening an inner conductor of a resonator structure and to a method for fastening an inner conductor of a resonator structure to a fastening surface structure. The arrangement comprises a fastening surface structure, which in turn comprises an edge of an opening and the opening defined by the edge, the opening being formed through the fastening surface structure. In addition, the arrangement comprises an inner conductor of a resonator structure arranged at the opening formed through the fastening surface structure, the inner conductor comprising an inner space at least on the portion of the conductor that faces the fastening surface structure, which inner space is defined by the wall of the inner conductor which extends into the opening formed through the fastening surface structure. According to the invention, the fastening arrangement comprises an expander, springy in the radial direction, which is brought and thereby fastened in place into the inner space of the inner conductor placed in the opening in the fastening surface structure, the expander being used for pressing the wall of the inner conductor surrounding the inner space of the inner conductor against the edge of the opening formed through the fastening surface structure, at least on the portion of the opening area where the wall surrounding the inner space of the inner conductor coincides with the edge of the opening formed through the fastening surface structure.

The invention relates to an arrangement for fastening an inner conductor of a resonator structure, the arrangement comprising a fastening surface structure comprising an edge of an opening and an opening defined by the edge, the opening being formed through the fastening surface structure, and an inner conductor of a resonator structure at the opening formed through the fastening surface structure, the inner conductor comprising an inner space at least in the portion facing the fastening surface structure, which inner space is defined by the wall of the inner conductor, the wall extending into the opening formed through the fastening surface structure
The invention further relates to a method for fastening an inner conductor of a resonator structure.
Resonator structures employed in high frequency areas, particularly in radio frequency areas, are used for example at base stations of mobile networks. Filters can be used for example as interface circuits and filter circuits in amplifiers of base station transmitter or receiver units.
In the resonator structures the inner conductor of the resonator is fastened to a fastening surface, which is in practice usually the end, such as a bottom or a cover, of a housing structure serving as the outer conductor of the resonator structure. In other words, the inner conductor is short-circuited to the fastening surface, i.e. in practice to the outer conductor. The short-circuited end of the inner conductor, i.e. the end where the inner conductor is short-circuited to the outer conductor, is also called an inductive end, because signal connection takes place inductively. At the other end of the inner conductor, the inner conductor is galvanically isolated from the outer conductor, the other end thus being what is known as a free end of the inner conductor. The free end of the inner conductor is also called its capacitive end, because signal connection takes place capacitively. The outer conductor and the inner conductor inside the compartment it forms together build a resonance circuit. In practice resonator structures are often multi-circuit structures, i.e. the resonator structure comprises a plural number of inner conductor and outer conductor pairs, each compartment formed of an outer conductor having a separate inner conductor. The resonance circuits of a multi-circuit resonator structure together provide the resonator structure with a desired frequency response.
In a prior art solution the inner conductor is fastened to the fastening surface by means of a screw or a bolt. To ensure that the joint between the inner conductor and the fastening surface is tight enough so that problems related to intermodulation are avoided, the solution has to be provided with a weld at the seam between the inner conductor and the fastening surface, i.e. at the foot of the inner conductor. The weld requires that the entire structure is heated in an oven to an elevated temperature, e.g. to 210 degrees Celsius, so it is apparent that the solution is inconvenient and expensive.
Another solution is provided using a riveting tool. The riveting is carried out by hitting the fastening surface around the opening of the fastening surface with the tool at the lower end of the inner conductor to make the material of the fastening surface at the opening squeeze the inner conductor. The problems related to this solution are similar to those described above.
Prior art also knows another riveting-type solution where a spreading tool is used for hitting the inner space of the inner conductor arranged into the opening of the fastening surface, thus causing the inner conductor wall placed in the opening to widen in the lateral direction. This kind of riveting solution does not, however, provide a permanently tight joint, because after the inner conductor wall has been hit with the spreading tool, there is no pressure left to prevent the radial return motion of the wall. The solution is therefore deficient with regard to the prevention of intermodulation and to the strength of the structure, and therefore a weld has to be used.
Fl publication 89115 teaches a structure, shown in FIG. 6 of the publication, where the inner conductor is fastened to an opening formed through the fastening surface with a solid, non-springy insertion piece, the lower edges of the inner conductor being thereby bent against the bottom of the fastening surface. A drawback of the structure is that the insertion piece is solid and non-springy, and therefore the fastening achieved is deficient, particularly with regard to the tightness required to allow intermodulation to be prevented.
An object of the present invention is to provide an arrangement for fastening an inner conductor of a resonator structure in a manner that offers a cost-effective, rapid and convenient means for accomplishing a tight joint with regard to intermodulation and provides a most solid structure by employing, however, a separate inner conductor that is easy to dimension precisely and the surface of which can be made very smooth, the inner conductor being, as stated, fastened to another separate piece, i.e. a fastening surface structure. The dimensional precision of the inner conductor with regard to the smoothness of its surface and its cross-sectional form has, as is well known, a great impact on the characteristics of a resonator structure.
The above stated object is achieved with a fastening arrangement of the invention, wherein the fastening arrangement comprises an expander, springy in the radial direction, which is brought and thereby fastened in place into the inner space of the inner conductor placed into the opening formed through the fastening structure, the expander being used for pressing the inner conductor wall surrounding the inner space of the inner conductor in a radial direction against the edge of the opening formed through the fastening structure at least on the portion of the opening area where the wall surrounding the inner space of the inner conductor coincides with the edge of the opening formed through the fastening surface structure.
A corresponding object is achieved with a method of the invention for fastening an inner conductor, wherein the inner conductor is fastened at an opening in the fastening surface structure by inserting an expander, which is springy in the radial direction, into an inner space of the inner conductor positioned at the opening in the fastening surface structure, the expander being used for pressing the inner conductor wall surrounding the inner space of the inner conductor in a radial direction against the edge of the opening formed through the fastening surface structure at least on the portion of the opening area where the wall surrounding the inner space of the inner conductor coincides with the edge of the opening formed through the fastening surface structure.
The solution of the invention provides a number of advantages. Thanks to the invention, welding or other additional sealing providing intermodulation between the lower end of the inner conductor and the fastening surface, such as the end of the housing structure of the resonator structure, are no longer needed. The end is for example the bottom or the cover of the housing. The solution of the invention alleviates problems related to intermodulation. The preferred embodiments of the invention and other more detailed applications thereof further emphasise the advantages of the invention. In addition, the manufacture of the invention is rapid and can be easily automated.

Method and arrangement for fastening inner conductor of resonator structure


System and methods are disclosed that enable the detection and management of network assets. Such systems in accordance with the present invention include one or more asset detection systems and one or more asset repositories. Asset detection systems and asset repositories in accordance with the present invention each have an interface for exchanging information. For example, such an interface may enable asset registration information to be detected at an asset detection system and automatically sent to asset repository. Furthermore, for example, such an interface may enable asset registration information to be verified at an asset repository, and enable a verification to be sent to an asset detection system.

To effectively operate and maintain a network infrastructure, network assets must be efficiently detected and managed. A network asset, as that term is used herein, refers to any resource that can be used on a network. Such a network asset may be a "hard" asset such as, for example, a personal computer or a printer, or a "soft" asset such as, for example, a software application.
In conventional systems for detecting and managing network assets, multiple independent systems are employed to acquire and store various information related to network assets. Such independent systems may include "asset detection systems" and "asset repositories." An asset detection system, as that term is used herein, refers to a system that automatically detects and registers assets. An asset repository, as that term is used herein, refers to a system in which assets are manually registered and recorded.
An exemplary conventional system for detecting and managing network assets is shown in FIG. 1. As shown, asset detection and monitoring system 100 includes multiple independent systems 120–150 connected to network 110. Multiple independent systems 120–150 include network and system monitoring tools 120, intrusion detection tools 130, digital asset management (DAM) system 140, and grid information service (GIS) 150. Network and system monitoring tools 120 and intrusion detection tools 130 are example of asset detection systems. DAM 140 and GIS 150 are examples of asset repositories.
Network and system monitoring tools 120 are typically employed to monitor a network and/or system for the appearance of new assets. Upon detection of a new asset, network and system monitoring tools 120 automatically register the asset by acquiring registration information from the asset. For a hard asset, such registration information generally includes information such as a number of central processing units (CPU's) operating at the asset or an amount of memory available at the asset. For a soft asset, such registration information generally includes information such as licensing information and information about the device on which the soft asset can be deployed. Such information about the device on which the soft asset is deployed may be acquired by examining a digital signature that is correlated with a digital certificate issued to the corresponding soft asset. Network "sniffers" may be employed to detect such digital signatures and acquire network information to determine the actual deployed location of a soft asset. A unique identifier such as, for example, an integer or a string may also be assigned to the asset.
Intrusion detection tools 130 are typically employed to detect assets and monitor such assets for an intrusion or security breach. Like network and system monitoring tools 120, intrusion detection tools 130 monitor a network and/or system for new assets, and automatically register such new assets. Intrusion detection tools 130 also monitor detected assets for an intrusion or security breach. If an intrusion or breach is detected, detection tool 130 may generate an alert including an identification of the breached asset. A network or system administrator may then suspend current applications of the breached asset and prevent the breached asset from executing new applications.
DAM system 140 is typically employed as a centralized repository for digital files that enables digital content to be archived, searched and retrieved. Digital content may be stored in databases, which are examples of "asset repositories." Metadata corresponding to the digital content such as photo captions, article key words, advertiser names, contact names, file names or low-resolution thumbnail images is stored in separate databases, that may be referred to as "media catalogs." Such media catalogs refer to items in the asset repositories. Assets are manually registered in the DAM system.
GIS 150 is also typically employed as a centralized repository for assets on a grid. A grid is a collection of distributed computing infrastructure resources, such as, for example, processors, memory, storage, and services that are available over a local area network (LAN) or wide area network (WAN). GIS 150 provides information such as, for example, the availability, location, functionality and capacity of such resources, so that such resources appear to an end user or application as one large virtual computing system. GIS 150 may be used to monitor assets on the grid and to produce reports relating to selected assets.
Such independent systems 120–150 perform several identical operations. For example, both network and system monitoring tools 120 and intrusion detection tools 130 serve as asset detection systems, and both DAM 140 and GIS 150 serve as asset repositories. However, conventional asset detection and management systems do not include an interface for exchanging identical information among independent component systems 120–150. Such an interface would offer several advantages. For example, such an interface would eliminate the duplicative acquisition of identical registration information by asset detection systems 120–130. Furthermore, such an interface would enable registration information to be automatically acquired by an asset detection system 120–130 and electronically reported to an asset repository 140–150. Thus, registration information would no longer need to be manually entered into asset repositories 140–150.
In addition to electronically reporting registration information, such an interface could be used to electronically verify registration information. Specifically, asset detection systems 120–130 could compare acquired registration information with registration information stored in asset repositories 140–150, and, if inconsistencies are detected, an error message could be generated. Such verification of registration information would be particularly advantageous for asset repositories 140–150 that require registration information to be manually entered and are thus susceptible to human errors.
Furthermore, such an interface could be used to enable independent systems to query one another. For example, GIS 150 could query the DAM 140 to obtain information regarding digital licenses. Thus, there is a need in the art for such an interface between multiple independent systems 120–150.

Systems and methods for the detection and management of network assets