Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1xc3x971018 to 1xc3x971019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.

1. Field of the Invention
The present invention relates to a semiconductor device such as DRAMs and a method of manufacturing the same.
2. Description of the Background Art
FIG. 217 is a circuit diagram illustrating a construction of a memory cell of a DRAM. As shown in FIG. 217, a capacitor C1 and an NMOS transistor Q1 are disposed between terminals P1 and P2. One electrode (a cell plate electrode) of the capacitor C1 is connected to the terminal P1, and the other electrode (a storage node electrode) is connected to one electrode (a source or drain electrode) of the NMOS transistor Q1. The gate of the NMOS transistor Q1 is connected to a terminal P3, and the back gate is connected to a terminal P4. In general, the terminal P1 is provided with a fixed potential, the terminal P2 is connected to a bit line, the terminal P3 is connected to a word line, and the terminal P4 serves as a terminal for setting the potential of a well region where the NMOS transistor Q1 is to be formed. Followings are examples of a memory cell element having a construction of xe2x80x9c1 Tr (transistor)+1 capa (capacitor)xe2x80x9d shown in FIG. 217.
FIG. 218 is a plan view illustrating a planar structure of a stack-type memory cell (Type 1). FIG. 219 is a sectional view taken along the line A1xe2x80x94A1 in FIG. 218.
Referring to these figures, an NMOS transistor Q1 and a capacitor C1 are formed within a P well region 22 in which elements are isolated by an isolation insulating film 23. The P well region 22 is selectively formed at an upper layer portion of a semiconductor substrate 21, as shown in FIG. 220. With a plurality of isolation insulating films 23, the P well region 22 is isolated transistor by transistor.
As shown in FIGS. 218 and 219, source/drain regions 31 and 32 are selectively formed in the surface of the P well region 22. A gate oxide films 33 and a gate electrode 34 are formed between the source/drain regions 31 and 32, and a sidewall 35 is formed on both side surfaces of the gate oxide film 33 and a gate electrode 34. The NMOS transistor Q1 is made up of the source/drain regions 31 and 32, gate oxide film 33, gate electrode 34 and sidewall 35.
A storage node electrode 41-1 is formed on the source/drain region 31 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-1 is formed on the upper and side surfaces of the storage node electrode 41-1, and a cell plate electrode 43-1 is formed on the upper and side surfaces of the insulating film 42-1. The capacitor C1 is made of up the storage node electrode 41-1, insulating film 42-1 and cell plate electrode 43-1.
The storage node electrode 41-1 is of a plate structure having a square shape in plan configuration.
FIG. 221 is a plan view illustrating a planar structure of a stack-type memory cell (Type 2). FIG. 222 is a sectional view taken along the line A2xe2x80x94A2 in FIG. 221.
Referring to these figures, a storage node electrode 41-2 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-2 is formed on the upper and side surfaces of the storage node electrode 41-2, and a cell plate electrode 43-2 is formed on the upper and side surfaces of the insulating film 42-2. A capacitor C1 is made up of the storage node electrode 41-2, insulating film 42-2 and cell plate electrode 43-2.
The storage node electrode 41-1 is of a cylindrical structure having a circular shape in plan configuration. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 223 is a plan view illustrating a planar structure of a stack-type memory cell (Type 3). FIG. 224 is a sectional view taken along the line A3xe2x80x94A3 in FIG. 223.
Referring to these figures, a storage node electrode 41-3 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-3 is formed on the upper and inner surfaces of the storage node electrode 41-3, and a cell plate electrode 43-3 is formed on the upper and inner surfaces of the insulating film 42-3. A capacitor C1 is made up of the storage node electrode 41-3, insulating film 42-3 and cell plate electrode 43-3.
The storage node electrode 41-3 has a hollow cylindrical structure having a circular shape in plan configuration, and the insulating film 42-3 and cell plate electrode 43-3 are formed within this cylindrical structure. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 225 is a plan view illustrating a planar structure of a stack-type memory cell (Type 4). FIG. 226 is a sectional view taken along the line A4xe2x80x94A4 in FIG. 225.
Referring to these figures, a storage node electrode 41-4 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-4 is formed so as to cover the convexoconcave part of the storage node electrode 41-4, and a cell plate electrode 43-4 is formed so as to cover the insulating film 42-4. A capacitor C1 is made up of the storage node electrode 41-4, insulating film 42-4 and cell plate electrode 43-4.
The storage node electrode 41-4 has a fin structure made up of a convex part having a large square shape in plan configuration and a concave part having a small area in plan configuration. This allows for a more junction capacitance. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 227 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 1). As shown in the figure, a cell plate electrode 43-5 of trench structure is buried within a P well region 22. The cell plate electrode 43-5 is covered at its surroundings with an insulating film 42-5, and a source/drain region 63 is formed so as to cover the surroundings of the insulating film 42-5.
The source/drain region 63 functions as one electrode of the NMOS transistor Q1 and also functions as a storage node electrode of the capacitor C1. Otherwise, the construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 228 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 2). As shown in the figure, a cell plate electrode 43-6 of trench structure is buried within a P well region 22. An insulating film 42-6 is formed so as to cover the side surface of the cell plate electrode 43-6, and a source/drain region 64 is formed so as to cover part of the surroundings of the insulating film 42-6.
The gate electrode 67 is partially buried in the P well region 22 and is isolated from the cell plate electrode 43-6 with an insulating region 70 interposed therebetween. A gate oxide film 66 is formed on one side surface of the gate electrode 67, and the side surface end of the gate electrode 67 overlaps in part the end of the source/drain region 64 via the gate oxide film 66.
A sidewall 68 is disposed above the P well region 22 via the gate oxide film 66 and is adjacent to the gate electrode 67. A source/drain region 65 is formed adjacent to the underside of the sidewall 68 in the P well region 22.
Thus, an NMOS transistor Q1 is made up of the source/drain regions 64 and 65, gate oxide film 66, gate electrode 67 and sidewall 68, and a capacitor C1 is made up of the source/drain region 64, insulating film 42-5 and insulating film 42-6. That is, the source/drain region 64 functions as one electrode of the NMOS transistor Q1 and also functions as a storage node electrode of the capacitor C1.
FIG. 229 is a plan view illustrating a planar structure of a stack-type memory cell (Type 5). FIG. 230 is a sectional view taken along the line A5xe2x80x94A5 in FIG. 229.
Referring to these figures, a storage node electrode 41-7 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-7 is formed on the upper and side surfaces of the storage node electrode 41-7, and a cell plate electrode 43-7 is formed on the upper and side surfaces of the insulating film 42-7. A capacitor C1 is made up of the storage node electrode 41-7, insulating film 42-7 and cell plate electrode 43-7.
The storage node electrode 41-7 is of a cylindrical structure having a circular shape in plan configuration and it has rough upper and side surfaces. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 231 is a plan view illustrating a planar structure of a stack-type memory cell (Type 6). FIG. 232 is a sectional view taken along the line A6xe2x80x94A6 in FIG. 231.
Referring to these figures, a storage node electrode 41-8 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 42-8 is formed on the upper surface and inner side surface of the storage node electrode 41-8, and a cell plate electrode 43-8 is formed on the upper surface and inner side surface of the insulating film 42-8. A capacitor C1 is made up of the storage node electrode 41-8, insulating film 42-8 and cell plate electrode 43-8.
The storage node electrode 41-8 is of a hollow cylindrical structure having a circular shape in plan configuration and it has rough upper and side surfaces. The insulating film 42-8 and cell plate electrode 43-8 are disposed in this hollow cylinder. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 233 is a plan view illustrating a planar structure of a stack-type memory cell (Type 7). FIG. 234 is a sectional view taken along the line A7xe2x80x94A7 in FIG. 233.
Referring to these figures, a storage node electrode 41-9 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 44-9 is formed on the upper and side surfaces of the storage node electrode 41-9, and a cell plate electrode 43-9 is formed on the upper and inner surfaces of the insulating film 44-9. A capacitor C1 is made up of the storage node electrode 41-9, insulating film 44-9 and cell plate electrode 43-9.
The insulating film 44-9 is formed from a material having a relatively high relative dielectric constant k. Examples of materials having a high relative dielectric constant are SiON, Si3N4, Al2O3, ZrO2, HfO2, Ta2O5, La2O3, TiO2, and BASrTiO3 (BST).
The storage node electrode 41-9 is of a cylindrical structure having a circular shape in plan configuration. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 235 is a plan view illustrating a planar structure of a stack-type memory cell (Type 8). FIG. 236 is a sectional view taken along the line A8xe2x80x94A8 in FIG. 235.
Referring to these figures, a storage node electrode 41-10 is formed on a source/drain region 31 of an NMOS transistor Q1 so as to be electrically connected thereto via a contact hole 40, an insulating film 44-10 is formed on the upper surface and inner side surface of the storage node electrode 41-10, and a cell plate electrode 43-10 is formed on the upper surface and inner side surface of the insulating film 44-10. A capacitor C1 is made up of the storage node electrode 41-10, insulating film 44-10 and cell plate electrode 43-10.
Like the insulating film 44-9, the insulating film 44-10 is formed from a material having a relatively high relative dielectric constant k. The storage node electrode 41-10 is of a hollow cylindrical structure having a circular shape in plan configuration. The storage node electrode 44-10 and cell plate electrode 43-10 are formed within this hollow cylinder. The construction of the NMOS transistor Q1 is the same as that shown in FIGS. 218 and 219, and a description thereof is thus omitted.
FIG. 237 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 3). As shown in the figure, an insulating film 44-11 is disposed between a cell plate electrode 43-11 and source/drain region 63. Like the insulating films 44-9 and 44-10, the insulating film 44-11 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIG. 106, and a description thereof is thus omitted.
FIG. 238 is a sectional view illustrating a sectional structure of a trench-type memory cell (Type 4). As shown in the figure, an insulating film 44-12 is disposed between a cell plate electrode 43-12 and source/drain region 64. Like the insulating films 44-9 to 44-11, the insulating film 44-12 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIG. 106, and a description thereof is thus omitted.
FIG. 239 is a plan view illustrating a planar structure of a stack-type memory cell (Type 9). FIG. 240 is a sectional view taken along the line A9xe2x80x94A9 in FIG. 239. As shown in these figures, an insulating film 44-13 is disposed between a storage node electrode 41-13 and cell plate electrode 43-13. Like the insulating films 44-9 to 44-12, the insulating film 44-13 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIGS. 229 and 230, and a description thereof is thus omitted.
FIG. 241 is a plan view illustrating a planar structure of a stack-type memory cell (Type 10). FIG. 242 is a sectional view taken along the line A10xe2x80x94A10 in FIG. 241. As shown in these figures, an insulating film 44-14 is disposed between a storage node electrode 41-14 and cell plate electrode 43-14. Like the insulating films 44-9 to 44-13, the insulating film 44-14 is formed from a material having a relatively high relative dielectric constant k. Otherwise, the construction of this memory cell is the same as that shown in FIGS. 231 and 232, and a description thereof is thus omitted.
FIGS. 243 to 251 are sectional views illustrating a method of manufacturing a memory cell element of xe2x80x9c1 Tr+1 capa type.xe2x80x9d Referring to these figures, a method of manufacturing a memory cell element having a memory capacitor with a plate structure that is the basis for stack-type ones (see FIGS. 218 and 219) will be described hereinafter with emphasis on the capacitor making process.
Referring to FIG. 243, the elements on a semiconductor substrate are isolated by an isolation insulating film 23, and boron ions are implanted (due to diffusion) at an energy of 300 keV and a dose of 1xc3x971013/cm2, thereby to form a P well region 22. Then, boron ions are successively implanted at an energy of 120 keV and a dose of 5xc3x971012/cm2, then at an energy of 30 keV and a dose of 5xc3x971012/cm2, thereby to form a channel region (not shown).
Referring to FIG. 244, a gate oxide film 33 composed of a silicon oxide film is formed in a thickness of 3 to 10 nm, and a gate electrode 34 of dual structure made up of a polysilicon layer and a tungsten silicon layer, each having a thickness of 50 nm, is then formed on the gate oxide film 33. By using the gate electrode 34 as a mask, phosphorus ions are implanted at an energy of 30 keV and a dose of 1xc3x971014/cm2. Further, a sidewall 35 composed of a silicon oxide film having a width of 5 to 15 nm is formed on the both side surfaces of the gate electrode 34. By using the gate electrode 34 and sidewall 35 as a mask, arsenic ions are implanted at an energy of 10 keV and a dose of 1xc3x971014/cm2, thereby to obtain source/drain regions 31 and 32.
This results in an NMOS transistor Q1 comprising the source/drain regions 31, 32, gate oxide film 33, gate electrode 34 and sidewall 35.
Referring to FIG. 245, an interlayer insulating film 24 is deposited on the entire surface, and a patterned resist 25 is then formed on the interlayer insulating film 24. By using the resist 25 as a mask, the interlayer insulating film 24 is selectively etched away, thereby to obtain a contact hole 40 having a diameter of 0.2 xcexcm and extending through the interlayer insulating film 24.
Referring to FIG. 246, the resist 25 is removed and a (doped) polysilicon layer 45 is then deposited in a thickness of 500 nm on the entire surface.
Referring to FIG. 247, by using a patterned resist 26 as a mask, the polysilicon layer 45 is etched away to obtain a storage node electrode 41. The resist 26 is then removed as shown in FIG. 248.
Referring to FIG. 249, an insulating film 46 and a polysilicn layer 47 are successively formed on the entire surface. For instance, the insulating film 46 may be of a dual structure which comprises SiO2 having a thickness of 7.5 nm and Si3N4 having a thickness of 7.5 nm. Alternatively, it may be TaO5 having a thickness of 15 nm, or BST having a thickness of 15 nm. The polysilicon layer 47 is formed in a thickness of 200 nm.
Referring to FIG. 250, a patterned resist 27 is formed on the polysilicon layer 47.
Referring to FIG. 251, by using the resist 27 as a mask, the insulating film 46 and polysilicon layer 47 are selectively removed to obtain an insulating film 42 and a cell plate electrode 43, and the resist 27 is then removed. This results in a memory cell element having plate type memory capacitors (41 to 43).
Various parameters that determine operating characteristics of an NMOS transistor Q1 used in a memory cell element are determined in well-balance taking mutual tradeoff into consideration. Tradeoff factors to be discussed here are (i) relaxation of gate edge field, (ii) suppression of threshold voltage rise, (iii) assurance of resistance to punch-through, and (iv) leak current reduction (relaxation of junction capacitance).
FIG. 252 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD (lightly doped drain) structure. As shown in the figure, LDD regions 31b and 32b having a low impurity concentration are disposed at an edge proximate region of a gate electrode 34 in source/drain regions 31 and 32. The source/drain regions 31 and 32 are formed by the LDD regions 31b and 32b, together with source/drain primary regions 31a and 32a.
This LDD structure can exhibit the best effect on relaxation of gate edge field, whereas it is less effective on suppression of threshold voltage rise and on leak current reduction, and it acts negatively on assurance of resistance to punch-through.
FIG. 253 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD (double doped drain) structure. As shown in the figure, a source/drain region 31 (32) is made up of a high concentration region 31c (32c) and a low concentration region 31d (32d) that are formed by double diffusion. The high concentration region 31c is formed at a relatively shallow region except for a gate edge proximate region, and the low concentration region 31d is formed at a relatively deep region of the gate edge proximate region and at relatively deep region except for the gate edge proximate region.
This DDD structure exhibits the best effect on relaxation of gate edge field and provides a relatively good result on leak current reduction, whereas it is less effective on suppression of threshold voltage rise and acts negatively on assurance of resistance to punch-through, similarly to the LDD structure.
Thus, the usual LDD structure and DDD structure suffer from the disadvantage that these are unsuitable for assurance of resistance to punch-through.
FIG. 254 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a channel dope region. As shown in the figure, in addition to the LDD structure, a P type channel dope region 38 is disposed so as to overlap in part a lower layer of a source/drain primary region 31a (32a) and overlap the lowermost part of an LDD region 31b (32b).
The LDD structure employing the channel dope region exhibits the best effect on assurance of resistance to punch-through and exhibits a relatively good effect on relaxation of gate edge field, whereas it acts negatively on suppression of threshold voltage rise and on leak current reduction.
FIG. 255 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a channel dope region. As shown in the figure, in addition to the DDD structure, a P type channel dope region 39 is disposed so as to overlap in part a low concentration region 31d (32d).
The DDD structure employing the channel dope region exhibits the best effect on assurance of resistance to punch-through and exhibits a relatively good effect on relaxation of gate edge field, whereas it acts negatively on suppression of threshold voltage rise and on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the channel dope region, suffer from the disadvantage that these structures are unsuitable for leak current reduction and suppression of threshold voltage rise.
FIG. 256 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a local channel dope region. As shown in the figure, in addition to the LDD structure, a P type local channel dope region 48 is disposed under a gate electrode 34, without overlapping source/drain regions 31 and 32.
The LDD structure employing the local channel dope region exhibits a relatively good effect on assurance of resistance to punch-through and relaxation of gate edge field, and it can be arranged such that this structure does not act negatively on leak current reduction, but acts negatively on suppression of threshold voltage rise.
FIG. 257 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a local channel dope region. As shown in the figure, in addition to the DDD structure, a P type local channel dope region 49 is disposed under a gate electrode 34 in little or no overlap relationship with source/drain regions 31 and 32.
The DDD structure employing the local channel dope region exhibits a relatively good effect on assurance of resistance to punch-through, relaxation of gate edge field, and leak current reduction, whereas it acts negatively on suppression of threshold voltage rise.
Thus, the LDD structure and DDD structure, each employing the local channel dope region, suffer from the disadvantage that these are unsuitable for suppression of threshold voltage rise.
FIG. 258 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a pocket region. As shown in the figure, in addition to the LDD structure, P type pocket regions 51 and 52 are disposed which respectively overlap source/drain regions 31, 32 and extend to a lower region of the source/drain regions 31, 32 and to a channel region in a P well region 22.
The LDD structure employing the pocket region exhibits the best effect on suppression of threshold voltage rise and exhibits a relatively good effect on assurance of resistance to punch-through and on relaxation of gate edge field, whereas it acts negatively on leak current reduction.
FIG. 259 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a pocket region. As shown in the figure, in addition to the DDD structure, P type pocket regions 56 and 57 are disposed which respectively overlap source/drain regions 31, 32 and extend to a lower region of the source/drain regions 31, 32 and to a channel region in a P well region 22.
The DDD structure employing the pocket region exhibits the best effect on suppression of threshold voltage rise and exhibits a relatively good effect on assurance of resistance to punch-through and on relaxation of gate edge field, whereas it acts negatively on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the pocket region, suffer from the disadvantage that these structures are unsuitable for leak current reduction.
FIG. 260 is a sectional view illustrating a sectional structure of an NMOS transistor having an LDD structure employing a shallow pocket region. As shown in the figure, in addition to the LDD structure, P type shallow pocket regions 53 and 54 are disposed which respectively overlap mostly of source/drain regions 31 and 32, extend slightly to a channel region in a P well region 22, and have approximately the same forming depth as the source/drain regions 31 and 32.
The LDD structure employing the shallow pocket region exhibits a relatively good effect on suppression of threshold voltage rise, assurance of resistance to punch-through, and relaxation of gate edge field, and further, it does not act negatively on leak current reduction.
FIG. 261 is a sectional view illustrating a sectional structure of an NMOS transistor having a DDD structure employing a shallow pocket region. As shown in the figure, in addition to the DDD structure, P type shallow pocket regions 58 and 59 are disposed which respectively overlap mostly of source/drain regions 31 and 32, extend slightly to a channel region in a P well region 22, and have a slightly shallower forming depth than the source/drain regions 31 and 32.
The DDD structure employing the shallow pocket region exhibits a relatively good effect on suppression of threshold voltage rise, assurance of resistance to punch-through, and relaxation of gate edge field, and further, it does not act negatively on leak current reduction.
Thus, the LDD structure and DDD structure, each employing the shallow pocket region, suffer from the disadvantage that these fail to exhibit the best characteristic in all the tradeoff factors.
In memory cell elements of DRAMs etc., when less leak current is desired only in a source/drain region to be connected to a storage node electrode of a memory capacitor, it can be considered to increase the forming depth of the source/drain region on the storage node side, as shown in FIGS. 262 and 263.
In the case of FIG. 262, a source/drain region 31 is made up of partial source/drain regions 31e and 31f, and the forming depth of the partial source/drain region 31f is increased.
In the case of FIG. 263, a source/drain region 31 (32) is made up of partial source/drain regions 31e (32e) and 31g (32g), and the forming depth of the partial source/drain region 31g is increased.
Thus, the source/drain regions 31f and 31g having the increased forming depth enables to improve the characteristic about leak current reduction.
If assurance of resistance to punch-through is satisfied, it is unnecessary to form the source/drain regions in the same fashion as with FIG. 263. That is, the partial source/drain region 31g having the increased forming depth may be formed only in the source/drain region 31 on the storage node side as shown in FIG. 262.
FIGS. 264 to 268 are sectional views illustrating a sequence of steps in a method of manufacturing a memory cell element in which the forming depth of a source/drain region on the storage node side is increased. The method will be described hereinafter by referring to these figures.
Referring to FIG. 264, after the elements on a semiconductor substrate are isolated by an isolation insulating film 23, a P well region 22 is formed in the same manner as the step in FIG. 243, and a channel region (not shown) is then formed.
Referring to FIG. 265, in the same manner as the step shown in FIG. 244, there is obtained an NMOS transistor Q1 comprising a source/drain partial region 31e, source/drain region 32, gate oxide film 33, gate electrode 34 and sidewall 35.
Referring to FIG. 266, in the same manner as the step shown in FIG. 245, an interlayer insulating film 24 is deposited on the entire surface, thereby obtaining a contact hole 40 extending through the interlayer insulating film 24.
Referring to FIG. 267, an N type impurity ions 49 such as of phosphorus is implanted from the contact hole 40, thereby to form a source/drain partial region 31f.
Referring to FIG. 268, a storage node electrode 41 is obtained in the same manner as shown in the steps in FIGS. 246 to 248.
Further, the steps shown in FIGS. 249 to 251 are performed to complete a memory cell element shown in FIG. 263.
As described above, the MOS transistor of the LDD structure or DDD structure employing the shallow pocket region enables to obtain such characteristics as not to cause any negative actions on relaxation of gate edge field, suppression of threshold voltage rise, assurance of resistance to punch-through, and leak voltage reduction (relaxation of junction capacitance).
On the other hand, MOS transistors used in memory cells of DRAMs call for the following characteristics:
i) relatively good characteristic about relaxation of gate edge field;
ii) characteristic in such degree as to cause no negative action about suppression of threshold voltage rise;
iii) the best characteristic about assurance of resistance to punch-through; and
iv) the best characteristic about leak current reduction.
There has been a problem in that the mentioned characteristics cannot be realized by employing any of the channel dope region, local channel dope region, pocket region and shallow pocket region in MOS transistor structures such as the LDD structure and DDD structure.
According to a first aspect of the invention, a semiconductor device comprises: a transistor forming region of a first conductivity type disposed in a semiconductor substrate; first and second source/drain regions of a second conductivity type disposed selectively in the surface of the transistor forming region, the transistor forming region between the first and second source/drain regions being defined as a channel region; a gate insulating film disposed on the channel region; a gate electrode disposed on the gate insulating film; and a transistor characteristic adjusting region of the first conductivity type disposed in the transistor forming region so as to at least overlap in part the channel region, wherein an insulating gate type transistor is defined by the first and second source/drain regions, the channel region, the gate insulating film, the gate electrode and the transistor characteristic adjusting region, and the first conductivity type impurity concentration of the transistor characteristic adjusting region and the second conductivity type impurity concentration of the first and second source/drain regions are set so as to satisfy the following conditions: 1018xe2x89xa6C1xe2x89xa61019/cm3 . . . (I); and C2/10xe2x89xa6C1xe2x89xa6C2 . . . (II) where C1 is the maximum value of the first conductivity type impurity concentration of the transistor characteristic adjusting region except for a surface proximate region of the transistor forming region, and C2 is the maximum value of the second conductivity type impurity concentration of the first and second source/drain regions except for the surface proximate region.
According to a second aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes a channel dope region disposed at a predetermined depth from the surface of the transistor forming region so as to overlap the channel region in a plane view over substantially the entire surface of the channel region.
According to a third aspect of the invention, the semiconductor device of the second aspect is characterized in that the channel dope region includes a normal channel dope region extending over substantially the entire surface of the transistor forming region in a plane view.
According to a fourth aspect of the invention, the semiconductor device of the second aspect is characterized in that the channel dope region includes a local channel dope region disposed in little or no overlap relationship with the first and second source/drain regions.
According to a fifth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to part of the channel region.
According to a sixth aspect of the invention, the semiconductor device of the fifth aspect is characterized in that the first and second pocket regions include first and second normal pocket regions extending also to the underside of the first and second source/drain regions.
According to a seventh aspect of the invention, the semiconductor device of the fifth aspect is characterized in that the first and second pocket regions include first and second shallow pocket regions having approximately the same forming depth as the first and second source/drain regions.
According to an eighth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes: a first partial transistor characteristic adjusting region disposed at a predetermined depth in the transistor forming region; and a second partial transistor characteristic adjusting region disposed in the transistor forming region so as to be deeper than the first partial transistor characteristic adjusting region.
According to a ninth aspect of the invention, the semiconductor device of the first aspect is characterized in that the transistor characteristic adjusting region includes: a first channel dope region overlapping the channel region in a plane view over substantially the entire surface of the channel region; a second channel dope region disposed at a region deeper than the first channel dope region so as to overlap the channel region in a plane view over substantially the entire surface of the channel region; and first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region.
According to a tenth aspect of the invention, the semiconductor device of the first aspect is characterized in that the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, the first and second high impurity concentration regions being spaced a predetermined distance away from the channel region.
According to an eleventh aspect of the invention, the semiconductor device of the first aspect further comprises a capacitor provided with one electrode electrically connected to one of the first and second source/drain regions.
According to a twelfth aspect of the invention, a method of manufacturing a semiconductor device comprises the steps of: (a) providing a semiconductor substrate having a transistor forming region of a first conductivity type; (b) forming a gate insulating film and a gate electrode on a channel region in the transistor forming region; (c) selectively introducing impurity of a second conductivity type into the transistor forming region, to form first and second source/drain regions of the second conductivity type sandwiching the channel region and being adjacent to the channel region; and (d) introducing impurity of the first conductivity type into the transistor forming region to form a transistor characteristic adjusting region of the first conductivity type so as to at least overlap in part the channel region, wherein an insulating gate type transistor is defined by the first and second source/drain regions, the channel region, the gate insulating film, the gate electrode and the transistor characteristic adjusting region, and the first conductivity type impurity concentration of the transistor characteristic adjusting region and the second conductivity type impurity concentration of the first and second source/drain regions are set so as to satisfy the following conditions: 1018xe2x89xa6C1xe2x89xa61019/cm3 . . . (I); and C2/10xe2x89xa6C1xe2x89xa6C2 . . . (II), where C1 is the maximum value of the first conductivity type impurity concentration of the transistor characteristic adjusting region except for a surface proximate region of the transistor forming region, and C2 is the maximum value of the second conductivity type impurity concentration of the first and second source/drain regions except for the surface proximate region.
According to a thirteenth aspect of the invention, the method of the twelfth aspect is characterized in that the step (d) includes the step of forming a channel dope region as the transistor characteristic adjusting region overlapping the channel region in a plane view over substantially the entire surface of the channel region, at a predetermined depth from the surface of the transistor forming region.
According to a fourteenth aspect of the invention, the method of the thirteenth aspect is characterized in that: the channel dope region includes a normal channel dope region formed over substantially the entire surface of the transistor forming region in a plane view; and the step (d) includes the step of introducing impurity of the first conductivity type into the entire surface of the transistor forming region.
According to a fifteenth aspect of the invention, the method of the thirteenth aspect is characterized in that: the channel dope region includes a local channel dope region formed in little or no overlap relationship with the first and second source/drain regions; and the step (d) includes the step of selectively introducing impurity of the first conductivity type into the channel region in the transistor forming region.
According to a sixteenth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region; and the step (d) includes the step, after the step (b), of forming the first and second pocket regions by introducing impurity of the first conductivity type into the transistor forming region by using the gate electrode as a mask.
According to a seventeenth aspect of the invention, the method of the sixteenth aspect is characterized in that: the first and second pocket regions include first and second normal pocket regions extending also to the underside of the first and second source/drain regions; the step (c) includes a process of implanting ions of the second conductivity type at a first energy by using the gate electrode as a mask; and the step (d) includes a process of implanting ions of the first conductivity type at a second energy higher than the first energy by using the gate electrode as a mask.
According to an eighteenth aspect of the invention, the method of the sixteenth aspect is characterized in that: the first and second pocket regions include first and second shallow pocket regions having approximately the same forming depth as the first and second source/drain regions; and the process of introducing impurity of the first conductivity type in said step (d) includes a process of obliquely implanting impurity ions of the first conductivity type.
According to a nineteenth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes a first partial transistor characteristic adjusting region formed at a predetermined depth in the transistor forming region and a second partial transistor characteristic adjusting region formed at a depth deeper than the first partial transistor characteristic adjusting region in the transistor forming region; the step (d) includes the steps of (d-1) implanting impurity ions of the first conductivity type to form the first partial transistor characteristic adjusting region, and (d-2) implanting impurity ions of the first conductivity type to form the second partial transistor characteristic adjusting region; and that ion implantation conditions of the steps (d-1) and (d-2) is set so that the second partial transistor characteristic adjusting region is deeper than the first partial transistor characteristic adjusting region.
According to a twentieth aspect of the invention, the method of the twelfth aspect is characterized in that: the transistor characteristic adjusting region includes a first channel dope region overlapping substantially the entire surface of the channel region in a plane view, a second channel dope region formed at a region deeper than the first channel dope region so as to overlap substantially the entire surface of the channel region in a plane view, and first and second pocket regions overlapping substantially the whole of the first and second source/drain regions and extending from the first and second source/drain regions to the channel region; and that the step (d) includes the steps of: (d-1) implanting impurity ions of the first conductivity type to form the first channel dope region; (d-2) implanting impurity ions of the first conductivity type to form the second channel dope region; and (d-3) implanting, after the step (b), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second pocket regions.
According to a twenty-first aspect of the invention, the method of the twelfth aspect is characterized in that: the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, each of first and second high impurity concentration regions being spaced a predetermined distance away from the channel region; that the step (c) includes the steps of: (c-1) implanting, after the step (b), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second source/drain regions of the first conductivity type; and (c-2) implanting, after the step (c-1), impurity ion of the first conductivity type by using the gate electrode as a mask, to form the first and second high impurity concentration regions in the surface of the first and second source/drain regions; and that ion implantation conditions of the step (c-2) is set so that the first and second high impurity concentration regions are spaced the predetermined distance away from the channel region.
According to a twenty-second aspect of the invention, the method of the twelfth aspect is characterized in that: the first and second source/drain regions have in their surfaces first and second high impurity concentration regions, respectively, having a higher impurity concentration than other regions, each of first and second high impurity concentration regions being spaced a predetermined distance away from the channel region, the method further comprising the step of: (e) forming a sidewall on both side surfaces of the gate electrode, wherein the step (c) includes the steps of: (c-1) implanting, after the step (b) and before the step (e), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the first and second source/drain regions of the first conductivity type; and (c-2) implanting, after the step (e), impurity ions of the first conductivity type by using the gate electrode and the sidewall as a mask, to form the first and second high impurity concentration regions of the first conductivity type.
According to a twenty-third aspect of the invention, the method of the twelfth aspect is characterized in that: at least one of the first and second source/drain regions has in its surface a high impurity concentration region having a higher impurity concentration than other regions, the high impurity concentration region being spaced a predetermined distance away from the channel region, the method further comprising the step of: (f) forming, after the step (c), a mask layer on the entire surface, the mask layer having an opening above part of at least one of the first and second source/drain regions, wherein the step (c) includes the steps of: (c-1) implanting, after the step (b) and before the step (f), impurity ions of the first conductivity type by using the gate electrode as a mask, to form the source/drain regions; and (c-2) implanting, after the step (f), impurity ions of the first conductivity type from the opening of the mask layer, to form the high impurity concentration region in a region including the surface of the source/drain regions.
According to a twenty-fourth aspect of the invention, the method of the twenty-third aspect further comprises the steps of: (g) filling, after the step (c-1), the opening with an impurity diffusion source of the second conductivity type; and (h) diffusing a second impurity from the impurity diffusion source into the surface of the high impurity concentration region, to form an impurity diffusion region.
According to a twenty-fifth aspect of the invention, the method of the twelfth aspect further comprises the step of (i) electrically connecting one electrode to one of the first and second source/drain regions to form a capacitor.
The insulating gate type transistor of a semiconductor device in the first aspect satisfies the conditions (I) and (II), so that the depletion layer also extends into the first and second source/drain regions at the time of operation. This provides a good characteristic about assurance of resistance to punch-through and a reduction in leak current from the bottom of the first and second source/drain regions.
In the semiconductor device of the second aspect, the above-mentioned good characteristics can be obtained by forming, as a transistor characteristic adjusting region, a channel dope region overlapping mostly of the channel region having a strong relationship with the characteristic of the insulating gate type transistor.
In the semiconductor device of the third aspect, the formation of the normal channel dope region is relatively easy because it is formed over the entire surface of the transistor forming region.
In the semiconductor device of the fourth aspect, the formation of the local channel dope region provides a better characteristic about leak current reduction.
In the semiconductor device of the fifth aspect, an increase in threshold voltage can be suppressed effectively by forming the first and second pocket regions to be partially formed only in the channel region, as a transistor characteristic adjusting region.
In the semiconductor device of the sixth aspect, the normal pocket region is formed so as to extend to a lower part than the first and second source/drain regions. Thereby, the normal pocket region can easily extend to part of the channel region.
In the semiconductor device of the seventh aspect, the shallow pocket region has approximately the same forming depth as the first and second source/drain regions. This permits a further effect of reducing leak current from the bottom of the first and second source/drain regions.
In the semiconductor device of the eighth aspect, a better characteristic about assurance of resistance to punch-through and about reduction in leak current from the bottom of the first and second source/drain regions can be obtained by individually setting the impurity concentration of the first and second partial transistor characteristic adjusting regions.
In the semiconductor device of the ninth aspect, a better characteristic about threshold voltage control, assurance of resistance to punch-through and a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by individually setting the impurity concentration of the first and second channel dope regions and that of the first and second pocket regions.
In the semiconductor device of the tenth aspect, the presence of the first and second high impurity concentration regions allows for a reduction in the resistance value of the current path on the surface of the transistor forming region, without adversely affecting assurance of resistance to punch-through and leak current reduction.
In the semiconductor device of the eleventh aspect, it is able to provide a memory cell comprising an insulating gate type transistor having a good characteristic about assurance of resistance to punch-through and leak current reduction, and a capacitor for storage.
In the insulating gate type transistor obtained by the method of manufacturing a semiconductor device in the twelfth aspect, the conditions (I) and (II) are satisfied so that a depletion layer also extends into the first and second source/drain regions at the time of operation. It is therefore able to obtain a good characteristic about assurance of resistance to punch-through and about a reduction in leak current from the bottom of the first and second source/drain regions.
In the insulating gate type transistor obtained by the method of manufacturing a semiconductor device in the thirteenth aspect, the above-mentioned good characteristic can be obtained by forming, as a transistor characteristic adjusting region, the channel dope region of which flat region overlaps mostly of the channel region having a strong relationship with the characteristic of the insulating gate type transistor.
With the method of the fourteenth aspect, it is relatively easy to form the normal channel dope region by introducing the first impurity into the entire surface of the transistor forming region in the step (d).
In the insulating gate type transistor obtained by the method of the fifteenth aspect, a better characteristic about leak current reduction can be obtained by providing the local channel dope region.
In the insulating gate type transistor obtained by the method of the sixteenth aspect, an increase in threshold voltage can be suppressed effectively by forming the first and second pocket regions disposed only in part of the channel region, as a transistor characteristic adjusting region.
In the method of the seventeenth aspect, the first and second normal pocket regions extending to part of the channel region can be formed relatively with ease by the step (d) in which the first conductivity type ions are implanted at the second energy higher than the first energy by using the gate electrode as a mask.
In the method of the eighteenth aspect, the shallow pocket region of the insulating gate type transistor has approximately the same forming depth as the first and second source/drain regions. This permits a further effect of reducing leak current from the bottom of the first and second source/drain regions.
In the method of the nineteenth aspect, the insulating gate type transistor having a better characteristic about assurance of resistance to punch-through and about a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by the steps (d-1) and (d-2) of individually setting the impurity concentration of the first and second partial transistor characteristic adjusting regions.
In the method of the twentieth aspect, the insulating gate type transistor having a better characteristic about threshold voltage control, assurance of resistance to punch-through, and a reduction in leak current from the bottom of the first and second source/drain regions, can be obtained by the steps (d-1), (d-2) and (d-3) in which the impurity concentration of the first and second channel dope regions and that of the first and second pocket regions are set individually.
In the insulating gate type transistor of the twenty-first aspect, the presence of the first and second high impurity concentration regions allows for a reduction in the resistance value of the current path on the surface of the transistor forming region, without adversely affecting assurance of resistance to punch-through and leak current reduction.
With the method of the twenty-second aspect, the step (c-2) is performed by providing an offset corresponding to the thickness from the channel region to the sidewall. This permits a precise formation of the first and second high impurity concentration regions spaced a predetermined distance from the channel region, respectively.
With the method of the twenty-third aspect, the step (c-2) is performed by providing an offset corresponding to the distance from the channel region to the opening. This permits a precise formation of the high impurity concentration region spaced a predetermined distance from the channel region.
With the method of the twenty-fourth aspect, it is relatively easy to obtain the source/drain regions of triple diffusion structure by the step (h) in which the impurity diffusion region is formed by allowing the second impurity to diffuse from the impurity diffusion source into the surface of the high impurity concentration region.
The method of the twenty-fifth aspect can provide a memory cell comprising the insulating gate type transistor having a good characteristic about assurance of resistance to punch-through and leak current reduction, and a capacitor for storage.
It is an object of the present invention to overcome the aforementioned problems by providing a semiconductor device having a MOS transistor capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and about leak current reduction, as well as a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Semiconductor device and method of manufacturing same


A first device wirelessly transmits beacon frames having distinct identifying contents within each. The first device issues a request to a second device to report what beacon frame contents the second device may have received. The second device sends a response to the first device. The first device analyzes the response in view of the beacon frame contents actually sent, the respective radio-frequency broadcast power of the beacon frames, and so on. Based on the analysis, the first device may determine proximity or other information regarding the responsive other device.

Many different types of devices use wireless resources to exchange data with each other or to perform various cooperative operations. Methods and apparatus for increasing the security of such wireless functions are continually sought after.
Certain implementations and embodiments will now be described more fully below with reference to the accompanying figures, in which various aspects are shown. However, various aspects may be implemented in many different forms and should not be construed as limited to the implementations set forth herein. Like numbers refer to like elements throughout.

Presence verification within a wireless environment


A fluid channeling device (10) is for a down-hole drill assembly (1) having a central axis (1c) and advanceable into a hole in a downward direction (D) along the axis (1c). The assembly (1) includes a drill member (2) with an inner surface (2a) bounding a central bore (2b) and an outer surface (2c). The channeling system includes at least one passage (12) provided within the drill member (2) so as to extend generally between the drill member inner (2a) and outer surfaces (2c). A generally annular channeling member (14) is disposeable about a portion of the drill member (2) and has at least one inlet port (20), at least one discharge port (16), and a passage (12) extending between the inlet (20) and discharge ports (16). The inlet port (20) is fluidly connectable with the drill member passage (12) to fluidly couple the central bore (2b) with the discharge port (16). The discharge port (16) is configured to direct fluid generally externally of the drill assembly (1) and generally in an upward direction (U) along the axis (1c).

The present invention relates to down-hole drill strings, and more particularly to devices for channeling working fluid within such drill strings.
Many deep-hole drilling applications require large volumes of air to provide ample hole cleaning velocity and "cuttings lift". Proper drill performance necessitate removal of cuttings from a work hole as they are produced by the drill to maintain a "clean" hole and prevent plugging or loss of fluid circulation. While working fluid, such as compressed air, is normally expelled at the bottom of the hole, it is also desirable to expel or discharge fluid at various depths in the work hole where supplemental fluid flow/velocity may be beneficial. However, there are generally limitations as the quantity or volume of fluid that can be circulated with a down-hole drill ("DHD") due to the internal geometry or structure of the DHD. Additionally, drill performance will be negatively affected by excessive internal backpressure that generally results from bypassing flow to create such supplemental flow. Further, most DHD's must be taken apart to make flow adjustments, which is usually a time consuming process that should only be performed by qualified service staff.
Furthermore, commercially available devices commonly referred to as "Jet Subs" are known for providing such desired air flows. However, these devices are rather complex, require incorporation of a separate device into the drill string, and prone to failure and thus generally unreliable. For example, these devices typically include throttle orifices that are protected from back-flow (to prevent debris from entering the clean high pressure air supply) with a spring check valve. Such check valves often break and allow contamination into the drill string.

Entrainment fluid channeling device for a down-hole drill string


This invention relates to nucleic acid-based logic gates. The invention further relates to circuits comprising nucleic acid-based logic gates and methods of performing operations with the gates and circuits provided herein.

Computation with biomolecules provides a basis for manufacturing high-density nano-scale computers. The massive parallel processing potential of such computers makes them ideally suited to solving small-scale NP-complete problems. Further, biomolecular-based computers allow for the embedded control of synthetic control systems and nano-fabrication techniques. Components suitable for use in biomolecular computers are generally compatible with biological environments. Accordingly, biomolecular computers can be used as logic controllers in biological systems generally unsuitable for incorporation of standard silicon-based chips.


A non-aqueous electrolyte secondary battery comprising at least a negative electrode having a current collector provided thereon with convex portions and columnar bodies formed on the convex portions, each of the columnar bodies comprising n stages (where n≧2) of overlaid columnar body portions alternately tilted to different orientations along a longitudinal direction of the current collector, a positive electrode having a positive electrode current collector provided on both surfaces thereof with a positive electrode mixture layer containing a positive electrode active material capable of inserting and extracting lithium ions reversibly, and a separator interposed between the positive electrode and the negative electrode in a confronting manner, wherein tip portions of the columnar body portions at the uppermost stage of the columnar bodies on the negative electrode are tilted toward a trailing end of winding direction.

1. Field of the Invention
The present invention relates to a non-aqueous electrolyte secondary battery of a cylindrical configuration, and more specifically to a negative electrode structure of the same.
2. Background Art
With the advancement in recent years of electronic apparatuses for their portability and cordless operation, secondary batteries such as nickel hydrogen batteries and lithium ion batteries gain attention as driving power sources because they are smaller in size, lighter in weight and higher in energy density.
A typical lithium ion secondary battery comprises a positive electrode made of a complex oxide containing lithium, a negative electrode containing a lithium metal, a lithium alloy or a negative electrode active material capable of inserting and extracting lithium ions, and an electrolyte.
There are also some researches reported in recent years on certain elements having the property of inserting lithium ions and theoretical capacity densities exceeding 833 mAh/cm3 in place of carbon materials such as graphite that have been used conventionally as the negative electrode material. Silicon (Si), tin (Sn) and germanium (Ge) having the property of alloying well with lithium, oxides and alloys of these elements are some examples of the elements used for the negative electrode active material having the theoretical capacity density exceeding 833 mAh/cm3. Of these materials, silicon particles and silicon-containing particles such as silicon oxide particles are studied broadly as less expensive alternatives.
However, any of these materials has such a property that its volume increases when inserting lithium ions. In the case of using a negative electrode having a negative electrode active material composed of Si, for instance, the negative electrode active material changes to a substance symbolized by Li4.4Si under a state of inserting lithium ions to its maximum level, and a ratio of increase in volume of the active material reaches up to 4.12 times.
For the foregoing reason, the negative electrode active material expands and contracts as it inserts and extracts lithium ions. There was thus a possibility that the negative electrode active material separates from the negative electrode current collector due to weakening of adhesion between them over repeated cycles of charging and discharging.
Japanese Patent Unexamined Publication, No. 2005-196970 ("patent document 1") is directed to address the above problem, and it discloses a method of forming a negative electrode, wherein a current collector is provided with convex portions and concave portions on its surface, and a film-like negative electrode material is formed thereon in a tilting orientation with respect to a plane perpendicular to the main surface of the negative electrode material.
According to the patent document 1, the negative electrode material of a pillar shape formed in a tilting angle on the convex portions of the current collector is overlaid with a separator and a positive electrode to make an electrode group, which is then wound to complete the secondary battery of a cylindrical configuration. It indicates that this structure can distribute stresses produced by expansion and contraction of the negative electrode material due to electric charges and discharges into directions of both parallel and perpendicular to the main surface of the negative electrode material, thereby preventing wrinkles and separation from being developed.
However, it is necessary to reduce the size of the electrode group in consideration of anticipated changes in shape of the electrode group so as to fit in the battery case since its diameter increase due to the expansion of the negative electrode active material by insertion of lithium ions. This gives rise to a problem that a space inside the battery case cannot be used effectively, thereby limiting improvement of the battery capacity. Besides, a large stress is developed upon the pillar-shaped negative electrode material due to the expansion of the negative electrode group because the size of the secondary battery is restricted by the dimensions of the battery case. In addition, since the pillar-shaped negative electrode material is connected to the current collector at the convex portions, in particular, the stress is likely to concentrate on the junctions, thereby giving rise to another problem that the pillar-shaped negative material separates from the current collector. There is also another possibility that the current collector wrinkles or deforms even if the negative electrode material remains not separated. There are cases as a consequence that the cycle characteristics and reliability became impaired.

Non-aqueous electrolyte secondary battery


Disclosed is an environmentally friendly near-azeotropic mixed refrigerant, consisting essentially of HFO-1234 yf, HFE-143a and a third component, with the mass percentage of each component being: 70%-98% of HFO-1234yf, 1%-15% of HFE-143a and 1%-15% of the third component. The refrigerant of the present invention is environmentally friendly, excellent in thermodynamic properties, can directly realize drop-in substitution in an original system using HFC-134a without changing any parts, and can be used as a long term alternative to HFC-134a.

1, 1, 1, 2-tetrafluoroethane (HFC-134a), as an alternative to CFC-12, has been widely used with its excellent performance. However, due to its high value of GWP up to 1430, it has been listed in one of the refrigerants with high GWP that are firstly eliminated in "Kyoto Protocol". For HFC-134a used in the small refrigeration equipments, most of them have been substituted by HC-600a, while for the alternative to HFC-134a used in the industrial and commercial refrigeration and air-conditioning in cars, it has become a hot issue to be resolved urgently across the world.
At present, internationally, the main alternatives to HFC-134a are carbon dioxide (CO2), 1, 1-difluoroethane (HFC-152a), 2, 3, 3, 3-tetrafluoropropene (HFO-1234yf), etc. But they have their advantages and disadvantages. CO2 is environmentally friendly and non-combustible, but the system pressure is high, the energy efficiency is low, and the system should be re-designed with high costs. HFC-152a has a high energy efficient and low price of refrigerant, but its flammability is strong and it is necessary to add secondary loop, which causes a high costs. HFO-1234yf has low flammability, small system transformation but its energy inefficient is low and the cooling capacity is low. Therefore, the studies on the alternative to HFC-134a have been continuously carried out in various countries across the world, and mixed refrigerant is a major research field.
In the prior art, Patent Document CN1285699C (200410084844.5) discloses a ternary composition composed of fluoroethane (HFC-161), 1, 1-difluoroethane (HFC-152a) and 1, 1, 1, 2-tetrafluoroethane; CN101671542A (200910018489.4) discloses a mixture composed of 2, 3, 3, 3-tetrafluoropropene (HFO-1234yf), 1, 1-difluoroethane (HFC-152a) and isobutene; CN101864277A (201010196224. 6) discloses a mixture composed of 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf), 1, 1-difluoroethane (HFC-152a) and dimethyl ether (DME); CN102703033A (201210165277.0) discloses a mixture composed of 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf), 1, 1, 1, 2-tetrafluoroethane (HFC-134a) and dimethyl ether (DME); CN102066518A (200980122002. 5) discloses a mixture composed of 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf), 1,1,1,2-tetrafluoroethane (HFC-134a) and 1, 1-difluoroethane (HFC-152a); CN102083935A (200980125796. 0) discloses a mixture composed of 1, 1, 1, 2-tetrafluoroethane (HFC-134a) and 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf). CN102083935A (200980125796. 0) discloses a mixture composed of 1, 1, 1, 2-tetrafluoroethane firing (HFC-134a) and 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf); and CN102712837A (201080038152. 0) discloses a mixture composed of 1, 1, 1, 2-tetrafluoroethane (HFC-134a), 2, 3, 3, 3-tetrafluoropropene (HFC-1234yf) and difluoromethane (HFC-32).
The refrigerant compositions disclosed in the above patents have such drawbacks as high GWP value, strong flammability, high temperature glide, low efficiency, small volume of cooling capacity, unable to be directly filled and used in HFC-134a system, etc. Therefore, it is necessary to develop an alternative refrigerant of HFC-134a with excellent cooling performance, better compatibility with existing systems, and better environmental performance.

Environmentally friendly near-azeotropic mixed refrigerant

ZHEJIANG LANTIAN ENVIRONMENTAL PROTECTION HI-TECH CO., LTD.


The present invention relates to a monitoring system for connection to an air conditioning system. The monitoring system includes a primary monitor for sensing the suction temperature and suction pressure of the air conditioning system along with the air conditioning unit temperature. In addition, the monitoring system includes a remote sensing device that is placed in the structure to monitor and transmit return air temperature and relative humidity to the primary monitor. The collected data is then used to calculate the superheat condition of the air conditioning system which is related to its efficiency.

Air conditioning units are commonplace in many of today's residential and commercial structures. These systems generally employ a conduit filled with a thermally conductive coolant, such as freon, which is subjected to at least two heat exchanges that transfer the heat from inside the structure to the outside. The conduit transfers high pressure, low temperature liquid coolant to an expansion valve wherein the pressure of the coolant is reduced, thereby lowering the temperature of the coolant. This low pressure, low temperature coolant is then directed into an evaporator, which is generally a system of coiled tubes, that act as a heat exchanger. More specifically, the fluid in the evaporator is exposed to warm return air that has been circulated through the structure, thus transferring the heat of a warm return air to the coolant in the evaporator. The now cooled air is directed through the structure, in various ways known in the field, where it will be warmed by the atmosphere into where it has been introduced and subsequently returned to the evaporator. The process of evaporation changes the coolant in the evaporator from a liquid to a vapor. That vapor is directed to a compressor, which operates on the vapor to increase the pressure and temperature thereof. The high temperature, high pressure vapor exiting the compressor is then directed to a condenser that transforms the vaporized coolant into a low temperature liquid. The condenser is much like the evaporator, in that a series of coils are provided to form a heat exchanger. A fan adjacent to the condenser blows ambient air past the high temperature, high pressure vaporized coolant in the coils, thus transferring the heat energy of the various coolant to exhaust air, transforming the vaporized coolant back into a liquid to complete the coolant loop.
The evaporator of the air conditioning system is designed to convert liquid coolant to vapor such that at the exit, or low pressure side of the evaporator contains only vaporized coolant. More specifically, it is desirable to maintain an operating condition wherein the evaporator efficiency changes liquid coolant into vapor such that the temperature at the low pressure end of the evaporator is the saturation temperature of the coolant. As those in the field will appreciate the saturation temperature of the coolant is dependent on various properties of the parts where coolant employed and is generally considered the temperature at which the coolant changes from a vapor to a liquid.
Air conditioning systems often do not operate at peak efficiency. For example, the liquid coolant may be evaporated too quickly, prior to the exit of the evaporator, such that a portion of the evaporator contains superheated coolant vapor. This condition results in a drop in efficiency of the overall air conditioning system since reduced heat transfer occurs between the warm return air and the fluid and/or vapor in the evaporator. Alternatively, if the heat transfer is insufficient to boil all the coolant prior to it reaching the evaporator exit, fluid may be directed into the compressor which is detrimental to its overall operation.
In order to maintain optimum cooling efficiency, technicians are often employed to periodically monitor and maintain air conditioning systems. Efficiency is commonly assessed by monitoring the superheat temperature of the air conditioning unit which, as those in the field appreciate, is equal to the suction temperature of the system minus the saturation suction temperature. The suction temperature is the temperature of the low pressure side of the system, usually but not always measured at the exit of the evaporator. The saturation suction temperature is a function of the pressure at the low pressure end of the evaporator. More specifically, the pressure at the evaporator exit may be monitored, and depending on the type of coolant in the system, the saturation suction temperature may be calculated.
It is considered by those in the field desirable to have an optimum superheat condition in the unit, which is the temperature of the coolant at the low pressure end of the evaporator. If the superheat temperature is too high, the use of the coil is not maximized, wherein the fluid evaporates too quickly and efficient heat transfer is not achieved. Alternatively, if the superheat temperature is too low, the coolant is not efficiently evaporating in the coil and coolant may then be transferred to the compressor, which is detrimental to the components therein. A superheat condition of zero is ideal, since that indicates the suction temperature of the system is equal to the temperature at which the coolant changes from a liquid to a vapor, thus indicating that the liquid coolant was efficiently transferred to vapor coolant at the proper place in the coolant loop. However, one skilled in the art will appreciate that this condition is not easily attained due to inefficiencies of any air conditioning system, such that acceptable superheat ranges for each air conditioning unit are generally used.
Devices of the prior art monitor the suction temperature and the suction pressure of air conditioning systems. They often also monitor other temperatures around the air conditioning coolant loop to assess the efficiency of the system. However, monitors of the prior art are commonly one-piece units such that a technician must make judgments where to place temperature and/or pressure sensors. In addition, a plurality of readings at various locations are usually required. In the prior art, these measurements are taken in series by a technician. This process is both time consuming to the technician and fosters inaccuracies in the superheat calculation, as measurement values may change due to the passage of time during the data collection process.

HVAC monitor and superheat calculator system


A device for inspecting the surface of a disc-shaped recording medium is provided. The inspection device is capable of performing track control unaffected by the widths of the land and the groove in the radial direction of the recording medium in inspecting the entire surface of a data recording region of the recording medium. The device has a spindle motor 1, an optical pickup 2 and a thread motor 3. While an output signal is supplied from a spot size control section 4b within a signal detection unit 4, two sub-beams are radiated from the optical pickup for tracking control. These sub-beams are radiated to the vicinity of the boundary region between the land sandwiched between the grooves where the light volume of the reflected light of the radiated light is minimized.

This invention relates to a device for inspecting a surface of a disc-shaped recording medium, such as an optical disc or a magneto-optical disc, and, above all, that of a mold used for producing the disc-shaped recording medium, such as a metal master or a stamper, in which the recording medium or the mold has lands and grooves. The device is used in an apparatus for producing the disc-shaped recording medium or the mold.
The disc-shaped recording medium, such as a magnetic disc, which is recorded or reproduced using a slide type recording/reproducing head, is required to have a smooth sliding surface in consideration of performance and durability of the recording/reproducing head. Such a disc-shaped recording medium is in need of surface inspection in the course of a manufacturing process thereof for detecting the possible presence of protuberances on the sliding surface on which slides the recording/reproducing head for providing a basis for judgement as to acceptability thereof as to the above-mentioned surface smoothness.
In surface inspection of the disc-shaped recording medium, the conventional practice has been to check the entire slide surface thereof on which slides the recording/reproducing head with the aid of an optical microscope or a picture processing device for detecting the presence of foreign matter. Although a high inspection capability can be achieved with these methods as to the presence of foreign matter, the information along the height of the foreign matter cannot thereby be obtained.
In the field of the optical disc, inspection with the aid of a laser beam is carried out in addition to visual inspection with the aid of an optical microscope. That is, a laser beam from a laser light source on the order of tens to hundreds of micrometers is converged by a laser light optical system on an optical disc surface and spirally swept thereon for inspecting the recording surface of the optical disc. With this method, since the variation in the light volume is averaged depending on the beam spot size, delicate variations in the minute-sized lands or grooves on the reflecting surface cannot be detected.
There has also been known a surface inspection device for inspecting the surface of the disc-shaped recording medium in which a laser spot, converged to a beam size on the order of several micrometers using the laser optical system, is simply swept in a spiral path for achieving the inspection of the entire surface of the recording medium.
If the surface inspection device for the optical disc-shaped recording medium employing the laser beam optical system is applied to a recording medium having grooves formed thereon, the light volume of the reflected light from the disc surface is changed significantly at a time instant the laser spot traverses the groove and the land respectively representing the recess and the protuberance formed on the disc surface, unless the tracking control is in operation. There may be occasions wherein the variation in the light volume from the lands and grooves on the disc surface becomes invisible. The surface inspection device for the disc-shaped recording medium having such grooves as recesses is in need of tracking control for surface inspection, that is, the laser spot has to be controlled so as to follow the land sandwiched between two grooves as the laser spot is caused to sweep the entire disc surface.
As shown in JP Laid Open Patent Publication No. JP-A-61-148636, provisionally published on Jul. 7, 1986, such tracking control is a technique commonly adopted with an optical disc. Such tracking control is now explained by referring to a tracking control circuit applied to a stamper inspection device, as shown in FIG. 1.
In general, a light receiving unit 200 for detecting the light reflected by an optical disc surface has six-segment light receiving elements A to F for receiving the reflected light of a main beam (O'th order light) S.sub.M and two sub-beams (.+-.1st order light). These two sub-beams are made up of a preceding sub-beam (+1st order light) preceding the main beam in its proceeding direction and a follow-up sub-beam (-1st order light) S.sub.-1 positioned following the main beam. These two sub-beams S.sub.+1 and S.sub.-1 are radiated so as to be located on a track inclined by a angle .+-..theta. with respect to a track TR.sub.m, as shown for example in FIG. 2.
For tracking control, the light receiving unit 200 employs detection outputs of the light receiving elements E and F, among the six-segment light receiving elements, which are configured to detect the reflected light from the leading sub-beam and the trailing sub-beam. These detection outputs are fed to a current/voltage converter 201. The current/voltage converter 201 includes current/voltage converting circuits 201e, 201f for conversion. The resulting converted signals are fed to a tracking error signal detection circuit 202.
The tracking error signal detection circuit 202 has an adder 202a and a phase compensation circuit 202b. An output signal of the light receiving element E is additively entered to an input of the addition unit 202a, while an output signal of the light receiving element F is subtractively entered to its other input. A tracking error signal is derived from these input signal inputs. The phase compensation circuit 202b performs phase compensation on the tracking error signal and transmits the phase-compensated signal to a fixed terminal a of a mode changeover switch 203. The phase compensation circuit 202b transmits the tracking error signal to a zero-crossing detection unit 204.
The zero-crossing detection unit 204 has an inverting circuit 204a, two differentiation circuits 204b, 204c and two diodes 204d, 204e. The zero-crossing detection unit 204 routes the tracking error signal from the phase compensation circuit 202b to the inverting circuit 204a and to the differentiating circuit 204c. The inverting circuit 204a inverts the signal level of the tracking error signal and transmits the inverted signal to the differentiating circuit 204b. The differentiating circuits 204d, 204c take out only positive terminal side signals as signals indicating the maximum and minimum positions of the supplied signals and transmit the signals to a jump control circuit 205.
The jump control circuit 205 issues an acceleration pulse for track jumping a laser beam spot radiated from e.g., an optical pickup unit, and subsequently transmits a deceleration pulse to the other fixed terminal b of the mode changeover switch 203. The jump control unit 205 also effects timing control in supplying these various pulse signals.
The mode changeover switch 203 is changed over responsive to a mode changeover signal changing over the tracking control mode to the track jump mode and vice versa. The mode changeover switch 203 issues the signals supplied to its fixed terminals as a tracking control signal.
If, with the above constitution, the tracking error signal is found based upon output signals from various parts, an output signal of the light receiving element E responsive to the leading sub-beam S.sup.+1 as shown in FIG. 3a and an output signal of the light receiving element F responsive to the trailing sub-beam S.sup.-1 as shown in FIG. 3c are outputted as signals 180 out of phase relative to each other. The output signals of the light receiving elements E and F are respectively entered at the adder 202a additively and subtractively for producing a tracking error signal as shown in FIG. 3d.
This tracking error signal is routed to the zero-crossing detection unit 204. The differentiating circuits 204b, 204c of the zero-crossing detection unit 204 differentiate the signal level of the tracking error signal for detecting the peak of the tracking error signal. The peak position of the tracking error signal represents the zero-crossing position of a high frequency (HF) signal obtained on summing the output signals of the four-segment light receiving elements A, B, C and D, as shown in FIG. 3.
In addition, the zero-crossing detection unit 204 supplies a positive polarity pulse signal to the jump control unit 205 as a zero-crossing signal via diodes 204d, 204e. In the jump control circuit 205, the accelerating pulse impression start timing and the decelerating pulse impression start timing for jumping over plural tracks can be accurately produced based upon the supplied pulse signal.
Among disc-shaped recording media, there is such a recording medium in which a convexed portion termed a land has a radial width larger than the laser spot size and a concave portion on the lateral side of the land termed a groove has a radial width substantially equal to the laser spot size, as shown in FIG. 4.
If, with such disc-shaped recording medium, the laser spot traverses a track, the light volume of the reflected light from the disc surface having such lands and grooves is not a repetition of increased light volume and decreased light volume with the reflected light volume from the lands being maximum and the light volume reflected from the grooves being minimum. In effect, the reflected light volume becomes minimum at the land-groove boundary region, and becomes only slightly smaller on the groove than on the land.
The tracking error signal produced on receiving the reflected light from the disc-shaped recording medium is obtained as an irregular waveform signal having a period twice that of the prior-art tracking error signal by setting the land width so as to be unequal to the groove width, such as by setting the land width to groove width ratio to 2:1. If such tracking error signal is employed, it is not possible with the conventional tracking control technique to cause the laser spot to follow the track with sufficiently accuracy.

Device for inspecting the surface of disc-shaped recording medium


The present invention relates to a signal detector, which discerns the presence of signals in a circumscribed area, and a warning is given if a signal is detected. The signal detector adjusts its conditions for the background noise elimination depending on the detected environments in order to discern the presence of signals more efficiently and correctly. Moreover, the present invention shows on a display device the protocol of the detected signal, and enables the user to know the type of the detected signal. Besides, the user can also choose to control the signal detector in a wired or wireless way through the signal connection port, and the user can manually adjust detecting conditions to its environment.

1. Field of the Invention
The present invention relates to a signal detector and more particularly, to a signal detector, which alters its conditions of detection depending on the diversity of the environment.
2. Description of Related Art
In these days, various kinds of high technology products, such as cell phones, digital cameras, and pagers, have become essential in our daily lives. Following the advancement of technology, those high-tech products become smaller and more compact, but new problems have consequently developed.
For example, the cell phone nowadays can display both numerals and characters. With Internet service, a cell phone is able to have transnational and confidential communication, such as on-line chatting, which is hard to trace. If it is put to use in a crime, the investigation will encounter difficulties arising from the telecommunications aspects. Another example of the high-tech product is the pinhole camera, which is designed to be easily hidden and evil people take advantage of that feature. That is, many people's personal lives have been taped for sale or blackmail, which causes a sense of paranoia in the society. The foregoing high-tech products both have to rely on the transmission of signals to obtain information. Therefore, any illegal acts committed by using cell phones and pinhole cameras can be traced by detecting signals therefrom. However, prior art signal detectors are not able to automatically adapt to the environment and thus lack versatility.


An inter-ureter signaling device intended to provide a surgeon with a signal to identify when a ureter is grasped by a surgical clamping device, such as a pair of forceps, the device being comprised of a catheter, a signal generator, and wiring, such that when the catheter component of the device, having been inserted into a ureter, is compressed by the surgical clamping device an electrical circuit is closed and the signal generator generates a human perceptible signal, indicating that the clamp has been placed on the ureter.

Surgeons operating on human patients often experience some difficulty in properly identifying tissue structures. If the wrong tissue structure is cut, the patient may suffer serious or even deadly consequences. This is a significant concern when surgery is performed proximate to the ureters. Because patients often have unique anatomy and because of the similarity in appearance of a ureter with other tissue structures, especially when viewed using laparoscopic instruments, inadvertent ureter dissections occur too frequently. What is therefore needed is a device that can easily and accurately alert the surgeon to the presence of a ureter, even when the ureter is not visually or otherwise identifiable by the surgeon.


The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.

One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage or current or charge can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. Furthermore, as the arrays are scaled to smaller and smaller geometries, the semiconductor structure can become a limiting factor in that the layers of semiconducting material must be kept thick enough to control reverse leakage currents; however, to further reduce the scale of the devices the thickness may also have to be reduced to facilitate such scaling.
In a diode array storage device, a bit is addressed by selecting one row through the array and one column through the array whereby said selected row and column intersect at said bit. If the rows are the array dimension to which the storage diode anodes are connected and the columns are the other array dimension to which the storage diode cathodes are connected, selection of a row is accomplished by applying a high voltage and selection of a column is accomplished by selecting a low voltage such that the diode at the point of intersection of the selected row and the selected column is forward biased. The non-selected rows and columns would have a voltage present such that a diode at the intersection of a non-selected row and a non-selected column would see a zero, a reverse, or a very small forward bias; the source of the non-selected rows and columns typically is high impedance or floating so as not to induce or enable significant leakage currents. The binary state of the addressed bit is determined by the presence or absence of a current path—if a low impedance current path is present it represents one logic state and if it is not (either no current path or a high impedance current path) the other logic state is represented. The bit is read at an output by either measuring the current flowing into the selected row line, column line or both (or into the entire array or a portion of the array) or by measuring the voltage on the selected row line, column line, or both or by extracting and measuring the charge remaining on the selected row line, column line, or both. In the case of the current measurement, a larger current reading would indicate the presence of a non-linear conductor at the addressed location. In the case of the voltage measurement, a convergence of the voltages applied to the selected row and selected column would indicate the presence of a non-linear conductor at the addressed location, and in the case of charge extraction, smaller remaining charge would indicate the presence of a non-linear conductor at the addressed location.
It must be noted that the selected row will typically have many diodes connected whose addressing is not intended and these diodes will often experience a slight forward bias and source a slight forward current to the non-selected columns. Likewise, the selected column will typically have many diodes connected whose addressing is not intended and these diodes will often experience a slight forward bias and sink a slight forward current from the non-selected rows. The extent of this current will be determined by the current paths existing within the array as a result of cumulative leakage currents of the many reverse biased diodes connecting the non-selected rows and non-selected columns. To minimize leakage, these diodes are typically made having multiple layers of semiconducting materials wherein some layers are made thicker to extend the depletion region of the device junction to reduce leakage currents. When the array is small, the cumulative leakage current is not a problem. But, when the array is very large, the cumulative leakage current can become great enough that the currents flowing in the non-addressed diodes on the selected row and selected column can become comparable to the current that would flow in an addressed diode if one is present. Since the current leaked in this manner is a function of the data stored in the array and the amount of leakage when reading any given bit can be different, it can be difficult to predict or compensate for this leakage. This makes it difficult or impossible to determine the cause of the current path and, consequently, the binary state of the addressed bit when the cumulative leakage current becomes too large. In many cases, the array can be divided into sub-arrays, but as the individual sub-arrays become large the problem returns.

Nano-vacuum-tubes and their application in storage devices


In a system for controlling a general-purpose air-cooled internal combustion engine having two cylinders each equipped with a throttle valve and a fuel injector, and a cooling fan that selectively directs air onto the cylinders, a throttle driver selectively drives the respective throttle valve of each cylinder to open or close. The system also includes an injector driver that selectively drives the respective injector of each cylinder to open, and a controller that controls operation of the throttle driver and injector driver in such a way that the throttle opening and an amount of fuel to be injected are different for each cylinder, such that an engine speed becomes substantially constant, thereby enabling the engine to obtain desired output characteristics.

1. Field of the Invention
This invention relates to a control system for controlling a general-purpose internal combustion engine, particularly to a control system for a general-purpose internal combustion engine of forced-air-cooled type that sucks in air through a cooling fan and selectively directs the air for cooling the engine.
2. Description of the Related Art
Among general-purpose engines used as prime movers in electric generators, agricultural machines and various other applications, in recent years, there is proposed a general-purpose engine equipped with a plurality of cylinders such as, e.g., two cylinders, each having a throttle valve for opening and closing air an intake path, and an injector for injecting fuel for the cylinder, as taught, for example, in Japanese Laid-Open Patent Application No. 2002-349384.
General-purpose engines, including the engine disclosed in the prior art mentioned above, are generally air-cooled. However, engines which produce a large amount of output, are often configured to forcibly air-cool by blowing or emitting air sucked in through a fan for cooling. Since the structure of this type of engines results in differences of cooling effect among the cylinders, they are disadvantageously difficult to control in a manner so as to perform desired output characteristics.

Control system for general-purpose engine