A decorated ceramic floor tile is disclosed, comprising a clay tile substrate, an initial glaze layer applied to the tile substrate, and a high-fired glazed decal image applied to the tile such that the decal extends substantially at least to the edges of the initial glaze layer around the entire perimeter of the tile substrate. A ceramic floor having a substantially continuous decorative image thereon, comprising a plurality of ceramic floor tiles of the invention also is disclosed. A process for making floor tiles of the invention includes providing a clay tile substrate, bisquing the clay substrate to remove moisture from the clay, applying an initial glaze layer to the bisqued clay tile substrate, performing a first firing of the glazed tile substrate, applying a glazed decal image to the fired glazed tile such that the decal extends substantially at least to the edges of the initial glaze layer, and performing a second firing of the decaled tile such that the decal image is substantially fully bled to the periphery of the tile around the entire perimeter of the tile.

Ceramics have been long used as the substrate for making tiles that may be used in a variety of environments, including wall tiles and floor tiles. The ceramic material composition, its method of manufacture, and its physical and mechanical properties typically will vary depending on the environment and circumstances in which the tile is employed.
Ceramic tiles conventionally have been manufactured by firing a clay material in a kiln to vitrify the clay. Ceramic tiles often are glazed to provide water, frost, chemical and abrasion resistance. Glaze compositions typically are applied to prefired clay which has been subjected to a bisquing process designed to remove moisture from the clay and solidify it somewhat. At the point of firing, the glazes become vitrified and inert, fusing with the ceramic surface to form a substantially single molecular structure.
Although floor tile and wall tile often share some characteristics, such as resistance to water, moisture, and mild chemical agents, they typically differ fundamentally in important characteristics. For example, wall tile may typically be more porous (which permits better adherence to wall substrates) and much less resistant to abrasion than floor tile. In particular, floor tiles need to resist abrasion due to traffic or wheeling of loads and have adequate resistance to skidding, that is, to meet certain coefficient of friction (COF) conditions. In contrast, wall tiles are not required to withstand excessive impact and are not normally subject to freezing and th awing cycles, unless used in an outdoor environment.
Wall tiles may be prepared by firing clay or a mixture of clay and other ceramic materials to produce a relatively thin body that may be either glazed or unglazed. The glaze is a fused facial finish composed of ceramic materials that is usually a vitreous covering that is practically impervious after firing. In some cases, the glaze may be non-vitreous or semi-vitreous. Single-fired glazed tiles are tiles that are glazed before firing. Double-fired glazed tiles may be obtained by firing an unglazed tile substrate, coating the fired tile with glaze and then firing a second time. Double-fired tiles are generally superior in terms of glaze quality and finish. The properties of the glaze composition itself provide the surface sealing, water resistance, etc. To decorate the wall tile, the glaze can be pigmented prior to firing so that the pigmented, fused glaze resulting from the second firing is incorporated onto the surface appearance of the tile.
Alternatively, glazed ceramic tiles can be decorated indirectly through the use of a ceramic decal. Ceramic decals for wall tiles are produced using an overglaze index of colors, that is, a "palette", independently from the actual initial glazing of the tile. To make the decal, an overglaze palette is used in the screening an image onto decal paper for later transfer to the vitrified glazed wall tile. The overglaze is fired onto the tile upon a second firing of the tile. The term overglaze refers to the characteristic of the overglaze to actually sit "on top of" or "over" the substrate glaze.
Overglazing of ceramic wall tiles may be accomplished under low-fire conditions, for example, at temperatures as low as 750-850.degree. C. Such overglazed ceramic tile should resist the normal demands of wall tile, such as resistance to water, moisture, cleaning agents, mild acids, and fading through ultraviolet light exposure is concerned. However, such tiles will not adequately resist the demands of traffic abrasion experienced in floor applications. Since floor traffic would quickly abrade the surface and deteriorate the finish of such overglazed tiles, they are unsuitable for use as floor tiles. Overglaze colors are designed to be produced using specific firing conditions. In particular, in order for the actual colors to mature properly they must be prepared using exact firing temperatures. Secondly, the characteristic to rest above or "over" the glaze, tends to make overglazes prime candidates for surface abrasion if introduced into a floor context. By contrast, in glaze colors sink "into" the substrate glaze by creating a union with the glaze itself. Once they are fired into the glaze, the in glaze colors are enhanced by the hardness of floor tile glazes which are much harder due to their formulation.
Floor tiles conventionally have been made by employing a high-fire glaze. That is, after subjecting the clay to a bisquing process to remove moisture, a high-fire glaze composition is applied to the tile surface, and the tile may then be fired in a kiln at temperatures of about 1000-1280.degree. C. for about 45 to about 120 minutes. The actual firing temperature and duration of firing may vary depending on the unique compositions that are specific to each manufacturer. The glaze compositions are designed to withstand such high-firing conditions so as to render a vitrified product after a single firing. The high-firing conditions create a product having the increased resistance to abrasion required for floor tile applications.
Ceramic floor tile conventionally has been decorated using a direct screen method in which the screened material is applied directly to the unfired, glazed clay bisque. In direct screen printing, an image is generally produced using a coarse line screen of about 65 to 85 wherein a decorative stencil is placed over the glazed clay bisque. Ceramic dyes/inks or colored glaze are then applied through the open parts of the screen to the clay using a roller or squeegee. A first firing is then carried out to glaze the decorated clay.
A significant limitation of the direct screen process is that it cannot be wrapped around contoured surfaces but is limited to screening images only on flat surfaces. Conventional ceramic floor tile substrates are "cushioned", that is, provided with rounded edges. Thus, a direct screen decoration of floor tiles cannot fully decorate the entire tile surface since screening does not wrap around the cushioned edges. This is a significant disadvantage since when a plurality of floor tiles are joined to create a floor surface, there will be a discontinuity in the decorative pattern around the edge of each tile. Thus, a true full field image on the floor is not feasible with conventional ceramic floor tiles. In addition, a decal would be unsuitable for application to the clay bisque since a water-soluble decal cannot be attached to a water-soluble pre-fired glaze without the decal losing its definition. Also the decal would destroy the integrity of the unfired glaze. The unfired glaze tile is highly fragile and easily contaminated and damaged upon handling. In addition, the decal cannot be positioned on the tile properly in such a situation.

Glazed ceramic floor tile having high-resolution image


A filter configured to photocatalytically oxidize target compounds in an air stream includes a support structure having an air permeability greater than approximately 155 CFM/ft2 and a photocatalyst supported by the support medium.

It has been demonstrated that photocatalytic oxidation can effectively degrade compounds in a fluid stream (U.S. Pat. No. 5,766,455). It has further been demonstrated that when a semiconductor catalyst utilized in such a photocatalytic oxidation reactor is metalized in situ the overall performance of the process can be significantly enhanced in the degradation of certain compounds (U.S. Pat. No. 5,834,069).
One of the limiting factors of the photocatalytic oxidation reactor described in U.S. Pat. No. 5,766,455 is that media used to support the semiconductor catalyst comprise a plurality of densely-packed fibers. While air can pass through such a densely-packed medium, the volume of air passable through it can limit the economic viability of the reactor. High pressure drops caused by densely-packed media require significantly high levels of energy to drive air through the media. Such high pressure drops can make photocatalytic oxidation reactors that utilize densely-packed media economically impractical.

Photocatalytic oxidation media and system


A tire assembly with integrated power generation features includes one or more piezoelectric devices and power conditioning modules. Piezoelectric devices may include a plurality of piezoelectric fibers embedded in a generally unidirectional fashion within an epoxy matrix, a piezoceramic wafer provided on a substrate and substantially surrounded by a protective casing, or a piezoceramic unimorph structure adhered with a thermoplastic polyimide to respective top and bottom conductive layers. Each piezoelectric device may include multiple piezoelectric elements connected in series and/or parallel arrangements, configured with respective poling directions in opposing or in-phase arrangements and/or configured in d33 or d31 displacement modes. Piezoelectric devices are preferably mounted within a tire or wheel assembly such that electric charge is generated therein as the wheel assembly moves along a ground surface and is subsequently stored in one or more energy storage devices. Stored energy may then be used to power electronics such as a tire monitoring system that wirelessly transmits such information as tire pressure, temperature and identification variables to a remote receiver location.

The incorporation of electronic devices with pneumatic tire structures yields many practical advantages. Tire electronics may include sensors and other components for obtaining information regarding various physical parameters of a tire, such as temperature, pressure, number of tire revolutions, vehicle speed, etc. Such performance information may become useful in tire monitoring and warning systems, and may even potentially be employed with feedback systems to regulate proper tire pressure levels.
U.S. Pat. No. 5,749,984 (Frey et al.) discloses a tire monitoring system and method that is capable of determining such information as tire deflection, tire speed, and number of tire revolutions. Another example of a tire electronics system can be found in U.S. Pat. No. 4,510,484 (Snyder), which concerns an abnormal tire condition warning system. U.S. Pat. No. 4,862,486 (Wing et al.) also relates to tire electronics, and more particularly discloses an exemplary revolution counter for use in conjunction with automotive and truck tires.
Yet another potential capability offered by electronics systems integrated with tire structures corresponds to asset tracking and performance characterization for commercial vehicular applications. Commercial truck fleets, aviation crafts and earthmover/mining vehicles are all viable industries that could utilize the benefits of tire electronic systems and related information transmission. Tire sensors can determine the distance each tire in a vehicle has traveled and thus aid in maintenance planning for such commercial systems. Vehicle location and performance can be optimized for more expensive applications such as those concerning earth mining equipment. Entire fleets of vehicles could be tracked using RF tag transmission, exemplary aspects of which are disclosed in U.S. Pat. No. 5,457,447 (Ghaem et al.).
Such integrated tire electronics systems have conventionally been powered by a variety of techniques and different power generation systems. Examples of mechanical features for generating energy from tire movement are disclosed in U.S. Pat. No. 4,061,200 (Thompson) and U.S. Pat. No. 3,760,351 (Thomas). Such examples provide bulky complex systems that are generally not preferred for incorporation with modern tire applications.
Some tire electronics systems have been powered by various piezoelectric devices. U.S. Pat. No. 6,438,193 (Ko et al.) discloses a self-powered tire revolution counter that includes a piezoelectric element mounted in a tire in a manner so as to be subjected to periodic mechanical stresses as the tire rotates and to provide periodic pulses in response thereto. Yet another example of piezoelectric devices used for powering tire electronics systems is disclosed in U.S. Pat. No. 4,510,484 (Snyder), which concerns a piezoelectric reed power supply symmetrically configured about a radiating center line of a tire.
Another typical solution for powering tire electronics systems corresponds to the use of a non-rechargeable battery, which inherently provides an inconvenience to the tire user since proper electronics system operation is dependent on periodic battery replacement. Conventional batteries also often contain heavy metals that are not environmentally friendly and which present disposal concerns, especially when employed in highly numerous quantities. Still further, batteries tend to deplete their energy storage quite rapidly when powering electronic applications characterized by complex levels of functionality. Battery storage depletion is especially prevalent in electronic systems that transmit information over a relatively far distance such as from truck wheel locations to a receiver in the truck cabin. Even when batteries are used in electronics systems that transmit from wheel locations to a closer receiver location, information is then typically relayed via hard-wire transmission medium from the RF receiver location to the vehicle cab thus requiring the installation of additional and often expensive communications hardware in a vehicle.
Yet another known method for deriving power for tire monitoring systems relates to scavenging RF beam power with an interrogation antenna in close proximity to a tire and integrated electronic features. Energy that is radiated from the antenna is scavenged to power the electronics, which must often be very specialized ultra-low-power electronics limited to within a few microwatts. Interrogation antennas employed in conjunction with beam-powered electronics must typically be placed in relatively close proximity (within about two feet) to each wheel well due to limited transmission ranges. This typically requires multiple interrogation antennas per vehicle, thus adding to potential equipment costs. Each antenna is also quite susceptible to damage from road hazards, and thus for many reasons may not be the most desirable solution for powering certain tire electronic applications.
The disclosures of all of the foregoing United States patents are hereby fully incorporated into this application for all purposes by reference thereto. While various tire electronics systems and power generation systems therefor have been developed, no design has emerged that generally encompasses all of the desired characteristics as hereafter presented in accordance with the subject technology.

System and method for generating electric power from a rotating tire's mechanical energy


A system for verifying intent in a card not present transaction is provided. The system includes a late binding token that is distributable to consumers without necessarily being bound to an account. The system also includes a client software that locates a token server configured to facilitate managing and communicating with the late binding token. The system also includes a protocol concerning how to build a verifiably secure structured proposal that carries an offer to the consumer through the client software.

Consumers use credit cards, debit cards, and other cards to make purchases. Increasingly, consumers use these cards in electronic commerce conducted, for example, over the Internet. But conventional credit cards are not ideally suited for transactions where the card is not present at the merchant's site. Thus, "smart cards" or integrated circuit cards are growing in popularity.
An integrated circuit card (IC) has, for example, a processor, a data input/output port controlled by the processor to receive and output data, a random access memory (RAM), a read only memory (ROM), and a programmable data memory (e.g., EEPROM, FLASH). IC cards are available from various sources and in several configurations. IC cards can store information and thus can simplify electronic transactions. Confidential information like private keys can be maintained in a private storage area while non-confidential information, like a card identification number, can be stored in a public storage area. Thus, an electronic transaction may rely on both public and private data. The processor can be configured to access both the public and private storage areas. The private storage may only be accessible after the processor has verified a password (e.g., personal identification number (PIN)). Even though IC cards can simplify and improve electronic transactions, they can also introduce security and verifiability of intent problems into electronic transactions, especially "card not present" transactions.
Numerous patents describe various computerized systems for conducting electronic transactions in multiple different environments. For example, U.S. Pat. No. 6,038,551, filed Mar. 11, 1996 and issued Mar. 14, 2000, concerns a system supporting computer implemented applications that access and manage a multi-purpose integrated circuit card. The '551 patent even discloses employing public and private keys with a smart card. However, the '551 patent, and others like it, typically bind the smart card to accounts, applications, and so on at an early time in the life cycle of the card, which limits the use of this type of IC card.
U.S. Pat. No. 6,044,349, filed Jun. 19, 1998, and issued Mar. 28, 2000, describes a portable storage medium that stores data and provides access to information from an information dissemination system. The storage medium is a smart card (e.g., IC card) that stores information like a customer name, a customer address, and various customer account data. The '349 patent describes a smart card as a small electronic device containing a re-writable memory and additional integrated circuitry. These types of smart cards typically have data downloaded to the card (e.g., a debit amount) and have that downloaded data manipulated by various applications. These types of smart cards, while potentially more secure than cash, may not provide assurances adequate to carry out a card not present transaction across an insecure medium like the Internet.
Smart cards are well known in the art. For example, U.S. Pat. No. 6,005,942, filed Mar. 24, 1998, and issued Dec. 21, 1999, describes a system that allows smart card users to securely add applications to the card during the lifetime of the card after the card has been issued. The smart cards in the '942 patent are typically credit card sized plastic cards holding a semiconductor chip that can support multiple applications. The smart card interfaces with external devices (e.g., ATMs, computers, vending machines). The semiconductor chip embedded in the smart card facilitates performing computational operations like encryption and decision making. One example of a smart card implemented as a "processor card" is illustrated in Prior Art FIG. 1. It is to be appreciated that a smart card can be implemented in various ways and programmed with various functionalities. In some embodiments, smart card 10 has a microcontroller 20 that includes a microprocessor 30, RAM 40, ROM 50, non-volatile memory 60, a cryptographic module 70, and a card reader interface 80. Other standard features of a microcontroller like a clock, a random number generator, control logic and so on may be present but are not illustrated.
Microprocessor 30 can be any of various central processing units that execute commands and control the device. RAM 40 can store calculated results and perform other typical RAM functions. ROM 50 can store fixed data, standard routines, and other typical ROM memory items. Non-volatile memory 60 (e.g., electronically programmable ROM (EPROM)) stores persistent information that should be maintained even when the card is not connected to a power source. This information includes, but is not limited to, a card identification number, a personal identification number, and so on. Cryptographic module 70 is an example of an optional hardware module on typical smart cards that performs a variety of cryptographic algorithms. Card reader interface 80 includes hardware and software that facilitates the smart card communicating with devices external to the smart card. Thus, the internal architecture of a smart card is well known.
The '942 patent describes a smart card being initialized with data placed on the card before the card is issued to a card user. This data can include data common to a large number of cards and a minimal amount of card unique terms like a serial number and personalization keys. The '942 patent then describes overcoming a limitation of conventional smart cards through the ability to add applications to traditional smart cards. While adding an application to a smart card after issuance increases the usefulness of the smart card, it may not facilitate using the smart card in card not present transactions in a way that provides adequate assurances that an offer was presented correctly, accepted in a verifiable manner, and transmitted securely to the offer or and/or other third party verifiers.
Other patents, for example, U.S. Pat. No. 5,781,723, filed Jun. 3, 1996, and issued Jul. 14, 1998, concern a smart card storing information that facilitates the smart card identifying itself to other computing units. The '723 patent describes a smart card architecture that enables a smart card to identify its type and properties to computing units with which it communicates. This communication may involve interacting with a certificate authority. However, the '723 patent, like the other patents described herein, does not describe and/or suggest functionality in a smart card that facilitates producing a level of trust in a transaction adequate to support verifiably trustworthy card not present transactions.
Some patents have attempted to address security concerns in card not present transactions. For example, U.S. Pat. No. 5,590,197, filed Apr. 4, 1995, and issued Dec. 31, 1996, concerns an electronic payment system and method that stores sensitive account information and public/private key processing. In a conventional point of sale credit transaction, a consumer physically presents their credit card to a merchant. The merchant can then verify the authentication information (e.g., signature, photograph, fingerprint, card verification numbers). The merchant can also transmit card information to a credit card servicer for authorization. Thus, the security of the parties involved in the transaction (e.g., authorized card owner, merchant, credit card account company) depends on the merchant authenticating the card, the merchant protecting sensitive account information, the credit card servicer protecting sensitive information, and so on. In this conventional model, much sensitive information is transmitted across an insecure network like the Internet. Furthermore, in this conventional type of transaction, the consumer credit card was likely bound to a credit card account at the credit card servicer very early in the life cycle of the card. Thus, this conventional point of sale credit transaction includes significant risks for all parties involved in the transaction. These risks are exacerbated in a card not present transaction, like when a consumer purchases an item across the Internet from their home computer. The merchant cannot authenticate the card by comparing signatures or fingerprints, and an additional transmission of sensitive information is made from the consumer's computer to the merchant's computer. Financial institutions may be reluctant to accept risk of fraud loss in card not present transactions, so the merchant typically must bear greater risk.
Thus, although numerous patents and products have attempted to address problems associated with insecure card not present transactions, improvements can still be made.


JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

1. Field of the Invention
The present invention relates to the field of semiconductor devices. More specifically, the field of the present invention is directed to junction field effect transistors (JFETS) and MESFETS for use in low voltage, high frequency and high current applications.
2. Related Art
The semiconductor industry faces difficult challenges in satisfying the expanding needs to provide transistors that are suitable for power management with low voltage applications, e.g., below 3 volts. As the feature size of the integrated circuits (ICs) become ever smaller and electronic devices are continuously being miniaturized, the voltages from AC or DC power sources that provide power to these devices are further dropped. Dropping the voltage from five volts to three volts results in a 25 percent reduction in power if the current density is maintained unchanged. At 1.8 volts, the power drops another 60%. However, the transient current loads can be very high. Under such operating conditions, 0.9 volts is the normal forward voltage drop for a p-n junction typically employed in a rectifier. Unfortunately, most of the power is consumed in the rectifying process. Therefore, power supply systems built with such types of p-n junctions are not really suitable for low voltage applications. Even the Schottky barrier diodes with a forward voltage drop below 0.5 volts are not a suitable solution to provide rectifiers or power switching devices for operation under the low voltage conditions.
Junction field effect transistors (JFETs) were developed after the invention of the bipolar transistors. A JFET transistor can be operated at very high frequencies with high switching speeds because the JFET transistor is operated with majority carriers. The depletion mode JFET transistor is well known and employed commonly in a naturally on state when the gate bias is zero. Because of the naturally on state, the JFET transistors are not as widely used in the semiconductor industry as the MOSFET, e.g., the metal oxide semiconductor field effect transistors. In order to make the JFET transistor operate in a naturally off state, the distance between the gates has to be reduced for the depletion regions from the gate to shut off the current conducting paths. However, such naturally off JFET transistors are not very useful in conventional configurations due to the longer current channel thus limiting the current capacity with a high on-resistance. S. M. Sze in "Physics of Semiconductor Devices" disclosed one example of such a configuration (Wiley & Son, 1981 Second Edition, page 322). The normally off JFET transistors discussed by Sze are for high speed low power applications. The long current channel and high-on resistance limit the usefulness of JFET transistors particularly the high on-resistance prevents such transistors for use in applications in modern electronic devices operated with extremely low voltages.
FIG. 1 illustrates a conventional JFET structure 10 having a drain (D) region 16 and an source (S) region 14 which are implemented as wells within a substrate 12. The gate (G) region 18 is also shown. A problem with this conventional JFET structure 10 is that it has a very long channel length thereby creating a large channel resistance. Further, the structure 10 consumes a large substrate surface area because the device 10 is substantially horizontal in orientation with respect to the surface of the substrate. Moreover, the drain 16 and source 14 contacts consume a relatively large amount of space on the substrate 12. Further, gate diffusion is very difficult to control in the JFET structure 10 meaning that the threshold voltage, Vt, is difficult to control.
Moreover, in U.S. Pat. No. 4,523,111 entitled "Normally-Off Gate-Controlled Electric Circuit with Low On-Resistance", Baliga disclosed a JFET serially connected to an IGFET. The gate of the IGFET is operated as the gate for the serially connected circuit. The gate of the IGFET is applied to block the current to flow through a normally on JFET until the IGFET is turned on with a positively biased voltage above an IGFET threshold voltage. The on-resistance is the sum of the JFET resistance and the IGFET resistance. The on-resistance would not be adequate for extremely-low voltage applications required by modern electronic devices as discussed above. A similar invention is disclosed in U.S. Pat. No. 4,645,957 that is entitled "Normally Off Semiconductor Device with Low On-Resistance and Circuit Analogue" by Baliga. The JFET transistor is serially connected to a bipolar transistor to achieve the normally off state. Again, the on-resistance is the sum of the bipolar resistance and the JFET resistance and becomes too high for extremely low voltage applications.
In U.S. Pat. No. 5,321,283 entitled "High Frequency JFET" Cogan et al. disclose a JFET for radio frequency (RF) operation at high frequency. The normally-on JFET transistors disclosed in this patent are operated with high voltage and therefore they are not suitable to satisfy the requirements of modern portable electronic devices that require extremely low voltage and relatively high current capacity. Similarly, in U.S. Pat. No. 5,618,688 entitled "Method of Forming a Monolithic Semiconductor Integrated Circuit having an N-Channel JFET," Ruess et al. disclose a normally on JFET transistor manufactured with BiCMOS processes. The JFET transistors disclosed in this patent are not suitable for low voltage and high current applications.
Therefore, a need exits in the art of design and manufacture of a transistor suitable for low voltage, high current and high frequency applications and a fabrication process that would address the above difficulties.

JFET and MESFET structures for low voltage, high current and high frequency applications


A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Automated test equipment (ATE) can be any testing assembly that performs a test on a device, semiconductor wafer or die, etc. ATE assemblies may be used to execute automated tests that quickly perform measurements and generate test results that can then be analyzed. An ATE assembly may be anything from a computer system coupled to a meter, to a complicated automated test assembly that may include a custom, dedicated computer control system and many different test instruments that are capable of automatically testing electronics parts and/or semiconductor. Automatic Test Equipment (ATE) is commonly used within the field of electrical chip manufacturing. ATE systems both reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
In testing devices or products, e.g. after production, it is crucial to achieve among others a high product quality, an estimation of the device or product performance, a feedback concerning the manufacturing process and finally a high customer contentment. Testing devices, e.g., NAND flash packages requires some type of error capture and analysis. Usually a plurality of tests is performed in order to ensure the correct function of a device or product, commonly referred to as a device under test ("DUT") in testing parlance. The plurality of tests is typically part of a test plan or test program that is loaded into the ATE system by the user. The test plan acts as a blueprint for running the tests on the DUTs.
Conventional ATE solutions for testing DUTs are limited because the test program controllers control tester resources in a fixed way, with fixed synchronization mechanisms between them. Conventional ATE solutions, for example, do not allow for flexibility in assigning hardware units to DUTs, and furthermore, do not allow for flexibility in keeping the hardware units synchronized between each other. This inflexibility in assigning hardware units to a DUT and keeping them synchronized in a flexible fashion results in a lack of efficient use of tester resources.


A foldable mat is provided. The foldable mat may move from a usable First Position A to a condensed Second Position B. The foldable mat has a plurality of grommets. The grommets are located along the four corners of the mat. The front and the back of the mat have a plurality of protrusions which extend outward and cover substantially the entire top and bottom surface of the mat. A first crease lacking the protrusions extends along the center of the mat parallel to the side of the foldable mat and a second crease lacking the protrusion extends along the center of the mat substantially perpendicular with respect to the first crease. The mat may be folded into a Second Position B and a fastener may secure the foldable mat in the Second Position B by securing the grommets together.

A foldable mat is provided. The mat is especially suitable for use by skiers, mountain bikers, campers, golfers and beach-goers. The foldable mat may move from a usable First Position A to a condensed Second Position B. The foldable mat has a plurality of grommets. In an embodiment, four grommets are located on the mat and provide an opening passageway between the top of the mat and the bottom of the mat. The four grommets are located along the four corners of the mat. The front and the back of the mat have a plurality of protrusions which extend outward and cover substantially the entire top and bottom surface of the mat. A first crease lacking the protrusions extends along the center of the mat parallel to the side of the foldable mat and a second crease lacking the protrusion extends along the center of the mat substantially perpendicular with respect to the first crease. The mat may be folded into a Second Position B and a fastener may secure the foldable mat in the Second Position B by securing the grommets together.
Foldable mats are well known. For example, U.S. Pat. No. 6,578,022 to Devine discloses a foldable, portable, magnetic tool mat. The tool mat includes generally rectangular obverse and reverse panels each formed of flexible material and connected together along substantially common side and end margins and along evenly spaced apart seam lines extending between said side margins defining elongated magnet bar holding portions. An elongated permanent magnet bar is held within each holding portion each without substantially inhibiting selective tool mat folding for fit and storage. The reverse panel is substantially thicker than the obverse panel for better wear characteristics and maximal magnetic attractive forces for tool and hardware retention. An attaching strap holds the tool mat.
Further, U.S. Pat. No. 7,188,713 to Espar discloses a mat/carrier foldable between a substantially flat configuration and a storage configuration. The mat/carrier comprises a mat/carrier component having a base panel, a plurality of side panels, and at least one intermediate panel intermediate adjacent side panels. A first set of folds separates each panel from its adjacent panels to facilitate re-orientation of each panel relative to its adjacent panels so as to form a container configuration. A second set of folds in at least some of the panels facilitate at least partial collapsing of the mat/carrier component from the container configuration to a smaller container configuration.
Still further, U.S. Pat. No. 6,752,773 to Leung discloses a foldable bubbling bath mat having two or more interconnected segments and a number of air channels with two or more apertures located in a bottom surface of the air channels. The bubbling bath mat is adapted to produce varying sized air bubbles and, thus, improve the overall therapeutic massaging effect on a user.
However, these patents fail to provide a foldable mat which is suitable for use on, for example, a snow mountain by winter sports enthusiasts. A need therefore exists for a foldable mat which has the features of the present foldable mat. Further, a need exists for a foldable mat which may be easily cleaned, folded and transported.


An electret filter media that includes a thermoplastic resin and a compound of the formula Y2-A(R1)n—Y1, where A is benzene, naphthalene or anthracene, Y1 and Y2 are each independently R2-R3, R2 is an ester linking group or an amide linking group, R3 is an alkyl group having from 10 to 22 carbon atoms, R1 is R2-R3 where R2 and R3 are each independently as defined above, and when A is benzene, n is from 0 to 4, when A is naphthalene, n is from 0 to 6, and when A is anthracene, n is from 0 to 8.

The invention relates to preparing electrets and to enhancing release properties of thermoplastic films using resin additives.
The filtration properties of nonwoven polymeric fibrous webs can be improved by transforming the web into an electret, i.e., a dielectric material exhibiting a quasi-permanent electrical charge. Electrets are effective in enhancing particle capture in aerosol filters. Electrets are useful in a variety of devices including, e.g., air filters, face masks, and respirators, and as electrostatic elements in electro-acoustic devices such as microphones, headphones, and electrostatic recorders.
Electrets are currently produced by a variety of methods including direct current ("DC") corona charging (see, e.g., U.S. Pat. Re. 30,782 (van Turnhout)), and hydrocharging (see, e.g., U.S. Pat. No. 5,496,507 (Angadjivand et al.)), and can be improved by incorporating fluorochemicals into the melt used to produce the fibers of some electrets (see, e.g., U.S. Pat. No. 5,025,052 (Crater et al.)) and by plasma fluorinating (see, e.g., U.S. Pat. No. 6,397,458 (Jones et al.)).
Many of the particles and contaminants with which electret filters come into contact interfere with the filtering capabilities of the webs. Liquid aerosols, for example, particularly oily aerosols, tend to cause electret filters to lose their electret enhanced filtering efficiency (see, e.g., U.S. Pat. No. 5,411,576 (Jones et al.)). In addition, heat and aging can impair the filter efficiency of some electret filters.
Numerous approaches have been developed to compensate for loss of filtering efficiency of an electret filter. One method for improving an electret filter's efficiency includes increasing the amount of the nonwoven polymeric web in the electret filter by adding layers of web or increasing the thickness of the electret filter. The additional web, however, increases the breathing resistance of the electret filter, adds weight and bulk to the electret filter, and increases the cost of the electret filter.
Another method for improving an electret filter's resistance to oily aerosols includes forming the electret filter from resins that include melt processable fluorochemical additives such as fluorochemical oxazolidinones, fluorochemical piperazines, and perfluorinated alkanes (see, e.g., U.S. Pat. No. 5,025,052 (Crater et al.)), perfluorinated moieties. The fluorochemicals are melt processable, i.e., suffer substantially no degradation under the melt processing conditions used to form the microfibers that are used in the fibrous webs of some electrets (see, e.g., WO 97/07272 (Minnesota Mining and Manufacturing)). Thermally stable organic traizine compounds also have been used to improve charging of an electret filter (see, e.g., U.S. Pat. No. 5,908,598 (Rousseau et al.) and U.S. Pat. No. 6,002,017 (Rousseau et al.)).

Electrets and compounds useful in electrets


A recording/reproducing device includes a laser and a laser drive carried by a pickup having a drive for movement. A control controls the drives to irradiate the recording medium with laser pulse sequences forming recording marks having recording mark lengths between a predetermined and maximum lengths, a top section, a last section including a cooling period, and an intermediate period. Heat of mark front edges is controlled by recording parameters for top sections that are classified according to recording mark lengths and recording parameters of the first through the maximum recording mark lengths are classified into a same group. Heat of mark rear edges is controlled by cooling start positions for cooling periods classified according to recording mark lengths. Cooling start positions for a second predetermined mark length through the maximum mark length are classified into a same group. The second mark length is longer than the first mark length.

Recording/reproducing devices for an information recording medium (such as an optical disc) which stores large amount of data have conventionally adopted an art which records information by focusing a laser beam onto an information recording medium and heating the information recording medium, so as to change physical characteristics of the medium. According to the art, binary digital data is recorded on the information recording medium. The binary digital data is expressed by (i) two states including a state where a recording mark is formed on the information recording medium (hereafter, referred to as "mark") and a state where a recording mark is not formed (hereafter, referred to as "space") and (ii) each length of the two states. The digital data is called "recording information" herein. Actually, the recording information is recorded on the information recording medium such that: (1) a recording parameter is set in accordance with the recording information to be recorded; (2) the recording parameter changes the laser beam; (3) the laser beam thus changed forms a recording mark on the information recording medium, thereby recording the recording information on the information recording medium.
In recent years, in response to an increase in the amount of data which is processed, recording speed is being increased for the purpose of reducing the processing time of a recording/reproducing device. Even when an information recording medium becomes capable of recording at a high speed, the information recording medium needs to be capable of recording also at a low speed so as to ensure backward compatibility. Therefore, the information recording medium capable of recording at a high speed has a property which is apt to accumulate heat so as to improve its recording sensitivity. The heat accumulation can distort a recording mark, thereby leading to deterioration in a reproduced signal quality. Therefore, in an information recording medium capable of recording at a high speed, it is important to control heat for forming a recording mark.
As an art which is used for controlling heat for forming a recording mark, there has been known write strategy, which is a high-level laser output control technology. The write strategy carries out laser output control in accordance with the recording parameter so as to control heat for forming a recording mark. As the number of recording parameters increases, the control of heat for forming a recording mark becomes complicated. There is a method where a recording parameter is once stored in an information recording medium in a form of a look-up table, and the recording parameter is read out from the look-up table by a recording/reproducing device so as to set the recoding parameter. In this method, the increased number of recording parameters prolongs read-out time of information from the look-up table by using the recording/reproducing device. This causes delay in the timing of starting a recording process. Therefore, it is preferable to use as small number of recording parameters as possible.
In view of this, for example, Patent Document 1: Japanese Unexamined Patent Application Publication, No. 2005-92942 (published on Apr. 7, 2005) discloses an optical disc recording method including a look-up table which defines recording parameters. In the method, the procedure of controlling heat for forming a recording mark proceeds while the table is looked up.
Specifically, Patent Document 1 describes as follows. A recording parameter for a top pulse which controls heat of a front edge, at which a forming process of a recording mark starts, uses a look-up table in which (i) front space lengths of recording marks are classified into four groups: 2T, 3T, 4T, and 5T or longer and (ii) recording mark lengths are classified into three groups: 2T, 3T, and 4T or longer (see FIG. 17). Also, a recording parameter for a last pulse which controls heat of a rear edge, at which a forming process of a recording mark ends, uses a look-up table in which (i) rear space lengths of recording marks are classified into four groups: 2T, 3T, 4T, and 5T or longer and (ii) recording mark lengths are classified into two groups: 3T and 4T or longer (see FIG. 18). That is, in the look-up table disclosed in Patent Document 1, mark lengths of 4T or longer are classified into the same group, and front and rear space lengths of 5T or longer are classified into the same group. This reduces the number of recording parameters. Thereby, heat for forming a recording mark is controlled at a front edge and a rear edge. The symbol "T" herein represents a time equivalent to one cycle of a clock. For example, a mark length of 2T indicates a region (i.e., a recording region) where a recording mark "1" is formed for a time equivalent to two cycles of the clock. Similarly, a space length of 2T indicates a region where no recording mark is formed for a time equivalent to two cycles of the clock.
With a further increase in a recording speed expected in the future, a recording mark will be formed on an information recording medium having improved recording sensitivity. When a recording mark is formed by using a laser beam, heat distribution is high at a rear edge of a recording mark, at which rear edge the forming process of the recording mark ends. Therefore, the increase in the recording speed will strengthen the tendency to accumulate heat at the rear edge. This leads to an increasing necessity for controlling heat at the rear edge more strictly by using the recording parameter.
Patent Document 1, however, uses the same setting for (i) the classification of recording parameters for controlling heat of a front edge, at which a forming process of a recording mark starts and (ii) the classification of recording parameters for controlling heat of a rear edge, which needs to be controlled strictly. Specifically, both types of the recording parameters use a look-up table in which recording mark lengths of 4T or longer are classified into the same group. In addition, Patent Document 1 does not specifically disclose on what basis the recording mark lengths, the front space lengths, and the rear space lengths are classified in the look-up table, which defines the recording parameters, for the purpose of reducing the number of recording parameters. Therefore, although the number of the recording parameters is reduced, there is a problem that a good reproduced signal quality is not guaranteed (i.e., a reproduced signal quality as desired is not guaranteed) in reading out a recording mark actually.

Recording/reproducing device and method using pulse sequences and information recording medium


A method for providing access control to a single sign-on computer network is disclosed. A user is assigned to multiple groups within a computer network. In response to an access request by the user, the computer network determines a group pass count based on a user profile of the user. The group pass count is a number of groups in which the access request meets all their access requirements. The computer network grants the access request if the group pass count is greater than a predetermined high group pass threshold value.

1. Technical Field
The present invention relates to computer security in general, and in particular to a method for providing access control to computer networks. Still more particularly, the present invention relates to a method for providing access control to single sign-on computer networks.
2. Description of the Related Art
For a large institution, such as a corporation, university, etc., computer security has been primarily focused on stopping external threats. However, it is expected that more than 70% of all intrusions to a computer network within a large institution come from internal sources. In other words, the majority of the security threats to a computer network of a large institution comes from its own employees. Regardless of whether the intrusions to the computer network are intentional or not, such intrusions may end up costing the institution millions of dollars.
With external hackers, network administrators can use firewalls and/or other computer security tools to detect and stop intrusions to a computer network. But with internal "hackers," network administrators are left without any useful tools to combat the intrusion problem because firewalls and other computer security tools are ineffective when the attacker is already inside the institution. In addition, network administrators must be able to maintain a delicate balance between access control and ease of access to a computer network. To that goal, a single sign-on approach is designed to simplify the process of accessing to resources within a computer network while maintaining access control to the computer network. With a single sign-on computer network, an employee can authenticate himself/herself to use most, if not all, resources within the computer network by simply signing on to the computer network once instead of logging on to various resources, such as the mail server, file server, web server, etc., separately.
With the single sign-on approach, a network administrator still has to define access permissions for each employee to each resource within the computer network initially. Such practice is prohibitively tedious from a network management standpoint as well as from a usability standpoint. In order to reduce setup time, employees may be divided into groups for the purpose of granting network access permissions. However, every employee within an institution is typically unique, and it is not uncommon to grant special access permissions to each employee in order to allow for individual circumstances, which in essence defeats the benefit of grouping. Besides, group permissions tend to be very restrictive and often limit employees' ability to perform their job efficiently. Because the current method of providing access control to a single sign-on system is both limiting and inefficient, it would be desirable to furnish an improved method for providing access control to a single sign-on computer system.

Method for providing access control to single sign-on computer networks

International Business Machines Corporation


Provided are a terminal device and related products. A method includes the following. Pixels contained in an ordinary pixel set and a standby pixel set in a preset area are controlled to emit light when a finger of a user is applied to the preset area, where the light emitted by the pixels is configured to illuminate a fingerprint of the user. Perform fingerprint collection on the fingerprint illuminated by the light emitted by the pixels of the user.

Nowadays, the fingerprint function has become the standard for smart phones. It can be seen that mobile phones without fingerprint function cannot keep up with the times. Fingerprint sensors are key devices for automatic fingerprint collection. In terms of the sensing principle, the fingerprint sensors can include an optical fingerprint sensor, a semiconductor capacitor sensor, an ultrasonic sensor, and the like.
The optical fingerprint sensor utilizes the principle of refraction and reflection of light. Light emitted by a light source has different angles of refraction and reflected light of different brightness on uneven lines of a fingerprint of a finger. The complementary metal-oxide-semiconductor transistor (CMOS) or charge coupled device (CCD) optics collects image information in different brightness to complete the fingerprint collection.
Fingerprint recognition plays a vital role in functions such as fingerprint unlocking and fingerprint payment. However, quality of the fingerprint collected by the fingerprint sensor determines a success rate of fingerprint recognition. Therefore, how to improve the quality of the fingerprint collected is a technical problem to be solved.

Method for fingerprint collection and related products

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


A system for controlling temperature of an energy store in a motor vehicle may include a coolant circuit in which a coolant may be flowable and into which the energy store may be incorporated in the thermally conductive manner, a refrigerant circuit in which a refrigerant may be flowable and including a refrigerant compressor, a flat tube condenser, and a receiver dryer, which may be secured in the flat tube condenser, and a refrigerant evaporator connecting the coolant circuit and the refrigerant circuit. Heat between the coolant and the refrigerant may be transferrable in the refrigerant evaporator. The system may be secured in a housing. A large area of the flat tube condenser, through which air may be flowable, and the receiver dryer, which may be secured in the flat tube condenser, may have an operating angle of greater than 5° and smaller than 90° with respect to an operating horizontal plane, wherein the operating angle may be selected in such a way that dimensions of the system may be adapted to desired values and the system may be designed in a more compact manner.

Systems for controlling the temperature of energy stores in an electric or in a hybrid vehicle are already known—for example from DE 10 2016 108 486 A1. A system of this type thereby usually has a coolant cooler, which, in a coolant circuit, is connected in a thermally conducting manner to an energy store—for example a traction battery. The energy store thereby dissipates the generated heat to the coolant, which is subsequently cooled in the coolant cooler. The ambient air can thereby flow, for example, through the coolant cooler, and the coolant can thus be cooled.
To be able to cool the coolant and thus the energy stored even in the case of a high external temperature, the system usually also has a refrigerant circuit. The refrigerant circuit usually comprises a refrigerant compressor, a receiver dryer, and a flat tube condenser. The refrigerant compressor compresses the refrigerant, which is subsequently cooled in the flat tube condenser and is freed from the residual water and collected in the receiver dryer. The flat tube condenser is thereby arranged so that air can flow through, and the receiver dryer is usually operated vertically in order to attain the highest possible efficiency.
The refrigerant circuit and the coolant circuit can be connected to one another via an evaporator or chiller, respectively—an evaporative cooling-based cooling unit—so that the refrigerant can be cooled in the evaporator or chiller, respectively. In the case of a high external temperature, the coolant can thus additionally be cooled in the refrigerant circuit, and the heat generated in the energy store can be discharged effectively.
Such systems are usually subject to spatial limitations and have to be as compact and light as possible.
It is thus the object of the invention to specify an improved or at least alternative embodiment for a system of the generic type for designing the system in a compact and light manner.

System for controlling the temperature of an energy store


An elastic warp knitted fabric which exhibits excellent extensibility and extension recovery characteristics and gives good wearing feeling, has excellent motion followability, can contribute to improvement in movement function, further has no limitation in applications due to extension force thereof, and can be used as the material of a garment less likely to lose the shape due to wearing. The elastic warp knitted fabric of the present invention is the elastic warp knitted fabric knitted at least two guide bars, and is characterized in that the elastic fibers are arranged on at least one guide bar and inelastic fibers are arranged on the other guide bar, respectively, both an extension force in the warp direction and that in the weft direction are 100 cN to 600 cN, in extension by 80% of the said knitted fabric, that the ratio of the extension force in the warp direction to that in the weft direction is 0.8 to 1.8.

Conventionally, an elastic warp knitted fabric containing elastic yarns has been used in many applications as an innerwear fitted to a body such as shorts, girdle, and brassiere, an undershirt fitted to a body such as sportswear, and a swimsuit, or the like. The inner wear where the warp knitted fabric is used has good wearing feeling and is also capable of enhancing shape retaining properties of body.
Further, as a sportswear or a swimsuit using these elastic warp knitted fabrics, various products have been sold aiming at enhancing body function owing to tightening action. As a tricot warp knitted fabric used in these products, a tricot 2-way warp knitted fabric has been used widely, which is composed of a half texture obtained by knitting a base texture with a knit texture of 1-0/2-3 using inelastic fibers composed of synthetic fiber multi-filaments or spun yarns such as cotton yarns, and combining to this base texture a knit texture of 1-2/1-0 using elastic fibers. This tricot 2-way warp knitted fabric has been dissatisfactory in fit feeling in wearing as a product, because of extremely little extension in a weft direction compared to that in a warp direction, although cloth extends in a weft direction and a warp direction.
In addition, in a knitted fabric having such largely different extensibility to a warp direction and a weft direction, there is also a problem of receiving large restriction in usage of cloth, because of requiring to cut cloth by matching a stress-receiving direction in practical wearing of a garment, and a direction in which cloth easily extends.
To solve this problem, there has been proposed a method for making extension stress in a warp direction and a weft direction relatively the same level, by knitting elastic yarns by two needle stitch to attain predetermined density in a course direction, aiming at fulfilling suitable balance of extensibility and extension recovery characteristics, in both of a warp direction and a weft direction, however, it has not referred at all to a knitting method of the inelastic fibers which determines extension recovery characteristics of the elastic fibers, which thus left a problem of being insufficient in motion followability arising from recovery characteristics when used as a garment (see PATENT DOCUMENT 1 below). In addition, there has been proposed a method for matching extensibility in a warp and weft to relatively same level, by knitting with a weft knit texture formed a loop by elastic yarns, or knitting by inserting elastic yarns to a base texture, however, this method only provides such one as requiring large force for extension, which limits applications, and thus has a problem of being not suitable for applications requiring extension by relatively small force, such as shorts, inner wears, sports undershirts (see PATENT DOCUMENT 2 below).
As an elastic warp knitted fabric having low stress in extension, an extension force ratio in a warp direction/in a weft direction within a certain range, and superior balance of elastic characteristics in weft and warp directions, such an elastic warp knitted fabric has also been disclosed that both of elastic yarns and inelastic yarns are composed of a specific Atlas knit texture (see PATENT DOCUMENT 3 below). This method gives a softly stretchable elastic warp knitted fabric not giving tight feeling in wearing, by decreasing stress in extension, however, it decreases extension recovery characteristics, which raises a problem of generation of losing shape at wearing, in sports goods aiming at enhancement of body function, or a problem of inhibiting motion caused by non integration of cloth and muscle movement due to poor motion followability.
In recent years, it has been required such cloth as not only simply stretching with matching to body movement but also having extension function like supporting body movement. Specifically, it has been required such a garment or a knitted fabric for a garment that is good in tightening feeling (or fit feeling), as well as extremely superior in motion followability and supports muscle or the like of a body and contributes to enhancement of movement function, by being capable of moving in nearly the same way as body movement, and still more has no limitation in applications due to extension force, and is less likely to lose shape due to wearing. However, it has been difficult to obtain a garment superior in soft stretching characteristics providing extension under low stress, and extension recovery characteristics enabling to follow extension recovery motion, by using the aforesaid knitted fabric.


Several circuits and methods implemented to perform signal quality estimation and control are disclosed. In an embodiment, a method of signal quality estimation includes generating a demodulated signal associated with a radio signal. Information associated with a quality of the demodulated signal is accessed. Further, a value of radio frequency signal-to-noise ratio (RF-SNR) for the radio signal based on the information is estimated. Estimating the value of RF-SNR facilitates in signal quality estimation of the radio signal and control of the demodulated signal.

Pursuant to an example scenario, estimating quality of a received signal in radio communications enables performance enhancement of various system parameters. For example, in a Frequency Modulation (FM) radio receiver, the consistency of perceptive audio quality is maintained across a wide variety of signal conditions by employing stereo noise control (SNC) mechanisms, such as, soft mute and mono-stereo blending. When the received signal to noise ratio (SNR) reduces in a radio receiver, the noise in a demodulated audio signal becomes relatively more perceptible. Soft mute is a technique used to attenuate a final audio output at low received SNRs to mitigate the noise audibility. Similarly, when the received SNR degrades, the audio output gradually switches from stereo to mono mode. In FM, optimal audio fidelity is maintained by dynamically scaling a stereo (L−R) signal by blending the stereo (L−R) signal with a mono (L+R) signal. Signal quality estimation is an important tool for enabling the SNC mechanisms, since the soft mute attenuation factor or the mono-stereo blending factor is to be controlled based on the signal condition.


One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate to thereby define a plurality of fins in the substrate, forming a layer of insulating material in the trenches, performing an etching process sequence to remove at least a portion of one of the plurality of fins and thereby define a fin cavity, wherein the etching process sequence includes performing a first anisotropic etching process and, after performing the first anisotropic etching process, performing a second isotropic etching process. In this embodiment, the method concludes with the step of forming additional insulating material in the fin cavity.

1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods for removing selected fins that are formed for FinFET semiconductor devices.
2. Description of the Related Art
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device "A" that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. The FinFET device may have either a tri-gate or a dual gate channel structure. In a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Accordingly, for a given plot space (or footprint), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
A shallow trench isolation structure (not shown) is formed in the semiconducting substrate around the FinFET device so as to electrically isolate the FinFET device. Traditionally, isolation structures were always the first structures that were formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches for the isolation structures and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. Thereafter, the isolation structures were masked and trenches were etched into the substrate so as to define the fins. However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form the trenches T in the substrate B to define multiple "fins" that extend across the substrate, and thereafter remove some of the fins C where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins C to very small dimensions due to the more uniform environment in which the etching process that forms the trenches T is performed.
After the trenches T have been formed, some of the fins C must be removed to create room for or define the spaces where isolation regions will ultimately be formed. There are two commonly employed techniques for accomplishing the goal of removing the desired number of fins C. One such removal process is typically referred to as "Fins-cut-First," as will be described with reference to FIGS. 1B-1E. Accordingly, FIG. 1B depicts the device 10 after a patterned hard mask layer 14, e.g., a patterned layer of silicon nitride, was formed above the substrate 12 in accordance with the desired fin pattern and pitch. In the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A, to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1C depicts the device 10 after a patterned masking layer 16, e.g., a patterned layer of photoresist, has been formed above the patterned hard mask layer 14. The patterned masking layer 16 has an opening that exposes the feature 14A for removal.
FIG. 1D depicts the device 10 after an etching process has been performed through the patterned masking layer 16 so as to remove the exposed feature 14A of the patterned hard mask layer 14.
FIG. 1E depicts the device 10 after the patterned masking layer 16 was removed and after an etching process was performed through the patterned hard mask layer 14 (without the feature 14A) so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Due to the removal of the feature 14A, this etching process removes the portions of the substrate 12 that would have otherwise formed a fin 15 in the area under the feature 14A. One problem with the "fin-cut-first" approach is that it inevitably causes different fin sizes, i.e., the dimensions 15X and 15Y are different. This is especially true between fins 15 inside an array of fins and the fins at the edge of the active region that is close to the isolation region. This occurs due to etch loading effects wherein there are different etch rates and etch profiles due to differing patterning densities, pitch, etc.
FIG. 1F depicts the device 10 after several process operations were performed. First, a layer of insulating material 18, such as silicon dioxide, was formed so as to overfill the trenches 17. A chemical mechanical polishing (CMP) process was then performed to planarize the upper surface of the insulating material 18 with the top of the patterned hard mask 14. Thereafter, an etch-back process was performed to recess the layer of insulating material 18 between the fins 15 and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15. At this point in the process, the patterned hard mask 14 may or may not be thereafter removed. Next, the gate structure of the device 10 may be formed using either gate-first or gate-last manufacturing techniques.
Another fin removal process is typically referred to as "Fins-cut-Last," as will be described with reference to FIGS. 1G-1J. FIG. 1G depicts the device 10 after the patterned hard mask layer 14 was formed above the substrate 12 in accordance with the desired fin pattern and pitch. As before, in the depicted example, only a single fin will be removed, i.e., the fin 15 corresponding to the feature 14A to make room for the isolation region. However, as will be recognized by those skilled in the art, depending upon the desired final size of the isolation region, more than one fin may be removed.
FIG. 1H depicts the device 10 after an etching process was performed through the patterned hard mask layer 14 so as to define full-depth trenches 17 in the substrate 12 that define the fins 15. Note that, in the Fins-cut-Last approach, the size of the fins is very uniform, i.e., the dimension 15A is approximately equal to the dimension 15B. This is primarily due to the fact that, in this approach, fins 15 are formed everywhere on the wafer and there is no undesirable etch loading effects.
FIG. 1I depicts the device 10 after several process operations were performed. First, a layer of insulating material 19, such as silicon dioxide, was formed so as to overfill the trenches 17. Then a CMP process was performed to planarize the upper surface of the layer of insulating material 19 with the patterned hard mask layer 14. Next, a patterned masking layer 22, e.g., a patterned layer of photoresist, was formed above the layer of insulating material 19. The patterned hard mask layer 22 has an opening that exposes the underlying fin for removal.
FIG. 1J depicts the device 10 after one or more etching processes were performed to remove the exposed portions of the layer of insulating material 19, the exposed portions of the hard mask layer 14, i.e., the feature 14A, and the underlying fin 15 by forming a trench 24 in the substrate 12. Inevitably, there will be some tapering of the sidewalls of the trench 24. Although not depicted in the drawings, after the trench 24 is formed, the patterned masking layer 22 will be removed and additional oxide material (not shown) will be formed through the opening 24A in the trench 24 where the fin 15 was removed. Then a chemical mechanical polishing (CMP) process will be performed to planarize the upper surface of all of the insulating materials with the top of the patterned hard mask 14. Thereafter, the isolation regions between devices will be masked and an etch-back process will be performed to recess the layer of insulating material 19 between the fins 15 for each device and thereby expose the upper portions of the fins 15, which corresponds to the final fin height of the fins 15.
One problem with the fins-cut-last approach is that if the size (CD) of the opening 24A of the trench 24 is relatively large, then there is less margin for misalignment error when removing the unwanted fin, i.e., there is less margin for error so as to avoid damage to the adjacent fins when the trench 24 is etched. Additionally, although not depicted, if the size of the opening 24A is kept small, there will typically be some residual portion of the fin 15 remaining at the bottom of the trench 24. Conversely, if the size of the opening 24A is increased in an effort to insure complete removal of the unwanted fin at the bottom of the trench 24, then there is a much greater likelihood of damaging the fins adjacent the trench 24 when it is etched. These issues only get worse as the depth of the trench 24 increases. Moreover, in many applications, e.g., SRAMs, it is often the case where only a single fin will need to be removed from the array or group of fins as initially formed. Removing a single fin without damaging adjacent fins is very difficult for at least the reasons noted above.
The present disclosure is directed to various methods of forming fins for FinFET semiconductor devices and the selective removal of some of the fins that may solve or reduce one or more of the problems identified above.

Methods for removing selected fins that are formed for finFET semiconductor devices


After a first insulating film is formed on a substrate, a wiring groove is formed in the first insulating film, and then a wire is formed inside the wiring groove. Subsequently, a protection film is formed on the first insulating film and on the wire, and then a hard mask film is formed on the protection film. After that, the hard mask film is patterned. Subsequently, the protection film and the first insulating film are partially removed using the patterned hard mask film to form an air gap groove, and then a second insulating film is formed to close an upper portion of the air gap groove for forming an air gap.

1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device.
2. Description of the Prior Art
Progressing miniaturization of semiconductor integrated circuit device in recent years narrows a wire-to-wire spacing. This results in a problem that capacitance between wires increases, lowering the propagation velocity of a signal. To reduce the capacitance between the wires, it has been studied to embed an insulating film material having a low dielectric constant between the wires. Meanwhile, it has also been studied to form an air gap between the wires to reduce the capacitance between the wires. A conventional method for forming the air gap disclosed in Patent Document 1 will be described below with reference to the drawings.
First, as illustrated with FIG. 5A, on a surface of a semiconductor substrate 1, an insulating film 2 is formed.
Then, as illustrated with FIG. 5B, photolithography and dry etching are performed to form wiring grooves 3 in an upper portion of the insulating film 2.
Then, as illustrated with FIG. 5C, over the insulating film 2 and inside the wiring grooves 3, a barrier film 4 and a Cu film 5 are sequentially deposited. Then, part of the barrier film 4 and part of the Cu film 5 which are lying outside the wiring grooves 3 are removed by CMP (chemical mechanical polishing) to form lower wires 6.
Then, as illustrated with FIG. 5D, CVD (chemical vapor deposition) or electroless plating is performed for selective growth of a cap film 7 on respective surfaces of the lower wires 6.
Then, as illustrated with FIG. 6A, CVD is performed to deposit a protection film 8 on the insulating film 2 and on the cap film 7 covering the lower wires 6.
Then, as illustrated with FIG. 6B, photolithography is performed to form a patterned resist mask 9 on the protection film 8. The resist mask 9 has an opening in an air gap formation region, and the air gap formation region can be defined by the opening.
Then, as illustrated with FIG. 6C, part of the protection film 8 located in the air gap formation region is removed using the resist mask 9.
Then, as illustrated with FIG. 7A, part of the insulating film 2 located between the lower wires 6 is removed by dry etching using part of the cap film 7 located in the air gap formation region and the resist mask 9 as a mask so that air gap grooves 10 are formed. Then, the resist mask 9 is removed.
Then, as illustrated with FIG. 7B, CVD is performed to deposit an insulating film 11 over the entire surface of the semiconductor substrate 1. This closes upper portions of the air gap grooves 10 with the insulating film 11 before the air gap grooves 10 are filled with the insulating film 11, thereby forming air gaps 12.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-120988

Method for fabricating semiconductor device


In one embodiment, an apparatus includes: a control circuit to enable a comparison circuit based on a dynamic update to a hook table and a patch table; and the comparison circuit coupled to the control circuit to compare an address of a program counter to at least one address stored in the hook table, and in response to a match between the address of the program counter and the at least one address stored in the hook table, cause a jump from code stored in a read only memory to patch code stored in a patch storage. Other embodiments are described and claimed.

In many electronic devices, embedded software or firmware can be stored in either random access memory (RAM) or read-only memory (ROM). Especially when the code is quite stable, ROM is the preferred option because of cost efficiency (smaller chip area) and power efficiency (lower leakage). However, when code is written onto ROM masks, it becomes unchangeable. Updates to be made to code stored in ROM, e.g., due to bug fixes or quality improvements, are typically patched to the ROM using a patch RAM (PatchRAM).
To enable these potential future ROM updates using PatchRAM, ROM code typically includes software hooks inserted a priori, to jump from ROM code into PatchRAM where code for the bug fix/update is stored. For a given code change, the amount of PatchRAM memory consumed is dependent on software hook placement. Such software hooks are typically placed at some granularity in the ROM code. If an update occurs many code lines away from a hook, large chunks of code are duplicated into the PatchRAM, which leads to an undesirably large PatchRAM. Or, for a given PatchRAM size, there is a limitation on the number of patches that can be supported. Current designs do not provide a suitable tradeoff to such constraints.

System, apparatus and method for dynamic update to code stored in a read-only memory (ROM)


A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line.

1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
A leakage current increasing with advancement of a technique for forming fine patterns in a semiconductor device is considered as a problem. The leakage current is a current flowing when the semiconductor device does not operate, and this unnecessarily leaking leakage current occupies a large proportion in a total of power consumption of the semiconductor device.
A semiconductor device is known in Japanese Patent Application Publication (JP-P2007-95787A: related art 1) in which an increase of this power consumption is suppressed by having two operation states of a standby state (a state that supply of power to a non-operation section is temporarily stopped) and a normal operation state (a state that a normal operation is performed). In the semiconductor device, the state thereof shifts from the normal operation state to the standby state by stopping the power supply to a region.
FIG. 1 is a circuit diagram of a semiconductor device 100 shown in the related art 1. Referring to FIG. 1, the semiconductor device 100 includes a controlled function block 101 and a power supply switch 102. In addition, the semiconductor device 100 includes a function block in which a control of power supply is not performed (hereinafter to be referred to as a non-controlled function block). The controlled function block 101 is a function block in which the power supply is stopped in the standby state. The power supply switch 102 connects the controlled function block 101 to a power supply wire Vdd in response to a control signal.
FIG. 2 is a layout diagram showing the semiconductor device 100 including the power supply switch 102 and the controlled function block 101. In the layout diagram of the controlled function block 101, a switch cell 107 and a function cell 108 are shown. The switch cell 107 is configured to include a first well 121. A switching transistor 113 is formed in the first well 121. In addition, the function cell 108 includes a second well 122. The first well 121 and the second well 122 are electrically isolated from each other A metal interconnection 116 is formed in a region of the first well 121. As described above, a power supply voltage VDD is supplied to the metal interconnection 116 via a first via contact (not shown).
When the power supply switch 102 is activated to connect the controlled function block 101 to the power supply line, a rush current (a current rapidly flowing in starting-up a circuit) sometimes flows in the power supply line Vddv and the power supply line Vdd. When the rush current flows, a counter electromotive force due to inductance components of a bonding wire and a long interconnection line is generated depending on a rate of change of the rush current. The counter electromotive force generates power supply noise on the power supply line, and the power supply noise continues until a power supply IC externally provided to the semiconductor device 100 responds to the rush current to sufficiently supply the power supply voltage. A malfunction of the controlled function block sometimes occurs due to the power supply noise. A technique for reducing the power supply noise by taking a countermeasure against the rush current to suppress the malfunction is known. For example, a technique is known which suppresses increase of the rush current generated in supplying the power supply by arranging a plurality of switch cells 107 and separating timings of turning on the respective switch cells.
A circuit area of the controlled function block 101 and the number of controlled function blocks 101 in the semiconductor device 100 have been increasing according to a high integration of a chip. A large controlled function block 101 and many controlled function blocks 101 cause a large rush current. In the semiconductor device 100; when the large rush current is generated, the number of the switch cells 107 is increased. However, it is very difficult to reduce the power supply noise by appropriately controlling many switch cells 107.

Semiconductor device with less power supply noise


A bus controller for a computer system. The controller comprises a monitor for monitoring request signals and response signals between a first component and a second component each connected to a bus of the computer system; and a terminator controlled by the monitor to terminate a request from one of the first and second components if a response to the request has not issued within a predetermined period of time.

This invention relates to a bus controller for a computer system such as a multi-processor system, for example, in which first and second processing sets (each of which may comprise one or more processors) communicate with an I/O device bus via a bridge.
The application finds particular but not exclusive application to fault tolerant computer systems where two or more processor sets need to communicate in lockstep with an I/O device bus via a bridge.
In such a fault tolerant computer system, an aim is not only to be able to identify faults, but also to provide a structure which is able to provide a high degree of system availability and system resilience to internal or external disturbances. In order to provide high levels of system resilience to internal disturbances, such as a processor failure or a bridge failure for example, it would be desirable for such systems automatically to control access to and from a device that might appear to be causing problems.
Automatic access control provides significant technical challenges in that the system has not only to monitor the devices in question to detect errors, but also has to provide an environment where the system as a whole can continue to operate despite a failure of one or more of the system components. In addition, the controller must also deal with any outstanding requests issued by components of the computer system and this is typically problematic as bus protocols, such as PCI for example, typically don't support error termination at all stages of operation.
Accordingly, an aim of the present invention is to address these technical problems.


A processor may identify a new application on a device. The processor may receive, from the device, user data. The user data may include user profile information and user activity information. The processor may evaluate the user data. The evaluating of the user data may include designating a security level to the user data. The processor may determine, from evaluating the user data, that a default security configuration for the new application is not secure. The processor may automatically generate a customized security configuration for the new application. The processor may apply the customized security configuration to the new application.

The present disclosure relates generally to the field of digital security, and more specifically to automatically generating customized security configurations based on user vulnerabilities.
In most instances, when a new application is added to a computing device, automatic configurations are generically generated and applied. However, many of the generic, automatic configurations incorrectly belong to security parameters. Incorrectly identified security parameters can lead to vulnerabilities in the application and computing device.

Dynamically customized cognitive security filter


A face model having outer and inner facial features is matched to that of first and second models. Each facial feature of the first and second models is represented by plurality of points that are adjusted for each matching outer and inner facial feature of the first and second models using 1) the corresponding epipolar constraint for the inner features of the first and second models. 2) Local grey-level structure of both outer and inner features of the first and second models. The matching and the adjusting are repeated, for each of the first and second models, until the points for each of the outer and inner facial features on the respective first and second models that are found to match that of the face model have a relative offset there between of not greater than a predetermined convergence tolerance. The inner facial features can include a pair of eyes, a nose and a mouth. The outer facial features can include a pair of eyebrows and a silhouette of the jaw, chin, and cheeks.

A three dimensional object can be represented in two dimensions. In fact, representing a three-dimensional object by using two-dimensional views has advantages in object modeling and synthesis. In such two-dimensional representations, the three-dimensional features of the object need not be explicitly recovered and this avoids difficulties in three-dimension based methods. Rather, it is conventional to use view-based models to represent the object with multiple two-dimensional view projections. When representing an object with more than one two-dimensional view, a pixel-wise correspondence map is usually required between each of the two-dimensional views. Alternatively, a sparse correspondence map between a small set of feature points, or edges of features, on the object can be used between each of the two-dimensional views. The correspondence map can be computed and applied to separate the shape of the object from the texture of the object. As such, both the shape of the object and the texture of the object, from a particular viewpoint, can be modeled in a linear subspace.
When representing an object with more than one two-dimensional view, it may be advantageous to establish points to represent features on the object (feature points). A feature point based correspondence between multiple two-dimensional views is advantageous in some applications because it is more robust in dealing with light intensity and color variations, and can involve less computation than establishing a dense representation of the object. Accordingly, to accurately model an image class of an object, two problems can be addressed and solved. The first problem is that of locating feature points on features of the object by using a training set of two-dimensional views. Once the feature points of the features on the object are located, the second problem is that of establishing the underlying correspondence between two or more sets of feature points from a corresponding number of two-dimensional views.
An additional degree of difficulty arises when locating features in a complex and non-rigid object using multiple two-dimensional views. These difficulties can be addressed by using prior knowledge regarding the object itself. For instance, a deformable model of the object is an example of such prior knowledge. The deformable model can provide constraints on the location of features on the object. These constraints, which can be derived from image data with respect to the object, can be used to deal with the problems like segmentation of the object or the detection of features on the object. In particular, the Active Shape Model (ASM) as proposed by Cootes et al. (Active Shape Model, T. F. Cootes, C. Taylor, D. Cooper, and J. Graham. Active shape models—their training and their applications. Computer Vision and Image Understanding, 61(1):38–59, January 1995) provided the advantage that the instances of the model of the object can be deformed only in those ways that were learned from the training set from which the model was derived. That is, the model can accommodate considerable variability in segmentation of the object, or in the detection of its features, but the model should still be specific to the class of the object that the model represents. ASM uses the Principle Component Analysis technique (PCA) to model an object by both the two-dimensional shape variations of the object and the local grey level structures of the object. In particular, ASM is a process that includes interrogating two-dimensional images of the object and approximating the shape of features on the object using points (feature points) that respectively represent each feature on the object.
When two or more different two-dimensional views of the same object are given, the features on the object for each view can be matched to a model of the object by using ASM. After the model matching for each view is performed, it would be desirable to find the correspondence between the respective feature points of the features of the object for the different views, such as by implication across each of the different views. The detected feature points for each feature on the object, however, may not be geometrically consistent across the different views. This inconsistency occurs because ASM only considers a single view rather than the correspondence between the different views. The matching of the model to each of the different views could benefit from the use of a multi-view geometry. While this can be accomplished, it requires that all key feature points of each feature on the object remain visible in each of the two-dimensional views.
One technique for using ASM involves using a set of training examples of one face view from different viewpoints. From these views of the one face, a set of feature points of facial features on the face can be manually labeled. This manual labeling represents a deformation of the face into its different facial features and respective points that make up the facial features. For instance, these features can include the nose, eyes and mouth. The feature points are those points that mark the facial features on the face. ASM uses the set of training data representing the deformation of the face to analyze facial features on a different face by using views of the different face. This conventional ASM technique, however, suffers from inaccuracy in locating facial features in the views of the face being analyzed. Moreover, the conventional ASM technique can only deform the face being analyzed in the ways that the face in the set of training data had been deformed. One partial solution to overcome the inherent inaccuracy is to use a larger training database. Such a solution is only partial because it does not take into consideration the local grey-level model fitting for the different views of the face. Local grey-level model fitting tends to interpret the data so as to move facial features toward the strongest photometric edge, which may not necessarily be the actual edge of a facial feature—thus introducing further inaccuracy. Moreover, using a larger training database may further decrease accuracy because the additional data tends to further extend the acceptable facial feature shapes into an inaccurate range for the face being analyzed.
In addition to the foregoing problems, ASM is not consistent in finding the same facial features in two slightly different views of the same face. ASM does not always guarantee that the features identified in training data for a training object will yield similar features when searching two slightly different views of another object. This inability can be attributed to illumination changes in the object as a result of rotating the object in different two-dimensional views, or it can be attributed to different initial parameters. Two negative results can occurs when using conventional ASM in this environment. One result is that the conventional ASM model will wrongly identify features on an object or will inaccuracy locate the feature points for features on the object. Either way, different two-dimensional views of the same object, when using conventional ASM, will yield features that do not match up between the different two-dimensional views. In consequence, the correspondence between the identified features of the different views is inaccurate when using conventional ASM.
If would be an advance in the art to develop a technique that will accurately and consistently identify the same features in different views of the same object.