Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash EEPROM, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, retaining its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment. This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements. These undesirable attributes make disk-based storage impractical in most mobile and portable applications. On the other hand, flash memory is ideally suited in the mobile and handheld environment because of its small size, low power consumption, high speed and high reliability features.
EEPROM and electrically programmable read-only memory (EPROM) are non-volatile memory that can be erased and have new data written or "programmed" into their memory cells.
An EPROM utilizes a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. A control gate is then provided over the floating gate. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, for a given level of charge on the floating gate, there is a corresponding voltage (threshold) that must be applied to the control gate before the transistor is turned "on" to permit conduction between its source and drain regions.
The floating gate can hold a range of charge and therefore an EPROM memory cell can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold window generally depends on the memory device's characteristics, operating conditions and history. Each distinct, resolvable threshold voltage level range within the window may, in principle, be used to designate a definite memory state of the cell.
For EPROM memory, the transistor serving as a memory cell is typically programmed to a programmed state by accelerating electrons from the substrate channel region, through a thin gate dielectric and onto the floating gate. The memory is bulk erasable by removing the charge on the floating gate by ultraviolet radiation.
FIG. 1A illustrates schematically a non-volatile memory in the form of an EEPROM cell with a floating gate for storing charge. An electrically erasable and programmable read-only memory (EEPROM) has a similar structure to EPROM, but additionally provides a mechanism for adding and removing charge electrically from its floating gate upon application of proper voltages without the need for exposure to UV radiation.
An array of such EEPROM cells is referred to as a "Flash" EEPROM array when an entire array of cells, or significant group of cells of the array, is electrically erased together (i.e., in a flash). Once erased, the group of cells can then be reprogrammed.
FIG. 1B illustrates schematically a non-volatile memory in the form of a NROM cell with a dielectric layer for storing charge. Instead of storing charge in a floating gate, it has a dielectric layer for storing charge. For example, U.S. Pat. Nos. 5,768,192 and 6,011,725 disclose a nonvolatile memory cell having a trapping dielectric sandwiched between two silicon dioxide layers.
Cell and Array Structure
FIG. 1C illustrates schematically a flash EEPROM cell having both a select gate and a control or steering gate. Memory devices having such a cell structure are described in U.S. Pat. No. 5,313,421, which patent is incorporated herein by reference. The memory cell 10 has a "split-channel" 12 between source 14 and drain 16 diffusions. A cell is formed effectively with two transistors T1 and T2 in series. T1 serves as a memory transistor having a floating gate 20 and a control gate 30. The control gate will also be referred to as a steering gate 30. The floating gate is capable of storing a selectable amount of charge. The amount of current that can flow through the T1's portion of the channel depends on the voltage on the steering gate 30 and the amount of charge residing on the intervening floating gate 20. T2 serves as a select transistor having a select gate 40. When T2 is turned on by a voltage at the select gate 40, it allows the current in the T1's portion of the channel to pass between the source and drain.
FIG. 1D illustrates schematically another flash EEPROM cell having dual floating gates and independent select and control gates. Memory devices having such a cell structure are described in co-pending U.S. patent application Ser. No. 09/343,493, filed Jun. 30, 1999, which disclosure is incorporated herein by reference. The memory cell 10′ is similar to that of FIG. 1C except it effectively has three transistors in series. Between a pair of memory transistors, T1—left and T1—right, is a select transistor T2. The memory transistors have floating gates 20′ and 20″ and steering gates 30′ and 30″ respectively. The select transistor T2 is controlled by a control gate 40′. At any one time, only one of the pair of memory transistors is accessed for read or program. When the storage unit T1—left is being accessed, both the T2 and T1—right are turned on to allow the current in the T1—left's portion of the channel to pass between the source and the drain. Similarly, when the storage unit T1—right is being accessed, T2 and T1—left are turned on. Erase is effected by having a portion of the select gate polysilicon in close proximity to the floating gate and applying a substantial positive voltage (e.g. 20V) to the select gate so that the electrons stored within the floating gate can tunnel to the select gate polysilicon.
FIG. 2 is a schematic block diagram of an addressable array of memory cells in rows and columns with decoders. A two-dimensional array of memory cells 100 is formed, with each row of memory cells connecting by their sources and drains in a daisy-chain manner. Each memory cell 50 has a source 54, a drain 56 and a steering gate 60 and a select gate 70. The cells in a row have their select gates connected to a word line 110. The cells in a column have their sources and drains respectively connected to bit lines 124, 126. The cells in a column also have their steering gates connected by a steering line 130.
When the cell 50 is addressed for programming or reading, appropriate programming or reading voltages (VS, VD, VSTG, VSLG) must be supplied respectively to the cell's source 54 and drain 56, steering gate 60 and select gate 70. A word line decoder 112 selectively connects a selected word line to a select voltage VSLG. A bit line decoder 122 selectively connects the pair of bit lines 124, 126 in an addressed column respectively to source voltage VS and drain voltage VD. Similarly, a steering line decoder 132 selectively connects the steering line 130 in the addressed column to a steering or control gate voltage VSTG.
Thus, a specific cell of the two-dimensional array of flash EEPROM cells is addressed for programming or reading by a selection or decode in the column direction of a pair of bit lines and a steering line, and in the row direction of a word line. In order to increase performance, the column decoders 122 and 132 allow a group of columns to be selected, and therefore a corresponding group or chunk of cells to be accessed in parallel, thereby accessing the row of cells chunk-by-chunk.
Previously, many flash EEPROM devices have had a word line connecting all the control gates of cells along each row. Thus, the word line essentially performs two functions: row selection; and supplying control gate voltage to all cells in the row for reading or programming. It is often difficult to perform both of these functions in an optimum manner with a single voltage. If the voltage is sufficient for row selection, it may be higher than desirable for programming. However, with a cell having independent steering gate and select gate, the word line which is connected to the select gates of cell in a row need only perform the selection function while the steering line performs the function of supplying optimum, independent control gate voltage to individual cells in a column.
Cell Characteristics
In the usual two-state EEPROM cell, at least one current breakpoint level is established so as to partition the conduction window into two regions. When a cell is read by applying predetermined, fixed voltages, its source/drain current is resolved into a memory state by comparing with the breakpoint level (or reference current IREF). If the current read is higher than that of the breakpoint level or IREF, the cell is determined to be in one logical state (e.g., a "zero" state), while if the current is less than that of the breakpoint level, the cell is determined to be in the other logical state (e.g., a "one" state). Thus, such a two-state cell stores one bit of digital information. A reference current source, which may be externally programmable, is often provided as part of a memory system to generate the breakpoint level current.
In order to increase memory capacity, flash EEPROM devices are being fabricated with higher and higher density as the state of the semiconductor technology advances. Another method for increasing storage capacity is to have each memory cell store more than two states.
For a multi-state or multi-level EEPROM memory cell, the conduction window is partitioned into more than two regions by more than one breakpoint such that each cell is capable of storing more than one bit of data. The information that a given EEPROM array can store is thus increased with the number of states that each cell can store. EEPROM or flash EEPROM with multi-state or multi-level memory cells have been described in U.S. Pat. No. 5,172,338.
In practice, the memory state of a cell is usually read by sensing the conduction current across the source and drain electrodes of the cell when a reference voltage is applied to the control gate. Thus, for each given charge on the floating gate of a cell, a corresponding conduction current with respect to a fixed reference control gate voltage may be detected. Similarly, the range of charge programmable onto the floating gate defines a corresponding threshold voltage window or a corresponding conduction current window.
Alternatively, instead of detecting the conduction current among a partitioned current window, it is possible to determine the threshold voltage at the control gate that causes the conduction current to just "trip" or transverse a fixed reference current. Thus, the detection is performed on a threshold voltage among a partitioned threshold voltage window.
FIG. 3 illustrates the relation between the source-drain current ID and the control gate voltage VSTG for four different charges Q1–Q4 that the floating gate may be selectively storing at any one time. The four solid ID versus VSTG curves represent four possible charge levels that can be programmed on a floating gate of a memory cell, respectively corresponding to four possible memory states. As an example, the threshold voltage window of a population of cells may range from 0.5V to 3.5V. Six memory states may be demarcated by partitioning the threshold window into five regions in interval of 0.5V each. For example, if a reference current, IREF of 2 μA is used as shown, then the cell programmed with Q1 may be considered to be in a memory state "1" since its curve intersects with IREF in the region of the threshold window demarcated by VSTG=0.5V and 1.0V. Similarly, Q4 is in a memory state "5".
As can be seen from the description above, the more states a memory cell is made to store, the more finely divided is its threshold window. This will require higher precision in programming and reading operations in order to be able to achieve the required resolution.
U.S. Pat. No. 4,357,685 discloses a method of programming a 2-state EPROM in which when a cell is programmed to a given state, it is subject to successive programming voltage pulses, each time adding incremental charge to the floating gate. In between pulses, the cell is read back or verified to determine its source-drain current relative to the breakpoint level. Programming stops when the current state has been verified to reach the desired state. The programming pulse train used may have increasing period or amplitude.
Prior art programming circuits simply apply programming pulses to step through the threshold window from the erased or ground state until the target state is reached. Practically, to allow for adequate resolution, each partitioned or demarcated region would require at least about five programming steps to transverse. The performance is acceptable for 2-state memory cells. However, for multi-state cells, the number of steps required increases with the number of partitions and therefore, the programming precision or resolution must be increased. For example, a 16-state cell may require on average at least 40 programming pulses to program to a target state.

This patent is subject to a terminal disclaimer.

Non-volatile memory with improved programming and method therefor


The amplification type solid-state imaging device of this invention includes amplification type photoelectric converting elements arranged in a matrix. Each of the amplification type photoelectric converting elements includes: a transistor formed at a surface of a semiconductor substrate, for accumulating signal charge generated from incident light on a portion of the transistor at the surface of the semiconductor substrate and outputting an output signal comprising a change in an electric signal corresponding to the accumulated signal charge; a gate region formed adjacent to the transistor, including a portion of the semiconductor substrate, an insulating film formed on the portion of the semiconductor substrate, and a gate electrode formed on the insulating film, the gate region allowing the accumulated signal charge to move from the surface of the semiconductor substrate to the inside of the semiconductor substrate; and an output impedance converting section connected to the photoelectric converting elements which sequentially receives the output signals from the amplification type photoelectric converting elements, the output impedance converting section including a driving transistor driven with the output signals and a load transistor.

1. Field of the Invention
The present invention relates to an amplification type solid-state imaging device including an array of amplification type solid-state imaging elements each having a transistor such as an MOSFET and a junction gate FET which accumulates signal charge obtained by photoelectric conversion of incident light and outputs electric signals corresponding to the accumulated signal charge.
2. Description of the Related Art
A charge-coupled device (CCD) type solid-state imaging device has been widely used in various fields as a featuring device of a solid-state imaging device. In a CCD type imaging device, signal charge, which is photoelectrically-converted and accumulated by a photodiode or a MOS diode, are transferred via a CCD transfer channel to a high-sensitivity charge detection portion and converted there into voltage signals. As a result, the CCD type imaging device has a higher signal-to-noise (S/N) ratio and a larger output voltage.
However, in order to meet the demand that such an imaging device should be smaller-sized and have a larger number of pixels, the size of a pixel to be used should be smaller and the amount of charge that can be transferred by a CCD should be reduced. Consequently, there have occurred serious problems such as a scale-down of the dynamic range, a significant increase of the power consumption, and the like. Because a larger amount of load capacitance and a higher driving voltage are required to drive the entire CCD device by several phases of clocks, the power consumption sharply increases as a larger number of pixels are used.
In order to overcome the above problems, an amplification type solid-state imaging device has been proposed, where signal charge generated in each pixel is not directly read, but a signal is first amplified in each pixel and read via a scanning circuit. By amplifying the signal in each pixel, the signal is no more limited, providing a wider dynamic range than the CCD type device. Moreover, only a horizontal line and a vertical line corresponding to a selected pixel from which a signal is to be read can be driven, and the required driving voltage is low. This reduces the power consumption compared with the CCD device.
Transistors are generally used for the above signal amplification in each pixel. Among various types of transistors such as a SIT, a bipolar type transistor, and a FET (a MOSFET and a junction type FET), a FET is advantageously used in consideration of the construction of the entire device since it is easy in construction to use a MOSFET for a scanning circuit for signal readout. (While a SIT and a bipolar type transistor are formed in the depth direction, a FET is formed in the plane direction, which facilitates the fabrication of the transistor).
FIG. 11A is a partial plan view of an amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called twin gate MOS image sensor (TGMIS) type. This type of the element has been proposed in Japanese Patent Application No. 6-303953 by the Applicant of the present application, which was published as Japanese Laid-Open Patent Publication No. 8-78653 on Mar. 22, 1996. FIG. 11B is a sectional view taken along line A-A' of FIG. 11A.
Referring to FIG. 11B, first gate electrodes 2 and second gate electrodes 3 are formed on a p-type semiconductor substrate 1 via an insulating film. Well layers 4 are formed in regions of the surface area of the semiconductor substrate 1 located directly under the first gate electrodes 2. Source regions 5 and drain regions 6 made of n+ diffusion layers are formed in the surface areas of the well layers 4 to constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate.
Referring to FIG. 1A, each first gate electrode 2 surrounds the source region 5 of each MOS type transistor, forming a pixel. Such pixels are arranged in the horizontal and vertical directions. The first gate electrodes 2 of horizontally adjacent pixels are connected to each other via horizontal connecting sections 2a. The second gate electrodes 3 are formed directly under the horizontal connecting sections 2a. Each drain region 6 surrounds the first gate electrode 2 and the second gate electrode 3 of each pixel.
Drain terminals VD are connected to the drain regions 6, while signal read terminals VS are connected to the source regions 5 via signal lines (column lines) connected to respective columns of pixels aligned in the vertical direction. Control terminals VGA are connected to the first gate electrodes 2, while control terminals VGB are connected to the second gate electrodes 3.
With the above configuration, a light energy h.nu. incident via each first gate electrode 2 causes pairs of electrons and holes to be generated in the transistor by photoelectric conversion. While electrons flow into the drain region 6, holes are confined by a barrier formed in the middle of the n-type well layer and a barrier formed under the second gate electrode 3 to become signal charge accumulated at the semiconductor/insulating film interface of the n-type well layer 4. The potential in the n-type well layer 4 changes depending on the amount of the accumulated signal charge. The amount of this change in the potential is read via the signal read terminal VS as a change in the source potential and output as a pixel signal.
The signal charge is drained in a reset operation after the above signal read operation. This can be easily achieved by lowering the potential barrier under the second gate electrode 3 to allow the accumulated signal charge to flow transversely toward the region located under the second gate electrode 3 and then vertically toward the p-type semiconductor substrate 1 as shown by an arrow 7 in FIG. 11B.
FIG. 12A is a partial plan view of another amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called surface reset type obtained by improving the above TGMIS type. This type of imaging element has been proposed in Japanese Patent Application No. 8-19199 by the Applicant of the present application. FIG. 12B is a sectional view taken along line A-A' of FIG. 12A.
Referring to FIGS. 12A and 12B, n-type semiconductor well layers 4 are formed in the surface area of a p-type semiconductor substrate 1. First gate electrodes 2 which are to be part of first gate regions are formed on the n-type semiconductor well layers 4, while second gate electrodes 3 which are to be part of second gate regions are formed on the exposed portions of the p-type semiconductor 1 located adjacent to the n-type semiconductor well layers 4. P-type low-resistance surface reset drains 8 are formed in the second gate regions between the adjacent n-type semiconductor well layers 4 before the formation of the second gate electrodes 3, to secure regions where potential barriers are formed by the second gate electrodes 3. Thereafter, n.sup.+ -type diffusion layers are formed for sources 5 and drains 6 which constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate. The reset drains 8 are formed in the surface area of the semiconductor substrate 1 under the second gate electrodes 3.
With the above configuration, a light energy h.nu. incident via each first gate electrode 2 causes pairs of electrons and holes to be generated in a photoelectric conversion region of the n-type semiconductor well layer 4 by photoelectric conversion. While electrons flow into the drain region, holes are confined by a barrier formed in the middle of the n-type semiconductor well layer 4 and a barrier formed under the second gate electrode 3 to become signal charge accumulated at the semiconductor/insulating film interface of the first gate region. The potential in the n-type semiconductor well layer 4 changes depending on the amount of the accumulated signal charge. The amount of this change in the potential is read as a potential change in the source 5 and output as a pixel signal.
The signal charge is easily drained in the reset operation by lowering the potential barrier under the second gate electrode 3 to allow the accumulated signal charge to flow into the reset drain 8 via a route shown by an arrow 7 in FIG. 12B. In this imaging device, the accumulated charge can be completely drained without influence of a potential ridge 107 formed in the middle between the semiconductor surface of the second gate region and the p-type semiconductor substrate 1. As for the potential ridge 107, refer to the aforementioned patent application.
Referring to FIG. 12A, each first gate electrode 2 surrounds the source region 5 of each MOS type transistor, forming a pixel. Such pixels are arranged in the horizontal and vertical directions, and the first gate electrodes 2 of horizontally adjacent pixels are connected to each other via horizontal connecting sections 2a. The second gate electrodes 3 are formed directly under the horizontal connecting sections 2a. Each drain region 6 surrounds the first gate electrode 2 and the second gate electrode 3 of each pixel.
Drain terminals VD are connected to the drain regions 6, while signal read terminals VS are connected to the source regions 5 via signal lines (column lines) connected to respective columns of pixels aligned in the vertical direction. Control terminals VGA are connected to the first gate electrodes 2, while control terminals VGB are connected to the second gate electrodes 3.
FIG. 13A is a partial plan view of yet another amplification type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called trench type obtained by improving the above TGMIS type from another aspect. This type of imaging element has been disclosed in Japanese Patent Application No. 8-19200 by the Applicant of the present application. The configuration of this amplification type solid-state imaging device is the same as those shown in FIGS. 11A and 12A except for the formation of a trench structure in a portion between each second gate region and the adjacent drain region, and thus detailed description thereof is omitted. FIG. 13B is a sectional view taken along line A-A' of FIG. 13A.
Referring to FIGS. 13A and 13B, n-type semiconductor well layers 4 are formed in the surface area of a p-type semiconductor substrate 1. First gate electrodes 2 which are to be part of first gate regions are formed on the n-type semiconductor well layers 4, while second gate electrodes 3 which are to be part of second gate regions are formed on the exposed portions of the p-type semiconductor 1 located adjacent to the n-type semiconductor well layers 4. Then, n.sup.+ -type diffusion layers are formed for sources 5 and drains 6 which constitute respective MOS type transistors together with the corresponding first gate electrodes 2 as a gate.
The TGMIS type amplification type solid-state imaging device shown in FIGS. 11A and 11B has a problem such that, as the width of the second gate electrode becomes smaller with the reduction of the pixel size, a three-dimensional potential ridge is formed on a route for the drainage of the accumulated charge due to the potential applied to the source and the drain. This potential ridge prevents the accumulated charge from being completely drained into the semiconductor substrate.
In the trench-type device, a trench structure 9 is formed adjacent to the second gate region to suppress the formation of such a potential ridge. This makes it possible to spatially lower the potential applied to the source 5 and the drain 6 and thus secure a channel through which the accumulated charge flows into the semiconductor substrate 1.
The trench structure is not necessarily formed over the entire region adjacent to the second gate region, but may be formed only over a portion of the region since the accumulated charge can be completely drained by securing such a portion formed as a reset drain under the second gate region.
In the reset operation, a high voltage VGA(H) which is, for example, the same as that applied when signal charge is accumulated, is previously applied to the first gate electrode 2. An intermediate voltage VGA(M) which is, for example, the same as that applied when signal charge is accumulated, is applied to the second gate electrode 3. At this time, the surface potential under the second gate electrode 3 is sufficiently lower than the surface potential of the n-type semiconductor well layer 4 obtained when no signal exists. This allows all signal charge (holes) in the surface area of the n-type semiconductor well layer 4 to flow into the p-type semiconductor substrate 1 through the potential barrier gate under the second gate electrode 3. In other words, the reset operation is effected.
At this time, thanks to the existence of the trench structure 9, there is formed no potential ridge which tends to be formed in the middle of the region under the second gate electrode 3 preventing the accumulated charge from being drained.
FIG. 14A is a plan view of yet another application type solid-state imaging device, showing pixels of amplification type solid-state imaging elements of a so-called bulk drain MOS image sensor (BDMIS) type. This type of imaging element has been disclosed in Japanese Patent Application No. 7-51641 by the Applicant of the present application. FIG. 14B is a part of a sectional view taken along line A-A' of FIG. 14A.
Referring to FIG. 14B, n-type wells 4 are formed in the surface area of a p-type semiconductor substrate 1 so that the surface thereof is on the same level as a principal surface 11 of the p-type semiconductor substrate 1. A p.sup.+ -type semiconductor region 5 is formed in the surface area of each well 4 so that the surface thereof is on the same level as the principal surface 11. A first gate electrode 2 is formed on the well 4 excluding the area where the semiconductor region 5 is formed via an insulating film. A second gate electrode 3 is formed on the exposed surface of the semiconductor substrate 1 adjacent to the well 4 via the insulating film. The surface area of the well 4, the insulating film, and the first gate electrode 2 constitute a first gate region. Likewise, the exposed surface area of the semiconductor substrate 1, the insulating film, and the second gate electrode 3 constitute a second gate region.
When an appropriate voltage is applied to the first gate electrode 2, a p-channel is formed in the surface area of the first gate region for the flow of holes which are minor carriers. When an appropriate voltage is applied to the second gate electrode 3, the entire portion of the semiconductor substrate 1 located under the second gate electrode 3 as well as the surface area of the second gate region form a p-channel. Under the above conditions, when a voltage V.sub.D is applied to the semiconductor substrate 1 and a voltage V.sub.S is applied to the semiconductor region 5, a channel for flowing holes is formed between the semiconductor substrate 1 and the semiconductor region 5. A current thus flows through this channel as shown by a solid-line arrow in FIG. 14B.
With the above configuration, a light energy h.nu. incident via the first gate electrode 2 causes pairs of electrons and holes to be generated in the portions of the well 4 and the semiconductor substrate 1 located under the first gate electrode 2 by photoelectric conversion. The holes flow into the semiconductor region, while the electrons are accumulated in a potential well formed in the middle of the well 4 as signal charge. The electrons used as the signal charge are major carriers in the well 4. The potential at the well 4 and thus the potential at the surface area of the first gate region change depending on the amount of the accumulated signal charge.
Consequently, the current flowing between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of the accumulated signal charge. Thus, by keeping a predetermined current flow between the semiconductor substrate 1 and the semiconductor region 5, the potential between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of accumulated signal charge. By keeping a predetermined potential between the semiconductor substrate 1 and the semiconductor region 5, however, the current flowing between the semiconductor substrate 1 and the semiconductor region 5 changes depending on the amount of accumulated signal charge. In this way, a first active element is formed between the semiconductor substrate 1 and the semiconductor region 5 having a channel composed of the surface areas of the first gate region and the second gate region. The electric characteristics of this active element change depending on the amount of accumulated signal charge.
A reset drain region 10 is also formed at the surface area of the semiconductor substrate 1 so that the surface thereof is on the same level as the principal surface 11. The reset drain region 10 is in contact with the surface area of the second gate region on the side opposite to the first gate region. An appropriate voltage is applied to the second gate electrode 3 to lower the potential barrier in the surface area of the second gate region. Then, the signal charge accumulated in the well 4 flows into the reset drain region 10 via a route shown by a dotted-line arrow in FIG. 14B. In this way, a second active element is formed between the well 4 and the reset drain region 10 having a channel composed of the surface area of the second gate region, realizing the drainage of the signal charge.
A plurality of amplification type solid-state imaging elements as shown in FIG. 14B are arranged in a matrix as shown in FIG. 14A. Rows of the first gate electrodes 2 aligned in the horizontal direction are commonly connected to respective clock lines VGA(i), VGA(i+1), . . . Likewise, rows of the second gate electrodes 3 aligned in the horizontal direction are commonly connected to respective clock lines VGB(i), VGB(i+1), . . .
The semiconductor region 5 which serves as a source is formed in the center of the first gate region of the well 4 of each amplification type solid-state imaging element. Columns of the semiconductor regions 5 aligned in the vertical direction are commonly connected to respective signal lines VS(j), VS(j+1), . . . The semiconductor substrate 1 itself is used as the drain of each transistor, which is therefore not shown in FIG. 14A.
FIG. 15 is a schematic view in combination of an equivalent circuit diagram and a block diagram illustrating a configuration of an amplification type solid-state imaging device using the amplification type solid-state imaging elements of the TGMIS type shown in FIGS. 11A and 11B.
Referring to FIG. 15, amplification type solid-state imaging elements (pixels) 11-11, 11-12, . . . 11-1n, 11-21, . . . , 11-mn are arranged in a horizontal (X) direction and a vertical (Y) direction to form a matrix. Terminals of the first gate electrodes 2 of rows of the amplification type solid-state imaging elements aligned in the X direction are connected to a first vertical scanning circuit 13 via respective first scanning lines 12-1, 12-2, . . . , 12-m. Terminals of the second gate electrodes 3 of rows of the amplification type solid-state imaging elements aligned in the X direction are connected to a second vertical scanning circuit 15 via respective second scanning lines 14-1, 14-2, . . . , 14-m. The signal read operation and the reset operation are conducted for each horizontal row of pixels by sequentially selecting each horizontal row of pixels via the first and second vertical scanning circuits 13 and 15.
Terminals of source regions 5 of columns of the amplification type solid-state imaging elements aligned in the Y direction are connected to respective column lines 16-1, 16-2, . . . , 16-n. The column lines 16-1, 16-2, . . . , 16-n are commonly connected to a video line 18 via respective column selective transistors 17-1, 17-2, . . . , 17-n. The video line 18 is grounded via a fixed current source load 19 while being connected to a signal output terminal 20. Control terminals of the column selective transistors 17-1, 17-2, . . . , 17-n are connected to a horizontal scanning circuit 21 so that the respective column selective transistors 17-1, 17-2, . . . , 17-n are sequentially selected and driven based on a control signal sent from the horizontal scanning circuit 21. The drain regions 6 of the amplification type solid-state imaging elements 11-11 to 11-mn are commonly connected, and a predetermined voltage is applied to the drain regions 6.
Thus, the above amplification type solid-state imaging device adopts a source/gate selection method, where columns of the pixels 11-11 to 11-mn are sequentially selected for each selection of a row of the pixels, and output signals of the respective selected pixels are sequentially read from the signal output terminal 20 via the video line 18.
The operation of the above solid-state imaging device will be described with reference to FIG. 16.
FIG. 16 is a timing chart showing the waveforms of signals used in the amplification type solid-state imaging device. The first vertical scanning circuit 13 outputs a first scanning pulse .phi.GI.sub.i to an i-th first scanning line 12-i. The second vertical scanning circuit 15 outputs a second scanning pulse .phi.GII.sub.i to an i-th second scanning line 14-i. The horizontal scanning circuit 21 outputs a signal read control pulse .phi.S.sub.j to a j-th column line 16-j.
First, the first vertical scanning circuit 13 sequentially outputs first scanning pulses (.phi.GI.sub.1, .phi.GI.sub.2, . . . , .phi.GI.sub.m of a low level VG(L) or a high level VG(H) in this order to the first gate electrodes 2 of the respective horizontal rows of pixels via the corresponding first scanning lines 12-1, 12-2, . . . , 12-m. Simultaneously, the second vertical scanning circuit 15 sequentially outputs second scanning pulses .phi.GII.sub.1, .phi.GII.sub.2, . . . , .phi.GII.sub.m of a low level VRG(L) or a high level VRG(H) in this order to the second gate electrodes 3 of the respective horizontal rows of pixels via the corresponding second scanning lines 14-1, 14-2, . . . , 14-m. At this time, the combination of the VG(H) of the first scanning pulse .phi.GI.sub.i and the VRG(H) of the second scanning pulse .phi.GII.sub.i is set in a signal read scanning period .tau.H for an i-th horizontal row of pixels. The combination of the VG(H) of a first scanning pulse .phi.GI.sub.(i+1) and the VRG(L) of a second scanning pulse .phi.GII.sub.(i+1) is set in a blanking period .tau.BL which starts from the end of the scanning of the i-th horizontal row of pixels and ends at the start of the scanning of the next (i+1)th row of pixels.
During the signal read scanning period .tau.H for the i-th row of pixels, the column selective transistors 17-1 17-2, . . . , 17-n are sequentially turned on with the signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n output from the horizontal scanning circuit 21. With this sequential activation of the column selective transistors, pixel signals which have been read from the amplification type solid-state imaging elements onto the corresponding column lines 16-1, 16-2, . . . , 16-n are sequentially read onto the video line 18. The signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n as the horizontal scanning signals supplied to the gate terminals of the column selective transistors 17-1, 17-2, . . . , 17-n are signals for sequentially selecting the column lines. The voltage values of these signals are set so that, when the signal level is low, a transistor among the column selective transistors 17-1, 17-2, . . . , 17-n which has received the low-level voltage is turned off, while, when the signal level is high, a transistor which has received the high-level voltage is turned on.
The i-th horizontal row of the amplification type solid-sate imaging elements are all reset at a time when the first scanning pulse .phi.GI.sub.i becomes the high level VG(H) and the second scanning pulse .phi.GII.sub.i becomes the low level VRG(L). This reset operation is conducted during the blanking period .tau.BL.
In this way, pixel signals are sequentially read from each horizontal row of pixels to obtain a field of video signals, and then reset.
Hereinbelow, the signal read operation and the reset operation for the first horizontal row of pixels will be described as an example.
Referring to FIG. 16, when the first scanning pulse .phi.GI.sub.1 output from the first vertical scanning circuit 13 becomes the high level VG(H) and the second scanning pulse .phi.GII.sub.1 output from the second vertical scanning circuit 15 becomes the high level VRG(H), the first row of the amplification type solid-state imaging devices 11-11, 11-12, . . . , 11-1n connected to the first scanning line 12-1 and the second scanning line 14-1 are selected to allow the pixel signals of the first row of the pixels to be read onto the column lines 16-1, 16-2, . . . , 16-n. As the column selective transistors 17-1, 17-2, . . . , 17-n are sequentially turned on in this order with the signal read control pulses .phi.S.sub.1, .phi.S.sub.2, . . . , .phi.S.sub.n output from the horizontal scanning circuit 21, the pixel signals on the column lines 16-1, 16-2, . . . , 16-n are sequentially output from the signal output terminal 20 of the video line 18 via the column selective transistors 17-1, 17-2, . . . , 17-n. The first row of the amplification type solid-state imaging elements are then all reset at a time when the first scanning pulse .phi.GI.sub.1 keeps the high level VG(H) and the second scanning pulse .phi.GII.sub.1 becomes the low level VRG(L). The above signal read operation and the reset operation are repeated for the second and subsequent rows of pixels until one field of video signals are obtained.
According to the above amplification type solid-state imaging device, a potential change corresponding to the amount of signal charge generated by photoelectric conversion in the region under the first gate electrode 2 of each amplification type solid-state imaging element is read onto the corresponding column line 16 as a source potential. The source potential is kept unchanged and fixed as a pixel signal by charging parasitic capacitances on the column line 16 and the video line 18 by the fixed current source load 19, and output to the video line 18 via the corresponding column selective transistor 17. Since the capacitance of each amplification type solid-state imaging element is small, in order to output the exact potential at the region under the first gate electrode 2 to the column line 16 as a pixel signal, the current supplied from the constant current source load 19 should be as small as about 100 nA or less. In other words, if the current supplied from the constant current source load 19 is large, the parasitic capacitances on the column line 16 and the video line 18 are sufficiently charged, preventing delay in signal readout. However, this increases the potential at the region under the first gate electrode 2, preventing the exact potential from being output onto the column line 16 as a pixel signal. Conversely, if the current supplied from the constant current source load 19 is too small, the parasitic capacitances on the column line 16 and the video line 18 are not sufficiently charged. This dulls the signal waveform by the time constant of the parasitic capacitances, causing delay in signal readout.
In the above amplification type solid-state imaging device, only the constant current source load 19 connected to the video line 18 is provided to cover all the amplification type solid-state imaging elements formed in a matrix. This is insufficient in supplying charge to the parasitic capacitances of all the column lines 16 and the video line 18, degrading the video signal read response. Moreover, if an electric circuit is intended to be connected downstream of the video line 18, it is less likely for the video signals obtained from the amplification type solid-state imaging elements to be output at high speed.
The amplification type solid-state imaging device using the amplification type solid-state imaging elements of the TGMIS type was described hereinbefore. The same problems as those described above also arise when the solid-state imaging elements of the surface reset type, the trench type, and the BDMIS type are used instead of the TGMIS type.

Amplification type solid-state imaging device


A method and apparatus is provided for forming an elongated solder joint between two soldered substrates of an electronic module by applying a controlled separating force between the two soldered substrates during and/or after heating of the module. The solder joints are plasticized, preferably to the molten state above the liquidus temperature, and are thereby stretched and the module is then cooled to solidify the stretched joints. An apparatus and method are provided which preferably uses a vacuum device as the separating force to stretch the existing solder joints to the desired solder height and configuration which is preferably an hour-glass shape.

1. Field of the Invention
This invention relates generally to electrically and mechanically interconnecting one electronic component to another electronic component to form an electronic assembly or module and, in particular, to stretching or otherwise elongating the solder joints of an existing module to form elongated solder joints having enhanced mechanical and electrical integrity and reliability.
2. Description of Related Art
Forming an electronic package assembly whereby an electrical component such as an integrated circuit chip is electrically connected to a substrate such as a card, or board, another chip or another electronic part is well-known in the art. Surface mount technology (SMT) has gained acceptance as the preferred means of joining electronic package assemblies. The following description for convenience will be directed to joining ceramic electronic components such as multilayer ceramic components as exemplified by integrated circuit chips to printed circuit cards or boards.
Multilayer ceramic electronic components are typically joined together by solder balls on a surface of one of the electronic components to corresponding pads on the surface of the other component. Control Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wire bonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer ceramic substrate or board pads on the chip are electrically or mechanically connected to corresponding pads on the other substrate by a plurality of electrical connections such as solder bumps. The integrated circuit chips may be assembled in an array such a 10.times.10 array.
In the C4 interconnect technology, a relatively small solder bump is attached to pads on one of the components being joined. The electrical and mechanical interconnects are then formed by positioning the corresponding pads on the other electronic component adjacent the solder bumps and reflowing the bumps as elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip bump pattern to the corresponding substrate pads.
A myriad of solder structures have been proposed for the surface mounting of one electronic structure to another. Typical surface mount processes form the solder structures by screening solder paste on conductive, generally metallic pads exposed on the surface of the first electronic structure or substrate. A stencil printing operation is used to align the contact mask to the pads. The solder paste is reflowed in a hydrogen atmosphere and homogenizes the pad and brings the solder into a spherical shape. The solder spheres on the substrate are then aligned to corresponding pads on the electronic structure or board to be connected thereto. After alignment, the substrate and board go through a reflow operation to melt the solder and create a solder bond between the corresponding pads on the substrate and other electronic component. The interconnection is typically in a form of a double truncated sphere as shown in FIG. 3.
Other known surface mount technology uses solder balls rather than solder paste to provide the solder connecting structures. By using solder balls, a more exact and somewhat greater quantity of solder can be applied than from screening. The solder balls are aligned and are held to a substrate and melted to form a solder joint on a conductive pad of the substrate. As before, the substrate with the newly joined solder balls is aligned to the board to be connected therewith and the solder balls are then reflowed to form a solder bond between the two substrates. The use of a copper ball surrounded by eutectic solder is also used as a solder joint structure for attaching a multilayer ceramic (MLC) substrate to a PC laminate wherein the ball serves as a standoff.
C4 joint technology, commonly referred to as ceramic ball grid array technology (CBGA), offers advantages of low cost, and a low inductance surface mounting interconnection. However, a thermal expansion mismatch between the chip and substrate will cause a shear displacement to be applied on each solder connection. Over the lifetime of a module, this leads to an accumulated plastic deformation and decreases the lifetime of the module. The typical solder joint having the shape of a doubly truncated sphere which is truncated at each pad is known to have a limited lifetime due to the thermal mismatch between the substrates and the shape of the bump. It is known that changes in shape away from a spherical segment can produce enhanced mechanical properties and testing has shown an order of magnitude difference in fatigue life between an hour-glass shape and a barrel-shape (double truncated spherical) joint. The fracture location of the hour-glass joint shifted to the center of the joint instead of at the pad-joint interface.
Stretched solder joints have been fabricated by a number of techniques including using different solders on the same chip. Solder columns have also been stacked to achieve improved fatigue life. Two solder alloys have been used in combination wherein the surface tension of a larger bump is used to raise and stretch the smaller area of the joints. Another approach involves stacking C4 bumps using polyimide interposer, but this technique adds considerable cost and manufacturing complexity without improved benefit.
A centrifugal force technique has also been employed wherein modules having C4 solder joints are heated and spun such that the C4s are elongated. This technique has obvious manufacturing difficulties when using large printed circuit cards. Brackets attached to one of the substrates has also been used to stretch the C4 joints. Basically, the bracket, when activated by heat or other means, raises one of the substrates in the z-axis stretching the C4 connection. The bracket, however, becomes an integral part of the final structure requiring the packaging design to incorporate the bracket and related fixturing.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of forming an elongated solder joint between two solder interconnected substrates in an electronic module to enhance the mechanical and electrical integrity and reliability of the module.
It is another object of the present invention to provide an apparatus for forming an elongated solder joint between two solder interconnected substrates of an electronic module to enhance the mechanical and electrical integrity and reliability of the module.
A further object of the invention is to provide electronic modules having solder joints having enhanced mechanical and electrical integrity and reliability.
It is yet another object of the present invention to provide an electronic component assembly or module made using the method and apparatus of the invention.
Other objects and advantages of the invention will be readily apparent from the description.

Ceramic ball grid array using in-situ solder stretch

International Business Machines Corporation


An air bag assembly in a vehicle having an inflator for generating inflation gas and an air bag cushion deployable upon generation of gas by the inflator. The air bag cushion includes a first inflatable portion which is proximal to the inflator for cushioning the torso of the vehicle occupant. The air bag cushion further includes a second inflatable portion distal from the inflator for cushioning the head of the vehicle occupant. A plurality of expansion restraining elements extend from opposing lateral sides of the air bag cushion at differing latitudes along the air bag cushion between the first and second inflatable portions. The expansion restraining elements extend partially but not completely across the width of the air bag cushion so as to partially restrict the flow of inflation gas from the first inflatable portion into the second inflatable portion while defining the flow path of the inflation gas between the first and second inflatable portions.

It is well known in motor vehicles to provide an air bag assembly for the protection of a vehicle occupant. Such air bag assemblies typically include an inflatable cushion structure in fluid communication with a gas emitting inflator. Upon the occurrence of predetermined vehicle conditions, such as deceleration exceeding a certain level, a signal is sent via appropriate sensors to the gas emitting inflator thereby causing the inflator to discharge gas into the air bag cushion thereby forcing the air bag cushion outwardly from a stored position into an operative position between the occupant to be protected and the interior portions of the vehicle against which the occupant might otherwise come in contact. The presence of the inflated air bag cushion between the occupant and the interior portions of the vehicle provides a cushioning effect as the occupant impacts the inflated cushion thereby dissipating the kinetic energy of the occupant in a controlled manner.
It is also known to provide an air bag assembly for side impact protection of a vehicle occupant. The prior art has disclosed side impact air bag assemblies which have either one cushion or a plurality of cushions which deploy to protect the head and torso portions of the vehicle occupant. The protection of the vehicle occupants against side impact injury may be desired in a large number of different types of vehicles wherein the interiors of such vehicles may be substantially different. While the prior art configurations of side impact devices have been generally useful in the protection of occupants, the method of establishing the head and torso protection portions of the cushion have not been highly adaptable to a large number of different categories of vehicles with different interior configurations.


A computer server supporting a social networking application that has multiple users, each user having a unique social networking application account identifier, is used for generating and managing an informational site accessible to the multiple users. Upon receipt of an informational site establishment request from a first client device, the informational site establishment request including a social networking application account identifier of a user of the first client device, the computer server establishes, according to the informational site establishment request, an informational site corresponding to the social networking application account identifier. The computer server then publishes a link to the informational site to users associated with a plurality of social networking application account identifiers of the social networking application, enabling the users to access the informational site from their accounts of the social networking application in the form of instant message exchanges.

With the extensive development of smart phones and tablet computers, the mobile Internet has a wide user basis. Mobile social networking application becomes a critical application of the mobile Internet and has a large number of users. With the user of the mobile social networking application as a target, information releasing, marketing, media propagation, simple interactions on the target already become an important way of applications such as marketing and information releasing. When information releasing is performed through a mobile social networking application, a public account often needs to be registered, and information releasing, business marketing, brand promotion, and the like are performed by using the public account. However, on a mobile social networking platform, if it is required to establish a mobile social networking site on a public account of a social networking application and use the mobile social networking site, an end user is required to have its own server or a virtual machine, a library name, bandwidth, and even hardware devices for providing backend services such as a database, and is also required to design, develop, and test programs for the mobile social networking site, and then file an application and establish a connection to a mobile social networking platform, which is a complicated informational site establishment process and requires large investment.

Method and system for managing an informational site using a social networking application

TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED


In some embodiments, methods of producing monoolefins include contacting an olefin stream with a polar solvent to extract a highly unsaturated hydrocarbon from the olefin stream, followed by contacting the polar solvent with a hydrogenation catalyst in the presence of hydrogen at conditions effective to hydrogenate the highly unsaturated hydrocarbon to a monoolefin. The monoolefin then desorbs from the polar solvent and enters the purified olefin stream, allowing the polar solvent to be recycled. In other embodiments, monoolefin production systems include an extraction-hydrogenation zone for performing the extraction and hydrogenating steps in situ. In alternative embodiments, the hydrogenation zone is disposed downstream from the extraction zone.

Monoolefins such as ethylene and propylene are often employed as monomers in preparing various polymers. Monoolefins may be produced by the thermal or catalytic cracking of refinery gas, ethane, propane, butane, and the like. Monoolefins produced in this manner usually contain acetylenes and diolefins that adversely affect polymer production. Thus, to form a polymer grade monoolefin, the amount of acetylenes and diolefins in a monoolefin stream recovered is typically reduced to form a polymer grade monoolefin.
One technique that has been used to reduce the amount of acetylenes and diolefins in a monoolefin stream involves hydrogenating the acetylenes and diolefins in the gas phase to monoolefins using catalysts comprising palladium and an inorganic support. Unfortunately, this total gas phase hydrogenation process does not entirely eliminate the acetylenes and the diolefins from the monoolefin stream. Further, in some applications total gas phase hydrogenation units produce green oil as a side-product by oligomerizing the acetylenes and diolefins. As used herein, green oil refers to molecules having 6 or more carbon atoms per molecule that undesirably foul the hydrogenation catalyst, causing the catalyst to deactivate. The deactivation of the hydrogenation catalyst results in the catalyst having a lower activity and selectivity to monoolefins. Consequently, the cycle time of total gas phase hydrogenation units are shortened by the presence of such green oil. Thus, the hydrogenation catalyst frequently requires regeneration, causing the operation costs of the hydrogenation process to be very high. Another technique that has been employed to reduce the acetylene content in a monoolefin stream has been the extractive distillation of the acetylenes. The extracted acetylenes have less commercial value than ethylene.
Therefore, a need exists for a less expensive process that improves removal of acetylenes and diolefins from a monoolefin stream without experiencing much fouling and that results in conversion of the acetylene to higher value chemicals. That is, it is desirable to extend the catalyst life and increase the selectivity of the hydrogenation catalyst to monoolefins such as ethylene.

Methods and systems of producing monoolefins by the extraction-hydrogenation of highly unsaturated hydrocarbons


A method (200) is described for an electronic assembly (30). An electronic die (24) with a sacrificial layer (28) on its back (27) and electrical contacts (26) on its front (25) is temporarily attached by its front (25) to a substrate (32). The back (27) is over-molded by a first material (34) extending over the substrate (32). The substrate (32) is removed leaving the die contacts (26) and the first material (33, 34) exposed. Interconnect layer(s) (44, 64) are provided over the first material (33, 34) and the die (24), electrically coupled to the contacts (26). Further components (66) can be coupled to the upper-most interconnects (64, 53). A second material (68) is over-molded over the components (66) and upper-most interconnects (64, 53). Thinning the first material (34) exposes the sacrificial layer (28) for removal. The die back (27) and vias (70) in the first material (34) extending to the first interconnect layer (43-2) laterally outside the die (24) are filled with a conductor (72, 72′, 73), providing single surface electrical and thermal contact (73-1, 73-2), separated by just the die thickness from heat generating regions of the die (24).

Modular electronic assemblies containing interconnected semiconductor (SC) die and other components are much used. In many applications, especially those involving radio frequency (RF) operation, it is important that the very good ground connections and very good thermal connections be made to various electronic elements within the assembly. This is especially true for RF integrated circuits (ICs) and RF power amplifiers where efficient heat removal and low RF ground inductance are vital to achieving the desired performance. The challenge of achieving efficient heat removal and low ground inductance is especially difficult in electronic assemblies that are used in many consumer and industrial applications where the electronic assembly must be as compact as possible. For example, in consumer electronic products such as cellular telephones and personal digital assistants (PDAs), the electronic assemblies providing the desired functionality must be as thin as possible in so that the outer dimensions of the device, especially the thickness may be made as small as possible Accordingly, there is an ongoing need for manufacturing methods capable of efficiently providing very thin electronic assemblies with improved thermal properties and low connection impedance for attachment to a the circuit motherboard or tape of the finished device. Other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.


An intra nasal dispenser clip for aromatherapy and for dispensing fragrances or aromatically odorous medicine includes a bendable arcuate band extending between distal ends. The ends have a pair of hollow aroma or aromatically odorous medicine dispensing containers, with hollow fragrant aroma dispensing containers affixed thereat. The hollow aroma or aromatically odorous medicine dispensing containers applying the fragrant or medically active aroma directly within the nostrils of the person using the clip. The band contacts the respective right and left sides of a user's nasal septum, with the band wrapped around the distal end of the nasal septum. The arcuate band is gentle on the nasal septum due to the geometry of the arcuate band being a wide circular arc bottom spring member, with inflection points at either distal ends, from which shorter reversed circular arcs emerge with the hollow aroma-dispensing containers at their distal ends.

Aromatherapy is the traditional and scientific art and practice of using essential oils for the treatment of illness or to restore or enhance health, beauty, and well being. These essential oils are extracted from aromatic plants and herbs. Cedar Vale Company, an Internet supplier of essential oils (www.cedarvale.net) lists 177 such essential oils with therapeutic properties.
According to Dr. Kurt Schnaubelt, Director of the Pacific Institute of Aromatherapy, essential oils exert their therapeutic effect through pharmacological properties and small molecular size, which easily penetrate bodily tissues.
Although inhalation is the principal method of administration, using a few drops of essential oils on a handkerchief is not a well-controlled method of use. Furthermore, it is well known that several essential oils including anise, bitter almond, cedarwood, peppermint, sage, and wintergreen can be especially irritating to the skin.
While nasal clips are used in aromatherapy, most of the aromatherapy dispensers are "extra nasal" in that they deliver from outside the nostrils. For example, the "BREATHE RIGHT" strip, as described in U.S. Pat. Nos. 5,706,800 and 6,244,265, both of Cronk emits aromatherapy aromas, but only outside the nostrils.
The CNS "BREATHE RIGHT" strip bends around, and goes over the outside of, the nose, and emits fragrances therefrom in the vicinity of the nose. However, the CNS BREATHE RIGHT strip loses approximately 90% of the aromas to the air outside of the nose, where the aromas are emitted, not directly into the nostrils.
Among other patents for nasal administration of fragrances is U.S. Pat. No. 6,015,425 of the Applicant James Altadonna, Jr. herein describes a U-shaped nasal clip for delivering fragrances in malodorous environments, such as in a dental office or work site. As noted in Altadonna '425, dental patients often complain about foul odors associated with certain procedures. The source of the odor is generally acknowledged to be bacterial decay within the mouth due to high temperatures generated by the drilling of teeth. The present invention reduces or completely masks the unpleasant odors in a convenient and aggressive manner. However, in Altadonna '425, all of the spring force of the arcuate U-shaped band is directed at the inflection points of the opening points of the intra-nasal clip band against the nasal septum of the user.
Therefore, there is a need to provide an intra-nasal clip, which spreads out and deflects some of the impinging spring force of the intra-nasal clip away from where the nasal-clip impinges upon the nasal septum of the user.
Other nose clips are disclosed in U.S. Pat. No. Re. 35,408 of Petruson describes a resilient nasal clip that pushes outward against the nasal sidewalls to maximize the nostril openings, a feature not desired by the present invention.
Among other related patents include U.S. Pat. No. 6,325,475 of Hayes for a mechanical inhaler for aromatherapy, U.S. Pat. No. 6,399,192 of Pinna for a skin adhered patch with microcapsules, U.S. Pat. No. 3,655,129 of Seiner for slow release pads, U.S. Pat. No. 3,688,985 of Engel for making odor releasing pads, U.S. Pat. No. 3,994,439 of Van Breen for slow release air fresheners, U.S. Pat. No. 4,492,644 of Matsomoto for slow release perfumes, U.S. Pat. No. 4,808,466 of Kotani for deodorant sheets and U.S. Pat. No. 5,622,992 of Beck for aromatic products for nasal passage congestion.
Nasal administration and ingestion of medicines are also known, such as with inhalers administrating particles or nebulizers administering mists.
Among related patents for nasal administration of medicines include U.S. Pat. No. 6,051,244 of Perricone for nasal administration of a fructose diphosphate gel for treatment or preventing epidermal or mucosal aging and inflammation. U.S. Pat. No. 5,543,434 of Weg describes the nasal administration of a dry powder such as ketamine for treatment of pain. U.S. Pat. No. 6,391,340 of Malmqvist-Granlund describes nasal administration of dry powders for treating conditions of the nose, such as antihistamines, i.e., lotatidine and terfenadine, anti-inflammatories, i.e., steroids, anticholinergic agents, i.e. ipratropium bromide, thiotropium bromide, oxytropium bromide, and vasoconstrictors. Malmqvist-Granlund '340 also describes the nasal administration of dry powders for other classes of drugs, such as proteins, peptides such as insulin, hormones, etc., as well as mixtures of such drugs, and salts, sovates, hydrates and esters thereof. Moreover, Nastech Pharmaceutical Company, Inc. of New York, N.Y. produces nasally administered forms of apomorphine hydrochloride for sexual dysfunction, morphine gluconate as an opioid analgesic, scopalamine hydrobromide as an anti-motion sickness medicine, interferon alpha for treating cancer and hepatitis, interferon beta for treating relapsing forms of multiple sclerosis, somataropin for treating growth failure and triptans for treating migraine. In addition, nasal administered FLONASE® of GlaxoSmithKline, is a metered dose aqueous suspension of microfine fluticasone propionate for treating nasal inflammations. In addition, U.S. Pat. No. 6,342,478 of Frey describes nasal administration of fibroblast growth factors to the brain via the olfactory nerve for treating Alzheimer's disease.
However, the aforesaid nasal administrations of medicines are by direct contact from squirting or other pumping of the medicine directly into the nasal passage tissues, which may irritate nasal tissues.
Moreover, medicines may be delivered in aromatically odorous form, such as from a VAPORIZER® steam dispenser, but they require access to electricity and water, and restrict the mobility of the patient to the room in which the VAPORIZER® is located. Portable vaporizers are known, such as a mist inhaler described in U.S. Pat. No. 5,186,164 of Raghuprasad and U.S. Pat. No. 5,195,514 of Liu, but they still require mechanical and/or electrical components.
Other nose clips are known, but they are generally used to hold the nostrils closed, as in swimming or surgical procedures, as discussed in U.S. Pat. No. 4,231,360 of Zloczysti, and U.S. Pat. No. 4,445,508 of Lake.
To reduce malodorous mouth odors, various formulations in the form of tablets, liquids, or other medicaments are applied to the mucosol cavities of the user's mouth, such as disclosed in U.S. Pat. No. 4,303,648 of Witzel, U.S. Pat. No. 4,606,912 of Rudy, or U.S. Pat. No. 5,281,415 of Suzuki. But these cannot be applied during dental procedures, except by intermittent spraying or ingesting into the patient's mouth.
Furthermore, odor reducing filter masks are known, but these generally cover the whole face or the whole nose, 4s in U.S. Pat. No. 5,636,629 of Patterson for a filter mask
Other odor reducing filter masks which cover the face or the nostrils of the nose include U.S. Pat. No. 5,392,773 of Bertrand and U.S. Pat. No. 5,740,798 of McKinney for filter masks that cover and mask the outer nostril end of the nose. Masks which cover the whole nose include U.S. Pat. No. 5,243,708 of Vanuch and U.S. Pat. No. 5,697,105 of White.
Moreover, U.S. Pat. No. 5,636,628 of Barnum discloses a mask to counteract odors that includes a cloth substrate covering the nose and mouth of the user, wherein the cloth substrate is held over the face by ear pieces which tie around the ears.
U.S. Pat. No. 5,538,013 of Brannon describes a mask with a scenting means. However, the mask of Brannon '013 covers at least the whole nose of the user.
In addition, U.S. Pat. No. 5,503,167 of Wilson et al. discloses a face shield covering the whole face of a user, wherein the user holds the face shield by gripping a mouthpiece between the user's teeth.
Furthermore, U.S. Pat. No. 4,267,831 of Aguilar and U.S. Pat. No. 5,417,205 of Wang describe nasal air filters and medicament dispenser devices, wherein two medication dispensing tubes are provided, one for insertion into each nostril. The problem with Aguilar '831 and Wang '205 is that the cylindrical outer surfaces of each tube completely block each nostril, thus increasing discomfort and preventing normal breathing through the nostrils.
However, these face coverings or nose covering masks are bulky and interfere with normal breathing during dental procedures.


The present disclosure provides a bromination method for m-diamide compounds comprising reacting a compound represented by formula I with a brominating reagent in the presence of an oxidant to obtain a brominated product represented by formula II. The method adopts a special design of brominating reagents and reaction conditions to introduce a bromine atom at a specific site of the m-diamide compound, with 87.9 to 99.5% yield of a brominated product obtained by the reaction and higher than 91.8% purity. Therefore, the bromination method has a simple route, mild reaction conditions, high efficiency, and does not require complicated and cumbersome post-treatment processes; furthermore, raw materials used for the bromination reaction are readily available, costs of the brominating reagent are low, and the brominated product finally obtained has high yield and high purity, thus the method is a novel one with a broad application prospect.

Diamide insecticides belong to a new type of high-efficiency insecticides developed from the end of 1990s to the early 21st century. An advent of this type of insecticides marks an entry of chemical pesticides into a microtoxicity era. Its representative species include flubendiamide and chlorantraniliprole. With an increasing pressure of environmental protection and rising insecticidal resistance, existing diamide insecticides have been encountering many problems and pressures. Due to high toxicity to aquatic organisms, the United States cancelled the registration of flubendiamide on more than 200 crops in 2016, and China cancelled its registration on rice and banned the use of flubendiamide on rice crops from Oct. 1, 2018. Therefore, it is an urgent demand in the field of chemical pesticides to find a new type of insecticide with high efficiency, low toxicity, environmental friendliness and a new mechanism of action. M-diamide compounds represented by Broflanilide are increasingly becoming research hotspots of pesticide companies at home and abroad due to their characteristics such as unique action mechanism, novel action target and environmental friendliness.
M-diamide compounds represented by Broflanilide, which has a meta-formamide benzamide structure and an active metabolite of gamma-aminobutyric acid (GABA) gated chloride channel allosteric regulator, have higher selectivity to GABA and characteristics of broad spectrum and high efficiency. Guided by novel action mechanism of m-diamide insecticides, more pesticide chemical companies are committed to developing more types of new m-diamide insecticides that have fast-acting and high insecticidal activity at low doses.
CN104245665A discloses a method for producing an alkylated aromatic amide derivative, and specifically discloses a synthetic route of Broflanilide, that is, firstly obtaining 2-fluoro-3-(N-methylbenzamido)-N-[2-(trifluoromethyl)phenyl]benzamide through the reaction of 2-(trifluoromethyl)aniline, triethylamine, and 2-fluoro-3-(N-methylbenzamido)benzoylchloride, and then reacting 2-fluoro-3-(N-methylbenzamido)-N-[2-(trifluoromethyl)phenyl]benzamide with heptafluoroisopropyl iodide to give 2-fluoro-3-(N-methylbenzamido)-N-[2-(trifluoromethyl)-4-(heptafluoroisopropyl)phenyl]benzamide, which is finally brominated with bromobutadienamine (NBS) to give Broflanilide. However, in this synthetic route, the bromine source NBS used in the last step of bromination reaction is expensive, and the product yield is only 56%, which is not suitable for industrial applications.
In the method for preparing Broflanilide disclosed in EP2319830A1, an intermediate 2-bromo-4-heptafluoroisopropyl-6-trifluoromethylaniline is obtained by a bromination reaction between 4-(perfluoropropane-2-yl)-2-trifluoromethylaniline and NBS, with a yield of only 80%. Not only reaction conditions for subsequent preparation of m-diamide involve low temperature environment, harsh preparing process and complicated post-treatment, but the yield of the final product is only 70%, which make it difficult to be used for large-scale industrial production.
CN109497062A discloses a m-diamide compound, a method for preparing the same, and an application thereof. The m-diamide compound has not only a high insecticidal activity at a low dose, but good fast-acting properties. However, in preparation of the m-diamide compound, an intermediate 2-bromo-4-heptafluoroisopropyl-6-trifluoromethylaniline is used to prepare the in-diamide compound with a yield of only 13-28%. Moreover, the product ought to be purified by column chromatography. Costs of raw materials, equipments and time of the preparation method are high, which make the method not suitable for industrial scale-up.
In summary, for the existing preparation processes of m-diamide compounds, bromination reagents required for the bromination reaction are expensive, yields of brominated products are low, synthetic routes for preparing the final target product m-diamide compounds are long, reaction conditions are difficult to control, and post-treatment procedures are complicated. Thus the industrial production of m-diamide compounds has problems of high costs of raw materials, equipments and time.
Therefore, it is a research focus in this field to develop a bromination method for m-diamide compounds with high yield, low cost, simple synthetic route and mild reaction conditions to realize a large-scale industrial production of in-diamide insecticides.

Bromination method for m-diamide compounds


The adhesion between metal foil serving as a current collector and a negative electrode active material is increased to enable long-term reliability. An electrode active material layer (including a negative electrode active material or a positive electrode active material) is formed over a base, a metal film is formed over the electrode active material layer by sputtering, and then the base and the electrode active material layer are separated at the interface therebetween; thus, an electrode is formed. The electrode active material particles in contact with the metal film are bonded by being covered with the metal film formed by the sputtering. The electrode active material is used for at least one of a pair of electrodes (a negative electrode or a positive electrode) in a lithium-ion secondary battery.

Examples of the secondary battery include a nickel-metal hydride battery, a lead-acid battery, and a lithium-ion secondary battery.
Such secondary batteries are used as power sources in portable information terminals typified by mobile phones. In particular, lithium-ion secondary batteries have been actively researched and developed because capacity thereof can be increased and size thereof can be reduced.
Patent Document 1 discloses that a multilayer graphene flake or multilayer graphene flakes are wrapped around positive electrode active material particles or negative electrode active material particles to prevent dispersion of the positive electrode active material particles or the negative electrode active material particles and collapse of a positive electrode active material layer or a negative electrode active material layer. Multilayer graphene can maintain the bond to the positive electrode active material particles or the negative electrode active material particles.

Secondary battery and a method for fabricating the same

Semiconductor Energy Laboratory Co., Ltd.


Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.

Conventional processing techniques used in connection with silicon and silica containing integrated circuit chips often involve high processing temperatures of 600° C. or more. Most conventional integrated circuit chips have a substrate made of glass, quartz, or silicon, which can tolerate relatively high temperature processing. Such high temperatures are required by one or more processing techniques including, for example, silicon re-crystallization, wet oxidation, high temperature chemical vapor deposition, and dopant activation anneals.
There is a continuing trend in the semiconductor industry to shrink components on integrated circuit chips for smaller, faster computing devices. At this time, commercially available integrated circuit chips contain MOSFETs (metal oxide semiconductor field effect transistors) that are microns in width. As the chips and components thereon shrink, it is more important to account for certain physical properties, such as unwanted diffusion, crosstalk, adequate insulation (both electrical and temperature), coefficients of thermal expansion, short channel effects, leakage, critical dimension control, drain induced barrier lowering, and the like, when making circuit designs. Accordingly, new materials, new methods, and new design parameters are required to further this continuing trend.

Semiconductor device built on plastic substrate


A curio cabinet with gun storage comprises a curio cabinet and a hidden compartment. The curio cabinet is in the style of a traditional flatback-type curio cabinet and comprises a plurality of shelves and compartments. A main compartment of the curio cabinet comprises the rear hidden compartment. The hidden compartment is accessed through hinged doors in the main compartment. The hidden compartment provides a means to store firearms.

Gun owning and collecting are major interests to many Americans. Responsible owners of weapons, rifles, shotguns, handguns, knives, and the like typically keep their weapons locked and out of sight at all times. One (1) common way of doing this is to store the weapons in a gun rack, also known as a gun safe or gun cabinet.
Gun racks have proven to be very effective at storing weapons and at preventing accidental injuries. However, firearms are relatively expensive and a major gun collection can be worth significant money. The mere presence of a gun rack may alert others that firearms are present within a household. This can and has led to the theft of firearms.
Another problem with gun racks is that they tend to be rather large. Many households simply do not have available storage space in the house for a large gun rack in addition to the other furniture. Furthermore, while gun racks are useful, usually they are not particularly attractive furniture pieces (they can be however, usually at great cost). Therefore many gun racks are located within garages, basements, or other areas, which tend to make the contained firearms not readily available should quick access be required.
Accordingly, there exists a need for a way to safely and securely store firearms and other weapons without the disadvantages described above.
Curio cabinets are traditional pieces of furniture that are used to display cherished items. Such cabinets usually have ample shelving that can be versatility arranged. Curio cabinets are almost always "fine" furniture. That is, they are usually quality made from quality woods and other materials, they are given a superior finish, they are artistically pleasing to look at, and they usually improve the aesthetics of the room in which they are located. Curio cabinets often have features such as multiple beveled glass doors mounted on touch activated hinges, multiple glass shelves, quality interior lighting, and a polished exterior. While they are often rather tall and heavy, thus not easily moved, curio cabinets are almost always kept inside the home so that they and their contents can be appreciated.
Therefore, a technique of using a curio cabinet as a gun rack would be useful. Even more useful would be a technique of using a curio cabinet as a gun rack such that the weapons stored therein are readily available when needed. Beneficially, such a curio cabinet gun rack would hide the weapons from view and would not reveal to others that weapons were kept therein. Preferably, the depth of the curio cabinet would be obscured with mirrors.


The invention provides a device for selective molecular recognition, the device comprising a sensing portion, wherein said sensing portion includes a substrate having coated thereon a layer comprising a non-volatile, small molecule compound having at least two pendant and terminal unsaturated groups, each being functionalized with at least one halogen substituted alcohol or phenol functional group. The compound of the invention preferably has one of the following general formulae:

1. Field of the Invention
The present invention relates to the detection of noxious chemical species by means of a functionalized small molecule, i.e. non-polymeric sorbent compounds. More particularly, the invention relates to the detection of toxic or explosive chemical vapors, such as chemical agents or nitroaromatic species, by sorbent materials comprising small molecules with halogen substituted alcohol or phenol functional groups.
2. Description of Related Art
Determining and/or monitoring the presence of certain chemical species within an environment, e.g., pollutants, toxic substances and other predetermined compounds, is becoming of increasing importance with respect to such fields as health, environmental protection, resource conservation, and chemical processes. Devices for the molecular recognition of noxious species or other analytes typically include (1) a substrate and (2) a molecular recognition coating upon the substrate. These devices may be used, for example, in chemical vapor sensing or the selective separation of gases by gas chromatography. Small molecular recognition devices are described in Grate et al., Sensors and Actuators B, 3, 85–111 (1991) and Grate et al., Analytical Chemistry, Vol. 65, No. 14, Jul. 15, 1993, both of which are incorporated herein by reference.
Frequently, the substrate is a piezoelectric material or a waveguide, which can detect small changes in mass. One illustrative example of a device relying upon molecular recognition as a surface is known as a surface acoustic wave (SAW) sensor. SAW devices function by generating mechanical surface waves on a thin slab of a piezoelectric material, such as quartz, that oscillates at a characteristic resonant frequency when placed in a feedback circuit with a radio frequency amplifier. The oscillator frequency is measurably altered by small changes in mass and/or elastic modulus at the surface of the SAW device.
SAW devices can be adapted to a variety of gas-phase analytical problems by designing or selecting specific coatings for particular applications. The use of chemoselective polymers for chemical sensor application is well established as a way to increase the sensitivity and selectivity of a chemical sensor with respect to specific classes or types of analytes. Typically, a chemoselective polymer is designed to contain functional groups that can interact preferentially with the target analyte through dipole-dipole. Van der Waal's, or hydrogen bonding forces. For example, strong hydrogen bond donating characteristics are important for the detection of species that are hydrogen bond acceptors, such as toxic organophosphorus compounds. Increasing the density of available hydrogen bond acidic binding sites in the coating of a sensor results in an increase in sensitivity.
Chemoselective films or coatings used with chemical sensors have been described by McGill et al. in Chemtech, Vol. 24, No. 9, 27–37 (1994). The materials used as the chemically active, selectively absorbent layer of a molecular recognition device have often been polymers, as described in Hansani in Polymer Films in Sensor Applications (Technomic, Lancaster, Pa. 1995). For example, Ting et al. investigated polystyrene substituted with hexafluoroisopropanol (HFIP) groups for its compatibility with other polymers in Journal of Polymer Science: Polymer Letters Edition, Vol. 18, 201–209 (1980). Later, Chang et al. and Barlow et al. investigated a similar material for its use as a sorbent for organophosphorus vapors, and examined its behavior on a bulk quartz crystal monitor device in Polymer Engineering and Science, Vol. 27, No. 10, 693–702 and 703–15 (1987). Snow et al. (NRL Letter Report, 6210–884A) and Sprague et al. (Proceedings of the 1987 U.S. Army Chemical Research Development and Engineering Center Scientific Conference on Chemical Defense Research, page 1241) reported making materials containing HFIP that were based on polystyrene and poly(isoprene) polymer backbones, where the HFIP provided strong hydrogen bond acidic properties. These materials were used as coatings on molecular recognition devices, such as SAW sensors, and showed high sensitivity for organophosphorus vapors. However, both the parent polymers and the HFIP-containing materials were glassy or crystalline at room temperature. Because vapor diffusion is slowed in glassy or crystalline materials, the sensors produced were slow to respond and recover. Additional information is reported in Polym. Eng. Sci., 27, 693 and 703–715 (1987).
Grate et al. in Analytical Chemistry, Vol. 60, No. 9, 869–75 (1988), discloses a polymeric compound called "fluoropolyol" (FPOL), which is useful for detecting organophosphorus compounds. FPOL has the formula:
An HFIP-containing polymer based on a polysiloxane backbone was described and demonstrated to be a good hydrogen-bond acid by Abraham et al., "Hydrogen Bonding XXIX. The Characterisation of Fourteen Sorbent Coatings for Chemical Microsensors Using a New Solvation Equation", J. Chem. Soc., Perkin Trans. 2, 369–78 (1995). The polysiloxane backbone provided a material with a Tg well below room temperature, however, other physical properties were not shown.
Grate, U.S. Pat. No. 5,756,631, discloses the use of hexafluoroalcohol-substituted siloxane polymers having the structure:
wherein R2 has the formula —(CH2)m-1—CH═CH—CH2—C(CF3)2—OH, and n is an integer greater than 1.
Grate et al., U.S. Pat. No. 6,015,869 discloses a strongly hydrogen bonding acidic, sorbent oligomer or polymer having a glass-to-rubber transition temperature below 25° C. The polymer has (1) fluoroalkyl-substituted bisphenol segments containing interactive groups and (2) oligodimethylsiloxane segments. These siloxane polymers are said to provide improved coatings and vapor sorption compositions for chemical sensors that are sensitive, reversible and capable of selective absorptions for particular vapors, particularly the hydrogen bond accepting vapors, such as organophosphorus compounds. However, these are still polymeric materials and, like all polymers, they can vary significantly from batch to batch in precise composition, purity and yield.
The inventors have now discovered a class of small molecules, rather than siloxane polymers, that can, in fact, be combined with polymeric matrices to produce composite hydrogen bond acidic coatings for chemical sensor applications. Using small molecules that are highly functionalized can result in significant sensitivity improvements. The host polymer matrix may or may not be functionalized with hydrogen bond acid groups. Thus, the functionalized small molecules described herein can improve the sensitivity of a sensor coating by increasing the density of hydrogen bond acid groups within the coating material.
Further, the chemoselective small molecules of the invention exhibit improved sensitivity to vapors of organophosphorus and nitroaromatic species, and are thus also useful for detecting the presence of these toxic materials. Conventional explosives, such as trinitrotoluene (TNT), hexahydro-1,3,5-trinitro-1,3,5-triazine (RDX), and octahydro-1,3,5,7-tetranitro-1,3,5,7-tetrazocine (HMX), may be contained in unexploded munitions, e.g., buried below the surface of the ground. Such munitions exude or leak vapors of the explosive. These vapors are typically concentrated in the surrounding soil and then migrate to the surface where they can be detected by the compounds, devices and methods of the invention. A similar situation exists for unexploded ordnance (UXO) found underwater.

Functionalized small molecules for use in chemical sensors

Abstract: wherein A is a core moiety;

Abstract: B is a pendant and terminal unsaturated group;

Abstract: q is at least 1;

Abstract: r is at least 2;

Abstract: X is a linking group; and

Abstract: n is an integer designating the number of repeating units from 1 to 3, with the proviso that, if n is greater than 1, then the B groups differ from each other in at least two of the repeating units.

Abstract: The device is used to detect the molecules of a hydrogen bond accepting vapor such as an organophosphonate or nitroaromatic vapor.

The United States of America as represented by the Secretary of the Navy


Provided is a technology which enables further improvement of the accuracy of the determination in the pattern matching processing. A dictionary learning device 1 includes a score calculation unit 2 and a learning unit 3. The score calculation unit 2 calculates a matching score representing a similarity-degree between a sample pattern, which is a sample of a pattern which is likely to be subjected to a pattern matching processing, and a degradation pattern resulting from a degrading processing on the sample pattern. The learning unit 3 learns a quality dictionary based on the calculated matching score and the degradation pattern. The quality dictionary is a dictionary which is used in a processing to evaluate a degradation degree (quality) of a matching target pattern of being pattern of an object on which the pattern matching processing is carried out.

A pattern matching processing is a processing which determines whether or not a plurality of patterns targeted for the pattern matching processing are identical patterns. The pattern is face image, fingerprint image, speech-signal waveform or the like. This pattern matching processing is a technology known as a particularly important technology in a field of biometrics authentication.
An example of the pattern matching processing will be briefly described below. First, a matching score is calculated, the matching score represents how much two patterns targeted for the pattern matching processing are similar. As one of methods for calculating the matching score, there is a method in which the matching score is calculated by using, for example, a feature vector extracted from the pattern targeted for pattern matching processing and a preliminarily prepared feature-vector group which is called a discrimination dictionary. In most of cases, the discrimination dictionary is generated by machine learning using a large number of pattern examples.
After the matching score has been calculated in such a way as described above, the matching score is compared with a threshold value, and a matching result (that is, whether or not the two patterns targeted for the pattern matching processing are identical) is determined. In this way, the pattern matching processing is carried out.
By the way, as one of problems on the pattern matching processing, there exists a problem described below. The existing problem is a problem which is caused by a quality degradation of a pattern (in other words, unsharpness (indistinctness) of a pattern). That is, in a case where a degree of the quality degradation of the pattern is large, sometimes, information necessary to the pattern matching processing (for example, information representing features of a face, a fingerprint or the like) is lost. For example, in a case where facial images of persons targeted for matching processing are blurry and indistinct, a facial image of any one of the persons results in resembling facial images of the other ones of the persons. For this reason, in a face matching processing based on blurry facial images, although two facial images targeted for the pattern matching processing are not images of an identical person, an erroneous determination that the two facial images are images of an identical person is likely to be made.
In this regard, there has been proposed a method for estimating the qualities (degradation degrees) of patterns and performing the pattern matching processing to the patterns in view of information related to the estimated qualities. In PTL 1 (Japan Patent Application Laid-Open Publication No. 2010-129045), there is disclosed a technology which, in fingerprint matching processing, detects (determines) a blur of a fingerprint image as information for estimating the quality of each pattern. In PTL 2 (Japan Patent Application Laid-Open Publication No. 2011-002494), there is disclosed a technology which, in speech recognition processing, estimates a sound quality level as information estimating the quality of the pattern.
Further, in PTL 3 (Japan Patent Application Laid-Open Publication No. 2007-140823), there is disclosed a technology which performs the pattern matching processing in view of condition under which the pattern is photographed (for example, a lighting environment, a direction of a face, presence or absence of a wearing object (for example, sunglasses)).
Moreover, in PTL 4 (Japan Patent Application Laid-Open Publication No. 2006-072553), there is disclosed a technology which, in biometrics authentication, in a case where an input image is indistinct, performs the pattern matching processing after having corrected the image. Furthermore, in PTL 5 (Japan Patent Application Laid-Open Publication No. 2008-107408), there is disclosed a technology which, in speech recognition processing, performs the speech recognition processing in view of an ambient environment.

Dictionary learning device, pattern matching apparatus, method for learning dictionary and storage medium