A vehicle sprocket chain maintenance apparatus that includes a brush for cleaning the vehicle sprocket chain and a device for applying lubricant to the vehicle sprocket chain is adapted to be mounted on a vehicle and used on the vehicle sprocket chain while running the vehicle. The vehicle sprocket chain maintenance apparatus includes a mechanism for individual remote control of actuating the brush and the device for applying lubricant on the vehicle sprocket chain while running the vehicle.

A vehicle sprocket chain maintenance apparatus comprising a brush for cleaning the vehicle sprocket chain, said apparatus is adapted to be mounted on a vehicle and used on the vehicle sprocket chain while running the vehicle.
The invention further relates to a method of using the sprocket chain maintenance apparatus according to the invention.
Bicycles are used for transport and sports all over the world. To keep a bike functional it is important that it is regularly seen to and especially that the sprocket chain is cleaned and lubricated. When bicycles are used in competitive sports, as for example mountain bike races or off road challenges, this need becomes even more pronounced and in many cases it is even necessary to clean and lubricate during a race. Usually the bicycle rider must stop and perform the cleaning and lubricating manually before continuing the race. This obviously delays the bicycle athlete and some times the time used in these stops can be crucial of whether a victory is earned or not. Similar problems regarding the constant maintenance of the sprocket chain exists on most sprocket chain driven vehicles, and even though the extent of the problems may vary from vehicle to vehicle depending on type and use the same need to keep the sprocket chain clean and lubricated exists.
Attempts have been made to make maintenance of sprocket chain and gears easier but all of these attempts have severe drawbacks. U.S. Pat. No. 5,343,588 discloses a gear cleaner for cleaning the speed change gear of a bicycle. A brush is mounted by the back wheel of a bike, positioned to be in permanent contact with the gear wheels of the speed change gear. As the brush cleans the gear parts constantly while running the bike the system has the severe drawback that the bristles of the brush are in permanent contact with the gear wheels. This causes a massive wear of the bristles of the brush and also applies a permanent pressure onto the gear wheels inducing a slight slowdown of the forward motion of the bicycle.
U.S. Pat. No. 4,593,923 describes a bicycle sprocket chain cleaner. This device cleans the chain by means of brushes and solvent in a box to be releasably mounted on the bicycle chain. The major drawback of this device is that it cannot be mounted on the bicycle while the bicycle is being run. Furthermore, as detergent is in the device, there is a need to re-lubricate the bicycle chain after using the device.
Thus there is an unmet need for a device for cleaning a vehicle chain without the need for the vehicle rider to stop e.g. during a race.

Vehicle sprocket chain maintenance apparatus and a method of using the sprocket chain maintenance apparatus


A terminal is disclosed that includes a processor that determines a cyclic shift based on a cyclic shift index associated with an orthogonal cover code index configured by a higher layer and a transmitter that transmits on an uplink control channel, uplink control information to which an orthogonal cover code associated with the orthogonal cover code index is applied. The transmitter further transmits, within a resource block assigned for the uplink control channel, a demodulation reference signal using a reference signal sequence having the cyclic shift. In other aspects, a radio control method for a terminal and a base station are also disclosed.

In the UMTS (Universal Mobile Telecommunications System) network, the specifications of long-term evolution (LTE) have been drafted for the purpose of further increasing high speed data rates, providing lower delays and so on (see non-patent literature 1). In addition, successor systems of LTE are also under study for the purpose of achieving further broadbandization and increased speed beyond LTE (referred to as, for example, "LTE-A (LTE-Advanced)," "FRA (Future Radio Access)," "4G," "5G," "5G+ (plus)," "NR (New RAT)," "LTE Rel. 14," "LTE Rel. 15 (or later versions)," and so on).
In existing LTE systems (for example, LTE Rel. 8 to 13), downlink (DL) and/or uplink (UL) communication are performed using 1-ms subframes (also referred to as "transmission time intervals (TTIs)" and so on). These subframes are the time unit for transmitting one channel-encoded data packet, and serve as the unit of processing in, for example, scheduling, link adaptation, retransmission control (HARQ (Hybrid Automatic Repeat reQuest)) and so on.
Also, in existing LTE systems (for example, LTE Rel. 8 to 13), a user terminal transmits uplink control information (UCI) by using an uplink control channel (for example, a PUCCH (Physical Uplink Control CHannel)) or an uplink data channel (for example, a PUSCH (Physical Uplink Shared CHannel)). The format of this uplink control channel is referred to as "PUCCH format (PF (PUCCH Format))" and/or the like.

User terminal and radio communication method


A monitoring circuit that includes a pickup loop to monitor a voltage applied to a cavity of a linear accelerator is disclosed. The monitoring circuit is electrically isolated from the linear accelerator and is also electrically isolated from the controller that receives input from the circuit and controls the linear accelerator. In certain embodiments, the monitoring circuit also includes an energy harvester so as to capture energy without any physical connection to the controller. This may be achieved using light energy or electromagnetic energy, for example. In certain embodiments, the monitoring circuit includes an analog-to-digital converter to convert the signals received from the pickup loop to digital values. In other embodiments, the monitoring circuit passes analog voltages to the controller. The outputs from the monitoring circuit may include the amplitude and phase of the voltage being applied to the respective cavity.

The fabrication of a semiconductor device involves a plurality of discrete and complex processes. In some of these processes, ions are accelerated toward a workpiece. These ions may be accelerated in a number of ways. For example, electrical fields are commonly used to attract and accelerate positively charged ions.
In certain embodiments, a linear accelerator (or LINAC) may be used to accelerate these ions. In certain embodiments, a LINAC includes a plurality of RF cavities which each serve to further accelerate the ions passing therethrough. The LINAC may operate optimally when each of the RF cavities is energized at its respective resonant frequency.
While LINACs are useful in accelerating ions, there are challenges associated with their use. For example, in certain embodiments, the cavities may be energized at voltages that are in the megavolts. Further, it is also possible that glitches or other anomalies occur in the LINAC, which may affect the quality of the beam.
Consequently, monitoring the voltages being applied to each cavity of the LINAC may be difficult, as there is the potential of ground loops and glitches.
Therefore, it would be advantageous if there were a system that is capable of reliably measuring the voltages associated with the LINAC. It would be beneficial if the system were electrically isolated from the LINAC and from the controller.


A method of operating a vehicle includes the steps of: entering a drive shaft test mode; receiving a command to position a yoke to drive the shaft; regulating the shaft speed so as to be below a predefined threshold; and determining whether a drive shaft is available based on whether an actual drive shaft speed is detected above the predefined threshold. When the detected actual drive shaft speed is above the predefined threshold, it is determined that the drive shaft is not available and the vehicle is disabled to prevent damage to the vehicle. When the detected actual drive shaft speed is not above the predefined threshold, it is determined that the drive shaft is available, and the vehicle may be operated as is typical. The methods may be performed by an controller executing program code stored on a non-transitory computer readable medium.

In conventional vehicle transmission systems, the drive shaft is removed for towing when the vehicle cannot be driven to a repair shop. This presents a potential danger in that a repair or service technician can forget to reinstall the drive shaft back into the vehicle before the vehicle is driven again. If the drive shaft is not reinstalled into the vehicle, subsequent driving could cause severe damage to the vehicle power train and drive train components. In absence of the drive shaft, such vehicle components become susceptible to high rotation speeds because there is very little counteracting inertia at the power train when drive shaft is removed.

Drive shaft detection for pump or motor protection


An integrated low NO.sub.x tangential firing system (12) that is particularly suited for use with pulverized solid fuel-fired furnaces (10), and a method of operating a pulverized solid fuel-fired furnace (10) equipped with an integrated low NO.sub.x tangential firing system (12). The integrated low NO.sub.x tangential firing system (12) when so employed with a pulverized solid fuel-fired furnace (10) is capable of limiting NO.sub.x emissions therefrom to less than 0.15 lb./10.sup. 6 BTU, while yet maintaining carbon-in-flyash to less than 5% and CO emissions to less than 50 ppm. The integrated low NO.sub.x tangential firing system (12) includes pulverized solid fuel supply means (62), flame attachment pulverized solid fuel nozzle tips (60), concentric firing nozzles, close-coupled overfire air (98,100), and multi-staged separate overfire air (104,106).

This invention relates to tangential firing systems for use with pulverized solid fuel-fired furnaces, and more specifically, to an integrated low NO.sub.x tangential firing system, which is applicable to a wide range of solid fuels and which when employed with a pulverized solid fuel-fired furnace is capable of limiting NO.sub.x emissions therefrom to levels consistent with alternate solid fuel-based power generation technologies.
Pulverized solid fuel has been successfully burned in suspension in furnaces by tangential firing methods for a long time. The tangential firing technique involves introducing the pulverized solid fuel and air into a furnace from the four corners thereof so that the pulverized solid fuel and air are directed tangent to an imaginary circle in the center of the furnace. This type of firing has many advantages, among them being good mixing of the pulverized solid fuel and the air, stable flame conditions, and long residence time of the combustion gases in the furnaces.
Recently though, more and more emphasis has been placed on the minimization as much as possible of air pollution. In this connection, with reference in particular to the matter of NO.sub.x control it is known that oxides of nitrogen are created during fossil fuel combustion primarily by two separate mechanisms which have been identified to be thermal NO.sub.x and fuel NO.sub.x Thermal NO.sub.x results from the thermal fixation of molecular nitrogen and oxygen in the combustion air. The rate of formation of thermal NO.sub.x is extremely sensitive to local flame temperature and somewhat less so to local concentration of oxygen. Virtually all thermal NO.sub.x is formed at the region of the flame which is at the highest temperature. The thermal NO.sub.x concentration is subsequently "frozen" at the level prevailing in the high temperature region by the thermal quenching of the combustion gases. The flue gas thermal NO.sub.x concentrations are, therefore, between the equilibrium level characteristic of the peak flame temperature and the equilibrium level at the flue gas temperature.
On the other hand, fuel NO.sub.x derives from the oxidation of organically bound nitrogen in certain fossil fuels such as coal and heavy oil. The formation rate of fuel NO.sub.x is strongly affected by the rate of mixing of the fossil fuel and air stream in general, and by the local oxygen concentration in particular. However, the flue gas NO.sub.x concentration due to fuel nitrogen is typically only a fraction, e.g., 20 to 60 percent, of the level which would result from complete oxidation of all nitrogen in the fossil fuel. From the preceding it should thus now be readily apparent that overall NO.sub.x formation is a function both of local oxygen levels and of peak flame temperatures.
Over the years, there have been numerous modifications made to the standard tangential firing technique. Many of these modifications, and in particular those that have been suggested most recently, have been proposed primarily in the interest of achieving an even better reduction of emissions through the use thereof. The resultant of one such modification is the firing system that forms the subject matter of U.S. Pat. No. 5,020,454 entitled "Clustered Concentric Tangential Firing System", which issued on Jun. 4, 1991 and which is assigned to the same assignee as the present patent application. In accordance with the teachings of U.S. Pat. No. 5,020,454, there is provided a clustered concentric tangential firing system that is particularly suited for use in fossil fuel-fired furnaces. The clustered concentric tangential firing system includes a windbox. A first cluster of fuel nozzles are mounted in the windbox and are operative for injecting clustered fuel into the furnace so as to thereby create a first fuel-rich zone therewithin. A second cluster of fuel nozzles are mounted in the windbox and are operative for injecting clustered fuel into the furnace so as to thereby create a second fuel-rich zone therewithin. An offset air nozzle is mounted in the windbox and is operative for injecting offset air into the furnace such that the offset air is directed away from the clustered fuel injected into the furnace and towards the walls of the furnace. A close coupled overfire air nozzle is mounted in the windbox and is operative for injecting close coupled overfire air into the furnace. A separated overfire air nozzle is mounted within the burner region of the furnace so as to be spaced from the close coupled overfire air nozzle and so as to be substantially aligned with the longitudinal axis of the windbox. The separated overfire air nozzle is operative for injecting separated overfire air into the furnace.
The resultant of another such modification is the firing system that forms the subject matter of U.S. Pat. No. 5,146,858, which is entitled "Boiler Furnace Combustion System" and which issued on Sep. 15, 1992. In accordance with the teachings of U.S. Pat. No. 5,146,858, a boiler furnace combustion system is provided of the type that typically includes main burners disposed on side walls of or at corners of a square-barrel-shaped boiler furnace having a vertical axis with the burner axes being directed tangentially to an imaginary cylindrical surface coaxial to the furnace. Moreover, in this type of boiler furnace combustion system air nozzles are disposed in the boiler furnace at a level above the main burners so that unburnt fuel left in a reducing atmosphere or a lower oxygen concentration atmosphere of a main burner combustion region can be perfectly burnt by additional air blown through the air nozzles. The boiler furnace combustion system, as taught in U.S. Pat. No. 5,146,858, is particularly characterized in that two groups of air nozzles are disposed at higher and lower levels, respectively. More specifically, the air nozzles at the lower level are provided at the corners of the boiler furnace with their axes directed tangentially to a second imaginary coaxial cylindrical surface having a larger diameter than the first imaginary coaxial cylindrical surface. The air nozzles at the higher level, on the other hand, are provided at the centers of the side wall surfaces of the boiler furnace with their axes directed tangentially to a third imaginary coaxial cylindrical surface having a smaller diameter than the second imaginary coaxial cylindrical surface.
The resultant of yet another such modification is the firing system that forms the subject matter of U.S. Pat. No. 5,195,450 entitled "Advanced Overfire Air System for NO.sub.x Control", which issued on Mar. 23, 1993 and which is assigned to the same assignee as the present patent application. In accordance with the teachings of U.S. Pat. No. 5,195,450, there is provided an advanced overfire air system for NO.sub.x control, which is designed for use in a firing system of the type that is particularly suited for use in fossil fuel-fired furnaces. The advanced overfire air system for NO.sub.x control includes multi-elevations of overfire air compartments consisting of a plurality of close coupled overfire air compartments and a plurality of separated overfire air compartments. The close coupled overfire air compartments are supported at a first elevation in the furnace and the separated overfire air compartments are supported at a second elevation in the furnace so as to be spaced from but aligned with the close coupled overfire air compartments. Overfire air is supplied to both the close coupled overfire air compartments and the separated overfire air compartments such that there is a predetermined most favorable distribution of overfire air therebetween, such that the overfire air exiting from the separated overfire air compartments establishes a horizontal "spray" or "fan" distribution of overfire air over the plan area of the furnace, and such that the overfire air exits from the separated overfire air compartments at velocities significantly higher than the velocities employed heretofore.
Throughout the 1990s and into the twenty-first century large, central pulverized solid fuel-fired power stations are expected to play an important role in worldwide power generation. These stations will be designed for maximum cycle efficiency, multiple-fuel flexibility, cycling, maximum availability, least capital cost, minimum maintenance cost, and lowest possible emissions that meet or exceed federal, state and local rules. Historically, tangential firing has demonstrated inherently low NO.sub.x production for large, pulverized solid fuel-fired furnaces. Lower NO.sub.x emissions result from the staging that occurs with the physical separation of the pulverized solid fuel and air streams emanating from the corner windboxes. The flames produced at each pulverized solid fuel nozzle are stabilized through global heat- and mass-transfer processes. A single rotating flame envelope ("fireball"), centrally located in the furnace, provides gradual but thorough and uniform pulverized solid fuel-air mixing throughout the entire furnace. This tangential firing process has been an advantage in developing advanced air staging systems for combustion NO.sub.x control. In contrast, wall-fired furnaces utilize groups of individually self-stabilizing burners that do not use global furnace flow patterns to achieve uniform pulverized solid fuel and air mixing. As a result, wall-fired arrangements, even though employing separated overfire air, typically create local zones of high temperature and O.sub.2 concentrations that cause NO.sub.x formation.
Thus, although firing systems constructed in accordance with the teachings of the three issued U.S. patents to which reference has been made hereinbefore have been demonstrated to be operative for the purpose for which they have been designed, there has nevertheless been evidenced in the prior art a need for such firing systems to be improved. More specifically, a need has been evidenced in the prior art for a new and improved tangential firing system that would enable NO.sub.x emissions from pulverized solid fuel-fired furnaces to be controlled at levels, which are consistent with alternate pulverized solid fuel-based power generation technologies, such as circulating fluidized bed (CFB) and integrated gasification combined cycle (IGCC), without utilizing either selective catalytic reduction (SCR) or selective non-catalytic reduction (SNCR). To this end, a need has been evidenced in the prior art for a new and improved tangential firing system that would enable the NO.sub.x emissions from pulverized solid fuel-fired furnaces to be limited to less than 0.15 lb./10.sup.6 BTU, while yet at the same time limiting carbon-in-flyash to less than 5% and CO emissions to less than 50 ppm. Moreover, such emissions levels should be attainable while a wide range of solid fuels, from medium-volatile bituminous coal through lignite, are being fired in a pulverized solid fuel-fired furnace that has been equipped with such a new and improved tangential firing system. Finally, there is a need in order that such a new and improved tangential firing system may be provided that attention be focused on the entire pulverized solid fuel combustion system, including pulverization, primary air flow, fuel admission assemblies, and multiple levels of air injection (auxiliary air, close-coupled overfire air, and separated overfire air). To this end, such a new and improved tangential firing system may be viewed as consisting of the following four major elements: solid fuel pulverization and classification, pulverized solid fuel admission and combustion near the pulverized solid fuel nozzle tip, lower furnace combustion, and upper furnace combustion (between the main windbox and the furnace arch). Moreover, such a new and improved tangential firing system should be predicated on the optimization therewithin of these four above-enumerated individual elements.
To thus summarize, a need has been evidenced in the prior art for a new and improved tangential firing system that when employed with a pulverized solid fuel-fired furnace is capable of meeting 0.10 to 0.15 lb./10.sup.6 BTU NO.sub.x emissions levels on Eastern U.S. bituminous coals, and of making pulverized solid fuel firing in a pulverized solid fuel-fired furnace competitive on an emissions basis with other new solid fuel-fired technology options, such as fluidized bed combustors and IGCC. Moreover, with such a new and improved tangential firing system the NO.sub.x emission target is to be achieved through combustion techniques only, while maintaining carbon-in-flyash at less than 5% and CO emissions at less than 50 ppm. That is, such a new and improved tangential firing system should be capable of enabling minimum total emissions to be achieved therewith. In this regard, techniques employed to reduce NO.sub.x formation, such as sub-stoichiometric primary zone combustion, staging of pulverized solid fuel and air mixing, reduced excess air, and lower heat release rates, are all aimed at controlling oxygen availability, the combustion rate and reducing peak flame temperatures. However, since these conditions may increase the potential for CO, hydrocarbons, and increased unburned carbon emissions, it is necessary that in such a new and improved tangential firing system that a balance be achieved among these opposing factors. Namely, it is necessary that such a new and improved tangential firing system comprise an integrated tangential firing system wherein finer solid fuel pulverization is combined with advanced pulverized solid fuel admission assemblies and in-furnace air staging utilizing multiple air injection levels. It is the integration of these features, which distinguishes such a new and improved integrated tangential firing system from prior art forms of firing systems.
The need for finer solid fuel pulverization is predicated on the need to minimize combustible losses (unburned carbon) caused by the staged combustion process for NO.sub.x control. Finer pulverized solid fuel can result in close ignition at the pulverized solid fuel nozzle tip discharge, enhancing fuel-bound nitrogen release and its subsequent reduction to N.sub.2 under staged conditions. Secondary benefits include fewer large (>100 mesh) particles impinging on the waterwalls of the pulverized solid fuel-fired furnace and improved low-load ignition stability.
The need for advanced pulverized solid fuel admission assemblies is to ensure that the ignition point of the pulverized solid fuel occurs closer to the nozzle tip than it does with conventional pulverized solid fuel nozzle tips. The rapid ignition of the pulverized solid fuel produces a stable volatile matter flame and minimizes NO.sub.x production in the pulverized solid fuel-rich stream. In addition, there should also exist the capability with the advanced pulverized solid fuel admission assemblies to horizontally offset some of the windbox secondary airflow in order to thereby make less air available to the pulverized solid fuel stream during the early stages of combustion. Such horizontally offsetting of some of the windbox secondary airflow also creates an oxidizing environment near the waterwalls of the pulverized solid fuel-fired furnace in and above the firing zone. This reduces ash deposition quantity and tenacity and results in both less wall soot blower usage and increased lower furnace heat absorption. Increased O.sub.2 levels along the waterwalls of the pulverized solid fuel-fired furnace also reduce corrosion potential, especially when coals with high concentrations of sulfur, iron, or alkali metals (K, Na) are fired. Corrosion by sulfidation or other mechanism(s) can be largely controlled in practice by minimizing the potential for direct fuel impingement on the waterwalls of the pulverized solid fuel-fired furnace. This potential is addressed via conservative heat release parameters and pulverized solid fuel-fired furnace geometries, as well as improved pulverized solid fuel fineness control.
The need for in-furnace air staging utilizing multiple air injection levels is predicated on the need to discharge a portion of the secondary air through air compartments at the top of the main windbox to improve carbon burnout without increasing NO.sub.x production. In addition, there should also exist the capability with the in-furnace air staging utilizing multiple air injection levels to control firing zone stoichiometry through multi-staged separated overfire air (SOFA). Two or more discrete levels of overfire air are incorporated in the corners of the pulverized solid fuel-fired furnace between the top of the main windbox and the pulverized solid fuel-fired furnace outlet plane to create the optimum stoichiometry history for NO.sub.x control for a given pulverized solid fuel. The SOFA compartments have adjustable yaw and tilt positioning, which allows tuning of the combustion air and pulverized solid fuel-fired furnace gas mixing process for maximum control of combustible emissions such as carbon, CO, total hydrocarbons (THC) and polycyclic aromatic compounds (PAC).
It is, therefore, an object of the present invention to provide a new and improved tangential firing system that is particularly suited for use with pulverized solid fuel-fired furnaces.
It is a further object of the present invention to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that through the use thereof NO.sub.x emissions from pulverized solid fuel-fired furnaces can be controlled at levels, which are consistent with alternate pulverized solid fuel-based power generation technologies, such as circulating fluidized bed (CFB) and integrated gasification combined cycle (IGCC), without utilizing either selective catalytic reduction (SCR) or selective non-catalytic reduction (SNCR).
It is another object of the present invention to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that through the use thereof NO.sub.x emissions from pulverized solid fuel-fired furnaces can be less than 0.15 lb./10.sup.6 BTU.
It is still another object of the present invention to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that through the use thereof NO.sub.x emissions from pulverized solid fuel-fired furnaces can be limited to less than 0.15 lb./10.sup.6 BTU while yet at the same time limiting carbon-in-flyash to less than 5% and CO emissions to less than 50 ppm.
Another object of the present invention is to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that through the use thereof NO.sub.x emissions from pulverized solid fuel-fired furnaces can be limited to less than 0.15 lb./10.sup.6 BTU while a wide range of solid fuels, from medium-volatile bituminous coal through lignite, are being fired in the pulverized solid fuel-fired furnace.
A still another object of the present invention is to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that included therewithin as an element thereof is solid fuel pulverization and classification.
A further object of the present invention is to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that included therewithin as an element thereof is pulverized solid fuel admission and combustion near the pulverized solid fuel nozzle tip.
A still further object of the present invention is to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that included therewithin as an element thereof is lower furnace combustion.
Yet an object of the present invention is to provide such a new and improved tangential firing system for pulverized, solid fuel-fired furnaces which is characterized in that included therewithin as an element thereof is upper furnace combustion.
Yet a further object of the present invention is to provide such a new and improved tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that finer solid fuel pulverization is combined therewithin with advanced pulverized solid fuel admission assemblies and in-furnace air staging utilizing multiple air injection levels such that the new and improved tangential firing system thereby constitutes a new and improved integrated tangential firing system for pulverized solid fuel-fired furnaces.
Yet another object of the present invention is to provide such a new and improved integrated tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that it is equally well suited for use in either new applications or in retrofit applications.
Yet still another object of the present invention is to provide such a new and improved integrated tangential firing system for pulverized solid fuel-fired furnaces which is characterized in that it is relatively easy to install, relatively simple to operate, yet is relatively inexpensive to provide.

Integrated low NO.sub.x tangential firing system


A portable and convenient electronic distance measuring apparatus using a laser beam and a supersonic wave is provided. A predetermined height is measured using a supersonic sensor and a laser pointer is rotated at the predetermined height to radiate a laser beam at a target object so that a distance to a target object at which that laser beam is pointing can be accurately measured using a resistance value corresponding to a rotation angle of the laser pointer

A laser is an apparatus which amplifies or oscillates an electromagnetic wave having a very short wavelength using quantum mechanics. The laser is referred to as a quantum oscillator or a molecular oscillator. The term "laser" is originated from Light Amplification by Stimulated Emission of Radiation.
Light emited when an object is burned or light emitted from a fluorescent lamp is generated from individual atoms or molecules heated at high temperature. Such light has a large number of different wavelengths even if the light is generated from the same kind of atoms or molecules. Light generated from individual atoms or molecules is the group of diverse lights having no relations with each other. However, a laser beam is coherent much more than other light beams and goes straight almost without diverging.
Such laser is wide spread in human life. A representative is a laser pointer which is an apparatus pointing at a direction by radiating a laser beam generated by a laser diode at a particulat position of a target object. The laser pointer is made compact so that a user can conveniently carry.
Meanwhile, in the industrial world including industrial sites, construction sites, and interiors and in daily life, a measuring tape is usually used to measure a distance. However, it is difficult for a user along to measure a size of a large object or place or a high object or place with the measuring tape. Moreover, since the measuring tape is easily bent or curved, it may be difficult to accomplish accurate measurement. To overcome this problem, a laser distance measuring apparatus, which counts time until an emitted laser beam returns back from a target object and measures a distance to the target object, has been developed.
Such laser distance measuring apparatus emits a laser beam, receives the laser beam reflected from a target object, and measure a distance to the target object. Accordingly, it is necessary to accurately receive the laser beam. However, when a user measures a distance while holding the laser distance measuring apparatus with the hand, it is difficult to receive a laser beam reflected from a target object if the laser beam is refracted and reflected by the target object.


An information processing apparatus includes clustering means for performing clustering on multiple images so as to more strongly connect the images at a closer distance based on the distances determined by metadata of the images, and grouping means for grouping the images such that the number of images of each group can be equal to or lower than a predetermined number of images in accordance with the strength of connection among the images.

1. Field of the Invention
The present invention relates to an information processing apparatus, method and program and, in particular, to an information processing apparatus, method, and program that allows grouping contents properly and creating new contents.
2. Description of the Related Art
In recent years, various clustering technologies have been proposed for grouping recorded contents in machines such as an HDD (Hard Disk Drive) recorder and a personal computer. By sorting recorded images by using the technology, contents may be created like an album of photographs shot by a silver salt camera.
Storing photographs shot by a silver salt camera may include dividing the photographs into albums or pages based on events, shot places and dates, for example. A user can lay out photographs with closer relationships regarding events, places, dates or the like on each page in accordance with the size of the page or the number of photographs.
By the way, a technology has been proposed that converts film images of shot photographs to electronic images, saves and manages them as electronic data by adding additional information such as the shot dates and places thereto and stores the photograph film recording the images in association with the electronic data (refer to JP-A-10-143631).

Information processing apparatus, method and program


A cement composition for use in acidic environments containing an acid resistant particulate aggregate of fused mullite aggregate or other aggregate material, with quartz, and microsilica in combination with a colloidal silica sol binder and being substantially free of Na compounds and K compounds which react in the presence of sulfuric acid to form alkali sulfates in service, thus reducing the durability or the service life.

This invention relates to cement compositions, and especially to cement compositions useful as mortar with refractory brickwork linings in thermal/chemical processing applications. One specific example is the high pressure autoclaves used in the acidic oxidation of refractory precious metal ores.
There are precious metal ores that are of refractory type, in which the metallic phase(s) of interest is not readily recoverable by cyanidation and other known techniques, unless the ores are first oxidized. One oxidation technique that is used is high pressure oxidation in an autoclave. Pressure oxidation methods and autoclaves are described, for example, in Thomas et al., U.S. Pat. Nos. 5,071,477 and 5,489,326. Such autoclaves are typically brickwork-lined (acid resistant refractory bricks and mortar) and the lining must withstand temperatures of 400.degree.-460.degree. F. and pressure oxidation conditions including total pressure in the range of about 400-500 psig, oxygen partial pressure of greater than about 20 psi, and agitated ore slurry contents of up to 25 or more g/L sulfuric acid.
The most common mortars now used in autoclave applications, and in the past, have included alkali silicate containing mortars and other alkali compound containing mortars. The alkali content of these mortars has limited the mortars' life because the alkali-containing phase(s) tends to react in the presence of sulfuric acid to form alkali sulfates, and other altered compounds, which are subject to significant expansion and volume change. This effect can cause or contribute to the breakdown of brickwork, because of associated stresses, cracking and strength loss that accompany the brick and mortar alteration in use.
U.S. Pat. No. 2,914,413 discloses a cold-setting acid corrosion resistant cement comprising an aqueous silica sol and solid alkali metal silicate setting agents. The cement is stated to be of reduced sodium content, due to its use of a very low sodium (less than 0.5%) source of silica for its binder, whereby problems associated with sodium content are reduced. However, potential problems associated with reaction effects, like the conversion and volume expansion of alkali metal sulfates, remain because of the incorporation of alkali metal silicate (sodium silicate) setting agents.


In a defective cell write mode, a precharge potential generating circuit generates a precharge potential at a high level or a low level in accordance with an external control signal, and applies the potential to a bit line pair. Parallel to a fuse element provided between a main bit line precharge potential supply line and a sub bit line precharge potential supply line and is cut when a column is replaced by a redundancy column of memory cells, a pass transistor which is rendered conductive in the defective cell write mode is provided.

1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having a defective cell write mode.
2. Description of the Background Art
As the degree of integration of semiconductor memory devices, particularly of dynamic RAMs (DRAMs) increases, power consumption in a standby state is ever increasing. Particularly in a DRAM, stored information is retained by re-reading/re-writing of stored information even in the standby state. Therefore, there is a limit in reducing the power consumption in the standby state in principle.
However, it is a critical issue to reduce as much as possible, the power consumption in the standby state in a system that uses a large number of DRAMs.
Increase in the degree of integration inevitably leads to increased possibility of defects in memory cells. In order to compensate for generation of error due to such defective memory cell, an approach by a so-called redundancy circuit is made where a column of memory cell including a defective memory cell is replaced by a spare column of memory cells, for example.
Such replacement allows the basic operation of reading/writing of data of a memory cell without any problem. However, even when the defect is repaired by the redundancy circuit, there still remains a leakage path at the defective portion. This means that the power consumption in the standby state of the DRAM is further increased.
The above circumstance will be described in detail with reference to FIG. 12.
The operation of each component will be described briefly.
In a Y address comparator circuit 6038 in a redundancy column decoder 6023, an address detected as including a defective bit at a time of previous testing is stored, in a nonvolatile memory such as a fuse circuit.
When an external address signal A0-Ai does not match the above identified address including the defective bit, a column selection line drive circuit 6034, for example, is activated, whereby a column selection line (hereinafter referred to as "CS line") 6024 is pulled up to an "H" level (logical high).
By an I/O gate 6018 of a bit line pair group unit 6102, for example, a pair of bit lines BL3, /BL3 is connected to a data input/output line 6020.
Potential difference between the pair of bit lines BL3 and /BL3 is amplified by a sense amplifier 6016 in accordance with the information stored in a memory cell connected thereto and selected by a signal of a word line, not shown.
By the above operation, the information of the memory cell is externally read out.
If there is a short-circuit portion 6200 between a bit line BL1 and the ground level GND, data cannot be read/written from and to the memory cell connected to that bit line.
In this case, the defective bit line is replaced by a spare bit line. Generally, this replacement is on a bit line by bit line basis or on unit by unit basis of the bit line pair group selected by a CS line.
More specifically, the address of CS line 6022 corresponding to the bit line pair group unit 6100 to which the defective bit line BL belongs is preprogrammed in a Y address comparator circuit 6038.
Externally applied address signal A0-Ai is compared with the programmed address of the defect by Y address comparator circuit 6038. When the two match each other, a signal (SE signal) activating a spare column decoder is input to a CS line drive circuit 6036, and a bit line pair group unit 6104 including spare bit lines SPARE BL1, SPARE /BL1 is selected.
At the same time, a signal (NED signal) inactivating the CS line associated with the defective bit line BL1 is input to a CS line drive circuit 6032.
Thus, defective bit is replaced and there is no problem in the basic operation of the memory cell.
However, the bit line pair is precharged to the level of a potential V.sub.BL generated by a bit line potential generating circuit (not shown) in the chip, for example, before sense amplifier 6016 starts amplifying operation in accordance with the information of the memory cell. Here, potential V.sub.BL is set to 1/2Vcc where Vcc represents the potential supplied from a power supply 6002.
Further, a first power supply line S2P to the sense amplifier connected through a switching transistor 6016 to power supply 6002 as well as a second power supply line S2N to the sense amplifier connected to the ground through switching transistor 6012 (hereinafter the power supply lines will be generally referred to as S2 line) are also precharged, similar to the bit line pair.
Therefore, a first leakage current path 6202 through which current leaks from the supply line of the potential of the bit line potential generating circuit through a bit line equalize circuit 6104 setting bit lines BL1 and /BL1 commonly to the potential V.sub.BL and through bit line BL1, and a second leak path 6204 through which current leaks from a S2 line equalize circuit 6008 setting S2 lines commonly to the potential V.sub.BL through the S2 line, sense amplifier 6016 and bit line BL1 are generated because of the existence of the short-circuit portion 6200.
As a result, a problem arises that the actual standby current at the memory cell portion increases.
Further, since the potential V.sub.BL attains lower than the designed value, operation margin with respect to V.sub.BL is significantly reduced. This will be described with reference to a timing chart of FIG. 13 showing the operation of the conventional DRAM.
First, at time t.sub.0, all the pairs of bit lines should be precharged to the level of potential V.sub.BL.
However, the potential of bit line pair BL1, /BL1 associated with the defective bit is lower than the potential V.sub.BL (1/2Vcc) because of the leakage current.
Line S2 of the sense amplifier is also lower than precharge voltage V.sub.BL, because of the leakage current. It is to be noted that reduction in potential of line S2 influences the operation of all the sense amplifiers commonly connected to line S2.
Following the transition of row address strobe signal /RAS from high ("H") to low ("L") at time t.sub.2, an internal signal BLEQ makes a transition from high to low at time t.sub.3, and the bit line pair is electrically isolated.
Similarly, S2 line equalize circuit 6008 is turned off, whereby the pair of lines S2 is electrically isolated.
Thereafter, at time t5, switching transistors 6010 and 6012 are turned on in response to signals /SOP and SON, respectively, and sense amplifier 6016 is activated.
As a result, potential of one of the paired bit lines BL1 and /BL1 and one of paired spare bit lines SPARE BL1 and SPARE /BL1 attains to the potential Vcc, and the potential of the other one of the paired line attains to the ground potential, in accordance with the information stored in the memory cell selected corresponding thereto. At time t.sub.8, at the transition of signals NED and SE from low to high, CS1 line 6022 is kept inactive while spare CS line 6026 is activated, and as a result, data is output to data input/output line (I/O line) 6020.
Thereafter, at time t.sub.12, signal /RAS makes a transition from low to high, and at time t.sub.13, the BLEQ signal makes a transition from low to high.
At the same time, the sense amplifier attains an inactive state by signals /SOP and SON. By the BLEQ signal, the bit line pair is again precharged to the potential V.sub.BL. However the potential of bit line pair BL1 and /BL1 lowers because of the leakage current, and the potential of S2 line also lowers.
As described above, the potential of S2 line immediately before activation of the sense amplifier is lower than V.sub.BL (=1/2Vcc) because of the leakage current. The resulting lower V.sub.BL would present more severe problem as the capacity of memories has been increased recently.
Increase in memory capacity and miniaturization of the device size require reduction in power supply voltage, from the stand point of reliability. Therefore, the problem of lower V.sub.BL margin caused by the reduction in voltage is further aggravated by the reduction of V.sub.BL due to leakage path.
As described above, the conventional semiconductor memory device suffers from a first problem that actual standby current of the memory cell portion is increased because of the leakage current at a defective portion and that operation margin with respect to the potential V.sub.BL is reduced.
Further, the conventional semiconductor memory device suffers from a second problem, which will be described in the following.
FIG. 14 is a partially omitted circuit block diagram showing a structure of a conventional DRAM and FIG. 15 is a partially omitted circuit block diagram showing, in detail, a structure of one column of memory cells shown in FIG. 14.
Referring to FIGS. 14 and 15, a memory cell array 6050 includes a plurality of memory cells MC arranged in a matrix, word lines WL provided corresponding to respective rows, and pairs of bit lines BL, /BL provided corresponding to respective columns.
Each memory cell MC is connected to the word line WL of the corresponding row. A plurality of memory cells MC of odd-numbered columns are connected to bit line BL or /BL alternately.
A plurality of memory cells of even-numbered columns are connected to bit line /BL or BL alternately.
Each memory cell MC includes an N channel MOS transistor 50 for accessing, and a capacitor 51 for storing information. N channel MOS transistor 50 of each memory cell MC has its gate connected to the word line WL of the corresponding row. N channel MOS transistor 50 is connected between the bit line BL or /BL of the corresponding column and one electrode (storage node SN) of capacitor 51 of the memory cell MC. Capacitor 51 of each memory cell MC receives, at the other electrode, a cell potential Vcp. The word line WL transmits an output from a row decoder 6020 and activates memory cells MC of the selected row. Bit line pair BL, /BL allows input/output of data signal to and from the selected memory cell MC.
A redundancy memory cell array 6052 has similar structure as memory cell array 6050 except that the number of columns is smaller than that of memory cell array 6050. Memory cell array 6050 and redundancy memory cell array 6052 have the same number of rows, and word lines WL are shared by memory cell array 6050 and redundancy memory cell array 6052.
A sense amplifier+input/output control circuit 6054 includes a column selection gate 6018, a sense amplifier 6016 and an equalizer 6014 which are provided corresponding to each column, and an intermediate potential generating circuit 6040 provided common to all the columns. Each column selection gate 6018 includes N channel MOS transistors 41 and 42 connected between bit lines BL and /BL and data signal input/output lines IO and /IO, respectively. N channel MOS transistors 41 and 42 have their gates connected to column decoder 6023a or 6023b through column selection line CSL. When column selection line CSL is pulled up to the high ("H") level, which is the selected level, by column decoder 6023a or 6023b, N channel MOS transistor 41 or 42 is rendered conductive and bit line pair BL, /BL is coupled to data signal input/output line pair IO, /IO.
Sense amplifier 6016 includes P channel MOS transistors 43 and 44 connected between a node N32 and bit lines BL and /BL, respectively, and N channel MOS transistors 45 and 46 connected between a node N32' and bit lines BL and /BL, respectively. MOS transistors 43 and 45 have their gates connected together to bit line /BL, while transistors 44 and 46 have their gates connected together to bit line BL. Nodes N32 and N32' receive sense amplifier activating signals SON and /SOP output from a clock generating circuit (not shown), respectively. Sense amplifier 6016 amplifies small potential difference between the pair of bit lines BL and /BL to power supply voltage Vcc, in response to sense amplifier activating signals SON and /SOP which have attained to "H" and "L" levels, respectively.
Equalizer 6014 includes an N channel MOS transistor 47 connected between bit lines BL and /BL, and N channel MOS transistors 48 and 49 connected between a node N33' and bit lines BL and /BL, respectively. N channel MOS transistors 47-49 have their gates connected to node N33. Node N33 receives a bit line equalize signal BLEQ, and node N33' receives a bit line potential VBL (=Vcc/2). Equalizer 6014 equalizes potentials of bit lines BL and /BL to bit line potential VBL in response to bit line equalize signal BLEQ which have attained to the active level of "H".
Intermediate potential generating circuit 6040 generates an intermediate potential Vcc/2 between power supply potential Vcc and ground potential GND, and outputs the generated intermediate potential Vcc/2 as bit line potential VBL.
Now, in such a DRAM, even when a defective memory cell is replaced by a redundancy memory cell MC, a normal memory cell near the defective memory cell MC may be affected by the defective memory cell and fails, dependent on the state of defective memory cell MC.
More specifically, referring to FIG. 16, a DRAM is formed on a surface of a p type silicon substrate 52. A gate electrode, that is, the word line WL is formed above the surface of p type silicon substrate 52 with a gate oxide film (not shown) interposed, and on the surface of silicon substrate 52 on both sides of word line WL, n.sup.+ source/drain regions 53 are formed, thus providing N channel MOS transistor 50 of memory cell MC. One of the source/drain regions 53 of N channel MOS transistor 50 is connected to bit line BL, and on the surface of the other one of the source/drain regions, a conductive layer 54, a dielectric layer 55 and a conductive layer 56 are stacked, thus providing capacitor 51 of memory cell MC. Conductive layer 54 serves as one electrode of capacitor 51, that is, a storage node SN, and conductive layer 56 serves as the other electrode of capacitor. Three memory cells MC1 to MC3 are formed in the figure.
Now, assume that there is a small conductive particle between the gate electrode of the central memory cell MC2, that is, word line WL2, and silicon substrate 52. Further, it is assumed that the particle is small enough to allow data writing though memory cell MC2 is defective, and that word line WL2 is driven in the normal manner.
In a state where "L" level is written at storage node SN of defective memory cell MC2 and "H" level is written in storage node SN of normal memory cell MC1, when word line WL2 corresponding to memory cell MC2 is pulled up to the "H" level, positive charges (holes) are introduced from word line WL2 to silicon substrate 52 through the particle. Because of this positive charges, silicon substrate 52 locally attains to positive potential, and a PN junction between the portion having the positive potential and storage node SN of memory cell MC2 is forward biased. Accordingly, negative charges (electrons) flow out from storage node SN which is at the "L" level to silicon substrate 52. The negative charges move even to the storage node SN which is at the "H" level of adjacent memory cell MC1, pulling down the storage node SN to "L" level.
Therefore, even when the defective memory cell MC is replaced by a normal memory cell MC of redundancy memory cell array 6052, DRAM may not operate properly because of possible failure of a memory cell MC near the defective memory cell MC.
It is possible to detect the defect such as described above by a test in which "L" level is written to the storage node SN of defective memory cell MC and "H" level is written to storage nodes SN of other normal memory cells MC, a word line corresponding to the defective memory cell is pulled up to "H" and data of normal memory cells MC are read thereafter. If the storage nodes SN of the normal memory cells MC are at the "H" level, it is determined that the device has passed the test, and if the storage node SN of a normal memory cell MC is inverted to the "L" level, it is determined that the device fails.
However, in the conventional DRAM, it is not possible to access the defective memory cell MC which has been replaced by the redundancy memory cell MC. Therefore, it is not possible to write "L" level to the storage node SN of the replaced defective memory cell MC.
Further, as shown in FIG. 14, since a plurality of memory cells MC of respective columns are connected to bit line BL or /BL alternately, it is necessary to switch logic levels to be applied to bit lines BL and /BL in accordance with the address of the memory cell MC even when the same logic level is to be written to the storage nodes SN of the memory cells MC. Therefore, writing of a logic level to the storage node SN of each memory cell MC has been difficult. Especially when a defective memory cell MC is replaced by a redundancy memory cell MC, there may be cases where a memory cell MC connected to bit line BL is replaced by a redundancy memory cell MC connected to bit line BL' and where it is replaced by a redundancy memory cell MC connected to bit line BL'. This makes it more difficult to write logic level to the storage node SN of the redundancy memory cell MC.
A structure of a semiconductor memory device which addresses the first problem is disclosed in U.S. Pat. No. 5,666,315.
FIG. 17 is a schematic block diagram showing a main portion of the DRAM disclosed in the aforementioned U.S. Pat. No. 5,666,315.
In FIG. 17, same reference characters as in FIG. 12 denote the same components.
Different from the prior art shown in FIG. 12, power supply lines V.sub.BL1, V.sub.BL2, . . . , V.sub.BLs for supplying precharge potential V.sub.BL for the bit lines and the line S2 of sense amplifier are arranged parallel to CS line for every unit of bit line pair group.
The precharge potential power supply lines and corresponding memory cell array portions are connected by nonvolatile switch means such as fuse elements, respectively.
Further, the line S2 is separated for each of the bit line pair group units 6100, 6102 and so on, which is a unit of replacement when there is a defective bit. An S2 line equalize circuit S2-EQ for connecting/disconnecting the pair of S2 lines is provided for each unit.
Now, when there is a short-circuit portion 6200 in a memory cell connected to bit line BL1 in bit line pair group unit 6100, for example, a fuse element 6028 is cut.
Accordingly, though there are first and second leak paths even after replacement by the unit of bit line pair group including the defective bit in the prior art example, the leak paths are cut off and leak current does not flow in accordance with the present structure.
Therefore, increase in standby current caused by the defective bit after replacement can be prevented.
FIG. 18 is a timing chart showing operation of a first embodiment.
Basically, the operation is similar to that of the conventional example shown in FIG. 13. Sensing operation is performed even for the bit line pair BL1, /BL1 connected to the defective bit, and the potential difference between the pair of bit lines is amplified.
Here, since there is leakage between bit line BL1 and the ground, bit line BL1 is amplified to the "L" level and bit line /BL1 to "H" level.
However, the bit line pair is replaced by a spare bit line pair, that is, SPARE BL1 and SPARE /BL1. Therefore, there is not a problem for the basic operation.
Thereafter, at time t.sub.9, the signal BLEQ goes from low to high and paired bit lines BL1 and /BL1 are connected to each other and attain to the level of 1/2Vcc. However, because of leakage current, the voltage level of the bit line pair gradually lowers, and at time t.sub.10, the potential is sufficiently lowered and thereafter a constant value is maintained.
Since fuse element 28 is cut, leakage current does not flow thereafter.
In the conventional redundancy circuit shown in FIG. 12, even when the bit line pair group unit including a defect is repaired, increase in standby current cannot be prevented.
By contrast, when S2 lines are isolated by the unit of replacement, the precharge power supply interconnection for the bit line and the line S2 is isolated and a leakage current path is cut by the fuse element as in the structure shown in FIG. 17, so that the first problem described above can be solved.
However, even by the DRAM having such a structure as shown in FIG. 17, the second problem cannot be solved. More specifically, since the defective memory cell MC which has been replaced by the redundancy memory cell MC cannot be accessed, a desired logic level cannot be written to the storage node SN of the replaced defective memory cell MC.

Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell


A misting system for a vehicle having a water pump uses a connector for splicing into a water line of the vehicle. A valve is coupled to the connector for activating and deactivating the misting system. Opening the valve causes pressure in the water line to be lessened thereby causing the water pump to activate and supply more water to the water line. A filter is coupled to the valve for removing particulates from the water in the water line. Piping is coupled to the filter. The piping will have watertight quick connect/disconnect connectors for quickly assembling the piping. Misting nozzles are coupled to the piping for spaying a fine mist of water in the air.

1. Field of the Invention
This invention relates generally to a misting system and, more specifically, to a misting system which can be installed on any existing vehicle which has a water pump.
2. Description of the Prior Art
Many people like to spend their free time in the outdoors. Camping, boating and the like have become extremely popular outdoor activities. People are spending more and more money on recreational vehicles, trailers/campers, boats, and the like. The problem is that hot climates can make outdoor activities unbearable. What's the use of going camping or boating if the hot weather causes some people to stay in the RV or boat all day long.
For those people who are willing to bear the heat and go outside during the heat of the day, some relief can be obtained by finding shade to avoid direct sunlight. But even finding shade may be insufficient, especially if the temperature in the shade is 100 degrees F. or higher.
Some people have been using misting systems as a way to stay cool when outside. People have been installing misting systems on there patio as a way to cool off while enjoying the ability to be outdoors on their patio. A misting system works by produces a fine mist of water. The mist is sprayed into the air and enhances evaporative cooling of the skin.
Some people have installed misting systems on golf carts as a way to cool off while golfing in hot weather. U.S. Pat. Nos. 6,389,835 and 5,613,371 both disclose misting systems for golf carts. While these systems do work, they have several problems associated with them. The main disadvantage of these systems are that they are too expensive to install. The main reason for their expense is due to the fact that these systems require a new water pump and a new water storage reservoir since golf carts are not equipped with these items. Another problem with these systems are that they are difficult to install. A golf cart must be completely retrofitted for a misting system to be installed. There are presently no misting systems which can easily be installed on a golf cart.
Presently, there are no misting systems for recreational vehicles, campers, trailers, boats, or any other type of vehicle. Even if the above patents could be modified to be used on the above vehicles, the misting system would still suffer from the same disadvantages.
Therefore, a need existed to provide an improved misting system. The improved misting system must overcome the problems associated with the prior art. The improved misting system must be cheaper and easier to install on a vehicle than prior art misting systems.

Vehicle misting system and method therefor


The invention relates to a method for the coding and the availability of a chip card, which is provided as memory storage in a programmable control system. During the initial operation of a chip card with a control system a coding process is performed. The coding process specifies the chip card to the control system and encodes the chip card. The chip card can only be copied after the coding process. However, the copy can only be used in the control system on which the original or master chip card was coded. In the event of a defect in the system hardware, a chip card may be used in a second control system so that the total system installation remains available. The second control system remains functionally operable with a chip card for a time-limited period if the code of the chip card does not coincide with the code of the control system.

1. Field of the Invention
The invention relates to a method for operating installations comprised of chip-card-operated control systems, where the method limits the availability to a properly authenticated control system, and wherein a chip card, provided as storage medium in a control system, makes contact in a receiver device, and exchanges data corresponding to the specific coding of the chip card with the control system via a data bus.
2. Brief Description of the Background of the Invention Including Prior Art
Security methods and the corresponding arrangements furnished for this purpose for chip cards are known in a wide variety. The state of the art is extensively dealt with in the technical literature by Karlheinz Fiesta "Chipkarten: Technik, Sicherheit und Anwendungen", ("Chipcards: Techniques, Security and Applications"): Huethig-Verlag, 1989 on the pages 112-137. The presently available methods for the protection against unauthorized reading, writing and erasing as well as against duplication and simulation are described in this reference.
A limiting of the availability of a chip card is taught in the U.S. Pat. No. 4,808,802 to Kano. In this reference, the limiting refers only to the properly authenticated card owner.
The printed patent document WO 86/04170 teaches the storing of an expiration date into the memory storage of a chip card as part of the personalization method.
The coding possibilities of the last-mentioned method is oriented toward and targets personal identification.
The German Printed Patent Publication DE-OS 3,804,618 to Klaus Lindenschmidt teaches a programmable chip card. The properties of a chip card are mentioned in particular in column 1, lines 34-49. The German Printed Patent Publication DE-OS 3,523,237 to Thomas Krivachi teaches a transporting system for shipping chip cards between two manufacturers. The German Printed Patent DE-OS 3,639,113 teaches an apparatus for reading cards.
However, these known methods are not suitable for providing a solution of the problem posed in connection with the invention. Starting with the consideration to employ the chip card as storage medium for storage programmable controls, it is of understandable significance for the producer of the chip cards and of the control systems to secure the components such that no economic disadvantage can arise for the producer of the chip cards.
A chip card or a chip board card comprises in general microelectronic devices furnished as integrated circuits, memory storage, and the like implanted on a card-like support made of plastic, and wherein the microelectronic devices on the card-like support are connected to each other by an address bus, a data bus, and/or, respectively, by a control bus. The chip card is furnished with contact terminals for electronic interaction with an interface of a control system.

Method for operating installations comprising chip-card-driven control systems


A method of reducing leakage from a pipeline includes the steps of: pumping fluid through a pipeline using at least one pump, the at least one pump comprising a reversible, positive displacement fluid pump; detecting a leak in the pipeline downstream of the pump; reversing the at least one pump to draw fluid out of a downstream section of the pipeline; and redirecting the fluid being drawn from the pipeline into a storage container.

When transporting crude oil or other hazardous fluids through a pipeline, there is a risk of leaks from the pipeline or at a pipeline station. This can result in environmental damage, whether the leak occurs in a subsea or surface pipeline.
U.S. Pat. No. 3,702,744 (Brown et al.) describes a pump connected to a pipeline in an environmentally sensitive area. The pump is activated in the event of a leak to pump fluids out of the pipeline and into a container. U.S. Pat. No. 3,741,233 (Smith, Jr.) describes another system in which fluid flowing along a pipeline is redirected into a container in the event of a leak.

Method of reducing leaks from a pipeline


A print-job-information display system holds print jobs over a plurality of printers and displays information about a print job, for a predetermined system user, of among the print jobs being held. The system includes a collating-information acquiring section that acquires collating information to collate the system user, a plurality of print-job holding sections that hold a plurality of print jobs corresponding respectively to and relevant to the plurality of printers, in association with the collating information, a print-job-information acquiring section that acquires print-job information matched to the acquired collating information of among the information of the print jobs being held by the print-job holding sections, and a print-job-information display section that displays the acquired piece of print job information.

1. Technical Field
The present invention relates to a confidential printing system allowing for printing of only a print job whose system user is authenticated, and more particularly to a print-job-information-display system, program and method, print-job holding apparatus, print-job-holding-apparatus-control program and method, print-job manager, print-job-manager-control program and method, printer and printer-control program and method, that is suited to display the information of a print job whose system user is authenticated, as to a plurality of printers of a confidential printing system wherein the printers, having a confidential printing function, are connected through a network.
2. Related Art
There is an existing image-output control method and image-output apparatus, described in JP-A-2001-306273, wherein a person who instructed for printing is allowed to obtain a printing matter without being stolen a glance from a third person.
In the image-output control method and image-output apparatus of JP-A-2001-306273, when an authentication code is sent together with printing data from a client apparatus, a printer system generates collating data from the received printing data instead of immediately executing a printing. The printing data is encrypted by means of the authentication code, to generate save data. The save data and the collating data are associated together and stored in a storage device. When the user selects the save data and inputs an authentication code, the printer server decrypts the save data by use of the authentication code inputted, and determines whether or not the decryption has been done correctly. In the case correctly done, the decryption result is printed by the printer system.
In the system requiring a user's authentication upon printing an image, the printing data is temporarily held in the printers so that printing is allowed only for the printing data the user is authenticated, as in the existing art JP-A-2001-306273.
There is another existing art adapted to display a list of print-job information held by printers on a user-by-user basis. Printing is made only for the printing job corresponding to the information the user designated for a print job desired to print (see JP-A-9-39311).
However, in the art disclosed in JP-A-9-39311, where a plurality of print jobs are held, say, sporadically over a plurality of printers connected through a network, there is a difficulty in displaying a list of all the pieces of print-job information being held sporadically.
Meanwhile, such a list of print-job information is not desired to be glanced by a third person from a view point of the characteristic of the system of JP-A-2001-306273 and JP-A-9-39311. When a list is displayed in such a place as possibly glanced by a third person, the user desirably can search an objective print job in a short time to a possible extent.

Print-job information display system, printing system, print-job manager, print-job manager control program and method, printer, and printer control program and method


The display device drive unit includes a liquid crystal driver that generates a liquid crystal driving voltage for display device driving, and can operate in a master mode for outputting the foregoing voltage and in a slave mode for driving the display device in accordance with the liquid crystal driving voltage that has been inputted from the outside. The display device drive unit further includes a selection register for storing mode information that indicates whether the liquid crystal drivers is set to be in the master mode or the slave mode, and the liquid crystal driver outputs the liquid crystal voltage when the mode information indicative of the master mode is stored, and stops outputting the foregoing voltage when the mode information indicative of the slave mode is stored. Thus, it is not necessary to provide a setting terminal for switching between the master mode and the slave mode, and it is also possible to switch between both the modes after the drive unit has been packaged in the display device.

A liquid crystal display device is provided with a liquid crystal driver for driving a liquid crystal panel for example. The liquid crystal driver generates a liquid crystal driving output, that drives the liquid crystal panel, from a liquid crystal driving voltage. As to the liquid crystal driver, the following conventional techniques are mainly applied, so as to obtain the liquid crystal driving voltage, according to purpose of use of the liquid crystal panel.    1. A technique in which liquid crystal driving voltages are provided to all the plurality of liquid crystal drivers from an external power source provided as a part of the liquid crystal driver.    2. A technique in which a voltage which functions also as a logic voltage is provided to the liquid crystal driver from a power source for logic driving so as to generate the liquid crystal driving voltage in the liquid crystal driver (note that, in a case where a voltage is generated by boosting the logic voltage, each liquid crystal driver includes a boosting circuit therein).    3. A technique in which a voltage which functions also as the logic voltage is provided to one of plural liquid crystal drivers, so as to generate the liquid crystal driving voltage in the liquid crystal driver, then providing the liquid crystal driving voltage to other liquid crystal drivers (note that, in a case where the liquid crystal driving voltage is generated by boosting the logic voltage, the corresponding liquid crystal driver includes a boosting circuit therein).
FIG. 7 shows an example of the foregoing prior art 1. A display device drive unit 101 shown in FIG. 7 is provided with a plurality of, for example, four liquid crystal drivers 103. A logic voltage of 3V for example and a liquid crystal driving voltage b of 15V for example are inputted from an external power source (not shown) to the liquid crystal drivers 103. Besides, a control signal c and a data signal d are inputted from a controller (not shown) to the liquid crystal drivers 103. Note that, description concerning a driver for driving a common electrode is omitted. The description is also omitted in FIG. 8 illustrating the prior art 2 and FIG. 9 illustrating the prior art 3.
In each liquid crystal driver 103, a liquid crystal driving output e of 0 to 15V for example is generated from the liquid crystal driving voltage b in accordance with resistance division etc. for example. The liquid crystal driving output e is outputted to the liquid crystal panel 102 in accordance with the control signal c and the data signal d. Thus, display is created in the liquid crystal panel 102 in accordance with the data signal d.
In the arrangement of the prior art 1, the liquid crystal driving voltage b is provided from the external power source, so that an extra circuit such as the boosting circuit is not required in the liquid crystal driver 103.
Next, FIG. 8 shows an example of the prior art 2. A display device drive unit 111 shown in FIG. 8 includes two liquid crystal drivers 112, and each of the liquid crystal drivers 112 has a boosting circuit 113 and a driving circuit 114. The logic voltage a of 3V for example is provided from a logic driving power source (not shown), which functions as an external power source, to each boosting circuit 113. Further, the control signal c and the data signal d are inputted from a controller 115 to the liquid crystal driver 112.
The boosting circuit 113 of the liquid crystal driver 112 generates the liquid crystal driving voltage b of 15V for example by boosting the logic voltage a of 3V for example, and the liquid crystal driving voltage b is outputted to a driving circuit 114. In the driving circuit 114, a liquid crystal driving output e of 0 to 15V for example is generated from the liquid crystal driving voltage b, and the liquid crystal driving output e is provided to the liquid crystal panel 102 in accordance with the control signal c and the data signal d.
In the display device driving unit 111, a dual scan mode based on a duty driving system using an STN liquid crystal is applied. In this case, a segment electrode of the liquid crystal panel 102 is divided into two electrodes (upper and lower electrodes), and there are provided the liquid crystal drivers 112 which drive the upper and lower electrodes respectively.
Next, FIG. 9 shows an example of the prior art 3. A display device driving unit 121 shown in FIG. 9 includes two liquid crystal drivers 122a and 122b, and each of the liquid crystal drivers 122a and 122b includes the boosting circuit 113 and the driving circuit 114. The logic voltage a of 3V for example is provided from the logic driving power source (not shown), that functions as an external power source, to each boosting circuit 113. Further, the control signal c and the data signal d are inputted from the controller 115 to the liquid crystal drivers 122a and 122b.
Each of the liquid crystal drivers 122a and 122b includes a setting terminal 123, and how voltages are provided to the liquid crystal drivers 122a and 122b varies depending on how the setting terminal 123 is set.
That is, the liquid crystal driver 122a, in which the setting terminal 123 is set to be High (logic power source voltage), allows the boosting circuit 113 to function. Thus, the logic voltage (3V) a is inputted to the liquid crystal driver 122a, so that the liquid crystal driving voltage (15V) b obtained by boosting the logic voltage a can be externally outputted.
While, the liquid crystal driver 122b, in which the setting terminal 123 is set to be Low (GND potential), does not allow the boosting circuit 113 to function. Thus, the liquid crystal driving voltage b is inputted from the outside to the liquid crystal driver 122b. Namely, the liquid crystal driving voltage b is inputted from the boosting circuit 113 of the liquid crystal driver 122a via a power feeder 124. The setting of the liquid crystal driver 122a is called "master mode", and the setting of the liquid crystal driver 122b is called "slave mode".
As described above, the liquid crystal driver 122a in the master mode generates the liquid crystal driving voltage b from the logic voltage a by means of the boosting circuit 113, and generates the liquid crystal driving output e from the liquid crystal driving voltage b by means of the driving circuit 114, so as to cause the liquid crystal panel 102 to create display in accordance with the liquid crystal driving output e. Further, the liquid crystal driving voltage b is outputted to the other liquid crystal driver 122b.
While, the liquid crystal driver 122b receives the liquid crystal driving voltage b from the liquid crystal driver 122a in the master mode, and generates the liquid crystal driving output e from the liquid crystal driving voltage b by means of the driving circuit 114, so as to cause the liquid crystal panel 102 to create display in accordance with the liquid crystal driving output e.
Note that, Japanese Unexamined Patent Publication No. 62746/1998 (Tokukaihei 10-62746)(Publication date: Mar. 6, 1998) discloses a similar technique, but it does not concern a power source. That is, this publication indicates a mode such that: a level shifter, which level-shifts an input signal of a vertical driver (corresponding to a common electrode driver) operating at a high voltage, is disposed only on a vertical driver in a master mode, and the input signal, outputted from the vertical driver in the master mode, that has been level-shifted, is received by a vertical driver in a slave mode.
It is general that the liquid crystal panel driven by the liquid crystal driver is under a loading condition in terms of capacity, so that it is necessary to charge and discharge the liquid crystal panel. Thus, a power source of the liquid crystal panel is required to provide a large quantity of current according to variation of outputs. In a case where power supplying ability is insufficient, a power source voltage itself varies. As a result, a bad influence is exerted on display of the liquid crystal panel.
The prior art 1 has the following advantage: external power sources providing the liquid crystal driving voltages b are additionally provided on all the plurality of liquid crystal drivers 103, so that it is possible to provide a power source appropriate for a property of the liquid crystal panel 102.
However, it is necessary to provide the external power sources. This increases the cost, and brings about necessity to make rooms for packaging the power sources thereon.
The prior art 2 is such that: the respective liquid crystal drivers 112 include the boosting circuits 113 which function as the power sources, so that the boosting circuits 113 are dispersively provided on the respective liquid crystal drivers 112. Thus, the power supplying ability of the boosting circuit 113 may be a little. Further, this does not increase the cost unlike the case where additional power sources are packaged.
However, it is impossible to equalize output voltages of the individual boosting circuits 113, that is, the output voltages are different from each other. Thus, it is difficult to create high quality display in the liquid crystal panel 102. That is, although preferable results may be brought about by other display conditions and display properties, the following problem tends to be brought about: as to the liquid crystal panel 102, in a case where one liquid crystal driving voltage b is different from other liquid crystal driving voltage b by 10 mV when a uniformed image is displayed on the entire screen for example, human eyes recognize the difference. Thus, it is impossible to use the prior art 2 in the case where the uniformed image is displayed on the entire screen. Further, it is general that power consumption of the boosting circuit 113 is large. Thus, when the boosting circuit 113 is operated in the liquid crystal driver 112, the power consumption of the liquid crystal driver 112 is increased.
The prior art 3 is such that: the boosting circuit 113 which functions as the power source is operated in a single liquid crystal driver 112, and the liquid crystal driving voltage b obtained therefrom is provided to other liquid crystal driver 122b. Thus, it is possible to reduce the power consumption. Further, variation of the output voltage of the boosting circuit 113, that is, variation of the liquid crystal driving voltage b uniformly occurs in each of the liquid crystal drivers 122a and 122b. Thus, this brings about an advantage that uneven display brought about by the variation of the liquid crystal driving voltage b is hardly seen.
Particularly in a case where a liquid crystal panel for a cellular phone is operated in accordance with dual scan driving, the following arrangement is applied: The liquid crystal drivers are disposed along both ends (upper and lower ends in FIG. 9) of the liquid crystal panel 102 as shown in FIG. 9, and the one is used in the master mode to obtain the liquid crystal driving voltage b by boosting, and the other is used in the slave mode to receive the liquid crystal driving voltage b that has been generated in the master mode. In this case, there is an advantage that: it is possible to simplify the power source circuits in the entire system, and to reduce the number of the boosting circuits 113 which consume a large quantity of current, and to uniform the liquid crystal driving voltages b in the respective liquid crystal drivers.
Incidentally, the invention of the aforementioned Tokukaihei 10-62746 includes LSIs which are different from each other as a master chip and a slave ship, that is, an LSI having the boosting circuit 113 therein and an LSI having no boosting circuit 113 therein. In this case, it is necessary to form LSIs, different from each other in a circuit arrangement, that function as the liquid crystal drivers, so that this increases the cost. Then, there is provided the setting terminal 123, which is used to switch between the master mode and the slave mode as shown in FIG. 9, so that there is formed an LSI which can be switched between the master mode and the slave mode. Upon packaging the LSI on the liquid crystal panel 102, the setting terminal 123 is set (fixed) to a desired mode.
However, according to the arrangement in which the liquid crystal driver is set to be in the desired mode by means of the setting terminal 123, it is necessary to provide a signal wiring 125, setting the mode, that is connected to the setting terminal 123 upon packaging the liquid crystal driver (LSI). Alternately, in a plurality of packages of the liquid crystal driver (LSI), for example, in TCPs (tape carrier packages), it is necessary to prepare a setting terminal whose level is fixed to High level and a setting terminal whose level is fixed to low level in the wiring provided in the TCP. Thus, this increases the cost.
Further, in the foregoing arrangement, it is impossible to switch the power supplying mode (current supplying ability) once the liquid crystal driver (LSI) is packaged. Thus, in the case where the ability of the power source is insufficient corresponding to the display condition, it is impossible to switch the voltage supplying mode so as to exhibit the ability required in creating display. As a result, it is necessary to set the power source by estimating the maximum power consumption, so that this increases the cost.

Display device drive unit and driving method of display device


Methods and process for detection of myocardial ischemia involve detection and analysis of changes in electrical conduction velocity within the heart to monitor changes in the condition of the cardiac muscle and indicate possible ischemia. Conduction velocity slows considerably when oxygen supply to the heart is reduced. Analysis of electrical conduction velocity can be used to verify the occurrence of myocardial ischemia in a more reliable manner. Changes in conduction velocity may be monitored based on conduction time between electrodes positioned in the left and right ventricles of the heart. The electrodes may be endocardial or epicardial electrodes. In general, the techniques may involve launching a stimulation waveform at one electrode and sensing a local cardiac depolarization at another electrode to assess conduction time.

Myocardial ischemia, a leading cause of mortality, involves oxygen starvation of the myocardium. Myocardial ischemia can lead to myocardial infarction if left untreated. Early detection of myocardial ischemia provides the opportunity for a wide range of effective therapies such as revascularization, neural stimulation, and drug delivery to reduce cardiac workload or improve cardiac circulation. Unfortunately, many episodes of myocardial ischemia do not cause excessive pain or other noticeable warning signs, and often go undetected.
An electrocardiogram (ECG) or electrogram (EGM) presents a PQRST waveform sequence that characterizes the cyclical cardiac activity of a patient. The ST segment, also associated with the repolarization of the ventricles, is typically close in amplitude to the baseline, i.e., isoelectric amplitude of the signal sensed in the TP or PQ segments. During episodes of myocardial ischemia, the ST segment amplitude often deviates from the baseline. Accordingly, deviation in the ST segment is often used to identify an occurrence of myocardial ischemia. Hence, an implantable medical device may be equipped with an ischemia detector that indicates an ischemic condition based on elevation or depression of the ST-segment relative to a baseline. Alternatively, the ischemia detector may rely on a measure of heart activity or patient workload.
Unfortunately, the use of the ST segment as an indicator of ischemia can be unreliable. The ST segment may deviate from the baseline due to other factors, causing false indications of myocardial ischemia. For example, the ST segment may deviate from the baseline due to changes in the overall PQRST complex, possibly caused by axis shifts, electrical noise, cardiac pacing stimuli, drugs and conduction aberrancy that distorts the PQRST complex. In addition, the occurrence of cardiac ischemia may not manifest as changes in the ECG or EGM signals. Consequently, the reliability of the ST segment as an indicator of myocardial ischemia can be unacceptably low.
U.S. Pat. No. 6,128,526 to Stadler et al. describes an ischemia detector that observes variation in the ST segment to identify an ischemic condition. To improve reliability, the detector is designed to filter out ST segment variations caused by factors other than ischemia, such as axis shift, electrical noise, cardiac pacing, conduction aberrancy, and other distortions in the overall PQRST complex. Nevertheless, the sensitivity and specificity of ischemia detection based on observation of ST-segment changes is suboptimal. Accordingly, there continues to be a need for a simplified system capable of automatically and reliably detecting myocardial ischemia.

Ischemia detection based on cardiac conduction time


A pair of infrared linked stereoscopic glasses (18) receives a train of short infrared pulses from a transmitter (26) of a stereoscopic imaging system (10). The rising edges of the infrared pulses are synchronized with the beginnings of the even numbered fields of a stereoscopic image displayed on a video display (14). In a stereo mode, the glasses provide a three-dimensional appearance because right and left liquid crystal cells (40 and 42) switch right- and left-eye pieces (20 and 22) between transmissive and opaque states synchronously with the even and odd fields of the stereoscopic image. In a flickerless mode, the right- and left-eye pieces are both essentially continuously transmissive. An optical state controller (36) is self-synchronizing in that a single pulse of the electrical pulse train signal will control the optical states of both the right- and left-eye pieces during a complete stereoscopic image. The transmitted IR pulses are not modulated and the electrical pulse train signal produced in response to the received IR pulses is not demodulated. The glasses automatically switch from stereo mode to flickerless mode when the glasses cease receiving the IR pulses. The glasses automatically switch from flickerless mode to stereo mode when the glasses begin to receive the IR pulses. The maximum voltage (VDD) applied to the electrodes (184, 186, 206, and 208) of the right and left liquid crystal cells is substantially higher in stereo mode than that in flickerless mode.

Stereoscopic imaging systems have been employed to give a three-dimensional appearance to field sequential images displayed on a video display screen. The three-dimensional appearance is created by active stereoscopic glasses that switch between opaque and transmissive optical states to alternately transmit to a viewer left- and right-eye views of a stereoscopic image that is sequentially displayed on the screen. The viewer fuses the separate left- and right-eye views into a single stereoscopic image.
In certain prior stereoscopic imaging systems, the active stereoscopic glasses are linked to the video display with wires. This is undesirable, however, because the wires tether the viewer to the video display. To overcome this problem, other stereoscopic imaging systems have used electromagnetic radiation to link the stereoscopic glasses to the video display. For example, U.S. Pat. No. 4,967,268 of Lipton et al. ("Lipton et al. patent"), entitled "Liquid Crystal Shutter System for Stereoscopic and Other Applications," describes electromagnetically linked active stereoscopic glasses.
In the system of the Lipton et al. patent, the transmitted electromagnetic signal includes pulse width modulated information. As shown in FIG. 10 and described in col. 7, lines 30-68 of the Lipton et al. patent, the electromagnetic signal includes a 61 microsecond start pulse. If the electromagnetic signal continues for an additional 61 microseconds following the start pulse, the signal receiver circuitry causes the left-eye piece to be transmissive and the right-eye piece to be opaque. If the electromagnetic signal is not present for the next 61 microseconds following the start pulse, the signal receiver circuitry causes the right-eye piece to be transmissive and the left-eye piece to be opaque. The demodulating circuitry employed in the signal receiver circuitry creates unnecessary complexity and expense.
There is a need, therefore, for electromagnetically linked stereoscopic glasses that do not employ demodulating circuitry.

Self-synchronizing optical state controller for infrared linked stereoscopic glasses


In general, one embodiment of the invention features a method comprising operations performed internally within a device. A first operation involves generating data for permanent storage in a protected area of internal memory of the device. This prevents subsequent modification of the data. A second operation involves producing a secret value being a combination of both the data and a short term value generated in response to a periodic event such as a power-up sequence of a platform employing the device.

1. Field
This invention relates to the field of data security. In particular, the invention relates to a platform and method for generating and distributing a secret value between multiple devices.
2. Background
In electronic commerce, it is becoming necessary to transmit digital data from one location to another in a manner that is clear and unambiguous to a legitimate receiver, but incomprehensible to any illegitimate recipients. Accordingly, such data is typically encrypted by a software application executing some predetermined encryption algorithm and is transmitted to the legitimate receiver in encrypted form. The legitimate receiver then decrypts the transmitted data for use. Often, encryption/decryption of data is accomplished through symmetric key cryptography. For symmetric key cryptography, the sender uses a secret value as a key to encrypt data prior to transmission over an unsecured link. The receiver uses the same secret value as a key to decrypt the data upon receipt. One problem associated with symmetric key cryptography is that it is difficult for devices, such as platforms or integrated circuit components for example, to distribute a secret value in a secure manner.

Creation and distribution of a secret value between two devices


One embodiment disclosed relates to a method of processing a packet sent to a provider network. The packet is received via a user port of an edge switch of the network. Forwarding and routing by the edge switch is determined based on a user VID. A provider VLAN tag, including a provider VID, is inserted into the packet prior to transmission of the packet via a provider port of the edge switch.

1. Field of the Invention
The present invention relates generally to networking and communications technology.
2. Description of the Background Art
Local area networks (LANs) that are IEEE 802 compliant may be connected together with media access control (MAC) bridges. The IEEE 802.1Q standard defines the operation of virtual LAN (VLAN) bridges that permit the operation of VLANs within a bridged LAN infrastructure. In accordance with IEEE 802.1Q, data frames may be routed between ports of the VLAN according to VLAN tags. Double Q tagging is an enhancement to IEEE 802.1Q. One technique for implementing double Q tagging has disadvantages that are discussed below.

Hewlett-Packard Development Company, L.P.