The present invention provides a drive mechanism having a high rigidity and capable of performing fine adjustment in 6-axis directions of an optical element such as a mirror or a lens, or a support member for supporting the optical element, in optical equipment such as an exposure device. The drive mechanism has such a feature that three monolithic planar 3-joint or 4-joint link mechanisms are each arranged between a movable portion and a stationary portion through the intermediation of a bearing having at least one degree of freedom of rotation.

1. Field of the Invention
The present invention relates to a precision adjustment/drive device, and more specifically to a device for performing fine adjustment on the orientation of an optical element (such as a lens or a mirror) of an exposure device used in the process of manufacturing a semiconductor or a liquid crystal device. In more detail, such orientation adjustment is performed during image formation in which an image on an original (e.g. a mask, a reticle, or the like) is projected to a target object. (e.g. a wafer) through exposure by using the optical element, for effecting the image formation with enhanced accuracy.
It is to be noted that, other than for the optical element adjustment described above, a mechanism described in the present invention can be used for performing 6-axis scanning of a movable portion such as a workpiece of a three-dimensional measurement instrument or a machine tool, a precision moving table, or a specimen mount of a microscope.
2. Related Background Art
A semiconductor exposure device is a device for transferring patterns on an original (reticle) having many different kinds of patterns formed thereon to a silicon wafer (base). For preparation of a high-density circuit, not only resolution performance but also enhanced accuracy of superposition is essential. A superposition error in semiconductor exposure devices is classified into an alignment error, an image distortion, and a magnification error. An alignment error can be mitigated by adjusting relative positions of the original (reticle) and the base (wafer) with respect to each other. On the other hand, an image distortion and a magnification error can be mitigated by moving a part of the optical elements of an optical system. When moving an optical element in the direction of the optical axis, care needs to be taken so that an error in the amount of movement in the movement direction of the optical element, and movement components in directions other than the movement direction, in particular a positional deviation (referred to as "parallel eccentricity") in a direction orthogonal to the optical axis of the optical element and a tilt of the optical element (referred to as "tilt eccentricity"), do not become large.
As a conventional optical element moving device for use in semiconductor exposure devices, there has been devised one as described in Japanese Patent Application Laid-Open No. 2000-357651 which employs a mechanism using a parallel flat spring.
FIGS. 16A and 16B are respectively a sectional view and a top view of the conventional optical element moving device. As shown in the figures, the conventional optical element moving device includes: a movable table 1 for retaining an adjusting lens 7 for adjusting the magnification, abberration, and the like of an optical system, and a cell 8 for supporting the adjusting lens 7; and a stationary table 2 constituting a part of a stationary portion of a projection optical system. A ring-shaped flat spring 11 is fixed to both end faces of the movable table 1 and the stationary table 2 so as to seal both the end faces. The movable table 1 has a cylindrical configuration, and a diameter of its upper surface is different from that of its lower surface. Likewise, the stationary table 2 also has a cylindrical configuration, and an inner diameter of an opening in its upper surface is different from that of an opening in its lower surface. The stationary table 2 has at least one hole, and is thus capable of changing the position of the movable table 1 by changes in the pressure or volume of a drive fluid.
As another conventional example, there is an optical element fine adjustment device as disclosed in U.S. Pat. No. 5,986,827. However, the structure disclosed therein allows fine adjustment in only three axes, and does not allow adjustment within the plane of an optical element, making the device inadequate for applications which require high-precision adjustments on the position and orientation of an optical element.
As still another conventional example, there is one disclosed in Japanese Patent Application Laid-Open No. 2002-131605. However, the device disclosed therein employs a contraction mechanism using a long-arm lever (the distance from the fulcrum to the point of application or the point of action is long), and thus it is expected that the device has a low natural frequency. When the natural frequency is low, vibrations from the exterior of the device are transmitted to a movable portion, which is not only unpreferable for high-precision position and orientation adjustments but also makes it difficult to perform high-speed drive.
With the invention disclosed in Japanese Patent Application Laid-Open No. 2000-357651, parallel eccentricity and tilt eccentricity components, generated in accordance with movement of an optical element, are dependent on the accuracy of guiding by a flat spring guide. In addition, the initial position and the orientation of the optical element are dependent on the assembling accuracy of the device. However, as semiconductor device patterns become increasingly fine, optical elements are increasingly required to realize higher position accuracy, higher orientation accuracy, and higher drive position positioning accuracy for correction of aberrations etc, than conventionally required. For this reason, the devices as disclosed in Japanese Patent Application Laid-Open No. 2000-357651 and U.S. Pat. No. 5,986,827, which perform only one-axis drive and three-axis drive, respectively, are inadequate and a device capable of performing adjustment along three orthogonal axes in a translational direction and also about three axes in the translational direction, thus in 6 axes in total, is being demanded.
Further, in order to mitigate positional displacement of an optical element due to vibrations entering from the exterior of the device, high rigidity is required of the above 6-axis adjustment mechanism at the same time.
In view of the above, an object of the present invention is to provide a drive mechanism or a positioning mechanism which is capable of performing fine adjustment in 6 axis directions and has high rigidity.

Drive mechanism, exposure device, optical equipment, and device manufacturing method


An endoscopic instrument assembly for fastening bodily tissue is disclosed. The assembly includes a surgical instrument for insertion into and withdrawal from the passageway of a cannula. The instrument has a tube with a neckdown region between the proximal and distal ends of the tube. The proximal and distal ends of the tube have a diameter greater than the neckdown region. When the instrument is inserted into the passageway of the cannula, the radial clearance at the neckdown region of the tube is greater than the clearance at the tube distal end. The instrument includes a suture filament for fastening the tissue, and a needle attached to the distal end of the filament. When the instrument is inserted through the cannula, the filament has a length where the needle lies adjacent the neckdown region of the tube and is contained within the greater radial clearance offered by the neckdown region. Consequently, the drag force observed during insertion of the instrument through the cannula because of frictional contact between the needle and the inner wall of the cannula is significantly lessened or avoided altogether. This reduction in drag force can be accomplished without sacrificing other important design features of the surgical instrument.

This invention relates to an assembly for facilitating the placement of a surgical knot made from a suture filament. In particular, the invention relates to such an assembly which is particularly adapted for deployment of the knot during minimally invasive surgical procedures where access to the surgical site is limited.
A mainstay of surgical practice has been and will continue to be the formation and placement of surgical knots from suture filament to fasten tissue during an operative procedure. Numerous surgical knots have been developed over an appreciable period of time, and the art of forming and tying knots for surgical applications is a critical skill which a surgeon must possess to perform an operation safely and efficiently. Accordingly, the art is extensively developed. See, for example, Tissue Approximation in Endoscopic Surgery, Alfred Cuschieri, Zoltan Szabo, Times Mirror International Publishers, 1995, which describes numerous surgical knots made from suture filament to facilitate the approximation of tissue during surgery.
The art of surgical knots is also well represented in the patent literature. U.S. Pat. No. 2,012,776 discloses a surgical instrument for facilitating the placement of various forms of slip knots made from surgical filament. The inventor named on the '776 patent, H. A. Roeder, developed the "Roeder Knot" which is a surgical knot which is frequently used in practice today. More recently, U.S. Pat. No. 5,573,286 discloses a surgical knot of suture strand particularly adapted for orthopedic applications. The preferred embodiment described in the '286 patent is directed to tying the knot to a bone.
Early on, it was recognized that the deployment and placement of surgical knots within a remotely accessible surgical site could be difficult, cumbersome and often unreliable. Accordingly, instrumentation was developed to facilitate the placement of knots in remote locations. Cleverly, a pre-tied knotted loop of suture was often used to reduce the number of steps required to form the tightened knot. For example, U.S. Pat. Nos. 2,566,625 and 3,090,386 describe surgical devices which are adapted to support a pre-tied knotted loop of suture for suturing or ligating tissue, particularly during procedures where the tissue desired to be manipulated is difficult to access.
More recently, instrumentation has been developed for facilitating the placement of knots particularly during minimally invasive surgical procedures. In particular, U.S. Pat. No. 5,320,629 discloses the formation of a pre-tied knotted loop of suture, and the placement of the pre-tied knotted loop on a surgical device for facilitating the tightening of the loop to approximate tissue during endoscopic surgical procedures. German Patent No. 912619 also discloses a device similar to that disclosed in the '629 patent.
Although the art of surgical knots is well developed, and surgical devices for facilitating the placement of tightened knots from a pre-tied knotted loop of suture have also been developed for application at remote surgical sites, there are problems which still need to be addressed. In particular, in those surgical procedures where access to the site is limited, for example during minimally invasive procedures such as endoscopic surgical procedures, the knots can be difficult to deploy. Frequently, the knots which can be deployed are routinely slip knots having poor knot security. If knot security is poor, then the approximated tissue may not be held for a sufficient period of time to promote adequate wound healing. Additionally, during minimally invasive procedures, the pre-tied knotted loops of suture which have been described in the prior art devices can be difficult to efficiently tighten for final deployment.
Therefore, in minimally invasive surgical procedures where access to the surgical site is limited, what is needed is an assembly for facilitating the formation of a surgical knot. The assembly should be relatively simple in construction and should be compatible with a partially tied surgical knot. The assembly should facilitate the conversion of the partially tied knot into a fully formed knot which can provide a consistently strong knot security each time the knot is placed to enable even an inexperienced surgeon to confidently and efficiently place a secure suture knot. Additionally, it would be desirable if it were possible to easily retrofit the assembly onto various surgical instruments, particularly endoscopic instruments, for ease of use of the assembly to place surgical knots. Finally, it would be helpful if it were possible to reload the assembly with a second partially tied knot following deployment of the first knot so that the assembly can be used to place multiple knots.
In addition, what is needed is a device to facilitate the loading of a suture cartridge assembly onto a surgical instrument. Specifically, what would advance the state of the surgical art would be a device which aids the surgeon to load the assembly onto a surgical instrument for deploying a surgical knot from the suture filament contained in the assembly, and to easily reload the instrument with a second suture cartridge assembly after the first spent assembly has been removed from the instrument. It would also be advantageous if such a device could be designed to avoid the need for the user to handle a needle when attached to the filament and to be a suitable container for shipping and storage of the suture cartridge when used in conjunction with the other packaging materials.
Further, in recognition of the need to facilitate knot tying endoscopically, what is also needed is an endoscopic instrument assembly which is capable of delivering the partially tied knot to the targeted anatomical structure within the internal body cavity during the endoscopic procedure. To that end, what is needed is an assembly which includes the knot tying instrument for efficient delivery through a trocar cannula. Specifically, it would be desirable if the suture filament and needle of the surgical knot tying instrument could be readily delivered through the cannula, without sacrificing or overly complicating the suture cartridge assembly or the resistance of the instrument to bending or tortial stresses incurred during use.

Endoscopic instrument assembly for fastening tissue


An apparatus for processing an encoded audio signal having a plurality of downmix signals associated with a plurality of input audio objects and object parameters. The apparatus includes a grouper configured to group the downmix signals into groups of downmix signals associated with a set of input audio objects. The apparatus includes a processor configured to perform at least one processing step individually on the object parameters of each set of input audio objects in order to provide group results. Further, there is a combiner configured to combine the group results or processed group results in order to provide a decoded audio signal. The invention also refers to a corresponding method.

The invention refers to an apparatus and a method for processing an encoded audio signal.
Recently, parametric techniques for the bitrate-efficient transmission/storage of audio scenes containing multiple audio objects have been proposed in the field of audio coding (see the following references [BCC, JSC, SAOC, SAOC1, SAOC2]) and informed source separation (see e.g. the following references [ISS1, ISS2, ISS3, ISS4, ISS5, ISS6]).
These techniques aim at reconstructing a desired output audio scene or audio source objects based on additional side information describing the transmitted/stored audio signals and/or source objects in the audio scene. This reconstruction takes place in the decoder using a parametric informed source separation scheme.
Unfortunately, it has been found that in some cases the parametric separation schemes can lead to severe audible artifacts causing an unsatisfactory hearing experience.

This patent is subject to a terminal disclaimer.

Apparatus and method for processing an encoded audio signal

Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.


A predictive video coder performs gradient prediction based on previous blocks of image data. For a new block of image data, the prediction determines a horizontal gradient and a vertical gradient from a block diagonally above the new block (vertically above a previous horizontally adjacent block). Based on these gradients, the encoder predicts image information based on image information of either the horizontally adjacent block or a block vertically adjacent to the new block. The encoder determines a residual that is transmitted in an output bitstream. The decoder performs the identical gradient prediction and predicts image information without need for overhead information. The decoder computes the actual information based on the predicted information and the residual from the bitstream.

A variety of protocols for communication, storage and retrieval of video images are known. Invariably, the protocols are developed with a particular emphasis on reducing signal bandwidth. With a reduction of signal bandwidth, storage devices are able to store more images and communications systems can send more images at a given communication rate. Reduction in signal bandwidth increases the overall capacity of the system using the signal.
However, bandwidth reduction may be associated with particular disadvantages. For instance, certain known coding systems are lossy, they introduce errors which may affect the perceptual quality of the decoded image. Others may achieve significant bandwidth reduction for certain types of images but may not achieve any bandwidth reduction for others. Accordingly, the selection of coding schemes must be carefully considered.
Accordingly, there is a need in the art for an image coding scheme that reduces signal bandwidth without introducing perceptually significant errors.

Video coder providing implicit or explicit prediction for image coding and intra coding of video


A pulley comprising a first pulley wheel and a second pulley wheel and a ratchet acting between the two pulley wheels. When substantially equal force is applied to each pulley wheel in use on a rope tail side causing the pulley wheels to rotate, a low gear ratio is achieved through a rope, chain or the like acting on a load through a block. When one pulley wheel is prevented from rotating and a force is applied to the other pulley wheel in use on a rope tail side causing it to rotate, then a higher gear ratio is achieved through a rope or chain or the like acting on a load through a block. When force is applied to the first wheel on a rope tail side and the second pulley wheel is allowed to rotate, then a still higher ratio is achieved in use through a rope, chain or the like acting on a load through a block. In another embodiment, the pulley comprises a first pulley wheel, a second pulley wheel and means to prevent relative rotation of the pulley wheels in one direction, the pulley wheels being able to rotate relative to each other in the other direction. In another embodiment, the pulley comprises a first pulley wheel, a second pulley wheel and means acting between the pulley wheels such that, a force acting to rotate the first pulley wheel in a first direction imparts a corresponding force to rotate the second pulley wheel in a second, opposite direction.

FIG. 1 shows a known differential pulley 10. Differential pulleys are used to lift heavy loads because they achieve a high gear ratio. A standard differential pulley 10 consists of two pulley wheels 12, 14 of different radii R, r which are fast with one another to rotate as one about a common axle. The differential pulley 10 is fixed in position so as not to move. A continuous chain 16 is run around both pulley wheels 12, 14 in opposite directions to create two hanging loops 18, 20. A moveable pulley block 22, which is connected to a load 24, is placed in a first hanging loop 18, and the load 24 is raised or lowered by pulling or releasing respectively a length of the second hanging loop 20. When the load 24 is being raised or lowered, the two pulley wheels 12, 14 rotate as one around the common axle and, because the chain 16 is reaved in opposite directions around each wheel 12, 14, the chain 16 winds upon one pulley wheel as it unwinds from the other. A high gear ratio is achieved because the pulley wheels 12, 14 have different radii. It is important that the chain 16 does not slip on the pulley wheels 12, 14, and so the pulley wheels 12, 14 have lugs (not shown) to engage the chain links and thereby prevent slipping.
The known differential pulley 10 achieves a single high power gear ratio which is determined by the radii of the two pulley wheels 12, 14, and it is not possible to achieve multiple gear ratios from a single known differential pulley 10. However, there are applications where more than one gear ratio is desired.
On a sailing boat 30, for example as shown in FIG. 2, when the mainsail 32 is being controlled, it is advantageous to be able to use a high gear ratio when large forces are acting on the mainsail 32, or when fine control of the position of the mainsail 32 is required. It is also advantageous to be able to trim the sail position quickly when maneuvering, and this requires that the pulley system 34 for the mainsheet 36 is configurable to have more than one gear ratio, preferably having at least one high power gear ratio and one low power gear ratio. The known differential pulley would not be useful for such applications. In the known boat shown in FIG. 2 the mainsheet pulley system acts between the boom 38 and a transverse spar 40 across the boat 30. A pulley system 42 is also used on the known boat 30 for the vang 44 or kicking strap to the boom 38.
Two-speed mainsheet block and tackle systems provide mainsail control with two gear ratios. For example, a mainsheet pulley system as shown in FIG. 3 with gear ratios of 4:1 and 16:1 are commercially available. Two-speed continuous mainsheet block and tackle systems, as shown in FIG. 4, having for example gear ratios of 2:1 and 4:1, 3:1 and 6:1, and 4:1 and 8:1 are also commercially available, for example, the Harken system 330 2-speed mainsheet system. However, only two gear ratios are possible with these block and tackle systems, and furthermore, the available gear ratios from a single system are relatively close to one another, thus preventing both very fine tuning and quick trimming of a mainsail with a single mainsheet system.


The present invention discloses a sanitary paper that is designed to be appropriate for dual functions: (1) as a tissue paper for wiping and cleaning by a user, and (2) as a toilet seat-cover. The sanitary paper is a folded continuous sanitary paper strip comprising detachable sections of tissue paper, where some sections are toilet seat-covers which are defined by appropriate transverse seat-cover perforation lines. Various embodiments are described regarding the folding of the sanitary paper strip. A precut bowl flap, in each of the detachable seat-covers, is provided as well. The sanitary paper strip can be made of a single or multi-ply paper. In the preferred embodiment of the present invention, the sanitary paper is made of a duplex paper, where each surface best serves the intended function of that surface. Additionally, the sanitary paper strip can be impregnated with various chemicals.

The present invention relates to a device for providing a sanitary paper that serves a dual function. The sanitary paper can serve as a tissue paper and as a toilet seat-cover. Among other features, this eliminates the need to maintain two types of sanitary paper in bathrooms.
Tissue paper and toilet seat-cover paper are soft, lightweight papers that are used in restrooms for personal hygiene. While the tissue paper is used for wiping the anus after defecation, the seat-cover paper is used to protect human skin from contacting the toilet seat surface. As sanitary papers which come in contact with human skin, and thus have to be disposed after use, both the tissue paper and the seat-cover paper are made of a soft, flushable, and water-soluble paper material. However, as a result of the differences in their specific tasks, they are usually differing in their paper/tissue type. Thus, for example, while tissue paper (which is designed mainly for cleaning of the anus) is usually composed of water-absorbing paper with a relatively rough surface, seat-cover paper (which is designed to protect human skin from contacting the toilet seat surface) is usually composed of a soft, smooth (glazed) paper, sometimes impregnated with chemicals (such as antibacterial compounds).
Today, as a result of the differences in their tasks and their material composition, tissue paper and seat-cover paper are usually packaged in a completely different configuration, and supplied to the customer as separate units. Thus, for example, while tissue paper is formed and supplied as a continuous strip packaged in a roll with a plurality of transverse perforations at regular intervals, seat-cover paper is usually supplied as separate sheets, packaged in a box-shaped dispenser.
Various types and configurations of tissue paper and seat-cover paper have been described in the prior art. Thus, for example, U.S. Pat. Nos. 2,025,941, 4,050,105 and 4,766,617 disclose disposable and flushable toilet seat-covers packaged as individual units, while U.S. Pat. No. 4,998,297 discloses reusable toilet seat-covers, packaged as individual units. U.S. Pat. No. 4,920,584 disclose a long sleeve of non-porous and non-biodegradable material that contains many non-disposable seat covers, while U.S. Pat. No. 5,107,549 discloses a disposable and flushable sleeve-shaped cover seat that is detachable from a continuous sheet packaged in a roll.
Another type of disposable seat cover that is packaged in a roll is disclosed in U.S. Pat. No. 4,627,117 and Japanese Patent 2000139774. In all cases of the prior art, the tissue paper and the seat-cover paper appear as separate units or in some type of package combination, such as those manufactured by Tubular Specialties Mfg. (TSM) located in California USA, and American Specialties Inc, (ASI) located in New-York USA.
Although it is of great importance to have seat-cover paper also in small public places such as restaurants, the present situation is far from that, even in private homes. This is counter to the fact that many people are reluctant to have contact with a toilet seat outside their own homes. A recent study shows that more than 90% of women would not sit directly on a toilet seat. Presently, it can be seen that, while use of tissue paper is widespread and it can be found in almost every home, seat-cover paper is found only in selected public places like hospitals, airports, and hotels.
Some of the reasons that hamper the wide commercial distribution of toilet seat-covers are: (1) the cost to manufacture such units, and (2) the relatively large and bulky dispensers, that are usually required for packaging and storage of the individually-folded, seat-cover sheets. Such bulky dispensers, in turn, necessitate the allocation of significant wall space to accommodate them. For these reasons, private citizens and owners of small public places (like restaurants) prefer not to buy the commercial, bulky, and expensive seat covers. Instead, they prefer to cut pieces of tissue paper (which they usually have a plentiful supply of), and prepare "hand-made" seat covers on the spot. Namely, they cut pieces of tissue paper, and arrange them around the rim of the toilet seat in such way that it will keep their skin from direct contact with the toilet seat.
Therefore, in order for such sanitary seat-cover paper to become attractive to private customers and small businesses also, it is of great importance to have a relatively inexpensive sanitary paper that can be used easily and conveniently as tissue paper, or alternatively, as a toilet seat-cover.

Tissue and toilet seat-cover sanitary paper


An insert for sports gear and footwear has a compliant casing formed of fabric sheeting that incorporates regions of fused or otherwise integral regions of activated carbon. A desiccant such as silica gel in the form of spheroidal beads or other granules is loosely enclosed inside of the casing. The activated carbon has an affinity for odor-causing constituents such as organic compounds, and extracts airborne odor-causing constituents as air enters the casing. Inside the casing, the desiccant extracts airborne water vapor. The two-stage removal of odor-causing constituents and water vapor rapidly and effectively extracts moisture and odors. The silica gel and activated carbon are porous and have high surface areas available for adsorption, whereby the insert is adapted to maintain moisture and odors at low levels during long-term storage.

The present invention relates to a means for counteracting odors and moisture accumulation in athletic footwear and other sports gear during use, and more particularly to devices insertable into shoes, boots, skates, gloves, shoulder pads, shin pads, sports bags, backpacks and other sports gear to draw moisture and odor-causing components away from their interior and exterior surfaces.
Sports gear, including, but not limited to footwear, has a well known tendency to collect moisture, largely from perspiration when in use, and also between uses when stored in closed containers or humid environments. Extreme or prolonged exposure to moisture can degrade and weaken the materials used in their construction, especially along inside surfaces. In addition, perspiration contains dissolved salts and organic compounds such as urea that can cause unpleasant odors as perspiration accumulates in such materials.
These problems can be more pronounced in athletic footwear due to more active and intensive usage, and also due to more frequent usage as in daily practices or training sessions. The requirements and style of certain athletic footwear can aggravate the problems. For example, the structural integrity required of ice skates results in the use of stronger, less porous material that extends upwardly to include the ankles. Thus, frequently used ice skates are particularly prone to the collection and retention of moisture and odor-causing organic constituents.
There are a variety of known approaches to counteract the moisture and odor accumulation in footwear, including powders and sprays, along with pads or insoles as disclosed in U.S. Pat. No. 4,185,402 (Digade) and U.S. Pat. No. 7,047,667 (Klavano).
U.S. Pat. No. 5,950,323 (Wroth et al.) and U.S. Pat. No. 6,378,224 (Qualkinbush et al.) disclose desiccant-containing devices that can be removably inserted into shoes and other footwear between uses. While both of these devices are said to remove moisture, the Wroth et al. device does not address the need to remove odor-causing constituents. Qualkinbush et al. notes that activated charcoal might be added to its desiccant material, but does not indicate what form the activated charcoal might take or the amount that might be added, nor does it recognize any need or desire to avoid intermingling these components. Specifically, the activated charcoal in granular form lacks the hardness of silica gel and other suitable desiccant materials. Thus, any device containing a mixture of the desiccant and activated charcoal would need to be handled with extreme care to minimize the fracturing, crumbling, and smudging of the charcoal granules that otherwise would occur from contact with the desiccant beads.
Accordingly, the present invention has several aspects directed to one or more of the following objects:                to provide a moisture and odor removal device that contains a first adsorbent component in the form of a desiccant and a second adsorbent component adapted to adsorb odor-causing constituents, in a manner that prevents any intermingling of these components;        to provide an insert for athletic equipment and footwear capable of rapidly removing moisture and odors between frequent episodes of use, and with sufficient moisture and odor retention capacity to prevent the accumulation of moisture and odors or bacteria during long-term storage;        to provide a footwear insert with an outer perimeter stage adapted to collect and retain airborne odor-causing constituents, and an inner stage adapted to collect and retain water vapor; and        to provide a device insertable into objects that more rapidly and effectively draws moisture and odor-causing constituents away from the material forming inside surfaces of the objects.


Provided is a mechanical-vibration detecting apparatus in which not only adjustment is easy but also mechanical vibration can be taken out with high accuracy, and a vibration-reduction control apparatus by which reduction of mechanical vibration can be achieved. In a motor control apparatus for controlling the torque of a motor, provided are an equivalent rigid body model 103; a proportional operation means 104; a high-pass filter 105; and means for adding a torque signal and an output of the proportional operation means to supply a resulting addition signal to the equivalent rigid body model, and for subtracting an output of the equivalent rigid body model from a velocity signal of the motor control apparatus to supply a resulting difference signal to the proportional operation means and to the high-pass filter so that an output of the high-pass filter is used as a mechanical vibration control signal.

As a mechanical-vibration detecting apparatus and a vibration-reduction control apparatus in a motor control system, there is an apparatus proposed in Japanese Patent Application No. 127859/94 filed by this applicant. In this prior art, a motor-containing mechanism system is separated into an equivalent rigid body system and a mechanical vibration system so that mechanical vibration is estimated at a high speed by an observer based on an equivalent rigid body system model to perform vibration reduction control.
In the prior art, however, a quadratic observer is constituted with the angular velocity and step-like torque disturbance of the equivalent rigid body system as state variables, so that not only an equivalent rigid body model and a proportional operation means but also an integrating operation means are required in order to constitute a mechanical-vibration detecting apparatus. Two parameters are required to be set for the observer and, furthermore, the phase of a mechanical vibration signal varies largely in accordance with the set-values of the parameters so that there arises a problem that it is difficult to adjust the parameters.

Mechanical vibration detector and vibration damping controller


A disk drive includes a drive housing, a storage disk, a head suspension assembly, an actuator assembly and a controller. The storage disk has a disk surface including a data region that stores data. In one embodiment, the head suspension assembly includes a slider and an attitude adjuster. The slider has an inner side edge, an outer side edge and a data transducer. The attitude adjuster can adjust a roll attitude and/or a pitch attitude of the slider relative to the disk surface. The slider moves between a first position wherein the data transducer is not positioned directly over the data region and a second position wherein the data transducer is positioned directly over the data region during one of a load operation and an unload operation. The controller controls an electrical signal to the attitude adjuster during one of the load operation and the unload operation to dynamically adjust the attitude of the slider. The attitude adjuster can include one or more piezoelectric elements that expand and/or contract to adjust the orientation of the slider relative to the storage disk.

Disk drives are widely used in computers, consumer electronics and data processing systems for storing information in digital form. The disk drive typically includes one or more storage disks and one or more head suspension assemblies. Each head suspension assembly includes a suspension and a slider assembly that transfers information to and from the storage disk. In many disk drives, in order to decrease the likelihood of unwanted contact between the slider assembly and the storage disk, the slider assembly is positioned off the storage disk when the drive is not powered up or when data transmission is not occurring. For example, the slider assembly can be moved onto a ramp positioned inward from an inner diameter or beyond an outer diameter of the storage disk, also referred to as "ramp load technology". Once the disk drive receives a command necessitating the transmission of data, an actuator repositions the slider assembly directly over a data storage area of the storage disk.
Because today's disk drives demand a greater and greater amount of data storage, utilizing as much of the disk surface of the storage disk for storing data has become of great importance. However, this desire to use more of the disk surface for data storage must be balanced with concerns of data loss and damage to the storage disk during repositioning of the slider assembly from the ramp to directly over the storage disk. Data loss can occur by damaging the storage disk with edges or corners of the slider during this type of repositioning of the slider, which can result in scratches or dings. Other types of disk contact can result in frictional heating, causing erasure of data, known as soft errors.
As a consequence, in conventional disk drives, an annular section of the disk surface near the inner and/or outer diameter is devoid of data tracks used for storing data. For example, in small form factor drives, as much as ten percent or more of the storage disk can be set aside for this purpose. Thus, despite the desire to increase data storage, a significant surface area of the disk surface is intentionally left vacant based on the higher degree of risk that any data in this area will potentially be lost.

Slider of a disk drive having data favorable load/unload attitude


In certain embodiments, device inspection or repair may be facilitated via signal-based determinations. In some embodiments, one or more flaws may be detected on a portion of a device via an optical sensor. Based on the detection, a physical structure may be caused to physically interact with the portion of the user device. Information indicating signals from the physical interaction may be obtained. Based on the signal information, a determination of whether a repair process should be performed on the device may be effectuated. The device may be assigned to be repaired via the repair process based on the determination indicating that the repair process should be performed on the device. In some embodiments, the signal information may be provided to a prediction model to determine whether the repair process should be performed on the device.

Advances in computing power and software development technologies (including technologies that facilitate automated assembly and repair) have made assembling and repairing devices faster and less costly. Despite such advancements, assembly and repair systems typically waste resources performing one or more unnecessary types of operations. As an example, with respect to scratch buffing, scratch buffing will often be performed on mobile devices with scratches or other similar physical flaws that cannot be buffed out to a satisfactory quality (e.g., such that the physical flaw is no longer practicably observable to the naked human eye). Thus, in such cases, time, energy, and other resources (whether machine or human resources) are needlessly utilized on such mobile devices. These and other drawbacks exist.


Disclosed is a novel multi-layered optical recording media and system for recording and reproducing information data. The multi-layered topical recording media has M information storage decks, and each information storage deck has N information storage layers, and each information storage layer has a pair of information storage structures. Each paired information storage structure has a characteristic wavelength and polarization state, and from which recorded information can be read by a laser beam having similar wavelength and polarization-state characteristics. In the illustrative embodiment, the multi-layered optical recording media of the present invention has MxNx2 information storage layers which can be read using only N laser lines (i.e. spectral components), thereby providing a 2M-fold increase in information storage capacity over prior art systems. The information storage and retrieval system of the present invention is completely backward compatible to allow for the reading of conventional CD-ROM devices.

1. Field of the Invention
The present invention relates to an information storage system employing a novel optical-based information storage media having multiple information storage layers each of which have a characteristic wavelength and polarization state, and from which recorded information can be read by a laser beam having similar wavelength and polarization-state characteristics in order to provide a significant improvement in information storage capacity.
2. Brief Description of Prior Art
In the contemporary period, there is a great need for high density information storage media. For decades, magnetic disc and tape have been the dominant information storage media for recording both analog and digital information. In more recent times, the trend has changed to optical storage media because of its higher information storage capacity. In principle, each optical storage media exploits one or more characteristics of light and its interaction with matter in order to store and access information.
In conventional optical CD-ROM technology, digital information in the form of a logical xe2x80x9c0xe2x80x9d is recorded as a microscopic protrusion formed on the reflective surface of the compact disc along a continuous spiral track, whereas a logical xe2x80x9c1xe2x80x9d is recorded as a microscopic section of planar surface area the size of about the cross-sectional diameter of the focused laser beam used during information reading operations. When an incident laser beam is reflected off such microscopic protrusions during information reading operations, a reduction in intensity of the reflected laser beam is detected by the photodetector of the CD-ROM drive unit and is converted into a logical signal. In conventional CD-ROM technology, the primary limitation on information storage capacity is determined by protrusion size. Consequently, great efforts are being undertaken to make inexpensive laser diodes that produce laser beams with shorter wavelengths for use in detecting smaller-sized protrusions during information reading operations.
Recently, there have been attempts to increase the information storage capacity of conventional CD-ROM devices. One technique in particular, which has received popular attention, is disclosed in U.S. Pat. No. 5,381,401. In essence, this technique involves stacking up multiple information layers of optically, substantially transmissive material, each realized by an regular CD disc having a thin aluminum film coating with a light reflectance of about 4%. By adjusting the depth of focus of the laser beam used during information reading operations, it is possible to read information from a selected information storage disc. However, a major drawback with this prior art technique is that only a relatively small number of information layers can be stacked up before severe attenuation of the reflected laser beam occurs, thereby resulting in an unacceptable signal-to-noise ratio and thus system performance.
An altogether different approach to optical mass storage has been taught in recently issued U.S. Pat. No. 5,353,247 to Faris, co-applicant of the present application. Rather than using semi-reflective coatings, as taught in U.S. Pat. No. 5,381,401, U.S. Pat. No. 5,353,247 teaches the use of the wavelength-selective property of the Cholesteric Liquid Crystal (CLC) material, and discloses an optical storage media comprising multiple information storage layers made of CLC material. However, a major drawback with this prior art system is that N laser lines (i.e. spectral components) are required to read N number of CLC-based information storage layers. How this shortcoming might be overcome is neither disclosed, taught or suggested by the prior art.
Thus there presently is a great need in the art for an improved method and apparatus for storing and retrieving information in a manner which achieves a substantial improvement in information storage capacity over prior art systems and methodologies.
Accordingly, a primary object of the present invention is to provide a novel optical information storage media which overcomes the shortcomings and drawbacks of prior art apparatus and methodologies.
Another object of the present invention is to provide novel information storage media which exploits both the wavelength-dependent and polarization-dependent reflective properties of particular optical materials.
Another object of the present invention is to provide a novel optical information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of CLC material.
Another object of the present invention is to provide a novel optical information storage structure comprising a pair of information storage layers, each of which exploit both the wavelength-dependent and polarization-dependent reflective properties of CLC material or multilayer dielectric thin-films so that digital information stored therein can be read in either a sequential or parallel manner.
Another object of the present invention is to provide a novel optical information storage system which employs an optical storage media having a single information storage deck with 2xN CLC-based information storage layers which can be read using only N laser lines (i.e. spectral components).
Another object of the present invention is to provide a novel optical information storage system which employs an optical storage medium having M information storage decks, wherein each storage deck has 2N CLC-based information storage layers, and the MxNx2 information storage layers can be read using only N laser lines (i.e. spectral components).
Another object of the present invention is to provide such an optical information storage system, in which an optical pick-up is employed that controls the polarization state of the laser beam as it is incident upon the optical storage medium during information reading operations.
Another object of the present invention is to provide such an optical information storage system, in which an optical pick-up is employed that controls the polarization state of the laser beam after it reflects off the optical storage medium during information reading operations.
Another object of the present invention is to provide a novel optical information storage media which exploits both the wavelength-dependent and polarization-dependent reflective properties of CLC material, and which can be realized in the form of a compact disc, tape, or card.
Another object of the present invention is to provide a novel method of manufacturing multilayered optical-based storage media having wavelength and polarization-state dependent characteristics.
Another object of the present invention is to provide a novel method of manufacturing an optical information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of CLC material.
Another object of the present invention is to provide a novel method of manufacturing a multi-layer information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of multilayer dielectric thin-films.
Another object of the present invention is to provide a novel optical pick-up for reading digital information recorded in a multi-layered information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of CLC material.
Another object of the present invention is to provide a novel optical pick-up for reading digital information recorded in a multi-layered information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of multilayer dielectric thin-films.
Another object of the present invention is to provide a novel optical pick-up for simultaneously reading digital information stored in the information recording tracks of a paired multi-layered information storage structure which exploits both the wavelength-dependent and polarization-dependent reflective properties of either CLC material or multilayer dielectic thin-films.
Another object of the present invention is to provide a novel information storage disc drive unit capable of reading CLC-based information storage discs of the present invention, as well as conventional CD-ROMs, thus providing an easy and inexpensive way to upgrade the information storage and reading capabilities of a computer system, without the need to discard conventional CD-ROMs in the possession of its user.
Another object of the present invention is to provide a novel method and apparatus for precisely aligning the information recording tracks formed in the information storage layers of a paired information storage structure.
These and other objects of the present application will become apparent hereinafter and in the Claims to Invention.

Multi-layer optical recording media and system for recording and reproducing information data


A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.

1. Technical Field of the Invention
This disclosure relates to a flash memory device and, more particularly, to a flash memory device having a column predecoder capable of selecting all column selection transistors and a stress test method thereof.
2. Description of the Related Art
A flash memory device is a highly integrated information storage device in which write and erase operations can be done on board. A flash memory cell includes one field effect transistor (FET) having a selection gate, a floating gate, a source, and a drain. Variation of a threshold voltage of the flash memory cell results in fluctuation of the amount of charges on a floating gate. The fluctuation is information, which is stored in the flash memory cell. A flash memory device is classified as either a NAND flash memory device or a NOR flash memory device. NAND flash memory devices are used as a mass data storage devices, and NOR flash memory devices are used as information storage devices for processing data at a high speed.
Generally, a NOR flash memory cell has two states, i.e., a programmed state and an erased state. When the NOR flash memory cell is programmed, residual electrons are trapped on a floating gate and a threshold voltage rises. Thus, drain-source current does not flow to a selected flash memory cell. The programmed state of the flash memory cell is called a logic "0". When the flash memory cell is erased, there are a small number of residual electrons on the floating gate or lots of source-drain current flows to the flash memory cell. The erased state of the flash memory cell is called a logic "1".
A typical NOR flash memory device is now described below with reference to FIG. 1.
Referring to FIG. 1, a NOR flash memory device 100 includes an address buffer 110, a row predecoder 120, a row decoder 130, a cell array 140, a column predecoder 150, a column decoder 160, and a sense amplifier 170. In the cell array 140, flash memory cells (not shown) are arranged at intersections of wordlines WLi and bitlines BLi. The address buffer 110 receives an address signal ADDR from the outside so as to program or erase the flash memory cells and divides a row address RowAdd from a column address ColAdd by means of an output of the address buffer 110. The row predecoder 120 decodes the received row address RowAdd to generate a row selection signal RowSel. The row decoder 130 enables a predetermined wordline WLi in response to the row selection signal RowSel and drives the wordline WLi to a predetermined voltage level according to an operation mode of the flash memory device 100. In a program mode, the wordline WLi is driven to a voltage level of 10V. In an erase mode, it is driven to a voltage level of −10V. In a read mode, it is driven to a voltage level of 4.5V.
The column predecoder 150 decodes the received column address ColAdd to generate column selection signals ColSel1[m:0] and ColSel2[n:0]. The column decoder 160 selects a predetermined bitline BLi in response to the column selection signals ColSel1[m:0] and ColSel2[n:0] and connects a selected bitline BLi with the sense amplifier 170 through a data line DLi. For the convenience of description, 16 bitlines BLi (i=0–15) are exemplarily described. A first column selection signal ColSel1[m:0] selects four bitlines BLi and a second column selection signal ColSel2[n:0] selects one of the selected four bitlines BLi to connect the selected one bitline with the data line DLi.
The column predecoder 150 is now explained in detail with reference to FIG. 2.
Referring to FIG. 2, the column predecoder 150 inputs column addresses ColAdd[3:0] to selectively generate first column selection signals ColSel1[3:0] and second column selection signals ColSel2[3:0]. The first and second column addresses ColAdd[0] and ColAdd[1] are decoded through a decoding block 200 to drive level shifters 202, 204, 206, and 208. Each of the level shifters 202, 204, 206, and 208 is structured as shown in FIG. 3 and generates a high voltage HV of about 10V as its output OUT in response to a low-level input signal IN. Four transistors in the column decoder 160 corresponding to the first column selection signals ColSel1[0], ColSel1[1], ColSel1[2], and ColSel1[3], respectively, are turned on when a high voltage HV appears as the output OUT of the level shifter 202, 204, 206, or 208, respectively. The third and fourth column addresses ColAdd[2] and ColAdd[3] generate second column selection signals ColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3] of high voltage HV through a decoding block 210 and level shifters 212, 214, 216, and 218. The second column selection signals ColSel2[0], ColSel2[1], ColSel2[2], and ColSel2[3] of high voltage HV select one of the four bitlines (BLi of FIG. 1). Each bitline BLi is coupled to one of the four transistors that are turned by an activated first column selection signal ColSel1[0], ColSel1[1], ColSel1[2], or ColSel1[3]. In this way the selected signal is connected with a data line DLi.
When the flash memory device (100 of FIG. 1) is in the program mode, a voltage of 5V˜0V is applied to a bitline of a memory cell selected according to a programming type and a voltage of 0V is applied to a bitline of an unselected memory cell. The state of the bias of a transistor MF in a first group of transistors 161 coupled to the bitline of the unselected memory cell is now described below with reference to FIG. 4A. A high voltage of about 10V is applied to a gate by a first column selection signal ColSel1[0] that is coupled to the gate. A voltage of 0V is applied to a source by a bitline BL0 that is coupled to the gate. Thus, a voltage of 10V is applied between the gate and the source of the transistor MF, and a voltage of 0V is applied to the data line DL0 of FIG. 1 that is coupled to the unselected memory cell. The state of the bias of a transistor MS in a second group of transistors 162 (FIG. 1) is now described below with reference to FIG. 4B. A high voltage of about 10V is applied to a gate by a second column selection signal ColSel2[0] that is coupled to the gate, and a voltage of 0V is applied to a drain by the data line DL0 that is coupled to the drain. This state is maintained until the program is completed, which leads to increased gate oxide stress of the transistors MF and MS.
Furthermore, when the flash memory device (100 of FIG. 1) is in an erase mode, a voltage of about 9V is applied to a bulk that is coupled to a bitline. In this case, the first and second column selection signals ColSel1[m:0] and ColSel2[n:2] have a voltage of about 0V. Accordingly, a voltage of 0V is applied to the gates of the first group of the transistors 161 and a coupling voltage of 9V is applied to the sources thereof. As a result, gate oxide stress in the first group of transistors 161 occurs.
Over time, oxide stress from repeated program and erase operations degrades the gate oxide layer to cause errors in a transistor. This contributes to faulty operation of a flash memory device. Accordingly, there is a need for a method of detecting a transistor error caused by the degradation of the gate oxide layer.
Since the first and second column selection signals ColSel1[m:0] and ColSel2[n:2] alternately apply a high voltage, it takes a long time to screen the transistor error by applying a stress to the first and second groups of the transistors in the column decoder (160 of FIG. 1).
Embodiments of the invention address these and other disadvantages of the prior art.

Flash memory device having column predecoder capable of selecting all column selection transistors and stress test method thereof


A method applied to an optical disc drive for calculating an error detection code corresponding to a data sector is disclosed. The data sector includes a plurality of bytes arranged in a matrix having N lines along a first direction and M lines along a second direction perpendicular to the first direction. The method includes: along the first direction, calculating error detection codes corresponding to M bytes located at each of the N lines, wherein for each of the N lines, only bytes having error bits affect an error detection code for the line; adjusting an error detection code of each of the N lines according to a displacement between each of the N lines and a last line of the N lines; and then determining the error detection code of the data sector by summing up the displacement-adjusted error detection code of each of the N lines.

1. Field of the Invention
The invention relates to a method for calculating an error detection code (EDC), and more particularly, to a method for calculating an error detection code, where the method can simplify related circuits and utilize pipeline calculation.
2. Description of the Prior Art
In a process of encoding and decoding digital data and a process of reading and writing digital data, the digital data are often arranged in a two-dimensional matrix. Additional digital code data are added into the two-dimensional matrix in order to check the accuracy of the digital data stored inside the two-dimensional matrix. In addition, as the amount of digital data increases, the two-dimensional matrix is often formed by a plurality of data blocks each having a plurality of data sectors, which have a predetermined format. Please refer to FIG. 1, which is a diagram of a conventional two-dimensional matrix. As shown in FIG. 1, the entire two-dimensional matrix can be divided into several data sectors, where each data sector can be further divided into multiple rows CW1-CW208 and multiple columns CW′1-CW′182. In the multiple bytes of each row, the partial bytes arranged in the front of the row have more bytes and correspond to the digital data. On the other hand, the partial bytes arranged in the back of the row have fewer bytes and correspond to a first error correction code (i.e., the parity of inner, PI), utilized for correcting the digital data in the same row. Similarly, in the multiple bytes of each column, the partial bytes arranged in the front of the column have more bytes and correspond to the digital data. On the other hand, the partial bytes arranged in the back of the row have fewer bytes and correspond to a second error correction code (i.e., the parity of outer, PO), utilized for correcting the digital data in the same column. Furthermore, each data sector further comprises cyclic redundancy check (CRC) bytes. For example, as shown in FIG. 1, the encoding units 2171-2174 in the data sector (1) correspond to the above-mentioned CRC bytes. That is, when the data are written into a disc, the CRC bytes are added to each data sector.
According to the two-dimensional matrix format and the algorithms (e.g.: Reed-Solomon algorithm, Galois Field algorithm, Euclidean algorithm, and Berlekamp-Massey algorithm) of the error detection code and error correction code, if the two-dimensional data, which are written into the memory, have no errors in each byte (for example, the data are correctly written into the memory without noise interference of the circuit or without an operational error of the pickup head), the first error correction code (i.e., PI) and the digital data in each row have a one-to-one corresponding relationship and the second error correction code (i.e., PO) and the digital data in each column have a one-to-one corresponding relationship. Furthermore, the accumulation of effects of all bytes on the error detection code of the entire data sector is theoretically equal to the error detection code of the data sector (because there are no error bytes in the data sector).
Therefore, in the practical application, the first error correction code of each row and the second error correction code of each column are first utilized to find out bytes having error bits (especially to find out the bytes having error bits that cannot be corrected using these error correction codes). Then, the effects of the aforementioned bytes, which have error bits, on the error detection code of each data sector are processed, where the calculation result and the error detection code (corresponding to the above CRC code) located in the last few bytes of the non-error-correction-code part in the data sector are utilized to verify the result of utilizing the error correction codes to correct error bits in the digital data. Therefore, through repeatedly utilizing the error correction codes and the error detection code to process the digital data in the two-dimensional matrix, the error rate can be reduced to 10−12 or even less than 10−12.
In today's technology, when the effects of all error bytes of a certain data sector on the error detection code of the data section are being calculated, the digital data of each row/column are often processed by a row-by-row in sequence/column-by-column in sequence method. As shown in FIG. 2, the row-by-row in sequence method starts from the first byte of the first row, and then sequentially proceeds to all bytes of the first row. Then the first byte of the second row is processed, and all bytes of the second row are sequentially processed. Until all the bytes of the last row are processed, the effects of all error bytes on the error detection code of the data sector cannot be obtained.
The column-by-column in sequence method as shown in FIG. 3, is illustrated as follows. First, the first byte of the first column is processed. Then, all bytes of the first column are sequentially processed. Then the first byte of the second column is processed, and all bytes of the second column are sequentially processed. Until all the bytes of the last column are processed, the effects of all error bytes on the error detection code of the data section cannot be obtained.
In other words, when an error byte is discovered, the prior art method of calculating the effect of the error value of the error byte upon the error detection code is illustrated as follows. First, the prior art method shifts the error value from its original location at the Kth row (Kth column) to the last byte along the Kth row (Kth column). The displacements from the error byte through the last byte of the Kth row (Kth column) are determined, and the effects of the displacements upon the error value are calculated. Next, the method further shifts the adjusted error value to the first byte of Kth+1 row (Kth+1 column), the displacement between the first byte of the Kth+1 row (Kth+1 column) and the last byte of the Kth row (Kth+1 column) is determined, and the effect of the displacement upon the error value is calculated. Finally, the method shifts the adjusted error value from the first byte through the last byte of the Kth+1 row (Kth+1 column), the displacements from the first byte through the last byte of the Kth+1 row (Kth+1 column) are determined, and the effects of the displacements upon the error value are calculated. In this way, the prior art method shifts the error value to a last byte of a current row (column), then shifts it to a first byte of a next row (column), and then shifts it to a last byte of the next row (column), and so on, until the method shifts the found error value to the last byte of the last row (column) such that the above-mentioned error detection code is completely calculated.
Please note that the concept of utilizing the error correction codes and the error detection code in the digital data processing procedure (for example, the above-mentioned encoding operation and decoding operation) is only illustrated in short, and further detailed illustration is omitted here for brevity. More related information can be obtained from U.S. Pat. Nos. 4,760,576, 4,979,174, 5,689,727, 5,793,724, 5,948,117, 5,996,105, 6,024,286, 6,044,484, 6,075,920, 6,260,169, 6,367,049, 6,564,362, 6,574,776, 6,615,387, and 6,742,157.
However, because electronic products are increasingly more light, thin, short, and small, it is a key point to reduce their cost and raise their efficiency. Therefore, a smart solution capable of utilizing the above-mentioned error correction codes and error detection code more efficiently and cheaply is required. For example, a solution of calculating the effects of the error bytes upon the error detection codes is always a field requiring attention and further rese h.
It is therefore one of the primary objectives of the claimed invention to provide a method of calculating the error detection code, and more particularly, to provide a method of calculating the error detection code through utilizing fewer memory space and utilizing fewer calculation processes, to solve the above-mentioned problem.
According to an exemplary embodiment of the claimed invention, a method applied to an optical disc drive for calculating an error detection code corresponding to a data sector is disclosed. The data sector comprises a plurality of bytes, where the plurality of bytes is arranged in a matrix, and the matrix has N lines along a first direction and M lines along a second direction orthogonal to the first direction. The method comprises: (a) along the first direction, calculating error detection codes corresponding to M bytes located at each of the N lines, wherein for each of the N lines, only bytes having at least one error bit have a non-zero effect on an error detection code corresponding to the line; and (b) adjusting an error detection code of each of the N lines according to a displacement between each of the N lines and a last line of the N lines, and then determining the error detection code of the data sector by summing up the displacement-adjusted error detection code of each of the N lines.
In addition, in other embodiments of the claimed invention, above exemplary embodiment is modified to introduce the pipeline calculation. Through adjusting the operations executed by different pipelines or modifying the connection relation between different pipelines, multiple operations are allowed to be executed in the same time period to thereby reduce the computation time or memory space required for buffering computational data.
Some objectives and advantages of the present invention can be summarized as follows.
(1) When the effects of the error value of each error byte upon the error detection code in the two-dimensional matrix (e.g.: a data sector) are being calculated, the displacement between each error byte and the position storing the error detection code of the two-dimensional matrix is calculated. Please note that the displacement between the error byte and the last byte of the row (column), which comprises the error byte, is directly calculated, and then the displacement between the last byte of the row having the error byte and the byte for storing the error detection code is directly calculated. Here, in general, the error detection code is stored in the end of the data sector utilized for storing digital data. Therefore, the calculation of the effects of the error bytes upon the error detection code is performed along the row (column) from the error byte through the end of the row (column). Please note, however, that the calculation can also be performed according to the position storing the error detection code. That is, the calculation can shift along the row (column) having the error byte to a specific byte, which is located in the same row (column) where the error value is directly shifted to the specific byte using the above-mentioned displacement adjustment. Then, the calculation further shifts along the rows (columns) to the byte storing the error detection code according to the above-mentioned displacement adjustment. Finally, a summation operation is performed such that the wanted error detection code can be calculated.
(2) A pipeline calculation can be utilized to allow the error value of a certain error byte and the error value of a next error byte to be calculated at the same time such that the needed operation time can be reduced.
(3) A pipeline calculation can be utilized to allow the operation of calculating the error value of a current error byte, an operation of looking for a next error byte, and a displacement applied to an obtained error value to be performed at the same time such that the needed operation time can be reduced.
(4) Pipeline calculations can be utilized. When a pipeline calculation finds out the error value of an error byte, another pipeline calculation can be immediately utilized to calculate the displacement applied to the error value of the error byte without waiting for the displacement of the previously obtained error value to be completely calculated. This can reduce needed operation time.
(5) The relative distance between error bytes does not have to be utilized. Instead, the absolute distance between each byte and the end of the row (column) can be utilized such that the calculation can be simplified and the circuit for performing the calculation can be simplified also.
In the following disclosure, the present invention's spirit, embodiments, objects, and advantages will be disclosed. First, in the prior art, the calculation of the error detection code has a common characteristic. That is, the effect of the error value of a certain error byte upon the entire data sector is only related to the displacement between the certain byte and the byte storing the error detection code, but is not related to which path is selected from the certain byte to the byte of the error detection code. Here, each path from the certain byte to the byte of the error detection code corresponds to a kind of hardware/firmware/software for achieving the displacements corresponding to the path. Because it is impossible to predict which bytes in each data sector have errors, each byte used for storing data needs a dedicated displacement to move to the byte storing the error detection code. In the practical implementation, in order to simplify the circuit hitecture and reduce the cost, all possible displacements are divided into several basic procedures according to the order of processing each byte in the data sector. That is, the circuit is correspondingly divided into several basic hardware/firmware/software parts. Therefore, if the number of needed basic procedures is smaller, the needed basic hardware/firmware/software parts become fewer such that the circuit hitecture is simpler and the cost is reduced.
In addition, the inventor of the present invention further discloses that the prior art flow of generating the error detection code can be divided into three steps: (i) Finding out error bytes (the byte having error bits) in the encoded data (data sector). (ii) Calculating the error detection code of each error byte. (iii) Calculating the error detection code generated by combining all error detection codes of all error bytes. Please note that all bytes have to be checked and the error detection codes are calculated according to a predetermined rule. The above-mentioned steps (i) and (ii) take a fixed time. In other words, only the step (iii) can be changed and simplified by changing the procedure of processing all bytes such that the time and circuit for the step (iii) can be reduced and simplified.
According to the above-mentioned thoughts, the inventor of the present invention points out that the method of row-by-row in sequence or the method of column-by-column in sequence according to the prior art needs at least three basic displacement operations. (a) Along a certain row or a certain column, move from a certain byte to a next byte. (b) From the last byte of a certain row (column) to the last byte of a next adjacent row (next adjacent column). (c) From the last byte of a certain row (column) to the first byte of the certain row (column). Obviously, the basic displacement operation (c) is performed due to the prior art in sequence method. However, the inventor of the present invention emphasizes that since the calculation of the error detection code is not related to the path, if an error byte is discovered and needs to be corrected, a shortest path (or the least calculations), for moving the error value of the error byte to the position of the byte storing the error detection code of a data sector, is the most efficient path. At the same time, because the procedure of finding out the error bytes needs to move between different bytes, if the paths in steps (1) and (3) can be integrated together (please note that the step (2) is not related to the path), the entire operation can be more efficient and the cost will be reduced.
Therefore, the inventor of the present invention discloses a method applied to an optical disc drive for calculating the error detection code corresponding to a data sector. The data sector comprises a plurality of bytes arranged in an N*M matrix. The key characteristic of the method is: only in each row (column) are the bytes processed in sequence or the bytes are processed individually. Appropriate displacement adjustment and adding operations are utilized to sum up the error detection codes (i.e., error values) caused by all error bytes. (Please note, for the Galois Field arithmetic, the adding operation is the XOR operation). After each row or each column is completely processed (that is, the last byte of the row or the column is processed), however, the displacement adjustment is performed to directly move the error detection code of each row/column to the end of the last row/column, which is utilized to store the error detection code of the data sector; or to directly move the error detection code of each row/column to the end of the next row/column, which is utilized to store the error detection code of the next row/column. In other words, the calculation of the error detection code of the data sector is for directly performing the displacement adjustment on the error detection code of a processed row/column to move across unprocessed rows/columns to the end of the data sector, which is utilized to store the error detection code. This is in contrast to the prior art, which needs to sequentially process all bytes located at unprocessed rows/columns.
Please refer to FIG. 4 and FIG. 5 in conjunction with FIG. 2 and FIG. 3. FIG. 4 and FIG. 5 are flow charts illustrating calculation of the error detection code according to the present invention. It can be seen that the present invention has at least the following advantages:
(1) In each row/column, each byte is processed in sequence. This can be combined with the above-mentioned step (i).
(2) The present invention only needs to (a) move along a certain row/column direction to a next byte and (b) move to the last byte of a next adjacent row/column from the last byte of a certain row/column. In contrast to the prior art, the present invention can save a basic displacement operation and related hardware/firmware/software part.
(3) Because the processing upon a certain row/column is not related to any other rows/columns, the present invention, in contrast to the prior art, is not limited to start the processing of a next row/column after completing the processing of a certain row/column. Therefore, the present invention can respectively (even simultaneously) process different rows/columns such that the total time of the entire operation can be reduced.
(4) Because each column can be processed respectively, the error detection code process can be performed on each column just after one row is completely read. This is in contrast to the prior art, which needs to read all rows and then perform the error detection code process. This allows the present invention to combine the process of reading data sector and the process of processing each column to obtain the second error correction code and the error detection code. In the prior art, the process of reading the data sector can be only combined with the process of processing each row but cannot be combined with the process of processing each column.
(5) Because the effects caused by the error bytes upon the error detection code can be dividedly processed, when only a few bytes are adjusted in the data sector, the error detection code can be recalculated in response to the adjusted bytes only. Furthermore, the effects caused by the error bytes upon the error detection code can be selectively reconfirmed when the error detection code needs to be validated such that possible error sources can be determined.
In addition, the inventor of the present invention also discloses a method applied to an optical disc drive for calculating an error detection code corresponding to a data sector. The data sector comprises a plurality of bytes arranged in an N*M matrix. The method comprises at least the following steps: processing each row of the N*M matrix (and processing all bytes of each row); when the Kth column is being processed, if a byte is discovered to have error bits, the error detection code corresponding to the error byte can be first calculated in order to adjust the error byte and then the displacement between the error byte between a predetermined byte of the Kth row (often the last byte of the Kth row) is utilized to adjust the error detection code to update the error correction code corresponding to the predetermined byte of the Kth row. After the Kth row is processed and the next Kth+1 row needs to be processed, the error detection code is adjusted again according to the displacement between the Kth row and the Kth+1 row. In addition, after all rows and all bytes of each row are processed, the adjusted error detection codes, corresponding to all error bytes and adjusted through the displacement adjustment, are summed up to obtain the error detection code corresponding to the processed data sector. Then, the error detection code and a certain value can be utilized to determine whether the content of the processed data sector is correct. Similarly, the method can be changed to process each column (and all bytes of each column) of the N*M matrix. Furthermore, instead of sequentially processing each row/column, the present invention can follow the data reading procedure to simultaneously process a plurality of rows/columns.
Moreover, if the procedure of reading the data section does not have to be combined with the procedure of generating error detection codes, the present invention can also be changed as follows: when the error detection code of a certain byte is discovered, the number of basic displacements between the certain byte to the byte storing the error detection code along the row (or column) direction and the number of basic displacements between two adjacent columns (rows) along the row direction (column direction) can be directly determined. Then, the error detection codes are directly adjusted according to these above-mentioned displacements. Finally, these error detection codes are directly summed up to obtain the error detection code of the data sector.
According to the above disclosure, the present invention provides a method of obtaining a first error correction code, a second error correction code, and the error detection code such that the calculation of each row and each column can be combined with the procedure of reading the data sector. This also reduces the cost and raises the efficiency. Here, it is emphasized that the present invention can be utilized in cooperation with the prior art. For example, the calculation of each row can be in accordance with the prior art method, but the calculation of each column is in accordance with the present invention operation.
In addition, in the procedure of processing each row or each column, the present invention can have the following modifications. That is, after an error byte is discovered in a certain row/column, the error detection code of the error byte is first calculated and then the obtained error detection code is adjusted according to the displacement between the error byte to the end (the last byte) of the certain row/column.
Moreover, in the procedure of processing multiple rows or multiple columns, the present invention can have the following modifications. That is, after the summing operation of error detection codes of a certain row/column is completely performed, the displacements of the error detection code of the certain row/column are first applied to move the error detection code to the place storing the error detection code of the data sector. Then, after all rows or all columns complete the summing operation and displacement adjustment of the error detection codes, these error correction codes generated from all rows/columns are summed up to obtain a final error detection code for the data sector.
In addition, after the summing operation of error detection codes of a certain row/column is completely performed, the error detection code of the certain row/column is moved to the end of a next row/column through a displacement adjustment. After the error detection code of the next row/column is calculated, the error detection codes of the two rows/columns are summed up. Then the summed error detection code is moved to another next row/column through the displacement adjustment. The above-mentioned operation is repeatedly performed until the error detection code of a last row/column is summed up such that a final error detection of the data sector can be obtained. Please refer to embodiments shown in FIG. 6 and FIG. 7 and compare the embodiments shown in FIG. 6 and FIG. 7 with those shown in FIG. 3 and FIG. 4. The embodiments shown in FIGS. 3-7 all belong to the scope of the present invention.
Utilizing the same concept, in the procedure of processing each row/column, the present invention can have following modifications (not shown in Figures). For example, after the error detection code of a certain byte in a certain row/column is completed, the error detection code is firstly moved to the end of the row/column having the certain byte through the displacement adjustment. Then, the row/column is se hed to find out other error bytes, and the error detection code calculation and displacement adjustment of calculated error detection code are performed. Finally, the results of all error bytes are summed up to obtain the error detection code of the row/column after the last byte of the row/column has been processed. Furthermore, after the error detection code of the first byte of a certain row/column, the error detection code can be moved to a next byte through the displacement adjustment and be summed up with the error detection code of the next found error byte. The above-mentioned operation is repeatedly performed until all bytes of the certain row/column are summed such that the error detection code of the certain row/column is obtained. This change also obeys the spirit of the present invention.
The difference between characteristics of the present invention and the prior art is: the displacement path used for calculating the error detection code in step (iii), which comes from the error detection codes of error bytes. Therefore, when each row/column is being processed, the present invention can adopt in sequence method as the prior art does.
For further illustration, please refer to FIG. 8. In FIG. 8, V1, V2, V3, V4 respectively represent four error values corresponding to four error bytes in a certain row/column. T represents the time period used for calculating the error value of any error byte. L1 represents the distance between the error byte to the start of the certain row/column. L2, L3, and L4 respectively represent the distances between two error bytes. L5 represents the distance between the last byte and the end of the certain row/column. T1 represents the time period for checking the bytes from the start to a first error byte. T2, T3, and T4 respectively represent the time period for checking all bytes between two adjacent error bytes. T5 represents the time period for checking the bytes from the last error byte to the end of the row/column. It is clear that the time period for checking the certain row/column (proportional to the consumption of the bandwidth) is T1+T+T2+T+T3+T+T4+T+T5=T1+T2+T3+T4+T5+4T. Please note that, for the purposes of simple illustration, the lengths of L1, L2, L3, and L4 shown in FIG. 8 are all equal to each other. However, in the practical implementation, the appearance of error bits is not predictable. Therefore, the error bytes are randomly distributed. That is, the lengths of L1, L2, L3, and L4 are not guaranteed to be the same. Similarly, in the following embodiments, the position of error byte, the distances, and the time periods are only utilized as examples, not limitations of the present invention.
However, with the progress of technology, the processing rate of hardware/firmware/software is getting faster and faster. Some applications, such as pipeline calculation, capable of raising data processing rates are utilized in current systems. Therefore, the above-mentioned time period T1+T2+T3+T4+T5 can be further reduced. For example, if the hardware/firmware/software is advanced and has faster processing rate, the time period for calculating each error value will be short enough. That is, in FIG. 8, T is less than or equal to the minimum of T2, T3, and T4. In this way, after the required data are ready, the present invention method can simultaneously perform the error value calculation of a certain error byte and the se hing operation of a next error byte. At this time, the process shown in FIG. 8 can be changed into the process shown in FIG. 9. In addition, the time period for checking the row/column (proportional to the consumption of the bandwidth) is T1+T2+T3+T4+T. If a distance between two error bytes is too short (for example, Nth error byte and Nth+1 error byte), this makes the time period for se hing the Nth+1 error byte be shorter than the time period for calculating the error value of the Nth error byte. At this time, after the calculation of the error value of the Nth error byte is performed, the operation of se hing the Nth+2 error byte and the operation of calculating the error value of the Nth+1 error byte can be simultaneously performed. Moreover, the present invention can perform the operation of calculating the error values of Nth error byte and Nth+1 error byte, and simultaneously perform the operation of se hing the Nth+2 error byte. Obviously, in the embodiment shown in FIG. 9, the time for calculating the error values can be ignored under an ideal condition.
Furthermore, the process shown in FIG. 8 can further use the pipeline calculation mechanism to simplify the entire process. Please refer to FIG. 10. This embodiment respectively utilizes a first procedure (i.e., a Chien Se h procedure), a second procedure (i.e., a Founey procedure), and a third procedure (i.e., an EDC procedure) to know the locations of the error bytes, to know the error values of error bytes having error bits, and to perform the calculation of error detection codes (the above-mentioned displacement adjustment of error detection codes and summing operation). Here, from the time T0, the Chien Se h procedure se hes the position L1 of the error byte. If the time of se hing the first error byte is T1, from T1, not only does the Chien se h procedure still find the position L2 of a next error byte, but also the Founey procedure calculates the error value V1 of the first error byte. On the other hand, if the time of se hing the second error byte is T2, from T2, not only does the Chien se h procedure still find the position L3 of a next error byte and the Founey procedure calculate the error value V2 of the second error byte, but the EDC procedure starts to calculate the effect EDC(1) (that is, to calculate the displacement adjustment of the error detection code) caused by the first error byte (corresponding to the error value V1) upon the error detection code. If the time of se hing the third error byte is T3, from T3, not only does the Chien se h procedure still find the position of a next error byte and the Founey procedure calculate the error value V3 of the third error byte, but the EDC procedure starts to calculate the effect EDC(2) (that is, to calculate the displacement adjustments of the error detection codes and then to sum them up) caused by the first error byte and the second error byte upon the error detection code. The above-mentioned operations are continued until all bytes are processed. Obviously, in contrast to the process shown in FIG. 8, the pipeline calculation process shown in FIG. 10 is more efficient. Because some operations can be performed synchronously, the present invention does not have to use the in-sequence procedure (i.e. perform a next operation until a current operation is completed). The present invention can still perform a part of pipeline calculation processes asynchronously if necessary, for example if the hardware performance is not good enough to process all operations in time.
However, if the process shown in FIG. 10 is utilized in firstly determining the positions and error detection codes of all error bytes of each row/column and then processing effects caused by error bytes upon the error detection codes, instead of directly processing the effect caused by one error byte upon the error detection code and then processing the effect caused by a next error byte upon the error detection code, some disadvantages might be introduced. For example, the Chien se h procedure detects the positions L1 (111−11n) of a plurality of error bytes of a certain row/column in a period of time (for example, from T0 to T1). The Founey procedure obtains the error values V1 (v11−v1n) of the error bytes in another period of time (for example, from T1 to T2). The EDC procedure can then calculate the effects EDC(e11−e1n) caused by the error bytes upon the error detection code in another period of time (for example, from T2 to T3). Therefore, before the time period from T2 to T3 (before the EDC procedure), the error values obtained from T1 to T2 and the positions of all error bytes obtained from T1 to T2 should be recorded completely. Therefore, a big memory space is required, the required storage time is long, the data amount of transmission in different procedures is large, and the number of computing and processing steps is larger. This reduces performance of the system and increases the production cost.
In response to the above-mentioned problem, the present invention further discloses another pipeline calculation method (as shown in FIG. 11). Succinctly, the Founey procedure and the EDC procedure are almost performed synchronously. If the Founey procedure obtains the error value of a certain error byte of a certain row/column (for example, v11 shown in FIG. 11), the EDC procedure immediately calculates the effect (for example, e11 shown in FIG. 11) caused by the error byte upon the error detection code (please note, at this time, the position 111 and the error value v11 have been obtained). After the effect is determined, the position (111) and error value (v11) are immediately deleted from the memory such that only the effect upon the error detection code is left. In this way, the above-mentioned operation is continuously performed until all error values obtained by the Founey procedure are utilized in the EDC procedure. Obviously, in this way, the operation of se hing the positions of error bytes and the operation of calculating the error values of the error bytes can be divided into two different processes (i.e., the Chien Se h procedure and the Founey procedure). This can raise the flexibility in actual applications. On the other hand, this can make the operation of calculating the error values and the operation of calculating the error detection code (i.e., the Founey procedure and the EDC procedure) able to be performed almost synchronously such that the processing time is reduced. In addition, with the execution of the EDC procedure, after an error byte is encoded the position and error value of the error byte is not stored inside the memory. This can help to reduce the demands of memory space, storage time, and data amount of transmission. Clearly, the change shown in FIG. 11 can meet the demands.
Furthermore, the implementation of the EDC procedure (as shown in FIG. 12) can utilize the in-sequence method because the prior art commonly processes rows/columns in-sequence. That is, when each row/column is processed, each time an error byte is processed, the corresponding displacement adjustment is performed on the error detection code according to the error value of the error byte. When a next error byte is processed, the error value is summed up with the error detection code processed by displacement adjustment, and then the displacement adjustment is applied to the summed error detection code. The above-mentioned operation is continuously performed until all bytes are completely processed and the error detection code is shifted to the end of the row/column using displacement adjustment. When the positions of error bytes are received, the displacement between the error bytes and the start of the row/column is received practically. At this time, although the length of each row/column is fixed (known), we can easily transform the displacement between the error bytes and the start of the row/column into the absolute displacement between the error bytes and the end of the row/column. However, because the prior art error detection code calculation utilizes the relative displacement between the error bytes and between the error bytes and the end of the row/column, the effects upon the error detection code EDC caused by error bytes having error bits can be simply illustrated by the following equation that computes the error detection code EDC using displacement conversion.EDC=ΔL3{ΔL2[(ΔL1V1)+V2]+V3}=L3{(L2−L3)[(L1L2)V1+V2]V3}
where L1, L2 and L3 represent the displacements between error bytes and the end of the row/column, and V1, V2 and V3 represent the error values of the error bytes.
Obviously, multiple calculation steps (two subtraction operations, one adding operation, and three multiplying operations) and three hardware devices (adder, subtractor, and multiplier) are needed. This raises the total cost and affecting the computation performance.
For the above-mentioned problem, the present invention further discloses another implementation of the EDC procedure. As shown in FIG. 13, at this time, the in-sequence method is no longer utilized. Instead, because the error detection code is only related to the displacement of the error value but not related to the displacement path, the present invention can utilize the above-mentioned characteristic. In other words, this embodiment directly moves the error value from the error byte to the end of a certain row/column and then calculates the effects upon the error detection code. That is, at this time, the effects upon the error detection code EDC caused by error bytes can be calculated by the following equation.EDC=L3V3+L2V2+L1V1
Obviously, the number of calculation steps is reduced, as only three multiplying operations and two adding operations, and only two hardware devices (adder and multiplier) are needed. In contrast to the process shown in FIG. 12, the process shown in FIG. 13 can further reduce the hardware cost and needed computation time.
A data block is divided into multiple data sectors, and each divided data sector has its corresponding error detection code. When the error detection code is being calculated, the data sector should be regarded as a unit to be processed. In other words, if the displacement between two error bytes goes across the boundary of two adjacent data sectors, the displacement should be divided to multiple displacements to process the effects upon the error detection code in different data sectors.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Method for calculating an error detecting code