An integrated circuit fabrication process is provided in which an interconnect having a least one vertical sidewall surface is formed. The interconnect thusly formed allows for higher packing density within the ensuring integrated circuit since the interconnect requires less space to accommodate the same current density as an interconnect having sloped (i.e., non-vertical) sidewall surfaces. A semiconductor topography is provided which includes transistors arranged upon and within a silicon-based substrate. A first interlevel dielectric is deposited across the semiconductor topography, and portions of the dielectric are removed to form vias to select portions of the transistors. Conductive plugs are formed exclusively within the vias. An insulating material patterned with vertical sidewall surfaces is then formed across the first interlevel dielectric and a portion of the plugs. The insulating material is then patterned. Conductive material is then deposited across the patterned insulating material, the plug upper surfaces, and the first interlevel dielectric. A portion of the conductive material is anisotropically removed to form interconnects which are laterally adjacent to the sidewall surfaces of the insulating material. Each interconnect includes two surfaces, one of which is vertical to the underlying topography and the other of which extends a distance from the fist surface and links with an upper region of the surface in an arcuate pattern. The first lateral surface of the interconnect is directly adjacent to a sidewall surface of the insulating material and is therefore intended to be vertical. The second lateral surface extends a distance from the first lateral surface, constrained the limitations of deposition and not lithography.

1. Field of the Invention
This invention relates to integrated circuit fabrication and more particularly to a high density metallization technique employing an interconnect formed laterally adjacent a patterned structure, wherein the resulting interconnect has a vertical sidewall surface.
2. Description of the Relevant Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been deposited within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed on the semiconductor topography and connected to contact areas thereon to form an integrated circuit. The entire process of making an ohmic contact to the contact areas and routing interconnect material between ohmic contacts is described generally as "metallization". While materials other than metals are often used, the term metallization is generic in its application. It is derived from the origins of interconnect technology, where metals were the first conductors used. As the complexity of integrated circuits has increased, the complexity of the metallization structure has also increased.
In general, the formation of interconnect routing between ohmic contacts first involves depositing a conductive material across the surface of a semiconductor topography embodying ohmic contact areas. Interconnects may need to extend relatively long distances across an integrated circuit to reach contacts. Therefore, it is popular to use a conductive material which exhibits low resistivity, such as aluminum or aluminum alloy. A photolithographic pattern consisting partially of stripes is formed upon the conductive material. An optical image and a photosensitive film are used to produce the interconnect pattern. The photosensitive film (i.e., photoresist) has two main properties: when exposed to appropriate radiation, resist solubility is altered, allowing certain areas to be easily washed away by a solvent; and when exposed to an etchant capable of removing the conductive material, it resists attack. Thus, to complete the formation of interconnect, areas of the conductive material not covered by photoresist are etched away using an etchant that exclusively attacks those areas.
A problem with the above-mentioned method for the formation of interconnect is that etching results in interconnects having sloped sidewall surfaces. Sloped sidewall surfaces particularly result when using isotropic etching which occurs laterally and obliquely at a relatively uniform rate in all directions. Thus, anisotropic etching has become popular in integrated circuit manufacturing because it allows the downward etch rate to be much larger than the lateral etch rate, resulting in less sloping of interconnect sidewall surfaces. However, even with the advent of anisotropic etch technology, sidewall surfaces of interconnect still exhibit an undesired amount of sloping (i.e., is not substantially vertical to the underlying topography surface).
Turning to FIG. 1a, a cross-sectional view of interconnect 10 is shown patterned upon a relatively planar topography 14. Patterned interconnect 10 results from conventional etchant as having such a sloped sidewall surface 16. A patterned photoresist layer 12 is shown lying directly above interconnect 10 being formed. Unfortunately, during etching, the top portion of interconnect 10 under photoresist layer 12 is oftentimes removed somewhat. Removal at the upper portion occurs at a faster rate than the bottom portion, most likely due to the isotropic component of conventional etchants. The result of such etching is that the base of interconnect 10 is be wider than its upper surface. This result is sometimes referred to as "undercutting". A detailed view of sidewall surface 16 is illustrated in FIG. 1b. The resulting sidewall surface 16 is shown non-perpendicular to the horizontal topography 14 upon which interconnect line 10 is disposed. Therefore, an angle 20 between sidewall surface 16 and surface 14 is less than ninety degrees. Dashed line 18 represents an ideal sidewall surface as being vertical.
Current density is dependent on the actual cross-sectional area of an interconnect line. The cross-sectional area of an interconnect must be large enough to accommodate a pre-determined current density. Thus, since conventional interconnect are wider at the bottom than at the top (e.g. interconnect 10 of FIG. 1a), the interconnect requires more space than it would if it had vertical sidewall surfaces. The packing density of an integrated circuit is therefore sacrificed by the sloped sidewall surfaces of interconnects. The amount of interconnect routing across a single horizontal level of an integrated circuit could be increased by the development of interconnect having vertical sidewall surfaces or, at the very least, more controlled placement of sidewall surfaces relative to one another. Packing density limitations further limit operation speed and circuit complexity. It is therefore desirable that a semiconductor fabrication process be developed for the formation of interconnect which allows higher density layout of advanced ULSI integrated circuits.

Semiconductor fabrication employing a spacer metallization technique


A computer controllable testing and monitoring station forms short-term intervals of simulated alternating current power level disturbance, either undervoltage (sag) or overvoltage (swell). The station forms the short term voltage sags or swells so that their effects on sensitive equipment can be measured. The starting point of the sag or swell disturbance, as well as the time duration of the disturbance, can be accurately controlled.

1. Field of Invention:
The present invention relates to testing and monitoring stations for alternating current power level disturbances.
2. Description of Prior Art:
There has in recent years been a significant growth in the use of electrical equipment of types which are generally termed sensitive loads. An item of electrical equipment considered as a sensitive load is one which would have its performance affected by power disturbances. The most common disturbances encountered have been variations in the level of alternating current power the load received as a source of energy. A common example of a sensitive load is a digital computer, although there are a wide variety of other types known. It has become a common practice to use power line conditioners to afford some measure of protection to sensitive loads.
It is known that at times there occur in power distribution networks disturbances in the level of alternating current power. They are frequently referred to as voltage sags when the alternating current power line voltage drops below its rated or specified level. Conversely, disturbances where the line voltage exceeds its rated or specified level have been referred to as voltage swells.
It has become important to measure and determine the sensitivity of power system loads, as well as the capabilities of their associated power line conditioners, in the presence of power line disturbances such as voltage sags and swells. So far as is known, presently available testers for power line disturbances have not been satisfactory because of lack of an ability to control the time at which the disturbance started, and the time when it stopped, with accuracy.

Board of Regents, The University of Texas System


A rotary valve actuator with movable actuator linkage maintained in a constant "pull-pull" tension, includes a sliding canister, rotatable lever, and a return spring substantially aligned in-line with each other. The linear motion of the canister in response to an expanding and contracting pressurized bladder is converted through chain linkage into rotary lever motion. The return spring is connected through respective chain linkage to the lever so the pulling tension of the spring/lever linkage rotates the lever and maintains tension on both chain linkages. Adjustable travel stops are provided. In an alternate embodiment the return spring chain linkage is configured at right angles to the linear movement of the canister.

A variety of fluid flow control valves and corresponding valve actuators are utilized for on/off control or throttling the flow of fluid, such as in a gas or oil pipeline system, or in other process fluid systems. The fluid flow control valves are typically sliding stem control valves or rotary action control valves and are operated by a valve actuator such as a pneumatic piston or diaphragm actuator responding to the output of a valve positioner or valve controller instrument for accurate throttling control of the valve.
In the case of rotary action control valves, these units typically employ a flow control member in the form of a rotatable ball, rotatable ball segment, or a rotatable butterfly element. The rotation of the flow control element opens and closes the valve gate or plug.
Valve actuators for controlling such rotary action control valves typically employ a movable diaphragm connected to a rod at the diaphragm center. Moving the diaphragm displaces the rod linearly and thus requires a linear to rotary action translation. A rotational link arm has one end fixed to the valve rotary shaft and the other link arm end is coupled to the diaphragm rod. Linear movement of the diaphragm rod moves the link arm and thereby actuates a rotational movement in the valve shaft which is ultimately connected to the rotatable flow control element in the fluid control valve.
Such presently available rotary valve actuators employ many components, several of which require time consuming and expensive machining during manufacture. A manufacturer and users of rotary valve actuators therefore must inventory a large number of parts, and also must inventory an increasing number of expensive, machined spare parts for repair and replacement.
It is desired therefore to reduce the number of parts as well as to reduce the number of time consuming and expensive machined parts in a rotary valve actuator so as to thereby reduce manufacturing costs and inventory requirements both for the manufacturer and the user. In addition, it is further desired to provide a rotary valve actuator of reduced size and weight, and one having the capability of actuating a variety of rotary valves to reduce the number of rotary valve actuators required.

Tension-spring return rotary valve actuator


A clock-supply control system has an AND circuit whereby, when a transfer halt signal and a processing completion signal output by a DSP as well as a transfer halt signal output by a data output unit are all activated, the supply of a clock signal to the DSP is cut off.

1. Field of the Invention
The present invention relates to a clock-supply control system of digital-signal processors.
2. Description of the Prior Art
FIG. 10 is a block diagram showing the configuration of a conventional digital-signal processing block. Reference numeral 1 shown in the figure is the digital-signal processing block and reference numeral 2 is a data input unit for inputting data 3. Reference numeral 4 is a digital-signal processor, referred to hereafter simply as a DSP, for inputting data 5 from the data input unit 2 and carrying out digital processing on the data 5 in synchronization with a clock signal 6. Reference numeral 7 is a data output unit for inputting data 8 from the DSP 4 and outputting data 9 to a circuit at the next stage. Reference numeral 10 is a frequency multiplier for multiplying the frequency of a system clock signal 11 in order to generate the clock signal 6 for driving the operation of the DSP 4.
Below is description of the operation of the digital-signal processing block.
A digital-signal processing technique using a DSP is known as a conventional method for carrying out digital-signal processing on audio or video data. Examples of such digital-signal processing are MPEG decoding and Dolby digital (AC3) decoding.
FIG. 10 is a diagram showing a digital-signal processing block having an embedded DSP 4 for carrying out such processing. Data 3 supplied to the data input unit 2 is transferred to the DSP 4 as data 5 with appropriate timing. The DSP 4 carries out digital processing on the data 5 in synchronization with the clock signal 6 in accordance with firmware embedded in the DSP 4. The DSP 4 then provides the data output unit 7 with data 8, which has completed the digital processing, with appropriate timing. The data output unit 7 then properly outputs the data 8 to a circuit at the next stage as data 9. It should be noted that the clock signal 6 for driving the operation of the DSP 4 is obtained by multiplying the frequency of the system clock 11 using the frequency multiplier 10.
The frequency of the clock signal 6 must be set at a value between a minimum frequency required for executing desired functions to carry out digital processing on the data 5 and a maximum frequency, above which the DSP 4 will most likely perform a malfunction.
In the case of a digital-signal processing block which is actually implemented by an LSI mounted on a board, the clock signal 6 supplied to the DSP 4 is normally generated from the system clock signal 11 of the board. In this way, oscillating elements can be eliminated and a non-synchronous frequency that can become a noise source can be avoided. It should be noted that the frequencies of the system clock signal used in an audio processing system are 256 fs and 384 fs where 1 fs is equal to 44.1 kHz.
In the case of a clock signal 6 generated from a board system clock 11 as described above, the clock signal 6 supplied to the DSP 4 may be obtained with a frequency which is higher than a minimum frequency required for the operation of the DSP 4 by an unnecessarily large difference. For example, assume that the minimum frequency required for the operation of the DSP 4 is 30 MHz and the system clock signal 11 has a frequency of 256 fs which is equal to 11.25 MHz. Let the frequency of the system clock signal be multiplied by 4 by means of the frequency multiplier 10 to generate a clock signal 6 to be supplied to the DSP 4 with a frequency of 4.times.11.25 MHz=45 MHz. In this case, the difference between the frequency of the clock signal 6 and the minimum frequency required for the operation of the DSP 4 is 45-30 =15 MHz. As a result, unnecessary operations may inadvertently take place even after the required digital processing has been completed early by the DSP 4 due to the clock signal 6 with an excessively high frequency.
The conventional digital-signal processing has a configuration described above wherein the clock signal 6 supplied to the DSP 4 is generated by merely multiplying the frequency of the system clock signal 11 using the frequency multiplier 10. Thus, the clock signal 6 may have a frequency which is higher than a minimum frequency required for the operation of the DSP 4 by an unnecessarily large difference. As a result, unnecessary operations may inadvertently take place even after the required digital processing has been completed early by the DSP 4 due to the clock signal 6 with an excessively high frequency, raising a problem that the amount of power consumed by the digital-signal processor increases unnecessarily.
It should be noted that the prior art is disclosed in, among other documents, JP-A No. 7-129272.

Clock-supply control system of digital-signal processors


A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined point in its cycle. The phase of the second clock is adjusted based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock. The pointer operating with the first clock is reset to achieve a desired value for the relationship. A skew created from adjusting the phase of the second clock is corrected.

When first-in-first-out buffers (FIFOs) are used to transfer data between two clock domains, the data is transferred from one domain to other by delaying the data unload until the load is completed and the data is settled. For reliability, this process should make sure that the load and unload addresses have enough separation or delay in time between them. If sufficient time separation is not given, it can cause a malfunction. However, if this process creates excessive delay, it deleteriously affects the latency through the interconnect. Also, in a multi-lane interconnect, inter-lane skew will add additional timing uncertainty to the entire link. Often, it is not possible to predict these delays since uncertainties depend on process, voltage and temperature on top of specific implementations of the physical layer components' clocking scheme that might include uninitialized, but free running clock dividers.
In order to ensure proper functionality, existing implementations use a programmable FIFO pointer separation scheme in which a suitable delay value is selected by characterizing the system across applicable operating conditions and integrated circuit manufacturing corners to find a delay setting that works across all conditions and corners. This fixed setting is then used for production. Some other solutions characterize individual system-on-chips (SoCs) and permanently fuse the setting on each SoC. The former solution is cumbersome and can lead to sub-optimal settings and deeper FIFOs, increasing the latency, while the latter solution often adds expense due to increased tester time and use of fuse bits.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word "coupled" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.


A method and system for discharging refrigerant, such as carbon dioxide, from an air conditioning system. The discharge rate of the refrigerant from the air conditioning system is controlled by a discharge rate controller, even as refrigerant pressure at the system input varies. By maintaining discharge rate at a controlled value, the discharge time of the refrigerant from the air conditioning system is reduced.

Recently, the refrigerant R744, i.e., carbon dioxide, has been employed in motor vehicle air conditioners instead of the conventional refrigerants R134a and R12. The use of carbon dioxide allows discharge of the refrigerant from the air conditioning system and venting to the atmosphere, unlike the conventional refrigerants. To protect system components from possible damage, it is usually recommended that the discharge rate be limited to some value. This value is typically expressed as a maximum pressure drop per minute such as 1 bar per minute.
Typically, discharge of carbon dioxide from an air conditioning system, such as used in an automobile, is accomplished by employing a fixed orifice that limits the flow rate of the discharging carbon dioxide. A block diagram of a conventional arrangement is depicted in FIG. 1, in which an air conditioning system 10 containing carbon dioxide to be discharged is connected to the fixed orifice 12. The carbon dioxide is discharged through the output 14 of the fixed orifice 12.
FIG. 2 shows an exemplary plot of the discharge rate (the Y-axis) vs. time (on the X-axis). It can be seen that the discharge rate decreases with time. The fixed orifice 12 prevents discharge rate from exceeding a safe maximum rate for the highest output pressure expected from the air conditioning system 10. However, one of the concerns for such a discharge arrangement is the relatively long time required to entirely discharge the air conditioning system 10. The long discharge time is a result of the refrigerant flow rate dropping due to reduced pressure differential across the fixed orifice 12. In other words, as carbon dioxide is discharged from the air conditioning system 10, output pressure from the air conditioning system 10 drops, causing input pressure at the fixed orifice 12 to drop and the pressure differential between the input of the fixed orifice 12 and the output of the fixed orifice 12 to be reduced. This reduces the discharge rate and increases the total discharge time, as depicted in FIG. 2. Even if the orifice were made adjustable to allow the discharge rate to be adjusted during a vehicle discharge, it would require an operator to be present to monitor and adjust the discharge rate.
There is a need for reducing the total discharge time for discharging carbon dioxide or other refrigerants from systems in a manner that still maintains integrity of the system and does not need to be tended to.

Arrangement and method for controlling the discharge of carbon dioxide for air conditioning systems


The present invention aims to manufacture a large size semiconductor device with the inter-substrate transcription technology of thin film circuits. Enlargement is enabled by disposing a plurality of second substrates (21) in a tile shape. As the second substrate (21), a print substrate or flexible print circuit having double-sided wiring or multilayer wiring is employed. The plurality of second substrates (21) is driven independently, and the plurality of second substrates (21) is made to mutually overlap, and a drive circuit (23) is disposed at such overlapping portion. Moreover, the plurality of second substrates (21) is made to mutually overlap, and the mutual circuits are connected at such overlapping portion.

1. Field of the Invention
The present invention pertains to a semiconductor device and electro-optic device employing stripping-transcription technology for stripping the thin film chip formed on a substrate and, by transcribing this to another substrate, assembling a semiconductor device. The present invention also relates to the manufacturing method of such semiconductor device and electro-optic device.
2. Description of the Related Art
A semiconductor device, for example, an electro-optic device such as a liquid crystal display device or organic EL display device, comprises function elements for carrying out a certain function of the likes of a thin film transistor or organic electroluminescence (EL) element, and a display panel including the wiring and support substrate between such function elements. Here, an electro-optic device shall mean general devices comprising an electric-optic element that emit light by an electrical effect, or which changes the state of light entering from outside, and includes those that emit light on its own, as well as those that control the passing of light. For instance, as the electro-optic element, considered may be a liquid crystal element, an electrophoretic element having a dispersive medium in which electrophoretic particles are dispersed, an EL (electroluminescence) element, and an electron emission element which makes the electron generated with the application of an electric field emit light by making such electron contact the luminescent substrate, and a display device and the like comprising the above are referred to as an electro-optic device.
Generally, the areal ratio covered by a function element in a display panel of an electro-optic device is a part of the overall area, and the wiring, electrode, support substrate and the like cover most of the area. Nevertheless, a sophisticated and complex manufacturing process is required for creating a function element of a desired performance. When manufacturing the likes of a display panel, since the support substrate, function element, wiring and so on are formed in a series of processes, a complex manufacturing process is inevitable, and, generally speaking, the manufacturing cost tends to be costly.
If it is possible to individually create the function element and wiring or support substrate and dispose such function element only at the portion required on the wiring or support substrate, on the average as a whole, the manufacturing cost of this display panel (large area semiconductor device) can be reduced. From the perspective of a manufacturing system, reduction in the manufacturing cost of semiconductor devices and electro-optic devices can be expected.
Moreover, by sequentially transcribing and disposing the function elements on a large size substrate, it will be possible to manufacture an extremely large size semiconductor device such as a large screen electro-optic device.

Method of manufacturing a semiconductor device having adjoining substrates


The present invention relates to a method of preventing caries and other sugar-dependent dental and oral lesions and to a carbohydrate binding protein-based composition suitable for use therein.

It is widely agreed that there is a direct relationship between sugar consumption and caries. Both total sugar consumption and between meal consumption have been shown to be important factors in cary development. Sugar is also thought to be an important pathogenic determinant for other oral lesions, including dental plaque and calculus, and gingival disease.
While caries have declined in frequency in most industrialized counties during the past 20 years, about 25% of the population of even those countries continues to be at high risk for caries (J. Am. Dent. Ass. 123:68 (1992)). Numerous measures have been used to control dental caries. These include fluoride treatment (of drinking water and teeth), pit and fissure sealants, vaccines, and "substrate modification". This last category includes non-sucrose sweeteners that are purported to have a specific anti-cariogenic effect, such as xylitol, sorbitol, mannitol and glycerol. Xylitol in particular is used in dentifrices such as mouthwashes and chewing gum. However, at best, such non-sucrose sweeteners have a modest effect, since they do little to remove the sucrose and other cariogenic sugars present. The present invention, by contrast, provides for the removal of sugars from the oral cavity, thereby preventing the development of caries and various other oral lesions.

Method of preventing dental caries and other oral lesions


A dual colored LED indicator is provided for each channel of an audio mixing console to enable an operator to determine the status of at least a first and second device. Preferably, a red indication from the LED indicates a device is active and a green indication from the LED indicates that a device is set to become active or has just become inactive. The invention enables an operator to determine which device is set to next become active in a cross fade operation.

In the use of audio for video mixing consoles, its is common to mix signals from various channels. With multi-channel devices, for example 24 or 48 channels, it is important to ascertain that the correct channels have been selected to implement the desired mix. Typically, a video editor may be used to implement a mix, in a manner well known in the art. Alternatively, automatic or manual mixing may be implemented.
Under a common set of circumstances, the mixing console may be connected to one or more VIDEO TAPE RECORDERS (VTRs) or other devices. Typically, the VTR may comprise some two-channel VTRs and some four-channel VTRs. Depending on the configuration of two and four-channel VTRs, different channels of the mixing console will be associated with different devices. It is often desired to cross fade different channels of these devices.
Prior art consoles enable various channels to be cross faded. However, the prior art fails to disclose enabling a user to ascertain which channels of the mixing console are currently active and which will be cross faded prior to implementation of the cross fade in the manner suggested by the present invention.
According to the invention, each channel of an audio mixing console is provided with a dual colored LED to visually indicate which channel(s) of the mixer is active and which is set to be cross faded. According to another aspect of the invention, a mode switch is provided to enable the user to make a quick verification of what is about to happen before a mix is actually implemented.


Flow control in a packet processing system includes obtaining metric data measuring utilization of at least one resource in the packet processing system over intervals of a time period. A value of a flow control load parameter is adjusted during each of the intervals based on comparing the metric data with at least one condition that indicates depletion of the at least one resource. A value of a packet flow budget is established for the packet processing system in each of the intervals based on the respective value of the flow control load parameter in each of the intervals.

Computer networks include various devices that facilitate communication between computers using packetized formats and protocols, such as the ubiquitous Transmission Control Protocol/Internet Protocol (TCP/IP). Computer networks can include various packet processing systems for performing various types of packet processing, such as forwarding, switching, routing, analyzing, and like type packet operations. A packet processing system can have multiple network interfaces to different network devices for receiving packets. The multiple network interfaces are controlled by a common set of resources in the system (e.g., processor, memory, and like type resources).
Sometimes, a network interface can receive packets at too high of a rate (e.g., higher than a designated maximum rate for the network interface). Such a packet overflow condition can be intentional, such as an attacker sending many packets to a network interface in a Denial-of-Service (DoS) attack. Such a packet overflow condition can also be unintentional, such as too many devices trying to communicate through the same network interface, or incorrectly configured network device(s) sending too many packets to the network interface. In any case, a network interface receiving an overflow of packets can monopolize the resources of the packet processing system or otherwise cause the resources to become overloaded. Other network interface and/or other processes not associated with the overflowing network interface can become starved of resources in the packet processing system, causing such network interfaces and processes to stop working.

Flow control in packet processing systems

HEWLETT PACKARD DEVELOPMENT COMPANY, L.P.


An address fault monitoring device and an ATM switching device capable of efficiently monitoring faults and quickly performing counter-fault process. Data storing unit stores data transmitted thereto. Write control unit controls the writing of data with respect to the data storing unit and notifies a read control side of write address information WD including information on a write address. Read control unit controls the reading of data with respect to the data storing unit and notifies the write control unit of read address information RD including information on a read address. Floating address measuring unit counts the number of floating addresses, and when a transmission error has occurred during transmission of the write address information WD or the read address information RD, it reckons the corresponding write or read address as a floating address. Fault notifying unit monitors the number of floating addresses to determine whether or not the number of floating addresses is greater than a preset threshold, and makes notification of fault if the number of floating addresses has become greater than or equal to the threshold.

(1) Field of the Invention
The present invention relates to an address fault monitoring device and an ATM (Asynchronous Transfer Mode) switching device, and more particularly, to an address fault monitoring device for monitoring faults associated with the occurrence of floating addresses which are unusable addresses and an ATM switching device for performing a cell routing-switching process.
(2) Description of the Related Art
ATM is a communication technique developed for public networks to accomplish, within one network, multimedia communications of data, voice, moving picture, etc. at respective required rates while maintaining respective required qualities, and has been accepted as the foundation of next-generation information communications.
Material techniques for achieving ATM communications include cell switching technique. The cell switching technique is a technique of distributing asynchronously arriving cells at high speed according to their destinations, and is implemented by an ATM switching device having a hardware-based self routing-switching function.
FIG. 10 illustrates a schematic arrangement of a conventional ATM switching device. An ATM switching device 100 constitutes a common buffer-type ATM switched speech channel.
A cell multiplexing section 101 multiplexes cells transmitted thereto from input routes #1 to #N. A write control section 102 performs write control on cells arriving at a rate of V from the N input routes, to write the cells once into a common memory 103 at a rate of Vxc3x97N.
A read control section 104 receives, from the write control section 102, write address information wd including information on addresses of the common memory 103 in which cells have been written, and stores the addresses in an address management FIFO 105 corresponding to output routes #1 to #N to which the cells are to be output.
In accordance with the addresses managed by the address management FIFO 105, the read control section 104 reads out the cells from the common memory 103.
In this case, read addresses of the common memory 103 are sent to the write control section 102 as read address information rd to be used for subsequent write operations.
A cell separating section 106 separates and outputs the cells read out from the common memory 103 according to their respective output routes.
The above components are constructed on respective integrated circuits. For example, the cell multiplexing section 101, the cell separating section 106 and the common memory 103 are constructed on LSIa, the write control section 102 is constructed on LSIb, and the read control section 104 is constructed on LSIc.
Accordingly, data is transmitted between the LSIs, and in order to ensure reliability of data transmission/reception, error correction needs to be made. In FIG. 10, error correction codes (parity information P) are exchanged between LSIb and LSIc.
If the read control section 104 detects a parity error while receiving the write address information wd, it does not read out the cell data then written into the common memory 103 at the corresponding address. An address like this which has ceased to be used due to transmission error or the like is called floating address.
Similarly, if the write control section 102 detects a parity error while receiving the read address information rd, the address (which becomes a floating address) then read out from the common memory 103 is not used thereafter as a write address.
Thus, if parity error occurs frequently, the number of floating addresses increases, reducing the storage area of the common memory 103.
Conventionally, therefore, a fault monitoring section is provided so that faults such as parity error or out-of-synchronism may be monitored by means of firmware.
However, with the conventional measures to cope with faults, those faults occurring at intervals shorter than the fault processing period of the firmware fail to be detected, and thus the number of occurrences of fault, if counted by the firmware, cannot be detected with accuracy.
Accordingly, if the firmware counts only one occurrence of fault though a plurality of floating addresses have occurred, a large number of floating addresses can possibly be created.
Seemingly, therefore, the maximum band of the overall system gradually narrows, giving rise to a problem that the common memory 103 overflows.
A first object of the present invention is to provide an address fault monitoring device capable of efficiently monitoring faults and quickly performing a counter-fault process.
A second object of the present invention is to provide an ATM switching device capable of efficiently monitoring faults and quickly performing a counter-fault process.
To achieve the first object, there is provided an address fault monitoring device for monitoring faults associated with occurrence of floating addresses which are unusable addresses. The address fault monitoring device comprises data storing means for storing data transmitted thereto, write control means for controlling writing of the data with respect to the data storing means and notifying a read control side of write address information including information on a write address, read control means for controlling reading of the data with respect to the data storing means and notifying the write control means of read address information including information on a read address, floating address measuring means for counting the number of the floating addresses by means of hardware, the floating address measuring means reckoning the write address or the read address as the floating address if transmission error occurs during transmission of the write address information or the read address information, and fault notifying means for monitoring the counted number of the floating addresses to determine whether or not the counted number is greater than a preset threshold, and making notification of fault if the counted number has become greater than or equal to the preset threshold.
To achieve the second object of the present invention, there is provided an ATM switching device for performing cell routing-switching process. The ATM switching device comprises a cell buffer for storing a cell transmitted thereto, write control means for controlling writing of the cell with respect to the cell buffer and notifying a read control side of write address information including information on a write address, read control means for controlling reading of the cell with respect to the cell buffer and notifying the write control means of read address information including information on a read address, floating address measuring means for counting the number of floating addresses, which are unusable addresses, by means of hardware, the floating address measuring means reckoning the write address or the read address as the floating address if transmission error occurs during transmission of the write address information or the read address information, and fault notifying means for monitoring the counted number of the floating addresses to determine whether or not the counted number is greater than a preset threshold, and making notification of fault if the counted number has become greater than or equal to the preset threshold.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

Address fault monitoring device and ATM switching device


A tool comprising a bar with a pair of teeth proved at one end of the bar and a handle portion attached at the other end of the bar approximately perpendicular to the bar. The teeth are spaced apart from each other in order to allow an end of a t-post clip to removably insert therebetween. The teeth are approximately parallel with the handle and extend outward from the bar in a direction opposite the direction that the handle extends from the bar. The tool is used to twist the ends of t-post clips in order to secure the clips to fence wire in order to secure the fence wire to the t-posts, or alternately, to remove the clips therefrom.

1. Field of the Invention
The present invention relates to a tool for attaching and removing a t-post clip to and from a metal t-type fence post or t-post in order to secure fence wire to the t-post and remove fence wire from the t-post.
2. Description of the Related Art
Farmers and ranchers in building fences to surround their fields often use metal t-type fence posts. Metal posts are employed because they are strong and will not deteriorate as quickly as traditional wooden fence posts.
Metal t-post clips are used to secure fence wire to the metal t-posts in order to create a fence with these metal t-posts. These metal t-post clips are short pieces of wire having a first end provided with a hook formed therein and having an opposite second end that is curved. In order to secure fence wire to a metal t-post with a t-post clip, the hook on the first end of the t-post clip is placed around the fence wire that is to be secured to the t-post. Then the curved end of the clip is pulled behind the post and back to the front of the post on the opposite side where it is then hooked to the fence wire which is positioned between raised bumps provided on the front side of the t-post. In order to secure the clip around the fence wire, the curved end of the clip is normally grasped by a pair of pliers and twisted around the fence wire so that the clip will not come loose from the fence wire. The person installing the t-clip may also then grasp the hook end of the clip with the pliers and also twist the hook end around the fence wire to make sure this end of the clip will not come loose from the fence wire.
In order to remove the fence wire from the t-post, this procedure is reversed, with the user again grasping the end of the t-clip previously twisted with pliers and bending the clip in the opposite direction to remove the clip from the fence wire and t-post.
The problem with this procedure is that the person who is building the fence will normally be wearing work gloves and it is difficult to handle a pair of pliers with gloves on. Thus, the workman who is building the fence must either try to awkwardly use the pliers with his gloves on or must constantly be taking his gloves on and off. The present invention solves this problem by providing a tool that does not require the user to grasp a pair of handles, such as found on pliers, but instead has only a single fixed handle that can be easily grasp by a gloved hand. The tool is provided with teeth that can be made to engage the clip easily and can be used by someone who is wearing gloves to easily and quickly secure a clip to fence wire around a t-post or to remove a clip therefrom.

Tool for attaching and removing T-post clips


A storage container kit with an insulated bowl and lid. Aspects of the present disclosure provide for a storage container kit comprising a first container having insulated walls, a first lid having an insulated portion extending between an upper surface and a lower surface of the first lid and configured to establish a pressurized seal with the first container, a second container configured to be housed within an interior portion of the first container, and a second lid configured to be removably coupled to an upper circumference of the second container. In some embodiments, the first lid is configured to be selectively interfaced with the first container to create a pressurized seal between a gasket, inner side walls of the first container, and a plug being removably coupled to a pressure release aperture in the first lid.

Portable insulated containers can be used for temporarily storing drinks or foods, or other products that may benefit from a cooled or warmed environment. Insulated containers that are easily transportable are known and can be used for a variety of purposes. Included are containers which are designed for temporary storage of food, drink or other perishable items for use in connection with personal travel, day trips, outings, and other similar activities where such perishable items need to be kept cool or warm for some period of time, typically several hours.

Portable container kit with insulated container and lid


A bonded joint for use in bonding composite materials is provided and includes a composite rib having electrically conductive properties and a composite structure having electrically conductive properties. An electrically conductive preform is provided that facilitates a bond between the composite rib and the composite structure. A mesh composition that bonds the composite rib to the preform and that bonds the preform to the composite structure is provided and is electrically conductive to conduct current between the composite rib and the composite structure.

In aircraft, mechanical fasteners are used to join structural components together, such as in an integrated fuel tank where a joint is formed between a spar or a rib and a skin of the aircraft. The mechanical fasteners provide a path for lightning strike currents to flow through the joint. As the industry gravitates towards newer technology that uses film adhesive with a non-conductive carrier (as an alternative to mechanical fasteners), this presents a technical gap with respect to electrical continuity of the bonded structure for lightning protection. The problem with the film adhesive process is that it electrically isolates the bond joints resulting in possible structural damage and arcing between the structural components in the event of a lightning strike. This is especially a concern with respect to integral fuel tanks.

Process for constructing lightning strike protection for adhesively bonded graphite composite joints


An elastic bearing, in particular for the suspension of a load, is provide that comprises at least one elastic body that has at least two bending beams and at least two receiving openings for receiving coupling elements, wherein at least one of the at least two bending beams is connected to at least one articulated section, and at least one reinforcement that is embedded in the at least one elastic body. The reinforcement extends at least into the at least two bending beams, wherein the reinforcement extends at least essentially linearly into the at least two bending beams in at least one predetermined section of the particular bending beam. The at least two bending beams each have at least one supporting point that ensures the at least essentially linear course of the reinforcement in the predetermined section.

The suspension device disclosed in DE 100 13 121 C1, for example, is known from the prior art. The suspension device has two bushings into which bolts may be inserted. In addition, the suspension device includes two articulated zones, between which a load beam extends. The load beam is connected to two support legs which are connected to one another. The support legs and the load beam are manufactured in one piece from a rubber. An insert is embedded in the support legs and the load beam.

SÜDDEUTSCHE GELENKSCHEIBENFABRIK GMBH & CO. KG


In an example embodiment, a method writes individual bits of data to a register. Bits of data are received in a data field. The number of bits in the data field is equal to the number of bits in the register and the bit locations in the data field correspond respectively to the bit locations in the register. Enable bits are received in a bit enable field. The number of enable bits in the bit enable field is equal to the number of bits in the register. The bit locations in the bit enable field correspond respectively to bit locations in the register. Only the bits at the bit locations of the register for which the enable bit in the corresponding location in the bit enable field is set are overwritten with the bit in the corresponding location in the data field.

1. Field of the Invention
This invention relates generally to data transfer operations between computer devices. In particular, the invention relates to methods of writing data to registers which control data transfer operations between devices in a computer system.
2. Description of the Related Art
The host processor of a computer system fetches and executes instructions which may cause the host processor to transfer data between the memory, a central processing unit (CPU) and an arithmetic and logic unit (ALU) or to initiate input/output (I/O) data transfer operations with I/O devices or peripherals external to the host processor. The computer system typically includes at least one controller which acts as the communications intermediary between the processor and one or more I/O subsystems, which may each contain one or more external I/O devices or peripherals. As a result transfer operations may not be optimized, and the wait time for processing data transferred through the computer system may be unnecessarily lengthened. The controller may be contained in a bridge, such as an I/O Controller Hub (ICH) available from Intel Corporation of Santa Clara, Calif., provided to interface with and buffer transfers of data between various computer devices.
The advanced technology attachment standard, frequently written as AT attachment (ATA) or integrated drive electronics (IDE), is commonly used for power and data signal interface communications between a host processor and a storage device. This set of standards is produced by Technical Committee T13 (www.t13.com) of the National Committee on Information Technology Standards (www.NCITS.org), Washington, D.C. The AT Attachment Interface for Disk Drives (ANSI X3.221-199×) is a disk drive interface standard that specifies the logical characteristics of the interconnecting signals as well as the protocols and commands for the storage device operation. This standard permits compatibility between host system products and storage device products that comply with the standard, even where these products are produced by different manufacturers.
An IDE controller is conventionally located between any IDE storage device (such as a hard disk drive) and the host processor. It serves as a translator to facilitate C(PU/IDE device communications over each I/O cycle. For example, on receiving an initialization command from the host processor, the IDE interface controller presents the command into something the downstream IDE device will understand, i.e. that the IDE device can handle, and sends this command to the attached IDE device. On receiving the converted command, the IDE device processes the command and sends back a completion notification to the processor through the IDE interface controller. This conventional I/O cycle from command sent to completion notification is a single task-file register access that may take approximately 1.2 microseconds (μs—one millionth (10−6) of a second).
Conventionally, the host processor dedicates a block of its processing time to the initialization of a peripheral, such as an IDE storage device. During this peripheral initialization dedication time, the host processor is prevented from performing other processing functions and thus its performance is slowed down. Furthermore, the performance of a bridge or a controller may be burdened by demands to access memory locations and control registers during data transfer operations. Conventional control registers usually offer only byte-level write control. Therefore, when software must write to a specific bit (or bits) of a byte in a control register, it must first read the byte, merge the bit (or bits) to be modified into the read byte, and then write the modified byte back to the register. See FIG. 3. For typical I/O and configuration registers, the processor is stalled approximately 1 microsecond (about 1,000 processor clocks) while performing this read-merge-write sequence (perhaps only to write a single bit). If the read-merge-write sequences are necessary for streamlining of the initialization command sequence, then they inherently prevent the sequence from being posted to the controller for the external I/O device or peripheral.

Bit-granular writes of control registers


A data driver device and a display device, in which the data driver device includes a plurality of data lines; a plurality of first charge-share switches connected between a share line and the plurality of data lines, respectively; and a plurality of second charge-share switches each connected between two adjacent data lines among the plurality of data lines.

With the development of semiconductor technology, display devices tend to have a large size in order to satisfy the consumers' demand. As a display device becomes large, the load of a display panel, for example, a liquid crystal display (LCD) panel, increases. Source lines or data lines in the display panel are driven by a data (or source) driver device.
When a display device, for example, an LCD television (TV), becomes large, a load resistor, for example, a source line resistor, of a display panel, for example, an LCD panel, is manufactured with a decreased value in order to reduce power consumption of the display panel. On the other hand, when the display device becomes large, the load capacitance, for example, source line capacitance, of the display panel is increased.
When the value of the load resistor of the display panel is decreased and the load capacitance of the display panel is increased, the power consumed in the data driver device to drive the source lines of the display panel increases, causing a considerable amount of heat to be generated in the data driver device. More specifically, power consumption increases significantly in charge-share switches included in an output circuit of the data driver device.
FIG. 1 illustrates an output circuit 100 of a conventional data driver device. Referring to FIG. 1, the output circuit 100 includes a plurality of output terminals 111 through 11n. The output terminals 111 through 11n respectively receive gray voltages V1 through Vn and output them to source lines S1 through Sn, respectively of a display panel (not shown) to respectively drive the source lines S1 through Sn.
Each of the output terminals 111 through 11n includes a respective amplifier 121 through 12n, a data line switch T1 through Tn, a charge-share switch H1 through Hn, and an output pad PAD1 through PADn. Each of amplifiers 121 through 12n respectively included in the output terminals 111 through 11n amplifies a corresponding gray voltage V1 through Vn output from a digital-to-analog converter (DAC) (not shown) is of the data driver device and outputs the respective amplified gray voltage V1 through Vn. When the data driver device drives source lines in the display panel using a dot inversion method or a source line inversion method, an odd numbered gray voltage, for example, V1, and an even numbered gray voltage, for example, V2 which are adjacent each other among the gray voltages V1 through Vn, have opposite polarities.
The first data line switch T1 of the first output terminal 111 is switched in response to a first control signal P1 and a first inversion control signal PB1, so that an output of the first amplifier 121 is transmitted to the first source line S1 of the display panel via the first output pad PAD1. Charge-share switches H1 through Hn are connected between a share line Sh and data line switches T1 through Tn, respectively. The charge-share switches H1 through Hn are switched in response to a second control signal P2 and a second inversion control signal PB2. When the data line switches T1 through Tn are turned off the charge-share switches H1 through Hn are turned on.
When the charge-share switches H1 through Hn are turned on, the source lines S1 through Sn in the display panel are connected with one another via the share line Sh, so that charges are distributed to a plurality of cells in the display panel. As a result, the source lines S1 through Sn share a source line voltage, that is, a charge-share voltage after the completion of the charge distribution. At this time, the share line Sh has the charge-share voltage.
FIG. 2 illustrates a pair of the adjacent output terminals, such as 111 and 112 illustrated in FIG. 1, and loads LOAD1 and LOAD2 respectively corresponding to the adjacent output terminals 111 and 112 in a display panel (not shown). Only one pair of the output terminals, such as 111 and 112, are illustrated in order to clearly describe power consumed by charge-share switches, for example, H1 and H2, of the data driver device when the display panel is charge shared. Each of the loads LOAD1 and LOAD2 is modeled of the resistance and capacitance of each of the source lines S1 and S2.
Referring to FIG. 2, when the display panel is charge shared, the data line switches T1 and T2 are turned off and the charge-share switches H1 and H2 are turned on. When the first gray voltage V1 is a positive voltage and the second gray voltage V2 is a negative voltage, a voltage of the first source line S1 is greater than that of the second source line S2. Accordingly, when the display panel is charge shared, a share current Is flows from the first source line S1 to the second source line S2 via the charge-share switches H1 and H2, as illustrated in FIG. 2. For the share current Is illustrated in FIG. 2, only the charge-share between the first source line S1 and the second source line S2 has been considered. When all of the source lines S1 through Sn in the display panel are considered, the share current Is may have a different value.
When a load resistance of a source line in a display panel decreases and a load capacitance of the source line increases, power consumption due to a share current in charge-share switches increases considerably. As a result, heat generation in a data driver device may also be increased. Accordingly, it is desired to reduce power consumed in the charge-share switches in an output circuit of the data driver device when the source lines in the display panel are charge shared.

Data driver device and display device for reducing power consumption in a charge-share operation


Aspects of the present invention include a circuit that includes an input balun circuit responsive to an input signal, the input balun circuit being configured to provide two output signals that are out of phase with each other. The circuit further includes an actual switched amplification stage configured to direct one of the balun output signals to a phase inverter output, and a replica switched amplification stage connected in parallel with the actual switched amplification stage, wherein the actual switched amplification stage and the replica switched amplification stage are responsive to the two output signals from the input balun circuit to direct one of the balun output signals to the phase inverter output, and wherein the actual switched amplification stage and the replica switched amplification stage are configured to have a constant load impedance for both switch states that matches an impedance of the input balun circuit.

The present invention relates to a phase inverter circuit, and more specifically, to a phase inverter circuit having an input balun circuit and having a replica switched amplification stage to load the input balun circuit in parallel with the actual switched amplification stage of the phase inverter.
A phase inverter is a circuit that includes an input terminal, an output terminal and one bit control terminal. Typically, the input and output signals are single ended signals. A phase inverter creates a 180 degrees phase difference of the output signals when the control bit is being toggled between the "ON" and "OFF" states.
A "balun" or "balanced to unbalanced" circuit is a common electrical or electronic circuit that comes in many different types or forms. A balun may be used as part of a phase inverter circuit that converts a single ended input signal into a differential output signal (i.e., phase inverted or 180 degrees out of phase).
The phase inverter may include a switched amplification stage or circuit at the output of the phase inverter. Only one of the two outputs of the balun circuit may be directed to the phase inverter output, thus controlling the desired phase of the phase inverter output.
As the phase inverter is toggled between its two output states, it is important that the differential load or impedance seen by the input balun circuit always remain approximately the same; for example, one hundred ohms (100Ω). If the balun is not properly loaded as such by the remainder of the phase inverter circuit, then the phase difference between the two outputs of the phase inverter may not be 180 degrees out of phase and, thus, the output of the phase inverter may not accurately invert the phase. Also, the phase inverter input matching may degrade.
Consider an example where a phase inverter circuit comprises only an input balun circuit and a switched amplification stage at the phase inverter output. When one side of the phase inverter circuit output is switched "ON" for example, that side of the phase inverter circuit can easily match the impedance seen by the input balun circuit to 50Ω. However, the other output side of the phase inverter circuit is switched "OFF" and exhibits a relatively high impedance value as seen by the input balun circuit. As a result, in this exemplary situation the input balun circuit is not properly loaded at all times with a 100Ω differential impedance.
A balun circuit may comprise transistors (an "active" balun circuit) or the balun circuit may comprise inductors and capacitors (a "passive" lumped balun circuit). Also, baluns may comprise transmission lines in a Marchand balun structure (a "passive" Marchand balun circuit). Also, baluns may comprise other types of electrical components (e.g., transformers).
Baluns find usage in a wide range of devices, including high frequency (e.g., 60 GHz V-Band) phased array devices and transceivers for use in, e.g., radar applications. Baluns are oftentimes embodied in integrated circuits ("ICs") or may comprise various discrete electrical components mounted on a printed circuit board. Regardless, it is desired that the phase inverter circuit that includes the input balun circuit be implemented in a relatively compact and simple manner.

Balun based phase inverter using replica load

INTERNATIONAL BUSINESS MACHINES CORPORATION


A beam shutter apparatus designed to handle high powered UV radiation is disclosed. The shutter includes a high reflectivity mirror mounted on a plate which can be rotated between a first position where the beam is reflected and redirected to a tool such as a beam dump and a second position where the beam is free to pass out of the laser, where the beam is free to pass out of the laser The shutter includes a support base with an angled upper surface upon which the mirror plate rests when in the second position. The support base has a beam path channel designed so that a beam can pass through the support base and out of the shutter when the mirrored plate is in the first position. The mirrored plate is rotated by a linkage, which is driven by an electrically powered actuator on a rotational magnet. The support base is machined out of a monolithic piece of metal allowing very high precision without the need for cumbersome alignment procedures.

The present invention relates to a beam shutter designed for industrial excimer lasers including a rotating mirror for selectively opening and closing the beam path.
High power lasers require laser shutters which can withstand up to 300 W output power. A prior art design consists of a large metal piece which can be pulled upwards out of the beam path by an electrically or pneumatically activated actuator. De-energizing the actuator results in closing the beam path by sliding down the metal piece. A common choice for the metal beamstop is an extruded aluminum heat sink guided by sliding rails or rod-roller bearings. For high power XeCL lasers it is advantageous to either plate the metal beam stop with copper or to use a solid copper beam stop. Copper has a lower ablation rate than aluminum and therefore contamination of laser and beam line optics is reduced. However, there are several disadvantages of this high power shutter design. First, the heavy metal beam stop results in slow opening and closing times. Further, the large heat load on the moving metal beam stop causes significant thermal expansion of the beam stop so that the sliding rails or rod-roller bearings of the beam stop must have large clearance to permit the up and down movement. Such large clearances are contradictory to precise shutter movement. In addition, the shutter is not light tight to the required extent because of the large required clearance between moving parts. Further, the removal of the large heat load requires a large opening for ventilation, which yields a design which cannot be integrated into a purged beam path with low losses of purge gas.
One state of the art beam shutter (U.S Pat. No. 5,596,590) has a linear slide base guided by a pair of rod-roller bearing supports. Making this shutter light tight requires precise alignment of the moveable mirror base relative to the shutter housing. Additionally, the pair of rod-roller bearing supports must be precisely aligned. The required precision is in the order of 0.1 mm. Low fit tolerances of all mechanical parts are mandatory. The precision alignment of the moveable mirror base and low fit tolerances are disadvantages to this type of shutter design. Therefore, it is desirable to have a shutter that achieves precision alignment for light tightness without cumbersome alignment procedures.
Another state of the art shutter has two metal blades that interrupt the beam path. This type of shutter is very fast, with opening and closing times of less than 100 ms. However, when the metal blades interrupt the laser, the laser power is partially reflected and partially absorbed by the metal blades. Consequently this type of design can handle only very low average power levels. Dielectrically coated metal blades increase the power handling capability of this shutter type significantly. However, in the ultraviolet spectral range, the coatings are not perfect and a portion of UV laser beam will still reach the metal blades. Therefore, the shutter can not handle the required level of UV light. Consequently it is desirable to have a beam shutter that can handle high levels of UV light.
Also, there is a state of the art shutter that consists of a hollow metal cylinder preferably made of a metal with low specific gravity rotated by an electrically powered actuator. The hollow cylinder has two rectangular openings symmetrically positioned to the cylinder axis. Depending on the rotational position of the cylinder, the laser beam could either pass through the two rectangular openings or be blocked by the solid section of the cylinder. The thin wall metal cylinder has a low moment of inertia which results in a fast opening and closing time of about 100 ms. However the disadvantage of this shutter is the low power handling capability and the high level of stray light caused by the beam reflected off the solid section of the hollow cylinder. It is more desirable to have a shutter that has a high power handling capability and is light tight.
An object of the present invention is to provide a beam shutter which can handle high powered UV radiation.
It is a further object of the present invention to provide a beam shutter that does not require precise alignment of moveable parts.
It is a another object of the present invention to provide a beam shutter that is leak tight regarding purge gas, making purge gas loss extremely low.
The objects and features of the present invention are realized by the use of a beam shutter having a high reflectivity mirror mounted on the top side of a plate which is rotated into the beam path in order to interrupt the beam and reflect it to a side port, to which a beam dump or diagnostic tool is attached. The beam dump or diagnostic tools are attached to the side port by rotation using a bayonet-type fitting.
The shutter has a base including an angled upper surface for supporting the plate and mirror at an angle for reflecting the laser beam to the side port. The shutter base has a beam channel through it to allow a beam to pass unimpeded when the plate and mirror are rotated to an open position away from the base. The plate carrying the mirror is equipped with a labyrinth seal on its underside to achieve light tightness when positioned on the shutter base.
Because the upper surface of the shutter base is machined at a predetermined angle, there is no need for precise motor control for positioning the mirror for reflection. The mirrored plate is simply rotated into contact with the upper surface of the shutter base. The labyrinth seal under the plate fills and seals the beam channel in the shutter base for light tightness. When no reflection is desired, the mirror is rotated out away from the channel an amount sufficient to allow the beam to pass.
The plate is connected to a linkage, which rotates the plate and mirror into and out of position for reflecting the beam. The linkage is comprised of several members connected by lubricant free bearings, and is operated by a rotational magnet, which is attached to the shutter housing. The design of the shutter base and linkage eliminates the requirement for the precision alignment of mechanical parts. Also the shutter body including the bearing seats are machined out of a monolithic piece of metal, which further allows precision without other cumbersome alignment features.


A medical bag formed of a flexible material includes a front bag part and a rear bag part joined together to form a bag body. A closable liquid inlet port is provided in an upper part of the bag body. The medical bag further includes a deformable elongated member provided in the vicinity of the liquid inlet port on at least one of the front and rear bag parts. The elongated member is deformable so as to retain the liquid inlet port in an open configuration when the elongated member is in a deformed state.

It is conventional practice to supply medical liquids such as medicinal products and nutrients by keeping the tip end part of a catheter inside a patient's body, for example. In cases such as these, a medical bag is connected to the rear end part of the catheter, and the medical liquid housed inside the medical bag is supplied to inside the patient's body via the catheter (see Japanese Patent Application H6-98922, for example). This medical bag (infusion container) is configured by a container main body made of thermoplastic resin, a contents filling part which is integrally provided with the container main body, a contents dispensing part adjacent to the contents filling part and integrally provided with the container main body and a sheet-shaped part in which a suspension aperture is formed. Then, the contents filling part is used to fill the medical bag with medical liquid, with the contents dispensing part being used to dispense medical liquid from inside the medical bag to the outside, and the contents filling part and the contents dispensing part are respectively configured by roughly cylindrical aperture parts.
However, with a conventional medical bag as described above, the contents filling part and the contents dispensing part are configured by a fairly rigid material which does not lose its shape, and the respective aperture parts are held open. Consequently, when this medical bag is packaged after production, there is a problem in that it ends up being bulky. Furthermore, the roughly cylindrical contents filling part and contents dispensing part must be moulded, and therefore there are problems in that the shape of the medical bag becomes complex and the production costs are increased.
For example in U.S. Pat. No. 4,869,725, use is also made of medical bags equipped with a zip-type medical liquid inlet port which is opened and closed with a detachable linear groove part and projection. However, with medical bags equipped with this zip-type medical liquid inlet port, when the medical bag is filled with medical liquid it is necessary for the user to handle the container which contains the medical liquid and to transfer the medical liquid in the container to the medical bag with one hand, while holding the medical liquid inlet port open with the other hand, and therefore problems arise in that the operation to fill the medical bag with medical liquid is troublesome.

Medical bag with a support member and grasping holes


A conduction-cooled radiofrequency coil subsystem of MRI system with high signal-to-noise ratio imaging capability at low field and/or ultra-low field. The conduction-cooled RF coil subsystem includes a radiofrequency (RF) coil module having at least one RF instrumentation; a cryocooler; and a thermal conduction line thermally connected between the cryocooler and the RF instrumentation. The RF coil module further includes a housing defining a thermally insulated vessel for accommodating the RF instrumentation. The thermal conduction line is thermally coupled to the cryocooler which is located outside the housing of the RF coil module and the RF instrumentation in the thermally insulated vessel to conduction cool the RF instrumentation. The at least one RF instrumentation includes one or more of an RF transceiver coil, an RF receiver coil, an RF preamplifier and an RF electronics module.

Magnetic resonance imaging (MRI) has impacted modern healthcare tremendously and is recognized by clinicians as the most valuable medical device innovation in the last three decades. MRI is now a routine procedure in diagnosis and management of various diseases and injuries, and over 100 million MRI investigations are performed each year worldwide. It is the most powerful diagnostic imaging modality because of its capability in detecting and characterizing pathological tissues with high sensitivity and specificity in an inherently quantitative, non-invasive and non-ionizing manner.
While advances in the MRI hardware such as increased field strength and improved gradient performance have been substantial, advances in the radiofrequency (RF) technology have also proved to be valuable to improve the resolution and shorten the duration of MRI examination. MRI RF coils are essential components for every MRI examination, as they are responsible for the excitation and the reception of the MR signal. The signal-to-noise ratio (SNR) fundamentally represents the statistical confidence one can have in the robustness of the appearance of features in the image. Moreover, a factor of √{square root over (N)} improvement in SNR by RF coils can be used to decrease scan time by a factor of N. In summary, the quality of MRI images and speed of an MRI examination, which are critical for clinical applications and diagnostics, are highly dependent upon the SNR performance of the MRI system. This issue of SNR performance is particularly critical for low (0.1 to 0.5T) and ultra-low (0.01 to 0.1T) field MRI systems, whereby SNR is extremely low compared to conventional high-field MRI system (1.5 to 3.0T) given the approximately linear relationship between SNR and field strength.

Conduction-cooled radiofrequency coil subsystem and magnetic resonance imaging magnet system having the same

CHENGDU YIJIAN MEDICAL TECHNOLOGY CO., LTD


A plating resist film 2 is formed on a wiring board substrate 1 as a core material of a multilayer printed wiring board, then a through-hole 3 is formed, and through-hole conductor 4 is formed along the wall surface of the through-hole 3 and the through-hole surface of the plating resist film 2, so that protrusion portion 4a is formed in the through-hole conductor 4. The plating resist film 2 is then stripped off and a panel plating layer 5 is formed on the surface of the wiring board substrate 1 and the through-hole conductor 4 so that the through-hole 4 and the panel plating layer 5 are connected with the protrusion 4a coated, and thus the connection area can be increased.

This application claims priority under 35 U.S.C. § 119 (a) on Patent Application No. 2004-312520 filed in Japan on Oct. 27, 2004, the entire contents of which are hereby incorporated by reference.
The present invention relates to a method for producing a multilayer printed wiring board that improves the reliability of through-hole conductor formed on a multilayer printed wiring board, a multilayer printed wiring board, and an electronic device using such a multilayer printed wiring board.
FIGS. 13 and 14 are cross-sectional views in a process for explaining a multilayer printed wiring board of Conventional example 1 and a method for producing the same.
FIG. 13 shows a base material of a multilayer printed wiring board of Conventional example 1. For the base material of the multilayer printed wiring board, a commercially available laminate having copper coating on both its sides, more specifically a laminate having a copper foil as a metal foil 102 laminated on each side of a resin plate 101 serving as a core material, is used. A through-hole 103 (see FIG. 14) is formed on the base material with a drill or the like, followed by application of an appropriate plating pretreatment.
FIG. 14 shows a state in which the laminate having copper coating on both its sides for a multilayer printed wiring board whose entire surface has been subjected to panel plating after the plating pretreatment performed in FIG. 13. The panel plating is a plating process to form a metal layer (a panel plating layer 104 and a panel-plated through-hole conductor 104a) on the entire surface of the multilayer printed wiring board (laminate having copper coating on both its sides) through electroless plating or electrolytic plating. The metal plating is usually performed using the same metal as the metal foil 102.
Subsequent to application of the panel plating, the multilayer printed wiring board is formed by forming an etching resist on the surface of the panel plating layer 104 and patterning the panel plating layer 104 and the metal foil 102 so that a conductor pattern that corresponds to specific circuit wiring is formed.
In addition to Conventional example 1 described above, Conventional examples 2 and 3 as follows have also been known.
As Conventional example 2, a method is proposed in which a desired pattern (conductor pattern) including a land portion for forming wiring around a through-hole portion is formed on the surface of a copper-coated laminate substrate, and then a resist is formed on the portions other than the through-hole portion and the land portion before a hole is opened so as to form the through-hole portion (for example, JP S60-43893A (hereinafter referred to as Patent document 1) and Japanese Patent No. 3048360 (hereinafter referred to as Patent document 2). This method requires an additional plating process since a through-hole conductor is formed by separately performing a plating process exclusively to the through-hole portion. In addition, as the land portion becomes smaller, positioning becomes more difficult.
As Conventional example 3, a method is proposed in which a through-hole conductor is formed by forming a desirable circuit conductor (conductor pattern) on the surface of an insulating substrate, then forming a protective film on the entire surface, forming a hole (through-hole), and removing the protective film from around the through-hole (for example, see JP H8-34340B). This method also entails the same problems as Patent documents 1 and 2.
As the size reduction and sophistication level of electronic devices advance, a demand for increased wiring density on a wiring board has become stronger. Responding to such a demand, the number of conductor layers on a wiring board shows an increase in trend. Meanwhile, there has also been a strong demand for cost reduction for wiring boards, and a demand for reduced number of conductor layers to reduce wiring board cost has also been strong. With these backgrounds, the line width of wiring patterns (conductor patterns) has kept decreasing in order to achieve a higher wiring density. This tendency is especially significant in a conductor pattern on the outer-most layer of wiring boards.
When forming a conductor pattern using a conventional etching method, it is difficult to achieve a fine conductor pattern beyond a certain point due to an issue of aspect ratio between the line width and film thickness of a conductor pattern. For example, as mentioned in Conventional example 1, the film thickness of a conductor in a layer for forming a conductor pattern (metal foil and panel plating layer) is a sum of the film thickness of a metal foil layered on a multilayer printed wiring board as the base material and the film thickness of a panel plating layer formed through panel plating, which results in 50 μm or more in normal constructions.
In addition, when forming a conductor pattern through etching, it is difficult to change the etching speed ratio between the depth direction and plane direction of the conductor pattern. The ratio between the minimum line spacing (width between conductor patterns) and film thickness of a conductor (film thickness of a conductor pattern) that can be produced by patterning is close to 1:1.
In general, the line width of a conductor pattern and the conductor pattern spacing are designed so that the ratio is close to 1:1. For this reason, it has not been easy to form a conductor pattern with a line width smaller than the film thickness of the conductor pattern.
Consequently, when a finer conductor pattern with a smaller line width is desired, a generally selected method is to reduce the film thickness of a panel plating layer or the film thickness of a metal foil, which is layered on the multilayer printed wiring board as the base material.
The film thickness of a panel plating layer is equal to the film thickness of a through-hole conductor. However, the film thickness of a through-hole conductor can become smaller than the film thickness of a panel plating layer depending on conditions such as the state of the wall surface of the through-hole and the flow of plating fluid, and often varies due to unstable deposition of a plating metal. Accordingly, the film thickness of a panel plating layer cannot be reduced too much, in view of the heat stress to be applied during the use of the multilayer printed wiring board and at the time of mounting electronic components, reliability in a long-term use, an increase in the conductive resistance of through-hole conductor and others, and therefore a conductor pattern with a small line width cannot be formed.
In addition, although it is possible to reduce the film thickness of the metal foil to some extent, there are problems in that the production cost increases to form thin metal foils, and in that handling of the metal foils is more difficult because of their small thickness, for example, a surface treatment prior to formation of a panel plating layer (pretreatment for plating) is performed with difficulty.
Furthermore, when the film thickness of the panel plating layer is reduced relative to the film thickness of the metal foil, the film thickness of the through-hole conductor (panel plating layer) can become particularly thin around the opening of the through-hole (shoulder area of the land portion of the through-hole conductor which achieves conductivity between the through-hole conductor and the metal foil), which could result in susceptibility to thermal shock. In other words, relative reduction in the film thickness of the panel plating layer causes such problems as deteriorated reliability of the through-hole conductor and increased conductive resistance of the through-hole conductor.

Method for producing multilayer printed wiring board, multilayer printed wiring board, and electronic device


The present invention relates to a thin film transistor. The thin film transistor includes a semiconductor having first, second, third, fourth, and fifth electrode regions arranged in a direction and spaced apart from each other and first, second, third, and fourth offset regions disposed between the first, second, third, fourth, and fifth electrode regions, respectively. An input electrode is connected to the third electrode region, an output electrode is connected to the first and fifth electrode regions, an insulating layer is disposed on the semiconductor, and a control electrode is disposed on the insulating layer and the second and fourth electrode regions.

1. Field of the Invention
The present invention relates to a thin film transistor and an organic light emitting device including the thin film transistor.
2. Discussion of the Background
Active display devices such as liquid crystal displays (LCDs) and organic light emitting devices (OLEDs) include a plurality of pixels arranged in a matrix. Each pixel includes a field generating electrode and at least one transistor. The transistor may be a thin film transistor (TFT) having a semiconductor and three terminals such as a control terminal, an input terminal, and an output terminal. The thin film transistor transmits a data voltage in response to a gate signal or generates a current in proportion to the data voltage.
A display panel of the display devices may include a plurality of conductive layers and a plurality of insulating layers. The control electrode, the input and output electrodes, and the field generating electrode may be formed on the different conductive layers, respectively, and may be spaced apart from each other by the insulating layers.
When constructing the display panel, the thin film transistor may be manufactured in an inverse staggered bottom gate manner or a staggered top gate manner.
With a staggered top gate thin film transistor, the semiconductor is formed as the bottom layer, the input and output electrodes are formed on the semiconductor, and the gate electrode is formed as the top layer. The gate electrode overlaps the input and output electrodes as well as the semiconductor through the gate insulating layer.
However, near the edges of the input and output electrodes, the inclination distribution of the gate insulating layer may be different for each transistor and therefore, section shapes of the control electrodes may differ. When the section shapes of the control electrodes differ, an electric field generated by the gate electrodes may have a different shape, which may change the current amount driven by the transistors.
To prevent the above problems, the control electrodes may be designed such that the input and output electrodes do not overlap the control electrodes, and offset regions may be generated in semiconductor portions between the control electrodes and the input and output electrodes.
The display panel may be manufactured by an exposing process, an etching process, etc. When a mother substrate for manufacturing the display panel is larger than a predetermined size, the mother substrate may be divided into several regions and the exposing process may be sequentially performed for each region (partition exposure).
However, in the exposing process, an alignment error may occur due to shifting, rotation, or distortion of a mask. In addition, even when partition exposure is not performed, an alignment error may occur because of inaccuracies caused by the exposure equipment.
In particular, when the distance between the control electrode and the input electrode of the thin film transistor and the distance between the control electrode and the output electrode of the thin film transistor are different, the distances of the offset regions at the sides of the control electrodes are different, and therefore, the resistance of the offset regions and current amount based on the resistance may deviate.

Thin film transistor and organic light emitting device including thin film transistor


An automatic solder paste feeding system, comprising: a base, a container mounted on the base and configured to contain a solder paste therein, a syringe mounted on the base and configured to inject the solder paste into the container, and a heater mounted on the base and configured to heat the solder paste contained in the container, so that the solder paste is melted into liquid state.

In the field of manufacturing an electrical device, solder paste is often used, for example, to weld a lead or a pin of the electrical device. In the prior art, the solder paste is generally manually coated on the lead or pin of the electrical device to be welded in advance. Then, the coated solder paste is heated and melted into liquid state by a solder head. After the solder paste is cooled and solidified, the operation of welding the lead or pin of the electrical device is finished.
However, the efficiency of manually supplying the solder paste is very low, which is only suitable for welding a single electrical product and not suitable for welding electrical products in mass.


A pluggable optical transceiver is disclosed in which, even an irregular operation is carried out, the engagement between the transceiver and the rail may be secured. The optical transceiver, which is pluggable with the rail provided in the host system, includes a grip assembled with the receptacle, a latch lever to be engaged with the rail, a leaf spring that pushes the latch lever outward and an actuator to make a seesaw motion to rotate the latch lever synchronizing with the slide of the grip. Because the center of the rotation center of the latch lever positions inward with respect to the end of the latch lever, the engagement of the latch lever with the rail may be further secured even the irregular operating is applied in the latch lever.

1. Field of the Invention
The present invention relates to an optical transceiver, in particular, the invention relates to a mechanism of a pluggable optical transceiver to engage or disengage with rail of the host system.
2. Related Prior Art
A pluggable optical transceiver in one aspect thereof is used to be installed in a host system such as computer or optical HUB system, while according to another aspect, the pluggable transceiver receives an optical connector in an optical receptacle installed in the transceiver to optically couple the optical fiber in the connector with an optical device in the receptacle.
Such optical transceiver is set on the host system by, for example, engaging the latch lever provided in the sides of the transceiver with the keyhole formed in the rail on the host system. To engage or disengage the latch lever with the keyhole may insert the transceiver in the host system or release it from the system.
A conventional transceiver provides a latching mechanism shown in FIGS. 4A and 4B, which has been disclosed in the United States patent application published as US20050286837A, to engage with and to release from the rail provided on the host system. FIGS. 4A and 4B omit the upper housing to explain the latching mechanism in the lower housing and only show the optical receptacle portion of the transceiver.
FIG. 4A shows a condition in a case that the optical transceiver 100 is set in the host system, where an end 101c of the actuator 101 engages with the keyhole 2a of the rail 2. The optical receptacle 16 of the transceiver 100 provides a grip 10, which surrounds the receptacle 16, to manipulate the grip 16 for releasing the engagement between the actuator 101 and the keyhole 2a. Pulling the grip 10 frontward, to the left side in FIG. 4A, the end 101c of the actuator 101 slides up the slope 10b to push the end 101c of the actuator 101 outward. Because the actuator 101 performs the seesaw motion by the pivot 101b as a center, the other end 101a of the actuator 101 may be pulled within the transceiver 100, which is shown in FIG. 4B.
Thus, the engagement between the end 101a of the actuator 101 and the keyhole 2a of the rail may be released and the transceiver 100 becomes free from the rail 2. Sliding the transceiver 100 on the rail 2 frontward after releasing the engagement between the end 101c and the keyhole 2a, which also disengages the electrical plug provided in the rear end of the transceiver 100 with the electrical connector on the host system, the transceiver 100 may be extracted from the host system.
An elastic member 102 such as leaf spring always applies an outward force to the other end 101a of the actuator 101, which not only pushes the other end 101c outward but also pulls the end 101c of the actuator inward. As a result, the end 101c of the actuator 101 is automatically set in the bottom of the slope 10b, that is, the transceiver 100 sets the grip 10 closest to the body of the transceiver 100 in a state free from the rail 2, which is the neutral position of the grip 10.
When an irregular external force F4 is applied to the transceiver 100, where the transceiver 100 in the end 101a of the actuator 101 engages with the rail 2, to extract from the rail 2 without manipulating the grip 10, the tip end 101a of the actuator 101 receives a moment F6 due to the reaction force F5, which operates so as to release the engagement with the rail 2 as shown in FIG. 5. This situation may appear when the rail 2 is relatively thick, that is, in a case the tip end of the actuator 101 abuts against the wall surface of the rail 2, not hooked by the rail in the case the rail is formed by a metal plate.

Optical pluggable transceiver with securable latching mechanism


An apparatus for treating textile yarn in package form is disclosed having a kier for supporting yarn packages for treatment therein, a pump connected to the kier for pumping treating liquor to the kier to treat yarn packages supported therein, an expansion tank connected to the kier for receiving treating liquor from the kier and connected to the pump for passage of treating liquor from the expansion tank to the pump for recirculation to the kier, a device for supporting yarn packages in the expansion tank, valving operable for alternatively using the expansion tank as a kier and the kier as an expansion tank. The kiers and expansion tank are of differing capacities to accommodate varying load sizes at minimum liquor ratios. The heat exchangers are also of differing capacities for more efficient operation of the system.

The treatment of yarn in package form may involve washing, bleaching, dyeing, rinsing or other liquid treatment. The yarn is typically wound on dye tubes as yarn packages and placed on a series of spindles or other core members within a treatment chamber. The yarn treating liquid is circulated into the treatment chamber and through the packages of yarn at elevated temperatures and pressures. The heated liquid under pressure penetrates the package and the individual strands of yarn or fibers fully or to a predetermined depth for special effects. The treating liquid is typically forced from the spindle or core member into the inside of the tube outwardly through the yarn, and in some systems the treating liquid is forced from outside the package inward through the package into the core member.
A problem with previous package dyeing systems is that it has not been practically feasible to vary the amount of treatment liquor for optimum usage with loads of yarn varying from a standard capacity of the system. This use of oversized equipment for small loads is both expensive and environmentally unsound because of the need to fill the kiers with the same amount of liquor as for full sized loads.
In other types of textile dyeing systems, for example dye becks for treating lengths rather than packages of textile material, where relatively large dye becks are standard in the art and are designed to handle several hundred yards of material bunched in rope form, conversion systems, such as disclosed in U.S. Pat. No. 3,635,053, have been developed for changing the capacities of such large dye becks by employing a number of relatively small dye becks constructed and designed to be fitted into the standard large dye beck in a side-by-side relation so that separate dyeing operations can be carried out in each of the smaller dye becks simultaneously. However, a satisfactory practical method and apparatus for selectively varying the capacities in package dyeing systems to adjust to loads varying from a standard load are not known.

Apparatus and method for treatment of yarn in package form