There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.

A flash memory device is a type of a nonvolatile memory device being capable of retaining data with a power supply cut off, and is a highly-integrated device made using an EPROM (erasable programmable read only memory) and an EEPROM (electrically erasable programmable read only memory).
A conventional flash memory cell has a stack-gate structure including a tunnel oxide layer, a floating gate, an insulating layer, and a control gate, which are stacked on a semiconductor substrate between a source and a drain.
One drawback associate with the stack-gate structure is an over-erase phenomenon, and as one of the efforts to solve the problem, there has been introduced a flash memory cell having a split gate structure. Japanese Laid Open Disclosure No. 1999-284084, entitled, "Nonvolatile Semiconductor Memory Device and its Manufacture," by Otani Toshiharu, discloses a method of fabricating a split gate using a local oxidation of silicon (LOCOS) process.
FIGS. 1A to 1E illustrate in detail a method of fabricating a flash memory cell having a split gate structure in accordance with prior art.
As shown in FIG. 1A, a gate oxide layer 11, a first polysilicon layer 12, and a silicon nitride layer 13 are stacked on a semiconductor substrate 10.
Then, as shown in FIG. 1B, by patterning the silicon nitride layer 13, there is formed a silicon nitride layer pattern 13A having an opening 13B therein, exposing a portion of the first polysilicon layer 12.
Then, as shown in FIG. 1C, a poly oxide layer 14 is formed by performing a LOCOS process using the silicon nitride layer pattern 13A as an oxidation stop layer so as to oxidize a portion of the exposed first polysilicon layer 12.
Then, as shown in FIG. 1D, a floating gate 12A is formed under the poly oxide layer 14 by removing the silicon nitride layer pattern 13A and etching the first polysilicon layer 12 using the poly oxide layer 14 as an etch mask.
Then, as shown in FIG. 1E, an oxide layer 15 is formed on the semiconductor substrate 10 and the poly oxide layer 14, and then, a control gate 16 overlapping a portion of the floating gate 12A is formed of a second polysilicon layer. Then, the processes of forming spacers 17 on the sidewalls of the floating gate 12A and the control gate 16, and forming source/drain 18A, 18B inside the semiconductor substrate 10, and the like are performed. The oxide layer 15 functions as a tunnel oxide layer 15A in the region between the floating gate 12A and the control gate 16, and functions as a gate oxide layer 15B in the region between the semiconductor substrate 10 and the control gate 16.
However, the LOCOS process in the conventional method of fabricating a flash memory cell having a split gate structure described above has a difficulty in forming the poly oxide layer 14, being formed for the insulation between the floating gate 12A and the control gate 16, with a uniform thickness. Further, the LOCOS process has some other drawbacks such as causing a heat budget due to the thermal oxidation performed at a temperature of about 800° C., and a smiling effect on the boundary of the gate oxide layer to be thickened. Therefore, the degradation of cell characteristics may result, and malfunctioning may happen during programming and erasing operations.
Many parasitic capacitors exist in the flash memory cell having the split gate structure fabricated by the method in accordance with the conventional approach described above. Referring to FIG. 1E, there exists a tunnel capacitor (Ct) between the sidewalls of the control gate 16 and the floating gate 12A, and there exists a gate interlayer capacitor (Cip) between the control gate 16 and the upper surface of the floating gate 12A. Further, there exists a channel capacitor (Cc) between the floating gate 12A and the semiconductor substrate 10, and there exists a source capacitor (Cs) between the floating gate 12A and the source 18A.
In programming the flash memory cell having the split gate structure as shown in FIG. 1E, a high voltage is applied on the source 18A, and a grounding voltage is applied on the drain 18B. The electrons generated in the drain 18B move to the source 18A through the channel region formed in the semiconductor substrate 10 by the program voltage applied on the control gate 16. The program voltage is lower than the voltage applied on the source 18A and higher than the threshold voltage for the formation of the channel region. Some of the electrons being moved to the source 18A are excited by the potential difference between the drain 18B and the floating gate 12A coupled by the high voltage applied on the source 18A, and are injected into the floating gate 12A. That is, the program operation is performed by a hot carrier injection to the floating gate 12A.
In this case, a program coupling ratio (rp) can be represented by Equation 1 as follows:
                              r          p                =                              C1            +            C2                                C1            +            C2            +            C3            +            C4                                              [                  Equation                                                              1                ]
In Equation 1, 'C1', 'C2', 'C3', and 'C4' are the capacitance of the source capacitor (Cs), the capacitance of the channel capacitor (Cc), the capacitance of the tunnel capacitor (Ct), and the capacitance of the gate interlayer capacitor (Cip), respectively.
Further, in erasing the flash memory cell having the split gate structure, if a high voltage is applied on the control gate 16, and grounding voltages are applied on the source 18A and the drain 18B, the electrons charged in the floating gate 12A are removed to the control gate 16 by the high voltage applied on the control gate 16, that is, the electrons charged in the floating gate 12A are erased by the F-N (Fowler-Nordheim) tunneling effect.
In this case, an erase coupling ratio (rE) can be represented by Equation 2 with the capacitances (C1, C2, C3, C4) of the parasitic capacitors (Cs, Cc, Ct, Cip) as follows:
                              r          E                =                              C3            +            C4                                C1            +            C2            +            C3            +            C4                                              [                  Equation                                                              2                ]
The width 'W' of the poly oxide layer 14 is reduced with the increase in integration of the device. That is, as shown in FIG. 1B, when the width of the exposed polysilicon layer 12 is reduced, the width of the opening 13B, provided for the formation of the poly oxide layer 14, is reduced, and so, the thickness of the poly oxide layer 14, produced by the LOCOS process, is reduced. The reduction of the thickness of the poly oxide layer 14 increases the capacitance of the gate interlayer parasitic capacitor (Cip) between the control gate 16 and the floating gate 12A, thereby resulting in degradation of the device characteristics. That is, if the capacitance of the gate interlayer capacitor (Cip), generated between the floating gate 12A and the control gate 16, is increased, the voltage, applied on the floating gate 12A during programming, is reduced, thereby resulting in decreasing the program efficiency.

Methods of fabricating flash memory cell having split-gate structure using spacer oxidation process


A beverage bottle having fingergrip indentations which facilitate grasping and holding of the bottle without slipping. The location of the fingergrips in relation to a label bearing a brand name affords a high degree of brand name visibility in environments where consumption of the contents is directly from the bottle. Special geometry of the fingergrip indentations permits high speed filling of the bottles with beer without excessive turbulence and foaming.

The invention relates to a beverage bottle having fingergrips, and more particularly to a beer bottle having fingergrips which are specially adapted to permit high speed filling of the bottle without excessive beer foaming.
The typical beverage bottle consists of a hollow vessel with a narrow mouth for holding and carrying liquids. While not particularly designed to facilitate the consumer to drink the contents directly from the bottle, it has become increasingly popular in recent years for consumers to walk around holding the bottles and sipping the contents. Young people today are very active and very often drink their beverages while on the go, or in conversation standing up, or even while engaged in other physical activities.
Since the contents of a bottle is typically cold, such as cold beer or soda, condensation results in the formation of dew on the outside of the bottle. One of the drawbacks associated with drinking the contents directly from such a bottle is this dew which causes the bottle to become slippery. This problem is exacerbated when the beverage bottles are stored in an ice cooler where ice slush clings to the bottles as they are removed from the cooler.
In an attempt to solve this problem, beverage bottles have been provided with rough outer surfaces. For example, U.S. Pat. No. 3,403,804 and Design U.S. Pat. No. 308,335 describe beverage bottles whose outer surface is etched with a multiplicity of closely spaced ridges. Although the presence of such ridges improves the grip which one can apply on the bottle, slipperiness of the outer surface remains a problem. Furthermore, the presence of these ridges interferes with labelling of the bottle.
It is known to provide heavy jugs containing, for example, cider or wine with fingergrips to facilitate lifting and holding of the jug and the pouring of its contents. For example, Design U.S. Pat. No. 91,653 to Guyer illustrates a jug having four fingergrips on one side and a thumbgrip disposed on the opposite side of the jug. However, such fingergrips have not been provided for single serving beer bottles, which are slender and light compared to cider jugs.
One of the major problems which would have been encountered in providing fingergrips in beer bottles, if such an attempt were ever made prior to the present invention, is the excessive product foaming which occurs during conventional high speed filling of such bottles. In state of the art filling processes, air is drawn out of the bottle and beer is injected radially from a filling tube inserted in the top of the bottle. As the beer hits the inner surface of the bottle, it flows down the surface in an annular stream. During this process, some foam is generated, however, the amount of foam does not impede the process.
On the other hand, upon filling a beer bottle having fingergrip and thumbgrip indentations, such as those illustrated in the Guyer patent, excessive product foaming occurs which results in beer spewing out of the top of the bottle and an incomplete fill.


A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.

Semiconductor devices are typically interconnected by patterned electrically conductive layers of high conductivity metal or metal alloy, commonly referred to as interconnects or interconnect wires. Complex circuits require very close spacing of interconnect wires and multiple levels of metalization to interconnect the semiconductor devices. Interconnects are made by depositing and patterning alternating layers of a conductive material and layers of an insulating dielectric material. In multilevel interconnects, small holes or contact vias are formed through the dielectric layers and filled with conductive material to interconnect the conductive layers.
The interlevel dielectric material is typically SiO2, which has a dielectric constant, k, of about 4.0. Efforts have been made to replace the SiO2 dielectric with materials having lower dielectric constants. As used herein, a low dielectric material or low-k material means a material having a dielectric constant, k, of lower than about 3.5 and preferably lower than about 3. As used herein, a high dielectric material or high-k material means a material having a dielectric constant, k, of higher than about 3.5 and preferably about 4.0.
With today's more demanding circuit density, wirability, array-I/O architecture and receiver performance requirements, semiconductor chip performance is requiring the transition from Al to Cu interconnects because of the impact of interconnect RC delay on MOSFET gate delay analysis. The interconnect delay components become a larger percentage of the total CMOS gate delay as the intrinsic delay decreases and must be reduced either through interconnect resistance or capacitance reduction. Interconnect RC delay can be reduced by migrating from Al- to Cu-based interconnects, which improves electrical conductivity.
The transition from Al-to-Cu interconnects is not only important for semiconductor chip performance objectives, it is also important for ESD robustness in high-performance chips. Aluminum interconnects are a significant ESD failure mechanism in high-pin-count microprocessor chips. The migration from Al- to Cu-based interconnects achieved a two-fold improvement in critical current density-to-failure, Jcrit, in a SiO2 ILD. The Al-to-Cu technology migration path led to continuous ESD improvement, allowing for metal film thickness and line width scaling.
The interconnect component of gate RC delay can be further reduced (i.e. line to line capacitance) by using low-k materials instead of SiO2 ILD. Cu interconnects and low-k materials enable the semiconductor industry to meet signal-delay requirements down to at least 100 nm technology.
Low-k materials must also have low leakage, a low thermal coefficient of expansion, high breakdown voltage, low film stress, high cracking resistance and compatibility and integrability with Cu interconnects. Low-k materials include, for example, silicon oxyfluoride (FxSiOy), hydrogen silsequioxane (HSQ), organic polymers such as poly(arelene) ethers, benzoncyclobutene (BCB), nanoporous silica and porous polymers. Other low-k materials such as, for example, Silicon Low-k (SiLK) from Dow Chemical Corp., Midland, Mich., having suitable material properties, compatibility with Cu interconnects, and the desired electrical permittivity will be known to those skilled in the art.
From an ESD perspective, the thermal properties of low-k materials are key to understanding the ESD robustness of Cu interconnect systems and the scaling implications on ESD robustness. Low-k materials have different thermal and mechanical properties which are a significant deviation from SiO2 dielectrics. The mass density, thermal conductivity, and the specific heat all influence the thermal characteristics of the ILD through the thermal resistance and thermal capacity. Models have been developed for determining the power-to-failure and critical-current-density-to-failure in the thermal diffusion time scale for various interconnect structures, as described in S. Voldman et al., "High-Current Characterization of Dual-Damascene Copper Interconnects in SiO2 and Low-k Interlevel Dielectrics for Advanced CMOS Semiconductor Technologies," International Reliablity Physics Symposium, Mar. 22, 1999.
The trend in the industry, especially with integrated circuits, has been to use low-k materials near the interconnect wires to improve the performance of the circuit. For example, U.S. Pat. Nos. 5,744,865 and 5,821,621 disclose interconnect structures having a low-k material placed between the multiple wires of the interconnect. The low-k material reduces the capacitance of the interconnect and helps reduce crosstalk noise between adjacent wires carrying different signals from different pads. However, the interconnects surrounded by low-k materials are not well suited for applications where ESD robustness is more important than performance, such as interconnects between pads and ESD devices or other devices for discharging or sinking a current. Such applications are the focus of the present invention.

Interconnect structure encased with high and low k interlevel dielectrics

International Business Machines Corporation


In forming a layer of a semiconductor wafer, a dielectric layer is deposited on the semiconductor wafer. The dielectric layer includes material having a low dielectric constant. Recessed and non-recessed areas are formed in the dielectric layer. A metal layer is deposited on the dielectric layer to fill the recessed areas and cover the non-recessed areas. The metal layer is then electropolished to remove the metal layer covering the non-recessed areas while maintaining the metal layer in the recessed areas.

1. Field of the Invention
The present invention generally relates to interconnections within layers of a semiconductor wafer. More particularly, the present invention relates to interconnections in low-K dielectric materials and ultra low-K dielectric materials.
2. Description of the Related Art
In general, semiconductor devices are manufactured or fabricated on disks of semiconducting materials called wafers or slices. More particularly, wafers are initially sliced from a silicon ingot. The wafers then undergo multiple masking, etching, and deposition processes to form the electronic circuitry of semiconductor devices.
During the past decades, the semiconductor industry has increased the power of semiconductor devices in accordance with Moore's law, which predicts that the power of semiconductor devices will double every 18 months. This increase in the power of semiconductor devices has been achieved in part by decreasing the feature size (i.e., the smallest dimension present on a device) of these semiconductor devices. In fact, the feature size of semiconductor devices has quickly gone from 0.35 microns to 0.25 microns, and now to 0.18 microns. Undoubtedly, this trend toward smaller semiconductor devices is likely to proceed well beyond the sub-0.18 micron stage.
However, one potential limiting factor to developing more powerful semiconductor devices is the increasing signal delays at the interconnections (the lines of conductors, which connect elements of a single semiconductor device and/or connect any number of semiconductor devices together). As the feature size of semiconductor devices has decreased, the density of interconnections on the devices has increased. The closer proximity of interconnections, however, increases the line-to-line capacitance of the interconnections, which results in greater signal delay at the interconnections. In general, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays have been found to decrease linearly with the reduction in feature size. As such, there is generally a net increase in overall delays with a reduction in feature size.
One conventional approach to compensate for this increase in interconnection delay has been to add more layers of metal. However, this approach has the disadvantage of increasing production costs associated with forming the additional layers of metal. Furthermore, these additional layers of metal generate additional heat, which can be adverse to both chip performance and reliability.
An alternative approach to compensate for the increase in interconnection delay is to use dielectric materials having low dielectric constants (low-K dielectrics). However, because low-K dielectric materials have porous microstructures, they also have lower mechanical integrity and thermal conductivity than other dielectric materials. Consequently, low-K dielectric materials typically cannot sustain the stress and pressure applied to them during a conventional damascene process.
In a conventional damascene process, metal is patterned within canal-like trenches and/or via. The deposited metal is then typically polished back using chemical mechanical polishing (CMP). In general, depending on the interconnection structure design, anywhere from half a micron to 1.5 millimeters of metal can be polished.
However, when metal is patterned within trenches and/or via of a low-K dielectric material, and then polished back using CMP, the low-K dielectric material can fracture or pull away from the metal within the trenches and/or via due to the stress and pressure of CMP. Consequently, strong or rigid structures have been formed within the low-K dielectric materials to help them sustain the stress and pressure applied during CMP. However, building such structures within the low-K dielectric materials can be costly and can increase the interconnection delays within the device that the low-K dielectric materials were intended to reduce.

Integrating metal layers with ultra low-K dielectrics


Disclosed is a vehicle lamp capable of improving a production efficiency, reducing a cost, and shortening a production line as compared to a case in which a dedicated mechanical equipment is used. The vehicle lamp includes an optical unit, a pivot member fixed to a bracket of the optical unit, a lamp body having a bearing insertion hole, and a bearing member which is fixed to the lamp body to be engageable with the pivot member. The pivot member and the bearing member are engaged with each other to constitute at least one supporting unit of an aiming mechanism. In addition, the optical unit is tiltably supported by the aiming mechanism and the bearing member is fixed to the lamp body by being inserted into the bearing insertion hole.

A conventional vehicle lamp has been provided with an aiming mechanism configured to adjust an optical axis of irradiation light. For example, Japanese Utility Model Laid-Open Publication S64-019205 discloses a vehicle lamp that is provided with an aiming fulcrum pivot as an aiming mechanism in which an angle of a reflector is adjusted by the aiming fulcrum pivot to perform aiming adjustment.


According to one embodiment, an electronic apparatus, includes a sensor-equipped display device includes a display device and a sensor configured to detect a contact or proximate position, a display driver configured to output an image display signal to the display device and to output a drive signal to the sensor, a detecting circuit configured to generate, based on the information from the sensor, raw data (Raw data) including three-dimensional information of coordinates of a position on the display device and a physical quantity at the coordinates, and an application processor configured to discriminate whether a part of the region in the display area should be further sensed or not, based on the raw data, and if the part of the region is further sensed, to output the range of the display device to be further sensed and the timing of driving the sensor to the display driver.

Cellphones, smartphones, tablet terminals, notebook-type personal computers, etc. have been widespread. Such an electronic apparatus comprises an input panel integrated with a display panel. When a user touches, for example, a display screen, the input panel detects the touched position. The input panel comprises, for example, a sensor configured to detect variation in capacitance.

Electronic apparatus and method of controlling the same


The embodiments of the present invention generally relate to or provide a counting apparatus for use with the art of hand knitting. Various embodiments of the present invention can provide, by way of one example, a knitting counter that can maintain multiple counts at the same time. By way of a further example, embodiments of the present invention can provide a knitting counter that can maintain multiple counts numbering at least eleven.

Conventional counting devices for the art of hand knitting are designed to count rows in a pattern; thus, they generally consist of an apparatus that displays two digits side by side. Each digit can be one of a range of ten numerals from 0 to 9, inclusive. The first digit, shown on the left, represents the tens column of a number; and the second digit, shown on the right, represents the ones column of a number. Using these two digits, a conventional knitting counter can display one number from 0 to 99, inclusive. One such example of a conventional knitting counter is the "Circular Row Counter" from Boye; another such example is the "Knitting Counter 'Kacha-Kacha'" from Clover.
Notwithstanding these conventional counters, however, most patterns do not provide users with instructions by row number, from start to finish. Instead, most patterns instruct users to undertake several actions, often at the same time, for a specified (but limited) number of repeats. A repeat can be a row, but it need not be. An instruction might read, for example, "Work the increase in Row 11 at each end of every 12th row 5 more times, continuing to work Rows 1 through 24 of Cable Pattern A as established." In this instruction, the first repeat consists of rows between and including increase rows; the second repeat consists of the number of increase rows worked; and the third repeat consists of the rows in Cable Pattern A. In the foregoing example, as in the substantial majority of patterns, the repeats do not exceed 36, but the pattern asks a user to count several repeats at once. Conventional counting devices thus are not helpful for following patterns that include a repeating count. First, because they use only the numerals 0 through 9, conventional counting devices require two digits to express any number exceeding 9. Second, because they display only two digits, conventional counting devices do not provide users with the ability to display more than one number exceeding 9. Third, as a consequence, conventional counters do not provide users with the ability to count a first repeat exceeding 9 while also counting a second or third repeat that exceeds 9. Again, many patterns require users to maintain multiple counts at the same time.
Accordingly, there is a need in the art for a counting apparatus for knitting that can maintain multiple counts at the same time. There is a further need in the art for a counting apparatus that can maintain multiple counts for at least the numbers 1 through 36.


Presented herein are non-disruptive noise estimation techniques that utilize a correlation between attributes of a received signal and the noise to generate estimated noise values for symbols of the signal. More specifically, a digital signal comprising symbols transmitted over a telecommunications network is received. For each of a plurality of the symbols, an estimated noise value associated with the respective symbol is generated through a correlation of a log-likelihood ratio (LLR) value to predetermined noise values. The estimated noise values for the plurality of symbols are used to generate noise information representing time and frequency characteristics of noise in the telecommunications network.

A Hybrid Fiber Coaxial (HFC) network is a telecommunications network that uses optical fiber cables and coaxial cables in different portions of the network to carry content (e.g., video, data, voice, etc.). For example, a Multiple System Operator (MSO) may install (or have installed) fiber optic cable from the distribution center (head-end facility) to intermediate nodes located close to a large number of users. From these intermediate nodes, coaxial cable may extend to individual businesses, residences, or other locations. A HFC network may be advantageous in that features of fiber optic cable (e.g., high bandwidth, low noise/interference susceptibility, etc.) can be utilized to reach points close to the users without having to install fiber optic cables to individual locations.
In general, messages/data are transmitted from a transmitting device to a receiving device over an HFC communication channel. Noise may be inherently present within such a communication channel. The transmission of messages over a noisy communication channel often involves some type of forward error checking/correcting process in order to reduce or eliminate noise induced errors at the receiving device.

Non-disruptive network noise measurement


A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j−1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.

An electrostatic discharge (ESD) protection element comprising diodes or resistance elements is used conventionally to protect the circuit elements in a semiconductor integrated circuit against ESD. Recently, ESD protection elements provided in a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit have come to be replaced by MOS-type protection elements that utilize a parasitic bipolar operation and exhibit a lower resistance and a higher discharge capability than ESD protection elements comprising diodes or resistance elements. Such a MOS-type protection element is one that utilizes the snapback phenomenon of a MOSFET (MOS Field-Effect Transistor).
The ability to pass electric current is limited even in a MOS protection element that relies upon a parasitic bipolar device. In many cases protection performance will not meet the required level unless the width of the protection element is enlarged to 400 to 800 μm. In an integrated circuit, however, the arrangement of bonding pads usually imposes a limitation upon layout and often the MOS protection element must be made to fit in a stipulated area. For this reason, a method adopted in the art is to employ not a MOS protection element consisting of a single element but rather one having a plurality of small MOSFETs referred to as fingers having a width of 10 to 50 μm, arranging them in a direction (e.g., the horizontal direction) perpendicular to the direction of current flow, connecting them in parallel with one another and arranging the elements in the stipulated area in an efficient manner. To achieve this, one method is to commonly connect the sources and drains of the fingers to thereby connect the plurality of fingers in parallel with one another, and another method is to array small MOSFETs individually and connect them in parallel with one another (see Non-Patent Document 1, namely Tong Li, Ching-Han Tsai, Elyse Rosenbaum and Sung-Mo Kang, "Substrate resistance modeling and circuit-level stimulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998, 6–8 Oct. 1998, pp. 281–289).
FIG. 15 is a plan view illustrating an input protection element 101 that utilizes the snapback phenomenon of an NMOSFET, which is a conventional MOS-type projection element, FIG. 16 is a diagram illustrating a cross section taken along line A–A′ in FIG. 15 as well as an equivalent circuit thereof, and FIG. 17 a graph illustrating the operating characteristic of this MOS-type protection element, in which voltage applied to the protection element is plotted along the horizontal axis and current that flows into the protection element is plotted along the vertical axis. In the MOS-type protection element 101, a plurality of gate electrodes 103 extending in one direction are provided in parallel above a P-type substrate 102, and regions directly underlying the gate electrodes 103 in the surface of the P-type substrate 102 serve as channel regions 104. The areas between the channel regions 104 in the surface of the P-type substrate 102 define source regions 105 or drain regions 106, and the source regions 105 and drain regions 106 are arrayed in alternating fashion.
As a result of this structure, a plurality of MOSFETs 111 are formed and the source regions or drain regions of mutually adjacent MOSFETs 111 are connected in common. A plurality of contacts 107 are arrayed in a single row on the surface of respective ones of the source regions 105 and drain regions 106 in a direction along which the gate electrodes 103 extend. A guard ring 108 comprising a heavily doped p+ is provided in the surface of the P-type substrate 102 so as to surround the plurality of MOSFETs 111 and is connected to a ground wiring 109. The guard ring 108 is provided for the purpose of preventing latch-up. An input pad 110 is connected to the contact 107 formed on the surface of the drain region 106.
Referring to FIGS. 15 to 17, the operation of the MOS protection element 101 is described. When a surge current enters the input pad 110, the surge current flows into the drain region 106 via the contact 107, thereby raising the drain voltage. If the drain voltage exceeds the voltage indicated at Vt0 in FIG. 17, avalanche breakdown begins at the PN junction between the drain region 106 and channel region 104 and a substrate current flows. At this time a parasitic bipolar transistor is formed in which the source region 105 of each finger is the emitter, the P-type substrate 102, inclusive of the guard ring 108, is the base and the drain region 106 is the collector. Owing to the current that flows through the interior of the P-type substrate 102, a potential difference corresponding to the product of this current and the resistance of the P-type substrate 102 is produced in the P-type substrate 102 and the potential in the vicinity of the bottom surface of the source region 105 in the P-type substrate 102 rises relative to the guard ring 108. When the voltage applied to the MOS protection element 101 reaches Vt1, as shown in FIG. 17, the potential in the vicinity of the bottom surface of the source region 105 relative to the guard ring 108 becomes large enough, e.g., 0.7 V, to forward bias the PN junction between the source region 105 and channel region 104. The PN junction thus is forward-biased, a further current flows and a state of low resistance is obtained owing to conduction of the parasitic bipolar transistor. As a result, a larger current flows. This phenomenon is referred to as snapback, and the voltage Vt1 is referred to as snapback starting voltage or trigger voltage.
If it is attempted to perform an I-V measurement of the kind shown in FIG. 17 by means of an ordinary current-voltage measuring apparatus, measurement requires application of current for an extended period of time. Consequently, the DUT (Device Under Test) will be destroyed before the snapback state is attained. To measure the snapback phenomenon, therefore, usually a measurement apparatus referred to as a TLP (Transmission Line Pulser) is employed. This apparatus subjects the DUT to a rectangular current waveform having a duration on the order of 100 ns and reads the values of current and voltage of the DUT from a change in the voltage and current thereof. (By way of example, see Non-Patent Document 2, namely Barth, J. et al, "TLP calibration, correlation, standards, and new techniques [ESD test]", Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 85–96.) In general, V=It2×1500 has been experimentally determined to be the relationship between breakdown current It2 [A] of a DUT measured with a TLP and breakdown voltage V [V] of the DUT measured by a human body model (HBM) test.
Non-Patent Document 3 (Christian Russ, Karlheinz Bock, et al., "Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998 pp. 177–186) states that since avalanche current is highly dependent upon the electric field applied to a PN junction, there is a high probability that snapback will occur in a MOS transistor from a corner where the electric field is strongest.
Further, Non-Patent Document 4 (Kwang-hoon Oh, et al., "Non-Uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design", IEEE 01CH37167.39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001 pp. 226–234) reports that in a process that uses a low-resistance substrate, there are instances where snapback occurs locally at random locations in a finger owing to statistical variations in the process.
In a single-finger protection element, as described above, a problem is that the element tends to be destroyed owing to current crowding. Further, there are instances where snapback voltage is too high and instances where breakdown occurs owing to application of excessive current to the element's own gate electrode. The inventions described in Patent Documents 3 and 4 (Japanese Patent No. 3157614 and Japanese Patent Kokoku Publication No. JP-B-8-24183, respectively) are inventions relating to such cases.
In Patent Document 3, as shown in FIG. 30, the impurity-doped region of a source area is provided with a resistor, and a gate electrode is connected to ground potential via this resistor, thereby preventing an excessive voltage from being impressed upon the gate voltage of the transistor.
As shown in FIG. 31, Patent Document 4 describes a structure in which the occurrence of electrostatic breakdown is prevented by forming notches in both sides of a source to thereby provide resistance and lowering the peak voltage of electrostatic stress at the boundary points between a field oxide film, gate electrode and source region or drain region where an electric field ascribable to application of static electricity tends to occur.
A MOS-type protection element comprising a plurality of fingers (namely a multifinger-type protection element) has the following problem: In multifingers, operation differs from finger to finger. This difference in operation can be explained as being ascribable to a difference in substrate resistance. More specifically, since the distance to the ground electrode (usually the guard ring) as seen from each finger differs, the substrate resistances, namely the base resistances of the parasitic bipolar transistors, differ from one another. As a result, owing to accumulation of electric charge after avalanche breakdown, a difference develops in the local voltage formed at the junction region between the source region and channel region of each MOSFET. Accordingly, the timings at which the parasitic bipolar transistors reach the snapback voltage differ and the timings at which the parasitic bipolar transistors turns on differ. In actuality, as shown in FIGS. 15 and 16, substrate potential is coupled to the substrate currents of the fingers and the substrate resistance differs depending upon the three-dimensional current route in each finger and the lateral substrate resistances within the fingers. Thus, the causes that lead to a difference is substrate resistance between fingers include complicated factors.
If a current flows into the PN junction on the drain side of a finger, namely the PN junction between the drain and channel regions, the potential difference at this PN junction comprises the major part of the potential difference within the finger and heat is therefore produced, mainly in the region of the PN junction. There is a positive correlation between the current and the junction temperature; the higher the temperature, the greater the current. In other words, if current concentrates in some of the fingers owing to process variations and structure, or if there are statistical variations in contact resistance and drain resistance within a finger and current concentrates in a specific finger or in a specific area of a finger, then this will trigger the occurrence of positive feedback in which the PN junction of the finger in which current has concentrated or in the specific region of the finger evolves heat, thereby raising the temperature and producing a further increase in amount of current. The heated portion will eventually melt. Consequently, the finger turned on first breaks down before other fingers are turned on, meaning that the advantages of the multifinger structure are not exploited.
A technique in which a protection element is provided with a trigger circuit to turn on a parasitic bipolar transistor in the protection element reliably has been disclosed (see Patent Document 1, namely U.S. Pat. No. 5,450,267). FIG. 18 is an equivalent circuit diagram illustrating this conventional protection element disclosed in Patent Document 1. As shown in FIG. 18, the conventional protection element is such that a current control switch 122 is connected to an input pad 121 into which a surge current flows. Further, the current control switch 122 is provided with an NMOS transistor 123 having its drain and source connected to the input pad 121 and to a ground electrode, respectively. The protection element is provided with a trigger circuit 124 in addition to the current control switch 122. The trigger circuit 124 is provided with an NMOS transistor 125 having its drain and source connected to the input pad 121 and to the gate of the NMOS transistor 123, respectively. When a surge current enters the input pad 121 of this conventional protection element, first the NMOS transistor 125 of the trigger circuit 124 turns on to apply a positive voltage to the gate of the NMOS transistor 123.
When the gate potential of the NMOS transistor 123 rises, a current starts flowing into the NMOS transistor 123, whereby avalanche breakdown tends to occur uniformly across the channel region. An advantage, therefore, is that snapback begins at a lower voltage.
As a result, NMOS 123 does not evolve heat locally, an excessively high voltage is not produced, safe turn-on is achieved and the surge current that entered the input pad 121 flows to the ground electrode.
However, the prior art described above involves the following difficulty: If the technique described in Patent Document 1 is applied to a protection element having a multifinger structure, e.g., if a trigger circuit is connected independently to each of the individual protection elements (fingers), there is the possibility that a protection element (an individual finger) will snap back and be destroyed by current crowding unless the device employs an arrangement in which the trigger circuit operates first (the present invention, described later, is equipped with such an arrangement).
On the other hand, if just one trigger circuit is provided and this single trigger circuit is connected to all of the multiple fingers, then, when only a specific finger snaps back, current will concentrate in this finger and it will be destroyed in a manner similar to the above.
A conceivable method of solving this problem is to connect the source of each finger to the gate of the neighboring finger (see Patent Document 2, namely U.S. Pat. No. 6,583,972). FIG. 19 is an equivalent circuit illustrating a multifinger-type protection element described in Patent Document 2, and FIG. 20 is a graph illustrating the operating characteristic of this MOS-type protection element, in which the voltage applied to the protection element and the current that flows into the protection element are plotted along the horizontal and vertical axes, respectively. In this protection element, as illustrated in FIGS. 19 and 20, n-number (where n is a natural number of 2 or greater) of fingers F1 to Fn are connected in parallel with one another between an input pad 131, to which ESD is applied, and a ground electrode 132. In each finger Fi (i=1 to n), a drain resistor Rdi (i=1 to n), NMOS transistor Ti (i=1 to n) and source resistor Rsi (i=1 to n) are connected in series in order from the input pad 131 to the ground electrode 132. The source resistor Rsk in the finger Fk [k=1 to (n−1)] is connected to the gate of NMOS transistor Tk+1 of the neighboring finger Fk+1. The source resistor Rsn of finger Fn is connected to the gate of NMOS transistor T1 of finger F1. Thus, all of the fingers are connected into a ring-shaped configuration as a whole.
When finger Fk snaps back, a current flows into source resistor RSk and a potential difference is produced. Since the intermediate point of the resistor Rsk is connected to the gate electrode of the neighboring finger Fk+1, the gate potential Gk+1 rises. Owing to the rise in gate potential, current begins to flow into the finger Fk+1. As a result, avalanche breakdown tends to occur uniformly across the channel region. This has the additional advantage of reducing the snapback voltage. Accordingly, the NMOS transistor Tk+1 of the neighboring finger Fk+1 turns on safely and finger Fk+1 snaps back. Owing to snapback of finger Fk+1, finger Fk+2 snaps back, and so on. When any single finger snaps back, all fingers snap back sequentially in a chain-like fashion. Thus, the method employed by this protection element is referred to as the "domino method" because all fingers snap back in a "domino effect" manner.
[Non-patent Document 1]
Tong Li, Ching-Han Tsai, Elyse Rosenbaum and Sung-Mo Kang, "Substrate resistance modeling and circuit-level stimulation of parasitic device coupling effects for CMOS I/O circuits under ESD stress", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998, 6–8 Oct. 1998, pp. 281–289
[Non-patent Document 2]
Barth, J. et al, "TLP calibration, correlation, standards, and new techniques [ESD test]", Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, 2000 pp. 85–96
[Non-patent Document 3]
Christian Russ, Karlheinz Bock, et al., "Non-Uniform Triggering of gg-nMOSt Investigated by Combined Emission Microscopy and Transmission Line Pulsing", Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1998 pp. 177–186
[Non-patent Document 4]
Kwang-hoon Oh, et al., "Non-Uniform Bipolar Conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design", IEEE 01CH37167.39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001 pp. 226–234
[Patent Document 1]
U.S. Pat. No. 5,450,267
[Patent Document 2]
U.S. Pat. No. 6,583,972
[Patent Document 3]
Japanese Patent No. 3157614
[Patent Document 4]
Japanese Patent Kokoku Publication No. JP-B-8-24183
In a MOS-type ESD protection element, as described earlier, usually the parasitic bipolar state that occurs locally in each finger spreads to all fingers, whereby all fingers attain a state of low resistance and snap back. As a result, ESD current can be caused to discharge stably. However, in a case where the parasitic bipolar state does not spread to all fingers, current concentrates in the region that that snapped back first in the fingers and this finger may be destroyed.
In the above-mentioned domino-type multifinger ESD protection element (Patent Document 2), the finger that snaps back first exhibits a snapback operation different from that of the other fingers that snap back sequentially thereafter because this finger has a gate potential that is ground potential. More specifically, in the finger that snaps back first, the parasitic bipolar state occurs locally in a region where the electric field at the drain end is strong. At this time current flows from the drain to the source of this MOS transistor but the gate potential thereof remains at ground potential. In other words, the circuit arrangement is such that in the finger that snaps back first, the electric field at the PN junction of the drain end is stronger than that of the other fingers; if a current flows, this electric field is strengthened further. Consequently, the parasitic bipolar state that occurs at the drain end does not readily spread to the regions of the other fingers and often current concentrates in the region in which the parasitic bipolar state occurred first.
By contrast, in the other fingers that snap back sequentially thereafter, the fact that the gate potential is initially elevated means that the parasitic bipolar state will readily spread to all fingers and a channel current will tend to flow uniformly over the entire region of fingers. As a result, all fingers attain the parasitic bipolar state and snap back substantially simultaneously. Thus, in the domino-type multifinger ESD protection element described above, a problem is that the finger that snaps back first tends to be destroyed.
In order to solve this problem, a method in which the gates of all fingers are connected together also is conceivable. FIG. 21 is a circuit diagram illustrating a conventional protection element in which the gates have thus been connected in common. As shown in FIG. 21, the gates of all fingers Fi (i=1 to n) of this conventional protection element are connected together and the respective sources of fingers are connected to the commonly connected gates via respective ones of diodes. As a result, when one finger has snapped back, the source potential of this finger rises, a voltage is applied to the gates of all fingers inclusive of this finger and all of the fingers snap back. With this method, however, there is an increase in the area of the layout because it is required that each finger be provided with a diode. Further, since all gates are interconnected, source potential is dispersed and eventually the highest electric potential is applied to the gate nearest the source whose potential has risen, namely the gate of the finger that has snapped back first. As a result, further current flows into the finger that snapped back first and current concentrates in this finger. In addition, in snapback of the other fingers, the fact that the operating speed of the diodes is slow means that the local current crowding in the finger that snapped back first cannot be suppressed and, hence, destruction of this finger cannot be prevented.
In a conventional multifinger MOS protection element having a shared source region (heavily doped n+ region), the snapback state is attained substantially simultaneously, in which the potentials at the base/collector PN junctions of each of the parasitic bipolar transistors affect one another via the substrate (P wells) owing to low resistance (i.e., as a result of substrate coupling). However, with the domino-type multifinger ESD protection element (see Patent Document 2), the multiple fingers are all such that their elements are isolated, as a result of which resistance rises and the effect of substrate coupling is diminished. This represents a problem.
Further, with the domino-type multifinger ESD protection element (see Patent Document 2), the source regions are split and a resistance element is inserted between the split source regions. A problem which arises is a larger layout area.
Accordingly, an object of the present invention is to provide a multifinger ESD protection element of reduced layout area in which it is possible to prevent destruction of a finger that snaps back first.

Multifinger-type electrostatic discharge protection element


This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.

FIG. 1 illustrates at 10 the concept of voltage boosting. The purpose of a voltage booster is to generate a specified voltage higher than VDD at node V-boosted, where VDD is the power supply voltage. A voltage booster basically contains two parts: a pre-charge circuit and a boosting capacitor (C boost). Before node Boost_Ctl is pulled to high, the pre-charge circuit charges node Ncb to some positive voltage. Then, node Boost_Ctl is pulled to VDD and switch S1 is turned on to charge load capacitor C_load to a voltage level above VDD. This boosted voltage level is determined by the voltage at node Ncb before Boost_Ctl goes high and the ratio of C_boost/C_load. The lower the pre-charged voltage at node Ncb, the larger the capacitance ratio is needed, and the larger the area cost for capacitor C_boost. Thus, it is best to pre-charge node Ncb to VDD before Boost_Ctl starts going high.
There are four ways known in the prior art of voltage boosters to pre-charge C_boost to VDD:                1) As shown in U.S. Pat. Nos. 5,999,461 and 4,186,436, when the boosted voltage is needed, the pre-charge circuit is enabled, but Boost_Ctl is not pulled to high until node Ncb is charged to VDD. Obviously, the major disadvantage is that some delay must be introduced. Thus, this scheme is not applicable to high speed devices.        2) As shown in U.S. Pat. Nos. 6,268,761 and 6,275,425, PMOS transistors are used to pre-charge node Ncb to VDD and keep the voltage at VDD during standby. The disadvantage is that the sizes of the PMOS transistors are huge when capacitor C_boost is large and pre-charging must be completed in a short time.        3) As shown in U.S. Pat. Nos. 5,175,448 and 5,636,115, NMOS transistors with their gate boosted above VDD are used to pre-charge node Ncb to VDD during standby. The advantage of using NMOS transistors is that the sizes of the transistors can be much smaller due to the higher drive capability of NMOSFET than PMOSFET. However, the voltage at node Ncb cannot be kept at VDD for a long time due to various leakages. When the voltage at node Ncb decreases, the size of capacitor C_boost must be increased in order to boost the voltage to the same level.        4) As shown in U.S. Pat. No. 5,701,096 charge pumps are used to continuously supply charge to capacitor C-boost and keep the voltage at some level. However, complex timing and control circuits must be introduced.
In one conventional memory application, a voltage booster is needed to boost the word line above VDD to VDD+Vthn, and the memory access time is about 11 ns. This means that there is no time for pre-charging the boosting capacitor after the chip is enabled, and the cycle time is about 20 ns. Thus, the boost capacitor must be quickly pre-charged to VDD as soon as the memory access is terminated. In the technique described in 3) above, the NMOS transistors are used as pre-charge devices. The boost capacitor is huge (60 pf) because the voltage on the booster capacitor decreases to a level below VDD due to the leakages. Furthermore, it takes a long time to pre-charge the boost capacitor to VDD due to the huge size.

This patent is subject to a terminal disclaimer.


A power converter has a transformer including a primary winding coupled to an input voltage, a secondary winding coupled to an output of the power converter, and an auxiliary winding is configured to detect an open connection fault of the auxiliary winding. The power converter includes a current source coupled to the auxiliary winding that, when activated, supplies a current to the auxiliary winding. A controller measures a voltage across the auxiliary winding. Responsive to detecting an increase in the voltage across the auxiliary winding while the current source is activated, the controller disables the power converter.

This disclosure relates generally to a switching power supply and more particularly to detecting open connection faults of an auxiliary winding in a switching mode power supply.
Many electronic devices, including smart phones, tablets, and portable computers, employ power supplies providing controlled and regulated power output over wide operating conditions. These power supplies often include a power stage for delivering electrical power from a power source to a load across a transformer. A switch in the power stage electrically couples or decouples the load to the power source, and a switch controller coupled to the switch controls on-time and off-time of the switch. Regulation of the power output can be accomplished by, among other things, measuring the output current or output voltage and feeding that back to the primary-side switch controller. In order to improve cost performance and reduce size, many commercially available isolated power supplies employ primary-only feedback and control.
In power supplies using primary-side feedback and control, an auxiliary winding provides a feedback signal to the switch controller. By sensing primary side signals, the controller detects the secondary output and load conditions in order to control and regulate the output of the power supply. However, if the auxiliary winding is faulty or disconnected from the power supply, the switch controller does not receive an accurate feedback signal. Without an accurate feedback signal, the controller may not maintain operation of the power supply within overvoltage limits, resulting in possible damage to the power supply or a load driven by the power supply. It is therefore important to detect open connection faults of the auxiliary winding prior to using the auxiliary winding to provide feedback to the switch controller.

Detecting open connection of auxiliary winding in a switching mode power supply


The present invention provides compositions and methods for the treatment of cardiovascular diseases. More particularly, the present invention relates to modifying thrombus formation by administering an agent which, inter alia, is capable of (1) selectively inactivating thrombin which is bound either to fibrin in a clot or to some other surface, but which has only minimal inhibitory activity against free thrombin, i.e., fluid-phase thrombin; (2) inhibiting the assembly of the intrinsic tenase complex, thereby inhibiting the activation of Factor X by Factor IXa; and (3) inhibiting the activation of Factor IX by Factor XIa. The compositions and methods of the present invention are particularly useful for preventing thrombosis in the circuit of cardiac bypass apparatus and in patients undergoing renal dialysis, and for treating patients suffering from or at risk of suffering from thrombus-related cardiovascular conditions, such as unstable angina, acute myocardial infarction (heart attack), cerebrovascular accidents (stroke), pulmonary embolism, deep vein thrombosis, arterial thrombosis, etc.

Blood coagulation is a process consisting of a complex interaction of various blood components, i.e., factors, which eventually gives rise to a fibrin clot. Generally, the blood components which participate in what has been referred to as the coagulation "cascade" are proenzymes or zymogens, i.e., enzymatically inactive proteins which are converted to proteolytic enzymes by the action of an activator which is, itself, an activated clotting factor. Coagulation factors that have undergone such a conversion are generally referred to as "active .alpha. factors," and are designated by the addition of a lower case "a" suffix (e.g., Factor VIIa).
Activated Factor X ("Xa") is required to convert prothrombin to thrombin, which then converts fibrinogen to fibrin as a final stage in forming a fibrin clot. There are two systems, i.e., pathways, that promote the activation of Factor X. The "intrinsic pathway" refers to those reactions that lead to thrombin formation through utilization of factors present only in plasma. A series of protease-mediated reactions ultimately generates Factor IXa which, in conjunction with Factor VIIIa, cleaves Factor X into Xa. An identical proteolysis is effected by Factor VIIa and its co-factor, tissue factor, in the "extrinsic pathway" of blood coagulation. Tissue factor is a membrane bound protein and does not normally circulate in plasma. Upon vessel disruption, however, it can complex with Factor VII or Factor VIIa to catalyze Factor X activation or Factor IX activation in the presence of Ca.sup.2+ and phospholipid. While the relative importance of the two coagulation pathways in hemostasis is unclear, Factors IX activation by the Factor VIIa-tissue factor complex has, in recent years, been found to play a pivotal role in the initiation of the normal clotting response. However, Factor IX activation in response to tissue factor exposed at sites of vascular injury has also been implicated in thrombosis, a pathological manifestation of the clotting cascade in blood vessels.
Thrombosis, which can complicate rupture of an atherosclerotic plague, can cause partial or total occlusion of the affected blood vessel, thereby leading to a number of important cardiovascular complications, including unstable angina, acute myocardial infarction (heart attack), or cerebral vascular accidents (stroke). Vessel injury and/or stasis can trigger venous thrombosis causing deep vein thrombosis and subsequent pulmonary embolism. Such diseases are a major cause of disability and mortality throughout the world, but particularly in Western societies. Moreover, thrombin and, in particular, surface-bound thrombin plays a role in thrombus formation in cardiac bypass circuits, after angioplasty and during and after thrombolytic therapy for acute myocardial infarction. Therefore, patients undergoing these procedures must be treated with very high doses of anticoagulants or antithrombin agents. Although high doses of these agents may effectively prevent clotting, they can give rise to serious bleeding complications.
The clot or thrombus, which forms as a result of activation of the clotting cascade, contains fibrin, platelets and numerous other blood components. Thrombin bound to fibrin remains active and causes growth of the clot by continued cleavage of fibrinogen and activation of platelets and other coagulation factors, such as Factor V and factor VIII. Moreover, unlike free thrombin which is readily inactivated by naturally occurring anti-thrombins (e.g., antithrombin III (ATIII)), clot-bound thrombin is protected from inactivation. As a result, the clot acts as a reservoir for active thrombin which triggers further clot growth. In addition, thrombin also induces smooth cell proliferation and, thus, may be involved in proliferative responses, such as graft-induced atherosclerosis and restenosis after angioplasty or atherectomy.
Because thrombin is critical to thrombus formation, the use of thrombin inhibitors for treating thrombosis and thrombotic complications has long been proposed. A number of partially effective inhibitors have been in use for years. Heparin, for example, can be used as an anticoagulant and antithrombin agent to inhibit fibrin formation, platelet aggregation and thrombus formation. Heparin, however, has a number of limitations. For example, it has biophysical limitations because it acts as an anticoagulant by activating ATIII and, thus, it is relatively ineffective at inactivating fibrin-bound thrombin at safe doses, thereby allowing the continued growth of thrombus mediated by thrombin bound to fibrin in the pre-existing thrombus. In addition, the doses required to produce an antithrombotic effect are quite unpredictable and, therefore, the dosage must be monitored closely. Low molecular weight heparins (LMWHs) can also be used as anticoagulants and anti-thrombin agents to inhibit fibrin formation, platelet aggregation and thrombus formation. LMWHs act by activating ATIII and, as such, have the same biophysical limitations as heparin. However, LMWHs produce a more predictable anticoagulant effect than heparin. Thus, both heparin and LMWH have the limitation of not readily inactivating surface-bound thrombin. The consequences of this are (a) high concentrations are needed to achieve an anti-thrombin effect which can lead to excessive bleeding, and (b) once the agents are cleared from the circulation, the surface-bound thrombin can reactivate clotting.
Inactivation of clot-bound thrombin may be achieved with another set of compounds known as direct thrombin inhibitors. Such inhibitors include hirudin and its derivatives, and inhibitors of the active site of thrombin, such as argatroban and PPACK (D-phenylalanyl-L-propyl-L-arginyl chloromethyl ketone). Hirudin is an anti-thrombin substance extracted from the salivary glands of leeches. Related compounds include hirulog which is a small, synthetic analog of hirudin. While these drugs are able to inhibit clot-bound thrombin, they have the following limitations. First, they do not typically inactivate clot-bound thrombin selectively, but do so at the same concentrations which are required to inhibit free thrombin. Secondly, their inactivation of thrombin is generally stoichiometric and, thus, unless very high concentrations are used, the inhibitory effect can be overcome by the large amounts of thrombin that are generated at sites where surface-bound thrombin accumulates (e.g., on bypass circuits, or at sites of arterial or venous thrombosis). As a result of the above two limitations, high concentrations of direct thrombin inhibitors (e.g., hirudin) must typically be administered to interact with and inhibit the free thrombin generated by clot-bound thrombin. Such high inhibitor concentrations can, however, cause unwanted bleeding. Moreover, direct thrombin inhibitors (e.g., hirudin, its analogs and small molecule active site thrombin inhibitors, such as argatroban) are generally reversible and, thus, their inhibitory effect is lost when the drugs are cleared from the blood. Unfortunately, this reversible inhibition can lead to rebound activation of coagulation.
In addition, inactivation of clot-bound thrombin may be achieved with a third class of compounds which bind reversibly or irreversibly to the active, i.e., catalytic, site of thrombin. PPACK is an example of an irreversible active site inhibitor. Such inhibitors, however, generally lack sufficient specificity for thrombin and, thus, have questionable safety. For example, PPACK also inactivates tissue type plasminogen activator, the major initiator of clot lysis. Thus, PPACK administration could trigger thrombosis by blocking the major pathway for clot degradation. Moreover, inhibitors such as PPACK have the same limitation as hirudin in that they typically have equal activity against clot-bound and free thrombin. This is problematic because evidence indicates that total inhibition of free thrombin using irreversible active site inhibitors may lead to excessive bleeding.
Moreover, other anticoagulant and antithrombin agents have been described in the literature. For instance, hirudin derivatives for blocking the active site of thrombin are described in U.S. Pat. Nos. 5,240,913 and 5,196,404. A bifunctional anti-thrombotic composition which includes both a glycoprotein IIb/IIIa inhibitory domain and a thrombin inhibitory domain is described in WO 92/10575. Peptide analogs of glycoprotein IIIa for thrombogenesis inhibition are described in WO 90/00178. Inhibitors of factor X and/or Xa are described in U.S. Pat. Nos. 5,239,058 and 5,189,019, and PCT publications WO 93/09803, WO 92/04378 and WO 92/01464. Inhibitors of factors VII and/or VIII are described in U.S. Pat. Nos. 5,223,427 and 5,023,236 and WO 92/06711. Platelet anti-adhesives and related antibodies are described in WO 92/08472. For a review of the structure and function of thrombin, see, Stubbs and Bode, Thrombosis Research 69:1-58 (1993).
In addition, numerous modified heparin compositions, as well as other glycosaminoglycans and their derivatives, have been developed. For example, U.S. Pat. Nos. 5,296,471, 5,280,016 and 5,314,876 describe the desulfation of heparin, periodate oxidation of heparin/heparan sulfates followed by reduction of resulting aldehyde groups, and high molecular mass N,O-sulfated heparosans, respectively. Low molecular weight heparin fractions have been used for several years (see, Boneu, et al., Thrombosis Research 40:81-89 (1985)). More recently, various dermatan sulfates have been developed and their interactions with heparin cofactor II studied (see, Mascellani, et al., Thrombosis Research 74:605-615 (1994), and Sheehan, et al., J. Biol. Chem. 289:32747-32751 (1994)). For a review of the limitations of heparin and the potential advantages of new anticoagulants as anti-thrombotics, see, Hirsh, Circ. 88:I-C (1993).
In view of the foregoing, there remains a need in the art for improved compositions and methods that are useful, for example, for inhibiting thrombogenesis associated with cardiovascular disease. An ideal antithrombotic agent would be one which can pacify the clot by inactivating fibrin-bound thrombin at concentrations which do not produce abnormal bleeding resulting from inhibition of thrombin production in the general circulation and/or which can selectively block the coagulation cascade at a desirable point. The present invention fulfills these and other needs.

Compositions and methods for inhibiting thrombogenesis

Hamilton Civic Hospitals Research Development Inc.


A snow plow blade includes a forward extending gate to catch snow rolling off the snow plow blade such as may form a snow ridge blocking drives, crosswalks and fire hydrants. The gate follows a trajectory forward from the curb edge of the plow blade to prevent catching the extension gate with the curb regardless of angulation of the plow blade or the degree of extension. The extension gate extension mechanism may be completely attached to the rear surface of the plow blade to operate independently of angulation of the plow blade.

The invention relates generally to snow plows for mounting on trucks and the like and specifically to a snow plow having a side gate controlling the off-flow of snow into abutting streets and driveways.
It is common practice to remove snow from streets through the use of an angled snow plow blade which channels snow from an area in front of a truck toward a curb side of the blade where the snow is deposited as a ridge running along the curb.
The angled plow, by spreading the removed snow in the ridge at the curb eliminates the need to haul the snow away. The snow ridge so formed at the side of the street is generally unobjectionable except where it blocks off adjoining streets, private drives or cross walks. The snow ridge may also cover fire hydrants. In these cases, time consuming and expensive additional steps must be taken to clear the blockage.
In order to prevent the formation of the snow ridge at certain points along the path of the snow plow blade, it is known to install a gate at the trailing edge of the snow plow blade. The gate may be closed to momentarily retain snow on the snow plow blade, stopping the formation of the offending snow ridge that may block streets or walks.
In one such approach, exemplified by U.S. Pat. No. 3,422,552, a side gate may be extended forward from the trailing edge of the main plow blade. Forward extension of this retaining gate allows the gate to immediately stop the small amount of snow flowing off the blade but to progressively handle the greater accumulation of snow over time as the side gate continues to extend forward. Likewise, as the gate is retracted in a rearward direction, the gradual retraction may evenly distribute the retained snow back into the ridge without dropping of a large block of snow in one location.
This forwardly extending side gate is not easily adapted to existing plow designs because it requires substantial additional mechanism to the side of the truck cab. Further, the side gate does not readily allow changes in angulation of the plow blade as may be required to adjust the plow to various snowfall conditions. Also, the tie rod 72 mounted to the front of the snowplow blade in U.S. Pat. No. 3,422,522 will break if the blade tips forward. Modern snowplow blades are designed to tip when they encounter road hazards such as utility hole covers, to avoid damage to the blade.


An information recording and/or reproducing apparatus, for performing recording and/or reproduction of information on a recording medium with a light beam emitted from an optical head, includes a vibration wave driving device for relatively moving the optical head to the medium, and a device for detecting information corresponding to a relation between a control signal for driving the vibration wave driving device and a relative movement velocity in the relative movement. The vibration wave driving device is controlled based on the information detected.

1. Field of the Invention
The present invention relates to an optical information recording and/or reproducing apparatus for optically recording or reproducing information by relatively translating an optical head to an optical information recording medium so as to scan information tracks in the recording medium with a light beam from the optical head. More particularly, the invention relates to an optical information recording and/or reproducing apparatus using a vibration wave driving device as means for moving the optical information recording medium and a vibration wave motor device capable of providing an output characteristic precisely irrespective of environmental changes.
2. Related Background Art
Recently, optical information recording and/or reproducing apparatus for optically recording or reproducing information with a light beam are drawing attention among information recording and/or reproducing apparatuses for recording or reproducing information on a recording medium. As the recording medium for optically recording or reproducing information there are those of a disk type, a card type, etc., among which card type recording media (hereinafter referred to as optical cards) are excellent in productivity, portability and accessibility and have a wide range of applications.
Information is recorded in the recording medium by scanning information tracks with a light beam of a fine spot modulated according to recording information, and is recorded in the form of information bit strings optically detectable.
On the other hand, information is reproduced from the recording medium by scanning the information bit strings on the information tracks with a light beam spot of constant power not enough to result in recording in the medium and then detecting reflected light or transmitted light from the recording medium.
The optical head used in recording or reproducing the information in or from the above recording medium is relatively movable with respect to the recording medium in directions along the information tracks and in directions traversing the information track directions, and movement of the optical head causes the light beam spot to scan the information tracks.
The optical head is provided with a converging lens for converging the light beam spot, an example of which is an objective lens. The objective lens is held so that it can move independently with respect to the optical head body in directions along the optical axis thereof (or in focusing directions) and in directions perpendicular to both the directions along the optical axis and the directions of the information tracks on the recording medium (or in tracking directions). Such holding of the objective lens is generally effected through an elastic member, and the movement of the objective lens in the two ways described above is generally driven by an actuator utilizing magnetic interaction.
FIG. 1 is a diagrammatic, plan view of a write-once optical card. There are a lot of information tracks 1001 arranged on an information recording surface of optical card 1000 in parallel in L-F directions. Also, a home position 1002 is provided as a reference position of access to the information tracks 1001 in the information recording surface of optical card 1000. The information tracks 1001 are arranged in the order of 1001-1, 1001-2, 1001-3, . . . from the side of home position 1002. Further, as shown in FIG. 2, there are tracking tracks 1003-1, 1003-2, 1003-3, . . . provided adjacent to the corresponding information tracks. These tracking tracks are used as a guide for autotracking (hereinafter referred to as AT) for controlling the beam spot so as not to depart from a selected information track during the scanning with the light beam spot in recording or reproducing information.
This AT control is performed using a servo system in the optical head, which is arranged so that deviation (AT error) of the above light beam spot from an information track is detected and this detected information is negatively fed back to a tracking actuator for driving the objective lens described above in the tracking directions, whereby the light beam spot is let to follow the desired information track while moving the objective lens relative to the optical head body in the tracking directions (along the D direction).
The AT control uses light spots of S.sub.1 and S.sub.3 and utilizes reflected light from tracking tracks on which the light spots S.sub.1, S.sub.3 impinge. Recording and/or reproduction of information is carried out using a light spot S.sub.2 located between the two light spots S.sub.1 and S.sub.3 The light spots S.sub.1, S.sub.2, S.sub.3 are obtained from a same light source so that they are formed at equal intervals with the light spot S.sub.2 between the light spots S.sub.1 and S.sub.3 by interference effect of a diffraction grating located between the light source and the objective lens.
While the information tracks are scanned with the light beam spot upon recording or reproducing information, autofocusing (hereinafter referred to as AF) control for the objective lens is carried out in order to shape (or focus) the light beam in a spot of an appropriate size on a recording surface of the optical card.
This AF control is carried out in such a manner that deviation (AF error) of the above light beam spot from an in-focus state is detected in the optical head, the thus detected signal is negatively fed back to a focusing actuator for moving the objective lens along the optical axis thereof, and the objective lens is moved relative to the optical head body in the focusing direction to focus the light beam spot on a recording surface of the optical card.
Meanwhile, as a method for relative scan between the light beam emitted from a semiconductor laser and the optical card, the optical card is mounted on a base (hereinafter referred to as a carriage), which is not movable in the directions along the tracks in the optical card but movable in the directions traversing the track directions, and the optical head body is moved using a voice coil motor in the directions parallel to the tracks on the optical card.
A vibration wave driving device (for example, an ultrasonic motor) is used for moving the carriage.
A first reason why the carriage is arranged to move in the directions perpendicular to (or traversing) the information tracks in the optical information recording and/or reproducing apparatus in the above structure is to enable access to another information track, and in this case, high-speed scanning is conducted in conventional apparatus while keeping the AT control in an off state.
A second reason is as follows. If there is deviation (hereinafter referred to as skew) as to parallelism between the tracks on the optical card and the scanning system in the track directions, for example in the case where the optical card is not regularly mounted on the carriage, and when the scanning in the track directions is performed while keeping the AT control in an on state, the objective lens is drive-controlled so as to be biased relative to the optical head body. There is, however, a limit in a biasing amount of the objective lens relative to the optical head body. Thus, the biasing amount could reach the limit during scanning in the length direction of the track. Therefore, the second reason is to keep the bias of the objective lens relative to the optical head body within a permissible range by moving (or relatively and finely moving) the carriage in the directions perpendicular to the tracks during scanning of light beam.
Here is briefly described the structure and the principle of driving of the vibration wave driving device.
A vibrator is formed by bonding a piezoelectric device which is an electricity-mechanical energy conversion element with an adhesive or the like to an elastic body made of a low-vibration-damping metal, for example an elastic body formed in an elongate oval shape, the vibrator is fixed to the back face or side surface of the carriage as described previously on the piezoelectric device side, and a straight portion on one side of a free end face of the elastic body is brought into press contact through a pressing means with a rail stator extending along the moving direction of the carriage.
The piezoelectric device includes piezoelectric device groups of two phases A and B separated at an odd multiple of a quarter wave from each other, and in each group there are formed piezoelectric devices different in polarizing-treatment direction in the thickness direction at intervals of .lambda./2. Then cyclic voltages such as alternating voltages with a phase difference of 90.degree. therebetween are applied to the piezoelectric device groups of the two phases A, B, whereby standing waves are oscillated by the respective piezoelectric device groups of the two phases A, B. The standing waves are synthesized to form traveling waves, which cause surface particles in the free end face of the elastic body to make an elliptical motion in a plane along the thickness direction, thereby moving the carriage by frictional drive against the stator.
FIGS. 3A to 3E are signal diagrams to show the operation of the above conventional example. FIG. 3A shows output signals from a lens position detecting circuit for detecting the position of the objective lens where the carriage with the optical card mounted thereon is moved by a short distance in the direction perpendicular to the tracks in an on state of tracking when the lens is located at distance m to the center position of lens. In this case, because the AT control is on, a motion of the objective lens relative to the optical head body becomes nearly equal to a motion of the carriage relative to the optical head body.
The vibration wave driving device starts moving the carriage at time t.sub.1 in the direction perpendicular to the tracks.
FIG. 3B shows an on-off signal of the vibration wave driving device, which is on in a time period between time t.sub.1 and time t.sub.4.
FIG. 3C is a drive voltage of the vibration wave driving device. The voltage is constant between time t.sub.1 and time t.sub.3 and the drive voltage is gradually decreased between time t.sub.3 and time t.sub.4 so as to decelerate to stop the carriage.
When the drive voltage of the vibration wave driving device is constant, the drive frequency determines a drive speed of the vibration wave driving device, that is, a velocity of the carriage (hereafter referred to as a carriage velocity) in the direction perpendicular to the tracks with respect to the optical head body. Here, FIG. 4 shows a relation of the carriage velocity v against the drive frequency f of the vibration wave driving device.
Let a state A (a curved solid line) represent a state in which the carriage velocity is V.sub.OA when the drive frequency of the vibration wave driving device is f.sub.0, as shown in FIG. 4. In FIG. 3A, the carriage starts moving at time t.sub.1, then the carriage velocity becomes approximately constant after the delay time t.sub.2, the carriage starts decelerating at time t.sub.3, and it stops at time t.sub.4. In this case, a moving distance of the objective lens relative to the optical head is m-n.sub.1.
Further, FIG. 3E shows the moving velocity of the objective lens and at the same time, indicates that the carriage velocity is approximately constant between time t.sub.2 and time t.sub.3.
FIG. 3D indicates the position of the light beam relative to the track (AT error) when the above carriage movement was performed. In FIG. 3D the solid line shows a change of AT error corresponding to the changes of the solid lines shown in FIG. 3A and FIG. 3E. As seen from FIG. 3D, the AT error becomes temporarily large upon the movement start of the carriage and again becomes large upon deceleration.
FIG. 5 is a structural drawing to show an example of the optical card recording and/or reproducing apparatus for recording or reproducing information in or from the optical card. In FIG. 5, reference numeral 200 designates the optical card being an information recording medium, and 201 the carriage on which the optical card 200 is mounted. The carriage 201 is arranged to be movable in the directions traversing the information tracks by drive of the vibration wave driving device (composed of a vibrator 202 and a carriage drive circuit). Numeral 202 denotes the vibrator. Numeral 203 represents the optical head in which a semiconductor laser as a light source and a photoelectric transducer are incorporated, 204 the objective lens provided on the optical head 203 to converge a light beam and to irradiate the optical card 200 therewith, 205 a comparator for comparing an information track intersecting signal output from the optical head 203 and inputting a result to MPU 206, 206 MPU for controlling the elements in the apparatus, 207 a carriage drive circuit for controlling the drive of vibrator 202 under a command from MPU 206, and 208 a lens position detecting circuit for outputting a deviation amount of objective lens 204 from the center position of optical head 203, output from the optical head 203, to MPU 206. Numeral 209 denotes a memory device for storing the voltage output to the carriage driving circuit 207 and the moving velocity of the carriage 201.
Here, suppose the light beam output from the optical head 203 is located on a certain information track on the optical card 200. A so-called seek control is performed in this case to move the light beam to another information track. If a target information track is outside a movable range of the objective lens 204 in the optical head 203, MPU 206 outputs a command to drive the vibrator 202 to the carriage driving circuit 207. The carriage driving circuit 207 outputs a drive voltage with a drive frequency and an amplitude preliminarily set in MPU 206 to the vibrator 202, thereby driving the carriage 201 with the optical card 200 mounted thereon. This relatively moves the information tracks on the optical card 200 in the information-track-traversing direction with respect to the light beam output through the objective lens 204, so that the optical head 203 outputs an information track intersecting signal through the comparator 205 to MPU 206 every time the light beam traverses an information track. When a number of input pulses from the comparator 205 reaches a target value, MPU 206 then outputs a command to stop the drive of vibrator 202 to the carriage driving circuit 207. Then the carriage driving circuit 207 stops the output of drive voltage so as to stop the carriage, thus completing movement of the light beam to the target information track.
Relative fine movement is next described. Suppose the optical card 200 has a skew angle .theta. as shown in FIG. 6. Let us consider a case that the objective lens 204 was moved relative to the optical head 203 to a left or right limit in the movable range from the center while the optical head 203 was kept in a scanning operation on an information track in an autotracking state. Since a current position of the objective lens 204 is input from the optical head 203 through the lens position detecting circuit 208 to MPU 206, MPU 206 judges from this signal that the objective lens is at the movable limit and gives the carriage drive circuit 207 such a command that the carriage drive circuit 207 should output to the vibrator 202 a drive voltage with such a drive frequency and an amplitude as to keep the moving velocity of carriage 201 slower than that in the seek control preliminarily set, thereby moving the carriage 201 so that the objective lens 204 is brought to the center of optical head 203. As soon as the information tracks on the optical card 200 start moving, the objective lens 204 also starts moving in the same direction because it is in the autotracking state. Since the position of objective lens 204 is input through the lens position detecting circuit 208 to MPU 206, a command to stop the output of drive voltage to the vibrator 202 is sent to the carriage drive circuit 207 when the objective lens 204 reaches the center position of optical head 203.
In this manner, correction is made in movement of the light beam to the information track and in positional relation between the light beam and the information track.
The relation between the drive frequency of the vibration wave driving device and the carriage velocity, however, is not constant because of machine differences, changes in environmental conditions such as the temperature or the humidity, changes with time, etc. Therefore, a same velocity would not be achieved even if drive is made at a constant drive frequency and a constant drive voltage.
The optical information recording and/or reproducing apparatus had such a problem that in the case of fine feed to move the carriage with the optical card mounted thereon in the direction perpendicular to the tracks in the tracking state with the AT control being on, for example if the moving speed of the carriage increases so as to make an AT error exceed a permissible value upon movement of carriage, the light beam deviates from a track to become incapable of recording or reproducing information, in turn causing track off.
Conversely, if the moving velocity of the carriage is too low, a moving amount per unit time becomes small, thereby failing to achieve a necessary moving amount.
Here, the state B shown by the dashed lines in FIGS. 3A-3E represents a case that the moving velocity of the carriage became higher in spite of the same drive frequency. FIG. 4 shows a case that the relation between the drive frequency (f) of the vibration wave driving device versus the velocity (v) changed from the state A to the state B because of machine differences, environmental conditions, changes with time, etc. Suppose the change is from the state A represented by the solid line on which the velocity v.sub.OA was attained by drive frequency f.sub.0 to the state B represented by the dashed line B on which the velocity v.sub.OB is obtained by drive frequency f.sub.0. When the vibration wave driving device is driven at the same drive frequency f.sub.0, the carriage starts moving at time t.sub.1 as in the state B shown by the dashed lines in FIGS. 3A-3E, the velocity becomes greater than that in the state A shown by the solid line, and the carriage starts decelerating at time t.sub.3 then to stop at a position of n.sub.2 at time t.sub.4. In this case, because the device is decelerated and stopped from the large velocity, the AT error becomes greater as shown in the state B represented by the dashed line in FIG. 3D as against that in the state A shown by the solid line. Therefore, there was a drawback that the deviation of the light beam relative to the track became greater, thereby making normal recording or reproduction impossible.
Since the seek operation requires a higher speed than in the fine feed operation of carriage, the carriage is driven at drive frequency f.sub.1 in the state A shown by the solid line in FIG. 4, thereby achieving a desired carriage velocity v.sub.1A. However, if the relation of drive frequency versus carriage velocity changes as shown in the state C shown by the chain line, the carriage velocity at drive frequency f.sub.1 is just v.sub.1C, thus failing to obtain a desired velocity. Therefore, there was a drawback that the necessary time for seek operation became longer.

Optical information recording and/or reproducing apparatus and method with vibration wave driving device or vibration driven motor device