The present invention discloses a method for forming a low biofouling filtration membrane. First, an ozone treatment is performed to a fluorine-based porous membrane to introduce peroxides on surface. Afterwards, a first grafting polymerization is initiated from the peroxides, and functional monomers are polymerized to introduce halide groups on surface. Finally, a second grafting polymerization is initiated from the halide groups, and macro-monomers are polymerized to introduce zwitterionic group on surface, so as to form the low biofouling filtration membrane.

1. Field of the Invention
The present invention is generally related to low biofouling filtration membranes, and more particularly to graft branched polymers or copolymers containing zwitterionic groups on fluorine-based filtration membranes or films for the purpose of anti-biofouling.
2. Description of the Prior Art
Proteinaceous biomolecules are highly complex, containing both hydrophilic and hydrophobic regions. These biomolecules are highly conformable and adaptable toward adsorption to surfaces having hydrophobic moieties thereat. Therefore, many hydrophilic surfaces are used to reduce protein adsorption. However, these surfaces are often not sufficient to prevent the undesirable adhesion of cells, bacteria, or other microorganisms. Even a small amount of proteins on a surface can lead to the adhesion and propagation of unwanted fouling. For example, fibrinogen adsorption less than 5-10 ng/cm2 is needed to inhibit platelet adhesion for blood compatibility, and superlow fouling surfaces are required for these applications.
However, only a few candidates are regarded as "nonfouling materials" or "superlow fouling materials". Poly(ethylene glycol) (PEG) or oligo(ethylene glycol) (OEG) modified surfaces have been extensively studied to resist protein adsorption. The steric exclusion effect was considered as one of the reasons for PEG polymers to resist protein adsorption. However, PEG or OEG group decomposes in the presence of oxygen and transition metal ions found in most biochemically relevant solutions.
Phophorylcholine (PC)-based polymers or surfaces have been shown to decrease protein adsorption. They are considered as biomimetic fouling-resistant materials since they contain phosphorylcholine headgroups, which are found in the outside layer of cell membranes. The hydration of PC-based materials is also thought to be the reason for their resistance to protein adsorption. However, it is desirable to develop new materials other than PC for applications requiring long-term material stability due to the tendency of the phosphoester group to be hydrolyzed. In addition, PC monomers, such as 2-methacryloyloxyethyl phosphorylcholine (MPC), are moisture sensitive and not easy to synthesize and handle.

Low biofouling filtration membranes and their forming method


A system for guiding a boat, which includes the boat and a remote server. The boat includes a central unit linked to a user interface, a receiver for receiving data transmitted by at least one electronic tag affixed to a device of the boat and to a radio device for bidirectional communication with the remote server. The central unit transmits information resulting from the data transmitted by the tags, the current position and the route plan of the boat via the radio device to the server, and receives route plan modification data, which are displayed on the user interface, from this server. In this way, the operator of the boat is able to gain knowledge of the movement of nearby craft and of possible collision risks. Further, the boat may include on-board connected objects that communicate with the central unit in order to determine whether devices are missing on board.

Nowadays, an increasingly substantial public indulges in the pleasure of recreational boating. Said activity procures a great pleasure and a strong feeling of freedom when the boat moves on the sea. But said leisure activity must remain safe and the occupants of a boat must not only learn to use same, but also know the environment of the sea to move there in complete safety. To avoid accidents, the boat is equipped with a number of devices, and first and foremost a radio communication means. Thanks to the radio, the skipper may communicate vocally with ground stations in order to know the weather forecasts (whereof the development of the wind and of the sea), the availability of a port, the possibility of refuelling. The skipper also has charts and/or a GPS system on board for finding his position. By knowing his position and by defining his point of arrival, the skipper traces a route plan that notably makes it possible to avoid obstacles, reefs for example.
The radio also makes it possible to launch distress calls to craft close by so that same come to your rescue. The skipper of the boat describes the criticality of its situation and communicates its position. The other craft may then divert in order to provide assistance to said boat. The radio also makes it possible for a skipper of a boat to warn the other craft of the presence of an obstacle at a certain place, an iceberg for example, and optionally indicate its movement.
In other less critical circumstances, the radio makes it possible to anticipate a need that will start to become apparent and risks compromising the continuation of the journey if it is not resolved. For example, the boat has a drinking water reserve that it is necessary to fill regularly, at risk of affecting the comfort of the passengers. Similarly, the refuelling must be provided by taking into account the route time to the next port. In the case of a motorboat, the tank must not become empty while the vessel is out at sea. All of said needs may be anticipated by radio communications in order to check that the products necessary for the continuation of the journey are indeed located on board.
If the boat is rented, the last person to take same must indicate to the renter its state and notably if important elements are missing (for example a life jacket). By indicating by radio that certain devices are missing or out of service, the renter may search for said elements so as to put same on the boat when said latter has returned to the port, and thus to make said boat more quickly operational for the next rental.
The boats may also be used during a race, in this case they are equipped with location beacons that permanently transmit signals to a ground server that may thus determine in real time the positions of competitors and determine who is in the lead.
Document JP-WO2004/019301 filed by ISHIKAWA HARIMA discloses the guiding of a craft according to a certain route plan, using mobile phones that communicate in real time the position of the craft to a ground server. The server transmits navigation orders to be performed in order to reach a certain position (the pier for example). Each craft may also communicate with the server that knows their respective positions and signals any collisions.
Document JP H06 325300 filed by TOKIMEC discloses a system for helping the craft to navigate in difficult atmospheric conditions, for example in fog, and to prevent collisions. The craft 20 communicate with satellites and a ground system and receive information to be displayed on a screen, whereof the trajectory of the boats that are close.
Document KR 2008/0086216 filed by RF TECKWIN describes a device for communication between on-board systems in craft and ground servers. The on-board system identifies the craft with a port authority and use in case of emergency, and transmits a distress signal in case of emergency.
All of said examples show the important role of the radio, but the communications are sometimes tedious for the skipper who must both concentrate on the navigation and hold a conversation.
All of said examples show the need to invent a new concept of management of the navigation for a boat that communicates automatically with the devices close by and advises its skipper on the action to take, by optionally proposing a new route plan.

System for guiding a connected boat equipped with an on-board system communicating with a remote server in order to modify its route plan


A method of forming perovskite thin films with micron-sized perovskite grains is provided. A layer of PbX2 in a solution containing a metal ion additive is applied to a structure. The structure with the PbX2 layer is annealed a first time. The PbX2 is exposed to CH3NH3X in a solvent. The structure with the exposed PbX2 layer is annealed a second time resulting in a CH3NH3PbX3 layer. X is selected from a group consisting of Cl, Br, I, CN, and SCN.

Field of the Invention
The present invention generally relates to growing perovskite film layers.
Description of the Related Art
Among different alternative energy technologies, thin-film photovoltaics (PV) hold great promise to provide cleaner and sustainable energy at a cost competitive with fossil fuels provided the associated material and fabrication costs for manufacturing such photovoltaic modules get substantially lower at reasonable efficiency levels. Current state-of-the-art commercial photovoltaic devices are produced in non-continuous batch-to-batch processes at high temperatures using high-vacuum deposition methods. The associated capital cost for such processes is enormous. The foundation of the next generation PV technology is believed to be based on solution-processing of device components. Solution processed methylammonium lead tri-halide (CH3NH3PbX3, X═Cl, Br, I) perovskite as a photoactive starting material is of particular interest due to its earth abundant nature, low temperature processability, favorable electronic properties, high photovoltaic power conversion efficiencies (PCEs), and low-cost roll-to-roll (R2R) coating compatibility on large area flexible substrates. However, the utility of this material system towards successful technology deployment will only be possible through the combined efforts of improved materials engineering, fine control of the photoactive layer morphology and integration into sophisticated device architectures.
Contemporary perovskite solar cells are based on two main device architectures; namely a mesostructured configuration and a thin-film planar heterojunction structure. In both cases, high PCEs have been achieved for small area devices. The construction of complex mesostructured device architectures require high-temperature sintering (>450° C.) for the formation of electron-transporting metal-oxide layers, such as mesoporous or compact TiO2, which limits their applicability on flexible roll-to-roll compatible plastic substrates. Thin-film planar heterojunction (PHJ) structures, with no mesoporous TiO2, are advantageous for high-throughput manufacturing in terms of their simple device configuration and low temperature processing. Several planar-heterojunction structures (p-i-n and n-i-p), which avoid the mesoporous scaffold and have different combinations of charge transporting interlayers, have been investigated by numerous research groups and the PCEs from these systems are on par with those utilizing a mesostructured configuration. Planar heterojunction p-i-n structures consisting of poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) as a hole-transport layer (p-type) and phenyl-C61-butyric acid methyl ester (PCBM) as an electron-transport layer (n-type) are promising due to their low-temperature solution processability, excellent bendability and tunable conductivity.
A typical perovskite based p-i-n planar heterojunction solar cell device fabrication starts using glass as a substrate, indium-doped tin oxide (ITO) as a transparent conductive oxide front contact and PEDOT:PSS as a hole-transport layer. Then the perovskite active layer is deposited on top of PEDOT:PSS, followed by a thin layer of PCBM as an electron acceptor and finally an aluminum (Al) metal layer as a cathode. At present, one of the main issues encountered in this device fabrication process is the fine control of film morphology during the deposition and crystallization of the perovskite layer. To avoid shunting in such planar structures, a homogeneous and pinhole-free perovskite layer is crucial. Besides surface coverage, the optimization of several other important material parameters, such as material crystallinity and grain structure, could lead to improved electronic properties of the perovskite films and thereby superior device performance.
Generally, the low temperature, solution processed, photovoltaic thin-film materials contain randomly oriented small grains with significant amount of grain boundaries. The presence of high density grain boundary regions creates traps and recombination centers for the charge carriers, and adversely affects the overall carrier transport properties. Accordingly, there is a need in the art for processes suitable for optimizing photoactive layer film morphology with large grains, while simultaneously minimizing the grain boundary regions, for reduced recombination of charge carriers.

Controlled crystallization to grow large grain organometal halide perovskite thin film

The United States of America represented by the Secretary of the Air Force


A method for operating a server to improve bandwidth efficiency in a computer network is disclosed. The server is operable to transmit files between a memory of the server and destinations on the computer network through a communication link having a finite bandwidth. The files are distinguishable by type and the server is provided with a rule set for prioritizing transmission of files by type. The method comprises monitoring a bandwidth usage of the communication link, and triggering application of the rule set when the bandwidth usage exceeds a threshold amount. The threshold amount is determined relative to the finite bandwidth. The method further comprises distinguishing between the files according to type, and prioritizing transmission of the files according to type and according to the rule set.

1. Field of the Invention
The present invention relates to a method and apparatus for improving bandwidth efficiency in a computer network. More specifically, this invention pertains to a bandwidth management tool that implements a set of rules for directing network traffic according to current network bandwidth levels.
2. Description of Related Art
Bandwidth is a critical resource and a key cost for Internet service providers (ISPs) in particular. Reliable bandwidth usage auditing and monitoring is important in two types of Web hostings offered by ISPs, i.e., "co-location" and "dedicated/shared-services. The Internet is a collection of interconnected (public and/or private) networks linked together by a set of standard protocols (such as TCP/IP and HTTP) to form a global, distributed network. As used herein, "Internet" is intended to refer to what is now commonly known as the Internet, it is also intended to encompass variations which may be made in the future, including changes and additions to existing standard protocols.
Bandwidth refers to maximum available bit rate for a specific application. In the context of a communication link of a computer network, bandwidth refers the maximum information rate that may be transmitted through the link. As used herein, the bandwidth capacity of a communication link includes any limitations such as arise from characteristics of servers, routers, and other network devices along a link.
Overuse of available bandwidth is generally undesirable. Although certain latency is inherently associated with any computer network (latency refers to the delay experienced by a packet from the source to destination), when bandwidth usage of a communication link approaches or saturates the bandwidth (capacity) of a communication link, increased latency and/or transmission failure results. Therefore, it is desirable to operate a computer network so as to preserve a margin of excess bandwidth at all times.
Bandwidth is also a commodity that may be assigned a definite economic value. In co-location services, a customer owns a dedicated Web server located at an Internet Service Provider's (ISP's) facility, and purchases Internet bandwidth from the ISP. The ISP buys bandwidth in bulk and resells it to each customer. Bandwidth is typically purchased in blocks. For example, a company may pay a fixed amount for a block of one hundred megabits of bandwidth. When bandwidth usage exceeds this amount, the company either incurs surcharges (in the event that it has acquired the ability to "burst" over the paid amount) or hits a cap, and is unable to serve all of the content that has been requested of it. The former results in undesired extra charges, with the latter results portions of the content being indiscriminately not served.
In dedicated-server service, customers rent dedicated servers that are owned and maintained by the ISP. In shared-server service, customers rent disk space, and share CPU and ETHERNET bandwidth with other website customers on the ISP's equipment. While this provides a low cost service for the customer, it frequently results in an overcrowding of the equipment and long delays or inaccessibility of the sites sharing the server. When the ISP has a clear picture of usage patterns, users can be relocated onto servers that do not clash with other users, or changed to dedicated-server service.
Accordingly, customers and ISP's alike desire accurate auditing, monitoring, and allocation of the bandwidth usage by each Web hosting customer. Current software tools for these tasks are not optimal.
The Web hosting business is becoming increasingly competitive. Customers are demanding guaranteed serviced and accountability for the access bandwidth charges by their ISPs. The customers too desire to monitor their own usage patterns in real time. It is further desirable to provide a guaranteed quality of service to improve customer satisfaction. In addition, unlike hit-rate data provided by other software, bandwidth usage patterns give web site owners a different way for gauging responses to changes in content on their sites.
A prior art pure-software approach to bandwidth management implements a priority-based queuing algorithm completely in UNIX or WINDOWS. These implementations usually have too much operating system overhead and throughput rarely exceeds 1,000 Kb/s. A prior art pure hardware approach implements a control algorithm in logic. But only very simple algorithms are practical, such as packet counting and dropping when a bandwidth limit is reached. These basic approaches can drop too many packets unnecessarily, which results in massive re-transmission on the Internet. Instead of improving throughput, these algorithms may actually degrade the network. A further disadvantages of hardware methods is that new features, e.g., Internet Protocol versions upgrades, generally require replacement of hardware equipment.
Routers are commonly used in the art and typically implement the use of headers and a forwarding table to determine the path in which data packets are sent. Very little filtering of data is done through routers. In fact, most routers do not distinguish between the different types of data being transmitted. Nevertheless, bandwidth management strategies are typically implemented at the router level. In networks where files of various types and sizes are frequently passed, however, these strategies are often inefficient.
Accordingly, it would be desirable to provide a method and apparatus for monitoring and optimizing bandwidth usage.

Method and apparatus for improving bandwidth efficiency in a computer network


A TFT with a drain-offset structure is provided, which realizes a high ON current while keeping an OFF current at a low level. This TFT includes a substrate and a patterned semiconductor film formed on a main surface of the substrate. At least the main surface of the substrate has an insulating property. The patterned semiconductor film is made of a silicon-system semiconductor material and is not monocrystalline. The patterned semiconductor film includes a source region of a first conductivity type, a channel region of a second conductivity type opposite to the first conductivity type, a first drain region of the first conductivity type, and a second drain region of the second conductivity type. The first drain region serves as an offset region. A gate electrode is formed to be opposite to the channel region through a gate insulating film. The source region is formed on one end of the semiconductor film. The second drain region is formed on an opposite end of the semiconductor film to the source region. The channel region is formed to be adjacent to the source region and the first drain region. The first drain region is formed to be adjacent to the channel region and the second drain region.

1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a Thin-Film Transistor (TFT) with the Lightly-Doped Offset (LDO) structure and a memory cell for a Static Random Access Memory (SRAM).
2. Description of the Prior Art
TFTs have been popularly used in the Liquid-Crystal Displays (LCDs) in which semiconductor circuits using the TFTs are formed on a glass substrate and the memory cell of SRAMs in which p-channel TFTs are used as load elements. The TFTs used in the LCDs are mainly formed by amorphous silicon and those used in the SRAMs are mainly formed by polycrystalline silicon (i.e., polysilicon). This material difference is due to the thermal process difference included in their fabrication sequences and the necessity of a high carrier mobility for the TFTs used in the SRAMs.
With the memory cell of the SRAMs, from the viewpoint of higher integration, it was advantageous that the load device is formed by a high resistance element. However, in recent years, the problems relating to leakage currents, noises, and .alpha.-ray-induced soft errors have been becoming obvious as the power supply voltage has been lowering with the progressing miniaturization. Thus, the configuration where a p-channel TFT is used as the load element of a memory cell of an SRAM has been becoming an important matter.
FIG. 19 shows a typical circuit configuration of a memory cell of an SRAM, in which six Metal-Oxide-Semiconductor (MOS) transistors are used.
As shown in FIG. 19, this memory cell is comprised of two n-channel access MOS transistors TA1 and TA2, two n-channel driver MOS transistors TD1 and TD2, and two p-channel load MOS transistors TL1 and TL2. The transistors TD1 and TL1 constitute a first inverter and the transistors TD2 and TL2 constitute a second inverter. The first and second inverters are cross-coupled at two nodes N1 and N2.
Source regions of the transistors TD1 and TD2 are connected to a ground line GND. Source regions of the transistors TL1 and TL2 are connected to a power supply line V.sub.DD. One of a pair of source/drain regions of the transistor TA1 and one of a pair of source/drain regions of the transistor TA2 are connected to a pair of bit lines BL1 and BL2, respectively. Another of the pair of source/drain regions of the transistor TA1 and another of the pair of source/drain regions of the transistor TA2 are connected to the nodes N1 and N2, respectively. Gate electrodes of the transistors TL1 and TL2 are connected to a common word line WL. The signals to be applied to the pair of bit lines BL1 and BL2 are opposite in phases.
When the electric potential at the node N1 is in a high level and the that at the node N2 is in a low level, the load transistor TL1 is in the ON (i.e., conductive) state and the load transistor TL2 is in the OFF (i.e., non-conductive) state. If the potential at the node N1 is temporarily lowered due to a leakage current, a noise, or an .alpha.-ray-induced electric charge, the ON-state of the transistor TL1 is strengthened to thereby supply electric charges to the node N1, recovering the potential lowering at the node N1.
The load transistors TL1 and TL2 have by far higher capabilities for supplying the electric charges to the nodes N1 and N2 than that of the high-resistance load element Therefore, the information or data value stored in the memory cell is difficult to be inverted. This lead to high stability of the memory cell.
The stand-by current of the SRAM is dependent upon the current flowing through the load transistor TL2 in the OFF state and the bit number.
If a p-channel TFT is used as the p-channel load transistor TL1 or TL2, this TFT needs to have both of a high current-driving capability (i.e., high ON current) and a low stand-by current (i.e., low OFF current). The high ON-current makes it possible to quickly raise the low node potential immediately after the data writing operation up to the power supply voltage, which is advantageous for high-speed operation.
To satisfy this requirement, the inventor and others reported an improved p-channel TFT having the Lightly-Doped Offset (LDO) structure, which was disclosed in Proceedings of 1991 Japan Applied Physics Society Spring Lecture-Meeting, p. 671, Lecture No. 30p-T-2, published in 1991. This p-channel TFT with the LDO structure is fabricated in the following way.
First, as shown in FIG. 1A, an insulating film 402 with a thickness of 100 to 800 nm is formed on a semiconductor substrate 401 by thermal oxidation or Chemical Vapor Deposition (CVD). The insulating film 402 is made of an oxide. After a gate electrode 404 with a thickness of 50 to 100 nm is formed on the insulating film 402, a gate insulating film 406, which is made of silicon dioxide and has a thickness of 5 to 20 nm, is formed on the insulating film 402 over the entire substrate 401 by Low-Pressure CVD (LPCVD). The gate electrode 404 is covered with the gate insulating film 406.
Further, an undoped polysilicon film (not shown) is formed on the gate insulating film 406 over the whole substrate by LPCVD. An n-type impurity such as phosphorus (P) is doped into this polysilicon film by ion-implantation until this polysilicon film has a doping concentration of 1.times.10.sup.15 to 1.times.10.sup.18 atoms/cm.sup.3. The impurity-doped polysilicon film is patterned to thereby form a patterned n.sup.- -type polysilicon film 411. The state at this stage is shown in FIG. 1A.
Subsequently, as shown in FIG. 1B, using a patterned photoresist film 426a as a mask, boron (as a p-type dopant) is selectively doped into the n.sup.- -type polysilicon film 411 by ion-implantation so that the implanted part of the n.sup.- -type polysilicon film 411 has a doping concentration of 1.times.10.sup.18 to 1.times.10.sup.19 atoms/cm.sup.3. Thus, a p.sup.- -type polysilicon region 415 is formed in the n.sup.- -type polysilicon film 411. The remaining part of the n.sup.- -type polysilicon film 411 serves as an n.sup.- -type polysilicon region 411a. The state at this stage is shown in FIG. 1B.
After the photoresist film 426a is then removed, as shown in FIG. 1C, using a patterned photoresist film 426b as a mask, boron (as a p-type dopant) is selectively doped into the p.sup.- -type polysilicon region 415 and the n.sup.- -type polysilicon region 411a. Thus, a p.sup.+ -type polysilicon region 416a is formed in the p.sup.- -type polysilicon region 415 and another p.sup.+ -type polysilicon region 416b is formed in the n.sup.- -type polysilicon region 411a. The p.sup.+ -type polysilicon regions 416a and 416b have doping concentrations of 1.times.10.sup.19 to 1.times.10.sup.21 atoms/cm.sup.3. The remaining part of the n.sup.- -type polysilicon region 411a serves as an n.sup.- -type polysilicon region 411aa. The state at this stage is shown in FIG. 1C.
Then, the photoresist film 426b is removed. Thus, the above-described p-channel TFT with the LDO structure is completed, as shown in FIG. 1D.
Following this, although not shown, an interlayer insulating film and a metallic wiring film are successively formed on the TFT by know processes.
This p-channel TFT with the LDO structure is of the bottom gate type. The p.sup.+ -type polysilicon region 416b, the n.sup.- -type polysilicon region 411a, and the p.sup.+ -type polysilicon region 416a serve as a source region, a channel region, and a drain region, respectively. The p.sup.+ -type polysilicon region 416a serving as the drain region is laterally shifted toward the right-hand side in FIG. 1D with respect to the gate electrode 404 by 0.1 to 0.6 .mu.m. In other words, the drain region 416a has an offset of 0.1 to 0.6 .mu.m with respect to the gate electrode 404. The p.sup.- -type polysilicon region 415a, which is located between the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a, constitute an offset region.
The p.sup.- -type polysilicon offset region 415a has an effect of decreasing the gradient of the dopant concentration between the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a. Not only the positional shift of the drain region 416a but also this gradient-decreasing effect will relax the electric field near the drain region 416a. Therefore, the OFF current of the p-channel TFT with the LDO structure is readily decreased to a low level compared with the simple offset structure where the offset region is formed by a same semiconductor as that of the channel region.
Further, since the p.sup.+ -type drain region 416a serves as the drain region, the parasitic resistance in the drain region is decreased. Thus, the ON current of the TFT with the LDO structure is readily increased compared with the simple offset structure.
The LDO structure may be applied to TFTs of the top gate type. Also, if the gate insulating film needs to have a sufficiently large thickness, a patterned p.sup.- -type polysilicon film having a lower doping concentration than the p.sup.- -type polysilicon film 415a may be used instead of the patterned n.sup.- -type polysilicon film 411.
Moreover, the LDO structure may be applied to the TFTs designed for LCDs where an amorphous polysilicon is mainly used for fabricating the TFTs. The LDO structure may be applied to n-channel TFTs.
As described above, with the conventional p-channel TFT with the LDO structure shown in FIG. 1D, the p.sup.- -type polysilicon region 415a located between the n.sup.- -type polysilicon channel region 411aa and the p.sup.+ -type polysilicon drain region 416a serves as the offset region. Due to the existence of the p.sup.- -type polysilicon offset region 415a, the ON current of the TFT with the LDO structure is greater in absolute value than that with the simple offset structure, and the OFF current of the TFT with the LDO structure is less in absolute value than that with the simple offset structure.
However, the conventional TFT with the LDO structure has the following problem.
The p.sup.- -type polysilicon offset region 415a needs to have a specific "offset length" allowing the Off current to decrease to a desired level, where the offset length is defined as the length from the drain-side edge of the n.sup.- -type channel region 411aa to the channel-side edge of the p.sup.+ -type drain region 416a. The p.sup.- -type polysilicon offset region 415a serves as a resistor serially-connected to the n.sup.- -type channel region 411aa and the p.sup.+ -type drain region 416a, which decreases the ON current. The resistance of this resistor varies as a function of the doping concentration of the p.sup.- -type polysilicon offset region 415a and the offset length. Therefore, if the doping concentration of the p.sup.- -type polysilicon offset region 415a is increased, the resistance of the resistor may be decreased. In this case, however, there arises a disadvantage that the OFF current is increased due to the electric-field increase near the channel-side edge of the drain region 416a.
Thus, with the conventional p-channel TFT with the LDO structure, the ON and OFF currents constitute an antinomy.
A similar antinomy exists in a memory cell of an SRAM using the conventional p-channel TFT with the LDO structure.
Specifically, if the length of the p.sup.- -type polysilicon offset region 415a (i.e., the offset length) is shortened and the doping concentration of the offset region 415a is raised, the ON current of the TFT will be increased. This enables the high-speed operation of the SRAM and stabilizes the operation of the TFT at a low power supply voltage. However, in this case, the stand-by current of the TFT is raised due to the increased ON current and as a result, it is difficult to reduce the electric power dissipation of the SRAM.
Also, the offset-length tends to fluctuate for the two p-channel TFTs in the memory cell during the photolithography process in the fabrication process sequence. Therefore, the operation of the memory cell tends to be unstable at a low power-supply voltage due to this offset-length fluctuation.

Thin-film transistor and SRAM memory cell equipped therewith


A method and system for determining a full open position of a closure member of a motor vehicle that articulates between an open position and a closed position includes a left pinch sensor coupled to the left side of the closure member for sensing a pinch condition on the left side of the closure member and generating a corresponding pinch signal. A right pinch sensor is coupled to the right side of the closure member for sensing a pinch condition on the right side of the closure member and generating a corresponding pinch signal. Left and right gas springs are coupled respectively to the left and right sides of the closure member for assisting in articulating the closure member and each of the gas struts has an extension at an end thereof for compressing their corresponding pinch sensor when the closure member is at its full open position.

In motor vehicles such as minivans, sport utility vehicles and the like, it has become common practice to provide the vehicle body with a large rear opening. A liftgate (also referred to as a tailgate) is typically mounted to the vehicle body with hinges for pivotal movement about a transversely extending axis between an open position and a closed position. The liftgate is operated either manually or electronically via a power drive mechanism including a reversible electric motor. For example, such arrangements are shown in commonly assigned U.S. Pat. Nos. 5,531,498; 5,563,483; and 5,448,856.
There are instances, however, when it is desirable to disable the power drive mechanism associated with the liftgate. For example, during power operation of a vehicle liftgate, the liftgate may unexpectedly encounter an obstacle in its path. It is therefore desirable to cease its powered movement in that event to prevent damage to the obstacle and/or the liftgate and its power drive mechanism. U.S. Pat. No. 6,297,605 discloses a powered liftgate system having a pinch sensor for causing the liftgate movement to stop upon sensing an encounter with an obstacle.
An electronic liftgate system also requires a full open switch in order to maintain a controlled opening and closing in situations where the liftgate was left open and an associated controller was put to sleep due to vehicle energy conservation. When the liftgate is closed, the closed position is known even after the controller goes to sleep since a latch switch is activated. However, when the liftgate is left open and the controller is put to sleep, the position memory is lost and the controller only knows that it is not in a closed position. This is important because when the position is known, the controller can slow down the operation of the liftgate just before full open and close to prevent the system from opening or closing too fast. In current systems, when the position memory has been lost, the liftgate is controlled to go to the full open position via a full open switch, identified by reference numeral 11 in FIG. 3. The switch 11 is mechanically activated just before full open position and triggers the controller to start its slow down for a controlled full open position.
Although full open switches and pinch sensors are available separately to identify full open position and to disable movement of the liftgate under pinch conditions, respectively, these components are typically packaged separately within the vehicle with an expense associated with each component. It is, thus, desirable to use the pinch sensor for sensing obstructions and providing indication of a full open position in a cost effective manner.

Method and system for determining full open position of a power liftgate


In a magnet system utilizing a pair of magnet bodies each having a cylindrical hollow, by effectively utilizing the hollow spaces of the magnet bodies, the ability of adjusting through magnetic shims the magnetic-field homogeneity of a homogeneous static-magnetic-field space region is enhanced. Two magnet bodies each incorporating a group of superconductive coils and each having a cylindrical hollow are arranged opposing each other; the first ring-shaped magnetic shim is arranged in the cylindrical hollow of the one magnet body, concentrically with the first group of superconductive coils; and the second ring-shaped magnetic shim is arranged inside the first ring-shaped magnetic shim, concentrically with the first group of superconductive coils. Moreover, the third ring-shaped magnetic shim is arranged in the cylindrical hollow of the other magnet body, concentrically with the second group of superconductive coils, and arranged opposing the first ring-shaped magnetic shim; and the fourth ring-shaped magnetic shim is arranged inside the third ring-shaped magnetic shim, concentrically with the second group of superconductive coils, and arranged opposing the second ring-shaped magnetic shim.

1. Field of the Invention
The present invention belongs to a technological field related to magnetic resonance imaging systems utilized for in-vivo imaging diagnosis, and relates to magnet systems utilized in magnetic resonance imaging systems. In particular, the present invention relates to enhancement of magnetic-field homogeneity in a homogeneous static-magnetic-field space region generated by a magnet system.
2. Description of the Related Art
Magnetic resonance imaging systems are roughly categorized in accordance with the shape of a magnet system into a cylindrical type and a facing type; in recent years, the facing type has become dominant. Facing-type magnetic resonance imaging systems form a sphere-shaped homogeneous static-magnetic-field space region between a pair of magnet bodies, and are superior to cylindrical-type systems in terms of the subject's feeling of not being confined and convenience for diagnosis-related staffs to walk around during a diagnosis. The strength of the magnetic field of a homogeneous static-magnetic-field space region in a facing-type magnetic resonance imaging system is 0.2 to 1.0 tesla, and a tolerance within a virtual sphere is normally several ppm. In addition, the size of a facing-type magnetic resonance imaging system is, for example, approximately 2 to 3 m in height and, in a plan view, approximately 2 m in maximal diameter. The weight of a facing-type magnetic resonance imaging system depends on the method of shielding magnetic field; for example, in the case where no magnet body is utilized, the weight is approximately 10 t.
In facing-type magnetic resonance imaging systems as described above, it is important to secure the magnetic-field homogeneity of a homogeneous static-magnetic-field space region, while enhancing downsizing and weight saving of the system. In conventional magnet systems, strip-shaped ferromagnetic shims have been arranged on respective facing sides of a pair of magnet bodies each having a cylindrical hollow, and ring-shaped ferromagnetic shims have been arranged on both the facing sides and on the surfaces of the hollow portions, of the magnet bodies (e.g., Japanese Laid-Open Patent Publication No. 2002-336215).

Magnet system and magnetic resonance imaging system utilizing the magnet system


In a particular implementation, a video decoder may decode an initial motion vector predictor from the bitstream for a current block, and perform motion search in a small search window to refine the initial motion vector predictor. The initial motion vector may be rounded before being refined. The motion refinement can be based on a discontinuity measure between pixels of a current block and pixels of adjacent block, and can also be based on gradients between the current block and adjacent blocks. The motion vector for the current block is then decoded based on the refined motion vector predictor, and the motion vector difference if there is any. The motion refinement can also be performed on the motion vector for the current block directly. Through motion refinement, the decoder may increase the motion resolution. A corresponding video encoder may choose whether to use motion refinement based on encoder decisions.

To achieve high compression efficiency, image and video coding schemes usually employ prediction and transform to leverage spatial and temporal redundancy in the video content. Generally, intra or inter prediction is used to exploit the intra or inter frame correlation, then the differences between the original image and the predicted image, often denoted as prediction errors or prediction residuals, are transformed, quantized, and entropy coded. To reconstruct the video, the compressed data is decoded by inverse processes corresponding to the prediction, transform, quantization, and entropy coding.

Video coding with adaptive motion information refinement


The present invention provides a method and system for supplementing a video stream of a fantasy card videogame, such as an online videogame electronically played between multiple players across a gaming platform, the gameplay being streaming with a streaming platform. The method and system includes receiving card name data from a game log that indicates a fantasy card being played in the game of the video stream. The method and system accesses a marketplace database using the card name data and electronically retrieves card purchase data therefrom, the card purchase data relating to a commercial transaction for a collectible card referenced by the card name data. Therein, the method and system generates an electronic offer display indicating the collectible card and the card purchase data and transmits the offer to a viewer application associated with a streaming application for displaying the electronic offer display in conjunction with the video stream.

Fantasy card games, both in real life and videogame versions, continue to grow in popularity. Real life games provide one play competing against another, for example in tournaments. Whereas videogames provide electronic representations of a gaming board and playing fantasy cards from players' decks of cards.
These games have evolved, including large numbers of fantasy cards available for the players' decks. Each card has unique designs and character properties. The game consists of the sequential playing of cards against other players, card characteristics controlling progress within the game. A popular series of fantasy card videogames are Magic: the Gathering® electronic videogames available from a variety of software developers. These fantasy card videogames seek to electronically replicate real-life card games.
Another growing area in game technology is gameplay streaming. In real life gameplay, the games can be captured via a video feed and transmitted (livestream or recording-based) to multiple viewers.
Similarly, viewers can subscribe to various streaming services and watch videogame gameplay. Current streaming technology is passive, viewers simply viewing the streaming content, may be providing written or audio comments. For example, a common streaming platform is Twitch® available from Amazon. Other users may engage multiple systems, such as streaming content and talking with friends via Discord® available from Discord, Inc.
Viewers watching the fantasy card game streams are currently unable to get additional information about the cards being played at any specific moment within the game. Fantasy card information is further complicated by these games having thousands of unique cards, each with unique features. During a typical game, 50 to 75 of these unique cards are in-play.
Viewers also seek to collect or trade in these gaming cards. For example, by owning a particular card, the viewer can later play that specific card in his or her own playing of the fantasy card game. Collection of cards, as well as other collectibles, occurs in both live games and videogame games.
There are current electronic marketplaces for a user to log-in and seek to purchase a card from the marketplace. For example, Card Kingdom, Inc. runs an electronic marketplace for users to sell or purchase fantasy game cards. Another example of purchasing options are gaming conferences or comic-book conferences where players can purchase cards or other collectible in-person from a retailer.
But current sales and marketplace techniques are limited to stand-alone and direct access locations. As online content distribution becomes available, there is a need for supplementing streaming content of a fantasy card game to include marketplace and purchase information to viewers.

Method and system for supplementing a video stream of a fantasy card videogame


A harvesting machine includes a frame carrying at least one harvesting mechanism and a lightening device of the harvesting mechanism. The lightening device includes second hydraulic jacks articulated on the frame and on the harvesting mechanism and connected by hydraulic circuits to first hydraulic jacks so as to be able to be actuated by the first hydraulic jacks and to hydropneumatic accumulators.

1. Field of the Invention
The present invention relates to a harvesting machine comprising:                a carrier frame comprising lateral uprights on which are articulated pivots equipped with wheels,        first hydraulic jacks which are connected to the lateral uprights and to the pivots,        at least one harvesting mechanism which is provided with cutting members,        a suspension device linking the harvesting mechanism to the frame and allowing a vertical displacement of the harvesting mechanism with respect to the frame and        a lightening device of the harvesting mechanism.
2. Description of the Related Art
In the known harvesting machines of this type, the lightening device is generally constituted by draw-springs arranged between the frame and the suspension device. These springs then exert an upward traction on the suspension device and the harvesting mechanism and thus transfer a part of their weight on the frame. This lightening prevents the harvesting mechanism from resting too heavily on the ground. It can thus easily follow the differences in level of the ground. This reduces the risk of mishandling the plant cover which could result from too strong a pressure of the said mechanism on the ground. The power to be developed for moving the machine during work can also be reduced. Finally, the wear of the parts of the harvesting mechanism which rub on the ground is less rapid.
The draw-springs currently used on harvesting machines are bulky and cumbersome, particularly when the machine has a large working width. On these machines, there is also a risk of cut products jamming between the turns of these springs, which could harm their functioning. Finally, their cost is relatively high.

Harvesting machine with a lightening device


Methods, systems and devices for displaying video content on large, high resolution video walls, which may comprise a mesh network of an array of display tiles with redundant network switching, in which a virtual, unlimited pixel canvas is created in a video controller memory to facilitate packetizing and addressing of video content packets for delivery to the video wall through a packet-switched network. Embodiments disclosed are particularly well-suited for use with video walls employing LED tiles.

Traditional large video display walls, such as LED video walls are made up of an array of light-emitting display modules, often referred to as tiles. Each tile represents X·Y pixels at a fixed pixel pitch/density, for example, 512×512 pixels. It is not unusual to have many variations of the tiles in unlimited pixel densities due to manufacturing cost and complexity. In addition, each tile is a fixed size, for example, 500 mm wide×500 mm high. Further, LED video walls generally utilize proprietary data protocols over a non-industry-standard physical medium to deliver the video signal. Some manufacturers utilize RS485, some use Ethernet Layer 2, some use Ethernet Layer 1. Due to this non-standard method of distributing data to the tiles, an LED processor or controller (hereinafter "LED controller") is generally used as a signal converter in order to get a standardized video signal, such as HDMI, DVI, DisplayPort, SDI, or another format to the manufacturer's proprietary format.
It is often difficult to send video content in a simple manner to the video wall, even with the "LED controller" because the resulting resolution of the video wall frequently does not correspond to a standard video content raster. As an example, a physical video wall size for a particular installation may be required to be 5 meters wide by 2.5 meters high. Using a common LED tile size, with dimensions as previously mentioned (500 mm×500 mm), this would result in an array of 10 tiles wide×5 tiles high. With the 512×512 pixel tiles, the resulting pixel resolution is 5120 pixels wide×2560 pixels high. In this case, the physical size of the video wall installation has dictated the resolution, since the tiles are a fixed size and pixel density. The resulting resolution far exceeds UHD/4 k resolution (3840×2160) and thus a traditional display using current UHD/4K technology must employ multiple video streams with extremely complex computers and/or video devices in order to provide sufficient pixel data to utilize the full resolution of the video wall.
Existing technology for driving this example video wall is explained in more detail with reference to FIGS. 6, 7 and 8. As illustrated in FIG. 6, four UHD rasters 2 must be utilized so that the 5120×2560 pixel tile array 4 can overlap a portion of each raster in order to receive enough pixel data to display on the tiles. Each of the UHD rasters contains information at not more than UHD/4K resolution corresponding to the portion of the image to be displayed on a portion of the video wall driven by its connected LED controller. In general, the video wall tile array must be divided into sufficient separate displays, each driven by its own LED controller, so that no individual display has a resolution greater than UHD/4K.
Another challenge presented by current technology results from the fact that typically the individual LED tiles are not electronically aware that they are part of a larger, single video wall with multiple tiles. Thus, despite the fact that tile array 4 might appear to have a seamless image, it is actually configured as shown in FIG. 7 with four separate display portions A, B, C and D, each configured as an independent display receiving one of four separate video feeds. However, in this case, as is often the case, the four separate displays cannot have equal resolution (i.e., all four at 2560×1280 pixels) because the physical sizes of the tiles do not permit it. Using current technology, one LED tile cannot bridge two video rasters, so to create the 5120×2560 pixel tile array 4 using 512×512 pixel tiles, two displays (A and B) have a pixel resolution of 2560×1536 and two displays (C and D) have a pixel resolution of 2560×1024. The unequal display resolutions required thus adds further set up and processing complications video source feeds must be precisely parsed in advance to match the specific resolution of the display portion to which they will be directed. Further, due to how the video feeds (A, B, C, D) must be aligned to traditional video rasters, there is a waste of bandwidth on both the video raster feeds going into the LED processors and also a waste of pixel processing bandwidth within each LED processor as these pixels do not get transmitted to an LED tile in a display.
A prior art system for driving the example video wall 4 might typically be configured as shown in FIG. 8. Using existing technology, each display portion (A, B, C, and D) requires its own LED controller running independent video content corresponding to the portion of the larger display wall of which it is a part. Thus, as shown in FIG. 8, the video signal path must be fully replicated four times, despite the fact that the resulting display for the observer is a singular display. Not only are four video sources 6 required, each providing the appropriate portion 8 of the final image, but also four independent LED controllers 10. Each LED controller 10 generates its image portion for the corresponding display portion A, B, C or D and communicates with that display portion via dedicated connections 12 specific to that individual controller/display portion pairing. In reality, however, the cabling complexity is much greater than shown in the simplified schematic illustration in FIG. 8 because dedicated connections 12 must individually connect to each LED tile to provide its portion of the video signal for the display portion (A,B,C,D) in which the tile resides. Such complex cabling requirements have led to other problems in providing a robust system with failsafe protections.
For example, current technologies for creating and controlling arrayed video devices, such as the prior art video wall system shown in FIG. 8, can exhibit a large gap in data redundancy and display resilience. In current systems, display tiles are commonly daisy-chained from one to the next until the capacity of the data line is maximized in order to provide a video signal path to each tile. In some prior systems, a backup line can be used in order to provide a fail-safe if the primary link goes down (due to upstream equipment or cable fault). Both methods are rudimentary, however, and still pose an aesthetically displeasing result. Moreover, such systems do not protect against multiple data link failures between tiles. For example, in a daisy-chained system, even with a backup data link, two separate data link failures will result in dead tiles between the failed data links.
While network communication techniques might be employed to simplify connections, communications and processing challenges with high resolution video walls, and other challenges presented by packet-based networking have limited its application. In a normal video system comprised of inputs and outputs, it is relatively straightforward to choose a specific x,y coordinate of the incoming video as a starting point to re-transmit a signal. The x,y start coordinate and width/height of the retransmission block is easy to ascertain because video formats are raster based—this means that line-by-line, or section-by-section, the data is transmitted from top left to lower right in a scanning order. However, in a packet switched network, for example an Ethernet payload, traffic routed on Ethernet switches is not required to receive or send packets in any meaningful order—the switches only deliver a packet from point A to B. The randomness of such networks thus traditionally has made delivery of high resolution video content at a high quality problematic.

Unlimited pixel canvas for LED video walls


Methods and apparatus (100) for scanning a surface (12) of a substrate (10) with an obliquely incident radiation beam (20) over a select scan path (210) to avoid damage (30) to the curved edge (14) of the substrate. The methods and apparatus allow for the substrate edge to be irradiated with the full intensity of the radiation beam, provided that the edge crossing positions avoid a region where the polar angle is less than a scan path critical (SPC) polar angle (φC). At the SPC polar angle the temperatures produced by scanning the beam on the substrate surface and on the edge are the same. The scan path is arranged so the edge crossing positions are located where the polar angle corresponding to each meets or exceeds the SPC polar angle. Ensuring that the substrate edge temperature (TE) remains at or below the substrate surface temperature (TS). The invention has particular utility in laser thermal processing (LTP) of circular silicon substrates when forming transistor-based integrated circuits.

1. Field of the Invention
The present invention relates to thermal processing of a substrate, and in particular relates to methods and apparatus for irradiating a substrate in a manner that avoids damaging the substrate.
2. Description of the Prior Art
Laser thermal process (LTP), also known more generally as rapid thermal processing (RTP), is a technique for manufacturing semiconductor devices such as integrated circuits or "ICs". LTP involves irradiating a substrate with a beam of intense radiation to rapidly bring the substrate surface from a relatively low temperature (e.g., 400° C.) to a relatively high temperature (e.g., 1,200° C.) so that the substrate bulk can pull the temperature down quickly.
One prime application of LTP is for dopant activation of the source/drain regions of transistors formed in a silicon Wafer. The source/drain regions are typically formed by exposing areas of a silicon wafer to an electro-statically accelerated ion beam containing boron, phosphorous or arsenic ions. After implantation, the dopant atoms are largely interstitial, do not form part of the silicon crystal lattice, and are electrically inactive. Activation of these dopant atoms is achieved by raising the substrate temperature high enough and for a period of time long enough for the crystal lattice to incorporate the impurity atoms. The optimum length of time depends on the maximum temperature. However, during the activation thermal cycle, the impurities tend to diffuse throughout the lattice causing the distribution to change from one approximating an ideal step profile during implant to a profile having a shallow exponential fall-off.
By employing higher annealing temperatures and shorter annealing times, it is possible to reduce dopant diffusion and retain the abrupt step-shaped dopant distribution achieved after the implant step. The continuous reduction in transistor feature sizes has lead to a process called Laser Spike Annealing (LSA), which employs a CO2 laser beam formed into a long, thin image that is raster scanned across the wafer. In a typical configuration, a 0.1 mm wide beam is scanned at 100 mm/s over the wafer surface to produce a 1 millisecond dwell time for the annealing cycle. A typical maximum temperature during this annealing cycle might be ˜1350° C. In the 1 millisecond time it takes to bring the wafer surface up to the annealing temperature, only about 100–200 microns of material nearest the upper surface is heated. Consequently, the bulk of the 800 micron thick wafer serves to cool the irradiated surface almost as quickly as it was heated once the laser beam moves past.
A wafer that has been processed to the point where it is ready for the annealing step typically contains a number of thin film structures such as gates, poly-silicon runners and pads, and oxide isolation trenches. These structures may be superimposed. The distribution of these structures varies from region to region across a circuit, depending on the function of a particular area of the circuit. Typically, the reflectivity of the circuit varies depending on the proportion of the various structures present in a given region. This leads to substantial variations in the proportion of the laser beam energy absorbed in any area and thus uneven heating.
In some cases, even a 5° C. variation in the maximum annealing temperature can lead to observable performance issues for the circuits being annealed. This temperature variation might correspond to less than a 0.5% variation in the absorption coefficient of the product wafer surface. A minimum variation in absorption can be achieved by using P-polarized radiation incident on the substrate at or near the Brewster angle. P-polarized radiation incident on an undoped silicon surface is completely absorbed at the Brewster angle. In the case of a patterned wafer, the Brewster angle refers to the angle of minimum or near-minimum reflectivity of P-polarized light from a surface. Strictly speaking, films on the surface of an object such as silicon wafer, or electrically active dopants in the silicon prevent it from having a true Brewster angle. Accordingly, the Brewster angle as used herein for a specular surface formed from a variety of different films stacked on a substrate (as is the case for a product IC wafer) can be thought of as an effective Brewster angle, or the angle at which the reflectivity of P-polarized radiation is at a minimum. This minimum angle typically coincides with or is near the angle of the true Brewster angle for the (bare) substrate.
A further reduction in reflectivity variation can be achieved by using wavelengths that are large compared to the device structures on the wafer. This condition is met with the 10.6 micron CO2 laser. The Brewster angle for bare silicon at 10.6 microns is about 75° from normal incidence.
FIG. 1 is a schematic side view of a substrate 10 with an upper surface 12 with an associated surface normal N12. Substrate 10 includes an outer edge 14 with an associated edge normal N14. Unlike surface normal N12, whose direction is the same for points on the upper surface, the edge normal N14 varies in direction as a function of the polar angle φ (see FIG. 4) in the X-Y plane.
Substrate 10 includes a narrow annular exclusion zone 18 of width WE (FIG. 4) that runs around the upper surface 12 adjacent outer edge 14. Exclusion zone 18 is the region between the substrate edge and the process area 19, which is the portion of the substrate where full yield is expected when producing semiconductor devices such as ICs. Substrate 10 is shown being irradiated with a radiation beam 20 that performs LTP of the substrate by scanning the beam over the upper surface. Radiation beam 20 is incident upon substrate upper surface 12 at a surface incident angle θ with respect to surface normal N12. Surface incident angle θ may be, for example the (effective) Brewster angle for the substrate. The intensity I(θ) of radiation beam 20 at substrate surface 12 is given by I(θ)=I0 Cos(θ), wherein I0 is the baseline radiation intensity measured normal to the radiation beam.
When irradiating the substrate at a high incident angle θ (e.g., ˜75°) with scanned radiation beam 20, substrate edge 14 on the far side FS (relative to the incident direction of the radiation beam) never sees the incident radiation beam, even when the beam moves from position A to position B. However, substrate edge 14 on side NS is prone to exposure by radiation beam 20 when the beam is in position A. Further, radiation beam 20 makes an incident angle ψ with respect to edge normal N14, wherein ψ=90°−θ when φ=0°. Thus, if θ=75°, then ψ=15°. Accordingly, if radiation beam 20 is in position A, the intensity I at the near side substrate edge 14 is approximately 3.73 times greater than the intensity at surface 12. This can raise the near-side substrate edge temperature to a level sufficient to damage (e.g., form fractures 30) in the substrate at the substrate edge.
At first glance, it might appear that this problem is easily solved by simply blocking the portion of radiation beam 20 that strikes wafer edge 14. However, when radiation beam 20 is coherent, as is typically the case for LTP or other irradiative processes requiring a high-power beam, a baffle that blocks a portion of the radiation beam before it reaches substrate edge 14 on near side NS, also diffracts the radiation beam. The diffracted radiation interferes constructively or destructively with the portion of the beam directly incident on the substrate, depending on the position. This causes some portions of the regions on substrate surface 12 to be overexposed while other regions are underexposed. The variation in exposure caused by diffraction can be as high as 20% or more. Thus, any attempt to block the beam from striking the substrate edge results in an unacceptable non-uniformity at the substrate surface that extends well beyond the narrow exclusion zone 18, making this shielding approach an untenable solution.
Simply turning the radiation beam off and on as it approaches and recedes from the wafer edge is also not particularly effective. This is because the wafer edge exclusion band 18 is typically only 3 mm wide, while radiation beam 20 has a typical width of 6 to 10 mm. Thus, a linear scan of substrate surface 12 near edge 14 results in either some of the edge being directly exposed by the beam, or the beam being turned off before all of the desired area of the substrate surface has been exposed.
The '739 patent application solves the edge exposure problem by utilizing an optical system that includes an anamorphic relay, an apodized aperture, and a vignetting edge moving in synchronism with the scan. However, this is a relatively complex and expensive solution to the problem.

Methods and apparatus for irradiating a substrate to avoid substrate edge damage


A semiconductor device includes an n channel conductivity type FET having a channel formation region formed in a first region on a main surface of a semiconductor substrate and a p channel conductivity type FET having a channel formation region formed in a second region of the main surface, which second region is different from the first region. An impurity concentration of a gate electrode of the n channel FET has an impurity concentration greater than an impurity concentration of the gate electrode of the p channel FET to thereby create a tensile stress in the direction of flow of a drain current in the channel forming region of the n channel FET. The tensile stress in the flow direction of the drain current in the channel forming region of the n channel FET is greater than a tensile stress in the direction of flow of a drain current in the channel forming region of the p channel FET.

One well-known type of field effect transistor, to be mounted on a semiconductor device, in an insulated gate type field effect transistor called a MISFET (Metal Insulator Semiconductor Field Effect Transistor). A MISFET is widely used as a circuit element constituting an integrated circuit, because it facilitates high integration.
A MISFET, whether it has an n channel conductivity type or a p channel conductivity type, usually has a channel formation region, a gate insulator, a gate electrode, a source region, a drain region and the like. The gate insulator is disposed in an element formation region on the surface (one main surface) of a semiconductor substrate on which a circuit is to be formed, and it is formed, for example, of a silicon oxide film. The gate electrode is disposed, via the gate insulator, on the element formation region of the surface of the semiconductor substrate on which a circuit is to be formed, and it is formed, for example, of a polycrystalline silicon film into which an impurity has been introduced to reduce the resistance. The channel formation region is disposed in a region (right below the gate electrode) of the semiconductor substrate, opposite to the gate electrode. The source and drain regions are formed of semiconductor regions (impurity diffusion regions) disposed on both sides of the channel formation region in a channel length direction.
A MISFET having a gate insulator made of a silicon oxide film is usually called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The term "channel formation region" means a region wherein a current channel connecting the source region with the drain region is to be formed.

Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor


A liquid crystal display module includes a bottom chassis comprising a lower surface including at least one fastening hole disposed along a first direction; a printed circuit board comprising a first surface supported by the lower surface of the bottom chassis, a second surface opposite to the first surface, and at least one opening hole corresponding to the at least one fastening hole of the bottom chassis; a plurality of light emitting diodes mounted on the second surface of the printed circuit board; and at least one fastening member comprising a head part inserted into the at least one opening hole of the printed circuit board so as not to be protruded outwardly from the second surface of the printed circuit board, and a fastening part disposed in and affixed to the at least one fastening hole.

1. Field
Exemplary embodiments relate to a liquid crystal display module having a structure in which a printed circuit board is connected to a bottom chassis, and a liquid crystal display device having the same.
2. Description of the Related Art
In general, a liquid crystal display (LCD) device displays an image using electrical and optical characteristics of liquid crystals. The LCD device has a thin thickness, a light weight and low power consumption and is operated at low drive voltage, as compared with other display devices, and thus has been widely used in the overall industries.
The LCD device includes a liquid crystal display panel in which liquid crystal molecules are injected into a gap between two transparent substrates and voltage is applied to liquid crystal molecules so as to change orientation of the liquid crystal modules to change light transmittance of the liquid crystal molecules and thus to optically display an image, and a liquid crystal display module to supply light to the liquid crystal display panel.
Recently, an edge type liquid crystal display module using light emitting diodes as a light source unit is mainly used so as to achieve slimness of the LCD device.
The edge type liquid crystal display module is provided with a printed circuit board, on which a plurality of light emitting diodes is mounted. The light emitting diodes are provided on the side surface of the liquid crystal display module, which guides light generated by the light emitting diodes to the front surface of the liquid crystal display module through a light guide plate, and then supplies the light to the liquid crystal display panel.
Such a liquid crystal display module is manufactured through a process of fixing the light source unit. In general, the printed circuit board of the light source unit is assembled with a metal structure having an L shape or other shapes by screws and is then mounted on a bottom chassis.

Liquid crystal display module and liquid crystal display device having the same


In some embodiments, a method can comprise accessing one or more neighborhood data structures, at least a portion of the one or more neighborhood data structures are active. In many embodiments, the one or more neighborhood data structures each comprise a label comprising a record identifier, the record identifier corresponding to a specified record of the one or more records, a neighborhood comprising a list of record identifiers for other records linked to the specified record of the one or more records by a pairwise link, and a message for each of the other records linked to the specified record of the one or more records, the message comprising the label and an activity state indicator, the activity state indicator indicating if the neighborhood data structure is active. Other embodiments of related methods and systems are also provided.

1. Field of the Invention
The present invention relates generally to identifying groups of records correspond to the same entity with larger datasets, and, more particularly, to resolving a plurality of pairwise links of records into one or more groups of records corresponding to the same entity.
2. Related Art
There are many avenues for a customer to acquire goods or products that meet their needs or wants. One way for a customer to acquire goods is through the use of a retailer. Depending on the market strategy of the retailer, there are many different avenues for retailers to sell products. For example, retailers can sell products in physical store locations (e.g., department stores, discount stores, warehouse stores, supermarkets, etc.), online, and even through vending machines.
Given the large number of choices for a consumer to acquire products, it becomes expedient for retailers to do their best to attract and retain customers. For example, retailers may need to keep their prices low relative to their competition to attract and retain customers. Further, retailers may need to provide a good or product that is not readily available through other retail options. Without staying competitive, retail stores may have a weakened customer base, and, in turn, lose their profitability.
In order for a retail store to better meet the needs of their customers, retail stores have an interest in the shopping patterns of their customers. As understanding of customer shopping habits and tendencies increases, a retailer can offer incentives such as coupons or rebates to entice its customers to make more purchases or purchase items that may be unfamiliar to a customer. This both improves the customer shopping experience and increases retailer profit margin. Also, customer shopping experience improves, customers may be more likely to refer their friends to user the retailer (e.g., visit a store, go to the Website, etc.).
There are many ways for a store to observe the shopping habits of their customers. One way is issuing a membership card to its customers. As the customer checks out, the customer card is scanned. The store database can then keep track of which items the customer purchases, and how often the purchases are made. The store incentivizes the customer to use the card by offering reduced prices for purchases made with the card.
In addition to membership cards, retail stores can also track the shopping patterns of their customers through a customer's online activity. The store can track which items the customer viewed on their website, which items the customer searched for using the website's search feature, which items they added to their online cart, and which items they purchased.
Further, if the customer pays with a check or credit card, the store can determine if the customer has a profile within the store's database, and can associate the customer's purchases, credit card, checking account, etc., with the customer's profile.
Given the many avenues for customer's to make purchases, it becomes increasingly difficult for a retailer to match a particular customer to all of their interactions with the retailer. For example, some of the customer's purchases may be made online with one credit card, other purchases may be made at a store with a different credit card, and remaining purchases may be made using a membership card and paying by cash or check. In addition, many retail stores have more than one type of retail store. For example, some retailers may operate both a discount store and a warehouse store. Identifying a customer of the discount store and a customer of the warehouse store as the same customer can be difficult.
As retail stores accumulate customer data through purchases or other interactions, an enormous amount of data is created, for example, for some retailers billions of records. As mentioned previously, many of these records may have been created through different types of customer interaction; whether they bought the items online, with a membership card, with a credit card, at the retailer's discount store, at the retailer's warehouse store, or some combination thereof. It can be very challenging to sort through the vast amount of records in order to associate each record with the customer that created the record.

This patent is subject to a terminal disclaimer.


In the present invention, there is provided an organic electro luminescence device including: an organic electro luminescence light emitting element; and a driving circuit for driving the organic electro luminescence light emitting element, wherein the driving circuit includes (A) an element driving transistor, (B) a video-signal write transistor, and (C) a capacitor having a pair of particular and other electrodes, with regard to the element driving transistor, (A-1) a source/drain area provided on a particular side of the element driving transistor to serve as a particular source/drain area of the element driving transistor is connected to a current supply section, and (A-2) a source/drain area provided on the other side of the element driving transistor to serve as another source/drain area of the element driving transistor is connected to the anode electrode of the organic electro luminescence light emitting element and the particular electrode of the capacitor, forming a second node.

1. Field of the Invention
The present invention relates to an organic EL (electro luminescence) device and an organic EL (electro luminescence) display apparatus employing this organic EL device. In this specification, the technical term 'electro luminescence' is abbreviated to EL. In addition, two sides of a component are referred to as respectively particular and other sides of the component. By the same token, two electrodes of a component are referred to as respectively particular and other electrodes of the component. In the same way, two faces of an area are referred to as respectively particular and other faces of the area.
2. Description of the Related Art
In an organic EL display apparatus employing an organic EL device including an organic EL light emitting element, the luminance of the organic EL device is controlled by a current flowing through the organic EL device. Strictly speaking, the luminance of the organic EL device is the luminance of the organic EL light emitting element employed in the organic EL device. In addition, much like a liquid-crystal display apparatus, a simple matrix method and an active matrix method are each generally known as a driving method of the organic EL display apparatus. In comparison with the simple matrix method, the active matrix method has a shortcoming of a complicated structure. Nevertheless, the active matrix method offers merits such as a high degree of image luminance.
A circuit for included in the organic EL device as a circuit for driving an organic EL light emitting element employed in the organic EL device is, for example, a driving circuit having five transistors and one capacitor. In the following description, the driving circuit employing five transistors and one capacitor is referred to as a 5Tr/1C driving circuit. The 5Tr/1C driving circuit is described in documents such as Japanese Patent Laid-open No. 2006-215213. As shown in FIG. 36, the 5Tr/1C driving circuit employs five transistors and a capacitor C1. The five transistors are a video-signal write transistor TSig, an element driving transistor TDrv, a light-emission control transistor TEL—C, a first-node initialization transistor TND1 and a second-node initialization transistor TND2. In this configuration, the other source/drain area of the element driving transistor TDrv forms a second node ND2 whereas the gate electrode of the element driving transistor TDrv forms a first node ND1. In the following description, the other source/drain area of the element driving transistor TDrv is a source/drain area provided on a side close to the organic EL light emitting element to serve as the other source/drain area of the element driving transistor TDrv.
Each of the transistors cited above is, for example, a TFT (Thin Film Transistor) of an n-channel type. The organic EL light emitting element denoted by notation ELP in figures in this specification is provided on a created inter-layer insulation layer for example, so as to cover the driving circuit. The anode electrode of the organic EL light emitting element ELP is connected to the other source/drain area of the element driving transistor TDrv. On the other hand, a voltage VCat of 0 volts, for example, is applied to the cathode electrode of the organic EL light emitting element ELP. Notation CEL shown in each figure of this specification denotes the parasitic capacitance of the organic EL light emitting element ELP.

Organic EL device and organic EL display apparatus


A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.

In recent years, to facilitate high integration densities and fine geometries of semiconductor devices, three-dimensional mounting in which multiple wiring substrates are piled in three dimension to be mounted has been studied. In such three-dimensional mounting, for example, a relay board having minute wirings can be joined on a main board. Specifically, between the main board and the relay board, an underfill material, such as a non-conductive film (NCF), is filled, and the relay board is attached to the main board. Moreover, conductive posts are formed on a surface of the main board, and these posts and an electrode pad formed on a surface of the relay board are connected with solder. Thus, the main board and the relay board are electrically connected.
When joining the main board and the relay board, pressure is applied toward a direction in which the both wiring substrates come close to each other in a state in which the underfill material is filled between the wiring substrates. At this time, for example, the underfill material flows over from between the wiring substrates, and forms, for example, a fillet around the relay board. That is, for example, as illustrated in FIG. 11, when a relay board 20 is attached to a main board 10, a fillet 30 is formed around the relay board 20 with the underfill material drained out from between the wiring substrates. FIG. 11 is a plan view of a stacked wiring substrate in which the main board 10 and the relay board 20 are joined, viewed from a direction of the relay board 20    Patent Document 1: WO2018/173764    Patent Document 2: Japanese Laid-open Patent Publication No. 2014-110390    Patent Document 3: Japanese Laid-open Patent Publication No. 2007-305814
However, there is a disadvantage to the stacked wiring substrate described above that a shape of the fillet formed around the relay board is not uniform, and a part mounting area on the main board is limited. Specifically, as illustrated in FIG. 11, the fillet 30 spreads widely at a central portion of each of four sides of the relay board 20, and it is difficult to mount a part near the relay board 20.
Moreover, because the fillet 30 spreads out largely at the central portions while the fillet 30 spreads less at portions of four corners of the relay board 20, it is difficult to mount parts on the main board 10 aligning positions thereof, and flexibility of parts arrangement is reduced.

Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate


Numerous mobile devices report their respective locations to a server which collects the location reports to provide real-time pedestrian traffic information, e.g., as a map that shows locations of individual mobile devices. Distribution of mobile devices in a geographic area more closely represents overall population locations and densities. Each device is identified by a digital fingerprint, formed from a number of system and device configuration parameters. Each mobile device is configured to periodically report its location, e.g., at a predetermined time interval and/or whenever the mobile device determines its location for another reason. A known location of a wireless network access point to which a mobile device is connected can serve as an estimated location of the mobile device.

1. Field of the Invention
The present invention relates generally to computer data processing and, more particularly, methods of and systems for monitoring and analyzing pedestrian traffic.
2. Description of the Related Art
There are countless occasions and studies in which knowing where people are at any given time is valuable. Some occasions are quite serious. For example, emergency services—such as fire departments and paramedics—need to get to places quickly. If areas of a city are blocked by public gatherings, public demonstrations, or the city's celebration of a sports team winning a national championship, emergency response vehicles can be significantly delayed, sometimes with very serious consequences. In addition, knowing whether and where people are in a burning building is highly valuable information for a fire department.
Analysis of pedestrian traffic patterns can help significantly with urban planning. Knowing where people tend to go within a city can help with planning a mass transit system. Knowing places that people tend to avoid can identify instances of urban blight. And, once the urban blight is removed, knowing how many people tend to go to that location can provide empirical evidence of the efficacy of the blight removal. Monitoring pedestrian traffic can also determine if and how often people enter environmentally sensitive areas.
Businesses also value information regarding where people are and where they go. Knowing approximately how many people are in a store at any given time is valuable. Knowing patterns regarding how many people are in the store at different times of day and different days of the week and during clearance sales and holidays is very valuable. Also valuable is knowing from where people travel to come to the store and what other stores they go to before and after shopping in the store.
What is needed is a way to monitor and analyze pedestrian traffic.

Pedestrian traffic monitoring and analysis using location and authentication of mobile computing devices


A three axes or three dimensional adjustment foundation target mount for use in industrial applications to provide for precise settings for machining and related operations, includes a body, the body has internal threads therein, an expandable vertical adjustment disc is provided therein, a lateral adjustment target cone is applied on top of the adjustment disc, and a top retainer disc is located and threadily engaged within the body, and holds a series of adjustment screws which can be adjusted to provide for the lateral and fore and aft adjustments to the target cone, to furnish, along with the adjustment disc, three dimensional adjustments for the survey target when applied to the mount. A cap is also provided to furnish coverage for the receptacle, following its precise setting and usage.

Various types of industrial survey and target means have been available in the art, most of them usually have a one dimension setting, in their usage and application. For example, U.S. Pat. No. 4,549,360, shows a floor target mount, but it is only adjustable in one axis, as can be seen therein. This does not provide for the precision required for industrial settings.
An adjustable floor target mount is available upon the market, under model No. 740, by a Brunson Products, but its particular target mount is only adjustable in two axes, the X and the Y axis, and can not be vertically adjusted, as along the Z axis, as desired.
Other types of foundation target inserts, are available in the art, such as a foundation sphere mount, but none of these products have adjustability in their fine and precise settings.

Three axes adjustable foundation target mount


The invention relates to an electromechanical drive for actuating valves, especially in steam turbines including an electromotor, a linear unit, a clutch and an electronic control unit. The linear unit includes a piston rod which is guided in a power-transmission thread of a screw nut, and is arranged, at least in sections, as a spindle and is displaceable along its longitudinal axis for actuating the valve in the screw nut with the power-transmission thread. The clutch is arranged for transmitting a rotational movement of the motor axis of the electromotor onto the piston rod. The electronic control unit is set up to control the speed and/or rotor position of the motor axis of the electromotor depending on a control signal and an output signal of a position pick-up of the position of the piston rod in the screw nut with power-transmission thread, and/or to control the engagement and/or disengagement of the clutch depending on the control signal.

1. Field of the Invention
The present invention relates to an electromechanical drive for actuating valves, especially in steam turbines.
2. Description of the Related Art
It is known to open and close valves in steam turbines with hydraulic or pneumatic drives, for example, to actuate an actuator for this purpose with a hydraulic cylinder or pneumatic cylinder in an electrohydraulic or electropneumatic manner. Examples for such actuators are described in German Patent documents DE 30 19 602 C2 and in DE 42 36846 C2.
Electrohydraulic or electropneumatic actuators are used for adjusting steam valves. Such actuators consist of a hydraulic cylinder or pneumatic cylinder which can be arranged in a single-acting or double-acting manner. A hydraulic/pneumatic control valve triggering the same is arranged as a 3/3 or 4/3 directional control valve and a position-sensing and a closed-loop control mechanism for the hydraulic cylinder or pneumatic cylinder. The position-sensing mechanism for the hydraulic cylinder or pneumatic cylinder, which can be arranged as an electronic position sensor or, in the simplest of cases, as a mechanical lever mechanism, is used to guide back the actual position of the hydraulic cylinder/pneumatic cylinder to the hydraulic/pneumatic control valve. A closed-loop position control loop for the hydraulic/pneumatic cylinder can thus be performed which allows a continuous setpoint-value-dependent positioning of the hydraulic/pneumatic cylinder.
One requirement in the adjustment of steam valves is that various fault conditions or events in the steam turbine require the steam valve to be closed reliably and very rapidly in order to bring the steam turbine to a secure state. Such quick-locking processes need to be performed even in the case of failure of the supply of medium of the hydraulic cylinder or pneumatic cylinder, e.g. the oil supply. This leads to the demand to enable performing the closing process independent of any functioning oil supply. Pressure springs are usually applied for this purpose to the actuator or the steam valve which exert the closing force independent of oil supply/air supply. Another solution is to provide the medium pressure reservoir as close as possible to the actuator and to remove the required medium quantity from the same and to exert the closing force.
For the feedback control of such actuators in steam valves in steam turbines, there are special requirements concerning the speed and the low-level signal behavior of such a feedback control. It is thus necessary that in the case of load changes in the steam turbine, as may occur, for example, in a sudden relief of a driven generator, the servo valve needs to move very rapidly to a new lower lifting position which corresponds to the new operating point of the generator and which holds the steam turbine within the permitted speed or frequency limits. If a demand for rapid closing occurs during such a feedback control process, it needs to be performed immediately. A precise low-hysteresis low-level signal behavior is required especially during the synchronization of a driven generator to the electric infeed network because no damping load acts on the steam turbine and thus small changes in the stroke of the actuator on the steam valve will lead to large changes in speed in the steam turbine. These high requirements can hardly be fulfilled with pneumatic drives. That is why they are only used in simpler applications such as steam turbines for compressor or pump drives. Electrohydraulically driven actuators are used otherwise.
The known actuators in steam turbines require a supply with a medium. Especially in the case of hydraulic drives a separate oil supply is usually necessary which supplies the required high medium pressure and oil quantity on the one hand and ensures the required oil purity which is required for operating directional control valves on the other hand. Moreover, complex mechanical piping is necessary which leads the medium to the actuator and from there back to the oil supply. There is always the likelihood of leakages of medium on the actuator and the piping, which is caused by improper piping or by the detachment of connecting elements by vibrations which are always present in steam turbines. These leakages of medium can lead to fires when flammable medium reaches the hot surface of the steam turbine. In order to avoid this, non-flammable medium liquids are used. However, they are expensive, lead to higher maintenance costs, and are hazardous for the environment which is why they have not prevailed as a solution to the problem. A further disadvantage of known actuator technology is that, in the case of electrohydraulic actuators, the mounting position cannot be chosen freely but is regularly predetermined in a fixed fashion, thus limiting the constructional freedom in the arrangement of such drives.
What is needed in the art is an electromechanical drive for actuating valves which avoids the disadvantages of the state of the art, especially by achieving a simple and secure actuation of valves of steam turbines.

Electromechanical drive for actuating valves


A latch circuit has two initializing circuits that receive identical inputs and generate two identical output signals, one internal and one external. An inverter inverts the internal output signal to generate a complementary external output signal. One or more control signals can force the output signals to fixed states. When the control signals are inactive, the output signals depend on either an input signal or a feedback signal generated from the internal output signal, as selected by a selecting circuit.

This invention relates to a latch circuit suitable for semi-custom integration, more particularly to a latch circuit with complementary output signals in which initializing signals such as set and reset signals have priority over latch signals.
Semi-custom integrations are created by interconnecting a set of standardized circuits on a semiconductor chip supplied by a manufacturer to obtain a device with desired functions. Use of semi-custom integrated circuits, typified by so-called gate arrays and application-specific integrated circuits, has become widespread. The standardized circuits employed range from simple logic gates to large macrocells. The standardized latch circuits of the present invention are intermediate in this range.
In designing a semi-custom integrated circuit, the user relies on timing parameters supplied by the manufacturer. In the case of a latch circuit, these timing parameters include, for example, setup time, hold time, input-to-output propagation delay in the unloaded state, and dependency coefficients indicating how the propagation delay increases with the size of the load. It is desirable that these parameters be constant and not vary according to the input and output connections of the circuit in question.
In the case of a circuit with two outputs it is undesirable for the timing parameters of one output to be influenced by the load coupled to the other output. This consideration applies in particular to a standardized latch circuit with two complementary outputs. A latch circuit in which the non-inverting output signal is branched to an inverter that generates the inverting output signal is unsuitable for semi-custom integration, because the propagation delay of the inverting output signal depends strongly on the load of the non-inverting output signal. The same problem occurs in latch circuits that use the inverting or non-inverting output signal as a feedback signal.
One way to avoid such unwanted interactions between the outputs of a latch circuit would be to add more inverters, so that each output signal is driven by an inverter which in turn is driven by an internal signal. Increasing the number of inverters, however, adds to the overall propagation delay, making the resulting latch circuit unfit for high-speed operation.

Latch circuit with independent propagation delays