In a method for driving a liquid crystal display apparatus in which in each field, scan lines are successively scanned in order to display an image, the scanning sequence or the polarity of a signal voltage is reversed between a first field and a second field. A liquid crystal display apparatus driven by the method is also disclosed. It is possible to provide a high contrast, high brightness liquid crystal display apparatus which is not affected by electrical asymmetry.

(a) Field of the Invention
The present invention relates to a liquid crystal display apparatus and a method of driving the same, and more particularly to a method of driving a liquid crystal display element which provides high contrast and high brightness and which is not affected by electrical asymmetry, as well as a liquid crystal display apparatus having a liquid crystal display element that is driven by such a method.
(b) Description of the Related Art
The mainstream of a high performance liquid crystal display apparatus is a TFT (thin-film transistor)-scheme active matrix liquid crystal display apparatus of a TN (twisted nematic) mode using nematic liquid crystal or an IPS (in-plane switching) mode. In such an active matrix liquid crystal display apparatus, an image is re-displayed at 60 Hz, because positive and negative image signals are written at 30 Hz, making the time period of one field about 16.7 ms (millisecond). The total of the time for writing the positive image signal and the time for writing the negative image signal is called a frame time, which is about 33.3 ms. By contrast, the response time of the fastest available liquid crystal is almost equal to the frame time. Therefore, display of an image including a motion picture or display of a high speed computer image requires a response speed faster than the current frame time.
Meanwhile, a field-sequential color liquid crystal display apparatus has been studied in an effort to increase resolution. In the field-sequential color liquid crystal display apparatus, the color of a back light of the liquid crystal display apparatus is sequentially switched among red, green, and blue. Since this method does not require that color filters be spatially disposed, the resolution can be increased to three times that of a conventional liquid crystal display apparatus. In the field-sequential color liquid crystal display apparatus, since an image for one color must be displayed within a period ⅓ that for one field, the time period that can be used for display is about 5 ms. Therefore, liquid crystal itself is required to have a response time shorter than 5 ms. Liquid crystal that causes spontaneous polarization, such as ferroelectric liquid crystal or antiferroelectric liquid crystal, has been studied as candidate liquid crystal capable of achieving such a high response speed. Further, in relation to nematic liquid crystal, various studies have been performed in an effort to improve a response speed through an increase in the degree of dielectric anisotropy, a decrease in viscosity and/or thickness, or employment of a pi-type liquid crystal orientation.
In an active matrix liquid crystal display element, the operation of storing a voltage and a charge in the liquid crystal section is actually performed only in a period during which each scan line is selected (write time). The write time is 16.7 μs (microsecond) in the case of a liquid crystal display apparatus which has 1000 lines and in which an image signal for the 1000 lines is written within one field time, and about 5 μs in the case of a liquid crystal display apparatus which is driven in a field sequential scheme. Presently, no known liquid crystal element or known manner of liquid crystal completes its response within the time period as described above. Even among liquid crystal elements that cause spontaneous polarization and nematic liquid crystal of improved response speed, no known element exhibits such quick response. This results in the problem that response of liquid crystal generally occurs after completion of signal write operation. Consequently, in liquid crystal elements that cause spontaneous polarization, a depolarization field is generated due to rotation of spontaneous polarization, so that voltages at opposite ends of a liquid crystal layer drop abruptly. Therefore, the voltages stored at the opposite ends of the liquid crystal layer change largely. Meanwhile, in the high speed nematic liquid crystal, change in the capacitance of a liquid crystal layer caused by anisotropy of dielectric constant increases considerably, resulting in a change in the voltage that is written into the liquid crystal layer and must be held constant. Such a decrease in the holding voltage; i.e., a decrease in the effective applied voltage, results in insufficient writing, so that the on-screen contrast decreases. Further, when the same signal is repeatedly written, the brightness continuously changes until lowering of the holding voltage stops, so that a few frames are required to obtain stable brightness.
"Japanese Applied Physics," Vol. 36, Part 1, No. 2, pp 720-729 reports that a so-called "step response" phenomenon occurs when an identical image signal is written over a few frames after a frame in which an image signal changes and thus the absolute value of a signal voltage changes. According to this phenomenon, for the same signal voltage, the transmittance of liquid crystal changes in the manner of damped oscillation over a few frames, so that the liquid crystal becomes bright in alternate frames and dark in other frames. After a few frames, the transmittance is stabilized at a predetermined level.
An example of the above phenomenon will be described with reference to FIGS. 1-3. FIG. 1(a) is chart showing the waveform of a data voltage; and FIG. 1(b) is a chart showing change in transmittance at that time. When the data voltage shown in FIG. 1(a) is applied to liquid crystal, as shown in FIG. 1(b), the transmittance of liquid crystal changes in the manner of damped oscillation such that the liquid crystal becomes alternately light and dark. In the illustrated example, the transmittance of the liquid crystal converges to a constant level in the fourth frame. Since the liquid crystal requires a few frames to change its transmittance as described above, high speed display of images is impossible.
FIG. 2(a) is a chart showing the waveform of a data voltage; FIG. 2(b) is a chart showing change in a gate voltage; and FIG. 2(c) is a chart showing change in transmittance at that time. FIG. 3 is a timing chart for scan lines in the drive shown in FIG. 2. The color shade during each of positive and negative display periods 102 and 104 represents brightness corresponding to the transmittance of FIG. 2. In FIG. 3, a time period of 16.7 ms is indicated by an arrow.
FIG. 3 depicts six scan lines. Positive writing 101 is successively performed from the top scan line in order to obtain a positive display 102, and then negative writing 103 is successively performed from the top scan line in order to obtain a negative display 104. In each scan line, the period of the positive writing 101 and the period of the positive display 102 constitute a first field, while the period of the negative writing 103 and the period of the negative display 104 constitute a second field. The first and second fields constitute one frame.
When the data voltage of FIG. 2(a) is applied and a TFT switch is turned on by the gate voltage of FIG. 2(b), as shown in FIG. 2(c), the transmittance of liquid crystal changes in the manner of damped oscillation such that the liquid crystal becomes alternately light and dark. This is observed as flicker, which has the effect of deteriorating the quality of display. Further, as shown in FIG. 2(c), the transmittance of the liquid crystal converges to a constant level in the second frame (fourth field) following application of the signal voltage.
As a result, the brightness changes in an oscillating manner, as shown in FIG. 3. As described above, even when liquid crystal of high response speed is used, the speed of a display image decreases, because a few frames are required to stabilize the brightness.
The transmittance of liquid crystal after response is determined not by an applied signal voltage but by the amount of charge stored in the liquid crystal serving as a capacitor. The amount of charge depends on a total amount of accumulated charge that exists before the signal is written and of charge that is newly written. The amount of charge accumulated after response also changes depending on design values in relation to pixels such as the physical constants of liquid crystal, electric parameters and an amount of charge accumulation. Therefore, in order to establish correspondence between a signal voltage and transmittance, data, actual calculation, and the like are required for determining (1) the relationship between the signal voltage and an amount of stored charge, (2) an amount of charge present before signal writing operation, and (3) an amount of charge present after response. Therefore, there becomes necessary a frame memory for storing the data regarding (2) for the entire screen, and a calculation section for calculating the data (1) and (3). This is not preferred, because the number of parts of the system increases.
In order to solve the above problem, there is sometimes used a reset pulse scheme, in which a reset voltage is applied to liquid crystal so as to bring the liquid crystal into a predetermined state before new data are written therein.
As an example, a technique described in IDRC, pp. 66-69, 1997 will be described. This technique uses an OCB (optically compensated bi-refligence) mode in which nematic liquid crystal is aligned to obtain a pi-type alignment, and compensation film is attached to the liquid crystal. The response speed of the liquid crystal mode is about 2 to 5 msec, which is considerably faster than that of a conventional TN mode.
Although response is theoretically considered to be completed within one frame, as described above, a few frames are required for attainment of stable transmittance, because a holding voltage greatly decreases due to change in dielectric constant caused by response of the liquid crystal. A method for solving this problem is shown in FIG. 5 of the above literature. In this method, within one frame, a signal for black display is always written after a signal for white display is written. FIG. 5 of the literature is reproduced as FIG. 4. The horizontal axis represents time, while the vertical axis represents brightness. A dotted line shows variation in brightness for the case of ordinary drive and indicates that the brightness reaches a stable level in the third frame.
When the reset pulse scheme is employed, liquid crystal always attains a predetermined state before new data are written therein, and one-to-one correspondence can be observed between a written signal voltage and an obtained transmittance. This one-to-one correspondence simplifies the manner of generation of drive signals and obviates a frame memory or other means for storing previous written information.
In order to apply a reset voltage to liquid crystal, there is used another method which comprises the steps of generating positive and negative data signal voltages for a certain image signal; applying to the liquid crystal the positive (negative) voltage and then the negative (positive) voltage; and subsequently applying a reset voltage to the liquid crystal. In this case, if the positive and negative data signal voltages having the same amplitude are applied, the "step response" as described above occurs. Therefore, a data signal voltage having a waveform shown in FIG. 5(a) is applied to liquid crystal. FIG. 5(b) is a graph showing a variation in transmittance observed at that time. The waveform of a data signal voltage whose negative and positive values have the same amplitude is indicated by a dotted line in FIG. 5(a), and a variation in transmittance when the data signal voltage of FIG. 5(a) is applied to liquid crystal is indicated by a dotted line in FIG. 5(b).
In order to avoid "step response," as shown in FIG. 5(a), the amplitude of a data voltage in a first half of a frame (a positive data voltage in this example) is made small, and the amplitude of the data voltage in a second half of the frame (a negative data voltage in this example) is made equal to that of the waveform indicated by the dotted line. This setting prevents step response, so that, as shown in FIG. 5(b), the same transmittance is obtained in the first and second halves-of the frame. By the subsequent step of resetting the liquid crystal at the end of the frame, the liquid crystal is brought into a predetermined reset state. In a subsequent frame, a new signal voltage having a similar waveform is applied, so that the transmittance of the liquid crystal changes in accordance with the new signal voltage. In this manner, one-to-one correspondence is established between the constant signal voltage and the constant transmittance.
Further, in order to solve these problems, there has been proposed a drive method called "pseudo DC-drive" shown in AMLDC, 97 digest, pp. 119-122.
This technique will be described with reference to FIGS. 6 and 7. Similar to FIG. 2, FIG. 6(a) is a chart showing the waveform of a data voltage; FIG. 6(b) is a chart showing change in a gate voltage; and FIG. 6(c) is a chart showing change in transmittance at that time. FIG. 7 is a timing chart for each scan line, and the color shade in each of positive and negative display periods 102 and 104 represents brightness corresponding to the transmittance of FIG. 6(c). In FIG. 6, a time period of 16.7 ms is indicated by an arrow.
In the literature, a period of 16.7 ms is defined as one frame period. However, since this definition is not generally accepted, the period is changed in the drawings of the present specification (one frame period described in the literature corresponds to one field period used in the present specification with regard to ordinary conventional techniques).
In the "pseudo DC-drive" unlike the case of AC drive as shown in FIG. 2, a data voltage of the same polarity is continuously applied to liquid crystal over a plurality of fields. After the plurality of fields, the polarity of the data voltage is reversed so as to eliminate electrical imbalance. In FIG. 6, after positive writing over four fields, negative writing is performed over four fields to complete display of one image signal. Since writing is performed for each scan line at timing as shown in FIG. 7, an operation of successively writing positive data from the top line is repeated four times, and then an operation of successively writing negative data from the top line is repeated four times.
This method enables attainment of a state in which voltages held at opposite ends of liquid crystal become the same as a constant applied DC voltage. As a result, the holding voltage does not decrease due to response of liquid crystal, and the final transmittance becomes higher than that in the case of AC drive shown in FIG. 2, in which the holding voltage decreases due to response of liquid crystal.
However, in this method, one frame period becomes equal to the total of a plurality of frames of different polarities. That is, in the example shown in FIG. 6, the length of one frame is four times that of the frame in FIG. 2.
Even if any of the reset pulse schemes described above is employed, the conventional reset pulse method has the following problems. First, brightness changes greatly depending on position within a screen which is effected by the timing when the reset operation is performed. For example, when scanning is performed from the top of the screen toward the bottom of the screen, and the reset operation is performed after completion of scanning of all lines; at the top of the screen, a period substantially corresponding to one field is available as a display time after the writing operation, but at the bottom of the screen, only a very short time is available as the display time after the writing operation. This phenomenon is described with reference to FIG. 8.
FIG. 8(a) schematically shows states in a write (scanning) period 101, a display period 102, and a reset period 103 in two dimensions; i.e., the scanning direction of a screen and time axis. In this Figure, eight scan lines are shown, and in the write period 101, scanning is performed successively from the top of the screen toward the bottom thereof. After the display period 102 having a predetermined length, the entire screen is reset at a time during the reset period 103. FIG. 8(b) schematically shows a scan line voltage and transmittance in the uppermost part of the display or on a first (No. 1) scan line when white color is displayed by use of the drive method as described above. FIG. 8(c) schematically shows a scan line voltage and transmittance in the lowermost part of the display or on an eighth (No.8) scan line. In the first scan line, white is displayed during a relatively long period corresponding to a value equal to one frame period less the sum of the reset period and a transient response period. However, in the eighth scan line, since the reset is started simultaneously with the end of the response period, white cannot be displayed sufficiently. As a result, when the entire frame period is considered, as shown in FIG. 9B, there occurs a phenomenon that the top portion of the screen is bright and the bottom portion of the screen is dark. Such a brightness variation within the screen deteriorates image quality considerably.
Next, since the period for bringing the liquid crystal into a predetermined display state always exists, the overall contrast and the maximum transmittance decrease. For example, if the liquid crystal is reset such that the liquid crystal display turns to black, a period available for displaying a certain color other than black becomes shorter than that available when no reset operation is performed, so that the maximum transmittance and the transmittance at each gradation both decrease. If the liquid crystal is reset such that the liquid crystal displays a color other than black, the transmittance at the time of the reset is added when black is displayed and is averaged with respect to time, with the result that the transmittance at the time of black being displayed is increased, and the contrast decreases.
Further, since the period during which the transmittance of the liquid crystal attains a constant level always exists, flicker is generated between that transmittance and a transmittance occurring at the time of another color being displayed. For example, when the entire screen is reset concurrently, flickering occurs over the entire screen, so that a great degree of flicker is observed.
Moreover, the scanning period decreases by an amount corresponding to the length of the reset period. In general, the scanning period (write time) is substantially equivalent to a time obtained through division of the field time, which is half the frame time, by the number of scan lines. However, if a reset period is provided in the field time, the scanning period 101 shown in FIG. 8(a) decreases to a time obtained through division of (the field time minus the reset time 103) by the number (8) of scan lines. As a result, the scanning period becomes shorter. In order to solve the problem that the reset period affects the scanning period, there has been proposed a method in which interlace drive is combined with reset, as shown in, for example, Patent Publication JP-A-92-186217. In this method, a FLC (ferroelectric liquid crystal) panel is driven in an interlace mode, and scan lines are reset in their respective non-display periods. This prevents a decrease in the length of the scanning period. Further, the reset timings of adjacent lines are shifted from each other, and the degree of flicker is considered to decrease due to averaging. However, even when this method is used, the remaining problems, such as variation of brightness within the screen and decrease in the maximum transmittance, cannot be solved.
Meanwhile, in the pseudo DC-drive, as described above, a longer frame period (in the example of FIGS. 6 and 7, a period four times that of an AC drive) is required compared to the AC drive, so that high responsiveness of the liquid crystal cannot be exploited effectively. Consequently, flicker of a long period, which fluctuates at a period a few times that of the ordinary frame period (16.7 ms), is generated of which brightness is shown in FIG. 7.

Liquid crystal display apparatus and method of driving the same


A multiple exercise performance or positioning apparatus comprising a generally upright stationary frame on which is mounted an elongated arm mechanism which is mounted on a pivot mechanism, the arm mechanism extending from a proximal end to a distal end relative to the frame, the pivot mechanism enabling pivoting of the arm mechanism such that the distal end of the arm mechanism is adjustably movable between positions of variable distance away from the frame, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first end interconnected to a handle mechanism which is mounted at the distal end of the elongated arm mechanism, the cable mechanism being interconnected to a weight resistance mechanism such that a user may grasp and pull the handle mechanism against an opposing force exerted by the weight resistance mechanism through the cable mechanism.

Multi functional physical exercise apparati have been designed in the past to incorporate a variety of different subassemblies into a single machine which enable the user to perform a variety of different exercises different for each subassembly. Such conventional multi functional exercise machines provide a limited number of available exercise routines which themselves are limited in the ranges and types of motions that the user may perform.
The present invention relates to exercise apparati generally and more particularly to an exercise apparatus which enables multiple exercise routines in various positions to exercise various muscles or muscle groups at a single station. The apparatus comprises a central support which anchors at least one and typically at least two arm members which are fixedly attached to the support in a spaced apart relationship such that a user/subject may, at a single location or station, engage a grip or handle provided at the end of each arm, the grip or handle being interconnected to a weight resistance mechanism such as a weight stack or a free weight.
The arm(s) are connected to the support in such a manner as to enable the arm(s) to be both rotated and pivoted/tilted. Typically, the arm(s) are rotatable between zero and 180 degree positions in increments (such as increments of twenty degrees) and, typically, the arm(s) are pivotable between zero and forty-five degrees in increments (such as increments of fifteen degrees), wherein the incremental rotation and pivot positions are selectable and reversibly lockable into such incrementally located rotated and pivoted positions by the user.
In accordance with the invention there is provided, a multiple exercise performance or positioning apparatus comprising a generally upright stationary frame on which is mounted an elongated arm mechanism which is mounted on a pivot mechanism, the arm mechanism extending from a proximal end to a distal end relative to the frame, the pivot mechanism enabling pivoting of the arm mechanism such that the distal end of the arm mechanism is adjustably movable between positions of variable distance away from the frame, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first end interconnected to a handle mechanism which is mounted at the distal end of the elongated arm mechanism, the cable mechanism being interconnected to a weight resistance mechanism such that a user may grasp and pull the handle mechanism against an opposing force exerted by the weight resistance mechanism through the cable mechanism.
In accordance with the invention there is provided, a multiple exercise performance apparatus comprising a generally upright stationary frame on which is mounted first and second elongated arm mechanisms for pivoting about first and second pivot axes, the arm mechanisms each extending from a proximal end to a distal end relative to the frame, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first terminal end interconnected to a handle mechanism which is mounted at the distal end of the first elongated arm mechanism, and a second terminal end interconnected to a handle mechanism which is mounted at the distal end of the second elongated arm mechanism, the cable mechanism having a second end interconnected to a weight resistance mechanism such that a user may grasp and pull at least one of the handle mechanisms against an opposing force exerted by the weight resistance mechanism through the cable mechanism.
In accordance with the invention there is provided, a multiple exercise performance apparatus comprising a generally upright stationary frame having a pair of opposing sides and a front face, wherein at least one elongated arm mechanism is mounted on the frame mechanism for rotation about an axis extending forwardly from the front face, the arm mechanism extending forwardly from a proximal end to a distal end relative to the front face, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first terminal end interconnected to a handle mechanism which is mounted at the distal end of the first elongated arm mechanism, and a second terminal end interconnected to a handle mechanism which is mounted at the distal end of the elongated arm mechanism, the cable mechanism being interconnected to a weight resistance mechanism such that user may grasp and pull the handle mechanism against an opposing force exerted by the weight resistance mechanism through the cable mechanism.
In accordance with the invention there is provided, a multiple exercise performance apparatus comprising a generally upright stationary frame on which is mounted an elongated arm mechanism for rotation about a generally horizontal axis, the arm mechanism extending from a proximal end to a distal end relative to the frame, the elongated arm mechanism being mounted to a rotatable member which rotates around the generally horizontal axis, the rotatable member being interconnected to a rotation damping mechanism, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first end interconnected to a handle mechanism which is mounted at the distal end of the elongated arm mechanism, the first end of the cable mechanism being interconnected to a weight resistance mechanism such that a user may grasp and pull the handle mechanism against an opposing force exerted by the weight resistance mechanism through the cable mechanism.
In accordance with the invention there is provided, a multiple exercise performance apparatus comprising a generally upright stationary frame on which is mounted an elongated arm mechanism for rotation about a generally horizontal axis, the arm mechanism extending from a proximal end to a distal end relative to the frame, the elongated arm mechanism being mounted to a rotatable member which rotates around the generally horizontal axis, the rotatable member being interconnected to a tension member which opposes rotation of the rotatable member.
In accordance with the invention there is provided, a multiple exercise positioning apparatus comprising a generally upright stationary support mounted on a mounting surface, at least one arm mechanism, one end of the arm being fixedly interconnected to the support at a selected height above the mounting surface, the one end of the arm being coupled to the support such that the arm is both rotatable and pivotable relative to the support, wherein the arm has another distal end which is stationarily positionable in a plurality of selected exercise positions via one or both of rotation and pivoting of the arm.
In accordance with the invention there is provided, a multiple exercise performance apparatus comprising a generally upright stationary frame having at least one elongated arm mechanism mounted on the frame mechanism for rotation about an axis extending outwardly from the frame, the arm mechanism extending outwardly from a proximal end to a distal end relative to the frame, wherein a cable mechanism is mounted around one or more pulleys, the cable mechanism having a first terminal end interconnected to a handle mechanism which is mounted at the distal end of the first elongated arm mechanism, and a second terminal end interconnected to a handle mechanism which is mounted at the distal end of the elongated arm mechanism, the cable mechanism being interconnected to a weight resistance mechanism such that user may grasp and pull the handle mechanism against an opposing force exerted by the weight resistance mechanism through the cable mechanism.
In accordance with the invention there is provided, in a multiple exercise positioning apparatus comprising a generally upright support having an elongated arm mechanism pivotably and rotatably mounted to the upright support wherein the elongated arm mechanism has a cable interconnected between a handle disposed at a distal end of the arm and a weight resistance mechanism which is actuated by pulling on the handle, a method of performing any one of a selected number of differently positioned or oriented exercises with the apparatus comprising positioning the elongated arm in a selected position of rotation around an axis of rotation of the arm, positioning the elongated arm in a selected position of pivot about an axis of pivot of the arm, manually pulling on the handle so as to exert an opposing force to the weight resistance mechanism through the cable.

Multiple exercise apparatus having an adjustable arm mechanism


A lighting control system comprises a smart device, at least one luminaire assembly, and a server. A user operates a client app installed on the smart device to communicatively with the server to further control the at least one luminaire assembly. The server comprises a database module, a brightness control module for implementing automatic brightness variations, a mode switching module for cooperating with at least sensor disposed in the at least one luminaire assembly to implement different ambient lighting controls, and a brightness compensation module for cooperating with a light sensor disposed on the smart device to implement ambient lighting control.

1. Field of the Invention
The present invention relates to lighting control and, more particularly, to a lighting control system.
2. Description of the Prior Art
A conventional lighting control system comprises luminaires, a gateway, a server, and a remote controller. The luminaires are wired to the gateway, and the gateway is wired or wirelessly connected to the server. A user may use the remote controller to transfer commands to the server, and then the server controls, via the gateway, the luminaires according to the commands. However, the conventional lighting control system has some disadvantages as follows.
First, the installation is inconvenient because the luminaires are connected to the gateway via physical wiring so that the amount of the physical wiring increases as the number of the luminaires increases, resulting in the increased complexity of the installation. Second, brightness variations of the luminaires are inadequate because the turn-on or turn-off of the luminaires is only controlled by the user so that the brightness of the luminaires does not automatically vary. Third, the conventional lighting control system is still focused on manually controlling the lighting. Users still have to monitor and operate the system by the remote controller. Fourth, the cost would be increased. If an additional function such as ambient lighting control is requested, additional components such as light sensors and additional wiring are needed, resulting in the increased complexity of the installation. Fifth, the conventional lighting control system has a narrow range of applications because it simply introduces a wireless network into a more conventional manual-switching lighting control system.


An aggregation channel for providing data communication for M data streams to N data streams comprises a first first-in, first-out (FIFO) buffer module that receives the M data streams and realigns them with each other based on respective alignment symbols. A lane mapping module receives the realigned M data streams from the first FIFO buffer module and routes predetermined ones of the M data streams to predetermined ones of the N data streams, wherein each of the N data streams receives at least one of the alignment characters. M is greater than N, N is greater than 1, and each of the M data streams includes an alignment symbol.

Digital systems employ network connections and/or data buses, referred to collectively as communication channels, to communicate between various subsystems. For example, a central processing unit may communicate with a disc storage module through a channel. The bandwidth of the channel is determined by several factors including a number of parallel communication lanes in the channel. A given digital system can employ a number of various channels between its subsystems, with each channel being best suited to its particular application in the digital system.
In some circumstances, it is necessary for data to travel over more than one channel as it propagates from one subsystem to another. In such instances a first-in, first-out (FIFO) buffer can be employed between the two communication channels provided that they are both serial communication channels and/or clocked parallel channels.
In some cases the first channel includes a plurality of lanes that are not synchronized by a clock and the second channel is a serial channel. In such a case the data on each lane of the first channel can include an alignment symbol that is read by a buffer between the first channel and the second channel. The buffer can use the alignment symbols in the lanes to eliminate skew between the data arriving over the first channel, and then aggregate the realigned data onto the serial second channel.


Technologies are generally described herein for electrocaloric effect heat transfer devices and methods effective to facilitate heat transfer over a wide operating temperature range of a corresponding heat source. Some example heat transfer devices may include multiple heat transfer stacks with at least two heat transfer stacks having electrocaloric effect materials with varying effective temperature ranges. The combined effective temperature ranges of the multiple heat transfer stacks encompass the operating temperature range of the heat source.

Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Electrocaloric effect materials are materials that experience a temperature change when subjected to an applied voltage. This temperature change is reversible upon the removal of the applied voltage. By physically connecting and disconnecting electrocaloric effect material to and from a heat source, and creating a unidirectional heat transfer path, a heat pump can be created for transferring heat away from the heat source.
The present disclosure appreciates that the electrocaloric effect and other materials used in various types of heat pumps may experience various performance efficiencies at various operating temperatures. As a result, the performance of an electrocaloric effect material heat pump may undesirably change throughout the operating temperature range of a heat source to which the heat pump is thermally connected. Consequently, a conventional electrocaloric effect material heat pump may not be suitable for use with a heat source operating within a relatively wide temperature range.

Heterogeneous electrocaloric effect heat transfer device


The invention concerns a piston compressor cylinder arrangement (1), particularly for a hermetically enclosed refrigerant compressor, with a cylinder body (2) and a cylinder head arrangement (7), the cylinder body (2) having a first front side (6) in the area of the cylinder head arrangement (7) and a second front side (8) at the other end. It is endeavoured to manufacture such a cylinder arrangement in a cost-effective manner without having to fear for a deformation during mounting. For this purpose, a cup-shaped mounting sleeve (9) surrounds the cylinder body (2) over its full axial working length with a radial distance on all sides.

Such a cylinder arrangement is, for example, known from DE 39 01 588 A1. In the area of its first end, the cylinder body has a circumferential projection. An edged mounting ring engages this projection and the cylinder head arrangement.
U.S. Pat. No. 6,095,768 discloses a further, similar refrigerant compressor. The cylinder body has a cylinder pipe, which is provided with two axially protruding ribs over its full axial length. By means of these two ribs, the cylinder body is welded onto a mounting rail of the compressor block.
EP 0 524 552 A2 shows a similar embodiment, in which a cylinder is located on a housing part, the cylinder having in the area of its first front side a radially extended flange, on which a valve plate is fixed.
EP 0 507 091 B1 shows a cylinder pipe, which is guided through and connected with a block-like housing.
Large numbers of refrigerant compressors are used in refrigeration appliances, that is, refrigerators, freezers or vending machines. Here, it is endeavoured to achieve the best possible efficiency. In order to achieve a good mechanical efficiency, it is required that a piston reciprocating in a cylinder formed inside the cylinder body fits as exactly into this cylinder as possible. Accordingly, the tolerances have to be small.
At the same time, it is desired to make the production of such refrigerant compressors as cost-efficient as possible. The more cost-effective the manufacturing process is, the larger is the risk that narrow tolerances will not be observed. Particularly, there is a risk that the cylinder body is deformed and then no longer "fits" with the piston.

Piston compressor cylinder arrangement, particularly for a hermetically enclosed refrigerant compressor


A random number generating device of the present disclosure includes: an arithmetic random number generator that generates an arithmetic random number sequence; an arithmetic random number converter that sequentially reads at least one arithmetic random number from the arithmetic random number sequence and converts a value of the read arithmetic random number into a voltage or current value of at least two predetermined levels of gray scale having an identical polarity; a hysteresis unit that outputs values depending on a presently-input voltage or current value and a previously-input voltage or current value with respect to the sequentially-input voltage or current value; and a threshold processor that binarizes the output of the hysteresis unit.

1. Field of the Invention
The present disclosure relates to a random number generating device used in general random number applications such as a random number key and personal authentication.
2. Description of the Related Art
Conventionally, a method in which a physical thermal noise is used and a method in which an arithmetic random number is used are well known as the random number generating device.
For example, Japanese Patent Publication No. 4,625,936B proposes a random number generating device in which the physical thermal noise is used. FIG. 26 is a view illustrating an outline configuration of the conventional random number generating device in which the thermal noise is used, and FIG. 27 is a view illustrating a method for driving the random number generating device in FIG. 26. In the conventional random number generating device of FIG. 26, a set pulse current from set current setting unit 104 and a reset pulse current, which has a reversal polarity of the set pulse current, from reset unit 103 are alternately passed through magnetoresistive element 102 to change resistance of magnetoresistive element 102, thereby generating a random number. In the random number generating device of FIG. 26, a magnetization direction of a magnetization free layer in magnetoresistive element 102 is initialized by passing the reset pulse current. FIG. 28 is a view illustrating a method for controlling the random number generating device in FIG. 26. According to Japanese Patent Publication No. 4,625,936B, in the random number generating device of FIG. 26, after the magnetization direction is substantially aligned in one direction by passing the reset pulse current through magnetoresistive element 102, a pulse current (set pulse current) having a current value in which a cumulative magnetization reversal probability becomes 0.5 is added, whereby magnetoresistive element 102 can make the random number generating device in which both an event probability of a low-resistance state (an event corresponding to "0") and an event probability of a high-resistance state (an event corresponding to "1") become 0.5. In the random number generating device of FIG. 26, the current value in which the cumulative magnetization reversal probability becomes 0.5 is decided by previously measuring a characteristic in FIG. 28. At this point, because the magnetization reversal actually obtained in magnetoresistive element 102 varies due to the thermal noise, the random number can be obtained by detecting a change in the resistance state of magnetoresistive element 102.
On the other hand, Japanese Patent Publication No. 4,828,068B proposes a random number generating device in which the arithmetic random number is used. FIG. 29 is a view illustrating an outline configuration of the conventional random number generating device in which the arithmetic random number is used. The random number generating device in FIG. 29 is called a linear feedback shift register (LFSR) that is frequently used to generate the arithmetic random number. As illustrated in FIG. 29, the linear feedback shift register can generate the arithmetic random number with a simple circuit configuration. It is clear that a generation frequency of the arithmetic random number is unbiased (the event probabilities of 0 and 1 are substantially equal to each other).
The conventional random number generating devices each have the following problems. For example, in the random number generating device of Japanese Patent Publication No. 4,625,936B in which the physical thermal noise is used, magnetoresistive element 102 has temperature dependence, or a temporal change in the characteristic is generated, which results in a problem in that the generation frequency is biased. Actually, in the random number generating device of Japanese Patent Publication No. 4,625,936B, the random number generated by the magnetization reversal of magnetoresistive element 102 is input to integrator 106 through comparator 105, and output of integrator 106 is input to error amplifier 107, thereby adjusting the magnetization reversal probability. However, it is necessary to separately provide an adjustment circuit in order to obtain the configuration, which results in a problem in that the circuit is complicated. Additionally, the magnetization reversal probability is adjusted after the random number is generated, which results in a problem in that a bias still remains in a short term.
In the random number generating device of Japanese Patent Publication No. 4,828,068B in which the arithmetic random number is used, although the bias of the generation frequency is not generated, there is a problem in that the generated arithmetic random number sequence has a periodic characteristic. Due to the periodic characteristic, possibly decipher is easily completed in the case where the arithmetic random number sequence is directly used in cipher.

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A centralized arbitration mechanism provides that a router switch fabric is configured in a consistent fashion. Remotely distributed packet forwarding modules determine which data chunks are ready to go through the optical switch and communicates this to the central arbiter. Each packet forwarding module has an ingress ASIC containing packet headers in roughly four thousand virtual output queues. Algorithms choose at most two chunk requests per chunk period to be sent to the arbiter, which queues up to roughly 24 requests per output port. Requests are sent through a Banyan network, which models the switch fabric and scales on the order of NlogN, where N is the number of router output ports. Therefore a crossbar switch function can be modeled up to the 320 output ports physically in the system, and yet have the central arbiter scale with the number of ports in a much less demanding way. An algorithm grants at most two requests per port in each chunk period and returns the grants to the ingress ASIC. Also for each chunk period the central arbiter communicates the corresponding switch configuration control information to the switch fabric.

A router system with a centralized switch fabric at its core requires that the entire switch be configured in an internally consistent way. A fabric is a collection of devices which cooperatively provide a general routing capability. In order to scale to a large router with several hundred ports, it is necessary to have a router switch fabric with uniform scaling properties. One example of a fabric with these properties is a centralized crossbar. Electrical crossbars typically have scalability limitations, limiting the size to tens of ports at a maximum. Previous IP routers have been unable to take advantage of optical switch technology due to their size and reconfiguration speed limitations. In order to utilize an optical switch for the fabric of an IP router, the fabric must be able to change configurations quickly enough to efficiently route the shortest IP packet, within on order of tens of nanoseconds. Present optical switch technology requires milliseconds for reconfiguration. Additionally, present optical switch technology is severely limited to just a small number of ports, such that an optical switch is unable to scale to large numbers of inputs and outputs.
In order to scale to larger systems, prior routers have resorted to distributed switching fabrics. These fabrics typically have multiple arbitration points to traverse the fabric, resulting in increased fabric latency and congestion hot spots within the fabric. Multiple packet forwarding modules are distributed around such a system in remote racks. The packet forwarding modules are responsible for organizing data packets from the input ports to be passed through the switch fabric.
In a future large router system, the number of input and output ports can reach several hundred. Packet forwarding modules are remotely distributed over a wide area. Complex switching is required, with long latency or delay times in passing information through the router system accurately with a high throughput. In such an environment, an arbitration system is needed to handle high data throughput and provide a consistently high connection rate of data with the switch fabric.

System and method for router central arbitration


A motion information output portion acquires horizontal motion information concerning a line where the telop is present. From a signal of the current frame and motion-compensated signal components of frames which are present before and after the current frame. A decision information acquisition portion and a binarizing processing portion obtains a flag indicating whether each pixel of a screen is pixel at edge position of the telop. Based on this flag, an edge pixel extraction portion extracts pixel data of the edge position. A histogram processing portion uses this pixel data as a material to create a histogram for each item of data, thereby determining values of the pixel data corresponding to the telop from a class having a largest frequency. An extraction region selection portion obtains another flag indicating a line where the telop is present. An extraction portion extracts pixel data corresponding to the telop.

1. Field of the Invention
The present invention relates to an apparatus and a method for extracting artificial image such as a telop from an input image signal and a program for performing the method. Particularly, it relates to an apparatus and the like for extracting pixel data corresponding to the artificial image from the input image signal whose each piece of the pixel data is constituted of multiple items of color data.
2. Description of Related Art
In TV broadcasting, a moving telop (characters) has used to display a news flash and the like on a screen. If pixel data corresponding to an artificial image including such a telop is extracted from an image signal, it is possible to utilize this pixel data by, for example, accumulating it in a hard disk drive (HDD).
Conventionally, an apparatus has been proposed which extracts pixel data corresponding to a telop from an image signal (see Japanese Patent Application Publication No. 2000-182053). In this case, by utilizing telop properties of high luminance and color saturation with respect to a background, an edge position of a telop is detected on the basis of luminance and color saturation values. An average and a variance of luminance and color saturation values of a telop region including this edge position are then obtained, so that based on these average and variance, pixel data corresponding to the telop is extracted from an image signal.
Thus, the conventional apparatus detects an edge position of the telop based on luminance and color saturation values. It, however, cannot accurately detect the edge position of the telop on a level of the luminance and color saturation values. It is feared that only pixel data corresponding to the telop cannot be extracted from an image signal properly.
It is an object of the present invention to provide an apparatus and the like for extracting only pixel data corresponding to an artificial image properly from an input image signal.

Apparatus and method for extracting artificial images and program for performing the method


A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.

1. Technical Field
The embodiments herein relate to a semiconductor integrated circuit, and more particularly to a receiver circuit that can be used in a semiconductor integrated circuit to increase operational speed and integration.
2. Related Art
The increasing processing speed of modern computers has increasingly required low-power, high-speed semiconductor integrated circuits. Due to this trend, in recent years, a multi level or a multi bit technology that achieves high storage density has been used as an information transmission technology between a semiconductor integrated circuit and a broader system. Multi level technology represents data using a plurality of signal levels and bits, instead of represented binary information using two levels, i.e., high and low.
For example, unlike conventional memory circuits in which unit cell that stores only high-level or low-level information, a unit cell in a multi level memory circuit can store data using four voltages or more.
However, conventional multi-level technology requires large amounts of power and can produce errors due to signal distortion during a high-speed operation.
A conventional receiver circuit acts as the interface circuit between the broader system and the particular integrated circuit. The receiver circuit is responsible for receiving signals to be input to the integrated circuit, buffering them, and then forwarding them to internal portions of the circuit. The receiver should transmit the signals to the internal circuits without generating additional signal distortion. Therefore, equalization is often used to ensure adequate signal margin and/or to compensate for signal attenuation losses.
In relation to the above, related technologies have been disclosed in "A Reconfigurable Fully-Integrated 0.18-gm CMOS Feed Forward Equalizer IC for 10-Gb/sec Back Plane Links" (ISCAS 2006), in which a Feed-Forward Equalization (FFE) architecture is described, and "8-Gb/s Source-Synchronous I/O Link With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew" (IEEE JSSC Vo. 40), in which a Decision Feedback Equalization (DFE) is described. However, such implementations are complicated and require a large circuit area. Additionally, FFE implementations tend to amplify signal noise in addition to the data information, which can be problematic.

Low power, high speed receiver circuit for use in a semiconductor integrated circuit


An apparatus for estimating a property of an earth formation includes: a carrier configured to be conveyed through a borehole penetrating an earth formation; a first fractal-shaped antenna element disposed on the carrier and configured to at least one of transmit electromagnetic energy into the formation and receive electromagnetic energy from the formation; and a second fractal-shaped antenna element electrically connected to the first fractal-shaped antenna element at a connection and configured to at least one of transmit electromagnetic energy into the formation and receive electromagnetic energy from the formation; wherein the second fractal-shaped antenna element is substantially a mirror image of the first fractal antenna element with respect to a reflection about the connection.

Earth formations may be used for various purposes such as hydrocarbon production, geothermal production, and carbon dioxide sequestration. In order to efficiently use an earth formation, the formation is characterized by performing measurements of many different properties using one or more tools conveyed through a borehole penetrating the formation. One category of tools includes tools that measure electrical characteristics of the earth formation such as resistivity or dielectric constant. Conventional resistivity and dielectric tools typically use a coil as an antenna to transmit electromagnetic signals into or receive electromagnetic signals from the formation in order to measure the resistivity or dielectric constant. Due to the physical size constraints, the desired transmitting efficiency for probing deep into the formation may be compromised. Hence, it would be well received in the drilling and geophysical exploration industries if designs of resistivity and dielectric tools could be improved to probe deeper into earth formations.

Use of a fractal antenna in array dielectric logging


Methods and apparatus are disclosed for the processing of frame buffer data, such as color buffer data, in graphics processing applications. Although more generally applicable, these methods and apparatus are particularly useful in real-time, polygon-based, 3D rendering applications. An exemplary method for processing graphics data according to one or more embodiments of the invention begins with the retrieval, from a buffer, of pixel values corresponding to a tile of two or more pixels, and with the updating of one or more of those updated pixel values. The updated pixel values are selectively compressed using a lossy compression operation or a lossless compression operation, based on an accumulated error metric value for the tile. If lossy compression is used, then the accumulated error metric value for the tile is updated; in either event, the compressed pixel values are stored in the frame buffer for further processing. With this approach, the accumulated error caused by successive, or tandem, compression operations may be limited to a pre-determined maximum.

The present invention generally relates to the processing of graphics data, and particularly relates to methods and apparatus for compressing frame buffer data in a three-dimensional (3D) graphics rendering system.
3D graphics rendering systems typically utilize several memory buffers during the rendering process, such as texture buffers, depth buffers (often called z-buffers), and color buffers. These buffers often are stored in random-access memory (RAM) external to the graphics processing unit (GPU), which may have relatively small cache memories on board. Because the buffered data may be retrieved and re-written several times during the rendering process, the memory bandwidth (the capacity for writing data to memory and reading data from memory) must often be quite high, especially to support real-time graphics processing applications such as real-time games. On a desktop personal computer, the available memory bandwidth might be very high, perhaps several gigabytes per second. In a mobile phone, several hundred megabytes per second of data transfer might be available.
Even with these high available memory bandwidths, the performance of a GPU might nonetheless be constrained by the memory bandwidth. Reducing the amount of data retrieved from and written to the external RAM is thus generally advantageous. The advantages of reducing memory transactions are particularly pronounced in mobile platforms, such as a mobile telephone, since the increased clock rates and wider data buses required to support very high memory bandwidths also result in increased power consumption, draining batteries more quickly.
Data compression is one approach to reducing the memory bandwidth required to support advanced 3D rendering applications. Lossless data compression techniques, which permit the reconstruction of the original data without any loss of information, are sometimes used today in 3D graphics rendering applications. Lossy data compression algorithms, which can provide significantly higher compression ratios but which may result in the introduction of visual artifacts in the reconstructed data, are commonly used in video applications, such as digital television, but appear to have been neglected with respect to compressing the color buffer in 3D rendering applications.
One reason for avoiding lossy compression schemes in 3D rendering applications is that it is possible to introduce large errors into the color buffer data when lossy compression is used several times. The need for repeated compression and decompression operations distinguishes many 3D graphics rendering applications from digital video applications, for instance, where a given frame is typically compressed just once. Some or all of the color buffer data for a single frame may be compressed and decompressed several times during the graphics rendering process. In a triangle-based 3D rendering system, for example, several triangles may be successively written to a segment (e.g., a tile, or block) of data. Each time, the segment of data may be retrieved from the frame buffer, decompressed, processed, compressed again, and written back to the color buffer. If lossy compression is used to compress the data segment each time, this tandem compression may result in repeated losses of information, introducing unacceptable errors into the final data.

Frame buffer compression and decompression method for graphics rendering


A semiconductor memory device 10 having sense amplifiers where the latch transistor moat region width is increased for the same sense transistor pitch. Each sense amplifier comprises latch transistors having a moat region and a gate region comprising a plurality of gate fingers where the length of the gate fingers is determined by the pitch of the sense amplifier. Adjacent latch transistors are offset from one another in both the horizontal and vertical directions and the gate fingers of those latch transistors are interleaved such that the latch transistors have wider moat regions while maintaining the sense amplifier latch transistor pitch. The resulting structure increases the sensing performance while maintaining the pitch.

Sense amplifiers are commonly used in semiconductor memory devices to sense and amplify a potential difference between paired bit lines. FIG. 1 shows a circuit diagram of the latch portion of a conventional sense amplifier, indicated generally at 4, formed by N-channel transistors M.sub.1 and M.sub.2 and P-channel transistors M.sub.3 and M.sub.4 where N.sub.1 and N.sub.2 are the paired bit lines, NC is the N-channel drive line, and PC is the P-channel drive line.
It is a generally desirable goal in semiconductor fabrication to reduce the size of semiconductor devices. This holds true for semiconductor memory devices such as Dynamic Random Access Memory (DRAM) devices. In a typical DRAM device, a sense amplifier must fit in the width of two bit line pairs which limits the sense amplifier width to four times the bit line pitch. This limitation on the pitch of sense amplifiers also limits the width of the sense amplifier latch transistors.
As the latch transistor width decreases, the sensing speed and performance of the sense amplifier also decreases. Thus, in a conventional memory device, the pitch of the memory bit lines limits the performance of the sense amplifiers by limiting the width of the latch transistors.

Semiconductor memory device having sense amplifiers with offset latch transistors and interleaved gate fingers


Various apparatuses and methods relate to coolers or other containers having attachment features to which modular accessories may be attached. Various apparatuses and methods relate to wheel and modular accessory attachment systems for attaching to a cooler or other container. Various apparatuses and methods relate to rails and channels for sliding attachment couplers. Various apparatuses and methods relate to keyed male-female attachment couplers. Various apparatuses and methods relate to a chassis configured to adjust in size for adapting the chassis to fit a variety of container sizes. Various apparatuses and methods relate to a coupler assembly for mechanically securing a container to a container undercarriage system.

Outdoor activities are a pastime for many people who enjoy being active and present out in nature. Some people may spend at least a portion of their leisure time hiking in the woods, lounging on a beach, boating on a lake, or playing at a park, for example. When people participate in recreational activities like the ones described above, they often like to bring various utilitarian devices and leisure-facilitating consumer goods that may increase and/or augment the enjoyment of these recreational activities. For example, some people bring floats or paddle boards to a beach or a river for recreational enjoyment. Some people may receive significant satisfaction from carrying ice chests filled with cool drinks to an outdoor concert. Yet other people may spend their leisure time camping in the woods using an array of utilitarian items and survival gear.
Various brands in the marketplace today have branded themselves as so-called "lifestyle brands." A lifestyle brand may be a brand that endeavors to embody the values, interests, attitudes, and/or opinions of a group or a culture for marketing purposes. While each lifestyle brand may satisfy a specific place in the marketplace, there are many lifestyle brands that appeal to the segment of the market that enjoys outdoor recreation and other associated activities. For example, the North Face® brand is a highly recognizable brand known as being a "mainstay" outerwear brand. Coleman® is another popular outdoor brand known for providing an array of outdoor products (including camping tents, for example). Yet another brand known for its lifestyle appeal is the YETI® brand, known for selling high-end coolers, as well as other items such as drinkware and apparel. Various outdoor and lifestyle brand companies may produce or distribute a wide array of useful outdoor items, including tents, backpacks, sleeping bags, lanterns, camp chairs, knives, and containers, for example.
Like reference symbols in the various drawings indicate like elements.

Adaptable modular attachment and accessory system for use with coolers, bait buckets and other containers


An ESD protective circuit having a contact terminal, a first supply voltage terminal for a first supply potential, a second supply voltage terminal for a second supply potential, a transistor chain having several transistors, wherein drain terminals of the transistors are connected to one of the supply voltage terminals, wherein the control terminal of a first transistor of the transistor chain is connected to the other supply voltage terminal, wherein the source terminal of the last transistor of the transistor chain is connected to the contact terminal, and a current source which is connected to a source terminal of at least one of the transistors of the transistor chain and is able to provide a current which compensates, up to a maximum tolerable voltage deviation from the first or second supply potential at the contact terminal, a current flowing into or from the source terminal.

Electrostatic discharge is, for example, an electrical current impulse that, triggered by a great difference in potential, can flow through electrically conducting, but also through a normally electrically insulating material.
Integrated circuits (ICs) are often damaged by voltage peaks that overload active elements within the integrated circuit and can cause permanent damage. When, for example, a body having static electricity contacts metallic pins of an IC, it will discharge a high voltage through the metallic pins of the IC, that may result in its internal circuit being damaged. Electrostatic discharge can also cause an electrical system to lose its effectiveness.
An ESD protective circuit can prevent damaging effects of electrostatic discharge. At the same time, an ESD protective circuit must be able to withstand the energy of the electrostatic discharge in order not to be damaged itself. Furthermore, an ESD protective circuit should only intervene if there is electrostatic discharge.
In normal operation of the integrated circuit, i.e. when there is no electrostatic discharge at the input/output contact of the IC, it is advantageous for reasons of current consumption of the integrated circuit when no or only a low current flows through the input/output contacts of the IC. Low currents through the input/output contacts will only be demanded if the circuit to be protected is energized, i.e., in operation. Signals from sensors that are either supplied from a different supply voltage than, for example, evaluating ICs to be protected, or signals in which overvoltages or undervoltages at the input/output contacts of the evaluating IC may arise due to shifts of reference potentials on long lines, may allow the input voltages of the IC to exceed an upper supply voltage (VDD) or fall below a lower supply voltage (VSS). Thus, an ESD protective circuit should be dimensioned such that it comprises only low input currents at input voltages to be tolerated slightly over the upper supply voltage (VDD) or slightly below the lower supply voltage (VSS).

ESD protective circuit having low leakage current


Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture. Additional inventive elements conveyed include: an architectural overview of a communications processor; a data path protocol support model for a communications processor; an exemplary network processor employed as the core packet processor for the communications processor; an exemplary rings-based SOC switch fabric architecture; and a variety of quality of support features.

The present invention relates generally to data communication networks and, more particularly, to receiving and transmitting systems, including ATM and other types of communications platforms and including such components as communications processors, packet processors, network processors, DMAs, FPGAs and other devices and peripheral devices.
The number of business and private home users of computers continues to rapidly grow, with these users typically being connected to local area networks (LANs), wide area networks (WANs), intranets, extranets, direct subscriber line (DSL) networks, etc. With growing demand from such users for increasingly large amounts of data across such networks, bandwidth and data processing and handling speed is an ever-present concern facing service and equipment providers to this vast audience of users. Hubs, routers, modems and switches have been the predominant mechanisms for providing the interconnectivity for many users to access networks. Switches made up of expensive VLSI (very large scale integration) circuits are often used to build out networks. In addition to the drawbacks presented by the expense of implementing such circuits, clock synchronization is of continuing concern in switched networks.
With the proliferation of the digital age, a significant demand has arisen for versatile networking technology capable of efficiently transmitting multiple types of information at high speeds across different network environments. One increasingly popular platform is Asynchronous Transfer Mode, commonly referred to as ATM, which was developed by the International Telegraph and Telephone Consultative Committee (CCITT), and its successor organization, the Telecommunications Standardization Sector of the International Telecommunication Union (ITU-T). ATM is a technology capable of high speed transfer of voice, video, and other types of data across public and private networks. Although widely implemented, ATM is just one example of many platforms used in handling communications and data across networks.
ATM utilizes very large-scale integration (VLSI) technology to segment data into individual packets (also referred to as cells). For example, B-ISDN calls for packets having a fixed size of fifty-three bytes (i.e., octets). Using the B-ISDN 53-byte packet for purposes of illustration, each ATM cell includes a header portion comprising the first five bytes and a payload portion comprising the remaining forty-eight bytes. ATM cells are routed across the various networks by passing though ATM switches, which read addressing information included in the cell header and deliver the cell to the destination referenced therein. Unlike other types of networking protocols, ATM does not rely upon Time Division Multiplexing (TDM) to establish the identification of each cell. Rather, ATM cells are identified solely based upon information contained within the cell header.
Further, ATM differs from systems based upon conventional network architectures such as Ethernet or Token Ring in that rather than broadcasting data packets on a shared wire for all network members to receive, ATM cells dictate the successive recipient of the cell through information contained within the cell header. A specific routing path through the network, called a virtual path (VP) or virtual circuit (VC), is set up between two end nodes before any data is transmitted. Cells identified with a particular virtual circuit are delivered to only those nodes on that virtual circuit. In this manner, only the destination identified in the cell header receives the transmitted cell.
The cell header includes, among other information, addressing information that essentially describes the source of the cell or where the cell is coming from and its assigned destination. Although ATM evolved from TDM concepts, cells from multiple sources are statistically multiplexed into a single transmission facility. Cells are identified by the contents of their headers rather than by their time position in the multiplexed stream. A single ATM transmission facility may carry hundreds of thousands of ATM cells per second originating from a multiplicity of sources and traveling to a multiplicity of destinations.
The backbone of an ATM network generally consists of switching devices capable of handling the high-speed ATM cell streams. The switching components of these devices, commonly referred to as the switch fabric, perform the switching function required to implement a virtual circuit by receiving ATM cells from an input port, analyzing the information in the header of the incoming cells in real-time, and routing them to the appropriate destination port. Millions of cells per second often need to be switched by a single device.
This connection-oriented scheme permits an ATM network to guarantee the minimum amount of bandwidth required by each connection. Such guarantees are made when the connection is set-up. When a connection is requested, an analysis of existing connections is performed to determine if enough total bandwidth remains within the network to service the new connection at its requested capacity. If the necessary bandwidth is not available, the connection is refused.
The design of conventional ATM switching systems involves a compromise between which operations should be performed in hardware and which in software. Generally, but not without exception, hardware gives optimal performance but reduces flexibility, while software allows greater flexibility and control over scheduling and buffering and makes it practical to have more sophisticated cell processing (e.g., OAM cell extraction, etc.).
The various protocols associated with platforms such as ATM, Ethernet and others are distinct and require special handling, which is essentially transparent to the user. One approach to packaging the hardware and software necessary to handle the protocol processing and general communications and data processing is system on a chip (SOC), which typically is made up of several modules, often dedicated to specific tasks, working together. A number of these modules typically are interfaces to the external environment, such as Ethernet or Utopia. Others modules can include processors or memories. To illustrate, FIG. 1 shows a typical SOC 10, such as a communications processor, having a variety of modules, such as CPUs 14, 22, RAM 16, Ethernet interface 18, i/o interface 20, and DMA 24, interconnected via a switch fabric 12.
The challenge currently faced by system designers is integrate the modules into a cohesive system. The usual approach is to define busses, connect the modules on the busses, run signals between the modules via the busses, add bridges to connect busses, and so on. Other challenges to designing a SOC, among others, include: heterogeneous peripheral devices; several active modules (CPU, DMA); performance bottlenecks; performance organization of connectivity and busses; customer reality changes over life of a project; design verification bottleneck, both intra-module and inter-module; and application verification. As demonstrated, these challenges result in a considerable number of mechanisms needing to be debugged during the design of a SOC.
Although the traditional bus oriented approach is extensively utilized, such an approach typically has the following problems: a number interfaces to debug for both timing and logic; architectural decisions typically need to be done early in design busses often create unpredictable timing and loadings; changing anything, like adding peripheral or deleting CPU requires considerable revamping of the system; and so on.
A communications processor is one example of a communications system commonly designed using the traditional buss approach. A robust SOC communications processor may find a myriad of applications, such as for modems, bridges, routers, gateways, multi-service gateways and access equipment, and so forth. Such a communications processor may be PHY [Physical layer]-independent, in which case it will be coupled with an appropriate PHY product, or it may by PHY-integrated, in order to provide the connectivity to the PHY layer of the ATM (or OSI [Opens Systems Interconnection]) layered protocol model. It can be readily appreciated that if such a SOC communications processor is to be robust in terms of the applications it can support, it must be able to process a wide variety of different protocols, such as ATM, FR (Frame Relay), IP (Internet Protocol), TDM, and so forth. Therefore, in such a SOC communications processor, a packet processor for processing the packets of information that may be of a variety of protocols may be implemented.
The processing of packets or cells performed by the packet processor may include the following tasks: packet header analysis (OSI Layer2, Layer3); frame validity—CRC (Cyclic Redundancy Code) check; forwarding decision—look up; header modification/conversion; segmentation and reassembly; data conversion (e.g., encryption); statistics gathering; and so on. In fact, as bandwidth requirements go up, and the demand for wire speed packet processing exists, packet processors have to be optimized to solve packet processing specific tasks. Proposed solutions for packet processing that exist today range from hard wired ASICs (Application Specific Integrated Circuits) (typically inflexible) to programmable packet processors (more flexible).
In the last few years, there has been a need for programmable packet processors for communication systems. The major advantages to programmable solutions can include: flexible adjustment for rapidly changing communication standards; implementation of increasingly complex communications difficult to implement in an ASIC; and consideration to differentiation and Time To Market (TTM) as a crucial aspect in today competitive environment.
From the system vendor's vantage, programmable packet processors generally have an advantage over ASIC solutions. A programmable packet processor can be viewed as a platform to be quickly deployed (in consideration of TTM) and then later one can add/modify system functionality by changing/adding code to the packet processor. The trade-off system vendors would have at the very high end solutions (core rate OC [Optical Carrier]-48, OC-192, for example) would be power and performance in programmable packet processors as compared to fixed ASIC solutions. However, several companies have announced programmable solutions for such core rates, indicating that a programmable solution is needed by vendors for such core rate products.
A programmable packet processor (also referred to as a network processor) would preferably provide a solution in the access space where the expected aggregate bandwidth is in the range of OC-3 to OC-12. Of course, the access market requirements are different from the network edge, and the core. At the access points, systems would need to deal with lots of subscribers (ports), low speed links (T1, xDSL [x Digital Subscriber Line]) and with different access methods (ATM, IP, FR, TDM, etc.), whereas at the edge and the core of the network generally would use one framing solution (MPLS, IP or ATM). Access systems, in this case, typically would be characterized by: a large number of subscribers (ports, flows), high density; requirements for Inter Working Functions (IWFs), such as voice (TDM) to packets (ATM or IP) (e.g., Voice gateways), MAN (Metropolitan Area Network) to WAN (Wide Area Network), Ethernet to ATM or PoS [Packet Over SONET]; data grooms—asymmetric behavior large pipe to many small pipes; and the like. Accordingly, access systems need lots of packet manipulation, especially on media conversions and IWF. Therefore, a programmable (and therefore flexible) packet processor often is a preferred solution.
Such a programmable packet processor could be developed using a standard general purpose microprocessor core. Several processor cores are commercially available, including those that are licensed by Advanced RISC Machines, Ltd., ARC International, MIPS Computer Systems, Inc., and Lexra, Inc. However, the above cores are general purpose cores that would need to be optimized for packet processing. Such optimization typically would include: additional instructions; DMA support; task switch with low overhead; specific bit manipulation instructions; etc. The disadvantages of using such general purpose cores in packet processing applications include: costs incurred from license fee and royalties; limited customization—a special license is usually required to modify the core; create dependency on the core provider roadmap and technical support; over featured—FPU (Floating Point Units), MMU (Memory Management Units]; etc.
Therefore, there is a need for a highly robust programmable packet processor that can support a variety of high end applications, that is capable of handling a variety of protocols, and that provides desired performance in terms of speed and power.
What is also needed is a high performance communications processor implementing such a programmable packet processor as its core network processor (s), and implementing other useful modules, such as memories, DMAs, and interfaces to outside PHY platforms, so that the high performance communications processor can be beneficially implemented as a SOC solution for a myriad of high end communication applications.

Communications system using rings architecture


Provided is an ion analyzer characterized by: an ionization chamber (10) to be maintained at atmospheric pressure; an analysis chamber (11) for analyzing an ion generated in the ionization chamber (10); a vacuum pump (15, 16) for evacuating the inside of the analysis chamber (11); a capillary (102) for allowing the ionization chamber (10) and the analysis chamber (11) to communicate with each other; a conductance changer (103, 104) for changing the conductance of the capillary (102); and a controller (20) for operating the conductance changer (103, 104) in such a manner as to decrease the conductance of the capillary (102) when the degree of vacuum in the analysis chamber (11) is lower than a predetermined degree of vacuum.

Ion sources used in mass spectrometers can be divided into two major types: an ion source which ionizes a sample under atmospheric pressure (atmospheric pressure ion source), and an ion source which ionizes a sample under vacuum. Atmospheric pressure ion sources have been popularly used since they do not require the task of evacuating the ionization chamber and is therefore easy to handle.
FIG. 1 shows a schematic configuration of a mass spectrometer having an atmospheric pressure ion source 501. This mass spectrometer includes an ionization chamber 50 which is maintained at atmospheric pressure and an analysis chamber 51 which communicates with the ionization chamber 50 through a capillary 502 and yet should be maintained in a vacuum state. The analysis chamber 51 has the configuration of a multi-stage differential pumping system which includes a first intermediate vacuum chamber 52 maintained in a low-vacuum state by a rotary pump, as well as a second intermediate vacuum chamber 53 and a mass spectrometry chamber 54 maintained in a high-vacuum state by a turbo molecular pump, with the degree of vacuum increased in a stepwise manner toward the rear side (for example, see Patent Literature 1).


DC and AC DCT transform coefficients of an INTRA coded block are differentially encoded by selecting predictor DC and AC coefficients from a left-hand neighboring block and a top neighboring block. Each block is coded according to a frame mode, a reordered field mode, and a non-reordered field mode. The AC predictor block is selected according to the respective coding modes of the blocks, and the block in which a DC predictor resides. The top block is selected as an AC predictor when the top block and current block are both reordered field mode, or both frame mode and/or non-reordered field mode, and the DC predictor resides in the top block. Zeroed AC spatial transform coefficients are used in place of the AC spatial transform coefficients from the selected block when the selected block is not INTRA coded, or does not reside in the same Video Object Plane (VOP) as the current block. DC coefficients may be non-linearly quantized.

The present invention relates to a method and apparatus for coding of DC and AC coefficients for intra-macroblock digital video, in particular, when the current macroblock and/or a neighboring macroblock is interlaced (e.g., field) coded. Predictor coefficients from neighboring macroblocks are selected for use in differentially encoding the coefficients of a current macroblock to optimize coding efficiency. The coefficients are obtained from a spatial transformation such as the Discrete Cosine Transform (DCT), for example.
The invention is particularly suitable for use with various multimedia applications, and is compatible with the MPEG-4 Verification Model (VM) 8.0 standard (MPEG-4 VM 8.0) described in document ISO/IEC/JTC1/SC29/WG11 N1796, entitled "MPEG-4 Video Verification Model Version 8.0", Stockholm, July 1997, incorporated herein by reference. The MPEG-2 standard is a precursor to the MPEG-4 standard, and is described in document ISO/IEC 13818-2, entitled "Information Technology--Generic Coding of Moving Pictures and Associated Audio, Recommendation H.262, " Mar. 25, 1994, incorporated herein by reference.
MPEG-4 is a new coding standard which provides a flexible framework and an open set of coding tools for communication, access, and manipulation of digital audio-visual data. These tools support a wide range of features. The flexible framework of MPEG-4 supports various combinations of coding tools and their corresponding functionalities for applications required by the computer, telecommunication, and entertainment (i.e., TV and film) industries, such as database browsing, information retrieval, and interactive communications.
MPEG-4 provides standardized core technologies allowing efficient storage, transmission and manipulation of video data in multimedia environments. MPEG-4 achieves efficient compression, object scalability, spatial and temporal scalability, and error resilience.
The MPEG-4 video VM coder/decoder (codec) is a block- and object-based hybrid coder with motion compensation. Texture is encoded with an 8.times.8 Discrete Cosine Transformation (DCT) utilizing overlapped block-motion compensation. Object shapes are represented as alpha maps and encoded using a Content-based Arithmetic Encoding (CAE) algorithm or a modified DCT coder, both using temporal prediction. The coder can handle sprites as they are known from computer graphics. Other coding methods, such as wavelet and sprite coding, may also be used for special applications.
Motion compensated texture coding is a well known approach for video coding, and can be modeled as a three-stage process. The first stage is signal processing which includes motion estimation and compensation (ME/MC) and a two-dimensional (2-D) spatial transformation. The objective of ME/MC and the spatial transformation is to take advantage of temporal and spatial correlations in a video sequence to optimize the rate-distortion performance of quantization and entropy coding under a complexity constraint. The most common technique for ME/MC has been block matching, and the most common spatial transformation has been the DCT.
Additionally, in certain situations, coding efficiency may be improved when macroblocks are INTRA coded, e.g., without reference to a temporally subsequent or previous predictor macroblock. INTRA coding may be desirable for an image sequence with rapid motion, a scene change, or rapid changes in lighting conditions, where there may be little frame-to-frame correlation. Coding efficiency may further be improved by differentially encoding the DCT coefficients of a current block using the coefficients of a neighboring block as predictor coefficients.
However, with coding schemes such as MPEG-4, it is possible to have both frame mode and field mode macroblocks next to one another in a video object plane (VOP) or other image area. Additionally, field mode macroblock may be reordered or non-reordered in an adaptive coding scheme. Accordingly, it would be desirable to have a system for selecting predictor coefficients for differentially coding the AC and DC DCT coefficients of a current INTRA coded block, where the current block and/or the neighboring blocks are coded in a frame mode, non-reordered field mode, and/or reordered field mode.
The system should further provide non-linear quantization of DC transform coefficients.
The present invention provides a system having the above and other advantages.

Intra-macroblock DC and AC coefficient prediction for interlaced digital video


A method and apparatus for protecting a die from damage due to material jams in material stamping equipment wherein feed material is stamped in a die and then advanced through the die by action of press feed rolls powered by a press feed roll drive motor. The position error of the press feed rolls or the torque of the press feed roll drive motor is monitored during the advance of the feed material through the die. The monitored position error of the press feed rolls or the monitored torque of the press feed roll drive motor is then compared to the expected position error of the press feed rolls or the expected torque of the press feed roll motor, respectively. The feed material is moved backwards to a previous position from which the feed material advanced, typically the position at which the feed material was last stamped, if the monitored position error of the press feed rolls or the monitored torque of the press feed roll drive motor deviates by more than a tolerance value from the expected position error of the press feed rolls or the expected torque of the press feed roll motor, respectively. Operation of the material stamping equipment may stopped after the feed material is moved back if desired.

The invention relates generally to the field of die stamping and more particularly to a method and apparatus for protecting a die and punch assembly from damage due to material jams.
Material stamping equipment, containing die and punch assemblies, stamps, forms or cuts patterns or holes in material that is fed into the die. As shown in FIG. 1, the stamping, forming or cutting is usually accomplished by a punch assembly 2 being driven into contact with the feed material 3 that is fed into the die 1. The feed material in turn is driven up against the die by the punch assembly. Material 4 that is stamped or cut out of the feed material 3 is ejected through holes 1a in the die if the stamping process does not become jammed. New feed material 3 is then advanced into the die 1 and material that has been stamped is advanced out of the die by the action of the press feed roll drive motor 5 and the press feed rolls 6.
It should be noted that the material stamping equipment, including the punch assembly 2, die 1, and material support 7, the press feed roll drive motor 5 and press feed rolls 6, and the in-position sensor 8 are all known in the art and are described and depicted in FIGS. 1, 2, 3, 4a, and 4b herein only as they relate to the current invention.
Unfortunately, as shown in FIG. 1 and FIG. 3, the material 4 stamped, formed or cut out from the pattern or hole in the feed material 3 does not always detach properly from the feed material and eject out of the die 1. This non-detaching material 4 either prevents the new feed material from fully advancing into the die 1 or remains in an unwanted position in the die causing damage to the die or renders subsequent work pieces improperly stamped.
Traditionally, as depicted in FIG. 2, and disclosed in U.S. Pat. No. 5,091,962, a die protection sensor 8, also known as an "in-position" sensor, is placed close to the feed material after said feed material has advanced through the die 1 to detect incorrectly positioned material. The problem with this traditional method is that, due to the high rate of speed at which material stamping machines operate, if a piece of material 4 is not properly stamped, formed or cut out of the feed material such that the material 4 is lodged in an undesirable position within the die as shown in FIG. 1 or FIG. 3, the punch assembly 2 will have already struck the jammed feed material and the die, potentially causing damage to the die, before the in-position sensor 8 can detect the incorrectly stamped material and stop the stamping machinery.
Buckle detectors have also been utilized to detect buckles 9 or other misfeeds in an effort to protect dies. However, the way such detectors have been traditionally used does not provide a satisfactory solution to the problem of material jamming because it provides only for stopping the press and still does not avoid damage to the material, die and punch assembly.
Accordingly, a method to protect dies from material jams, prior to the die stamping a subsequent work piece and thereby becoming damaged, has been desired.

Method and apparatus for die jam protection/anticipation and correction


A candle extinguisher includes a body of thin-plate, non-combustible material, the body having a ring-shaped part defining an inner space, with an inner diameter at least slightly exceeding the outer diameter of a candle on which the extinguisher is to be positioned. The body has a plurality of flexible finger elements extending upwardly from the ring-shaped part, each of the finger elements having a proximal part and a distal part. The proximal finger parts extend substantially in coplanar relationship with the ring-shaped part and are bendable outwardly relative to the inner space defined by the ring-shaped part. The distal finger parts are bent substantially perpendicularly relative to a respective proximal part and extend inwardly relative to the inner space defined by the ring-shaped part, each of the distal parts having a length exceeding one half of the width of the inner space defined by the ring-shaped part.

The present invention relates to a candle extinguisher comprising a unitary body of a thin plate material and made from a non-combustible or non-inflammable material, i.e. material which is not caused to burn, melt or otherwise be deteriorated when contacted with the burning flame of a candle or when exposed to the heat generated by the burning flame of a candle.
For centuries, a candle extinguisher has been used, which candle extinguisher is made from a conical metal cup having a rod constituting a handle by means of which the cup is positioned in an inverted state on the top of a candle for extinguishing the candle by preventing oxygen from being admitted to the burning candle.
The technique of extinguishing a burning candle has also been refined throughout several decades as candle extinguishers have been developed as described in, among others, DE 177488, DE 162195, U.S. Pat. No. 4,818,214 and WO 02057688. Reference is made to the above publications and the above US patent is hereby incorporated in the present specification by reference.
Common to these prior art candle extinguishers is the technical functionality of the extinguishers as the extinguishers have been developed for providing an automated functionality similar to the above-described candle extinguisher as the candle extinguishers described in the above publications are based on the technique of extinguishing a burning candle by closing off a compartment in which the burning flame is enclosed for causing the flame to be extinguished by the prevention of admission of oxygen to the burning flame.

Candle extinguisher and a method for producing a candle extinguisher