A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.

A common computing architecture for processing relatively large amounts of data in a relatively short period of time includes multiple interconnected processors that share the processing burden. By sharing the processing burden, these multiple processors can often process the data more quickly than a single processor can for a given clock frequency. For example, each of the processors can process a respective portion of the data or execute a respective portion of a processing algorithm.
FIG. 1 is a schematic block diagram of a conventional computing machine 10 having a multi-processor architecture. The machine 10 includes a master processor 12 and coprocessors 141-14n, which communicate with each other and the master processor via a bus 16, an input port 18 for receiving raw data from a remote device (not shown in FIG. 1), and an output port 20 for providing processed data to the remote source. The machine 10 also includes a memory 22 for the master processor 12, respective memories 241-24n for the coprocessors 141-14n, and a memory 26 that the master processor and coprocessors share via the bus 16. The memory 22 serves as both a program and a working memory for the master processor 12, and each memory 241-24n serves as both a program and a working memory for a respective coprocessor 141-14n. The shared memory 26 allows the master processor 12 and the coprocessors 14 to transfer data among themselves, and from/to the remote device via the ports 18 and 20, respectively. The master processor 12 and the coprocessors 14 also receive a common clock signal that controls the speed at which the machine 10 processes the raw data.
In general, the computing machine 10 effectively divides the processing of raw data among the master processor 12 and the coprocessors 14. The remote source (not shown in FIG. 1) such as a sonar array loads the raw data via the port 18 into a section of the shared memory 26, which acts as a first-in-first-out (FIFO) buffer (not shown) for the raw data. The master processor 12 retrieves the raw data from the memory 26 via the bus 16, and then the master processor and the coprocessors 14 process the raw data, transferring data among themselves as necessary via the bus 16. The master processor 12 loads the processed data into another FIFO buffer (not shown) defined in the shared memory 26, and the remote source retrieves the processed data from this FIFO via the port 20.
In an example of operation, the computing machine 10 processes the raw data by sequentially performing n+1 respective operations on the raw data, where these operations together compose a processing algorithm such as a Fast Fourier Transform (FFT). More specifically, the machine 10 forms a data-processing pipeline from the master processor 12 and the coprocessors 14. For a given frequency of the clock signal, such a pipeline often allows the machine 10 to process the raw data faster than a machine having only a single processor.
After retrieving the raw data from the raw-data FIFO (not shown) in the memory 26, the master processor 12 performs a first operation, such as a trigonometric function, on the raw data. This operation yields a first result, which the processor 12 stores in a first-result FIFO (not shown) defined within the memory 26. Typically, the processor 12 executes a program stored in the memory 22, and performs the above-described actions under the control of the program. The processor 12 may also use the memory 22 as working memory to temporarily store data that the processor generates at intermediate intervals of the first operation.
Next, after retrieving the first result from the first-result FIFO (not shown) in the memory 26, the coprocessor 141 performs a second operation, such as a logarithmic function, on the first result. This second operation yields a second result, which the coprocessor 141 stores in a second-result FIFO (not shown) defined within the memory 26. Typically, the coprocessor 141 executes a program stored in the memory 241, and performs the above-described actions under the control of the program. The coprocessor 141 may also use the memory 241 as working memory to temporarily store data that the coprocessor generates at intermediate intervals of the second operation.
Then, the coprocessors 142-14n sequentially perform third—nth operations on the second—(n−1)th results in a manner similar to that discussed above for the coprocessor 141.
The nth operation, which is performed by the coprocessor 14n, yields the final result, i.e., the processed data. The coprocessor 14n loads the processed data into a processed-data FIFO (not shown) defined within the memory 26, and the remote device (not shown in FIG. 1) retrieves the processed data from this FIFO.
Because the master processor 12 and coprocessors 14 are simultaneously performing different operations of the processing algorithm, the computing machine 10 is often able to process the raw data faster than a computing machine having a single processor that sequentially performs the different operations. Specifically, the single processor cannot retrieve a new set of the raw data until it performs all n+1 operations on the previous set of raw data. But using the pipeline technique discussed above, the master processor 12 can retrieve a new set of raw data after performing only the first operation. Consequently, for a given clock frequency, this pipeline technique can increase the speed at which the machine 10 processes the raw data by a factor of approximately n+1 as compared to a single-processor machine (not shown in FIG. 1).
Alternatively, the computing machine 10 may process the raw data in parallel by simultaneously performing n+1 instances of a processing algorithm, such as an FFT, on the raw data. That is, if the algorithm includes n+1 sequential operations as described above in the previous example, then each of the master processor 12 and the coprocessors 14 sequentially perform all n+1 operations on respective sets of the raw data. Consequently, for a given clock frequency, this parallel-processing technique, like the above-described pipeline technique, can increase the speed at which the machine 10 processes the raw data by a factor of approximately n+1 as compared to a single-processor machine (not shown in FIG. 1).
Unfortunately, although the computing machine 10 can process data more quickly than a single-processor computing machine (not shown in FIG. 1), the data-processing speed of the machine 10 is often significantly less than the frequency of the processor clock. Specifically, the data-processing speed of the computing machine 10 is limited by the time that the master processor 12 and coprocessors 14 require to process data. For brevity, an example of this speed limitation is discussed in conjunction with the master processor 12, although it is understood that this discussion also applies to the coprocessors 14. As discussed above, the master processor 12 executes a program that controls the processor to manipulate data in a desired manner. This program includes a sequence of instructions that the processor 12 executes. Unfortunately, the processor 12 typically requires multiple clock cycles to execute a single instruction, and often must execute multiple instructions to process a single value of data. For example, suppose that the processor 12 is to multiply a first data value A (not shown) by a second data value B (not shown). During a first clock cycle, the processor 12 retrieves a multiply instruction from the memory 22. During second and third clock cycles, the processor 12 respectively retrieves A and B from the memory 26. During a fourth clock cycle, the processor 12 multiplies A and B, and, during a fifth clock cycle, stores the resulting product in the memory 22 or 26 or provides the resulting product to the remote device (not shown). This is a best-case scenario, because in many cases the processor 12 requires additional clock cycles for overhead tasks such as initializing and closing counters. Therefore, at best the processor 12 requires five clock cycles, or an average of 2.5 clock cycles per data value, to process A and B.
Consequently, the speed at which the computing machine 10 processes data is often significantly lower than the frequency of the clock that drives the master processor 12 and the coprocessors 14. For example, if the processor 12 is clocked at 1.0 Gigahertz (GHz) but requires an average of 2.5 clock cycles per data value, then the effective data-processing speed equals (1.0 GHz)/2.5=0.4 GHz. This effective data-processing speed is often characterized in units of operations per second. Therefore, in this example, for a clock speed of 1.0 GHz, the processor 12 would be rated with a data-processing speed of 0.4 Gigaoperations/second (Gops).
FIG. 2 is a block diagram of a hardwired data pipeline 30 that can typically process data faster than a processor can for a given clock frequency, and often at substantially the same rate at which the pipeline is clocked. The pipeline 30 includes operator circuits 321-32n, which each perform a respective operation on respective data without executing program instructions. That is, the desired operation is "burned in" to a circuit 32 such that it implements the operation automatically, without the need of program instructions. By eliminating the overhead associated with executing program instructions, the pipeline 30 can typically perform more operations per second than a processor can for a given clock frequency.
For example, the pipeline 30 can often solve the following equation faster than a processor can for a given clock frequency:Y(xk)=(5xk+3)2xk where xk represents a sequence of raw data values. In this example, the operator circuit 321 is a multiplier that calculates 5xk, the circuit 322 is an adder that calculates 5xk+3, and the circuit 32n (n=3) is a multiplier that calculates (5xk+3)2xk.
During a first clock cycle k=1, the circuit 321 receives data value x1 and multiplies it by 5 to generate 5x1.
During a second clock cycle k=2, the circuit 322 receives 5x1 from the circuit 321 and adds 3 to generate 5x1+3. Also, during the second clock cycle, the circuit 321 generates 5x2.
During a third clock cycle k=3, the circuit 323 receives 5x1+3 from the circuit 322 and multiplies by 2x1 (effectively left shifts 5x1+3 by x1) to generate the first result (5x1+3)2x1. Also during the third clock cycle, the circuit 321 generates 5x3 and the circuit 322 generates 5x2+3.
The pipeline 30 continues processing subsequent raw data values xk in this manner until all the raw data values are processed.
Consequently, a delay of two clock cycles after receiving a raw data value x1—this delay is often called the latency of the pipeline 30—the pipeline generates the result (5x1+3)2x1, and thereafter generates one result—e.g., (5x2+3)2x2, (5x3+3)2x3, . . . , 5xn+3)2xn—each clock cycle.
Disregarding the latency, the pipeline 30 thus has a data-processing speed equal to the clock speed. In comparison, assuming that the master processor 12 and coprocessors 14 (FIG. 1) have data-processing speeds that are 0.4 times the clock speed as in the above example, the pipeline 30 can process data 2.5 times faster than the computing machine 10 (FIG. 1) for a given clock speed.
Still referring to FIG. 2, a designer may choose to implement the pipeline 30 in a programmable logic IC (PLIC), such as a field-programmable gate array (FPGA), because a PLIC allows more design and modification flexibility than does an application specific IC (ASIC). To configure the hardwired connections within a PLIC, the designer merely sets interconnection-configuration registers disposed within the PLIC to predetermined binary states. The combination of all these binary states is often called "firmware." Typically, the designer loads this firmware into a nonvolatile memory (not shown in FIG. 2) that is coupled to the PLIC. When one "turns on" the PLIC, it downloads the firmware from the memory into the interconnection-configuration registers. Therefore, to modify the functioning of the PLIC, the designer merely modifies the firmware and allows the PLIC to download the modified firmware into the interconnection-configuration registers. This ability to modify the PLIC by merely modifying the firmware is particularly useful during the prototyping stage and for upgrading the pipeline 30 "in the field".
Unfortunately, the hardwired pipeline 30 may not be the best choice to execute algorithms that entail significant decision making, particularly nested decision making. A processor can typically execute a nested-decision-making instruction (e.g., a nested conditional instruction such as "if A, then do B, else if C, do D, . . . , else do n") approximately as fast as it can execute an operational instruction (e.g., "A+B") of comparable length. But although the pipeline 30 may be able to make a relatively simple decision (e.g., "A>B?") efficiently, it typically cannot execute a nested decision (e.g., "if A, then do B, else if C, do D, . . . , else do n") as efficiently as a processor can. One reason for this inefficiency is that the pipeline 30 may have-little on-board memory, and thus may need to access external working/program memory (not shown). And although one may be able to design the pipeline 30 to execute such a nested decision, the size and complexity of the required circuitry often makes such a design impractical, particularly where an algorithm includes multiple different nested decisions.
Consequently, processors are typically used in applications that require significant decision making, and hardwired pipelines are typically limited to "number crunching" applications that entail little or no decision making.
Furthermore, as discussed below, it is typically much easier for one to design/modify a processor-based computing machine, such as the computing machine 10 of FIG. 1, than it is to design/modify a hardwired pipeline such as the pipeline 30 of FIG. 2, particularly where the pipeline 30 includes multiple PLICs.
Computing components, such as processors and their peripherals (e.g., memory), typically include industry-standard communication interfaces that facilitate the interconnection of the components to form a processor-based computing machine.
Typically, a standard communication interface includes two layers: a physical layer and a services layer.
The physical layer includes the circuitry and the corresponding circuit interconnections that form the interface and the operating parameters of this circuitry. For example, the physical layer includes the pins that connect the component to a bus, the buffers that latch data received from the pins, and the drivers that drive signals onto the pins. The operating parameters include the acceptable voltage range of the data signals that the pins receive, the signal timing for writing and reading data, and the supported modes of operation (e.g., burst mode, page mode). Conventional physical layers include transistor-transistor logic (TTL) and RAMBUS.
The services layer includes the protocol by which a computing component transfers data. The protocol defines the format of the data and the manner in which the component sends and receives the formatted data. Conventional communication protocols include file-transfer protocol (FTP) and transmission control protocol/internet protocol (TCP/IP).
Consequently, because manufacturers and others typically design computing components having industry-standard communication interfaces, one can typically design the interface of such a component and interconnect it to other computing components with relatively little effort. This allows one to devote most of his time to designing the other portions of the computing machine, and to easily modify the machine by adding or removing components.
Designing a computing component that supports an industry-standard communication interface allows one to save design time by using an existing physical-layer design from a design library. This also insures that he/she can easily interface the component to off-the-shelf computing components.
And designing a computing machine using computing components that support a common industry-standard communication interface allows the designer to interconnect the components with little time and effort. Because the components support a common interface, the designer can interconnect them via a system bus with little design effort. And because the supported interface is an industry standard, one can easily modify the machine. For example, one can add different components and peripherals to the machine as the system design evolves, or can easily add/design next-generation components as the technology evolves. Furthermore, because the components support a common industry-standard services layer, one can incorporate into the computing machine's software an existing software module that implements the corresponding protocol. Therefore, one can interface the components with little effort because the interface design is essentially already in place, and thus can focus on designing the portions (e.g., software) of the machine that cause the machine to perform the desired function(s).
But unfortunately, there are no known industry-standard services layers for components, such as PLICs, used to form hardwired pipelines such as the pipeline 30 of FIG. 2.
Consequently, to design a pipeline having multiple PLICs, one typically spends a significant amount of time and exerts a significant effort designing "from scratch" and debugging the services layer of the communication interface between the PLICs. Typically, such an ad hoc services layer depends on the parameters of the data being transferred between the PLICs. Likewise, to design a pipeline that interfaces to a processor, one would have to spend a significant amount of time and exert a significant effort in designing and debugging the services layer of the communication interface between the pipeline and the processor.
Similarly, to modify such a pipeline by adding a PLIC to it, one typically spends a significant amount of time and exerts a significant effort designing and debugging the services layer of the communication interface between the added PLIC and the existing PLICs. Likewise, to modify a pipeline by adding a processor, or to modify a computing machine by adding a pipeline, one would have to spend a significant amount of time and exert a significant effort in designing and debugging the services layer of the communication interface between the pipeline and processor.
Consequently, referring to FIGS. 1 and 2, because of the difficulties in interfacing multiple PLICs and in interfacing a processor to a pipeline, one is often forced to make significant tradeoffs when designing a computing machine. For example, with a processor-based computing machine, one is forced to trade number-crunching speed and design/modification flexibility for complex decision-making ability. Conversely, with a hardwired pipeline-based computing machine, one is forced to trade complex-decision-making ability and design/modification flexibility for number-crunching speed. Furthermore, because of the difficulties in interfacing multiple PLICs, it is often impractical for one to design a pipeline-based machine having more than a few PLICs. As a result, a practical pipeline-based machine often has limited functionality. And because of the difficulties in interfacing a processor to a PLIC, it would be impractical to interface a processor to more than one PLIC. As a result, the benefits obtained by combining a processor and a pipeline would be minimal.
Therefore, a need has arisen for a new computing architecture that allows one to combine the decision-making ability of a processor-based machine with the number-crunching speed of a hardwired-pipeline-based machine.

Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method


Output voltage of a charge-to-voltage converter used in an image sensing system is compared with one or more thresholds to determine if the output voltage exceeds predetermined threshold levels. If the output voltage exceeds one or more of the threshold levels, the input terminal of the charge-to-voltage converter is connected to a reference voltage to prevent the charge-to-voltage converter from saturating. Problems that could be caused due to overload of the voltage-to-charge converter are obviated. In an embodiment, the charge-to-voltage converter is implemented by an operational amplifier (OPAMP). A pair of comparators compares the output of the OPAMP with corresponding threshold voltages. The result of the comparison is used to generate a signal for connecting the input of the OPAMP to the reference voltage, thereby preventing saturation of the OPAMP.

1. Technical Field
Embodiments of the present disclosure relate generally to image sensing systems, and more specifically to techniques for mitigating the effects of signal overload in analog front-end circuits used in image sensing systems.
2. Related Art
Image sensing systems generally refer to systems used for capturing images of objects. The captured images may be suitably processed for desired applications and/or displayed. An example of an image sensing system is a digital X-ray machine. Image sensing systems typically use image sensor arrays. Sensors in the image sensor arrays generate a charge proportional to the intensity of energy or rays (such as visible light, X-rays, infra red light, etc.) incident on the sensors (and thus representative of the image to be captured). The term 'energy' is used generically herein to include rays such as those noted above. Each sensor typically corresponds to one "pixel" of the image to be captured.
Sensor arrays of an image sensing system may be connected to analog front-end (AFE) circuits. AFE circuits are typically used for amplification of the signals generated by the sensors, conversion of the signals from charge to voltage and digital representation of the voltage, etc. For example, in a digital X-ray machine, the AFE may include charge-to-voltage converters, a multiplexer and one or more analog to digital converters (ADC). The charge-to-voltage converter is typically implemented by an amplifier configured as a signal integrator. One problem that may occur in an AFE (and more specifically in the charge-to-voltage converter in the AFE) of an image sensing system is signal overload. Signal overload of a charge-to-voltage amplifier occurs when the magnitude of charge received as input is such as to cause the output voltage of the charge-to-voltage amplifier to exceed desired operating thresholds. Such signal overload may be caused by a large amount of energy being incident on a pixel, resulting in an excessively 'bright' pixel. Other causes of signal overload may include readout of a defective pixel/sensor in the image sensor array. Signal overload may result in images generated by the image sensing system to be blurred or otherwise not faithfully representative of the imaged object.
One prior technique to address the problem noted above employs an additional transistor in each pixel (sensor) in the image sensor array, the transistor operating as a clamp to prevent signal overload of the charge-to-voltage amplifier. Another prior technique reduces the possibility of such signal overload by laser-cutting defective sensors in the sensor array. A yet another prior technique employs special materials with smaller dielectric constant and adsorption for implementing the signal lines (interconnect) from each sensor.
The prior techniques noted above are implemented in the image sensor arrays (and not in the AFE), and may be associated with increased cost. Further, having to rely on such implementation in the image sensor array provides lesser flexibility for a system integrator in integrating sub-systems, components and modules that make up an image sensing system.

Mitigating the effects of signal overload in analog front-end circuits used in image sensing systems


An immersion cleaning device is provided with concave portions housing respective chemical baths into which a workpiece is selectively immersed. Any gas and mist generated from the chemical baths is exhausted from the concave portions. A transportation element has a portion to hold a workpiece with takes the workpiece into or out from the chemical bath. A controller is included to control operation of transportation means. An enclosure body moves with the holding portion and is moved with the workpiece to substantially enclose any gases and chemical mist generated during the transportation. Corrosion of the device and pollution which might be caused by leaks of gases and mist to the outside are thus prevented.

1. Field of the Invention
The present invention relates to improvements to an immersion device, in which a workpiece such as a semiconductor wafer is immersed into a chemical and cleaned.
2. Description of the Prior Art
In production of semiconductor devices such as LSI, various kinds of fine particle dust is generated due to various reasons. For example, there are process dust caused in the process of diffusion, CVD or ion injection, and mechanical dust caused in the process of handling, storage or transportation. When such fine particle adheres to semiconductor wafer, that greatly affects production yield of semiconductor device. Accordingly, the semiconductor wafer must be cleaned in production of the semiconductor device. Generally 5-10 processes are repeated for the cleaning process of the semiconductor wafer. In the cleaning method, there are wet-type cleaning device which removes dirt using liquid such as chemical or pure wafer, and dry-type cleaning device which uses no liquid. An immersion cleaning device can clean all of various particles with low cost, and effectively. FIG. 1 shows the immersion cleaning device as an example of former wet-type cleaning device. In the figure, an immersion cleaning device 1 is composed of ceiling portion 1a, cleaning bath portion with a plurality of cleaning bath (chemical bath or pure water bath) 10b, loader portion 1c, unloader portion 1d and work transportation portion 1e. Specified number of magazine If mounted with semiconductor wafer is put on loader portion. Upon this, when cleaning conditions is inputted into controller 1g, work transportation portion 1e chucks magazine 1f with clicks 1i, puts it into cleaning bath 10b and cleans semiconductor wafer, and semiconductor wafer is dried at IPA (isopropyl alcohol) vapor drier 1h situated at unloader portion 1d. When cleaning treatment is completed, controller 1g inform operator of the completion. As sequence of cleaning treatment for semiconductor wafer, there are, for example, the following: heated concentrated nitric acid--pure water--heated cencetrated sulfuric acid --pure water--dilute hydrofuluoric acid--pure water--IPA drier; (ammonia water+hydrochloric acid)--pure water dilute hydrofluoric acid pure water IPA vapor drier. When the device, as shown in FIG. 1, has a plurality of work transportation portion 1e, range of cleaning bath 1b, which each work transportation portion 1e takes charge of, is specified, and each transportation portion 1e takes the magazine 1f into and from the cleaning bath. (Upon this, cleaning bath ranges, which neighboring work transportation portion 1e takes charge of, partially lap.)
There is sometimes an immersion cleaning device, in which, to prevent contamination due to fine particle on semiconductor wafer and mist, clean air having passed through high performance filter is flowed downward from ceiling portion 1a to be exhausted through exhaust hole (exhaust means) 1j, and by this, inside of the immersion cleaning device 1 is kept clean and gas generating from cleaning bath 10b is suppressed. In reference to FIG. 2, an example of a cleaning process in such device for semiconductor wafer is still explained in detail. Each cleaning bath 10b-10b-3 is housed in concave portions formed on upper surface of the cleaning portion 1b. To begin with, magazine 1f is immersed for 10 min. in heated concentrated nitric acid bath 10b-1. Then, work transportation portion 1e holds the magazine 1f and transports it to pure water bath 10b-2. After cleaning semiconductor wafer for 110 min. in the pure water bath 1b2, the work transportation portion 1e again holds the magazine 1f and transport it to dilute fluoric acid bath 10b-3 3 to immerse it for 5 min.. Then, the work transportation portion 1e again transport the magazine 1f to the following bath. In this way, the magazine is put in or taken out from chemical bath to clean semiconductor wafer in the magazine. Upon this, clean air 1k blown out from ceiling portion 1a is exhausted by exhaust means 1m through exhaust hole 1j together with gas generating from each cleaning bath 10b. In the figure, clean air 1k is shown only above the cleaning bath 10b-2, but the cleaning air is generally blown out over the entire cleaning bath portion 1b from ceiling portion 1a. In the case of the above device, almost all gases generating from cleaning bath (for example, cleaning bath 10b-3 in FIG. 8), in which magazine 1f mounted with semiconductor wafer as work is completely immersed, and generating from cleaning bath (for example, cleaning bath 10b-1), in which magazine 1f is not immersed, are exhausted through each hole 1j. However, gas generating from chemical adhering to magazine 1f or to semiconductor wafer (work), during transportation (for example, as shown in the above of clearing bath 10b-2 in FIG. 2), is not completely absorbed through exhausted hole 1j and stirred by clean air 1k blown out from ceiling portion 1a. In addition, when chemical is heated, the specific gravity becomes less than air, so that the gas is scattered in upper or side direction going counter flowing direction of the clean air 11k. In this case, part of chemical combines with moisture in the air to become mist, and is scattered to outside of the immersion cleaning device 1 together with gas. Gas or mist generating from chemical is often acid or alkaline. Accordingly, if such gas or mist is scattered to outside of the immersion cleaning device is not only corrodes or deteriorates surrounding parts, but also gives unfavorable effects to human bodies.
In addition, in the case of above device in which clean air is blown out, part of scattered gas or mist is again taken into the high performance filter at the ceiling portion 1a together with room air and circulates through the device and concentrates in proportion to operation time. As result, the high performance filter and motor fan are corroded. Beside, if the work transportation portion 1e and senser system of the device are corroded, operation error of the device is sometimes caused. This not only leads to poor cleaning and damage of the semiconductor wafer, but also dangerous to an operator. Conventional device has the above problems.


A positive-working radiation-sensitive mixture and recording material are disclosed. The mixture contains, as essential constituents, a 1,2-quinone diazide and/or a combination of a compound which forms strong acid on exposure to actinic radiation and a compound containing at least one cleavable C--O--C bond and a polymeric binder containing repeating units of formula I ##STR1## in which R.sub.1 is a hydrogen or halogen atom, or a cyanide or an alkyl group, R.sub.2, R.sub.3 are identical or different and are hydrogen, or alkyl or aryl groups, R.sub.4, R.sub.5 are identical or different and are and R.sub.6 hydrogen or halogen atoms, or alkyl, alkoxy or aryl groups, X represents the atoms necessary to complete a monocyclic or polycyclic carbocyclic aromatic ring system, and is 1, 2 or 3. The mixture yields lithographic plates having high print runs which can be thermally post-cured and which have good resistance to chemicals. The mixture also produces photoresists having good heat resistance.

The present invention relates to a positive-working radiation-sensitive or photosensitive mixture that contains, as essential constituents, a water-insoluble polymeric binder which is soluble in aqueous-alkaline solutions and a 1,2-quinone diazide and/or a combination of a compound which forms strong acid on exposure to actinic radiation and a compound containing at least one cleavable C--O--C bond. The invention also relates to a radiation-sensitive recording material composed of a layer base on which the radiation-sensitive mixture is deposited.
Positive-working photosensitive mixtures, i.e., mixtures used to produce a copying layer which becomes soluble where exposed, are known and have been described for a wide variety of possible applications, including lithographic plates and photoresists. A substantial number of the properties of these copying layers is determined by the polymeric binder. The binders used for positive copying layers are virtually exclusively phenol formaldehyde or cresol formaldehyde condensation products of the novolak type. For some applications of positive copying layers, however, the properties resulting therefrom are still not ideal. This is true, in particular, of the heat resistance when the mixture is used as a photoresist, and of the number of print runs when the mixture is used as a lithographic plate.
It has been found that substitution of novolaks by binders having higher glass transition temperatures results in a generally better property profile. Thus, a whole series of alkali-soluble binders for positive copying layers have been described, such as, for example, naphthol-based phenolic resins (U.S. Pat. No. 4,551,409), homopolymers and copolymers of vinylphenols (DE 2,322,230, corresponding to U.S. Pat. No. 3,869,292 and DE 3,406,927, corresponding to U.S. Pat. No. 4,678,737), polymers of the esters of acrylic acids with phenols (Japanese Published Specification 76/36,129, Ep 212,440 and EP 212,439) or copolymers of hydroxyphenylmaleimides (Ep 187,517).
Binders of the type mentioned have, however, hitherto not found any practical application. One reason for this is that these polymers do not satisfactorily fulfill an essential requirement imposed on binders of positive copying layers, i.e., the facility for thermal self-crosslinking. This property, which exists in the case of novolaks, is of significance in cases where the copying layer is intended to resist aggressive chemicals. In this respect it is also known to incorporate in the polymers units which, although they are not alkali-soluble, make thermal crosslinking possible (EP 184,044). As a result of this, however, other properties, such as development behavior and storage stability of the mixture, are impaired.
DE 3,820,699 describes polymers based on hydroxybenzylacrylamides which meet the requirement for crosslinkable alkali-soluble monomer units. It is disadvantageous, however, that the polymers can only contain these monomers in a limited amount, since otherwise photosensitivity and development behavior are affected unfavorably.

Radiation-sensitive mixture and recording material comprising as a binder a copolymer having hydroxybenzyl(meth)acrylate groups or derivatives thereof


The shoe shall include at least one spring (R), notably a metal spring, set into the sole between an upper plate (2) extending as far as the back of the shoe and a lower plate (3) to cushion the shoe from shocks from the ground. The upper plate (2) shall be rigid and shall be wholly located behind a line (L) underneath the metatarsus (4) of the foot; the sole shall present an area to allow for transversal articulation (5) in the area of this line (L) in such a way that the angle formed between the upper rigid plate (2) and the section of the sole (6) located in front of the area of articulation may vary; the lower edges of the sides of the uppers (9) of the shoe which cover the foot shall be joined to the upper rigid plate (2); the spring(s) (R, 11) shall be situated in the only part of the rigid plate which will be under the heel of the foot, the whole being such that variations in the load applied to the spring (R, 11) shall provoke an oscillating movement of the upper rigid plate (2) around a transversal line of articulation (L), in relation to the lower plate (3).

1. Field of the Invention
The invention relates to a shoe of the type which includes at least one spring, notably a metal spring, set into the sole between an upper plate extending as far as the back of the shoe and a lower plate, to cushion the shoe against shocks from the ground.
2. Description of the Prior Art
The invention relates particularly to such a shoe, destined to be used for sport but which may also be used for everyday wear.
FR-A-958 766 shows a shoe of this type. In accordance with the illustrations in FIGS. 6 to 8, elasticity is provided by helical springs set in diverse places between the upper and lower plates. This arrangement of springs does not give good stability to the wearer of the shoe because it produces at element of `floating` of the upper plate which would jeopardise the maintaining of stability. Furthermore, the natural movement of the foot upon the ground would not occur under favourable conditions. Finally, the production of such a shoe is relatively complex.

Shoe, notably a sports shoe, which includes at least one spring set into the sole, cassette and spring for such a shoe


A wiper device includes a trimmer to trim an needle thread, a needle bar mounted so as to be vertically moveable and having a sewing needle attached in the lower end, a wiper member to wipe the needle thread extending from an eye of the sewing needle as to pull the needle thread above the upper surface of work cloth after trimming the needle thread, a wiper driving unit to actuate the thread wiping movement of the wiper member and a switch unit to switch the wiper member between an operable state and an inoperable state in conjunction with the position of the needle bar.

1. Field of the Invention
The present invention relates to a wiper device for wiping a trimmed needle thread.
2. Description of the Related Art
Conventionally, sewing machines capable of sewing embroidery are provided with a cloth presser mechanism to drive the cloth presser to press work cloth on performing embroidery sewing, a thread trimmer device to trim a sewing thread on completing the sewing procedure and a thread wiping mechanism to wipe up the trimmed sewing thread with a wiper member have been reduced to practice.
JP-A-2003-103080 discloses a sewing machine of the above-described type, for example. In the vicinity of a bottom surface of a needle plate of a sewing machine bed, a thread trimming device is provided for automatically trimming a needle thread and a bobbin thread. On a head of the sewing machine above the sewing machine bed, a thread wiping device is provided which pulls out the needle thread connected to the sewing needle by lifting the needle thread onto the needle plate.
To describe the operation of the thread wiping device, when the wiper is driven by a wiper drive mechanism with a needle bar and the cloth presser in lifted position, the needle thread trimmed by the thread trimming device is hooked on a wiper hook to be pulled out of the work cloth and above the needle plate. Then the needle thread is further held by a needle thread retainer.
Also a wiper device of a sewing machine disclosed in JP-U-6-52782 includes a wiper body rotatably supported by a sewing machine frame, a presser to press the work piece to be sewn, a vertically moving unit to be vertically moved with the presser, and a connecting link having one end contacting an upper end of the vertically moving unit, and the other end connected to the wiper body. In this wiper device, the wiping of the sewing thread is actuated by lifting the presser of the sewing machine, which in turn lifts the vertically moving unit contacting the presser. Then, the lifting of the vertically moving unit moves a lower end of the wiper body towards the sewing needle via the connection link to wipe up the sewing thread.
A thread wiping device disclosed in JP-A-2003-103080 is provided in a main body of the sewing machine, and the drive of a wiper is controlled by a wiper drive mechanism in synchronization with the thread trimming movement, thereby leading to increased complexity, size and cost.
In the wiper device in the sewing machine disclosed in JP-U-6-52782, the wiper body moves in conjunction with the vertical movement of the presser and the wiper body is lifted by the lifting of the presser. Therefore, for example, in case the presser is lifted without trimming the needle thread, the needle thread is forcibly pulled by the wiper body, which leads to a problem of deformation of the wiper body and sewing needle.


Under the present invention, a system, method, and program product are provided for reducing the overhead of cache invalidations in a shared cache by transmitting a hashed code of a key to be invalidated. The method for shared cache invalidation comprises: hashing a key corresponding to an object in a first cache that has been modified or deleted to provide a hashed code of the key, wherein the first cache forms part of a shared cache; transmitting the hashed code of the key to other caches in the shared cache; comparing the hashed code of the key with entries in the other caches; and dropping any keys in the other caches having a hash code the same as the hashed code of the key.

1. Field of the Invention
The present invention generally relates to caching. More particularly, the present invention provides a method, system and program product for reducing the overhead of cache invalidations in a shared cache (e.g., a cache cluster) by transmitting a hashed code of a key to be invalidated rather than the entire key.
2. Related Art
Caching is used in many systems to reduce access time to data. In a clustered environment, caches are often distributed among multiple systems in a cluster. A group of caches in a cluster that all cache the same data are called "peers." To provide cache consistency among peers, caches may send invalidation messages to their peers when an object associated with a key is modified or deleted from the cache.
Sending an invalidation to peers in current shared cache systems involves sending the entire key of the object to be invalidated. In Java, as shown in the flow diagram of FIG. 1, this is typically done by serializing the key (step S1), transmitting the serialized version of the key to each peer (step S2), and deserializing the received serialized version of the key at each peer (step S3). The key received by each peer is subsequently discarded from the cache (step S4). Unfortunately, there is a processing overhead in the serialization/deserialization of the key. Further, the entire key must be transmitted, which consumes extra network bandwidth. As such, there is a need to reduce the processing and bandwidth overhead of cache invalidations in a shared cache.

Lower overhead shared cache invalidations

International Business Machines Corporation


Transparent receptor substrates, well suited for electrostatic reprography, e.g., for the production of overhead transparencies, exhibit excellent transparency, good slip, good adhesion of toner thereto and good electrical conductivity, comprise (i) a transparent composite polyester base(s) having (ii) a toner-receptive primer coating (P) on at least one of the face surfaces thereof, such composite polyester base comprising (a) a thick layer (A) of semicrystalline polyester and (b) a thin layer (B) of an identical or different polyester adhered to at least one of the face surfaces of said thick layer (A), and the at least one primer coating (P) comprising an acrylic polymer having a glass transition temperature ranging from 10.degree. C. to 50.degree. C., a free --COOH carboxylic functional group content less than 50 millimoles per 100 grams of said acrylic polymer and a thickness no greater than 0.3 .mu.m.

1. Technical Field of the Invention
The present invention relates to transparent receptor components or substrates comprising a polyester base for electrostatic photocopying, notably for the production of overhead transparencies.
2. Description of the Prior Art
It is known to this art that photocopies that can be projected onto a screen by means of an overhead projector are easily obtained from a source document by electrostatic photocopying same onto a transparent base. According to this process a uniform, positive or negative electrostatic charge is applied to a photoconductive surface preserving this charge when it is maintained sheltered from light, and the image of a subject to be copied (text, drawing and the like) is formed on said surface by means of an optical system and of a source of light. In the regions where light impinges on the charged surface, the electrical charge is dissipated by grounding, the other regions then forming or defining the electrostatic image of the source document; particles of an electrostatic ink in powder form (hereinafter simply "toner") of opposite charge to that of the electrostatic surface are then deposited onto the latter via electrostatic attraction. The image thus obtained is then intimately contacted with a base, for example a transparent base substrate, to which an opposite electrostatic charge is applied, in order to transfer the toner from the electrostatic surface onto the base. The image thus obtained is fixed onto the base by heat treatment and/or by pressure.
The transparent bases employed for producing projectable electrostatic photocopies must satisfy various requirements to obtain projected images of excellent quality, in particular, sharp images. They must exhibit, particularly, a transparency, a dimensional stability and a high slip, a low capacity for accumulating static electricity charges and good adhesion to the image printing material. It too is known that these bases must exhibit, more particularly, a transparency such that the percentage of light scattered by the passage of the light rays through the thickness thereof, or haze, is less than or equal to 7%. It is also known that when these bases are prepared from a biaxially oriented film, especially a polyester, they must exhibit a dimensional stability such that their shrinkage at 150.degree.-170.degree. C., namely, under the temperature conditions required for fixing the toner, is less than 1% in the directions of drawing.
By reason of their excellent mechanical, physical and chemical properties, polyester films constitute a material of choice for producing transparent bases for projectable electrostatic photocopies. However, their low slip, their great tendency to accumulate static electricity by rubbing or induction and their relative chemical inertness, which is reflected in a low adhesiveness of the toner to the base, present problems which have required solutions complicating the manufacture of transparent bases and making it more costly.
Thus, the drawback of the slip of polyester films cannot be resolved by creating a surface roughness using particles of a filler dispersed within the polyester. Indeed, because of the thickness of the films destined for use as a base far electrostatic photocopying, which ranges from 50 to 200 .mu.m, the presence of filler throughout their thickness imparts a substantial haze which is incompatible with such intended use. The transparency can be obtained only at the expense of a decrease in the filler content, which compromises the slip of the bases and consequently the ability of the bases to slide over one another in the reams employed in photocopying machines, or to slide over the metal surfaces of said machines.
The low affinity of the polyester films for the toner is reflected in easy removal of the toner when the photocopies are being handled and by a gradual deterioration of the image. In its turn, the ability of the polyester base to accumulate static electricity interferes both with the uniform deposition of the toner onto the base during photocopying, which is detrimental to image quality, and with the sheet-by-sheet feed of the bases from a ream source.
To avoid the problems presented by the adhesion of the toner to the base, the transparency, the slip and the tendency to accumulate electrical charges, it has been proposed to deposit, by spreading onto at least one face surface of a filler-free transparent polyester film, a coating comprising a polymeric binder which has at least a good adhesion to the toner and which contains fillers creating a sufficient roughness on the base to impart the necessary slip thereto, and, if appropriate, an antistatic agent. In an alternative embodiment of this solution, a filled adhesive or primer coating is deposited onto one face surface of the polyester film and an antistatic coating on the other face surface.
Thus, U.S. Pat. No. 4,526,847 describes depositing onto a filler-free polyester film a coating of a composition comprising a solution or nitrocellulose in an organic solvent (esters, ketone) containing a plasticizer, a filler which has a particle size of 0.3 to 10 .mu.m (for example colloidal silica) and an antistatic agent.
European Patent Application EP-A-332,183 describes transparent components for electrostatic photocopying, namely, a filler-free polyester base coated with a layer of an acrylic binder containing a filler and an antistatic agent. However, it remains necessary to interpose between the acrylic coating and the polyester a primer facilitating adhesion of the is layer destined to receive the toner to the polyester.
And European Patent Application EP-A-104,074 describes depositing onto one face surface of a polyester base film an acrylic coating containing a filler and providing the adhesion to the toner and, on the other face surface of the polyester base, a coating containing an electrically conductive polymer; placing of a primer coating between the polyester base and the layer receiving the toner is also recommended.
The solutions proposed by the aforesaid prior art are only partially satisfactory. Indeed, the use of compositions based on organic solvents presents health and safety concerns. Certain of the solutions adopted entail increasing the number or layers of coatings: (a) application of a primer which exhibits good adhesiveness of the polyester base to the latter receiving the toner; (b) deposition of a receiving layer providing the adhesiveness of the toner, good slip and, where appropriate, good electrical conductivity; and (c) optionally deposition or an antistatic coating onto the face surface of the base film which is opposite to that receiving the toner. It has also been found that the introduction or an antistatic agent into the adhesiveness layer destined to receive the toner may, depending on the nature of said agent, decrease the effectiveness of the adhesion of the toner to the receptor layer. The presence of fillers in the layer receiving the toner also presents the disadvantage of requiring a thickness of said layer which is greater than that required merely from the standpoint of enhancing the adhesion of the toner to the base.

Transparencies for electrostatic reprography


Before a phosphoric acid fuel cell generates electric energy, a cathode is supplied with a hydrogen gas (fuel gas) and air (oxygen-containing gas) to cause a reaction between hydrogen and oxygen. At this time, the hydrogen and the oxygen are caused to react with each other under a condition in which the concentration of phosphoric acid at the time the amount of water produced by the reaction (liquid water) for reducing the concentration of phosphoric acid and the amount of water evaporated from phosphoric acid are in equilibrium is equal to or greater than a reference phosphoric acid concentration which is capable of keeping the fuel cell at a desired performance level. The temperature of an electrolyte electrode assembly of the fuel cell is increased by the heat which is generated by the reaction.

1. Field of the Invention
The present invention relates to a method of operating a phosphoric acid fuel cell (PAFC) including an assembly which comprises an anode, a cathode, and an electrolyte layer impregnated with a phosphoric acid and interposed between the anode and the cathode.
2. Description of the Related Art
Each unit of the phosphoric acid fuel cell has an electrolyte electrode assembly comprising an anode, a cathode, and an electrolyte layer impregnated with phosphoric acid and interposed between the anode and the cathode. The matrix which is impregnated with phosphoric acid is generally made of porous body of silicon carbide. However, it has been proposed to use a basic polymeric membrane of polybenzimidazole or the like (see U.S. Pat. No. 5,525,436).
Usually, the phosphoric acid fuel cell includes a predetermined number of unit cells which are stacked together and electrically connected in series to form a stack body.
For operating the phosphoric acid fuel cell, the anode is supplied with a fuel gas (hydrogen-containing gas), and the cathode is supplied with an oxygen-containing gas. Hydrogen in the hydrogen-containing gas which is supplied to the anode is ionized by the anode according to the following formula (A), generating hydrogen ions and electrons:2H2→4H++4e  (A)
The generated hydrogen ions move through the electrolyte layer to the cathode. The electrons are transmitted to an external circuit which is electrically connected to the anode and the cathode. After the electrons are used as a DC electric energy for energizing the external circuit, they reach the cathode.
The hydrogen ions that have moved to the cathode and the electrodes that have reached the cathode via the external circuit react with oxygen contained in the oxygen-containing gas supplied to the cathode according to the formula (B):O2+4H++4e→2H2O  (B)
The electrochemical reaction is an exothermic reaction. Therefore, heat is generated in operating the fuel cell.
When the phosphoric acid fuel cell is operated at a temperature lower than 100° C. which is the boiling point of water, the ratio of H2O generated as a liquid (water) increases, and the generated water remains stagnant in the phosphoric acid fuel cell. Then, the phosphoric acid in the electrolyte layer is dissolved into the generated water, and discharged together with the generated water when the water is finally discharged out of the fuel cell. As a result, the concentration of the phosphoric acid in the electrolyte layer is lowered, degrading the cell characteristics of the phosphoric acid fuel cell.
The phosphoric acid fuel cell is usually operated in a temperature range from 140° C. to 190° C. in order to avoid the above drawback. Specifically, the phosphoric acid fuel cell is heated to a temperature above 100° C. by a heating means such as a heater. Thereafter, the fuel gas and the oxygen-containing gas are supplied to react as described above, and the fuel cell is further heated up to the temperature range from 140° C. to 190° C. with the heat generated by the reaction.
However, the above heating process is disadvantageous because it takes a long period of time until the phosphoric acid fuel cell reaches the operating temperature. The phosphoric acid fuel cell thus suffers a practical problem in that it cannot generate electric energy immediately when desired because it takes a long period time until the fuel cell becomes ready to operate stably in a steady state.
One solution would be to use a heater having a large heat-generating capability. However, such a heater would be large in size, make the overall fuel cell system also large in size, and greatly lower the energy efficiency per volume and weight.
Japanese laid-open patent publication No. 63-225477 and U.S. Pat. No. 6,103,410 disclose a process of supplying a fuel gas and an oxygen-containing gas simultaneously to a cathode of a fuel cell, causing a reaction represented by the formula (C) shown below, and heating the phosphoric acid fuel cell with the heat generated in the reaction:2H2+O2→2H2O  (C)
Even according to the above disclosed process, liquid water is generated when the temperature of the phosphoric acid fuel cell is lower than 100° C. Therefore, the phosphoric acid in the electrolyte layer is dissolved into the generated water, and discharged together with the generated water out of the fuel cell. Consequently, it is impossible to avoid the shortcoming that the cell characteristics of the phosphoric acid fuel cell are lowered simply by the reaction of hydrogen and oxygen.

Method of operating phosphoric acid fuel cell


A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

1. Technical Field
The present disclosure relates to semiconductor devices and methods for fabricating the same.
2. Description of the Related Art
Wide-bandgap semiconductors are applied to various semiconductor devices such as power devices, devices with enhanced environmental resistance, high-temperature operating devices, and high-frequency devices. Among such devices, attention has been directed to applications to power devices such as switching devices and rectifying devices.
Among wide-bandgap semiconductors, silicon carbide (SiC) is a semiconductor material that enables relatively easy fabrication of a substrate and also enables formation of a silicon dioxide (SiO2) layer, which is a high-quality gate insulating layer, by thermal oxidation. In view of this, power devices using SiC have been actively developed (see, for example, Japanese Unexamined Patent Application Publication No. 2012-151400).
Examples of a switching device for a power device using SiC include a metal insulator semiconductor field effect transistor (hereinafter referred to as a "MISFET") and a metal semiconductor field effect transistor (hereinafter referred to as a "MESFET").
The electrical breakdown field and thermal conductivity of SiC are higher than those of Si. Thus, a SiC power device using SiC can increase the breakdown voltage and reduce a loss more easily than a Si power device. In the case of obtaining the same performance as the Si power device, the SIC power device can significantly reduce the device area and thickness, as compared to the Si power device.
As the device area and thickness decrease, the parasitic capacitance of a gate electrode with respect to a substrate decreases. SiC has a higher electron saturation velocity than that of Si. By utilizing these advantages, the SiC power device performs a switching operation at a much higher speed than the Si power device.
To obtain a SiC power device that can operate at high speed while taking advantages of the above-described features, Japanese Unexamined Patent Application Publication No. 2012-151400 describes a SiC power device including a gate insulating layer with a double-layer structure of an oxidized layer doped with phosphorus and an insulating layer for reducing diffusion of phosphorus. Japanese Unexamined Patent Application Publication No. 2012-151400 describes that this structure reduces the interface state density at the interface between a silicon carbide semiconductor layer and the insulating layer and, thereby, increases on mobility.

Semiconductor device and method for fabricating the same

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A method for analytically reconstructing a multi-axial computed tomography (CT) dataset, acquired using one or more longitudinally-offset x-ray beams emitted from multiple x-ray sources is provided. The method comprises acquiring one or more CT axial projection datasets, wherein the CT axial projection datasets are acquired using less than a full scan of data. The method further comprises reconstructing the CT axial projection datasets to generate a reconstructed image volume. The reconstruction comprises back projecting one or more voxels comprising the multi-axial CT dataset, along one or more projection views, based upon a cone-angle weight determined for the voxels, wherein the cone-angle weight for the voxels is determined along a longitudinal direction.

The invention relates generally to multi-source inverse geometry CT ("IGCT") systems and more particularly to a method and system for three-dimensional analytic reconstruction of cone-beam projection data, acquired using an IGCT system.
Most modern CT scanners are based on a third generation architecture, which embodies a single x-ray source and a large x-ray detector. The x-ray detector can be a one-dimensional, usually curved, array of detector cells, resulting in fan-beam geometry. In axial scans (i.e. the patient table does not move during the gantry rotation) the result is a purely planar dataset to which two-dimensional ("2D") filtered backprojection (FBP) can be applied. Reconstruction is theoretically exact, and any possible image artifacts may come from physical limitations of the scanner, such as quantum noise, aliasing, beam hardening, and scattered radiation.
In the early 1980's, helical (or spiral) CT systems were introduced. Such systems acquired data faster by translating the patient table during the gantry rotation. In a helical CT system, the raw CT data is typically interpolated to 2D planar datasets as if it was acquired without table translation, and 2D FBP is applied.
Since about 1990, multi-slice or multi-detector-row CT systems have become the standard CT architecture for premium medical scanners, wherein the detector has multiple rows, i.e. a two-dimensional array of detector cells, resulting in cone-beam geometry. Since these geometries do not result in planar datasets, 2D image reconstruction algorithms will not be based on the correct scan geometry and may result in cone-beam artifacts. For axial scan mode, Feldkamp, Davis, and Kress proposed a three-dimensional ("3D") cone-beam reconstruction algorithm ("FDK algorithm") that adapts 2D fan-beam filtered backprojection (FBP) to cone-beam geometry. The FDK algorithm works well near the mid-plane and near the center of rotation, but artifacts occur and get worse as the cone-angle increases. For 40 mm-coverage scanners (which typically corresponds to about a 4 degree cone-angle) significant artifacts occur, particularly towards the z=−20 mm and z=20 mm slices. The raw CT data is actually fundamentally incomplete in 3D axial scans, and therefore, even the best thinkable algorithm will result in artifacts in some cases.
On the other hand, in helical cone-beam scans, the data is fundamentally complete (provided the table speed is not too high compared to the gantry rotation speed and the slice thickness) and therefore exact reconstruction is possible. The FDK algorithm has been adapted for helical scan modes, but results in non-exact or approximate reconstruction. Accordingly, exact 3D helical cone-beam reconstruction algorithms ("Katsevitch algorithms") have been developed, which perform filtering operations along special filter lines followed by backprojection. Disadvantages associated with the Katsevitch algorithms are that such algorithms assume the detector surfaces are continuously sampled, and that such algorithms have other associated limitations.
Another disadvantage associated with the fan-beam and cone-beam geometries discussed above is that each type of geometry has a limited field of view ("FOV"). In a fan-based geometry, the FOV is an area of a scannable object that constantly receives an x-ray beam as the source and detector rotate around the scannable object. At some image voxels outside the FOV, the projection data is incomplete. Consequently, the size of the FOV and how many artifacts (if any) it contains are important, the goal being to make the FOV as large as possible and as free of as many artifacts as possible. In conventional CT systems, the size of the FOV is proportional to the trans-axial size of the x-ray detector. The larger the detector, the larger the FOV will be, and vice versa. Increasing the size of the detector makes the FOV larger but is technically difficult and costly to implement.
As an alternative to using a larger detector to cover the FOV, multi-source CT imaging systems have been developed wherein multiple sources sequentially project a part of the FOV onto a much smaller detector. Specifically, these systems typically use a small detector combined with a large distributed source, on which multiple x-ray sources are arrayed trans-axially (in the x-y-plane) and longitudinally (along the z-axis). Each x-ray source emits a fan-beam (or a cone-beam) at different times, and the projection data (e.g., sinograms) is captured by the detector. FIG. 1 is a three-dimensional perspective view of a multi-source inverse geometry CT (IGCT) system. As shown in FIG. 1, the system 100 includes a detector 101 combined with a large distributed x-ray source 102, on which multiple x-ray sources 103 are arrayed trans-axially (in the x-y-plane) and longitudinally (along the z-axis). Each x-ray source 103 emits a fan-beam (or a cone-beam) 104 at different times, and the projection data (e.g., sinograms) 105 is captured by the detector 101. Additionally, the detector 101, the distributed source 102, and the fan beams (or cone-beams) 104 may be axially rotated about a rotational axis 107. The projection data 105 captured by the detector 101 is processed to reconstruct an object of interest within the field of view 106. Trans-axially, the multiple x-ray sources 103 are positioned preferably on an iso-centered arc so that all corresponding fan beams (or cone beams) 104 can be rotated to fit into a conventional third generation system with an iso-focused detector. This makes exact re-binning to full cone beams possible and also helps to achieve a uniform beam profile. The resulting dataset can be re-arranged or re-binned into multiple longitudinally offset third-generation datasets. An algorithm developed for the multiple x-ray sources 103 distributed in z can also be applied to multiple longitudinally-offset axial scans with a conventional third generation CT system, and vice versa. While positioning the sources on iso-centric arcs is desirable for these reasons, other arrangements, such as detector-centered arcs and flat arrays, can also be used.
An embodiment of multi-source projection data re-binning is shown in FIGS. 2 and 3. In FIG. 2, a multi-source IGCT system 200 includes a single x-ray detector array 201 and a plurality of x-ray sources 203, which are arranged along an iso-centered arc at a predetermined radius from the x-ray detector 201. In use, each x-ray source 203 projects a beam 202, 204 onto the detector 201. Each beam 202, 204 creates a sinogram (not shown). Thus, as can be appreciated from FIG. 2, raw projection data from the multi-source IGCT system 200 comprises a group of sinograms that are generated by the x-ray sources 203.
In FIG. 3, a conventional third generation CT system 300 is shown that comprises a single x-ray source 303 positioned at a predetermined distance from at least two detector arrays 301 that are aligned along an iso-centered arc. Comparing FIGS. 2 and 3, it is seen that the beam 202 in the IGCT system 200 corresponds to the beam 302 in the third generation CT system 300, and that the beam 204 in the IGCT system 200 corresponds to the beam 304 in the third generation CT system 300. Consequently, sinograms that correspond to the beams 202, 204 in FIG. 2 and that are in the same trans-axial plane may be combined and re-arranged by a re-binning process. When each x-ray source 203 on the same trans-axial plane is positioned on the same iso-centered circle (e.g. shifted to the point occupied by the single point source 303 in FIG. 3), exact rebinning is possible. As FIG. 3 illustrates, the resulting re-binned sinogram will exactly correspond to a sinogram from a third generation system having multiple flat panel detectors 301 positioned along an iso-centered circle 306.
Multi-source IGCT 3D rebinning may use any of the following three techniques (or combinations thereof): (1) z-rebinning, (2) trans-axial (x-y) rebinning, and (3) feathering between sub-views, each of which is further described below.
The z re-binning technique re-bins the IGCT projection data for example to a source-focused-detector geometry. For example, each sinogram may be rebinned using 1D linear interpolation with extrapolation. Depending on the new source-to-iso-center distance, a larger detector height may be required to capture all the information.
The trans-axial (x-y) rebinning technique further rebins the IGCT projection data to a third generation geometry with a source-focused detector. To perform trans-axial rebinning, the angle and the distance from center for each ray are computed and interpolated into the desired geometry.
A process called "feathering" is used in situations where some mismatch may occur between measurements at the edge of the detector array across neighboring sub-sinograms. To mitigate this discontinuity, a slightly larger detector can be used, such that there is some overlap between neighboring sub-sinograms. The overlapping channels are multiplied with linearly decreasing/increasing weights and added together with the weighted channels from the adjacent sub-sinograms.
FIG. 4 illustrates multi-source IGCT projection data 401 that is re-binned and/or feathered to produce a re-binned third generation sinogram 402. After the re-binning described above has been performed, the resulting multiple third generation sinograms are associated with x-ray sources 103 offset along the z-axis (as illustrated in FIG. 5). Therefore, any conventional 3D cone-beam reconstruction algorithm—such as FDK—can be used to reconstruct each of the third generation datasets. With multiple sinograms from different sources in z-axis, combining this projection data results in better reconstructions as compared to a single third-generation dataset. This is especially true since cone beam artifacts due to data insufficiency may be reduced using additional information from longitudinally offset data.
While multi-source CT imaging systems can extend the axial scan coverage to a large extent, without sacrificing image quality due to cone-beam artifacts, image reconstruction is typically based on the fact that a full scan of data (i.e., based on a full rotation of the CT gantry) can be acquired from the multiple x-ray sources. However, when only less than a full scan of data is available, conjugate rays are not available, and depending on system geometry, there can even be a region in the reconstruction volume that does not get illuminated by any x-ray source for a given view angle.
It would be desirable to develop a method to mitigate cone-beam artifacts and increase scan coverage by combining information from longitudinally distributed x-ray sources without sacrificing image quality, when only less than a full scan of data is available. In addition, it would be desirable to develop a method and system for analytically reconstructing cone-beam projection data, by combining information from longitudinally distributed x-ray sources, when only less than a full scan data is available.

Method for analytic reconstruction of cone-beam projection data for multi-source inverse geometry CT systems


An improved wheel interface for walkers that includes a spring interface connection between the frame of the walker and the wheel assembly. The walker is able to better absorb shocks that occur when encountering an obstacle such as a curb, allowing the user to avoid the necessity of allowing the walker to fall or to risk falling himself.

Older and disabled persons often require the additional balance, stability and support offered by a walker. Walkers of various designs are well-known in the art; however, a standard walker does not "give" when it hits a bump in the sidewalk or the curb. As a result, the walker can become stuck, requiring the user to nudge the walker over the impediment with his knee. Additionally, this lack of "give" makes it more likely that that walker will become off-balance causing the walker to fall forward and collapse. The user may then have to either let go of the walker and/or risk falling. It is therefore an object of this invention to provide an improved walker that allows for shocks caused by rough ground and impediments to be ameliorated.


A CPU (30) sets a plurality of stages in which a plurality of opposing characters which are to become opponents in a battle become able to appear, and causes a player to advance to a next stage after having won over respective opposing characters in a certain stage, thereby increasing the number of cards available in a battle.

1. Field of the Invention
The present invention relates to an improvement in a game machine which enables a player and an opponent to play a battle by way of laying down their cards on a game screen. Also, the present invention relates to an improvement in a method of controlling the operation of the game machine. Further, the present invention relates to an improvement in a recording medium, such as a computer readable medium, having recorded thereon an operation control program for controlling the game machine.
The present application is based on Japanese Patent Application No. 2000-230124, which is incorporated herein by reference.
2. Description of the Related Art
There has been in vogue a game in which a player and an opponent play a battle by way of laying their cards in a predetermined area on a display section of a game machine through actuation of operation buttons. In a game machine of the type, a plurality of cards capable of being used for a battle are stored in a memory location called "baggage." A predetermined number of cards chosen from the cards are stored in a memory location called a "deck." Card information is read directly from the deck, and a card game is effected.
In a game of the type, entertainment value is increased as the number of cards capable of being stored in a deck are stored in the baggage is increased. To this end, it is considered that the number of cards usable in a battle is increased, by way of purchasing several from among an abundance of available recording mediums having card information recorded thereon.
Even when the number of cards usable in a battle is increased in such a way, no additional entertainment value is found in the manner of increasing the number of cards. Therefore, there has existed a desire for increasing the number of cards usable in a battle while a player is enjoying a game.

Game machine, method of controlling operation of the game machine, and computer readable medium having recorded thereon operation control program for controlling the game machine


The invention relates to a process and a centrifuge for removing solids located on a cylindrical casing wall (3) of a rotating centrifuge, in particular solids precipitated in the centrifuge from a liquid-solid mixture, to a solids exit opening (6) by sweeping the entire casing inner wall (9) in the direction of the solids exit opening (6). In order to reduce clogging, it is proposed according to the invention that in each case the casing inner wall (9) is swept in strips up to the solids exit opening (6), during one sweep up to the solids exit opening (6) only a part of the casing inner wall (9) is swept, and after a certain time the entire casing inner wall (9) is swept by strips (11) swept sequentially in time.

The invention relates to a process for removing solids located on a cylindrical casing wall of a rotating centrifuge, in particular solids precipitated in the centrifuge from a liquid-solid mixture. The solids are removed to a solids exit opening by sweeping the entire casing inner wall in the direction of the solids exit opening. The invention also relates to a centrifuge for carrying out this process, having a rotating casing wall and a transport device which sweeps the casing inner wall towards the solids exit opening for the purpose of removing the solids.
The precipitation of solids in a liquid-solid mixture through the use of centrifugal force is known, in particular, in the metal-processing industry. In a rotating casing wall, solids of a mixture introduced beforehand are precipitated on the casing inner wall because of the higher density, and are then removed by a transport device towards a solids exit opening. In known centrifuges, the transport devices are formed by worms which rest with their radial outer rim on the casing wall and sweep the latter owing to a slight difference in rotational speed with reference to the casing wall. A problem is posed by the danger of clogging, which can lead to blocking of the worm. Automatic increase of the worm speed is provided in the prior art as a countermeasure against clogging, and this requires special outlay on control measures.

Centrifuge with an eccentrically mounted worm for transporting solids


A pressure-sensitive displacement sensor comprises: (A) a contact portion (11) which includes: a semi-conductive matrix layer (14) containing conductive materials with a predetermined density, wherein the semi-conductive matrix layer is formed with a soft material having elasticity and has a resistance (Rx) under a normal condition without subjecting to a contact pressure, and when the semi-conductive layer is pressed, a density of the conductive materials in the semi-conductive matrix layer is increased due to compression of the soft semi-conductive layer, which results in reduction of the resistance (Rx); a first conductive layer (12) disposed on a first surface of the semi-conductive matrix layer; and a second conductive layer (13) disposed on a second surface of the semi-conductive matrix layer; (B) a first resistor (19) having one side connected to the first conductive layer and the other side connected to a power source; (C) a second resistor (21) having one side connected to the second conductive layer and the other side connected to ground; (D) a first voltage comparator (16) having a plus terminal and a minus terminal, the minus terminal connected to the first conductive layer; (E) a second voltage comparator (17) having a plus terminal and a minus terminal, the plus terminal connected to the second conductive layer; (F) a third resistor (22) having one side connected to the power source and the other side connected to the plus terminal of the first voltage comparator; (G) a fourth resistor (23) having one side connected to the plus terminal of the first voltage comparator and the other side connected to the minus terminal of the second voltage comparator; (H) a fifth resistor (24) having one side connected to ground and the other side connected to the minus terminal of the second voltage comparator; and (I) an OR-gate (18) connected to the outputs of the first and second voltage comparators and operable to output signals in response to the outputs of the first and second voltage comparators.

A sensor is a device that changes a physical quantity to another physical quantity in response to a physical stimulation.
There are typically two kinds of sensors;
Contacting sensor that perceives the existence of an object by contacting the object; and
Non-contacting sensor that perceives the existence of an object without contacting the object.
The contacting sensor is used wider than the non-contacting sensor. For one example of the contacting sensors, a limit switch is often used in a place where the safety needs to be secured, for example, to protect from explosion, and it is not sensitive to an effect of magnetic field.
However, it was difficult to install a conventional contacting sensor to some part of the limited device that is narrower than the limit switch space.
Therefore, the conventional contacting sensors have limitations to install to the various featured devices.


A computer usable medium including computer usable program code for determining an oilfield parameter for a drilling operation. The computer usable program code when executed causing a processor to identify first decision factors and second decision factors about the drilling operation, where each of the first decision factors is contained within first nodes, and where each of the second decision factors is contained within second nodes, where the first and second nodes contain common nodes. The computer usable program code further causing the processor to associate the first nodes to create a first belief network and associate the second nodes to create a second belief network, associate the common nodes of the first belief network with the common nodes of the second belief network to form a multinet belief network, and generate at least one oilfield parameter from the multinet belief network.

1. Field of the Invention
This invention relates to methods and systems for determining an oilfield parameter for a drilling operation in an oilfield. In particular, the invention provides methods, apparatuses, and systems to more effectively and efficiently determine an oilfield parameter for a drilling operation in an oilfield using combined belief networks.
2. Background of the Invention
During the oilfield operations, data is typically collected for analysis and/or monitoring of the oilfield operations. Such data may include, for example, subterranean formation, equipment, historical and other data. Data concerning the subterranean formation is collected using a variety of sources. Such formation data may be static or dynamic. Static data relates to formation structure and geological stratigraphy that defines the geological structure of the subterranean formation. Dynamic data relates to fluids flowing through the geologic structures of the subterranean formation. Such static and/or dynamic data may be collected to learn more about the formations and the valuable assets contained therein.
While performing these oilfield operations, various conditions can occur while drilling or pumping that can require prompt action. However, these conditions are noticeable only from the data collected. Because different operators and engineers can interpret the collected data to arrive at dissimilar conclusions, it is often difficult to accurately characterize the downhole conditions that are occurring. Determining a most acceptable course of action to take in response to the encountered condition can therefore take time away from production or drilling, resulting in lost profits to the enterprise.
Despite improvements in data collection and modeling, there remains a need to quickly and effectively interpret and model data collected from a wellsite in response to an encountered condition.

This patent is subject to a terminal disclaimer.

Combining belief networks to generate expected outcome


A purified enzyme-I is obtained that participates in C-terminal amidation by acting on a peptide C-terminal glycine adduct to form a peptide C-terminal .alpha.-hydroxyglycine adduct. The enzyme has an optimum pH of about 5 to 7, an optimum temperature of 25.degree. to 40.degree. C. and a molecular weight of about 25 kDa or about 36 kDa, and metal ions and ascorbic acid act as a cofactor. A purified enzyme-II is obtained that participates in C-terminal amidation by acting on a peptide C-terminal .alpha.-hydroxyglycine adduct to produce a C-terminal amidated compound. The enzyme has an optimum pH of about 5 to 6, an optimum temperature of 15.degree. to 35.degree. C. and a molecular weight of about 40 kDa or about 43 kDa. Enzyme-I does not act on the peptide C-terminal .alpha.-hydroxyglycine adduct and enzyme-II does not act on the peptide C-terminal glycine adduct. The enzymes may be purified from a biological material such as horse serum by affinity chromatography using a peptide C-terminal glycine adduct as a ligand. The enzymes may also be obtained from host cells transformed with a plasmid containing a cDNA coding for the enzymes. Assay of activity of the enzymes is carried out by measuring adduct (II) or the compound (III) that has been isolated such as by high performance liquid chromatography with the use of an acetonitrile-containing buffer.

In the past, the enzyme participating in the enzymatic reaction in vivo, i.e., a C-terminal amidation of a C-terminal glycine adduct of peptides (compound in which glycine is peptide-bonded to C-terminal residue) is called peptidylglycine-.alpha.-amidating monooxygenase (C-terminal amidating enzyme) (EC.184.108.40.206) (Bradbury et. al., Nature, 298, 686, 1982: Glembotski et. al., J. Biol. Chem., 259. 6385, 1984), and is considered to catalyze the following reaction: ##STR1##
To clarify the amidation mechanism in vivo and utilize the enzyme for the method of converting the peptides which exhibit a physilogical activity for the first time by an amidation of the C-terminal with the peptide produced by the recombinant DNA technique, for example, calcitonin and gastrin, in vitro, attempts have been made to purify this enzyme. For example, there have been reported those derived from bovine pituitary gland middle lobe (Murthy et. al., J. Biol. Chem., 261, 1815, 1986), porcine pituitary gland (Kizer et. al., Endocrinology, 118, 2262, 1986; Bradbury et. al., Eur. J. Biochem., 169, 579, 1987), porcine heart atrium (Kojima et. al., J. Biochem., 105, 440, 1989), Xenopus body skin (Mizuno et. al., Biochem., Biophys. Res. Commun., 137, 984, 1986), rat thyroid gland tumor (Mehta et. al., Arch. Biochem., Biophys., 261, 44, 1988).
On the other hand, since it is difficult to procure a large amount of these purified enzymes, attempts have been made to isolate the cDNA's necessary for expression of these enzymes by use of the recombinant DNA technique generally practiced in recent years, and the production of the enzymes by utilizing same. For example, Eipper B. A, et. al. in Mol. Endocrinol. 1, 777-790, 1987, Ohsuye K. et. al. in Biochem. Biophys. Res. Commun., 150, 1275-1281, 1988, Stoffers, D. A. et. al. in Proc. Natl. Acad. Sci., USA, 86, 735-739, 1989, and Glauder, J. et. al. in Biochem. Biophys. Res. Commun., 169, 551-558, 1990, have reported peptide C-terminal amidating enzyme cDNA's derived from bovine pituitary gland, frog skin, rat atrium and human thyroid gland cell, respectively. Further, although not necessarily having a satisfactory productivity, there are also known examples of peptide C-terminal amidating enzymes produced by using of the recombinant DNA technique utilizing the cDNA derived from frog and bovine (e.g., see Japanese Unexamined Patent Publication (Kokai) No. 1-104168, Published International Application: WO89/02460, and Perkins et. al., Mol. Endocrinol., 4, 132-139, 1990).
On the other hand, these proteins have been reported to have molecular weights of 38, 42 or 54 kDa in bovine, 39 kDa in frog, and 41, 50, or 75 kDa in rat, which are very different from each other, depending on the collecting methods, etc. For example, the literature of Bradbury et. al., described above, Ramer et. al., 110, 8526-8532 (1988) and Young et. al., J. Am. Chem. Soc. 111, 1933-1934 (1989) suggest the existence of reaction intermediatesm, but there are no current examples which clarify the isolation of an intermediate, and the relationship between the intermediate and the amidating enzyme.
As described above, the peptide C-terminal amidating enzyme exhibits a very interesting action in vivo, and a composition having a constant purity derived from a specific living body organ is known. Nevertheless, these compositions cannot be used for the production of a peptide C-terminal amidated compound in vivo, as the purity and stability as well as to production costs thereof are not satisfactory. To solve these problems, on the premise that it is necessary to collect basic knowledge concerning the enzyme, i.e., clarify the reaction mechanism when carrying out the C-terminal amidation reaction, the present inventors attempted to isolate the intermediate product, and consequently successfully isolated the intermediate and determined the structure thereof. From this result it was found that the enzymatic active substance called the C-terminal amidating enzyme of the prior art is not a one-step reaction as considered in the prior art, but is a two-step reaction through the intermediate (corresponding to C-terminal .alpha.-hydroxylglycine adduct).
Since it is predicted that an efficient conversion of a peptide C-terminal glycine adduct into the corresponding amidated compound can be carried out by the single or combined use of enzymes catalyzing the respective reaction under adequate conditions, it will become necessary to provide these enzymes. Further, where the existence of these enzymes can be confirmed, it will become necessary to provide an efficient method of preparing same.

Purified enzymes participating in C-terminal amidation


Systems and methods for linking a data set to respective locations of relevant data elements in documents included in electronic files in which a formatting server identifies a specific location of each occurrence of each of a plurality of different categories of fields in documents in an electronic file and links an identifier of each of the categories to each specific location of each of the occurrences. Thereafter, a review server compares data populating all of the occurrences at each specific location of at least one of the categories of fields to which the identifier of the particular category of fields is linked and generates a notification when the data populating any of the occurrences differs from data populating any of the other occurrences of the same category of fields.

A mortgage loan package is a collection of all documents needed for the processing and closing of a mortgage loan. Such mortgage loan package may include, for example, relevant information about the borrower, such as borrower pay stubs, borrower W2 forms, and borrower ID verification; about the property, such as an appraisal; and about the mortgage loan, such as the mortgage loan note. This information is used in underwriting of the loan and may consist of numerous file documents in various electronic formats. Typically, many thousands of mortgage loans may be traded between different counterparties in the secondary mortgage market every day. When a counterparty invests in the purchase of a mortgage loan, the counterparty must review the loan file to ensure that the loan was underwritten according to guidelines suitable to the investor.
Currently, most loans are underwritten according to requirements of secondary mortgage market lenders, such as Federal National Mortgage Association (FNMA) and Federal Home Loan Mortgage Corporation (FHLMC) guidelines, but there are also many loans that are underwritten to requirements of private investors. Such underwriting requirements may vary according to a particular investor, and standardization in terms of loan documents included in a mortgage loan package is limited at best. For example, residential appraisals may typically vary from state to state, pay stubs may depend on the employer, and documents used for verification of borrower identification, such as drivers' licenses, may also vary depending on the state.
The present lack of standardization results in a tedious and cumbersome process for underwriters or buyers of mortgage loans. For example, upon receiving a mortgage loan file by an investor, it is necessary to verify data consistency and accuracy in hundreds of instances, which may currently require careful visual checking of information that is not received in a standard format. Typically, when an investor purchases a mortgage loan, the purchase may be based on a small subset of data known as a data set, and loan files are often received with data sets which do not lead back to source documents, making verification of the validity of that data very difficult. Therefor, the investor must review the mortgage loan file to ensure that it meets all the investor's underwriting requirements. Such loan file review is currently a complicated process which may involve, for example, physically inspecting each of hundreds of pages of many different kinds of loan documents included in the mortgage loan file.
At least some effort has previously been made to develop a standard data set to accompany a mortgage loan file, such as the Mortgage Industry Standards Maintenance Organization (MISMO) data set sponsored by FNMA and FHLMC that identifies data points and data delivery format for delivery of loans to FNMA and FHLMC. While the MISMO data set is intended to be representative of what is in a mortgage loan file, the MISMO data set does not include anything that links to the actual mortgage loan documents in the mortgage loan file. Thus, there is nothing in the MISMO data set to verify that a MISMO data set accompanying a mortgage loan file actually corresponds to information contained in the mortgage loan documents. Additionally, many optical checks, such as signatures, are not captured in these data sets.
There is a current need for systems and methods for linking a data set to locations of relevant elements of complex data sets to respective locations of relevant data elements in documents included in electronic files, such as mortgage loan files, that address the problems of the above identified legacy mechanisms. The problem solved by embodiments of the invention is rooted in technological limitations of such legacy approaches. Improved techniques and, in particular, improved applications of technology are needed to address the problems of currently employed mechanisms. More specifically, the aforementioned legacy approaches fail to achieve the sought-after capabilities of the herein-disclosed techniques for systems and methods for linking a data set to locations of relevant elements of complex data sets to respective locations of relevant data elements in documents included in electronic files.

Systems and methods for linking a data set to recurring data elements