The present invention provides a method and a circuit for driving a color liquid crystal display in a normal driving mode and a power saving mode, wherein in the normal driving mode, voltages corresponding to image display data are applied to data electrodes of the color liquid crystal display, and wherein in the power saving mode, voltages corresponding to highly significant bit signals of the image display data are applied as display data signals to the data electrodes.

1. Field of the Invention
The present invention relates to a method of driving a liquid crystal display and a driver circuit for driving the liquid crystal display as well as an electronic device with the driver circuit, and more particularly to an improvement of the driver circuit and the driving method for driving a color liquid crystal display with a relatively small display screen in a line inversion driving system or in a frame inversion driving system at a reduced power consumption.
2. Description of the Related Art
The liquid crystal display has been applied to various electronic devices such as note-type computers, palm-type computers, pocket-type computers, mobile terminals such as personal digital assistants, mobile phones, and personal handyphone systems. The advanced liquid crystal display is a color liquid crystal display.
FIG. 1 is a block diagram illustrative of a first conventional driver circuit for driving a color liquid crystal display. A color liquid crystal display 1 may be driven by an active matrix driving system using thin film transistors as switching devices. The color liquid crystal display 1 includes a plurality of scanning lines or gate lines which exend parallel to each other in a column direction at a constant pitch, and a plurality of data lines or source lines which extend parallel to each other in a row direction at another constant pitch, as well as a two-dimensional matrix array of pixels, each of which is positioned in an area defined by adjacent two of the scanning lines and adjacent two of the data lines.
Each of the pixels further includes a liquid crystal cell as an equivalent capacitive load, a common electrode, a thin film transistor for driving the liquid crystal cell, and a data electrode for storing data charge in a vertical synchronizing term. A gate electrode of the thin film transistor is connected to the scanning line. The gate electrode of the thin film transistor serves as a scanning electrode.
The color liquid crystal display 1 may be driven as follows. The common electrode is applied with a common potential Vcom. The data electrode is applied with data signals, wherein the data signals may include data red signals, data green signals and data blue signals, which have been generated from red data DR, green data DG, and blue data DB as digital image data. The scanning electrode is applied with a scanning signal which has been generated from a horizontal synchronizing signal SH and a vertical synchronizing signal SV.
The following description with reference to FIG. 1 will be made assuming that the color liquid crystal display 1 is a normally white type color liquid crystal display which is high in transmittivity under no voltage application.
The driver circuit for driving the color liquid crystal display 1 mainly includes a control circuit 2, a gray scale power supply 3, a common power supply 4, a data electrode driver circuit 5, and a scanning electrode driver circuit 6.
The control circuit 2 may, for example, comprise an application specific integrated circuit (ASIC). The control circuit 2 receives parallel inputs of red data DR of 6-bits, green data DG of 6-bits and blue data DB of 6-bits. The control circuit 2 converts the red data DR, green data DG and blue data DB into 18-bits display data D00-D05, D10-D15 and D20-D25 respectively, and outputs the 18-bits display data. The, 18-bits display data outputted from the control circuit 2 are supplied to the data electrode driver circuit 5.
The control circuit 2 also receives further inputs of a dot-clock signal DCLK, a horizontal synchronizing signal SH, and a vertical synchronizing signal SV, so that the control circuit 2 generates a strobe signal STB, a clock signal CLK, a horizontal start pulse signal STH, a vertical start pulse signal STV, a polarity signal POL, a data inversion signal INV from the dot-clock signal DCLK, the horizontal synchronizing signal SH, and the vertical synchronizing signal SV. The strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV are supplied to the data electrode driver circuit 5. The polarity signal POL is supplied to the gray scale power supply 3 and the common power supply 4. The vertical start pulse signal STV is supplied to the scanning electrode driver circuit 6.
The strobe signal STB has the same cycle as the horizontal synchronizing signal SH. The clock signal CLK may be either identical with or different in frequency from the dot-clock signal DCLK. The clock signal CLK may be used for allowing shift registers in the data electrode driver circuit 5 to generate sampling pulse signals SP1-SP176 from the horizontal start pulse signal STH.
The horizontal start pulse signal STH is identical in cycle to the horizontal synchronizing signal SH, and delayed from the strobe signal STB by a time corresponding to a few pulses of the clock signal CLK. The polarity signal POL is inverted in a single line unit or in a single horizontal synchronizing cycle for alternating current driving of the color liquid crystal display 1. The vertical start pulse signal STV has the same cycle as the vertical synchronizing signal SV.
The data inversion signal INV is used for the purpose of reducing the power which is consumed by the control circuit 2. If the current 18-bits display data D00-D05, D10-D15 and D20-D25 has at least 10-inverted bits from the previous 18-bits display data, the data inversion signal INV is inverted in synchronizing with the clock signal CLK, instead of inversions of the current 18-bits display data D00-D05, D10-D15 and D20-D25 for the following reasons.
It is general that the control circuit 2 and the gray scale power supply 3 are integrated over a printed board whilst the data electrode driver circuit 5 is mounted as a tape carrier package (TCP) over a film tape carrier which provides an electrical connection between the printed board and the color liquid crystal display 1. The printed board is mounted at an upper portion on a back face of a back light which is attached to the color liquid crystal display 1.
18-signal lines are provided on the film carrier tape for transmitting the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2 to the data electrode driver circuit 5. The 18-signal lines have a line capacitance. In addition, the data electrode driver circuit 5 has an input capacitance of about 20 pF from the control circuit 2. A sufficient current for charging and discharging the line capacitance and the input capacitance would be needed if the polarity of the 18-bits display data D00-D05, D10-D15 and D20-D25 are inverted and supplied to the data electrode driver circuit 5 from the control circuit 2. For reducing the necessary charge and discharge currents to the line capacitance and the input capacitance, it is effective that the data inversion signal INV is inverted, instead of inversions of the 18-bits display data D00-D05, D10-D15 and D20-D25. The reduction of the charge and discharge currents results in a reduction in the power consumed by the control circuit 2.
FIG. 2 is a circuit diagram illustrative of a circuit configuration of a gray scale power supply in the driver circuit shown in FIG. 1. The gray scale power supply 3 includes a series connection of resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, a first pair of switches 8-a and 8-b, a second pair of switches 9a and 9-b, a single inverter 10, and voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7 11-8, and 11-9 as well as gray scale voltage input ports which receive gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9. The gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 have been set for gamma-control.
The gray scale power supply 3 amplifies the gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 and supplies the amplified gray scale voltages to the data electrode driver circuit 5. The polarity inversions of the gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 between positive and negative potentials with reference to the common voltage Vcom applied to the common electrode-are made based on the polarity signal POL in the single line unit.
The resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 are different in resistance values from each other. The switch 8-a has a first terminal applied with a power voltage VDD and a second terminal connected to a first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-1 is connected directly to the second terminal of the switch 8a. The switch 8-a also has a control terminal applied with the polarity signal POL. If the polarity signal POL is low level "L", then the switch 8-a is in OFF-state. If the polarity signal POL is high level "H", then the switch 8-a is in ON-state, whereby the power voltage VDD is applied to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The inverter 10 receives the polarity signal POL and generates an inverted polarity signal /POL. The switch 8-b has a first terminal grounded and a second terminal connected to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-1 is connected directly to the second terminal of the switch 8-b. The switch 8-b also has a control terminal connected to an output from the inverter 10 for receiving the inverted polarity signal /POL from the inverter 10. If the inverted polarity signal /POL is low level "L", then the switch 8-b is in OFF-state. If the inverted polarity signal /POL is high level "H", then the switch 8-b is in ON-state, whereby the ground potential GND is applied to the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The switch 9-a has a first terminal grounded and a second terminal connected to a second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-10 is connected directly to the second terminal of the switch 9-a. The switch 9-a also has a control terminal applied with the polarity signal POL. If the polarity signal POL is low level "L", then the switch 9-a is in OFF-state. If the polarity signal POL is high level "H", then the switch 9-a is in ON-state, whereby the ground potential GND is applied to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The switch 9-b has a first terminal applied with the power voltage VDD and a second terminal connected to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, wherein the resistance 7-10 is connected directly to the second terminal of the switch 9-b. The switch 9-b also has a control terminal connected to the output from the inverter 10 for receiving the inverted polarity signal /POL from the inverter 10. If the inverted polarity signal /POL is low level "L", then the switch 9-b is in OFF-state. If the inverted polarity signal /POL is high level "H", then the switch 9-b is in ON-state, whereby the ground potential GND is applied to the second end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10.
The series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 has first to ninth nodes N1, N2, N3 N4, N5, N6, N7, N8 and N9, at which divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated respectively if the first and second ends of the series connection are biased. The first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 are connected to inputs of the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively, whereby the divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively.
If the polarity signal POL is the high level "H", then the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 is applied with the power voltage VDD, whilst the second end thereof is applied with the ground voltage, whereby positive polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD>V1>V2>V3>V4>V5>V6>V7>V8>V9>GND. The positive-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth positive-polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the data electrode driver circuit 5, provided that the VI1>VI2>VI3>VI4>VI5>VI6>-VI7>VI8->VI9.
If the polarity signal POL is the low level "L", then the first end of the series connection of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10 is applied with the ground voltage, whilst the second end thereof is applied with the power voltage VDD, whereby negative-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD<V1<V2<V3<V4<V5<V6<V7<V8<V9<GND. The negative-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth negative-polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the data electrode driver circuit 5, provided that VI1<VI2<VI3<VI4<VI5<VI6<VI7<VI8<VI9.
The common power supply 4 receives an input of the polarity signal "POL" from the control circuit 2 and supplies the common potential Vcom to the common electrode of the color liquid crystal display 1. If the polarity signal "POL" is in the high level "H", then the common power supply 4 sets the common potential Vcom at the ground levelGND. If the polarity signal "POL" is in the low level "L", then the common power supply 4 sets the common potential Vcom at the power voltage level VDD.
The data electrode driver circuit 5 receives the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV in addition to the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2. The data electrode driver circuit 5 selects the gray scale voltages based on the 18-bits display data D00-D05, D10-D15 and D20-D25 under the controls by the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH and the data inversion signal INV. The data electrode driver circuit S applies the selected gray scale voltages to the data electrodes of the color liquid crystal display 1.
The scanning electrode driver circuit 6 receives the vertical start pulse signal STV from the control circuit 2, so that the scanning electrode driver circuit 6 generates, in sequence, the scanning signals and apples the scanning signals to the scanning electrodes of the color liquid crystal display 1.
FIG. 3 is a block diagram illustrative of the data electrode driver circuit shown in FIG. 1. It is assumed that a resolution of the color liquid crystal display 1 is defined by 176×220 pixels. Since each pixel comprises three-dots of red (R), green (G) and blue (B), then the color liquid crystal display 1 has a 528×220 dot-pixels.
The data electrode driver circuit 5 includes a shift register 12, a data buffer 13, a data register 14, a control circuit 15, a data latch 16, a gray scale voltage generating circuit 17, a gray scale voltage selecting circuit 18, and an output circuit 19.
The shift register 12 is a serial in parallel-out shift register which comprises 176 delay-flip-flops. The shift register 12 receives the clock signal CLK and the horizontal start pulse signal STH from the control circuit 2, so that the shift register 12 shifts the horizontal start pulse signal STH in synchronizing with the clock signal CLK, and generates sampling pulses SP1, SP2, - - - SP176 which comprise a 176-bits parallel-out signal. The data buffer 13 receives the 18-bits display data D00-D05, D10-D15 and D20-D25 and the data inversion signal INV from the control circuit 2, so that the data buffer 13 performs an inversion operation of the 18-bits display data in accordance with the data inversion signal INV, so that the data buffer 13 outputs 18-bits display data D′00-D′05, D′10-D′15 and D′20 -D′25.
FIG. 4 is a partial circuit diagram illustrative of a part of the circuit configuration of the data buffer shown in FIG. 3. The data buffer 13 comprises first to eighteenth data buffer circuits 13a1, 13a2, 13a3, - - - 13a18, and a single control unit 13b. The control unit 13b includes two series connections of plural inverters. The two series connections of plural inverters in the control unit 13b receive the data inversion signal INV and the clock signal CLK from the control circuit 2 respectively, so that the control unit 13b delays the data inversion signal INV and the clock signal CLK from the control circuit 2 by predetermined delay times respectively, whereby the control unit 13b supplies a delayed clock signal CLK1 and a delayed data inversion signal INV1 to the first data buffer circuit 13a1.
The control unit 13b also supplies other delayed clock signals CLK2, CLK3, - - - CLK18 and other delayed data inversion signals INV2, INV3 - - - INV 18 to the remaining second to eighteenth data buffer circuits 13a2, 13a3, - - - 13a18, respectively. The first to eighteenth data buffer circuits 13a1, 13a2, 13a3, - - - 13a18 have the same circuit configuration and perform the same operations, for which reason the following description will focus on the first data buffer circuit 13a1 only.
The first data buffer circuit 13a1 includes a D-flip-flop 20-1, inverters 21-1, 22-1 and 23-1, and a switching circuit 24-1. The switching circuit 24-1 comprises two parallel switches 24-1a and 24-1b. The control unit 13b supplies the delayed clock signal CLK1 to the D-flip-flop 20-1 and the delayed data inversion signal INV1 to the switching circuit 24-1.
The D-flip-flop 20-1 latches a single bit display data D00 in synchronizing with the clock signal CLK1 for a term corresponding to the single pulse width of the clock signal CLK1, and outputs the single bit display data D00. The inverter 21-1 inverts the single bit display data D00, so that the inverted bit display data D00 is supplied to the switch 241b. The non-inverted bit display data D00 outputted from the D-flip-flop 20-1 is also directly supplied to the switch 241a.
If the delayed data inversion signal INV1 from the control unit 13b is high level "H", then the switching circuit 24-1a is placed in the ON-state, whilst the switching circuit 24-1b is placed in the OFF-state, whereby the non-inverted bit display data D00 is transmitted through the series connection of the inverters 22-1 and 23-1 to an output terminal as the output bit display data D′00.
If the delayed data inversion signal INV1 from the control unit 13b is low level "L", then the switching circuit 24-1a is placed in the OFF-state, whilst the switching circuit 24-1b is placed in the ON-state, whereby the inverted bit display data D00 is transmitted through the series connection of the inverters 22-1 and 23-1 to the output terminal as the output single bit display data D′00.
With reference again to FIG. 3, the data register 14-receives the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25 from the data buffer 13 and also receives the sampling pulses SP1, SP2, - - - SP176 from the shift register 12. In synchronizing with the sampling pulses SP1, SP2, - - - SP176, the data register 14 accepts the inputs of the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25 and transmits display data PD1, PD2, PD3, - - - PD528 to the data latch 16.
The control circuit 15 comprises a series connection of plural inverters. The control circuit 15 receives the strobe signal STB from the control circuit 2, so that the control circuit 15 generates a delayed strobe signal STB1 which has a predetermined delay time from the strobe signal STB as well as generates a switch control signal SWA which is opposite in phase to the delayed strobe signal STB1. The control circuit 15 transmits the delayed strobe signal STB1 to the data latch 16 and also transmits the switch control signal SWA to the output circuit 19.
The data latch 16 accepts the inputs of the display data PD1, PD2, PD3, - - - PD528 in synchronizing with a rising edge of the displayed strobe signal STB1 and holds the display data PD1, PD2, PD3, - - - PD528 for a time period of the vertical synchronizing term. In synchronizing with the next rising edge of the delayed strobe signal STB1, the data latch 16 transmits the display data PD1, PD2, PD3, - - - PD528 to the gray scale voltage selecting circuit 18.
FIG. 5 is a circuit diagram illustrative of the gray scale voltage generating circuit shown in FIG. 3. The gray scale voltage generating circuit 17 comprises a single series connection of first to sixty third resistances 25-1, 25-2, 25-3, 25-4, - - - 25-63. The first to sixty third resistances 25-1, 25-2, 25-3, 25-4, - - - 25-63 have respective resistance values which are adjusted to applied voltage to-transmittivity characteristic of the color liquid crystal display 1. The gray scale voltage generating circuit 17 receives first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9 from the gray scale power supply 3.
The first gray scale voltage VI1 is supplied to a first node of the first side of the first resistance 25-1. The second gray scale voltage VI2 is supplied to an eighth node between the seventh resistance 257 and the eighth resistance 25-8. The third gray scale voltage VI3 is supplied to a sixteenth node between the fifteenth resistance 25-15 and the sixteenth resistance 25-16. The fourth gray scale voltage VI4 is supplied to a twenty fourth node between the twenty third resistance 25-23 and the twenty fourth resistance 25-24. The fifth gray scale voltage VI5 is supplied to a thirty second node between the thirty first resistance 25-31 and the thirty second resistance 25-32. The sixth gray scale voltage VI6 is supplied to a fortieth node between the thirty ninth resistance 25-39 and the fortieth resistance 25-40. The seventh gray scale voltage VI7 is supplied to a forty eighth node between the forty seventh resistance 25-47 and the forty eighth resistance 25-48. The eighth gray scale voltage VI8 is supplied to a fifty sixth node between the fifty fifth resistance 25-55 and the fifty sixth resistance 25-56. The ninth gray scale voltage VI9 is supplied to a sixty fourth node of a second side of the sixty third resistance 25-63.
The gray scale voltage generating circuit 17 generates first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9 from the gray scale power supply 3 and also on the respective resistance values of the first to sixty third resistances 25-1, 25-2, 25-3, - - - 25-63. Each of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 may individually be inverted between positive-polarity and negative-polarity with reference to the common potential Vcom.
With reference back to FIG. 3, the generated first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 are supplied to the gray scale voltage selecting circuit 18. Namely, a gray scale signal of 64 bits is supplied from the gray scale voltage generating circuit 17 to the gray scale voltage selecting circuit 18.
The gray scale voltage selecting circuit 18 comprise first to five hundred twenty eighth gray scale voltage selecting mits 18-1, 18-2, 18-3, - - - , 18-528. Each of the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528, so as to select one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 based on the corresponding one of 6-bits display data PD1, PD2, - - - PD528, whereby the selected one gray scale voltage is supplied to the output circuit 19. For example, the first gray scale voltage selecting unit 18-1 receives the 6-bits display data PD1 to select one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 based on the 6-bits display data PD1, whereby the selected one gray scale voltage is supplied to the output circuit 19.
The first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 have the same circuit configuration, for which reason the following description will focus only on the first gray scale voltage selecting unit 18-1. The output circuit 19 comprises first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - , 19-528 which are connected to the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 respectively. The first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - , 19-528 have the same circuit configuration, for which reason the following description will focus only on the first output unit 19-1.
FIG. 6 is a circuit diagram illustrative of the first gray scale voltage selecting unit included in the gray scale voltage selecting circuit and a first output unit included in the output circuit of FIG. 3. The first gray scale voltage selecting unit 18-1 comprises a single multiplexer 26, first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64, and first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64. Each of-the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 comprises a pair of p-channel MOS field effect transistor 29a and an n-channel MOS field effect transistor 29b.
A gate of the p-channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD1 from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD1 through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26.
The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. For example, the first transfer gate 27-1 receives the first gray scale voltage V1. The single multiplexer 26 receives the 6-bits display data PD1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first output unit 19-1 is connected to the first gray scale voltage selecting unit 18-1. The first output unit 19-1 comprises a first amplifier 30-1, and a first switch 31-1. The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Each of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch control signal SWA from the control circuit 15.
If the first switch 31-1 of the first output unit 19-1 turns ON based on the switch control signal SWA from the control circuit 15, then the amplified data red, green or blue signal S 1 is outputted from the first output unit 19-1. As shown in FIG. 3, the output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
FIG. 7 is a timing chart illustrative of operations of the control circuit, the gray scale power supply 3, the common power supply 4 and the data electrode driver circuit 5 in FIG. 1. The control circuit 2 supplies the data electrode driver circuit 5 with the strobe signal STB, the clock signal CLK, the horizontal start pulse signal STH delayed by a few clock pulses of the clock signal CLK from the strobe signal STB, and the polarity signal POL. The shift register 12 in the data electrode driver circuit 5 shifts the horizontal start pulse signal STH and outputs the sampling pulse signals SP1-SP176 of 176 bits in synchronizing with the clock signal CLK.
The control circuit 2 also converts the red data DR, green data DG, and blue data DB, into the 18-bits display data D00-D05, D 10-D 15 and D20-D25 which are then supplied to the data electrode driver circuit 5. The data buffer 13 in the data electrode driver circuit 5 receives the 18-bits display data D00-D05, D10-D15 and D20-D25 from the control circuit 2 and holds the 18-bits display data D00-D05, D10-D15 and D20-D25 for a time period corresponding a single pulse width of the clock signal CLK in synchronizing with the clock signal CLK, before the data buffer 13 supplies the data register 14 with the 18-bits display data D′00-D′05, D′10-D′I15 and D′20-D′25.
The data register 14 in the data electrode driver circuit 5 accepts serious inputs of the 18-bits display data D′00-D′05, D′10-D′15 and D′20-D′25 as the 6-bits display data PD1, PD2, - - - PD528 in synchronizing with the sampling pulse signals SP1- SP 176. The data latch 16 accepts simultaneous inputs of the 6-bits display data PD1, PD2, - - - PD528 in synchronizing with a rising edge of the strobe signal STB and latches the 6-bits display data PD1, PD2, - - - PD528 for a single horizontal time period.
The gray scale power supply 3 shown in FIG. 2 receives the polarity signal POL If the polarity signal POL is high level "H", then the switches 8a and 9a turn ON as well as the switches 8b and 9b turn OFF, whereby the first side of the first resistance 7-1 is applied with the power voltage VDD whilst the second side of the tenth resistance 7-10 is applied with the ground voltage GND, so that the series connection of the first to tenth resistances 7-1, 7-2, 7-3, - - - 7-10 is biased between the power voltage VDD and the ground voltage GND. As a result, positive-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD>V1>V2>V3>V4>V5>V6>V7>V8>V9>GND. The positive-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth positive-polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the gray scale voltage generating circuit 17 in the data electrode driver circuit 5, provided that the VI1>VI2>VI3>VI4 >VI5>VI6>VI7>VI8>VI9.
The gray scale voltage generating circuit 17 generates first to sixty fourth positive-polarity gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth positive-polarity gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9, wherein VI>V2>V3> - - - >V64. The first to sixty fourth positive polarity gray scale voltages V1, V2, V3, - - - V64 are then supplied to the gray scale voltage selecting circuit 18 in the data electrode driver circuit 5.
Each of-the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528.
A gate of the p-channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26. The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. The single multiplexer 26 receives the 6-bits display data PD1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Each of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch control signal SWA from the control circuit 15, wherein the switch control signal SWA rises at the timing of falling edge of the strobe signal STB. The output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
In FIG. 7, shown is the signal S1 which is the data red signal, in case that the display data PD1 is "000000". In this case, the transfer gate 27-1 in the first gray scale voltage selecting unit 18-1 turns ON based on the display data PD1 "000000", whereby the positive-polarity gray scale voltage V1 is outputted as the data red signal S1. The data red signal S1 is represented by a broken line when the strobe signal "STB" is high level because the switch 31-1 is in the OFF and the signal S1 applied to the data electrode of the color liquid crystal display 1 is in the high impedance state.
The common power supply 4 supplies the ground level-GND to the common electrode of the color liquid crystal display 1 based on the polarity signal POL of high level "H", wherein the common potential of the common electrode of the color liquid crystal display 1 becomes the ground level-GND. The pixel corresponding to the data electrode shows black, assuming that the color liquid crystal display 1 is of the normally white type.
If the polarity signal POL is low level "L", then the switches 8a and 9a turn OFF as well as the switches 8b and 9b turn ON, whereby the first side of the first resistance 7-1 is applied with the ground voltage GND whilst the second side of the tenth resistance 7-10 is applied with the power voltage VDD, so that the series connection of the first to tenth resistances 7-1, 7-2, 7-3, - - - 7-10 is biased between the power voltage VDD and the ground voltage GND. As a result, negative-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are generated at the first to ninth nodes N1, N2, N3, N4, N5, N6, N7, N8 and N9 respectively in accordance with respective ratios of the resistances 7-1, 7-2, 7-3, 7-4, 7-5, 7-6, 7-7, 7-8, 7-9, and 7-10, provided that VDD<V1<V2<V3<V4<V5<V6<V7<V8<V9<GND. The negative-polarity divided voltages V1, V2, V3, V4, V5, V6, V7, V8 and V9 are then amplified by the voltage followers 11-1, 11-2, 11-3, 11-4, 11-5, 11-6, 11-7, 11-8 and 11-9 respectively to generate the first to ninth negative-polarity gray scale voltages VI1, VI2, VI3, VI4, VI5, VI6, VI7, VI8 and VI9 which will subsequently be supplied to the gray scale voltage generating circuit 17 in the data electrode driver circuit 5, provided that VI1<VI2<VI3<VI4<VI5<VI6<VI7<VI8<VI9.
The gray scale voltage generating circuit 17 generates first to sixty fourth negative-polarity gray scale voltages V1, V2, V3, - - - V64 at the first to sixty fourth nodes respectively, wherein the generated first to sixty fourth negative-polarity gray scale voltages V1, V2, V3, - - - V64 depend on the first to ninth gray scale voltages VI1, VI2, VI3, - - - VI9, wherein V1<V2<V3< - - - <V64. The first to sixty fourth negative polarity gray scale voltages V1, V2, V3, - - - V64 are then supplied to the gray scale voltage selecting circuit 18 in the data electrode driver circuit 5.
Each of the first to five hundred twenty eighth gray scale voltage selecting units 18-1, 18-2, 18-3, - - - , 18-528 receives corresponding one of 6-bits display data PD1, PD2, - - - PD528.
A gate of the p-.channel MOS field effect transistor 29a of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives the display data PD from the multiplexer 26. A gate of the n-channel MOS field effect transistor 29b of each of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 receives inverted display data /PD through the corresponding one of the first to sixty fourth inverters 28-1, 28-2, 28-3, - - - 28-64 from the multiplexer 26. The first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 also receive the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 from the gray scale voltage generating circuit 17 respectively. The single multiplexer 26 receives the 6-bits display data PD 1 from the data latch 16 for selecting one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 based on the received 6-bits display data PD1, whereby the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 turns ON, and the selected one of the first to sixty fourth transfer gates 27-1, 27-2, 27-3, - - - 27-64 outputs the corresponding one of the first to sixty fourth gray scale voltages V1, V2, V3, - - - V64 as a data red signal, a data green signal or a data blue signal.
The first amplifier 30-1 receives the data red signal, a data green signal or a data blue signal as the gray scale voltage from the first gray scale voltage selecting unit 18-1 for amplifying the received signal. Each of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 also receives a switch control signal SWA from the control circuit 15. The first to five hundred twenty eighth switches 31-1, 31-2, 31-3, - - - 31-528 of the first to five hundred twenty eighth output units 19-1, 19-2, 19-3, - - - 19-528 receive the switch-control signal SWA from the control circuit 15, wherein the switch control signal SWA rises at the timing of falling edge of the strobe signal STB. The output circuit 19 outputs the first to five hundred twenty eighth data red, green and blue signals S1, S2, S3, - - - S528 which are then supplied to the data electrodes of the color liquid crystal display 1.
In FIG. 7, shown is the signal S1 which is the data red signal, in case that the display data PD1 is "000000". In this case, the transfer gate 27-1 in the first gray scale voltage selecting unit 18-1 turns ON based on the display data PD1 "000000", whereby the positive-polarity gray scale voltage VI is outputted as the data red signal S1. The data red signal S1 is represented by a broken line when the strobe signal "STB" is high level because the switch 31-1 is in the OFF and the signal S1 applied to the data electrode of the color liquid crystal display 1 is in the high impedance state.
The common power supply 4 supplies the power voltage level VDD to the common electrode of the color liquid crystal display 1 based on the polarity signal POL of low level "L", wherein the common potential of the common electrode of the color liquid crystal display 1 becomes the power voltage level VDD. The pixel corresponding to the data electrode shows black, assuming that the color liquid crystal display 1 is of the normally white type.
The above-described driving system is so called to as a line-inversion driving system, wherein the data signals applied to the data electrodes are opposite to each other in polarity with reference to corresponding common potentials Vcom between adjacent two of the data lines, provided that the common potentials Vcom are respectively inverted between ground and power voltage levels for every data lines.
The line-inversion driving system has been utilized for the following two reasons. The first reason is that the applications of the same or uniform polarity voltages to the liquid crystal cells shorten the life-time of the color liquid crystal display. The second reason is that the transmittivity of the liquid crystal cells is almost independent from the polarity of the applied voltage to the liquid crystal display.
The above described line-inversion driving system, however, has the following disadvantages particularly in case of the mobile phones and personal handy-phone systems. In a stand-by mode, the power ON-state is maintained without, however, any operations by the users, and a predetermined stand-by display is displayed in full-colors on the color liquid crystal display screen, even the users are unlikely to view the display screen. The driver circuit of the color liquid crystal display is driven in the same manner as in the normal mode. This means that, in the standby mode, the driver circuit consumes the same power as in the normal mode. It is desirable to suppress the power consumption by the driver circuit in the stand-by mode as many as possible.
FIG. 8 is a view illustrative of a display screen of the mobile phone or the personal handyphone system. A display screen 1 of the mobile phone or the personal handyphone system includes a top display region 32, a center display region 33 and a bottom display region 34. The top display region 32 displays a battery mark 32a and an antenna mark 32b. The battery mark 32a indicates a charge-level of a battery accommodated in the mobile phone or the personal handy-phone system. The antenna mark 32b indicates whether the position of the mobile phone or the personal handy-phone system is in a service area of a wireless phone service on a mobile communication network.
The center display region 33 displays images of the contents attached to e-mails and provided from World Wide Web servers. The bottom display region 34 displays month-and-day information 34a and clock-time information 34b. The center display region 33 shows the full color display. The top and bottom display regions 32 and 34 show monochrome or 8-colors displays.
For performing the monochrome or 8-colors display on the top and bottom display regions 32 and 34, the conventional driver circuit of the color liquid crystal display 1 operates the data electrode driver circuit 5 in the same manners as performing the full-color display on the center display region 33. This causes unnecessary power consumption by the conventional driver circuit. It is thus desirable to suppress the power consumption for displaying the top and bottom display regions 32 and 34.
Another driving system, for example, the frame inversion system also has the same disadvantages as described above. In the frame inversion system, the data signals applied to the data electives are opposite to each other in polarity with reference to corresponding common potentials Vcom between adjacent two frames, provided that the common potentials Vcom are respectively inverted between ground and power voltage levels for every frames.
The above described disadvantages of the line inversion driving system and the frame-inversion driving system are also common to other potable or mobile electric devices than the mobile phones and the personal handy-phone systems, for example, various electronic devices such as note-type computers, palm-type computers, pocket-type computers, mobile terminals such as personal digital assistants.
In the above circumstances, the developments of a novel method of driving a liquid crystal display and of a drive circuit for driving the liquid crystal display as well as of an electronic device with the driver circuit are desirable.

Method of driving a color liquid crystal display and driver circuit for driving the display as well as portable electronic device with the driver circuit


The object of the present invention is to increase PHEX activity to improve the osteogenic process in a mammal where this process has been diminished due to pathology or a condition that require osteogenesis. Osteocalcin is an endogenous inhibitor of the PHEX activity. Therefore, the identification of a substance capable of potentiating PHEX activity by preventing the inhibitory action of endogenous inhibitors will improve osteogenesis. Since PHEX is generally associated with the growth plane of bone or teeth and the absence of osteocalcin is associated with increased bone mass, potentiation of PHEX activity can promote bone growth. Increased PHEX activity can also be obtained by administration of the enzyme itself.

The bone. The solid matrix of the bone is made of an organic phase, collagen, and of an inorganic phase, composed of calcium and phosphate (hydroxyapatite). Bones are continuously remodeling themselves, a process of combined dissolution (resorbtion) and re-construction of the bone matrix. The bone relies on two cell types for remodeling process: osteoclasts, which are responsible for resorbtion, and osteoblasts, which promote for bone formation. In normal bones, both processes are strictly coordinated to maintain bone mass within defined limits. More specifically, at a specific site, resorbtion occurs first and over a shorter period than bone formation. At the end of the formation stage most osteoblasts will disappear through the apoptotic process. About 10% will be enclosed in the bone and remain there to form osteocytes. It is generally believed that the osteocytes participate in some form of mechanical stress sensing mechanism. Osteoporosis occurs when the resorbtion process is initiated more often than formation is completed, leading progressively to more fragile bones (Harisson 14th Ed). PHEX. The PHEX gene (formerly PEX; a Phosphate regulating gene with homologies to Endopeptidases on the X chromosome) was identified by a positional cloning approach as the candidate gene for human X-linked hypophosphatemia (XLH) (1). XLH is a Mendelian disorder of phosphate homeostasis characterized by growth retardation, rachitic and osteomalacic bone disease, hypophosphatemia, and renal defects in phosphate re-absorption and vitamin D metabolism (2). Several groups have cloned and sequenced the human and mouse PHEX/Phex cDNAs (3-7) (PHEX/Phex refers to the human and mouse genes, respectively). Amino acid sequence comparisons have demonstrated homologies between PHEX/Phex protein and members of the M13 endopeptidase family, as previously observed in the partial sequence of the candidate gene (1). The M13 endopeptidases are zinc-containing type 11 integral membrane glycoproteins with a relatively short cytoplasmic amino-terminal region, a single transmembrane domain, and a long extracytoplasmic domain, which contains the active site of the enzyme (8). In addition to PHEX, this family includes neprilysin (NEP, neutral endopeptidase 24.11), a widely distributed peptidase involved in the degradation of several bioactive peptides (9), the endothelin-converting enzymes 1 and 2 (ECE-1 and ECE-2) responsible for the processing of inactive big-endothelins into active endothelins (10), the Kell blood group protein, a protein of the erythrocyte membrane with unknown function (11), and ECEL/DINE (12,13) and SEP/NL1 (14,15), two recently reported peptidases with homology to the neprilysin family.
The precise physiological role of PHEX is unknown and the mechanisms whereby loss of PHEX function causes renal phosphate wasting, abnormal regulation of vitamin D metabolism and impaired bone mineralization are not completely understood. Homology of PHEX to members of the M13 family of zinc metallopeptidases suggests a role in regulating the activity of extra-cellular bioactive peptide(s) that act in an autocrine, paracrine or endocrine fashion. In support of this hypothesis, Lajeunesse et al. (16) and Nesbitt et al. (17) have reported the existence of a renal phosphate transport inhibitory factor in the culture medium of osteoblasts isolated from the Hyp mouse, an animal model for human XLH (18). The role of PHEX would appear be to inactivate this circulating factor. However, the molecular identity of this factor (phosphatonin) has yet to be established.
PHEX and mineralization. In situ hybridization performed on sections of embryos and newborn mice showed the presence of Phex mRNA in osteoblasts and odontoblasts (32). Phex gene expression was detectable on day 15 of embryonic development, which coincides with the beginning of intracellular matrix deposition in bones. Moreover, Northern analysis of total RNA from calvariae and teeth of 3-day-old and adult mice showed that the abundance of the Phex transcript is decreased in adult bones and in non growing teeth but maintained in growing incisors throughout life. This result was confirmed when the presence of the Phex protein in new born and adult bones was investigated by Western blotting using a monoclonal antibody raised against human PHEX. Immunohistochemical studies on a 2 month-old mouse showed exclusive labeling of mature osteoblasts and osteocytes in bones and of odontoblasts in teeth (27). Taken together these results suggest that PEX/Phex plays an important role in the development and maintenance of mineralization in these tissues.
Studies performed with the Hyp mouse, an animal model harboring a large deletion in the 3′ region of the Phex gene (5) and exhibiting the same phenotypic features that characterize patients with XLH (18), also suggest that PHEX is involved, in an unknown way, in the mineralization process. Hyp mice exhibit enlarged osteoid area in bones (27, 33) which was shown not to be due to abnormal matrix deposition (34,35) but to impaired mineralization (33).
Osteocalcin. Osteocalcin is the most abundant of the non-collagenous bone proteins and is expressed only in osteoblasts. The mature peptide is 49 amino acids long with 3 Gla residues and one difulfide bond. A vitamin K-dependent gamma-carboxylase is responsible for the transformation of certain Glu into Gla residues. These Gla residues are well known for their affinity toward calcium ions and hydroxyapatite crystals. About 80% of bone mass is made-up of hydroxyapatite, a mineral composed of calcium and phosphate. An increase in osteocalcin mRNA is associated with the mineralization stage and the transformation of osteoblasts into osteocytes (39).
In vitro, osteocalcin inhibits growth of mineral crystals (36, 37) whereas in vivo, gene targeting aimed at the disruption of both mouse osteocalcin genes resulted in the generation of osteocalcin-deficient animals (38). These osteocalcin-knockout mutant mice display a phenotype "opposed to osteoporosis" which is also characterized by an increase in the rate of bone formation, increased bone mass, as well as an overall improved functional quality of the bone.

This patent is subject to a terminal disclaimer.

Method and compositions for promoting osteogenesis


The present invention relates to a polypeptide comprising the amino acid sequence of SEQ ID NO:1 or a sequence of SEQ ID NO:1 where in, one or more amino acids are deleted, replaced or added, and the polypeptide having polyester synthase activity. A polyester synthase gene comprising DNA coding for the above polypeptide; a recombinant vector comprising the gene; and a transformant transformed with the recombinant vector is also provided.

Polyesters (e.g. poly-3-hydroxyalkanoic acid) biosynthesized by microorganisms are biodegradable plastics with thermoplasticity ranging widely from rigid matter to viscoelastic rubber.
Poly-3-hydroxybutanoic acid (P(3HB)) is a typical polyester consisting of C4 monomer units, but it is a rigid and brittle polymeric material, so its application is limited. Accordingly, various polyesters such as P(3HB-co-3HV) having (P(3HB)) copolymerized with a C5 monomer unit (3HV) by adding propionic acid etc. to the medium have been prepared and examined to alter the physical properties of the polyester. On the other hand, polyesters consisting of at least C6 monomer units are soft polymeric materials having plasticity.
Polyester-synthesizing microorganisms are roughly divided into 2 groups, that is, those synthesizing polyesters with C3-5 monomer units and those synthesizing polyesters with C6-14 monomer units. The former microorganisms possess a polyester synthase using C3-5 monomer units as the substrate, while the latter microorganisms possess a polyester synthase using C6-14 monomer units as the substrate. Therefore, polyesters with different properties are synthesized by the respective microorganisms.
However, the respective polyesters from such known microorganisms are different in substrate specificity, so with one kind of enzyme given, polyesters (copolymers) having various monomer unit compositions adapted to the object of use are difficult to synthesize.

Polyester synthase and a gene coding for the same

Japan Science and Technology Corporation

The Institute of Physical and Chemical Research


In this invention is described a circuit and method for auto programming of a flash memory cell of an EEPROM. A step split gate is used that has low voltage and low current program conditions. This allows a load device to be connected to each bit line, and sets up a voltage divider between the cell being programmed and the load device. The load device limits the programming current and provides programming data to the cell being programmed. The load device is shut off when the bit line voltage is reduced below a predetermined reference, ending programming of the flash memory cell. The source to drain voltage increases as the memory cell is programmed as a result of the voltage divider between the load device and the cell being programmed thus maintaining pinch off. This produces more energy to program the flash cell and with proper design allows the programming efficiency to be relatively constant over the time that elections are injected onto the floating gate of the flash memory cell. This voltage divider effect also provides for more programming cycles because as charge is built up in the oxide in the vicinity of the floating gate the source to drain voltage is increased automatically providing more energy to program the cell.

1. Field of Invention
This invention refers to flash memory and in particular to the automatic programing of flash memory cells.
2. Description of Related Art
In an electrically erasable programmable read only memories (EEPROM), there exists a floating gate in each memory cell which is charged by hot elections injected onto the floating gate to store data into the memory cell. These floating gales are erased by a Fowler-Nordheim tunneling technique where a second gate called a control gate is grounded or negative biased and the drain is set at a high voltage. The injection of charge on a floating gate takes a period of time to accumulate the necessary amount of charge to establish the proper threshold voltage. A mechanism is therefore needed to determine when programming of floating gate device has been accomplished.
In U.S. Pat. No. 5,712,815 (Bill et al.) and U.S. Pat. No. 5,724,284 (Bill et al.) a method of programming a flash EEPROM uses reference cells to monitor and disable programming. Multiple threshold voltages are used in the memory cell to allow one erased state and three programmable states. The multiple threshold states are established using a reference cell array. Two transistors are placed in the bit line path to act as a switch and a current source. Bit line voltage is monitored by a reference voltage. The conventional memory cell requires high voltages and high programming currents resulting in a low bit line voltage and making it difficult to obtain adequate sensing margins for multilevel data.
Referring to U.S. Pat. No. 5,684,741 (Talreja), a current mirror is used to monitor current through an EEPROM memory cell that provides a signal to a differential amplifier. The device current during program is compared to a programmed cell current to determined when to stop programming of the memory cell. In U.S. Pat. No. 5,532,964 (Cernea et al.) a method and circuit using a novel sense amplifier is used to determine when programming of an EEPROM cell has been accomplished. The sense amplifier and associated programming circuitry are shared with a plurality of bit lines through a bit line selection circuit. In both U.S. Pat. No. 5,684,741 and U.S. Pat. No. 5,532,964 the sensing circuits are not compact enough to allow future implementation of wide page mode programming of every bit line in an array.
The programming of EEPROM cells is a relatively slow process because charge is injected onto a floating gate by means of the channel hot electron process. As charge is built up on the floating gate, the threshold voltage of the transistor with the floating gate rises and slows the process of inducing charge onto the floating gate. Without a method to detect when programming of an EEPROM cell has been accomplished, the process is even longer because a "program and then read method" must be used to determine if data has been programmed to the correct threshold voltage. There is also the potential of over programming the cell and reducing the number of times a particular cell can be reprogrammed because of charge buildup. A means by which the process of writing data to an EEPROM cell can be done quickly and efficiently is needed that automatically terminates programming when a cell is programmed, providing consistent programming with longevity of repeated erasure and programming.

Fast, low current program with auto-program for flash memory

Halo LSI Design & Device Technology, Inc.


A method includes determining a relationship between indirect thermal data for a processor and a measured temperature associated with the processor, during a calibration process, obtaining the indirect thermal data for the processor during actual operation of the processor, and determining an actual significant temperature associated with the processor during the actual operation using the indirect thermal data for the processor during actual operation of the processor and the relationship.

This disclosure relates to the thermodynamic arts, and more particularly, to techniques for estimating processor junction temperatures and optionally controlling processor operation based on the same.
Modern integrated circuit chips, and servers or other computing devices using them, pose significant thermal control challenges. Liquid cooling, air cooling, and hybrid liquid-air cooling solutions have been employed.

Calibrating thermal behavior of electronics

INTERNATIONAL BUSINESS MACHINES CORPORATION


An expansion ring for expanding the size of an oven is disclosed. The expansion ring has a plurality of expansion ring segments which are connected together by one or more clips. The expansion ring segments have end portions which, when two segments are placed in end-to-end relation, form an engagement portion having first and second stops. The clip has a channel which engages the engagement portion so as to hold the expansion ring segments together and a finger projecting into the channel. According to this arrangement, the clip is slidable between a first position where the finger engages the first stop and a second position where the finger engages the second stop. In the first position, the expansion ring segments are locked together. In the second position, the segments may be separated, but the clip remains attached to one of the segments so that it will not be lost. An oven incorporating the expansion rings and clips of the present invention is also disclosed.

The present invention relates generally to a multi-piece expansion ring used to expand the size of a portable oven, and to a unique clip used to hold the pieces of the expansion ring together. More specifically, the present invention relates to such an expansion ring/clip combination which securely holds the expansion ring segments together, but allows for easy disassembly of the expansion ring for cleaning and storage.
The concept of using expansion rings to increase the cooking capacity of a portable oven is disclosed in U.S. application Ser. No. 325,157 filed Mar. 17, 1989 and assigned to the same assignee as the present invention. The present invention it is particularly useful with the oven disclosed in Ser. No. 325,157. To the extent that the disclosure of that application is necessary to an understanding of the present invention, it is incorporated by reference herein.
It is desirable for a number of reasons to form an expansion ring out of two or more segments. Such a multi-segment design is easier to manufacture. It is also more compact for shipping and storage purposes, and is easier for the user to clean.
When such a multi-piece extension ring is used, some means must be provided to connect the segments together. One such means which is known is the clip shown in FIG. 1. This clip, which is made of aluminum, has a generally planar front face 2 and a rounded back face 4. A slot 6 is formed along the front face of the clip. The expansion ring segments (not shown) have projections extending along the free ends thereof. The projections are shaped so that when two expansion ring segments are placed together, the projections of the two segments together form a shape generally the same as that of slot 6. Thus, the clip can be slid over the two projections so as to hold the segments together.
The clip of FIG. 1 suffers from numerous disadvantages. Several disadvantages result from the use of aluminum for the clip. One, aluminum has high thermal conductivity. Thus, when the oven is heated up, the clips tend to heat up quickly and retain that heat. These hot clips are potentially dangerous to the user, who can be burned.
Two, the expansion ring segments are made of plastic, which has a different thermal expansion rate than the aluminum of the clips. Thus, when the oven is used, the plastic expansion ring segments expand faster than the clips. This causes great stress to be placed on the projections, which can crack under the pressure.
Another related problem is that the only thing holding the clip in place is friction. If the clip is designed to fit tightly on the projections so as to remain securely in place, then the cracking problem referred to in the previous paragraph is particularly troublesome. One the other hand, if the clip is designed to only loosely fit over the projections, the clip is not held securely, and has a tendency to fall off.
One solution which has been suggested is shown in FIG. 2. The only difference between the clip of FIG. 2 and that of FIG. 1 is the use of two small bumps 8 located within space 6. The bumps are designed to cooperate with two small detents located on the projections of the expansion ring segments.
However, this clip, which is also made of aluminum, still suffers from disadvantages. Importantly, when the clip is slid on and off numerous times, the metal bumps on the clip eventually form a groove in the softer plastic of the expansion ring segments. This loosens the fit of the clip on the projections, so that eventually the bumps and detents would cease to served any function.
Finally, the aluminum clips shown in FIGS. 1 and 2 are very labor intensive, and thus expensive, to produce.

Expansion ring and clip for use with an expandable oven


Liquid microbial starter culture that retains its initial metabolic activity during storage for extended periods of time. Such liquid starter cultures are useful in the manufacturing of food and feed products. Starter cultures of the invention include culture of lactic acid bacteria, e.g. Lactococcus species.

Microorganisms are involved in the manufacture of food and feed products including most dairy products. Thus, bacterial cultures, in particular cultures of bacteria that are generally classified as lactic acid bacteria are essential in the making of all fermented milk products, cheese and butter. Cultures of such bacteria are referred to as starter cultures and they impart specific features to various dairy products by performing a number of functions.
Commercial dairy starter cultures are generally composed of lactic acid and citric acid-fermenting lactic acid bacteria. In the present context, the expression "lactic acid bacteria" designates a group of Gram positive, catalase negative, non-motile, microaerophilic or anaerobic bacteria which ferment sugar with the production of acids including lactic acid as the predominantly produced acid, acetic acid, formic acid and propionic acid. The industrially most useful lactic acid bacteria are found among Lactococcus species, Streptococcus species, Enterococcus species, Lactobacillus species, Leuconostoc species and Pediococcus species.
Commonly used dairy starter culture strains of lactic acid bacteria are generally divided into mesophilic organisms having optimum growth temperatures at about 30° C. and thermophilic organisms having optimum growth temperatures in the range of about 40 to about 45° C. Typical organisms belonging to the mesophilic group include Lactococcus lactis subsp. lactis, Lactococcus lactis subsp. cremoris, Leuconostoc mesenteroides subsp. cremoris, Pediococcus pentosaceus, Lactococcus lactis subsp. lactis biovar. diacetylactis and Lactobacillus casei subsp. casei. Thermophilic lactic acid bacterial species include as examples Streptococcus thermophilus, Enterococcus faecium, Lactobacillus lactis, Lactobacillus helveticus, Lactobacillus delbrueckii subsp. bulgaricus and Lactobacillus acidophilus.
Also the strict anaerobic bacteria belonging to the genus Bifidobacterium including Bifidobacterium bifidum and Bifidobacterium longum are commonly used as dairy starter cultures and are generally included in the group of lactic acid bacteria. Additionally, species of Propionibacterium are used as dairy starter cultures, in particular in the manufacture of cheese.
Additionally, organisms belonging to the Brevibacterium genus are commonly used as food starter cultures.
Another group of microbial starter cultures is fungal cultures, including yeast cultures and cultures of filamentous fungi, which are particularly used in the manufacture of certain types of cheese and beverage. Examples of currently used cultures of fungi include Penicillium roqueforti, Penicillium candidum, Geotrichum candidum, Torula kefir, Saccharomyces kefir and Saccharomyces cerevisiae.
Presently, commercial starter cultures are commonly distributed as frozen concentrates. Under these conditions, the viability of the cultures is preserved for extended periods of time and the cultures can be inoculated directly into milk without intermediate transfer. Such cultures are generally referred to as direct vat set (DVS)-cultures. Another presentation of commercial DVS-starter cultures is as freeze-dried or lyophilised cultures in the form of a powder. In this form, the starter can be shipped without refrigeration, but storage below freezing temperature is recommended.
Although commercial starters thus are available as cultures, which can be added directly to milk without any intermediate transfer or propagation, it is not uncommon that dairies produce in-house bulk starters at regular intervals depending on the requirement. A "bulk starter" is defined herein as a starter culture propagated at the dairy plant for inoculation into milk. Such bulk starters are generally made by inoculating heat treated milk with a volume of a previous bulk starter or with a freeze-dried or frozen starter culture preparation, followed by incubating the thus inoculated milk under conditions permitting the starter culture strain(s) to propagate for a sufficient period of time to provide a desired cell number. The incubation period is typically in the range of 4 to 24 hours.
However, the preparation of such bulk starter cultures is labour intensive and it occupies much space and equipment, and there is a considerable risk of contamination with spoilage bacteria and/or phages during the step of propagation.
The use of commercial liquid starter cultures in the food and feed manufacturing industry including the dairy industry has been suggested as a useful alternative to the use of commercial frozen and freeze-dried starter cultures. The advantages for the industry by having such liquid starter cultures at its disposal would be several. Thus, it would be highly convenient and much less labour consuming to handle such starter cultures at food and feed manufacturing plants as compared to the use of the conventional frozen or freeze-dried cultures. Thus, when using liquid starter cultures, the inoculation of the material to be inoculated can be made directly e.g. by connecting the container with the liquid culture directly to the process line, thus avoiding the tedious work connected with opening several packagings of culture prior to inoculation. Additionally, it can be avoided to open the process line, as it is required when using frozen or freeze-dried cultures, which reduces the risk of contamination.
However, the use of commercial liquid starter cultures has so far not been feasible or possible, as such cultures, even if the cells of the cultures keep their viability, rapidly loose their metabolic activity such as e.g. their acid-producing (acidification) activity when kept stored even for shorter periods of time. To be commercially useful, liquid starter cultures should preferably retain their metabolic activity for at least 1 week and more, preferably for at least 2-3 weeks. Up till now it has not been possible to provide commercial liquid starter cultures having such a high stability.
It is therefore an important objective of the present invention to provide liquid starter cultures which show a high degree of storage stability in respect of retaining the metabolic activity when kept under cool storage conditions for extended periods of time.

Liquid starter cultures having an improved storage stability and use thereof


A paging apparatus and method in a mobile communication system providing an MBMS (Multimedia Broadcast Multicast Service). In the mobile communication system, to page a UE for a first service through a primary carrier during a second service in progress through a secondary carrier, a PICH (Paging Indication Channel) transmitter in a Node B transmits paging indication information to the UE through the primary carrier by oscillating the primary carrier as a transmission frequency. A PCH (Paging Channel) transmitter transmits paging information to the UE through the primary carrier or the secondary carrier by oscillating the primary carrier or the secondary carrier as the transmission frequency under a predetermined control. A PBMSCH (Physical Broadcast Multicast Shared Channel) transmitter transmits data of the second service through the secondary carrier by oscillating the secondary carrier as the transmission frequency. A controller controls the primary carrier or the secondary carrier to be oscillated as the transmission frequency of the PCH transmitter if the paging indication information indicates paging.

1. Field of the Invention
The present invention relates generally to a mobile communication system, and in particular, to a paging apparatus and method in a mobile communication system providing an MBMS (Multimedia Broadcast Multicast Service).
2. Description of the Related Art
CDMA (Code Division Multiple Access) generally uses a plurality of physical channels. The physical channels are common channels and dedicated channels. The common channels are shared among a plurality of UEs (User Equipments) within a cell area of a Node B, and the dedicated channels are assigned to particular UEs by the Node B. The common channels include a CPICH (Common Pilot Channel), a P-CCPCH (Primary Common Control Physical Channel), an S-CCPCH (Secondary Common Control Physical Channel), and a PICH (Paging Indicator Channel). The dedicated channels include a DPCH (Dedicated Physical channel).
In CDMA, broadcasting channels broadcast information to UEs. There are different broadcasting channels in a CDMA mobile communication system, for example, in a Release 99 mobile communication system. They are a BCH (Broadcasting Channel) and an FACH (Forward Access Channel). The BCH broadcasts SI (System Information) required for cell access to UEs, and the FACH sends control information about assignment of a dedicated channel and a broadcast message to a particular UE in addition to the function of the BCH. Since the main use of the broadcasting channels is to deliver common control information to UEs and control information to a particular UE, transmission of user data on the broadcasting channels is limited.
Recently, the development of communication technology has brought with it multicast multimedia communication that enables transmission of a large amount of data, such as packet data and circuit data, in addition to voice service in CDMA mobile communication systems. Thus many multicast multimedia applications have been proposed. Particularly, the MBMS has emerged as a future generation mobile communication service. The MBMS is a service that provides audio data and video data contemporaneously. Since the MBMS requires a large amount of transmission resources and is likely to cause concurrent provision of different services within a Node B on a large scale, it is provided on broadcasting channels. BMC (Broadcast Multicast Control), a single channel sharing technique, is free of constraints of temporal delay since it is applied to low rate transmission such as text broadcasting. As compared to the BMC, the MBMS is provided at a very high data rate and is sensitive to temporal delay. Therefore, the MBMS must be serviced in a different way from the BMC.
When transmitting a signal on a radio channel, the signal is modulated with a carrier having a higher frequency than the signal itself prior to transmission in order to improve transmission characteristics against external noise in a typical mobile communication system. Hence, the conventional CDMA mobile communication system sends physical channels available to a Node B with one carrier. In other words, both common channels and dedicated channels are transmitted with one carrier. However, resources are not sufficient to provide existing services in the conventional CDMA mobile communication system. Accordingly, it is obvious that the provision of the MBMS will lead to a further lack of resources.
In this context, studies have been conducted on a solution to the lack of resources to support the future generation mobile communication system requiring a large amount of resources.

Paging apparatus and method in a mobile communication system providing multimedia broadcast multicast service


A system and method for managing battery slump in a battery-powered communications device including: an input configured for receiving battery voltage level information; an output configured for sending a signal for terminating a transmission; and a controller connected to the input and the output and configured to receive the battery voltage level information from the input; monitor the battery voltage level information; and send a signal via the output to terminate a transmission if the battery voltage level information crosses a predetermined threshold during the transmission. In particular, the system and method may further include an input connected to the controller and configured for receiving a signal indicating when a transmission is beginning or occurring and the controller is further configured to receive and monitor the battery voltage level information only when the transmission is occurring.

Mobile communication devices such as mobile phones, personal data assistants, and the like are generally powered by internal means, such as an internal battery pack. The internal battery pack is an assembly of one or more batteries/cells that typically have a predetermined capacity. Typically, battery packs can have different termination voltages (associated with full charge) such as 4.2 V and 4.4 V, for example, as well as different charging/discharging characteristics.
As is well understood, the battery pack needs to have a sufficient capacity to operate the mobile communication device under a variety of conditions, including handling the comparatively greater power requirements encountered when transmitting a signal wirelessly. In transmitting a wireless signal, a mobile communication device generates an internal data signal that is transmitted using a radio transmitter. The data signal is typically a comparatively low frequency signal that is generally referred to as a baseband signal. The baseband signal is mixed with a carrier signal having a substantially higher frequency to produce a high (e.g. radio) frequency transmission signal. The transmission signal is amplified in one or more stages of an output power amplification block and then applied to a radio antenna to be radiated. The amplified transmission signal needs to be sufficiently powered so that it is received with appropriate strength and little or no data loss at a remote base station or another communication device.
The amplification stages of the output power amplification block may include a pre-amplification stage and a power amplification stage for producing the amplified transmission signal. The amplification level of either the pre-amplification stage or the power amplification stage may generally be adjusted depending on the power required for a particular type of signal. The power amplification stage is powered so that it can produce an amplified transmission signal that has an appropriate instantaneous maximum power for the required transmission.
In wireless communications, there are many cases where the amplified transmission signal is required to have a large dynamic range of power levels. This range is needed in order to accommodate a signal that has a high peak-to-average power ratio (PAPR) or to accommodate different types of signals that may have different desired power levels and different PAPRs. In these cases, the power amplification stage must be capable of generating an amplified transmission signal such that the highest instantaneous power level desired for any data type or data rate of the baseband data that is present in the amplified transmission signal is always accommodated without saturation or undue distortion. In conventional power management schemes, the maximum instantaneous power increases with available power supply voltage, such that insufficient supply voltage may induce amplifier saturation and excessive distortion. As such, the power amplification stage is typically provided with a power supply voltage that is sufficient for accommodating a specified maximum instantaneous power level. For lower power levels, the excess power supplied to the power amplifier is unnecessary and is generally dissipated as heat or otherwise lost.
In wireless devices that are using a battery, the supply current requirements of the amplifier can constitute a heavy drain on the battery. For example, a GSM transmit pulse has a very high current drain on the battery for a time of ˜500 usec and the current can reach ˜2 Amps. Such a pulse causes the voltage appearing at the power amplifier stage (PA) to "slump" because of battery internal source resistance (ISR) and other printed circuit board (PCB) trace/component resistances.
This battery voltage slump has led to standards that require the PA to operate with a minimum voltage requirement. These standards include, for example, FCC regulations as well as GSM standards with regard to radiated emissions. However, it is difficult to accurately choose/set the minimum voltage level of the PA, because battery ISR can have a wide range depending on the age of the battery, the temperature at which the battery is operating and the like. For example, the worst case slump for cold temperatures and an aged battery can be 2-3 times the slump of a newer battery at indoor temperatures. Thus, in order to design a mobile device that is compliant with standards, the worst case slump must be considered and a lower PA operating voltage must generally be assumed in order to meet the "worst case scenario". The use of a lower PA operating voltage sacrifices efficiency and available power because in conditions where battery slump is better than the worst case, there will be excess power that is dissipated. This results in shorter battery life and lower production yields.
As such, there is a need in the art for an improved method of monitoring and managing battery slump voltage in mobile devices.
These and other features of the exemplary embodiments are described in more detail below.

System and method for managing battery slump during wireless communications using signal triggered voltage monitoring


The present invention is a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.

1. Field of the Present Invention
The present invention relates to a technique for producing planar silicon on insulator MOS transistors, where the channel regions are created in an underlying single crystal silicon wafer, and where the source-drain extension regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.
2. Description of the Prior Art
The primary advantage of using silicon on insulator (SOI) substrates, rather than using bulk silicon, for forming MOS transistors has long been recognized as being that of reduced stray capacitance. This allows, of course, higher operating frequencies to be obtained. SOI has other advantages such as better packing density, borderless contacts, latch-up freedom, and radiation hardness.
A thin film of crystalline silicon epitaxially deposited on a polished single crystal aluminum oxide substrate (SOS) was the first composite material to be used for SOI. However, since the crystal properties of aluminum oxide do not perfectly match those of silicon there has always been the problem of reduced yield due to defects in the silicon film.
In recent years SOI circuits have been made by forming a thin film of crystalline silicon on silicon dioxide, where the oxide has been grown on a silicon support wafer. This has enabled the production of silicon films with much lower defect densities, because the support wafer physical properties, such as thermal expansion coefficient, match those of the silicon film. Currently SOI refers to silicon on oxide, which will be our convention.
There are a few different methods for producing SOI substrates, such as wafer bonding or high current oxygen implantation. All of these methods are rather difficult because the silicon film has to be single crystal, and for best performance of the finished circuit, the film should be very thin (less than approximately 1000 Angstroms).
Another difficulty with current SOI is that the MOS transistor body connections are typically left floating for efficiency of chip layout. This can sometimes cause problems. For example, excess charge can remain in a transistor floating body region when attempting to turn a transistor off, which can slow down circuit operation. This problem can be solved by implanting just the right amount of recombination centers in the film; however, this is difficult to control, because too many centers will degrade the mobility of the film.
It is therefore the object of the present invention to provide a simplified method for producing SOI substrates; and to provide a technique for electrically connecting MOS body regions to well defined voltages without incurring any layout area penalty; and to maintain the high density layout capability of current SOI.

Damascene pattering of SOI MOS transistors


This disclosure relates to adaptively reducing the peak power of harmonic distortions as a function of the operating conditions for transmission communications. Specifically, the bias of the amplifier is adaptively increased to reduce harmonic distortions when a small fraction of the resource blocks are active.

LTE (Long Term Evolution) modulation and WCDMA (Wideband Code Division Multiple Access) are distinct transmission standards that must both adhere to the same specifications for harmonic distortions, and both are measured in the same bandwidth and have the same limits. In LTE modulation, resource blocks (RBs) may be assigned (activated) to increase the active transmission bandwidth. For example, an LTE channel structure is provided in 3GPP (3rd Generation Partnership Project) standard TS 36.521-1 V2.0.0 (2008-12).
When few resource blocks (less than 22 in one embodiment) are activated in an LTE modulation, then the peak power of the harmonic distortion is undesirably high. This condition may be described as a low activity condition, which has a relatively small number of active resource blocks. This condition may also be described as a low data rate condition.
The conventional solution in industry is to place lossy filters in the transmission path to filter out the undesired harmonic distortions, which occur during low activity conditions. Unfortunately, this conventional solution increases the circuit footprint, increases the circuit cost, and increases the power consumption (thus decreasing the maximum talk time for any battery dependent device). Further, the lossy filters constantly consume power, even though they are really only needed during low activity conditions.
Harmonic distortions may also interfere with GPS (global positioning systems), and prevent GPS from functioning properly.

Adaptive biasing to meet stringent harmonic requirements


An antenna array comprises a substrate; a plurality of projecting, tapering structures disposed in an array and attached to a first major surface of said substrate, the plurality of projecting, tapering structures defining a plurality of waveguides therebetween; and a plurality of box-shaped structures disposed in an array and attached to a second major surface of the substrate, the plurality of box-shaped structures defining a plurality of waveguides therebetween, the plurality of waveguides defined by the plurality of projecting, tapering structures aligning with the plurality of waveguides defined by the plurality of box-shaped structures. The substrate includes a plurality of probes for feeding the plurality waveguides.

Many existing antenna arrays utilize printed circuit board (PCB) antennas as the radiating elements. Patch antennas are often formed on PCBs using standard PCB fabrication techniques. Although PCB technology provides a potentially low-cost fabrication method, prior art arrays of patch antennas are inherently narrowband due to the narrowband nature of the radiating elements, i.e., the patches. Some researchers have attempted to increase the bandwidth of PCB array antennas by utilizing wideband printed circuit elements such as printed spiral antennas. Although these elements are inherently wideband, they require a large area (relative to a wavelength of the frequencies of interest) and the element spacing cannot be made small enough to avoid grating lobes for scans at low elevation angles. Thus, these prior art wideband elements severely limit the achievable field of view of the array.
Elongated radiating elements are known in the prior art as seen with the dielectric rod antenna disclosed in U.S. Pat. No. 6,208,308. Although this antenna is wideband and can be closely spaced to neighboring elements, the dielectric rod is not inherently compatible with PCB technology. The most common way to excite a rod antenna is from a waveguide. Since a typical low cost array requires that electronic components be mounted on a PCB, this type of array requires a PCB to be mounted to a dielectric rod transition. A low cost method of fabrication for this complicated transition structure does not exist at this time. (Note: many practical antenna arrays require thousands of elements.)
One related prior art disclosure is the microstrip reflect array antenna described in U.S. Pat. No. 4,684,952. This antenna suffers the limitations described above, specifically that the bandwidth is very low, a few percent at most. The present invention provides better impedance and pattern bandwidth by using radiating elements that are not constrained to be planar. In one embodiment, the radiating elements are pyramidal in shape although other shapes could be used that may give even better performance. The extent of the radiating element, which may be more than one wavelength, creates a gradual transition from the narrow throat of the element (near the planar element feed) to free space, thus obtaining a relatively good impedance match over a wide frequency range.
Other antenna arrays attempt to increase the bandwidth by various means. One approach uses "wideband" patch elements that contain parasitic patches or stubs. Although this does increase the array bandwidth somewhat, patches remain inherently narrowband and the overall array bandwidth remains low. Another approach, found in D. G. Shively and W. L. Stutzman, "Wideband arrays with variable element sizes," IEE Proceedings, Vol. 137, Pt. H, No. 4, August 1990, suggests the use of other wideband printed elements for use in an array, such as printed spirals. Wideband planar antennas necessarily have a width that is larger than half a wavelength, usually by many wavelengths. Incorporating any planar wideband element into an array restricts how close the elements can be placed. This restriction limits the amount of scanning that can be accomplished (i.e., the antenna field of view) since excessive scanning will result in grating lobes unless the inter-element spacing can be kept near half a free space wavelength. The present invention extends the element size in a direction perpendicular to the plane of the array to achieve wideband characteristics while keeping its extent in the plane of the array to half a wavelength or less. This way, wideband operation can be achieved over a wide field of view.
Typical phased array antennas are made of transmit/receive (T/R) modules that contain the radiating element as well as RF electronics, such as low noise amplifiers, mixers, and oscillators. This modular architecture allows each individual element to be manufactured separately; however, high gain antenna arrays that require thousands of elements are extremely expensive. A more recent approach found in R. J. Mailoux, "Antenna Array Architecture," Proc. IEEE, vol. 80, no. 1, 1992, pp 163–172, has been the "tile" architecture where the RF circuitry for each element resides on a planar surface with the radiating element located on the backside of the planar RF substrate. The present invention preferably uses "tile" architecture, which is lower in cost than the T/R module approach, but the tiles must be electrically connected to the radiating element with low RF losses. To avoid complicated RF transitions, it is desirable to use radiating elements that are compatible with PCB technologies. This invention describes how to make very wide bandwidth radiating elements that are fully compatible with PCB technologies.


Disclosed herein are a thermoplastic copolymer, which is a polymer of a monomer mixture including: a phosphorus (meth)acrylic monomer represented by Formula 1; an aromatic vinyl monomer; and a vinyl cyanide monomer. The thermoplastic copolymer can exhibit excellent flame retardancy with minimal or no deterioration in heat resistance, and is eco-friendly.

Thermoplastic resins exhibit excellent physical properties, such as low specific gravity, good moldability, and good impact resistance, as compared with glass or metal. Recently, with the trend of producing low cost, larger and lighter weight electronics, plastic products made of thermoplastic resins are quickly replacing existing glass or metal-based products, thereby broadening application ranges of the thermoplastic resins to fields from electronics to automobile components.
To impart flame retardancy to the thermoplastic resins, a method of blending antimony, halogen, phosphorus compounds, or compounds containing nitrogen as a flame retardant is widely known. Among such flame retardants, when a halogen flame retardant is used, there are drawbacks in that the halogen flame retardant causes corrosion of a processing apparatus due to corrosive gases generated therefrom during processes, and generates toxic gases such as dioxin, hydrogen halide gases and the like during burning. Thus, demand for resins free from halogen flame retardants is increasing.
The most general technique for imparting flame retardancy without use of the halogen flame retardants is use of phosphorus flame retardants. However, although phosphorus flame retardants are superior to the halogen flame retardants in terms of suppression of corrosive gases and toxic gases, phosphorus flame retardants exhibit lower flame retardancy than halogen flame retardants and have a drawback in that polymeric resins capable of acting as a flame retardant are limited to resins containing polycarbonate and polyphenylene ether. In addition, a higher amount of a phosphoric acid ester flame retardant causes deterioration in heat resistance of a resin composition. Further, the phosphoric acid ester flame retardant has problems in that a molded article suffers from a juicing phenomenon causing the phosphoric acid ester flame retardant to move to a surface of the molded article, or in that an injection-molded article suffers from black points and black lines on a surface thereof due to decomposition of the flame retardant, and deteriorates mechanical strength, such as impact strength, flexural strength, flexural modulus, and the like.
To resolve such problems, a method of introducing a flame retardant into a polymer chain has been proposed. For example, U.S. Pat. Nos. 3,725,509 and 4,014,836 disclose use of a copolymer of a halogen-containing unsaturated monomer and bis(hydrocarbyl)vinyl phosphonate as a flame retardant additive, and U.S. Pat. Nos. 4,444,969 and 4,571,418 disclose flame retardant copolymers prepared by copolymerization of an aromatic vinyl monomer, bis(hydrocarbyl)vinyl phosphonate, and an imide derivative of unsaturated anhydride. In addition, U.S. Pat. No. 4,035,571 discloses a flame retardant copolymer prepared by copolymerization of an unsaturated monomer, bis(hydrocarbyl)vinyl phosphonate, and acrylic or methacrylic acid.
However, such methods and copolymers have drawbacks in that a large amount of bis(hydrocarbyl)vinyl phosphonate must be introduced to secure sufficient flame retardancy, thereby extremely limiting use of the copolymers due to deterioration in heat resistance and mechanical properties.
Therefore, there is a need for a novel flame retardant thermoplastic copolymer, which can prevent deterioration in heat resistance caused by simple addition of a phosphorus flame retardant, and impart flame retardancy.

Flame retardant thermoplastic copolymer, method for preparing the same, and molded article including the same

Abstract: wherein R1 is hydrogen or methyl; R2 is a substituted or unsubstituted C1 to C20 hydrocarbon group; R3 and R4 are each independently a substituted or unsubstituted C6 to C20 cyclic hydrocarbon group; m is an integer from 1 to 10; and n is an integer from 0 to 5.