A housing for a solid, fluidal substance for removing an undesired respiratory gas component of a respiratory gas flow, the housing comprising a space for receiving the solid, fluidal substance, a wall surrounding part of the space, a first separator surrounding part of the space, the first separator being configured to allow the respiratory gas to flow and to prevent the solid, fluidal substance from escaping from the space through the first separator, a second separator surrounding part of the space, the second separator being configured to allow the respiratory gas to flow and to prevent the solid, fluidal substance from escaping from the space through the second separator; and a limiter disposed between the first separator and the second separator, the limiter being configured to limit movement of the solid, fluidal substance inside the space.

Field of the Invention
This disclosure relates generally to a housing for solid, fluidal substance for removing an undesired respiratory gas component of a respiratory gas flow and an arrangement for ventilating lungs of a subject.
Description of the Prior Art
Anesthesia machines are optimized for delivering anesthesia to a patient using volatile anesthetic agent liquids. In such systems, the anesthetic agent is vaporized and mixed into the breathing gas stream in a controlled manner to provide a gas mixture for anesthetizing the patient for a surgical operation. The most common volatile anesthetic agents are halogenated hydrocarbon chains, such as halothane, enflurane, isoflurane, sevoflurane and desflurane. Additionally, nitrous oxide (N2O) can be counted in this group of volatile anesthetic agents, although the high vapor pressure of nitrous oxide causes nitrous oxide to vaporize spontaneously in the high pressure gas cylinder, where it can be directly mixed with oxygen. The anesthetizing potency of nitrous oxide alone is seldom enough to anesthetize a patient and therefore another volatile agent is used to support that.
Since the volatile anesthetic agents are expensive and are effective greenhouse gases that are harmful to the atmospheric ozone layer, anesthesia machines have been developed to minimize the consumption of the gases. To keep a patient anesthetized, a defined brain partial pressure for the anesthetic agent is required. This partial pressure is maintained by keeping the anesthetic agent partial pressure in the lungs adequate. During a steady state, the lung and body partial pressures are equal, and no net exchange of the anesthetic agent occurs between the blood and the lungs. However, to provide oxygen and eliminate carbon dioxide, continuous lung ventilation is required.
Anesthesia machines are designed to provide oxygen to the patient and eliminate carbon dioxide (CO2), while preserving the anesthetic gases. To meet these goals a re-breathing circuit is used, in which a patient's exhaled gas is reintroduced for inhalation. Before re-inhalation, carbon dioxide must be removed from the gas, which is done with a carbon dioxide absorber. Before inhalation, the gas is supplied with additional oxygen and anesthetic agents based upon the patient demand. In this arrangement, the additional gas flow added to the re-breathing circuit can be less than 0.5 L/min although the patient ventilation may be 5-10 L/min. Such ventilation of the lung is carried out using a ventilator pushing inhalation gas with overpressure to the patient's lungs and then allowing that to flow out passively from the pressurized lungs to the breathing circuit.
Ventilation carries the breathing circuit oxygen to lungs for uptake to be burned in body metabolism. The outcome is CO2 that diffuses to lungs and is carried out with exhalation gas. Before re-inhalation the gas is guided through an absorber for CO2 removal. Effective CO2 removal requires close contact with the breathing gas and the removing substance. To provide large contact area, the removing substance is therefore a surface of a porous structure of granules that fill a cartridge. The form of this granular structure is guided by flow resistance, the limitation of which is one of the key design goals of the breathing circuit. In an absorber optimized for minimal resistance, the gas flow path through the stacked granules is short and the flow distributes to a wide area. In such structure the gas flows slowly because the large surface area provides time for reaction between the gas and absorbent granules.
However, such optimal wide and short cartridge design involves a problem. Because the removing material is in granules, the granules may move in relation to each other. Packaging of the granules into a cartridge occurs in a factory, and thereafter the cartridge is transported to a customer site. The granules experience shaking during transportation which compresses the granules, increases the granule packaging grade and reduces the volume of the granule bed in the cartridge. Therefore the cartridge may have some empty space on its top when used. Because of the empty space, the gas flows through the absorber vertically, since when flowing horizontally the gas, which favors the route of the least resistance, would flow through the empty space without communication with the absorbent and thus allows the CO2 to flow through the absorber.
When the gas flows vertically, the horizontal empty space is not harmful since the horizontal empty space does not disturb the internal flow resistance distribution within the cartridge. However, if the top surface of the granules is slanted as shown in FIG. 1, flow density at the low granule level, where the empty space 1 exists, increases over the areas of high level of granules 2. This is known as a flow channeling. A typical cartridge 3 comprises a gas input 4, a gas output 5 and mesh plates 6 and 7 for preventing granules therebetween to escape from the cartridge. A demand of CO2 removal is proportional to the flow rate and the absorbent is consumed faster at the volumes of high gas flow. The absorbent volume in these areas is also smaller. Each of these factors causes fast absorbent wear-out at these high flow volumes. When all absorbent has been consumed, the CO2 penetrates through the cartridge using the flow path where the capacity has been reduced, which increases the inspired patient gas CO2 concentration. This signals the wear-out of the whole cartridge, even though unused material may still exist at the reduced flow volumes. Therefore, slanting reduces usable cartridge CO2 removal capacity. The surface level of the granules may become slanted if inclined during unpacking and installing a cartridge having empty space caused during transportation.

Housing for solid, fluidal substance for removing an undesired respiratory gas component of a respiratory gas flow and an arrangement for ventilating lungs of a subject


The present disclosure relates to a display apparatus. The display apparatus may include a display panel, a peripheral region, an electronic component, and a gap-fill layer. The display panel defines a display region. The peripheral region is adjacent to the display region. The peripheral region includes lines and pads. The lines are disposed in the peripheral region, and the pads are connected to the lines. The electronic component includes connecting pads in contact with the pads. The gap-fill layer is between the display panel and the electronic component, between the connection pads, between the pads, and in the openings. Each of the pads may overlap at least two pads of the connection pads, and the openings may overlap between the connection pads, when viewed in a plan view.

The present disclosure relates to a display apparatus, and in particular, to a display apparatus with increased bonding reliability.
Televisions, mobile phones, tablet computers, navigation systems, gaming machines, and the like use display devices to convey information to a user. These display devices may contain a display panel. The display panel includes electrical lines for transmitting electrical signals. The display device may also contain other electronic components that provide the electrical signals. The electrical signals are used to display an image on the display panel.
The electronic components may be connected to the display panel through a conductive film or by other bonding methods. Some boding methods increase the conduction property between the display panel and the electronic components. In some cases, the bonding methods may be unreliable. Therefore, there is a need in the art for systems and methods to increase bonding reliability between a display panel and other electronic components.


Provided is a method, system, and article of manufacture for generating topology information including information on local interfaces in a device and remote interfaces in at least one remote device that connect to the local interfaces identified in the topology information. For each connected remote interface, a determination is made of a device type of the one remote device including the remote interface. For each local interface connecting to one remote interface in one remote device of a specified device type, communication initiated with the remote interface to access remote topology information from the remote device indicating devices attached directly and indirectly to the remote device.

1. Field
The present embodiments relate to generating topology information identifying devices in a network topology.
2. Description of the Related Art
An adaptor or multi-channel protocol controller enables a device coupled to the adaptor to communicate with one or more connected end devices over a connection according to a storage interconnect architecture, also known as a hardware interface, where a storage interconnect architecture defines a standard way to communicate and recognize such communications, such as Serial Attached Small Computer System Interface (SCSI) (SAS), Serial Advanced Technology Attachment (SATA), Fibre Channel, etc. Further details on the SAS architecture for devices and expanders is described in the technology specification "Information Technology—Serial Attached SCSI (SAS)", reference no. ISO/IEC 14776-150:200x and ANSI INCITS.***:200x PHY layer (Jul. 9, 2003), published by ANSI (referred to herein as the "SAS Specification"); details on the Fibre Channel architecture are described in the technology specification "Fibre Channel Framing and Signaling Interface", document no. ISO/IEC AWI 14165-25; details on the SATA architecture are described in the technology specification "Serial ATA: High Speed Serialized AT Attachment" Rev. 1.0A (January 2003).
Devices may communicate through a cable or through etched paths on a printed circuit board when the devices are embedded on the printed circuit board. These storage interconnect architectures allow a device to maintain one or more connections with end devices through a direct connection to the end device or through one or more expanders. In the SAS/SATA architecture, a SAS port is comprised of one or more SAS PHYs, where each SAS PHY interfaces a physical layer, i.e., the physical interface or connection, and a SAS link layer having multiple protocol link layer. Communications from the SAS PHYs in a port are processed by the transport layers for that port. There is one transport layer for each SAS port to interface with each type of application layer supported by the port. A "PHY" as defined in the SAS protocol is a device object that is used to interface to other devices and a physical interface.
An expander is a device that facilitates communication and provides for routing among multiple SAS devices, where multiple SAS devices and additional expanders connect to the ports on the expander, where each port has one or more SAS PHYs and corresponding physical interfaces. The expander also extends the distance of the connection between SAS devices. With an expander, a device connecting to a SAS PHY on the expander may be routed to another expander PHY connected to a SAS device. Further details on the SAS architecture for devices and expanders is described in the SAS Specification.
A port in an adaptor or expander contains one or more PHYs. Ports in a device are associated with PHYs based on the configuration that occurs during an identification sequence. A port is assigned one or more PHYs within a device for those PHYs within that device that are configured to use the same SAS address during the identification sequence and that connect to attached PHYs that also transmit the same address during the identification sequence. A wide port has multiple PHYs and a narrow port has only one PHY. A wide link comprises the set of physical links that connect the PHYs of a wide port to the corresponding PHYs in the corresponding remote wide port and a narrow link is the physical link that attaches a narrow port to a corresponding remote narrow port.
The SAS specification provides two expander types, a fanout expander and an edge expander. A fanout expander may be located between edge expanders. An edge expander PHY connects to a fanout expander PHY, and each fanout expander PHY may connect to a separate edge expander, which edge expander connects to end devices. However, in the current SAS specification, there can only be one fanout expander in a domain. A domain comprises all devices that can be reached through an initiator port, where the port may connect to multiple target devices through one or more expanders or directly. Further, each edge expander device set shall not be attached to more than one fanout expander device. An edge expander device set may be attached to one other edge expander device set if that is the only other edge expander device set in the domain and there are no fanout expander devices in the domain.
After the identify and link initialization sequences where the initiator obtains the address of each PHY connected to one of its PHYs, the initiator performs link initialization to determine all devices that can be accessed from one port, otherwise known as the domain for that port. The initiator begins the discovery process by determining that an expander is attached and configures the attached expander if configuration is necessary. The initiator then traverses the topology by opening a Serial Management Protocol (SMP) connection to the attached expander device and querying each expander PHY in ascending order using the SMP DISCOVER function to discover the PHYs on devices connected to the expander PHYs. If the initiator discovers that a device attached to the expander PHY being queried is a further expander, then the initiator will issue SMP discovery requests to discover every device and its PHYs attached to that further expander. This process continues until the initiator discovers all target devices in the domain of each port on the initiator. This process is further repeated by every end device, i.e., initiator and target, in a topology to discover all connected devices in the topology.

Generating topology information identifying devices in a network topology


A face detection method and apparatus using a level-set method. The method includes: laying a first initial shape model over a face image; evolving shape curves of the first initial shape model using the level-set method; detecting first through M-th neighboring boundary points that neighbor first through M-th initial boundary points of the first initial shape model, and that neighbor the evolved shape curves, M being a positive integer larger than 1; laying a modified shape model rendered using the detected first through M-th neighboring boundary points over the face image; detecting a rotation angle of the modified shape model; determining whether the detected rotation angle of the modified shape model is within a predetermined angle range; and selecting one of a second initial shape model, which is rotated to the left, or a third initial shape model, which is rotated to the right, according to the detected rotation angle, and laying the selected initial shape model over the face image, and returning to the detecting of the first through M-th neighboring boundary points, when the detected rotation angle of the modified shape model is outside the predetermined angle range.

1. Field of the Invention
The present invention relates to an image processing apparatus, such as a digital camera, and more particularly, to a face detection method and apparatus using a level-set method that is capable of quickly detecting the shape of a face from an image.
2. Description of the Related Art
Image processing devices use principal component analysis (PCA) in order to detect human faces. PCA is a technique of dividing a learning image into a plurality of eigen images that represent features of the learning image using the statistical characteristics of the learning image and then rendering an image using a linear combination of the eigen images.
In other words, PCA, which is one of the most widely used face detection methods, analyzes arbitrary input data using principal components extracted using a plurality of eigenvalues and a plurality of eigenvectors.
However, PCA is vulnerable to variations in pose and illumination. In other words, PCA provides low face detection rates especially when detecting a face in an image where a person horizontally or vertically moves his or her face or where illumination abruptly changes.

Face detection method and apparatus using level-set method


A method of treating a disorder in a patient is provided. The method comprises delivering a stimulation lead within a blood vessel, intralumenally puncturing a wall of the blood vessel to create an exit point, and then introducing the stimulation lead through the exit point into direct contact with tissue the stimulation of which treats the disorder. Optionally, the method comprises implanting a source of stimulation within the patient's body, and then electrically coupling the proximal end of the stimulation lead to the implanted stimulation source. Using the stimulation lead, the tissue can then be stimulated in order to treat the disorder.

It is known to treat neurodegenerative diseases, such as Alzheimer's Disease, Parkinson's Disease, Tremor, and Epilepsy, and ischemia of the brain, such as stroke, by electrically stimulating selected portions of the brain. Currently, this is accomplished by first drilling a burr hole through the patient's cranium in order to gain access to the brain tissue. A stimulation lead, and in particular, a lead with multiple electrodes extending along its length, is then introduced through one or more burr holes into contact with the selected brain tissue. In a deep brain stimulation (DBS) procedure, typically used to treat Parkinson's Disease, Tremor, and Epilepsy, the stimulation lead is advanced through a burr hole deep into the brain, e.g., the anterior thalamus, ventrolateral thalamus (Thal), internal segment of globus pallidus (GPi), substantia nigra pars reticulata (SNr), subthalamic nucleus (STN), external segment of globus pallidus (GPe), and neostriatum. In a cortical brain stimulation procedure, typically used to rehabilitate stroke victims, the lead is introduced through two burr holes and placed underneath the dura matter in contact with the cortex of the brain.
Once the lead is properly located in contact with the selected brain tissue, the proximal end of the lead or an extension lead is subcutaneously routed from the burr hole underneath the patient's scalp, down the neck, and into the chest region in electrical connection with an implanted electrical stimulator. The electrical stimulator is programmed either prior to or after the procedure to deliver electrical pulses to the brain tissue via the stimulation lead.
Although the current brain stimulation techniques used to treat neurological disorders have proven to be successful, such techniques are still quite invasive, requiring the cranium to be opened through at least one burr hole. In addition, the need for a burr hole further complicates the procedure—not only requiring the additional step of accessing the patient's cranium while attempting to minimize tissue trauma, but also requiring that the burr hole be capped at the end of the procedure. Also, additional risks are posed by the possibility that the burr hole may become infected and the routing of the stimulation or extension leads through the neck in close proximity to the jugular veins and carotid arteries.
Thus, there remains a need to provide improved methods, apparatus, kits, and systems for therapeutically stimulating tissue.

This patent is subject to a terminal disclaimer.

Method of intravascularly delivering stimulation leads into direct contact with tissue


A method in an industrial process control and remote engineering system comprises receiving, by a remote control system, a control configuration, interfacing, by the remote control system, via a network, with at least one process equipment, and remotely controlling, by the remote control system, the at least one process equipment according to the control configuration. In some embodiments of the method, the remote control system is a twin of a local control system.

Industrial process control and automation systems are routinely used to automate large and complex industrial processes. These types of systems typically include sensors, actuators, and controllers, and include algorithms and control configurations created to control and monitor the system. Typically, process equipment from multiple manufacturers is used in any given process in an industrial plant. Equipment from disparate manufacturers is typically brought together on the plant site and connected to controllers in order to validate control configurations using the equipment.

Cloud based control for remote engineering


In an adaptive transform coding system and/or and adaptive transform decoding system, coding efficiency in the case where a small number of quantized values having large absolute value are present, is improved. The adaptive transform coding system codes the small number of quantized values having large absolute values and other quantized values are coded separately. More particularly, the adaptive transform coding system includes a selector (6) discriminating the small number of quantized value having large absolute value from other quantized value, a pulse coding means for coding the small number of quantized values having large absolute values (8) and the pulse decoding means (16) for decoding the same, a coding means (7) for coding the quantized value other than those having large absolute values and a decoding means (15) decoding the same, and a synthesis means (18) for synthesizing the small number of quantized values having large absolute value and other quantized values.

1. Field of the Invention
The present invention relates generally to an adaptive transform coding and/or decoding system. More specifically, the invention relates to a system for efficiently coding and decoding speech and audio signals with maintaining high quality.
2. Description of the Related Art
Conventionally, as an adaptive transform coding system and an adaptive transform decoding system for efficiently coding and decoding a speech signal and an audio signal with maintaining high quality, there are MPEG (Moving Pictures Expert Group)/Audio Layers 3 or so forth. The technology of MPEG/Audio Layer 3 has been discussed in 1993 ISO/IEC 11172-3, "Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mb/s" (hereinafter simply referred to as reference No. 1).
FIG. 3 is a block diagram showing one example of the conventional adaptive transform coding system. The conventional adaptive transform coding system is constructed with an input terminal 1, a transform means 2, an analysis means 3, a quantizing parameter determining means 4, a quantizing means 5, a coding means 7, a parameter coding means 9, an adder 22, a multiplexer 23 and an output terminal 12.
In the input terminal 1, digitized audio signal samples are inputted. The input audio samples are outputted to the transform means 2 and an analysis means 3.
In the transform means 2, at every input of N time-domain audio samples, N frequency-domain-samples are generated from the input audio samples by a hybrid analysis filter bank. N frequency-domain-samples grouped in ascending order are referred to as "frame". The derived frequency-domain-samples are outputted to the quantizing means 5 and the analysis means 3. N is a positive integer, and in case of MPEG/Audio Layer 3, N is 576. The hybrid analysis filter bank has been discussed in detail in the foregoing reference 1.
In the analysis means 3, an allowable quantization error for each frequency-domain-sample in the frame is derived and outputted to the quantization parameter determining means 4. In coding of the audio signal, a subjective quality is important. Therefore, allowable quantization error is determined so that the degradation of the frequency domain signals is not easily perceptible by human acoustic sense. The manner of determining the allowable quantization error has also been discussed in detail in the reference 1. For example, there is a method to analyze a frequency spectrum obtained through Fourier transform of the input audio samples.
In the quantizing means 5, the frequency domain signal X is quantized on the basis of a quantization step size QS derived from the quantization parameter determining means 4, Then, the quantized value Y is derived from rounding the (¾)th power of quantized frequency domain signal. Namely, the quantized value Y is expressed by:Y=nint(pow(X/S, ¾))
Wherein nint ( ) represents rounding process for rounding the fraction off after the decimal point, and pow (a, b) represents a to the (b)th power. The quantized values in each frame are grouped in ascending order in the frequency to be fed to the coding means 7. On the order hand, the quantizing means 5 calculates a quantization error YZ to output to the quantization parameter determining means 4. An inverse-quantized value YY of the quantized value Y is expressed by:YY=pow(Y, 4/3)
Therefore, the quantization error YZ is expressed as:YZ=X−pow(Y, 4/3)
In the coding means 7, as set out in detail later, each quantized value in the frame is encoded. Then, a code C1 and a code amount L1 of the code C1 are derived. The code C1 is outputted to the multiplexer 23, and the code amount L1 is outputted to the adder 22.
In the parameter coding means 9, the quantization step size QS inputted from the quantization parameter determining means 4 is encoded. Then, a code C2 and a code amount L2 of the code C2 are derived. The code C2 is inputted to the multiplexer 23 and the code amount L2 is inputted to the adder 22.
In the adder 22, the total code amount outputted from the coding means 7 and the parameter coding means 9, namely the sum of L1 and L2, is derived, and outputted to the quantization parameter determining means 4 as a total code amount.
The total code amount outputted from the adder 22 is variable depending upon the size of the quantization step size QS. Generally, when the quantization step size QS becomes smaller, the total code amount becomes larger and when the quantization step size QS becomes larger, the total code amount becomes smaller. In the quantization parameter determining means 4, the quantization step size Q is controlled so that the total code amount can be maintained to be less than or equal to the allowable code amount which is determined on the basis of the coding bit rate, and that the quantization error is proportional to the allowable quantization error. For an example of this control, at first, the quantization step size QS is set at sufficiently small value, and the coding means 7 and the parameter coding means 9 are operated to derive the total code amount. Then, the following two operations are repeated until the total code amount becomes equal or less than the allowable code amount. As the first operation, the quantization step size QS is set at a greater value in proportion to the allowable quantization error. Then, the coding means 7 and the parameter coding means 9 are operated to derive the total code amount.
In the multiplexer 23, the codes C1 and C2 are multiplexed to generate a bit stream.
The bit stream is outputted from the output terminal 12.
In the coding means 7, the quantized values of the frame are divided into three regions on the frequency axis, i.e. a type 1 region, a type 2 region, and a type 3 region. Each quantized values in the type 1 region and the type 2 region are Huffman-encoded.
At first, a method for dividing the quantized values in the frame into three regions will be discussed. The N quantized-values are grouped in ascending order of the frequency and compose the vector X as follows:Vector X=[x(1), x(2), . . . , x(N)]
Each element x(1), x(2), . . . , x(N) of the vector X represents respective quantized value. The type 1 region includes the quantized values of the low frequency signal, and includes x(1), x(2), . . . , X(2×bigvalues) of (2×bigvalues) elements. The type 2 region includes the quantized values whose absolute values are 0 or 1 and includes x(2×bigvalues+1), x(2×bigvalues+2), . . . , x(2×bitvalues+4×count 1) of (4×count1) elements. The type 3 region includes elements whose values are zero, and includes x(2×big values+4×count1+1), x(2×bigvalues+4×count1+2), . . . , x(N) of (2×rzero) elements. Here,2×big_values+4×count1×2×rzero=N.
The value rzero is calculated byrzero=(N−t(t mod 2))/2
where t is the maximum value satisfyingx(t)=0, (t=1, 2, . . . , N)
(x1 mod x2) represents the remainder in division by x1 by x2.
The value count1 is calculated bycount1=(N−rzero×2−t2 −((N−rzero×2−t2) mod 4/4 where t2 is the maximum value satisfying |x(t2)|>1. The value bigvalues is derived frombig_values=(N−rzero×2−count1×4)/2
Each element included in the type 1 and type 2 regions is Huffman-coded employing a table selected among prepared Huffman tables for respective regions. An appropriate Huffman table is selected so that the total amount of the Huffman code becomes minimum.
Huffman tables prepared for coding respective elements in the type 1 region are different in terms of the assumed appearance frequency of respective element-values and the region of the quantized values to be coded. The region of the quantized values to be coded by the Huffman table selected upon coding of each element in the type 1 region becomes larger depending upon the maximum absolute value of respective elements included in the type 1 region. All the same time, each code in the Huffman table generally becomes longer. On the other hand, since the type 2 region includes only elements having absolute values 0 or 1, the average code amount per one element upon coding in the type 2 region becomes smaller than that of the type 1 region.
The bigvalues, rzero and information relating to the Huffman tables to be used in the type 1 region and the type 2 region are coded as side information. The Huffman code and the side information are multiplexed and outputted as the code C1.
FIG. 4 is a block diagram showing one example of the adaptive transform decoding system. The conventional adaptive transform decoding system includes an input terminal 13, a demultiplexer 24, a decoding means 15, a parameter decoding means, an inverse quantizing means 19, an inverse transform means 20 and the output terminal 21.
To the input terminal 13, the bit stream is inputted. The bit stream is then outputted to the demultiplexer 24.
In the demultiplexer 24, the bit stream is separated into the code C1 and the code C2. The code C1 is outputted to the decoding means 15 and the code C2 is outputted to the parameter decoding means 17. In the parameter decoding means 17, the quantization step size is derived by decoding the code C2. The derived quantization step size is outputted to the inverse quantizing means 19.
In the decoding means 15, at first, the code C1 is separated into the Huffman codes and the side information. Next, the quantized values of the type 1 region and the type 2 region are derived by decoding the Huffman codes using the Huffman table indicated by the side information. The quantized values thus obtained are fed to the inverse quantizing means 19.
In the inverse quantizing means 19, an inverse quantized value is derived by the inverse quantization of the quantized value. The inverse quantized value YY is derived from the quantized value Y through the following equation:YY=pow(Y, 4/3) The inverse quantized values thus derived are outputted to the inverse transform means 20.
The inverse transform means 20 derives a time domain signal from the inverse quantized values through a hybrid synthesis filter bank. The hybrid synthesis filter bank has been discussed in detail in the foregoing reference 1.
Then, the time domain signal is outputted from the output terminal 21.
A first problem encountered in the foregoing adaptive transform coding and decoding systems is low coding efficiency upon coding the element in the vicinity of the boundary to the type 2 region in the type 1 region.
Most elements of the type 1 region in the vicinity of the boundary to the type 2 region have absolute value of 0 or 1 similar to the elements in the type 2 region. These elements may be encoded by using the Huffman code table for the type 2 region. However, because of the presence of a small number of elements having absolute value of 2 or more, in the vicinity of the boundary to the type 2 region, the elements having absolute value 0 or 1 in the vicinity of the boundary to the type 2 region of the type 1 region should be coded as elements in the type 1 region. Since the average code amount for one element in the type 1 region is larger than that in the type 2 region, when a small number of elements having absolute value of 2 or more are included in the type 1 region in the vicinity of the boundary to the type 2 region, the coding efficiency is degraded.
The second problem to be encountered is that when the type 1 region includes a small number of elements having a large absolute value, the coding efficiency is degraded.
The size of the Huffman table to be selected upon coding the elements in the type 1 region becomes larger depending upon the maximum absolute value of the element included in the type 1 region. At the same time, each code length in the Huffman table becomes longer. When the type 1 region includes a small number of elements having large absolute value, the average code amount for one element becomes large and the coding efficiency is degraded.

Adaptive transform coding system, adaptive transform decoding system and adaptive transform coding/decoding system


A push-button telephone dialing device for a telephone set has a push-button keypad with a plurality of keys which include a hold function key, and a telephone dialing integrated circuit including a key input signal generator wired to the push-button keypad and producing an appropriate key input signal corresponding to a key pressed on the push-button keypad. The key input signal generator produces a hold function key input signal whenever the hold function key is pressed. The telephone dialing integrated circuit further includes a speech network interrupt circuit which receives the hold function key input signal from the key input signal generator. The speech network interrupt circuit is wired to and controls the operation of a speech network of the telephone set.

1. Field of the Invention
This invention relates to a push-button telephone dialing device, more particularly to a push-button telephone dialing device which incorporates a telephone hold function circuit.
2. Description of the Related Art
As the number of telephone sets in a single household increases, so does the need to provide each telephone set with an additional telephone hold function circuit. Presently, there are two methods which can be employed so as to incorporate the telephone hold function in a telephone set. In the first method, an additional telephone hold circuit is connected to a telephone dialing integrated circuit of the telephone set. The required number of components is increased, thereby increasing the complexity and cost of the system. In the second method, the telephone hold function circuit is incorporated in the telephone dialing integrated circuit. The size of the telephone dialing integrated circuit is increased because two additional pins (the hold function input pin and the hold function output pin) are required. Moreover, the hold function input signal employed in the second method is not derived from the push-button keypad of the telephone set and thus does not undergo a debouncing process to obviate any erroneous signal. Therefore, the untimely entry and release of the telephone set from the telephone hold state caused by erroneous signals cannot be prevented.
Most telephone sets are also provided with a "hands-free" dialing circuit to permit the execution of a dialing action without lifting the telephone handset. In a conventional telephone dialing integrated circuit, which incorporates both hands-free dialing and telephone hold circuits, the operation of one function is completely independent and does not affect the operation of the other function.
To reduce the electrical power consumption of conventional telephone sets, the status of the telephone handset (off hook or on hook) is used to determine when electric power should be supplied to the telephone dialing integrated circuit. Thus, dialing and communication can be achieved only when the telephone handset is an off hook condition. No keypad input signal can be received by the telephone dialing integrated circuit when the telephone handset is in an on hook condition. From the foregoing, it can be concluded that the hands-free dialing function is incompatible and cannot be incorporated in a keypad input scan system. The keypad input scan system can be used with the telephone hold function since the telephone hold function is generally deployed when the telephone handset is in an off hook condition.

Push-button telephone dialing device with telephone hold function circuit


A radiation imaging system that can continuously use sections of a radiation imaging device that has not been damaged and a radiation imaging device are provided. The radiation imaging system comprises: a radiation device that applies radiation; and the radiation imaging device with an imaging panel that captures images of the applied radiation. The radiation imaging device comprises: a failure cause detection unit that detects environmental noise or falls that cause failures in the radiation imaging device; a malfunction diagnostic unit that, in a case where a detected environmental noise value reaches a threshold value or in a case where a fall has been detected, diagnoses a malfunction in the radiation imaging device; and a function limiting unit that applies limits to the radiation imaging device functions that are used continuously, in accordance with the diagnosis results of the malfunction diagnostic unit.

In the medical field, portable radiographic image capturing apparatus (e.g., FPD (Flat Panel Detector)) have been used for capturing a radiographic image of interior portions of a human body by detecting the intensity of radiation that has passed through the human body. Since the user of a portable FPD carries the portable FPD, the user may mistakenly drop the portable FPD or hit the portable FPD against a hard object such as an image capturing base, a door, or the like while handling the portable FPD, which could possibly cause damage to the portable FPD.
Japanese Laid-Open Patent Publication No. 2005-177379 discloses a portable FPD equipped with an impact sensor. The portable FPD initiates a self-diagnostic process in response to a signal from the impact sensor. If it is decided that the portable FPD has a fault based on the results of the self-diagnostic process, then the portable FPD is prohibited from starting an image capturing process or applying radiation to a target subject.

Radiation imaging system and radiation imaging device


The present invention provides a method, system, terminal, and storage medium for rapid generation of reference lines. Path planning points are classified according to driving difficulty of different road segments, and the segments with low driving difficulty are assigned reference lines obtained by geometric processing; the segments with high driving difficulty are assigned reference lines obtained by algorithmic processing in combination with vehicle dynamics constraints. Then the reference lines of all segments are combined to form a complete reference line. This method requires little system resource and the algorithm consumes less time.

Reference lines are commonly used in path planning services based on a map. After receiving a start location and a destination input by the user, the map module generates a global path, which consists of sparse path nodes along the roads of a chosen route. The path nodes are topologically connected from the start location to the destination to form the global path.
Generally, the path nodes in a global path are geometrically connected by straight lines. Nevertheless, under circumstances of different road scenarios and various vehicle models with different dynamical parameters, a reference line has to simultaneously satisfy vehicle dynamics constraints and complex road conditions in reality as the vehicle's actual driving path of L4 or even L5. In complex parking lot scenarios, reference lines are updated by algorithm every time it receives a local map. Road segments with different driving difficulties also entail different difficulties in calculating reference lines. Adopting a single universal algorithm for all road segments with different driving difficulties will result in waste of system resources and make the calculation time-consuming.

Method, system, terminal, and storage medium for rapid generation of reference lines


A lithographic apparatus configured to transfer a pattern from a patterning device onto a substrate includes an integrated post-exposure bake device, the post-exposure bake device configured to subject the substrate to a predefined temperature cycle. A post-exposure bake step of the substrate (a temperature cycle) is executed within a predetermined time period after the transfer of the pattern. The lithographic apparatus may be combined with a processing system having one or more processing modules. More efficient use may be made of the combination, allowing flexibility for a device manufacturing method.

A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the "scanning"-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In a chip production facility, or a substrate processing facility, a lithographic apparatus is usually directly connected to a track module. At least one of the processing steps performed by the track module, i.e. the post-exposure bake step, can be time critical. Variation in time between the exposure and the bake of a substrate may then result in variations in obtainable critical dimension (CD). Furthermore, the reliability of the (single) track module or scanner module partly determines the reliability of the entire substrate processing facility (when a module is down, the entire production line is typically down). A track module is in general controlled using a fixed frequency, whereas a lithographic apparatus is more event driven (one exposure step possibly takes much longer than another exposure step for the same substrate).
An inline cluster of a track module and a lithographic apparatus may be created, which eliminates two intermediate transport steps between the track module and the lithographic apparatus. Such a cluster can process substrate layers that require a single or two (or more) consecutive lithographic exposure steps ("double exposure"). A potential problem of such a cluster is that the performance of this linked cluster may be determined by the slowest component in the cluster. The handling complexity in the track module that combines both the coat (i.e., substrate input path) as well as the post exposure bake (PEB) and develop (i.e., substrate output path) processes can result in a situation where the slowest of these steps determines the throughput of the other steps. Therefore, as a result of speed differences and different control strategies, the combination of track module and lithographic apparatus may not always be used at maximum efficiency.

Lithographic apparatus, combination of lithographic apparatus and processing module, and device manufacturing method


There is provided a double closure orifice fitting having an orifice fitting body and a valve carrier sized to be installed within a valve cavity. The body of the valve carrier has an actuator surface on the bottom, retainer clip recesses formed in the first and second end, one or more spring members extending from the top, and a valve strip having retainer clips that is removably attached above the top of the valve carrier body and against the spring members by engaging the retainer clip recesses and the retainer clips such that the retainer clips are held in tension by the one or more spring members. The valve carrier is movable between an open position spaced laterally from the passageway and a sealed position such that the valve strip sealingly engages the valve cavity to seal the passageway by an actuator that engages the actuator surface.

Dual chamber orifice fittings are often sealed by an isolation valve. The isolation valve allows an orifice plate to be replaced or inspected without the need to depressurize or interrupt the flow through the associated flow lines. One example of an orifice fitting with an isolation valve can be found in U.S. Pat. No. 5,474,103 (Klak) entitled "Safety Guard for Orifice Fitting Device".


A cellulose ester composition is provided comprising at least one cellulose ester and at least one polymeric aliphatic polyester (PAP), and optionally at least one impact modifier and/or at least one monomeric plasticizer. Processes for producing the cellulose ester compositions as well as articles made using these compositions are also provided.

Cellulose ester compositions typically have a heat deflection temperature (HDT) or glass transition temperature (Tg) of less than 90° C. Commercially available cellulose esters that are melt processed into articles typically contain significant amounts of monomeric plasticizer to allow for processing and to impart sufficient toughness to the molded article. However, the addition of high levels of monomeric plasticizer can have drawbacks, as it can decrease the HDT relative to the base cellulose ester and limit the use of the cellulose ester materials for applications that can accommodate an HDT below about 90° C. Also, common monomeric plasticizers used in cellulose ester molded articles can experience plasticizer exudation during processing and use.
It would be beneficial to be able to provide melt processable cellulose ester compositions that do not have such drawbacks.

Cellulose ester and polymeric aliphatic polyester compositions and articles


A method is provided for operating a memory system having a plurality of memory blocks. The method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks when the asserted timing signal is received; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted. A memory system for implementing this method is also provided.

The present invention relates to a semiconductor memory that must be periodically refreshed. More specifically, the present invention relates to a method and apparatus for performing refresh operations in a semiconductor memory during idle cycles of the memory.
Some conventional semiconductor memories, such as dynamic random access memory (DRAM), must be periodically refreshed in order to retain valid data. During refresh operations, external access typically is not allowed. In addition, a mechanism is required to inform the memory controller that the DRAM is performing a refresh operation. Any pending memory transaction has to be delayed until the refresh operation is completed. Refresh operations therefore lengthen the overall access time for memory accesses. It is therefore important to design a memory system in which the impact of refresh operations on external memory access is minimized.
Many different methods have been proposed to refresh these semiconductor memories. In one of these methods, which is commonly referred to as xe2x80x9cCAS before RAS,xe2x80x9d an external device signals a refresh operation by asserting a column access signal CAS# prior to asserting a row access signal RAS#. During normal accesses, the column address strobe signal RAS# is asserted before the column address strobe signal CAS#. In response to detecting the xe2x80x9cCAS before RASxe2x80x9d condition, the memory performs a refresh operation. The refresh operation typically is performed by reading the row of the memory to be refreshed. A xe2x80x9cCAS before RASxe2x80x9d refresh scheme is described in 1991 Memory Products Data Book, uPD424248 262,144xc3x974-Bit Dynamic CMOS RAM, NEC Electronics, pp 6-101 to 6-113. This reference also illustrates a hidden refresh that is a variation of the xe2x80x9cCAS before RASxe2x80x9d refresh method. These methods for refresh require handshake communication between the semiconductor memory and the external device, making the external device control the memory refresh.
Another conventional semiconductor memory that must be periodically refreshed is synchronous DRAM (SDRAM). One conventional SDRAM initiates refresh operations in response to control signals (i.e., RAS#, CAS#, CS#, WE# and CKE) received from an external device. These control signals are decoded to provide command codes that are used to control the refresh operations of the SDRAM. For example, when the control signals RAS#, CAS#, CS#, WE# and CKE have values of 0,0,0,1, and 1, a control code for initiating an auto refresh operation is generated. Similarly, when those same control signals have values of 0,0,0,1, and 0, a control code for initiating a self refresh operation is generated. This SDRAM is described in more detail IBM0316409C, 16 Mbit Synchronous DRAM data sheet, 1996, IBM Corporation.
Other synchronous DRAM have used explicit command codes for handling memory refresh. These include SLDRAM [4M=18 SLDRAM CONS400.P65xe2x80x94Rev. Sep. 22, 1997, 400 Mb/s/pin SLDRAM SLD4M18DR400 4M=18 SLDRAM Data Sheet, SLDRAM Consortium] and Rambus DRAM (RDRAM). [Direct Rambus Technology Disclosure, Oct. 15, 1997, Rambus Inc.] All of the above-described command codes are generated by the external device, and must be communicated to the memory device, thereby complicating the interface to the semiconductor memory. The interface then becomes incompatible with the interface of a simpler device, such as an SPAM.
Other conventional DRAM refresh schemes incorporate a dedicated refresh control signal. These schemes are exemplified by enhanced DRAM (EDRAM) [DM2202/2212 EDRAM, 1 Mbxc3x974 Enhanced Dynamic RAM, 1994, Ramtron International Corporation] and cache DRAM (CDRAM) [Dosaka et. al, U.S. Pat. No. 5,559,750]. In both the EDRAM and the CDRAM, a dedicated external refresh signal is used to initiate refresh operations. As noted with the external signals of the aforementioned devices, this additional external signal is incompatible with an SRAM and other simple interface devices.
Schemes for performing refresh operations during unused idle memory cycles of a DRAM are described in U.S. Pat. No. 6,078,547 entitled xe2x80x9cMethod And Structure For Controlling Operation Of A DRAM Arrayxe2x80x9d, U.S. Pat. No. 6,028,804 entitled xe2x80x9cMethod And Apparatus For 1-T SRAM Compatible Memoryxe2x80x9d, U.S. Pat. No. 5,999,474 entitled xe2x80x9cMethod And Apparatus For Complete Hiding Of The Refresh Of A Semiconductor Memoryxe2x80x9d, and U.S. Pat. No. 6,075,740 entitled xe2x80x9cMethod And Apparatus For Increasing The Time Available For Refresh For 1-T SRAM Compatible Devicesxe2x80x9d, all by the present inventor.
Accordingly, the present invention provides a memory system having a memory controller and one or more memory blocks that are commonly coupled to a system bus. Each memory block includes an array of memory cells that must be periodically refreshed to retain valid data. Each memory block also includes a refresh control circuit that refreshes the memory cells during idle cycles of the memory array.
The memory controller includes a refresh manager that monitors the number of idle cycles on the system bus during a refresh period, and forces one or more idle cycles on the system bus if the monitored number of idle cycles is less than a predetermined number of idle cycles during the refresh period. For example, in one embodiment, the refresh period for eight rows of memory cells is 20.48 microseconds. If the refresh manager detects fewer than eight idle cycles on the system bus during the 20.48 microsecond refresh period, then the refresh manager forces the appropriate number of idle cycles onto the system bus at the end of the refresh period. For example, if the refresh manager only detects six idle cycles on the system bus during the refresh period, then the refresh manager will force two additional idle cycles on the system bus at the end of the refresh period. As a result, eight idle cycles are provided on the system bus. Each of the memory blocks performs a pending refresh operation during an idle cycle on the system bus. As a result, the eight rows of memory cells are always refreshed within eight cycles of the end of the refresh period (or shorter). There is a relatively high probability that the refresh manager will not have to force any idle cycles at the end of the refresh period. Moreover, even if idle cycles must be forced, the maximum time required for these idle cycles represents a small fraction of the refresh period (e.g., 0.4 percent).
While idle cycles are being forced, the refresh manager asserts a control signal that informs accessing clients of the memory system that memory accesses must be deferred. After the idle cycles have been forced, the refresh manager de-asserts the control signal to inform the accessing clients that memory accesses can proceed.
In a particular embodiment, the refresh manager includes an idle cycle counter for counting the number of idle cycles on the system bus. When the number of idle cycles on the system bus is equal to the predetermined number of idle cycles, the idle cycle counter generates a FULL signal. A refresh counter is coupled to receive the FULL signal. If the refresh counter determines that the refresh period expires prior to receiving the FULL signal from the idle cycle counter, then the refresh counter asserts a control signal that forces idle cycles on the system bus. If the refresh counter receives the FULL signal prior to the expiration of the refresh period, the refresh counter is reset, thereby beginning a new refresh period.
Within each memory block, an access arbiter receives external access requests (which are initiated by the memory controller) and refresh requests (which are generated within the memory block). The access arbiter always grants priority to any pending external access request. The access arbiter will allow refresh requests to be granted only if there are no pending external access requests. As a result, the refresh requests do not impede the external access requests. The refresh operations are performed during naturally occurring idle cycles or during the forced idle cycles.
In another embodiment, the memory blocks are logically divided into two or more sets. In this embodiment, the refresh manager monitors the number of idle cycles occurring in each set of memory blocks during the refresh period. The refresh manager forces idle cycles on the system bus only if the number of idle cycles occurring in at least one set of memory blocks during the refresh period is less than the predetermined number of idle cycles.
In yet another embodiment of the present invention, the refresh manager is modified to force a predetermined number of idle cycles on the system bus after the refresh period has expired, regardless of the number of idle cycles occurring during the refresh period. For example, the refresh manager can force eight idle cycles at the end of each refresh period.
Another embodiment of the present invention includes the steps of (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks upon receiving the asserted timing signal; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.
A memory system for implementing this method includes a memory controller, one or more memory blocks and a system bus. The memory controller and each of the memory blocks are coupled to the system bus. Each memory block includes an array of memory cells that must be periodically refreshed, a refresh timer, a refresh detector, an access arbiter, and a logic circuit.
The refresh timer in each block periodically asserts a refresh timing signal. For example, the refresh timer may periodically assert a refresh timing signal every 256 clock cycles. The refresh detector in each block is coupled to receive the refresh timing signal. If the refresh timing signal is asserted, refresh detector will assert a refresh pending signal.
The access arbiter in each block is coupled to receive the refresh pending signal. If the refresh pending signal is asserted, and an idle cycle exists in the memory block, then access arbitrator will enable a refresh operation to be performed in the memory block. Upon enabling a refresh operation, the access arbiter asserts a refresh acknowledge signal.
Within each block, the refresh acknowledge signal is provided to the refresh detector. Each refresh detector receiving an asserted refresh acknowledge signal de-asserts the corresponding refresh pending signal.
Within each block, the logic circuit is coupled to receive the corresponding refresh pending and refresh timing signals. Each logic circuit that receives both an asserted refresh pending signal and an asserted refresh timing signal pulls down on a dedicated refresh line of the system bus. That is, each logic circuit that has not performed a refresh operation by the time the refresh timing signal is asserted pulls down on the refresh line. The signal on the refresh line is referred to as the refresh forcing signal.
The memory controller is coupled to receive the refresh forcing signal on the refresh line of the system bus. If the refresh forcing signal is pulled down to a logic low value, the memory controller forces an idle cycle on the system bus. This enables all of the memory blocks to be properly refreshed.
Another embodiment of the present invention includes a method of operating a memory system having a plurality of memory blocks. This method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks upon receiving the asserted timing signal; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted.
A memory system for implementing this method includes a memory controller, one or more memory blocks and a system bus. The memory controller and each of the memory blocks is coupled to the system bus. Each memory block includes an array of memory cells that must be periodically refreshed, a refresh timer, a refresh detector, an access arbiter, and a logic circuit.
In an alternate embodiment, a common refresh timer can be shared among the memory blocks. This arrangement is particularly suitable in an integrated environment where the entire memory system resides on the same silicon substrate. Furthermore the timing signal generated by the refresh timer can be arranged to propagate through a daisy-chain connecting serially to all the memory blocks. Such a scheme is described in detail in pending U.S. patent application Ser. No. 09/405,607 xe2x80x9cRead/Write Buffers For Complete Hiding Of The Refresh of A Semiconductor Memory And Method Of Operating Samexe2x80x9d by Wingyu Leung.
The refresh timer in each block periodically asserts a refresh timing signal. For example, the refresh timer may periodically assert a refresh timing signal every 256 clock cycles. The refresh detector in each block is coupled to receive the refresh timing signal. If the refresh timing signal is asserted, refresh detector will assert a refresh pending signal.
The access arbiter in each block is coupled to receive the refresh pending signal. If the refresh pending signal is asserted, and an idle cycle exists in the memory block, then access arbitrator will enable a refresh operation to be performed in the memory block. Upon enabling a refresh operation, the access arbiter asserts a refresh acknowledge signal.
Within each block, the refresh acknowledge signal is provided to the refresh detector. Each refresh detector receiving an asserted refresh acknowledge signal de-asserts the corresponding refresh pending signal.
Within each block, a logic circuit is coupled to receive the corresponding refresh pending signal. Each logic circuit that receives an asserted refresh pending signal pulls down on a dedicated refresh line of the system bus. That is, each logic circuit pulls down on the refresh line until a refresh operation is performed by the memory block. The signal on the refresh line is referred to as the refresh forcing signal.
The memory controller is coupled to receive the refresh forcing signal on the refresh line of the system bus. If the memory controller detects that the refresh line is continuously pulled down to a logic low level for a predetermined time period, then the memory controller forces an idle cycle on the system bus. This enables all of the memory blocks to be properly refreshed.
The present invention will be more fully understood in view of the following description and drawings.

Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory


An inkjet printer configured to print by ejecting ink based on print data, an inkjet head comprising a plurality of nozzles, the plurality of nozzles divided into a plurality of nozzle groups, each nozzle of a nozzle group configured to eject ink of a same color and type and a control device configured to control the inkjet head to print in a normal print mode and a low-temperature print mode.

An example of a liquid ejection device prints characters and/or images by ejecting liquid through one or more nozzles onto a recording medium. When ink temperature is low (e.g., a threshold dictated by the type of ink), ink may become highly viscous, thereby making it difficult to eject ink from the nozzles and resulting in an occurrence of ejection failure. Often, inkjet printers that have facsimile functionality receive facsimile data when atmospheric temperature is low, e.g., in the early morning, and perform printing upon receipt of the facsimile data under conditions where the ink temperature is still low. These low-temperature printing conditions can cause a failure in the printing of all ink dots in a printed result, thereby causing, for example, characters to become blurred printed information to become illegible.
In order to solve such printing problems, some known inkjet printers prohibit the reception of facsimile data and the recording operation performed by an inkjet head when it is determined that an ink temperature sensed by a temperature sensor is lower than or equal to a predetermined temperature (e.g., ambient and/or ink temperature). Thereafter, when the ink temperature rises above the predetermined ink temperature, the inkjet printer permits reception of the facsimile data and removes the prohibition of the recording operation performed by the inkjet head.
In yet another known inkjet printer, both the reception of facsimile data and the printing of facsimile data onto a recording medium may be prohibited when the ink temperature is low. Nevertheless, such a configuration may prevent printing from starting until the ink temperature rises to a predetermined temperature even when information received via facsimile communication is desired to be confirmed at once, for example, in the early morning. Thus, it may be impossible to confirm the information until printing is performed after the ink temperature rises at or above the predetermined temperature. The same problem may also occur in a printer that might not have a facsimile function. That is, even when it is desired to perform printing immediately from a personal computer ("PC"), printing may be prevented from starting until an ink temperature in the printer rises to a certain temperature.

Inkjet printer, liquid ejection device, and printing method


In accordance with the present invention, there is provided a method for sharing a secret value x among n participating network devices via an asynchronous network. The n participating network devices comprises t faulty devices and k sub-devices capable of reconstructing the secret value x, wherein t<n/3 and k<n. The secret value x being provided by a distributor. The method comprising of deriving by the distributor share values si and subshare values sij of the secret value x by applying a linear secret sharing scheme and deriving verification values gsij usable for verification of validity of the share values si and the subshare values sij; sending to each participating network device a share message comprising the corresponding subshare values sAi,siA, sBi,siB, sCi,siC; broadcasting a verification message comprising the verification values gsij; receiving by at least l participating network devices the verification message comprising the verification values gsij, wherein n−t≧l≧2t+1, and performing the following steps 1) to 4) for each recipient network device, 1) if a share message comprising subshare values sij is received, determining the validity of the subshare values sij in dependence on the verification values gsij and 2) broadcasting in the event of positive determination an agree message comprising an agree-value Y; 3) receiving l agree messages comprising the agree-values YA, YB, Yc; 4) in the event of l received agree messages, obtaining the share value si either from the share message sent by the distributor D or from subshare values sij received from participating network devices and determining the validity of the subshare values sij in dependence on the verification values gsij. In a second aspect of the present invention a method without broadcast is disclosed.

Secret sharing schemes protect the secrecy and integrity of information by distributing the information over n different locations. The information can only be recovered if one has access to a certain minimal number of locations. In particular, in a (k, n)-threshold scheme, k locations together can reconstruct the secret information, where k−1 locations cannot get any information about it.
In H. Krawczyk et al. "Proactive secret sharing or: How to cope with perpetual leakage" In Crypto '95, pages 339-352, Santa Barbara, 1995, a synchronous proactive secret sharing scheme is presented. Therein, the lifetime of the system is divided into short time periods only, such that it is plausible to assume that an adversary cannot break into more than k−1 locations during one time period. Further, the adversary is assumed to be transient, i.e. corrupted servers can be identified and rebooted, such that the adversary looses control over them, but still remembers the last state of the server. At the beginning of each time period, the system is refreshed such that the information, an adversary gathered in a previous period becomes obsolete. Refreshing the system involves the generation of new random shares of the old secret.
An asynchronous verifiable secret sharing system has been proposed by Ran Canetti and Tal Rabin, "Fast asynchronous Byzantine agreement with optimal resilience" in STOC 93, pages 42-51, New York, 1993, basing on ideas from Feldman and Micali, "An Optimal Probabilistic Protocol for Synchronous Byzantine Agreement", STOC 88, pages 148-161, New York 1988. This scheme does not use public key cryptography, but has a very high message complexity.
It is an object of the present invention to create a verifiable secret sharing scheme for a potentially asynchronous network capable of tolerating a maximum of t faulty devices, processors or parties. Partially asynchronous network in that sense means that the network can work either in synchronous or asynchronous mode, depending on the circumstances and the given assumptions.
It is a further object of this invention to provide a method to be operable among n processors or parties, where at most t<n/3 processors are faulty, and further where the sharing can be achieved in constant time with the number of messages being exchanged in the order of the square of n.
Glossary
The following are informal definitions to aid in the understanding of the description.
In Asynchronous Verifiable Secret Sharing (AVSS), a secret value x is shared by a dealer or distributor among n parties P1, . . . , Pn such that each coalition of k−1 parties can not compromise x, while any coalition of k or more parties can efficiently construct x. This is also called (k, n) sharing, indicating that k out of n parties are required to reconstruct the secret value x.
Group: A group in the cryptographic sense is an algebraic system (G,*) consisting of a set of elements or numbers and a group operation (*) with some specified properties, where (*) is associative, has a neutral element, and where every element in G has an inverse element.
The choice of the symbol (*) is arbitrary. In fact, the operation of most groups is denoted by either + or ·, and such groups are referred to as additive or multiplicative group, respectively.
For example, for any positive integer q, a set Zq consists of the integers 0, . . . , q−1, and it forms a group under the operation of addition modulo q. Moreover, the subset of Zq consisting of those integers relatively prime to a forms a group under multiplication modulo q, and is denoted Zq*. In particular, if p is prime, then Zq* consists of {1, . . . , p−1}, and is a group with p−1 elements.
Hash function: A hash function is a computationally efficient function mapping binary strings of arbitrary length to binary strings of some fixed length.
Hybrid Failures
The method for achieving Byzantine Agreement can distinguish between several different ways in which a network device can fail. This could for example be
Byzantine Failures BF: If a byzantine failure BF occurs, the adversary has taken full control over the corresponding machine. All secrets this machine has are handed over to the adversary, who now controls its entire behavior.
Crash Failures CF: A crash failure CF simply means that the corresponding machine stops working. This could happen anytime, i.e., even in the middle of a broadcast or while sending a message. It is assumed that there is no mechanism other parties can reliably detect such a crash.
Link Failures LF: A link failure LF occurs when not a party, but an interconnecting link becomes faulty. As the link has no access to authentication keys, it is easy to prevent it from modifying or inserting messages. A faulty link could however delete messages, and it might completely disconnect two parties.
Adversary Structure
An adversary structure T is a set of sets (coalitions) of parties whose corruption the system should tolerate. This generalizes a threshold scheme to be more flexible and adapt to environmental structures.

Method of verifiably sharing a secret in potentially asynchronous networks

International Business Machines Corporation


An arrangement for supplying fuel from a supply container to an internal combustion engine of a motor vehicle, has a supply tank having an interior with a separate chamber, a supply aggregate having a suction side connected with the supply tank and a pressure side connectable with the internal combustion engine, the supply aggregate receiving fuel from the separate chamber of the supply tank, a branching conduit connected with the pressure side of the supply aggregate and having a portion extending near a bottom of the supply tank, an ejector arranged in the portion of the branching conduit and having a pressure pipe opening in the chamber of the supply tank, and a check valve provided in the branching conduit upstream of the ejector as considered in a flow direction of fuel, and opening in the branching conduit after a predetermined limiting pressure has been exceeded.

The present invention relates to an arrangement for supplying fuel from a supply tank to an internal combustion engine of a motor vehicle.
More particularly, it relates to an arrangement of the above mentioned type which has a supply aggregate connected at a suction side with a supply tank and at a pressure side with an internal combustion engine, and also branching conduits with a portion accommodating an ejector.
Supply arrangements of the above mentioned general type are known in the art. In the known arrangement the ejector is used for sufficient filling of a supply cup in which the supplying aggregate is arranged and for supplying the fuel from it to the internal combustion engine. Thereby even with a relatively empty fuel tank of the supply aggregate a fuel supply is provided, which guarantees that long increases can be overcome without problems. A further objective which can be solved with an .ejector is that the fuel contained in a two-chamber supply tank is available and is supplied by the ejector into the chamber from which the supply aggregate aspirates the fuel.
However, during starts of the internal combustion engine when only a relatively low voltage is provided in the drive motor of the supply aggregate and thereby a substantially reduced supply power of the aggregate takes place, a certain fuel quantity flows through the ejector in dependence on the nozzle diameter without producing in the gasoline injection system a pressure which is sufficient for the start. With low feed flow consumption and high system pressure a relatively small feed nozzle diameter is required. It however must be produced with narrow tolerances and is prone to dirtying in these conditions. The feed nozzle diameter can b made greater than approximately 0.4 mm. However, the above mentioned disadvantages during starts of the internal combustion engine are especially pronounced.
The required feed flow for a predetermined suction flow consumption corresponding generally to at least the maximum motor consumption, is substantially inversely proportional to the feeding pressure. With the advantageous branching at the pressure side of the supply system the feed pressure is substantially identical to the system pressure of the injection device of the internal combustion engine.

Arrangement for supplying fuel from supply tank to internal combustion engine of motor vehicle


An inkjet head includes a common ink puddle section, a nozzle plate having a plurality of nozzle orifices, an ink flow channel substrate having grooves communicating from the common ink puddle section to the nozzle orifices, and being formed alternatively in front and back surfaces of the ink flow channel substrate, to end sections of the grooves the nozzle plate being fixed, a chamber plate being stacked on the ink flow channel substrate, and having pressure generation chambers corresponding to the nozzle orifices, a diaphragm stacking on the chamber plate opposite from the ink flow channel substrate, a pressure generator provided on the diaphragm for the respective pressure generation chambers to generate a change in an internal pressure. Preferably, a volumetric capacity of the pressure generation chambers is changed in accordance with a change in the pressure, to eject an ink droplet from the nozzle orifice.

1. Field of the Invention
The invention relates to an inkjet head, and more specifically, to mounting and configuration of an inkjet head nozzle used for the inkjet head.
2. Background Art
In association with proliferation of personal computers and progress in graphic processing programs, an output of a hard copy having a high image quality as well as an output of a character have come to be required in connection with inkjet printing. In the field of printing of a signboard or a large-sized poster, many on-demand print requests are issued. For these reasons, an on-demand inkjet recording apparatus has been frequently used.
An inkjet head used in the on-demand inkjet recording apparatus is roughly divided into three types. Namely, a first type of inkjet head is a so-called thermal jet inkjet head which is equipped with a heater for momentarily vaporizing ink disposed at the extremity of a nozzle, thereby producing and ejecting an ink droplet by means of expansion pressure derived from vaporization. A second type of inkjet head is an inkjet head utilizing shear-mode deformation of a piezoelectric element, wherein a container for forming an ink puddle section is equipped with a piezoelectric element which becomes deformed in accordance with a signal, and wherein an ink droplet is ejected by means of pressure derived from deformation. A third type of inkjet head is an inkjet head where in a piezoelectric element is disposed so as to oppose a pressure generation chamber formed from an ink puddle section, and an ink droplet is ejected by inducing dynamic pressure in the pressure generation chamber by means of contraction and extraction of the piezoelectric element. Electrostatic absorption is utilized in place of a piezoelectric element.
In the on-demand inkjet head of the third type, a plurality of nozzle orifices are arranged in a row on a chamber plate, and a plurality of plates are stacked to constitute an ink chamber. A piezoelectric element is mounted so as to oppose the ink chamber, and an ink droplet is ejected by utilization of deformation of the piezoelectric element (see e.g., JP-A-6-8422).
In the case of the inkjet head, when a nozzle packaging density, that is, a pitch between nozzles, has become small, the pitch between the ink chambers eventually becomes smaller, along with the piezoelectric element. To prevent such a reduction in pitch or size, nozzles are arranged in a plurality of rows within a head, and nozzles of the respective rows are offset from each other, thereby attempting to increase a print density which can be achieved by one scanning operation (see, e.g., JP-A-2000-289233). However, a plurality of rows of nozzles are provided in one plate, and hence piezoelectric transducers must also be formed for respective rows of nozzles so as to oppose the nozzles, because the piezoelectric transducers oppose nozzles when packaged.
FIG. 10 shows another related-art example of means for increasing the packaging density of nozzles. FIG. 10 is a schematic plan view showing a state in which a nozzle plate 101 has a plurality of nozzle orifices 100, a state of a chamber plate 103 in which the pressure generation chambers 102 are alternately arranged thereon in a staggered arrangement with respect to the nozzle orifices 100 arranged on the nozzle plate 101, and a state in which a piezoelectric element 150 divided in a comb-shaped pattern are fixed so as to oppose a pressure generation chamber 102 sealed with a diaphragm 104. In the case of such a configuration, since the pressure generation chambers 102 are arranged in a staggered arrangement, the corresponding piezoelectric elements 15 are also arranged in a staggered arrangement. Specifically, two groups of piezoelectric elements located very close to each other must be inserted and fixed with superior accuracy. Therefore, there arises a problem of poor ease of assembly.
In some inkjet heads, a silicon monocrystal substrate is taken as a constituent member, and nozzles formed in one surface of the silicon monocrystal substrate and those formed in the other surface are arranged in a staggered pattern within a single plane made by slicing a predetermined position on the silicon monocrystal substrate (see, e.g., JP-A-6-8449). In this case, the nozzle orifices, the pressure chambers, and restrictors are formed simultaneously in the silicon monocrystal substrate. Hence, the nozzle orifices formed in both surfaces of the substrate must assume a staggered arrangement.

Inkjet head with high density nozzle packing


A suspension system for towed vehicles automatically adjusts for different payloads and road conditions without the need for manual shims used in prior art suspensions. automatically adjusts a mechanical bias on the vehicle to keep the suspension within a preferred ride height range. A hydraulic cylinder between the frames of the towing and the towed vehicles provides a mechanical biasing force to the towed vehicle. A sensor measures the ride height and causes the hydraulic cylinder to retract or extend according to the bias needed to maintain the suspension in the preferred ride height range.

Vehicle suspension systems are important for both maintaining vehicle control and for isolating a vehicle's contents from bumps and vibrations caused by imperfections in the road. Typical suspension systems may utilize one or more of springs, shock absorbers (or dampers), hydraulic cylinders and air bags.
Isolating the vehicle's contents from bumps and vibrations caused by road imperfections allows the vehicle to ride relatively undisturbed. Suspension systems are designed to absorb the energy generated when the vehicle rides over unevenness on the road and to dissipate the energy without causing undue vertical movement of the vehicle body.
A proper suspension system also assists in maintaining vehicle control by minimizing weight transfer of the vehicle from side to side and from front to back that occurs during movement, braking and acceleration. This allows all of the wheels to better maintain contact with the ground, and maintains the vehicle's ability to steer, brake, and accelerate.
The present invention relates to towed vehicles used to carry a payload such as trailers, as well as to their load-sharing accessory vehicles known as tag dollies and boosters. For simplicity, the term "dollies" will be used to refer collectively to all of such accessory vehicles.
An effective dolly suspension system may help to prevent "bridging", a condition that occurs when the wheels from one or more axles unload, or lose contact with the ground, typically caused by uneven road conditions. As a result, the entire load is borne by the remaining axles which may damage the dolly, and cause reduced brake performance or even loss of control if the axles are self-steering.
Air bag suspension systems have an "air bag performance zone" defined by the manufacturer. The air bag performance zone determines the preferred range of ride heights, defined as the distance between axle and the frame. It is important that the suspension system maintain a ride height within this preferred ride height range in order to provide the most effective suspension and to ensure optimal performance and operating life for the air bags. One prior art suspension system for a dolly includes both a hydraulic bias mechanism (comprising one or more hydraulic cylinders) and an air suspension mechanism (comprising one or more air bags). In normal operation, the hydraulic cylinders are fully extended thereby acting effectively as struts between the towing vehicle and the dolly to bias the dolly frame toward the ground. The air bags provide the suspension performance. In the event that the air bags threaten to collapse, the cylinders are immediately retracted to reduce the downward bias of the dolly and to relieve the air bags. The operator of the dolly manually adjusts the suspension system upon loading or unloading cargo so that the ride height falls within the preferred range by removing or inserting metal shims in the hydraulic bias system so as to increase or decrease the downward bias. The manual removal and insertion of shims according to the payload is time-consuming.
The distribution of the load can also be affected by a significant change in road conditions, such as an abrupt change in road grade or cornering an elevated curve. This change in distribution can affect the ride height and create handling problems.
When the dolly is traveling, variations on the surface of the road may affect the ride height as well. For example, if the dolly encounters a bump on the road, the wheel (and axle) will experience upward vertical acceleration and rise, resulting in the compression of the air bags and instantaneous variations in the ride height that are normally compensated for by the air suspension system. If the bumps on the road are extreme, the air suspension system may be driven outside the air bag performance zone, bottom out and cease to provide suspension. This condition has a negative impact on the handling of the dolly and may lead to damage to the suspension and to the dolly. In prior art suspension systems that use a hydraulic bias system to achieve a nominal ride height, when the air suspension mechanism has collapsed, the hydraulic bias mechanism is activated on an emergency basis to decrease the load on the air suspension. This usually results in a violent jolt to the dolly, which is uncomfortable and potentially damaging to the cargo.
It is therefore an object of the present invention to provide a suspension system that overcomes the aforementioned limitations.
The particular objects of the invention will be better understood by reference to the detailed description of the preferred embodiment that follows.


A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the memory cells in the same column, and serial access control means which serially accesses a plurality of memory cells in a given column of the memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cells storing information, and then sequentially rewrites the bits of information into a different memory cell unused for storing valid data, in the same column where the memory cell exists.

1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) with an array of cascade dynamic memory cells capable of storing bits of information in bits.
2. Description of the Related Art
DRAM cells now in practical use are made up of a transfer gate MOS (Metal-Oxide-Semiconductor) transistor connected to a word line and a bit line and an information-storing capacitor connected to this transistor.
In connection with this, the applicant of this invention has proposed cascade gate semiconductor memory cells, for example, as shown in FIGS. 1 and 2, in U.S. Pat. application Ser. No. 687,687.
The DRAM cell of FIG. 1 contains cascade-connected MOS transistors Q1 to Q4 and information-storing capacitors C1 to C4 one end of which is connected to one end of each of transistors Q1 to Q4. By performing on/off control of transistors Q1 to Q4 in a specified sequence, stored information is sequentially read to the node N1 from capacitors C1 to C4, starting with capacitor C1 nearest one end of the cascade connection (read/write node N1). It is also possible to sequentially write information at node N1 into capacitors C4 to C1, beginning with C4 farthest away from node N1.
The DRAM cell of FIG. 2 is such that an additional MOS transistor Q5 is connected between one end of DRAM cell transistor Q4 of FIG. 1 and a second node N2. By performing on/off control of transistors Q1 to Q5 in a specified sequence, stored information is sequentially read to the node N1 from capacitors C1 to C4, starting with capacitor C1 nearest the node N1. It is also possible to sequentially write information at node N2 into capacitors C1 to C4, beginning with C1 nearest node N1.
Cascade-gate memory cells as shown in FIGS. 1 and 2 can store bits of information in bits. An array using these cells requires only one connection between a memory cell and a bit line for every specified number of bits, which results in much higher packing density than that of a conventional DRAM with an array of one-transistor one-capacitor cells, thereby reducing the price per bit remarkably.
With a DRAM with the aforementioned cascade-gate memory cells, because the information stored in the cell is lost as a result of destructive reading, it is always necessary to rewrite the original information in it. Since the reading and writing order for the capacitors in one memory cell is determined, it is impossible to rewrite the information into a given capacitor immediately after it has been read from that capacitor. That is, rewriting into a given capacitor from which the information has been read is impossible until the succeeding capacitors within the same cell have been read from.
For this reason, when a DRAM is constructed using an array of aforementioned cascade-gate memory cells, a means is necessary which can sequentially rewrite (or write) the information after multiple bits have been read from the memory cells in time sequence.
In this connection, the applicant of this invention has proposed, in U.S. Pat. application Ser. No. 721,255, a semiconductor memory device that contains a storing means for temporarily storing bits of information read in time sequence from the memory cells and is able to sequentially rewrite (or write) the bits of information after the reading has finished.
It may be possible to construct a DRAM where a group of memory cells in a column of an array of cascade memory cells is accessed serially, making use of the ability of the above-mentioned cascade memory cells to be accessed serially. This construction, however, requires improvements in the method of rewriting the information read in time sequence from the cascade memory cells.


A method and device for bending the end tabs of blanks for producing rigid flip-top cigarette packets. The blanks are loaded on a conveyor and are fed continuously along a path with the end tabs slidably engaged in a helical slit, which is in part defined by facing helical surfaces of first and second helical guide elements. The blanks wind over an arc of 180.degree. for bending the end tabs in a U and enabling the bent end tabs to be fed between two pressure rollers of a stabilizing unit.

The present invention relates to a method of bending the end tabs of blanks for producing rigid flip-top cigarette packets.
Rigid flip-top cigarette packets are produced from substantially elongated rectangular blanks, each comprising an end tab with a transverse bend line. On the end tab, the bend line defines an inner portion constituting the front wall of the flip-top lid of the packet; and an outer portion constituting a stiffening tab for the front wall, when bent in a U about the bend line and on to the inner surface of the front wall.
On known packing machines, the stiffening tab is normally bent in a U as described above by means of devices comprising a conveyor, on to which the blanks are fed successively, with the end tab projecting from the lateral edge of the conveyor, and fed in steps transversely, i.e. in a direction parallel to the bend line, through a fixed bending station, where they are arrested for bending the stiffening tab by means of a movable bending member.
Known methods of the type described above present several drawbacks, all of which are mainly caused by using a step conveyor. To avoid penalizing the output capacity of the packing machine, the step conveyor must be arrested for as short a time as possible, which means maximizing the speed of the operations performed on the packets and/or blanks between successive steps of the conveyor. Clearly, however, in the case of bending a tab in a U by means of a movable bending member, such high speed operation invariably involves the risk of puncturing or tearing the tab.
To overcome the above drawback, highly complex bending members have been devised for minimizing impact between the tab and the bending member. These, however, are extremely expensive and of such complex mechanical design as to be invariably unreliable.

Method and device for bending the end tabs of blanks for producing rigid flip-top cigarette packets


A pair of eyeglasses includes a lens, two engaging blocks each having an end engaged with a side of the lens, and two clamping members. A ring is mounted to the other end of each engaging block. An end of each clamping member is mounted to a cap visor. The other end of each clamping member includes an engaging hole. An annular toothed wall extends from a bottom wall defining the engaging hole. An annular groove is defined between an outer face of the annular toothed wall and an inner circumference defining the engaging hole. The rings are engaged in the engaging holes the clamping members, with teeth on the annular toothed wall engaged with teeth on the ring. The annular toothed wall expands into the annular groove when the teeth of the rings press against the teeth of the annular toothed wall during pivotal movement of the rings.

1. Field of the Invention
The present invention relates to a pair of eyeglasses. More particularly, the present invention relates to a pair of eyeglasses that can be attached to a visor of a cap.
2. Description of the Related Art
Eyeglasses and hats are often used for shielding from the sun when going out. Eyeglasses and hats are separate and thus must be carried separately. It is very inconvenient for a use wearing a pair of corrective eyeglasses to carry a pair of sunglasses.
Eyeglasses attachable to a visor of a cap have been proposed. A pair of eyeglasses of this type can be moved between an operative position for shielding from the sun and an inoperative position for clear vision.
FIGS. 7 and 8 of the drawings illustrate a pair of conventional eyeglasses attachable to a visor of a cap. The pair of eyeglasses includes a lens 1′, two engaging blocks 2′ (only one is shown) respectively on two sides of the lens 1′, and two clamping members 3′ (only one is shown). Each engaging block 2′ includes an end securely engaged with an associated side of the lens 1′. The other end of each engaging block 2′ includes a protrusion 21′ with a plurality of teeth 211′ on a circumference thereof. Each clamping member 3′ includes a first end that can be clamped to a side of a visor (not shown) of a cap (not shown). Each clamping member 3′ further includes a second end that has an engaging hole 31′ for receiving the protrusion 21′ of an associated engaging block 2′. A plurality of teeth 311′ are defined in an inner circumference defining the engaging hole 31′ and engage with the teeth 211′ of the protrusion 21′. The engaging block 2′ can be pivoted relative to the clamping member 3′ and then retained in place.
However, expansion of the circumferential wall defining the engaging hole 31′ is not easy such that a large force is required to turn the engaging block 2′, which is inconvenient to adjustment of the angular position of the lens 1′. Further, the teeth 211′ and 311′ wear out easily, leading to unreliable positioning of the engaging block 2′ relative to the clamping member 3′.