A recovery system for a hot fill system. The hot fill system has a first diverter for diverting the flow of overflow product from a product tank to a filler feed tank. The system also has a source of compressed air for clearing the line between the overflow tank and the product tank. The system also has a source of water for clearing the line from the product tank to the filler feed tank. The system also has a heater for reheating overflow product with a recirculation/recovery loop. The system allows for the recovery of product which would have been lost during a hot fill product run.

1. Field of the Invention
The present invention relates to hot fill processing systems for liquid food products. More specifically, the present invention relates to a product recovery system for a hot fill pasteurization system.
2. Description of the Related Art
Liquid food products are packaged in a variety of containers such as polyethylene terephthlate ("PET") bottles, blow molded high density polyethylene ("HDPE") jugs, gable-top cartons, glass bottles, aluminum cans, pouches and parallelepiped containers (e.g. the TETRA BRIK.RTM. package). Liquid food products include fruit juices, sports drinks, tea, milk, soft drinks, and the like. It has become commonplace to have more shelf stable products and extended shelf life ("ESL") products. A shelf stable product is defined as a product that may be stored without refrigeration for up to three months while an ESL product is defined as one that may be stored with refrigeration for up to four months. The popularity of these products with retailers is due to the extended amount of time that the product may be "marketed" to the consuming public without spoilage.
In order to obtain ESL and shelf stable products, the liquid food product most be processed in a manner that renders the product essentially free of micro-organisms and microbial growth. Several methods are utilized to process products in this manner. One such process is a hot fill pasteurization process.
Basically, a hot fill pasteurization process is a continuous flow through processing system which heat treats the product to kill micro-organisms . The product is then directed to a container filling machine which fills the product into a container at an elevated temperature (hot fill). The heat treatment and the hot fill render the product shelf stable.
In a typical hot fill pasteurization system, a product such as fruit juice is pumped from an external storage tank to a primary balance tank as needed to maintain a constant level in the primary balance tank. The product is continually pumped from the primary balance tank through a product heater, then through a holding loop, then through a product cooler and to a filler feed tank. The heater typically uses hot water to heat to heat the product to an elevated temperature, usually 87.degree. C. to 119.degree. C. (190.degree. F. to 245.degree. F.). The holding loop maintains the product at this elevated temperature for a predetermined time period necessary to kill the micro-organisms. The predetermined time period will vary depending on the product. The cooler uses cold water to cool the temperature of the product to a hot fill temperature. For example, for a PET bottle, the hot fill temperature is 85.degree. C. (185.degree. F.) which is just below the softening temperature of the PET bottle. Hot filling containers maximizes shelf life by killing organisms on the container surface, and also assists in vacuum sealing of the container.
At the filler feed tank, the product is pumped to a filler where most of the product is filled into containers. A portion of the product overflows from the filler into a filler overflow tank or return tank. The overflow product from the filler is approximately 5% to 25% of the total product fed to the filler when the filler is filling containers and 100% when containers are not being conveyed through the filler. The latter scenario occurs during priming of the processing system or during shut-down of the system. Overflow product from the filler overflow tank is pumped to the main balance tank where it joins fresh product feeding into the system. In this manner the overflow product is processed through the entire cycle again.
Once a product batch is completed, the product remaining in the system is rendered excess product. This remaining product is either in the overflow tank, in the primary balance tank or in the sterilization portion of the system (the heater and cooler). Current practice is to dispose of the excess product or to transfer it to a separate tank where the products value is greatly diminished. Depending on the product and processing system, this excess product could account for 25% to 100% of the system hold-up volume.


A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

The invention relates to semiconductor technology, and in particular to a lateral bipolar transistor and the process for making same.
Recently respectable bipolar transistors have been formed using a CMOS (complementary metal-oxide semiconductor) transistor in a typical CMOS process. These bipolar transistors are also referred to as lateral bipolar transistors and are reported to have a threshold frequency (t) as high as 3.7 Ghz and a Beta as high as 1000. This alternate method of forming a bipolar transistor has some strong advantages. The process is extremely simple compared to a typical BiCMOS process that uses complicated and expensive process flows costing 30-40% more than a typical CMOS flow. The use of a CMOS flow to create a lateral bipolar transistor adds negligible cost to a current CMOS process and provides a capable bipolar transistor.
The lateral bipolar transistor is fabricated using a typical lightly doped drain (LDD) MOS transistor. An NPN device is formed from an NMOS transistor and a PNP device is formed from a PMOS transistor. The base width of the lateral bipolar transistor is determined by and is usually equal to the MOS channel length. As MOS devices have shrunk the channel lengths have approached the base width of a bipolar making the lateral bipolar transistor possible.
In one variation a base implant is added to the process steps to balance the bipolar and MOS modes of operation. In addition the typical lateral bipolar transistor employs a base-gate contact for providing an electrical connection between the base and gate of the lateral bipolar transistors. Since the base is typically fabricated in the well, the gate depletes the base while the substrate contact controls the base voltage.
The Inventors have discovered that the lateral bipolar transistors, fabricated according to the structures described above, have a reduction in gain at high currents or at high bias voltages. Thus, it would be desirable to have a CMOS-based bipolar transistor having improved bipolar performance during high current or high bias voltage conditions.
One exemplary embodiment of the invention is a substantially concentric lateral bipolar transistor and the method of forming same. The lateral bipolar transistor includes a base region disposed about a periphery of an emitter region and a collector region disposed about a periphery of the base region. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. The invention includes a metal oxide semiconductor inversion region formed in the substrate and a retrograde well formed below the inversion region.
In a further exemplary embodiment a bipolar transistor is formed according to the following method. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction.
In a further exemplary embodiment the invention is a lateral bipolar transistor having a decreased base width. The decreased base region is created by implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.


Provided are methods of depositing hafnium or zirconium containing metal alloy films. Certain methods comprise sequentially exposing a substrate surface to alternating flows of an organometallic precursor and a reductant comprising M(BH4)4 to produce a metal alloy film on the substrate surface, wherein M is selected from hafnium and zirconium, and the organometallic precursor contains a metal N. Gate stacks are described comprising a copper barrier layer comprising boron, a first metal M selected from Hf and Zr, and a second metal N selected from tantalum, tungsten, copper, ruthenium, rhodium, cobalt and nickel; and a copper layer overlying the copper barrier seed layer.

Deposition of thin films on a substrate surface is an important process in a variety of industries including semiconductor processing, diffusion barrier coatings and dielectrics for magnetic read/write heads. In the semiconductor industry, in particular, miniaturization requires a level control of thin film deposition to produce conformal coatings on high aspect ratio structures. One method for deposition of thin films with such control and conformal deposition is atomic layer deposition (ALD). Most ALD processes are based on binary reaction sequences. Each of the two surface reactions occurs sequentially. Because the surface reactions are sequential, the two gas phase reactants are not in contact, and possible gas phase reactions that may form and deposit particles are limited. The typical approach to further ALD development has been to determine whether or not currently available chemistries are suitable for ALD.
One useful application of ALD processes relates the deposition of metal and metal alloy films. One such method of the ALD of a metal alloy involves introducing an organometallic precursor into an ALD system where it partially reacts with the surface of the wafer. Then, a reducing agent like hydrazine in introduced to reduce the partially reacted precursor to a metal. Accordingly, there is a continuing need for new deposition chemistries that are commercially viable.

Atomic layer deposition of hafnium or zirconium alloy films


The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a stacked semiconductor device package. The methods and apparatus include providing a first semiconductor device with an adhesive flow control dam located on an upper surface thereof. The dam is positioned between electrical contacts and a substrate attach site on the upper surface of the first semiconductor device. The dam is rendered of a sufficient height and shape to block applied adhesive from flowing over the electrical contacts of the first semiconductor device when a second substrate is mounted onto the upper surface of the first semiconductor device. The semiconductor device package may be encapsulated with the dam in place or with the dam removed. The adhesive flow control dam thus protects the electrical contacts of the first semiconductor device from contamination by excess adhesive, which can result in unusable electrical contacts.

Field of the Invention
This invention relates generally to integrated circuit semiconductor device assemblies. More particularly, the present invention relates to stacked arrangements for semiconductor dice in semiconductor device assemblies.
Semiconductor devices are increasingly used in portable electronic applications, necessitating the development of smaller, higher-performance components. In conventional semiconductor manufacturing processes, a multitude of integrated circuit (IC) dice or semiconductor dice is typically fabricated at one time onto a wafer comprising a semiconducting substrate (e.g., silicon or gallium arsenide) through methods well known in the art. These semiconductor dice are then incorporated, in turn, into a system by mounting them on a carrier substrate, for example, a printed circuit board, to interconnect with the rest of the elements of the system, many of which are also other semiconductor dice.
In recent years, semiconductor manufacturing technology has steadily progressed, resulting in ever-increasing numbers of circuit elements placed on a single semiconductor die. Semiconductor wafers are now subjected to thinning processes, resulting in the removal of nearly all excess silicon from individual semiconductor dice. To further decrease the size of the overall packaged system, printed circuit boards and other component supporting substrates are made as small as practicable. For still further increases in electronics density, recent innovations have turned to new ways to package semiconductor dice. One such innovation involves vertically stacking a plurality of horizontally disposed semiconductor dice to form a dense electronic package. By using such stacking arrangements, multiple semiconductor dice can be attached to the system using the footprint area of a single semiconductor die. The resulting increases in density allow for faster signal propagation while providing lower overall device weight. Additionally, these "chip-on-chip or die-on-die" arrangements can often be fabricated faster and more cheaply than by designing new integrated circuitry for substrates.
The lack of available "real estate" on smaller circuit boards makes the stacking of semiconductor dice particularly desirable. One type of stacking arrangement, wherein several bare semiconductor dice used for the same or different functions are mounted in a common package, is known as a multi-chip module (MCM). MCMs generally contain a plurality of semiconductor dice in a dense arrangement where they are packaged together in a supporting substrate that can be hermetically sealed. Although prior art MCMs typically have a number of individual semiconductor dice mounted within the package in a laterally adjacent manner, the vertical stacking of semiconductor dice is increasingly gaining acceptance.
Many types of semiconductor dice can be used to form MCM chip-on-chip or die-on-die stacks, including dynamic random access memory (DRAM), static random access memory (SRAM) and FLASH memory chips, as well as semiconductor dice having other types of functions such as analog-to-digital convertor (ADC) semiconductor dice, microprocessors, and field programmable gate arrays (FPGAs). Typically, the stacked semiconductor dice have electrical contacts which are coupled in common or in parallel to contacts on the substrate board.
In early MCM stacking arrangements, single stacks of semiconductor dice were generally made using semiconductor dice having substantially equal dimensions. For example, in U.S. Pat. No. 5,323,060, assigned to the assignee of the present application, a plurality of identical, vertically stacked semiconductor dice is disclosed with a relatively thick adhesive layer interposed therebetween. The active circuitry of the horizontally disposed semiconductor dice is shown facing upwardly, with wirebonds from each semiconductor die extending downwardly from the active surface to contact pads onto a multi-chip module substrate.
In the case of memory semiconductor dice, vertical stacking proves particularly advantageous since a plurality of semiconductor dice could be used to multiply the amount of memory available. Illustrative of the prior state of the art in this regard is "Laminated Memory: A new 3-Dimensional Packaging Technology for MCM," Proceedings of 1994 IEEE Multi-Chip Module Conference, pp. 58–63.
More recently, single stacks have been made comprised of semiconductor dice of different sizes and/or functions directly attached to one another. Generally, one or more semiconductor dice are bonded on top of a larger semiconductor die, although larger semiconductor dice have been placed on smaller semiconductor dice using various ball grid array connections and various interposers as shown in U.S. Pat. Nos. 5,977,640 and 5,790,384, respectively.
Numerous packaging alternatives for stacked dice are found in the art. In U.S. Pat. No. 5,777,345, an integrated circuit package is disclosed wherein a first semiconductor die (a microprocessor) is attached to a die paddle of a lead frame, and a second smaller semiconductor die (a memory chip) is directly attached to the upwardly facing active surface of the first semiconductor die. The bonding pads of the semiconductor dice are shown to be connected to each other, and to the lead frame, by a wire bonding process.
U.S. Pat. No. 5,998,864 discloses horizontally disposed bare semiconductor dice stacked atop one another in offset fashion such that an edge portion of each semiconductor die is exposed. On the edge portions of each semiconductor die are terminals (bond pads) for interconnection of the semiconductor dice to an interconnection substrate.
U.S. Pat. No. 6,005,778 shows semiconductor die stacking arrangements wherein a planar silicon spacer with a conductive surface and upwardly facing bond pads is mounted between two semiconductor dice on a substrate carrier. The planar conductive spacer is shown with two configurations. In a first configuration, the intermediately disposed spacer has a two-tiered portion at its lateral edges, with bond pads exposed on the lower of the two tiers. The spacer is further provided with lesser horizontal dimensions than the first semiconductor die, such that the two lateral edges of the first semiconductor die, containing bond pads for wire bonding to the substrate, remain exposed after the spacer is adhesively affixed to the first semiconductor die. In a second embodiment, the planar spacer has a larger footprint than the horizontally disposed semiconductor dice used in the assembly. The spacer is placed intermediate to the two smaller semiconductor dice such that lateral edge upper surface areas of the spacer, containing bond pads and wire bonds, extend beyond the footprints of both semiconductor dice. The second semiconductor die, also containing wire bonds on its upper surface lateral edges, is bonded to the spacer by an adhesive layer, leaving the bonding pads and wire bonds of the spacer exposed.
In these types of stacked semiconductor die arrangements, the semiconductor dice are typically bonded to each other, or to intermediately disposed spacers/interposers, by means of an adhesive layer. Typically, bare semiconductor dice are attached to such substrates using organic-based adhesives. The adhesive layer is typically dispensed automatically by screen printing, by a stamping device, or by a needle or syringe, in a non-cured state (soft phase), and is deposited in a predetermined area designated for the mounting of the semiconductor die (i.e., the die attach area). Meanwhile, the semiconductor die to be mounted is then typically picked up and held by an automated vacuum mechanism, or other apparatus, of a die bonding machine. The semiconductor die is then positioned over the center of the die attach area and is pressed into the previously deposited adhesive, ideally forming a uniform layer of adhesive under the semiconductor die. Usually, the adhesive layer is thereafter brought to its cured phase through exposure to elevated temperatures for a specified time period.
In many adhesive compositions, the carrier material, which provides the adhesion and mechanical strength in the bond line, is a polyimide or an epoxy resin. The carrier can be filled with metal particles in the event electrical and thermal conductivity is required. Alternatively, the carrier can be filled with nonmetallic particles, such as alumina, if the final bond is to act as an insulator.
One problem associated with the application of die attach adhesives is that an amount of a particular adhesive must be satisfactorily dispensed in a particular thickness and over a particular area which will provide sufficient bond integrity for the application while simultaneously being free from voids. Voids are a problem for several reasons. First, if a void appears directly under an active part of a power circuit, the junction temperature may rise significantly since there is no material available to pull away the heat. Second, and more obviously, voids can affect the quality and mechanical strength of the die attach itself. Thus, the distribution of voids across the adhesive bonding layer is important in determining the effects which they will have. Small, random voids have only a modest effect on the thermal performance and mechanical integrity of the attach. Large, contiguous voids, however, can be catastrophic to both thermal and mechanical performance. Voids can also serve as sites for moisture to collect during storage. This is especially problematic in plastic packages since this moisture can spread to critical interfaces and cause delaminations and package cracking. Care must be taken, therefore, to ensure a sufficient amount of a properly viscous adhesive is applied to the die attach site so that void formation is minimized.
A related problem is that the adhesive, when dispensed, may overflow the site for semiconductor die or spacer/interposer attachment, or the adhesive may be squeezed out too far when the semiconductor die or spacer/interposer to be mounted is pressed into it. In the situation of vertically stacked semiconductor dice, this overflow or excess of adhesive can lead to the contamination of nearby bond pads, consequently interfering with subsequent wire bond operations, or even resulting in the loss of the function of the semiconductor die.
An associated phenomenon pertains to the use of conductive silver-filled epoxies for the bonding of silicon semiconductor dice, a well-established procedure in the microelectronics industry. One of the problems that has plagued the industry in the past is the separation or "bleeding out" of the resin vehicle from the epoxy. In some cases, this resin bleed is severe enough to interfere with subsequent wire bonding and lid sealing operations by disadvantageously coating the surfaces with a thin film of the resin material.
The rheology (also referred to as viscosity) of adhesives is therefore a property which is critical to proper die attach processes. Viscosity can be a difficult property to control, and may be affected by even small changes in the ambient temperature. Different application methods for adhesive also have different viscosity ranges. For example, viscosity ranges typical for dispensing are from about 20,000 to about 60,000 centipoise (cps), from about 8,000 to about 20,000 cps for stamping, and from about 30,000 to about 100,000 cps for screen printing.
Therefore, when attaching vertically stacked semiconductor dice, it would be advantageous to develop a method and assembly for preventing adhesive overflow which can potentially lead to bond pad contamination. Such a method and assembly should ideally be simple, inexpensive, and compatible with widely practiced means of fabricating stacked semiconductor die package assemblies. Additionally advantageous would be a method which allows for relaxed requirements for die attach materials and process controls.

Plurality of semiconductor die in an assembly


A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.

1. Field of the Invention
The present invention relates to a sequential semiconductor device tester, and in particular to a sequential semiconductor device tester wherein a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.
2. Description of the Related Art
A tester for testing a semiconductor device tests whether the semiconductor device is defective. The tester for testing the semiconductor device is designed and developed according to a development state of a memory device, a DRAM in particular which takes up most of the memory devices since the tester for testing the semiconductor device is mostly used for testing the memory devices.
The development of the DRAM is progressing from an EDO (Extended Data Output) DRAM, SDRAM (Synchronous DRAM), Rambus DRAM to DDR (Double Data Rate) DRAM.
In order to test the DRAM, a high speed and a high accuracy are required for the tester so as to correspond to a high speed DRAM. In addition, as a capacity of the memory is increased, a time required for testing the DRAM also increases. Therefore, a testing speed is also required to be increased. Moreover, a cost for testing the memory should be reduced by embodying a miniaturized and economical tester.
Of the tester for testing the semiconductor device, the memory tester in particular is typically used for testing and verifying a memory component or a memory module in a form of a SIMM or DIMM. The tester detects a functional defect of the memory module or the memory component prior to an installation thereof in a real computer system.
The tester is classified into a hardware semiconductor device tester and a software diagnostic program executed in a PC environment. However, since the software diagnostic program diagnoses a state of the memory when the memory module or the memory component is installed in the real computer, the hardware semiconductor device tester is mainly used during a semiconductor memory manufacturing process.
The tester may be classified as a high-end tester referred to as an ATE (Automatic Test Equipment), a medium range memory tester and a low-end memory tester.
The ATE which is the high-end tester is typically used in order to carry out a test process of the memory device. The conventional ATE carries out tests such as a DC test for testing whether a DC parameter is suitable for a digital operation of a circuit, a transmission delay time of signals, and an AC margin related to a set-up time and a hold time. The ATE also generates a test pattern and a timing for the test. However, a manufacturing cost of the ATE is high since the ATE is manufactured using a dedicated equipment such as a main frame having a large size and a high price.
FIG. 1 is a block diagram illustrating a conventional semiconductor device tester.
As shown in FIG. 1, the conventional tester comprises a pattern generator 110, a timing generator 120, a format controller 130, a driver 140, a comparator 150, and a test result storage 160. In addition to these components, the conventional tester may comprise a power supply controller for the DC test, a component for generating a clock signal, a component for supplying a power for an operation of a DUT (Device Under Test) 180, a component for relaying a test pattern data to the DUT 180 and receiving a test result from the DUT 180, a component for receiving a test pattern program from an outside, and a component for transmitting the test result to the outside. However, a description thereof is omitted.
The pattern generator 110 generates the test pattern data required for testing the DUT 180 based on the test pattern program. For instance, the test pattern program is written to include an instruction for carrying out various operations in order to carry out the test. The pattern generator 110 generates the test pattern data by receiving and interpreting the test pattern program from an external storage for instance. The test pattern data includes a data such as a command, address and a data inputted to the DUT 180. In addition, an expected data corresponding to the generated test pattern data is generated.
The timing generator 120 generates a timing edge which is a reference for converting the test pattern data generated in the pattern generator 110 into various waveforms. The timing edge is generated using a plurality of clocks for a smooth conversion.
The format controller 130 converts the test pattern data to a desired waveform based on the timing edge.
The driver 140 transmits the converted test waveform to the DUT 180.
The comparator 150 tests the DUT 180 by comparing the test output data being outputted from the DUT 180 after an operation of the DUT 180 is complete by the test waveform applied to the DUT 180 with the expected data generated in the pattern generator 110.
The test result storage 160 stores a test result based on a result of the comparison of the comparator 150. For instance, an information on a defective DUT is stored.
As described above, the conventional ATE is very highly priced. Therefore, it is preferable that a manufacturer designs the highly priced ATE efficiently in order to increase a competitiveness by minimizing a manufacturing cost thereof. For the efficient design of the ATE, the generation of the test pattern and the timing should be optimized.
Moreover, since the conventional ATE is very highly priced, a tester for testing the semiconductor device under an actual environment, i.e. an application environment tester may be used instead of the ATE.
For instance, Korean Patent Application No. 10-2002-0004428 filed on Jan. 25, 2002 by Silicontech titled "SEMICONDUCTOR MEMORY TESTER" discloses the application environment tester. In addition, Korean Patent Application No. 10-2004-78152 filed on Oct. 1, 2004 by the Applicant titled "SOCKET INTERFACE FOR APPLICATION TEST OF SEMICONDUCTORDEVICE" wherein the test is carried out using an electronic device such as a hard disk drive, a graphic board and a DVD drive instead of a PC mainboard, and Korean Patent Application No. 10-2004-78153 filed on Oct. 1, 2004 by the Applicant titled "TEST FIXTURE FOR APPLICATION TEST AND SEMICONDUCTORDEVICE APPLICATION TESTER HAVING THEREOF" disclose the application environment tester.
The application environment tester overcomes problems of the ATE that a long time is required for the test and that a detection of a defectiveness is limited under an application environment. Therefore, the application environment tester may carry out the test under the application environment using various diagnostic program such that the application environment tester is used for testing a new product or a product of a mass production.
Manufacturers of the semiconductor device uses both the ATE and the application environment tester are used to carry out the test.
Because basic principles employed by the ATE and the application environment tester are different, it is difficult to embody the ATE and the application environment tester simultaneously. Moreover, the application environment tester cannot test multiple semiconductor devices simultaneously.
In case of the ATE, because the number of semiconductors that may be tested using the pattern generator 110 shown in FIG. 1 is limited, a plurality of the pattern generators 110 should be used to test the multiple semiconductor devices in the ATE.

This patent is subject to a terminal disclaimer.


IPoE/PPPoE forwarding table 106 is provided with which registered are network addresses, protocol types, destination IP addresses used in IPoE and retrieval indexes of PPPoE sessions used in PPPoE, a protocol type is selected corresponding to a network address in IPoE/PPPoE forwarding table 106 that matches a destination IP address included in header information of an IP packet of an input frame, and when the selected protocol type is PPPoE, a PPPoE session is further selected from a retrieval index corresponding to the network address.

1. Field of the Invention
The present invention relates to a gateway apparatus that supports PPPoE (Point to Point Protocol over Ethernet(R)) and a method of controlling such an apparatus.
2. Description of the Related Art
Conventionally, a gateway apparatus is used so as to implement mutual communications between networks constructed in a corporation and external networks. For example, the gateway apparatus is used as a protocol converter for mutually connecting networks with different protocols. Examples of configuration of the gateway apparatus is one that supports only IPoE (Internet Protocol over Ethernet(R)) as a protocol for external networks, and one that supports both IPoE and PPPoE as protocols for external networks.
FIG. 1 illustrates a configuration of gateway apparatus 1100 that supports only IPoE. FIG. 2 is a diagram illustrating an example of network configuration to which gateway apparatus 1100 that supports only IPoE is connected.
As shown in FIG. 2, gateway apparatus 1100 is connected in its one interface to networks 1201 to 1204 that use IPoE as a protocol. Gateway apparatus 1100 communicates with gateways 1205 to 1208 disposed respectively on networks 1201 to 1204. Gateway apparatus 1100 is further connected in its other interface to terminals 1209 to 1211 such as personal computers (hereinafter referred to as "PC") that use IPoE as a protocol.
In gateway apparatus 1100 shown in FIG. 1, frame transmitting/receiving sections 1101 and 1102 transmit/receive frames to/from Ethernet (R) I/F. IPoE frame assembling/deassembling sections 1103 and 1104 assemble and deassemble IPoE frames, while recognizing the IPoE frame structure.
Forwarding control section 1105 controls the output of IPoE frame based on a destination IP address included in the header information of an IP packet of an input IPoE frame. In controlling the output of IPoE frame, forwarding control section 1105 uses IPoE forwarding table 1106 and ARP (Address Resolution Protocol) table 1107.
As shown in FIG. 3, with IPoE forwarding table 1106 are registered network addresses, output interface numbers (output IF numbers), types of routing (direct/indirect routing) and destination IP addresses (next hop IP addresses) in indirect routing in relation to one another.
As shown in FIG. 4, with ARP table 1107 are registered destination IP addresses, source MAC addresses and destination MAC addresses in relation to one another. In addition, in source MAC address, since the MAC address of gateway apparatus 1100 is generally used, all the entries have the same value. Accordingly, it may be possible to provide the MAC address of gateway apparatus 1100 as a separate register, instead of providing areas for source MAC addresses in ARP table 1107.
The operation of gateway apparatus 1100 will be described below which has the aforementioned configuration and supports only IPoE. Herein, the case is explained where an IPoE frame is input to frame transmitting/receiving section 1101.
When an IPoE frame is input to frame transmitting/receiving section 1101, IPoE frame assembling/deassembling section 1103 recognizes a structure of the IPoE frame, and provides the recognized structure of the IPoE frame to forwarding control section 1105.
Forwarding control section 1105 compares a destination IP address included in the header information of an IP packet of the IPoE frame with a network address registered with IPoE forwarding table 1106.
When the table 1106 has the same network address as the destination IP address, the section 1105 acquires an output IF number and information of routing type (information indicative of whether the routing is direct routing or indirect routing) in relation to the network address in IPoE forwarding table 1106, and when the indirect routing is indicated, further acquires a destination IP address (next hop IP address). In addition, when the direct routing is indicated, the section 1105 acquires the destination IP address of the IP header of the IP packet.
Then, forwarding control section 1105 searches ARP table 1107 using the retrieved destination IP address to retrieve a source MAC address and destination MAC address of the IPoE frame. The retrieved source MAC address and destination MAC address are provided to IPoE frame assembling/deassembling section 1104.
Using the source MAC address and destination MAC address, IPoE frame assembling/deassembling section 1104 re-assembles the IPoE frame. There-assembled IPoE frame is provided to frame transmitting/receiving section 1102 and output from the section 1102. In this way, IPoE frames are forwarded in gateway apparatus 1100 that supports only IPoE.
FIG. 5 is a diagram illustrating a configuration of gateway apparatus 1500 that supports PPPoE. In addition, in FIG. 5 sections assigned the same reference numerals as in FIG. 1 have the same functions and descriptions thereof are omitted. FIG. 6 is a diagram illustrating an example of network configuration to which gateway apparatus 1500 that supports PPPoE is connected.
As shown in FIG. 6, gateway apparatus 1500 is connected in its one interface to network 1601 using IPoE as a protocol and networks 1602 to 1604 using PPPoE as a protocol. Gateway apparatus 1500 communicates with gateway 1605 disposed on network 1601 and PPPoE servers 1606 to 1608 disposed respectively on networks 1602 to 1604. Gateway apparatus 1500 is further connected in its other interface to terminals 1609 to 1611 such as personal computers that use IPoE as a protocol.
In gateway apparatus 1500 shown in FIG. 5, IPoE/PPPoE frame assembling/deassembling sections 1501 and 1502 assemble and deassemble IPoE frames and PPPoE frames, while recognizing the IPoE frame structure and PPPoE frame structure.
Forwarding control section 1503 controls the output of IPoE or PPPoE frame based on a source IP address or destination IP address included in the header information of an IP packet of an input IPoE frame, while controlling the output of PPPoE frame based on PPPoE header information of an input PPPoE frame. In controlling the output of IPoE or PPPoE frame, forwarding control section 1503 uses PPPoE forwarding table 1504 and PPPoE session table 1505 in addition to IPoE forwarding table 1106 and ARP table 1107.
As shown in FIG. 7, PPPoE forwarding table 1504 has source IP addresses, output IF numbers and retrieval indexes of PPPoE session (hereinafter referred to as "PPPoE session indexes") in relation to one another.
As shown in FIG. 8, PPPoE session table 1505 has PPPoE session indexes, client MAC addresses, server MAC addresses and PPPoE session IDs in relation to one another.
The operation of gateway apparatus 1500 will be described below which has the aforementioned configuration and supports PPPoE. Herein, cases are explained separately where an IPoE frame is input to frame transmitting/receiving section 1101 and where a PPPoE frame is input to the section 1101.
When either frame is input to frame transmitting/receiving section 1101, IPoE/PPPoE frame assembling/deassembling section 1501 recognizes a structure of the frame, and provides the recognized structure of the frame to forwarding control section 1503.
When the input frame is an IPoE frame, forwarding control section 1503 compares a source IP address included in the header information of an IP packet of the IPoE frame with a source IP address registered with PPPoE forwarding table 1504.
When the table 1504 has the same source IP address as the source IP address included in the header information of the IP packet of the IPoE frame, the section 1503 acquires an output IF number and PPPoE session index in relation to the source IP address in PPPoE forwarding table 1504.
Then, forwarding control section 1503 searches PPPoE session table 1505 using the retrieved PPPoE session index, and acquires information such as a source MAC address, destination MAC address and PPPoE session ID to generate a PPPoE frame. The retrieved information to generate the PPPoE frame is provided to IPoE/PPPoE frame assembling/deassembling section 1502.
In addition, there is no direction information of source MAC address and destination MAC address in PPPoE session table 1505. The client MAC address is acquired as the source MAC address, and the server MAC address is acquired as the destination MAC address.
Based on the information to generate the PPPoE frame, IPoE/PPPoE frame assembling/deassembling section 1502 re-assembles the input IPoE frame to a PPPoE frame. The re-assembled PPPoE frame is provided to frame transmitting/receiving section 1102 and output from the section 1102.
When the same source IP address as that included in the header information of the IP packet of the IPoE frame is not registered with PPPoE forwarding table 1504, forwarding control section 1503 compares a destination IP address included in the header information of the IP packet with a network address registered with IPoE forwarding table 1106.
When the table 1106 has the same network address as the destination IP address, the section 1105 retrieves an output IF number and information of routing type (information indicative of whether the routing is direct routing or indirect routing) in relation to the network address in IPoE forwarding table 1106, and when the indirect routing is indicated, further retrieves a destination IP address (next hop IP address). In addition, when the direct routing is indicated, the section 1105 retrieves the destination IP address of the IP header of the IP packet.
Then, forwarding control section 1503 searches ARP table 1107 using the retrieved destination IP address to retrieve a source MAC address and destination MAC address of the IPoE frame. The retrieved source MAC address and destination MAC address are provided to IPoE/PPPoE frame assembling/deassembling section 1502.
Using the source MAC address and destination MAC address, IPoE/PPPoE frame assembling/deassembling section 1502 re-assembles the IPoE frame. The re-assembled IPoE frame is provided to frame transmitting/receiving section 1102 and output from the section 1102.
Meanwhile, when the input frame is a PPPoE frame, forwarding control section 1503 compares PPPoE header information of the PPPoE frame with an entry in PPPoE session table 1505.
When PPPoE header information of the PPPoE frame is matched with an entry registered with PPPoE session table 1505, the section 1503 compares a destination IP address included in the header information of an IP packet of the PPPoE frame with a network address registered with IPoE forwarding table 1106.
When the table 1106 has the same network address as the destination IP address, the section 1503 retrieves an output IF number and information of routing type (information indicative of whether the routing is direct routing or indirect routing) in relation to the network address, and when the indirect routing is indicated, further retrieves a destination IP address (next hop IP address). In addition, when the direct routing is indicated, the section 1503 retrieves the destination IP address of the IP header of the IP packet.
Then, forwarding control section 1503 searches ARP table 1107 using the retrieved destination IP address to retrieve a source MAC address and destination MAC address. The retrieved source MAC address and destination MAC address are provided to IPoE/PPPoE frame assembling/deassembling section 1502.
Using the source MAC address and destination MAC address, IPoE/PPPoE frame assembling/deassembling section 1502 re-assembles the PPPoE frame to an IPoE frame. The re-assembled IPoE frame is provided to frame transmitting/receiving section 1102 and output from the section 1102.
Thus, gateway apparatus 1500 that supports PPPoE relays an IPoE frame as an IPoE address according to a network address corresponding to a destination IP address included in the header information of an IP packet of the IPoE frame, while outputting as a PPPoE frame, selecting a PPPoE session corresponding to a source IP address included in the header information of the IP packet of the IPoE frame.
However, gateway apparatus 1100 that supports only IPoE has a problem that the apparatus 1100 cannot relay frames except IPoE frames. Further, gateway apparatus 1500 that supports PPPoE selects a PPPoE session corresponding to a source IP address included in the header information of an IP packet of an input IPoE frame. Accordingly, there arises a problem that since each terminal (1609 to 1611) cannot select a plurality of PPPoE sessions concurrently, it is not possible to access a plurality of PPPoE servers. Further, there is another problem that when source IP addresses are matched, since an IPoE frame is output automatically as a PPPoE frame, it is not possible to access a network that uses IPoE.

Gateway apparatus and its controlling method

Matsushita Electric Industrial Co., Ltd.


By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.

1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing integrated circuits, and, more particularly, to the formation of device features on the basis of lithography techniques requiring sensitive focus parameters.
2. Description of the Related Art
Typically, the fabrication of modern integrated circuits includes a complex process flow, in which a large number of individual processes are performed, such as deposition, implantation, etching, lithography and the like. For example, a typical process sequence frequently encountered may involve the deposition of conductive, semiconductive or insulating material layers on an appropriate substrate. After deposition of the corresponding layer, device features may be formed in the material layer by patterning the corresponding layer on the basis of photolithography and etch techniques, thereby creating a certain topography by the resulting features, such as trenches, vias, lines and the like, which are formed from the underlying material layer. The resulting surface topography may also affect further manufacturing processes, such as the deposition and patterning of subsequent layers. Since sophisticated integrated circuits are typically comprised of a plurality of stacked material layers, each of which may bear a specified spatial relationship to underlying and overlying layers, it has become standard practice to periodically planarize the surface of the substrate to provide well-defined conditions for deposition and patterning of subsequent material layers. This holds especially true for so-called metallization layers in which metal interconnect structures are formed to electrically connect the individual device features, such as transistors, capacitors, resistors and the like, to establish the functionality required by the circuit design.
Recently, the so-called damascene or inlaid technique has become a preferred method in forming metallization layers, wherein a dielectric layer is deposited and patterned to include trenches and vias that are subsequently filled with an appropriate metal, such as copper, copper alloys and the like. In this manufacturing regime, the previously formed trenches and/or vias have to be filled such that the various openings, which may have different sizes, may be reliably filled, thereby requiring the deposition of a certain amount of excess material. The excess metal is then removed and the resulting surface is planarized by performing a planarization process which may typically comprise a chemical mechanical polishing (CMP) process. Chemical mechanical polishing (CMP) has proven to be a reliable technique to remove the excess metal and planarize the resulting surface to leave behind metal trenches and vias that are electrically insulated from each other as required by the corresponding circuit layout. Chemical mechanical polishing typically requires the substrate to be attached to a carrier, a so-called polishing head, such that the substrate surface to be planarized is exposed and may be placed against a polishing pad. The polishing head and polishing pad are moved relative to each other by individually moving the polishing head and the polishing pad. Typically, the head and pad are moved against each other while controlling the relative motion to achieve as uniform a material removal as possible.
However, the removal rate may not only depend on the characteristics of the chemical and mechanical adjustments of the polishing process but also on the type of materials to be polished and the local pattern geometry. For instance, at a polishing state where the major portion of the metal has already been removed, the dielectric material and metal, such as copper, barrier material and the like, may be treated concurrently with different removal rates, thereby resulting in a certain degree of non-uniformity, wherein a varying degree of metal coverage of the currently polished surface, due to a difference in pattern density with respect to the metal regions, may also contribute to corresponding overall non-uniform planarity. For example, the presence of a plurality of closely spaced metal lines may result in a higher total removal rate for the dielectric material and the metal compared to areas including isolated lines. The resulting different non-uniformity of the surface topography may, however, affect subsequent processes, such as the deposition of dielectric materials and the patterning thereof on the basis of sophisticated lithography techniques, due to the very restricted process window when highly scaled devices are considered, as will be explained in more detail with reference to FIGS. 1a-1c.
FIGS. 1a-1c schematically illustrate cross-sectional views of a semiconductor device 100 at various stages during the fabricating of a metallization layer according to a typical damascene process sequence.
In FIG. 1a, the semiconductor device 100 comprises a substrate 101 including circuit features and any other components related thereto, which, for convenience, are not shown in FIG. 1a. Furthermore, a dielectric layer 102 may be provided above the substrate 101, and above any circuit elements formed therein and thereon, which may represent the dielectric material of a respective metallization layer of the device 100. The dielectric layer 102 may be comprised of any appropriate material, such as silicon dioxide, silicon nitride and the like, wherein, in sophisticated applications, the dielectric layer 102 may at least be partially comprised of a low-k dielectric material having a relative permittivity of approximately 3.0 and significantly less. Furthermore, in and above the dielectric layer 102 are defined device areas 110A, 110B in which different structural characteristics, such as pattern density and the like, may result in respective non-uniformities of the resulting surface topography. For instance, in the area 110A, a plurality of closely spaced metal-filled trenches 103 may be provided, while the area 110B may be characterized by a significantly reduced metal density, for instance by including an isolated metal trench 104. It should be appreciated that the areas 110A, 110B are illustrative examples of different structural characteristics with respect to the effective "averaged" metal contents in respective device areas. Furthermore, it should be appreciated that the device areas 110A, 110B may not necessarily be defined by well-defined boundaries but may be substantially determined by the corresponding "global" or "averaged" effect during certain manufacturing processes, such as a CMP process, which will be described later on in more detail. The metal-filled trenches 103, 104 may comprise highly conductive metal materials, such as copper, copper alloys and the like, which may typically be provided in combination with respective barrier materials (not shown) in order to reduce out-diffusion of copper material, enhance the adhesion thereof to the neighboring dielectric material and reduce any interaction of reactive components with the highly sensitive copper material.
Typically, the semiconductor device 100 as shown in FIG. 1a may be formed on the following process techniques. After the completion of any circuit elements including respective contact portions and the like, the dielectric layer 102 may be formed on the basis of well-established recipes, which may include the deposition of an etch stop material (not shown) followed by the application of an appropriate dielectric material, such as a low-k dielectric material or a combination of a silicon dioxide-based dielectric material in combination with other low-k dielectric materials, depending on the device requirement. Next, sophisticated lithography processes may be performed in order to form appropriate openings in the dielectric layer 102, wherein sophisticated lithography techniques may be used, as will be described later on with reference to FIG. 1b. Thereafter, the resulting openings, such as trenches and the like, may be filled with an appropriate conductive material, wherein typically respective barrier materials may be deposited, for instance on the basis of chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like. Subsequently, after providing appropriate seed materials, such as copper and the like, the copper-based material may be deposited on the basis of a wet chemical deposition process requiring highly sophisticated process regimes to fill the respective trenches from bottom to top in a substantially void-free manner. Furthermore, in order to reliably fill the respective trenches, which may have different lateral sizes, depth and the like, a certain amount of excess material may also be formed on horizontal surface portions of the device 100, wherein the resulting surface topography may depend significantly on the local deposition conditions, which, in turn, may be determined, among others, by the different pattern densities in the respective areas 110A, 110B. After the deposition process, the corresponding excess material may be removed, wherein usually a CMP process may be applied, at least at a final phase. During the removal of the copper material, the seed layer and the barrier materials, highly complex CMP process conditions may occur during the final phase of the CMP process, thereby resulting in respective surface non-uniformities, that is, in the various device areas 110A, 110B, different height levels may be created locally, as is, for instance, indicated by the dashed line 111, which may represent enhanced material removal of the dielectric material and the metal in the trenches 103 compared to the situation in the area 110B. It should further be appreciated that the respective surface topography of the area 110A may further comprise a certain "fine structure" since the material erosion in the respective trenches 103 compared to the neighboring dielectric areas may also be different, which is however not shown in FIG. 1a. Consequently, although a generally substantially flat surface topography may be provided, nevertheless a certain degree of non-planarity with respect to the specified device areas 110A, 110B may have been created, for instance by CMP, thereby providing a difference in height levels and thus a certain amount of non-planarity which may vary depending on device-specific characteristics, such as pattern density and the like.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. Here, a further dielectric layer 103 may be provided, followed by an anti-reflective coating (ARC) 104 and a resist layer 105 in order to prepare the device 100 for a further sophisticated lithography process in order to pattern the dielectric layer 103 for receiving via openings and/or trenches, depending on the process requirements. As previously explained, one essential process in the manufacturing of semiconductor devices is the lithography process, since exposure processes at the various device levels represent the major part of the overall production costs while also providing the potential for compensating for across-substrate non-uniformities and also rectifying exposure-specific errors prior to permanently transferring such exposure-specific errors into the semiconductor structure, such as the dielectric layer 103. It is thus of great importance to provide process conditions for reliably imaging the respective device features having the minimum lateral dimensions of the circuit design of the respective process layer under consideration into the resist material 105. The resolution of the corresponding imaging process is substantially determined by the numerical aperture of the imaging system, the exposure wavelength and the depth of focus. For obtaining an increased resolution, typically the exposure wavelength may be reduced, which results, for a fixed numerical aperture, in a reduced depth of focus. For instance, with ever decreasing exposure wavelengths, which may presently be at approximately 190 nm for critical lithography processes also used in the metallization level, the requirements with respect to appropriately focusing each exposure field are becoming more and more stringent. In an exposure process, therefore, highly complex and automated procedures are performed in order to appropriately align and focus the substrate to be exposed. The alignment and focusing procedure is usually performed individually for each exposure field in a step and scan system and may thus require different alignment and focusing values of the respective parameters. For example, in the presence of non-uniformities of the resulting surface topography, for instance the respective non-uniformity 111 in the areas 110A, 110B, which may represent respective areas within a specific die region and which may therefore be contained in the same exposure field, the respective exposure process may result in slightly defocused latent images in some of these areas, depending on the respective non-uniformities. Thus, during a lithography process 106, the difference in planarity in the regions 110A, 110B, as indicated by 111, may cause respective non-uniformities of the imaging process and subsequently respective non-uniformities during the patterning of the dielectric layer 103. Hence, respective patterning errors and even missing patterns may occur due to the CMP-induced non-uniformities 111.
FIG. 1c schematically illustrates a cross-sectional view of the device 100 in an advanced manufacturing stage, wherein respective via openings 107 may be formed above the area 110A, and a corresponding opening 108 may be formed above the area 110B. As illustrated, the difference in the surface planarity may result in respective patterning errors or even missing features, wherein it may be assumed that the respective focus conditions may not have been appropriate for the area 110A. In this case, the respective resist features formed from the resist layer 105 on the basis of the exposure process 106 may result in corresponding pattern transfer errors during the subsequent anisotropic etch process, finally resulting in faulty interconnect structures.
Thus, although the critical dimensions of the respective device level, such as the level formed on the basis of the exposure process 106, may be monitored and controlled on the basis of appropriately designed CD (critical dimension) measurement structures during respective metrology strategies, the corresponding patterning errors, such as the faulty openings 107, may not be efficiently detected by conventional CD monitoring techniques but may require sophisticated electrical tests, thereby additionally increasing cycle time, increasing defect rate caused by the additional electrical tests and the like. Furthermore, respective electrical measurement data of focus related patterning errors may be available after permanently transferring the respective patterns into the respective device level, thereby producing respective faulty devices in exposure fields processed on the basis of inappropriate focusing parameters.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.

Method and test structure for estimating focus settings in a lithography process based on CD measurements


A capacitor connected to a voltage source is charged during a charging phase up to a voltage value, and during a discharging phase the capacitor is discharged via a coupling element connected to the flame sensor. The period for the charging or discharging phase of the capacitor respectively is selected in this case as a function of the characteristics of the flame sensor, especially of its impedance. For flame monitoring the charging and discharging of the capacitor is repeated cyclically, with the voltage signal obtained in this way being evaluated in single-channel mode with the aid of a threshold value.

The invention relates to a method and a device for flame monitoring.
A method and a device of the type mentioned at the start is known for example from EP 617 234 910 A1. This publication discloses an ionization flame detector with a capacitor, which is connected to a reference voltage source and via a coupling element to the secondary circuit of a firing circuit. For as long as there is no flame present between the firing electrode and the ground lead the capacitor is charged via a resistor to an operating voltage. As soon as an ionization stream flows as a result of flame generation the capacitor is discharged. The capacitor is connected to a monitoring circuit which, if a predetermined threshold value is exceeded, creates an output signal which indicates the presence of a flame.
EP 1 256 763 A2 discloses a flame monitoring method, in which the radiation created by the flame is recorded by a photoresistor and the sensor signal is evaluated on two channels. The first channel is used to record the average brightness and the second channel is used to record changing components which emanate from flickering of the flame. The flame is only recognized as burning correctly if the signal is within a predetermined range in each case at both channel outputs.

Siemens Building Technologies HVAC Products GmbH


A pressure regulator for regulating fuel pressure in an internal combustion engine, containing a valve including a closing member forced into a valve seat by the action of an angularly shaped valve leaf spring one arm of which is braced on the closing member and the other arm is braced on a support member of a regulator housing. In the region of its angled portion, the leaf spring is fixed on a pin supported in the regulator housing, and the bearing of the pin in the regulator housing contains side walls of the regulator housing that wrap around bearing bores in the valve leaf spring with parallel spacing and that extend substantially perpendicular to the pin. The side walls are overlapped at least in part by tabs that are connected to the support member of the regulator housing and are provided with bearing bores for the pin which are coaxial relative to the bearing bores in the side walls.

1. Field of the Invention
This invention is directed to an improved pressure regulator, and more particularly to an improved fuel pressure regulator for an internal combustion engine.
2. Description of the Prior Art
Pressure regulators for a fuel supply system of an internal combustion engine are known which contain a valve that includes a valve closing member that is forced into the closing position against a valve seat by the action of an angularly shaped valve leaf spring, and one arm of the valve leaf spring is braced on the valve closing member and the other arm is braced on a support member of a regulator housing, and in the region of its angled portion, the valve leaf spring is fixed on a pin supported in the regulator housing, and the bearing of the pin in the regulator housing contains side walls of the regulator housing that wrap around bearing bores in the valve leaf spring with parallel spacing and that extend substantially perpendicular to the pin.
One such pressure regulator is described in German Patent Disclosure DE 101 07 223 A1; the valve leaf spring is pivotably supported by the pin in such a way that there is a torque equilibrium at the valve leaf spring. The valve leaf spring braced on the support member of the regulator housing is prestressed, and the prestressing force acts as a closing force on the valve closing member. The pin acts here as a bearing point, which transmits the forces acting on the valve leaf spring to the regulator housing. If at a pressure inlet of the pressure regulator fuel pressure prevails that is high enough to generate a pressure force greater than the closing force acting on the valve ball, then the valve closing member lifts away from the valve seat and uncovers a defined flow cross section, so that fluid, in particular fuel, can flow to a pressure outlet of the pressure regulator.


A process for re-refining used lubricating oil (ULO) having thermally unstable additives. ULO is heated by mixing with superheated lubricant boiling range hydrocarbons recovered and recycled from the process. The mixture of ULO feed and superheated hydrocarbons is charged to a vacuum column, producing an overhead vapor free of unstable additives and a residual fraction, containing additives. The overhead vapor is condensed to produce an overhead liquid of lubricant boiling range hydrocarbons, a portion of which is recovered as a product and a portion of which is recycled. The overhead liquid free of unstable additives, may be superheated without fouling to produce superheated fluid which can heat the ULO feed sufficiently to permit fractionation. Superheating may occur in a fired heater or preferably in a heat exchanger to prevent high temperatures and cracking of recycled liquid. Mixing of superheated fluid and ULO feed may occur in a pipe in fully developed turbulent flow, and preferably via an inline mixer. Energy efficiency is improved by heat exchanging ULO feed with product streams.

Processing used motor oil has been a problem in search of solution for over 50 years. It is a problem both in size and technology. In the USA, over 1 billion gallons of used motor oil is "produced". Little of it is recycled or used effectively and much is improperly dumped. Re-refining is a problem because the very additives which make modern lubricating oils stick to metal surfaces in an engine greatly complicate recovery of the lubricant boiling range hydrocarbons, at least recovery using commercially viable technology. The state of the art of producing, collecting and re-refining of used motor oil and other industrial oils will be reviewed.
Automotive and many industrial lubricating oils are usually formulated from paraffin based petroleum distillate oils or from synthetic base lubricating oils. Lubricating oils are combined with additives such as soaps, extreme pressure (E.P.) agents, viscosity index (V.I.) improver, antifoamants, rust inhibitors, anti-wear agents, antioxidants, and polymeric dispersants to produce an engine lubricating oil of SAE 5 to SAE 60 viscosity.
After use, this oil is collected from truck and bus fleets, automobile service stations, and municipal recycling centers for reclaiming. This collected oil contains organo-metallic additives such as zinc dialkylthiophosphate from the original lubricating oil formulation, sludge formed in the engine, and water. The used oil may also contain contaminants such as waste grease, brake fluid, transmission oil, transformer oil, railroad lubricant, crude oil, antifreeze, dry cleaning fluid, degreasing solvents such as trichloroethylene, edible fats and oils, mineral acids, soot, earth and waste of unknown origin.
Reclaiming of waste oil is largely carried out by small processors using various processes tailored to the available waste oil, product demands, and local environmental considerations. Such processes at a minimum include partial de-watering and coarse filtering. Some more sophisticated processors may practice chemical demetallizing or distillation. The presence of organo-metallics in waste oils such as zinc dialkylthiophosphate results in decomposition of the zinc dialkyldithiophospnate to form a carbonaceous layer rich in zinc and often other metals such as calcium, magnesium and other metals present as additives and thus difficult if not impossible to process. The carbonaceous layer containing the various metals forms rapidly on heated surfaces and can develop to a thickness of more than 1 mm in 24 hours. This layer not only reduces the heat transfer coefficient of tubular heaters rapidly, it also results in substantial or total occlusion of these tubes within a few days.
Successful reclaiming processes require the reduction of the organo-metallics (or ash) content to a level at which the hot oil does not foul heated surfaces. Such reduction can be carried out by chemical processes which include reacting cation phosphate or cation sulfate with the chemically bonded metal to form metallic phosphate or metallic sulfate. U.S. Pat. No. 4,432,865 to Norman, the contents of which are incorporated herein by reference, discloses contacting used motor oil with polyfunctional mineral acid and polyhydroxy compound to react with undesired contaminants to form easily removable reaction products. These chemical processes suffer from attendant disposal problems depending on the metal by-products formed.
Ash content can also be reduced by heating the used lubricating oil (ULO) to decompose the organo-metallic additives. Direct contact heating of ULO with a recycled bottoms fraction was disclosed in U.S. Pat. No. 5,447,628 to Harrison, et al., the contents of which are incorporated herein by reference. The ULO was added to a lower section of a vacuum column with an enlarged bottom section. There was enough volumetric capacity below the first tray of the column to provide "a residence time of 10 to 120 minutes." The EXAMPLE reported that a residence time of 45 minutes and a relatively constant temperature of 660° F. A dehydrated ULO fraction was mixed with a recycled bottoms fraction in the rate of 1:45. The long residence time and high temperature were believed sufficient to decompose the additives in the ULO, so that a bottoms fraction from this column could be sent to a fired heater, to supply the heat needs of the process. The patentee reported that additive decomposition began at 400° F. The Figure in the patent showed that zinc compound decomposition was a function of temperature, with time temperature decomposition profiles presented for 400° F., 500° F., 750° F. and 1000° F.
UOP's Hy-Lube process, described in U.S. Pat. No. 5,244,565, U.S. Pat. No. 5,302,282, and many more patents, uses a hot circulating hydrogen rich stream as a heating medium to avoid deposition of decomposed organo-metallic compounds on heating surfaces.
The problem of fouling of heated surfaces can be ameliorated to some extent by gentler heating. Some processes, such as the fixed bed version of catalytic cracking, the Houdry process, used a molten salt bath to provide controlled, somewhat gentle heating of vaporized liquid hydrocarbon passing through tubes of catalyst immersed in the salt bath. Molten metal baths have also been used as a convenient way to heat difficult to processes substances to a control temperature, e.g., flammability of some plastics is tested by putting a flask with plastic into a bath of molten metal. Use of molten salt bath, or molten metal bath, or condensing high temperature vapor, could be used to reduce uneven heating of heat exchange surface and thereby reduce ΔT across a metal surface and perhaps slow the fouling of metal surfaces in ULO service, but the additives in the ULO would still tend to decompose on the hottest surface, which would be the heat exchanger tubes.
In U.S. Pat. No. 7,150,822 and U.S. Pat. No. 7,241,377 Malone taught use of a molten metal or molten salt bath for direct contact heating of ULO. The process effectively heats ULO without fouling the heating surface, a molten metal or salt bath, but the process requires a large and heavy molten metal vessel for processing of the oil. Start-up of such a process, or perhaps operation, may have encountered problems as the first commercial unit is believed no longer in operation.
Solvent extraction with light paraffin solvents such as propane, butane, pentane and mixtures thereof have been practiced by Interline and others. Details of the Interline Process are provided in U.S. Pat. No. 5,286,380 and U.S. Pat. No. 5,556,548. While the extraction approach seems like an elegant solution to the problem of processing ULO, the process may be relatively expensive to operate. Their quarterly report of May 15, 2002, reports that "It has become evident that demanding royalties based on production is impractical in many situations and countries. Unless and until the re-refined oil produced in a plant can be sold at prices comparable to base lubricating oils, collecting royalties based on production will be difficult. This reality was experienced in Korea, where the royalty was terminated for the first plant, and in England where the royalties were reduced and deferred until the plant becomes profitable."
Another approach to ULO processing was direct contact heating of the ULO with steam or a non-hydrogenating gas. This solved the problem of zinc additive decomposition fouling of hot metal surfaces, by ensuring that the metal surfaces holding the ULO were always relatively cool. The hottest spot in these ULO process was the point of vapor injection. Decomposing additives had only themselves to condense upon.
A vapor injection ULO process was disclosed in U.S. Pat. No. 6,068,759 Process for Recovering Lube Oil Base Stocks from Used Motor Oil and U.S. Pat. No. 6,447,672 Continuous Plural Stage Heated Vapor Injection Process for Recovering Lube Oil Base Stocks from Used Motor Oil. The heated vapor was steam, methane, ethane, propane or mixtures. Other variations on the theme of ULO vapor injection are disclosed in U.S. Pat. No. 6,402,937 Pumped Recycle Vapor and U.S. Pat. No. 6,402,938, Vaporization of Used Motor Oil with Non-hydrogenating Recycle Vapor, which are incorporated by reference. This approach used a "working fluid" such as methanol or propane, which was heated and mixed with ULO to vaporize lube boiling range components. A lube fraction was recovered as a product and the methanol or propane working fluid either compressed, or condensed and pumped, through a heater to be recycled to heat incoming ULO.
Petroleum refiners have been trying for over half a century to devise a satisfactory way to reprocess used lube oil. No process is known which could be considered a commercial success. Despite the abundance of a potentially valuable waste material, the lubricating oil boiling range hydrocarbons trapped in the ULO, most ULO is not re-refined. The "state of the art" of used motor oil processing could be summarized as follows:
Chemical additive and extraction approaches can be used to react with or extract everything but zinc additives, but costs associated with such processes are apparently high, as evidenced by little commercial use. Additives could be extracted, but the operating costs are high.
Indirect heating in a fired heater causes rapid fouling of metal surfaces. Using milder heating, via a double boiler approach or molten metal heating medium, can minimize but not eliminate fouling on hot metal surfaces.
Direct contact heating with high pressure hydrogen may eliminate fouling but requires high capital and operating expenses.
Direct contact heating, with a recycled bottoms fraction can still suffer from heater fouling. A stream containing the non-distillable additive package and/or the decomposition products thereof is still sent through a fired heater where fouling can occur.
Direct contact heating with steam or a light hydrocarbon "working fluid" vapor is an attractive approach. When steam is the injected vapor, the process can create a water disposal problem and is thermally less efficient because the latent heat of water is lost when the steam is condensed against cooling water or air in a heat exchanger. There are also concerns about possible formation of emulsions or corrosive regions in portions of the plant, when water is condensing. When a "working fluid" is used for heating e.g., propane, the water problem is largely eliminated, but large volumes of vapor are needed to provide sufficient heat input, so costs increase to heat and recycle such vapor streams. The working fluid approach also calls for a somewhat higher capital cost, because higher pressure operation is generally needed to facilitate circulation of the large volumes of working fluid to heat the used lube oil feed.
We wanted a better approach, one which is simple and reliable and which does little or no harm to the used lube oil fraction. We define harm in the sense of thermally cracking the ULO and generating large amounts of reactive intermediate species, many of which are chloride containing.
Brute force heating, by recycling a bottoms stream, forces at least some of the additive package to end up in the bottoms and go through a fired heater, and cause fouling. The brute force approach vaporizes the lubricant boiling range components, but can easily degrade the lube components and contaminate them with significant amounts of the breakdown products of the additive package. The recovered lube boiling range components will have significant value as fuel or cracker feed blending component, but are generally not suitable for use as lubricant blending stock, at least not without a lot of expensive hydrotreating. Destructive distillation of ULO, by spraying it on top of a coker drum, decomposes the additive package and leaves it behind in the coke—but the valuable, paraffinic lubricant boiling range hydrocarbons are converted to coker naphtha or other reactive and difficult to process fractions. The lube fraction is arguably "recovered" but is no longer remotely suitable for use as a blending component.
Steam injection, for heating of ULO, would minimize thermal degradation of lubricant boiling range hydrocarbons in the ULO, but the relatively "wet" approach causes concerns about disposal of waste water, emulsion formation and/or plant corrosion. The "pumped vapor" approach, using propane or the like, eliminates most water problems, but requires a more complicated plant to recycle the hydrocarbon vapor. Large molar volumes of injected vapor are needed because of the relatively low molecular weight and low heat capacity of hydrocarbon vapors. Condensation and separation of injected heating vapor and recovered lubricating components are somewhat expensive.
We wanted to vaporize the valuable lube components in ULO without unduly damaging the lube containing vapor product or fouling the plant heaters. We realized that there was a way to overcome the deficiencies of the prior art process by doing something akin to early treatment of FCC feed. In the FCC process, refiners charge a selected distilled fraction to the cracking unit. A distilled feed is used because distillation leaves behind unwanted metal species which are a poison to the cracking catalyst. Our approach was something like an island hopping campaign in war. We did not care about eliminating the enemy, namely the additive package, if we could get around it.
We found in the effluent of a used lube oil refining process the ideal material to heat the incoming used lube oil. The recovered distilled lubricant boiling range material was essentially a metal and contaminant free material. This material could be safely heated without additive fouling of metal surfaces to produce a super-heated fluid which could be mixed with and vaporize a ULO feed. It may seem counter-intuitive, to use a clean, distilled material that was the desired product of the process, to send this product to a heater at temperatures which could in time thermally crack the product, and then mix this clean superheated product completely with a highly contaminated feed. Refiners usually want to recover a valuable product and send it to storage for sale, not heat it to a temperature which could in time coke it, and then mix it with a highly contaminated feed stock.
The key feature was heating the ULO with a clean, distilled material—a portion of the lubricant boiling range product recovered from the used lube oil fractionator. This material was essentially free of metals and could safely be heated in a heat exchanger or fired heater without fear of fouling. This distilled material, a lubricant boiling range fraction, was always available downstream of the vaporizing portion of the plant. It has a high boiling point, essentially the same as the boiling point of the lubricating oil components of the ULO feed to the process. This vaporized lube fraction could be readily condensed at high temperature. It also, by virtue of its high molecular weight, could carry a lot of energy with it when heated in a furnace or heat exchanger so that undue volumetric amounts were not required to achieve the desired amount of direct contact heating of ULO feed.
We realized that the high grade energy in hot, vaporized lubricant boiling range hydrocarbon vapor recovered from the ULO, could be used to effectively and gently preheat incoming feed for energy savings. The resulting condensed lube fraction could also be split into a net product fraction removed from the process and a recycle fraction sent through a fired heater, heat exchanger or other heating means to generate the hot vapor needed to vaporize the ULO feed. The relatively hot product liquid fraction could be used for a measure of preheating of ULO to facilitate dehydration.
The use of a vaporized lubricant boiling range hydrocarbon simplified the process flow and gave the option to achieve significant improvement in thermal efficiency of the process and facilitate plant operation. Lubricant boiling range materials are always available in the feed ULO, so no purchased working fluid is needed save perhaps at initial startup. The vaporized lube fraction condenses readily at elevated temperature, even under vacuum conditions so fin fan coolers or heat exchangers can easily condense these vapors. Preferably much of the energy in the vaporized lube fraction is recovered by heat exchange with ULO feed.
The condensed lubricant boiling range material recovered from the product is a relatively stable material, at least far more stable than the feed ULO. This stable material may tolerate a lot of heating by heat exchange with heavy residue material withdrawn from the product fractionator, by heating in a fired heater, or by heat exchange with some other high temperature heat source. While the paraffinic lubricant boiling range material is subject to thermal cracking, at least the only cracking products will be those typically experienced during mild thermal cracking of relatively pure hydrocarbons, a modest amount of olefins. Such a stream is a valuable product, suitable for use as cracker feed or, depending on thermal severity, suitable for use as a lubricant blending stock. With hydro-processing it can produce a premium blending stock or fuel. Such modestly cracked streams with some olefins but few dienes may be processed easily using conventional refinery technology, whereas severely cracked streams with high diene content require extra and expensive processing to make them stable enough for further processing.


A system and method for differentiating customers according to their worth to the casino. Customer information is accumulated at each affiliated casino through one or more LAN-based management systems, updated to a central patron database (CPDB) that is coupled to each casino LAN through a WAN, and made available to each affiliated casino property as needed. Customer accounts are automatically activated and provided with data from the CPDB when a customer from one casino property first visits an affiliated casino property. Customer accounts are updated with status information based on the customer's worth to the casino. Customer accounts are updated with new activity data whenever a management system associated with the casino receives customer data from input devices, such as card readers, workstations, and dumb terminals, located at various venues throughout the casino. Customers are awarded points, based on their tracked activity at all affiliated casino properties. Customers also have theoretical win profiles. Customer status may be based on accumulated points or the theoretical win profile. When the customer is recognized at a gaming machine, or any location having a suitable card reader, the customer's status is determined in the customer account. For a special status customer, a physical instrumentality is activated for the benefit of the customer, such as a telephone, light, lockable cabinet, or the like. Distinguished services may also be provided once the special status customer is recognized.

1. Technical Field
This invention relates to the field of systems for tracking customer activity at casinos, and in particular, to systems for tracking customers' gaming and non-gaming activity across affiliated casino properties, for use in customer recognition and marketing programs.
2. Background Art
Substantially all casinos have implemented some form of customer tracking to identify and reward their valuable customers. These tracking programs often use the betting activity of a customer as the basis for awarding the customer complementary rooms, meals, event tickets, and the like ("comps"). Typically, these tracking programs are implemented by providing each customer with a casino membership card which includes a machine readable identification number specific to the customer. Each identification number has an associated customer account that is stored in the casino's computer system and updated to reflect customer activity. Customers need only insert their cards in slot machines or card readers associated with gaming tables or give their cards to a casino employee to have their betting activity monitored and reflected in their accounts. Customer cards may also be used to track customer activity at casino venues, such as special events, showrooms, and hotels, through card readers and computer terminals manned by casino employees.
The growth of the gaming industry has created new challenges to the way in which customer tracking programs are implemented. Many states and territories have recently legalized casino gambling, and companies have built casino properties at these new gaming locations to meet the demand for gaming facilities. Despite the increased number of casino properties affiliated with a company, conventional casino management practices continue to treat these casino properties as autonomous, decentralized entities that compete with each other for valuable customers. In particular, customer tracking at each casino property is typically controlled by local management, and few if any attempts have been made to coordinate customer information across affiliated casino properties. For example, each casino has its own system that tracks betting data on the casino's customers. The property treats this betting data as confidential, in order to prevent competing casinos, including those affiliated with the property, from luring away valuable customers. Thus, customer tracking programs at affiliated properties remain fragmented, and conventional management practices provide little incentive to coordinate data accumulated by these tracking programs.
Even if a casino company was to attempt some coordination of customer tracking programs at its affiliated casinos, the systems currently in place at various casino properties are too localized to integrate easily. Casino management systems are typically custom designed for each casino property, the customer data is limited to selected customer activity at the specific casino property, and the customer data accumulated by different computer systems within the same casino is often in different, incompatible formats. Thus, while each casino has useful data for its regular customers, there is no ready means for consolidating this data or making it available conveniently for use at other casinos. In short there are both operational and technical barriers to coordinating customer tracking programs at individual casino properties into national, company-wide tracking and marketing programs.
Another limitation of conventional casino management systems is that they do not take adequate steps to differentiate the worth of a customer to the casino on the basis of the customer's gaming activities. In particular, conventional systems do not adequately provide the customer with the use of various physical instrumentalities that enhance the customer's experience, based on the customer's worth to the casino.

Customer worth differentiation by selective activation of physical instrumentalities within the casino