Solving simultaneous equations of the moment method defining relationships between a mutual impedence between elements of an electronic apparatus, a wave source, and an electric current flowing in each element so as to simulate an electric current, provided with a unit for calculating the mutual impedance at a sampling frequency and calculating approximation coefficients, when expressing the mutual impedance by approximation expressions in terms of exponents and exponent powers, from the calculated values and sampling frequency; a unit for forming the simultaneous differential equations by setting the approximation coefficients and initial value with respect to the simultaneous differential equations derived by performing a Fourier transform on the simultaneous equations of the moment method in which the approximation expressions are substituted; and a unit for calculating the electric current in the time domain flowing through the specified element by solving the simultaneous differential equations formed.

1. Field of the Invention
The present invention relates to a simulation apparatus and method for simulating an electric current flowing in an electronic apparatus and an intensity of an electromagnetic field radiated from the electronic apparatus by using the moment method and to a memory medium storing a program for realizing the simulation apparatus therein, more particularly relates to a simulation apparatus and method using the moment method for making simulation in the time domain possible and a memory medium storing a program for realizing the simulation apparatus therein.
One of the rules imposed by society on electronic apparatuses is that they should not emit more than a predetermined level of undesired radio waves or noise. This is now being strictly regulated by the standards of many countries.
A variety of technologies, such as shielding technologies and filtering technolgies, are used in order to satisfy such radio wave regulations, but use of these requires the development of simulation technology for making it possible to quantitatively simulate to which degree they can reduce the radio waves.
Another rule imposed on electronic apparatuses by society is that they should not be influenced by less than a predetermined level of radio waves or noise radiated from other electronic apparatuses. This too is now being strictly regulated by the standards of many countries.
2. Description of the Related Art
In order to satisfy such radio wave regulations, development of simulation technology for making it possible to clarify why an electronic apparatus radiates undesired radio waves or noise or why an electronic apparatus malfunctions due to the radio waves or noise is necessary.
Development of the latter simulation technology requires a simulation apparatus which can simulating the electric current changing over time which will flow in an electronic apparatus due to noise or the like and the intensity of the electromagnetic field changing over time which is radiated from the electronic apparatus. Nevertheless, no such simulation apparatus for simulating such an electric current and the intensity of an electromagnetic field changing over time has yet been commercialized. The reason for this will be explained in detail later with reference to the drawings.
An object of the present invention is to provide a novel simulation apparatus and method using a moment method which uses approximation expressions explained in detail later to make it possible to simulate a temporally changing electric current changing over time which flows in an electronic apparatus due to noise or the like and an intensity of an electromagnetic field changing over time which is radiated from an electronic apparatus and to provide a memory medium storing a program for realizing the simulation apparatus therein.
To attain the above object, the present invention is of a configuration which simulates an electric current by solving simultaneous equations of the moment method defining a relationship among the mutual impedance between elements of the electronic apparatus, a wave source, and the electric current flowing through the elements and, here, is provided with a means for calculating the mutual impedance at a sampling frequency and calculating approximation coefficients for when expressing the mutual impedance by a defined approximation expression from the calculated value and the sampling frequency; a means for forming simultaneous differential equations by setting the calculated approximation coefficients and an initial value for the simultaneous differential equations derived by performing a Fourier transform on the simultaneous equations of the moment method into which the approximation expression has been substituted; and a means for calculating the electric current of the time domain flowing in a specified element by solving the formed simultaneous differential equations.

Simulation method and apparatus using a Fourier transform


An optical switch having a plurality of switch cells. The optical switch has n inputs (n is a natural number) and m outputs (m is a natural number). The optical switch has a unit size defined as the distance between any two adjacent ones of the switch cells. The optical switch comprises a substrate having a switch size of K×L (K is an integer satisfying n≦K, and L is an integer satisfying m≦L), first and second mirrors parallel to each other and perpendicular to a principal surface of the substrate, and an optical unit providing a plurality of input optical paths for the n inputs and a plurality of output optical paths for the m outputs. The plurality of input optical paths are inclined relative to the first and second mirrors, and the plurality of output optical paths are inclined relative to the first and second mirrors. Each switch cell comprises a switch mirror provided movably relative to the substrate. With this configuration, the path dependence of loss is substantially eliminated.

1. Field of the Invention
The present invention relates to an optical switch, and more particularly to an optical switch suitable for a node in a photonic network using wavelength division multiplexing (WDM).
2. Description of the Related Art
The development and commercialization of a wavelength division multiplexing (WDM) system are proceeding as a communication system that can greatly increase a transmission capacity. To construct a large-scale photonic network by connecting WDM systems, there has been examined a ring type network obtained by connecting nodes through optical fibers in the form of a loop.
In the ring type network, a transmission capacity in the loop increases with an increase in scale of the network. However, in each node, it is sufficient to perform processing using a relatively small-scale optical switch.
To the contrary, in a mesh type network, a transmission capacity in each route is small, but it is necessary to perform processing using a large-scale optical switch in each node.
Further, not only in the ring type network, but also in a point-to-point link system, an electrical switch is conventionally used to extract lower-order signals in the node. By substituting an optical switch for the electrical switch, a cost in the node can be reduced. Accordingly, the development of a large-scale optical network is proceeding in various types of networks.
A waveguide type optical switch is known as a conventional commercialized small-scale optical switch. The waveguide type optical switch includes a switch element and fiber arrays for inputs and outputs connected to the switch element.
To increase the scale of the switch element, the yield of each switch cell itself formed on the switch element must be increased. However, increasing the yield is relatively difficult because of narrow manufacturing tolerances. Further, loss is caused by a loss in each switch cell and losses at the connections between the input and output fibers and the switch element.
Accordingly, in increasing the scale of the waveguide type optical switch, it is necessary not only to improve the yield by improving the manufacturing method, but also to remarkably improve the performance of the switch element.
On the other hand, a configuration of spatially switching light is considered as a traditional technique. By using a reflection mirror as an element for changing an optical path, the problems in performance of the waveguide type optical switch, such as on/off ratio and crosstalk can be almost eliminated.
However, such a space switch is large in volume, and it is therefore difficult to increase the scale of the switch from the viewpoint of size.
To break through such circumstances, there has recently been developed a technique of reducing the size of this space switch by using a semiconductor technology. This technique is referred to as MEMS (Micro Electro Mechanical System), and it is also called optical MEMS in the case of application to the field of optics.
The optical switch using MEMS has a plurality of small mirrors formed on a substrate by a semiconductor fabrication technique, and performs switching of optical paths by selectively raising these mirrors by static electricity.
Information on MEMS may be provided by IEEE Photonic Technology Letters, Vol. 10, No. 4, APRIL 1998, pp. 525-527.
The optical switch using MEMS is superior in switch performance to a waveguide switch owing to the use of the mirrors, and has a small size like the waveguide switch. However, as will be hereinafter described, an optical path length differs according to a switching path, causing path dependence of loss. Further, when the optical path length increases with an enlargement in scale, an increase in loss due to beam spread also becomes a matter of concern because of spatial coupling.


A regenerative type air conditioning equipment in which the available concentration range of a heat accumulating liquid is widened, and the quantity of the heat accumulating liquid to be stored is decreased, so that the size of the equipment is reduced, with the conditioning equipment comprises a concentration difference regeneration device which, at least, cools a medium fed to an air conditioner, using a condensate liquid and a concentrated liquid produced by vaporizing the heat accumulating liquid, and a heat pump device which cools a coolant due to adiabatic expansion. The concentration difference regeneration device includes a container with a chamber for storing the condensate liquid, a spray nozzle which sprays the condensate liquid into the condensate liquid chamber, and an evaporator which vaporizes the sprayed condensate liquid under a low pressure. The heat pump device includes a heat exchanger which performs the heat exchange between the coolant and the medium to pass through the air conditioner, and an air cooling mode medium line in which the medium having passed through the air conditioner is circulated in the order of the evaporator, heat exchanger and air conditioner.

1. Field of the Invention
The present invention relates to an air conditioning equipment and a regenerative type air conditioning method wherein, for leveling electric power loads in the daytime and the nighttime, wherein, for example, heat is accumulated with night power so as to perform air conditioning and hot water supply in the daytime.
2. Description of the Related Art
For stabilizing the activity rate of a power plant, it has been desired to level day and night power loads. Especially in recent years when the day power load in an air cooling system in summer has become very heavy and when the capability of a power supply side has approached its limit, techniques for leveling the day and night power loads have been sought. In this regard, regenerative type air conditioning equipment has been proposed electric power generated in the nighttime is stored so as to derive it as energy for the air cooling in the daytime.
Regenerative type air conditioning equipment of the aforementioned type is proposed in, for example, Japanese Patent Application Laid-Open No. 218773, 1987, wherein adopts a concentration difference regeneration method is employed, with the equipment including a heat pump device having a compressor for adiabatically compressing a coolant, and a concentration difference regeneration device for performing air cooling and heating by a concentrated heat accumulating liquid and a condensate liquid that are produced by vaporizing the heat accumulating liquid. The concentration difference regeneration device includes a container provided with a chamber for reserving the concentrated heat accumulating liquid, and a chamber for storing the condensate liquid. The concentrated heat accumulating liquid chamber of the container is furnished with a concentrated heat accumulating liquid heat exchanger for effecting the heat exchange between the coolant adiabatically compressed and the concentrated heat accumulating liquid, and a spray nozzle for sprinkling the concentrated heat accumulating liquid into this concentrated heat accumulating liquid chamber, while the condensate liquid chamber is furnished with a condensate liquid heat exchanger for effecting the heat exchange between the coolant adiabatically compressed and the condensate liquid, and a spray nozzle for sprinkling the condensate liquid into this condensate liquid chamber.
With the regenerative type air conditioning equipment, in a heat accumulating mode, the coolant whose temperature has been raised by the adiabatic compression is passed through the concentrated heat accumulating liquid heat exchanger, to heat and vaporize the heat accumulating liquid. The remaining liquid is stored in the concentrated heat accumulating liquid chamber as the concentrated heat accumulating liquid. On the other hand, the vapor is introduced into the condensate liquid chamber and is condensed, whereupon the resulting condensate is stored in this condensate liquid chamber. In an air cooling or heating mode, the condensate liquid and the concentrated heat accumulating liquid are respectively sprayed by the corresponding spray nozzles, the sprayed condensate liquid is vaporized under a low pressure, and the sprayed concentrated heat accumulating liquid is caused to absorb this condensate liquid. Herein, in the air cooling mode, the latent heat of vaporization of the condensate is taken away from a medium having passed through an air conditioner, thereby cooling the medium, and the cooled medium is immediately fed to the air conditioner. In the heating mode, the medium passing through the air conditioner is heated by the heat of absorption developing from the concentrated heat accumulating liquid.
Additionally, the heat accumulating liquids of high and low concentrations are reserved in an identical reservoir. Whenever the heat accumulating liquid is to be drawn out of the reservoir, it is drawn out from the lower part of this reservoir, and whenever it is to be returned into the reservoir, it is returned thereinto from the upper part of the container.
In recent years, a large number of such regenerative type air conditioning equipment has been found in urban areas. In this regard, reduction in the size of the equipment is eagerly requested because of the influences of a sudden rise in the price of land, and so on.
Nevertheless, the regenerative type air conditioning equipment in the prior art cannot meet this request. More specifically, in the air cooling mode, the medium is cooled to a desired temperature by taking the latent heat of vaporization of the condensate liquid from the medium of the air conditioner, and the cooled medium is directly fed to the air conditioner. Therefore, the concentrated heat accumulating liquid which absorbs the vapor of the condensate liquid so as to vaporize this condensate liquid at a low temperature cannot be used until it turns into the heat accumulating liquid of low concentration. Accordingly, a large sized liquid reservoir is required.
Also, in the heating mode, the condensate liquid is vaporized merely under the low pressure condition without being heated, so that a low internal pressure of the container needs to be maintained. Therefore, the concentrated heat accumulating liquid cannot be used until there is a low concentration, and liquid reservoir is large in size.
Generally, a liquid of high concentration is higher in density than a liquid of low concentration, for this reason, when these liquids are received in an identical container, the high concentration liquid precipitates downwardly in the container. With the regenerative type air conditioning equipment in the prior art, even in the heat accumulating mode, the heat accumulating liquid is drawn out of the lower part of the reservoir, and the concentrated heat accumulating liquid is put into the reservoir from the upper part thereof. Consequently, the heat accumulating liquid which has been concentrated liquid into the high concentration precipitates downwardly, and it mixes with the heat accumulating liquid of the low concentration which is not concentrated, so that the heat accumulating liquid cannot be held at the high concentration. Therefore, the heat accumulating liquid having reached a somewhat high level needs to be reserved in a comparatively large amount, and the reservoir of the heat accumulating liquid necessarily becomes large sized.
In this manner, the regenerative type air conditioning equipment in the prior art has a problem in that, since the available concentration range of the heat accumulating liquid is narrow, the quantity of this heat accumulating liquid which needs to be reserved is large, thereby increasing the size of the equipment.
Moreover, the regenerative type air conditioning equipment in the prior art has a problem in that, since a concentrating operation and a diluting operation at different temperature levels are carried out in the identical container, the start stage of the concentrating operation requires surplus heat until the container is heated, whereas the start stage of the diluting operation is incapable of deriving a predetermined temperature for the air cooling until the container is cooled.


The invention involves the production of a catalyst that contains (1) at least one refractory inorganic oxide support, (2) at least one iron oxide, and (3) at least one cerium oxide, (4) at least one metal A, for example, from Groups VIB, VIIB, VIII, and IB of the Periodic System and, optionally (5) at least one compound of metal B, for example, from Groups IA, IIA, the rare-earths group, and Group IVB of the Periodic System, deposited in the form of a porous layer ("washcoat") on a ceramic or metal substrate:. (a) atomizing an aqueous suspension of at least one powder of the refractory inorganic oxide, cerium salt, iron salt, and optionally salt of the metal B; and/or A PA1 (b) resuspending the resultant powder and adding any remainder or all of the compound of metal B, as well as, optionally at least one bonding agent and, optionally at least one mineral acid or organic acid; PA1 (c) coating a ceramic or metal substrate is coated with the suspension obtained in step (b); PA1 (d) calcining the resultant coated substrate; PA1 (e) impregnating the resultant coated and calcined substrate with any remainder or all of the precursor of metal A; and PA1 (f) thermally activating said coated, calcined, and impregnated substrate coming from step (e).

This invention has as an object a process for producing automotive post-combustion catalysts on metal or ceramic substrates or other refractory inorganic materials. It also has as its object the catalysts obtained by this process.
These catalysts can be used, for example, in the treatment of exhaust gases from internal combustion engines with controlled or non-controlled ignition, operating with a liquid fuel, a liquified petroleum gas (LPG), or a compressed natural gas (CNG).
For monolithic substrates having a beehive (or honeycomb) structure or obtained by stacking of metal strips or else produced by the interlocking of fibers, either metal or ceramic, to be able to receive a well-dispersed, catalytically active phase (generally precious metals) (the catalytic activity generally being proportional to the exposed metal surface area), it is important that the specific surface area of such substrates (which is almost the same as the geometric surface area and is equal to several m.sup.2 per liter of substrate) be substantially increased. Covering the surface of the substrate with a refractory inorganic oxide having a large surface area (100-200 m.sup.2 /g) is one way to accomplish this.
Other criteria also have to be met in order for the catalyst to perform well: actually, to keep the performance of the catalyst from being excessively diminished by rapid and intermittent changes in operating conditions, or to impart a certain stability to the catalyst (thermal stability of the substrate and/or of the catalytic phase, reduced sensitivity to potential poisons), it is desirable to add to this inorganic oxide of large surface area compounds that are able to attenuate the extent of these detrimental effects.
It is well known that cerium and iron oxides (particularly U.S. Pat. No. 4,378,307 and U.S. Pat. No. 4,294,726) or other oxides such as those of rare earths or of alkaline-earth metals or else of zirconium (U.S. Pat. No. 4,587,231 or U.S. Pat. No. 4,791,091 or FR-A-2568143) can provide such improvements. In general, these agents are introduced either in the form of pigments in the coating suspension or by impregnating precursor salts on the refractory oxide before being put into suspension, or by impregnating the coated monolith.

Process for preparing a catalyst suitable for the treatment of exhaust gases from internal combustion engines


An apparatus for printing bead spacers at selected locations on an LCD substrate includes a cylindrical transfer roller and a printing plate having a plurality of semispherical recesses respectively located at positions corresponding to the selected locations of the spacers on the LCD substrate. A volume of an ink containing the spacers is loaded into each of the recesses, and the substrate is translated tangentially relative to the rotating transfer roller such that the volumes of ink are transferred onto the roller. A support plate having the LCD substrate mounted thereon is then translated tangentially relative to the roller such that the volumes of ink on the roller are transferred onto the surface of the LCD substrate at the selected locations. The apparatus enables the spacers to be printed onto the LCD substrate accurately and inexpensively, and prevents the spacers from being inadvertently printed in double layers.

The present invention relates, in general, to apparatus for manufacturing liquid crystal displays (LCDs), and more particularly, to apparatus for printing bead spacers at selected locations on LCD substrates.
An LCD, which is one of the more widely used types of flat panel displays, includes two substrates, or panels, having electric field generating electrodes, i.e., pixel electrodes and a common electrode, with a liquid crystal layer interposed therebetween. The LCD displays an image by applying a voltage to the electrodes to generate an electric field in the liquid crystal layer to selectively align the molecules of the liquid crystal layer and thereby control the polarization of light passing through the layer.
Upper and lower substrates of the liquid crystal display apparatus are attached to each other by means of a sealing member formed around the respective peripheries of the substrates to confine the liquid crystal material in the space between the two substrates. The upper and lower substrates are supported relative to each other by a plurality of spacers disposed between the substrates that define and maintain a selected cell gap, or spacing, between the two substrates.
The spacers can comprise either "bead-type" spacers having a generally spherical shape, which are distributed between the substrates in a random, or irregular pattern, and columnar spacers that are distributed between the spacers in a regular pattern.
The columnar spacers are formed by coating a photosensitive film on a color filter panel of the LCD and then exposing and developing the film such that the spacers are distributed in a desired pattern corresponding to channels, gate lines, storage electrode lines, light blocking members, or other regions of the panel through which light is not transmitted. Accordingly, when columnar spacers are used in an LCD, a separate, additional photolithography process is needed, so that the production cost of the panel increases correspondingly. Additionally, unlike the plastic-based bead spacers, the columnar spacers have a relatively low elasticity, such that the margin for liquid crystal filling errors is reduced. Thus, use of columnar spacers can result in LCD panel charging problems as well as smearing of underlying layers of the panel.
On the other hand, while the irregularly distributed bead spacers do not require an additional photolithography process, the bead spacers can be located in light transmitting areas of the panel, and thus, act like extrinsic materials to cause leakage of light from the panel, thereby causing a deterioration in the light contrast of the panel. Additionally, it is possible for a portion of the bead-type spacers to move slightly during placement, and thereby cause damage to an alignment layer of the panel. Further, it is possible to inadvertently deposit the bead spacers in stacked, or double layers, such that the substrates of the LCD are spaced too far apart at some locations.
What is needed, then, is a technique that enables the less expensive bead-type spacers to be deposited on LCD substrates at precise, selected locations thereon, and which prevents the spacers from being deposited in thicknesses greater than a single layer of the spacers.

Apparatus and method for printing bead spacers on a liquid crystal display substrate comprising a planar printing plate having recesses including a radial protrusion disposed at center


A network system having a client, a content server, application servers and a proxy server is described. The proxy server relays content and data between the client, the content server and the application servers upon a request for content from the client. The application servers process the requested content in accordance with pre-established signature and content verification requirements before the content is relayed to the client. The applications servers also provide signature and content verification management for the network.

In a network system wherein content existing on a server can be accessed from clients connected to the server through communication lines, the present invention relates to a proxy server that relays data to be communicated between the server and the clients, and a system using the proxy server.
It has been come into popular use for end users to download computer-executable programs and files of music and moving pictures, using a protocol called Hypertext Transfer Protocol (HTTP), and run programs or play music and moving pictures on the end users' personal computers. In this way of getting programs and information files over a network, it is an important problem to assure providing user terminals with security. It is possible that, for example, a malicious third party invades a Web server on the Internet and alters data of content (for example, a moving picture file or computer-executable program) existing on the server to program data polluted with a computer virus. In that event, when a user downloads the program to the user's terminal unconsciously and run the program, trouble will happen that data stored on the terminal is corrupted or that the user personal important information that should be secret is transmitted over a network freely by the malicious third party. As countermeasures against such trouble, a virus detection program is used to detect and eliminate computer viruses. The countermeasures using the virus detection program may be taken in the following two manners.
One method is running the virus detection program on end user's terminals or a Web server. Another method is running the virus detection program on a proxy server or a fire wall, wherein content being downloaded to a user terminal is checked for viruses in real time. A Web proxy is a Web communications intermediary technology via which Web data is transmitted from a server to a client. Description of the Web proxy is provided in Sections 1.3 and 1.4, R. Fielding, et al. RFC 2616 "Hypertext Transfer Protocol—HTTP/1.1" June, 1999, The Internet Society, <URL:http://www/ietf.org/rfc/rfc2626.txt>. The latter method in which virus detection is performed on the network is suitable for communication carriers that provide Internet connection services in providing users with security services as well.
As an advanced version of the latter technology, a Web proxy verifies digital signatures, as described in PCT Gazette WO 00/64122. According to this art, tampered content is detected as follows. First, a digital signatures to all content items stored on a Web server are generated beforehand. When content is downloaded via the Web proxy, the Web proxy verifies that the content being downloaded is authorized, using its digital signature. The digital signatures are generated and stored in a storage of the Web proxy beforehand. If authorized content is verified, the content is sent as is to the user that requested the content. If tampered content is detected, the Web proxy returns an error message or sends its original content stored beforehand on it to the user.
In the former method, it is difficult to install the virus detection program on all user terminals connected to the network. If a mobile phone is used as such a terminal, it is impossible to run the virus detection program on it. Even if virus check is performed on the server, there is a possibility of the checked data being polluted with a virus when it is routed over the network.
In the latter method by which the Web proxy performs virus detection, because the proxy at which traffic on the network rushes must perform the task of virus detection that is a heavy processing load, the processing performance of the proxy itself becomes very low. Another approach has been proposed in which the virus detection program runs on another server connecting to the proxy and data is exchanged between the server and the proxy. Even for this approach, the processing performance of the server on which the virus detection program runs is also a bottleneck.
In the art disclosed in WO 00/64122, because the proxy does not perform the virus scan, its processing load is reduced. However, increase in its processing load for decrypting digital signatures is inevitable.
As described above, the approach that an intermediary device on the network, instead of the server, performs additional processing of content being downloaded from the server to a client involves the problem that its processing load becomes too heavy.
Another problem also exists. The sequence of downloading a plurality of contents cannot be checked by prior art, even though such check would be desirable. For example, when a content and its metadata are downloaded, it cannot be checked whether the content is downloaded after the metadata is downloaded.


Embodiments of the present invention provide a method and a node for discovering topology structure automatically in a Multi Protocol Label Switching (MPLS) ring network. The method includes: when receiving a topology discovering message, determining, by a node in the MPLS ring network, whether the topology discovering message is sent by the node; if yes, updating information of topology structure of the MPLS ring network stored in the node according to information of topology structure of the MPLS ring network carried by the topology discovering message; otherwise, appending information of topology structure of the node to the topology discovering message and forwarding the topology discovering message to a next node. Thus, the network topology may not depend on the topology of the physical layer network and the speed of discovering topology structure of the ring network is increased.

With the development of communication network technologies and the rapid popularization of the Internet, categories, formats and service demands of network information flows become more and more abundant, and the data transport network gradually becomes unable to deal with the dispatching and switching of services of the transport layer effectively. The primary technologies adopted in the data transport network are the Synchronous Digital Hierarchy (SDH) technology, the Asynchronous Transfer Mode (ATM) technology, the Multiple Service Transport Platform (MSTP) technology and the Wave-length Division Multiplexing (WDM) technology. Therefore, the transport network urgently needs a transport ring network technology which can carry multiple types of services uniformly, provide better Quality of Service (QoS) and be extended flexibly, and is applicable to both the Metropolitan Area Network (MAN) and the Wide Area Network (WAN). In this case, a ring network based on an MPLS protocol appears.
The key of the MPLS protocol is the introduction of a Label, whose information content is short and easy to be dealt with, with local meaning and without topology information. The Label is short, thus easy to be dealt with, and may be cited directly by an index generally, and since the Label only has the local meaning, it is easy to be assigned.
In an MPLS network, a packet is encapsulated with the Label by an MPLS edge device when entering a first MPLS device. The MPLS edge device selects an appropriate Label for the packet by analyzing the content of the packet. Specifically, the MPLS edge device analyzes not only destination address information in the header of the packet but also other information in the header of the packet. And, all the nodes in the MPLS network determine whether to forward the packet according to a Label assigned. Thus, the MPLS network forwards a packet much faster than an IP network does. The Label will be separated by an edge device when the packet leaves the MPLS network.
Such a new MPLS network of ring type that applies to the transport layer is referred to as an MPLS ring network. To guarantee the reliable operation of the MPLS ring network, it requires that the MPLS ring network have a function of discovering topology structure automatically to enable each node in the network to acquire states of other nodes in the network in real time. However, there is not a perfect function of discovering topology structure automatically in the MPLS ring network yet at present.

Method and node for discovering topology structure in multiprotocol label switching ring network


A bidirectional pentaplex system is connected to a machine room. The machine room provides a first optical signal, a second optical signal and a monitoring signal and transmits to the bidirectional pentaplex system. The bidirectional pentaplexer includes a first receiving unit, a second receiving unit, a first emitting unit, a second emitting unit, a filter, a transceiver, a grating, a plurality of reflecting units and a control circuit. The receiving units and the transceiver respectively receives the signals, then the control circuit controls the emitting units emitting the feedback signals and transmits the feedback signals back to the machine room.

(1) Field of the Invention
The invention relates to a bidirectional pentaplex system, and especially relates to a bidirectional pentaplex system and method thereof.
(2) Description of the Prior Art
With the enhancing penetration of global broadband Internet, the currently triple play service containing voice, data and multimedia service replaces the data service as the core in the past. In the provisioning of broadband networks, in addition to the carriers that active in the construction, the Multiple System Operator (MSO) also offers a video, Voice over Internet Protocol (VoIP) and broadband Internet services to users through the Hybrid Fiber Coaxial (HFC). The appearance of Radio Frequency over Glass (RFoG) allows MSO can use the backstage equipment of traditional HFC continually, and then transmits cable television signals and broadband Internet service to the optical network unit through the fiber that can provide triple play service. It can improve the disadvantages of HFC, and reduce equipment replacement costs.
At the moment, many manufacturers combines Bi-directional Optical Sub-Assembly (BOSA) with Triplexer to apply for RFoG and Gigabit Passive Optical Network (GPON) or Gigabit Ethernet Passive Optical Network (GEPON). However, its main function is to design the operational wavelength in single Internet which applied for RFoG or GPON/GEPON. For the RFoG and GPON/GEPON integrated in the same passive optical network architecture, it doesn't have any integrated device that can transmit and receive different wavelengths by wavelength division multiplexing.

Bidirectional pentaplex system and method

NATIONAL TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY


A process for making powder-free medical gloves that are nevertheless easy to don involves first forming a glove on a form by successively dip-coating layers of a coagulant containing acid-soluble powder dispersed throughout, an elastomer, and an antiblocking composition with particles distributed throughout. After curing the elastomer and applying a silicone coating, the glove is removed from the form and treated successively with acid, to dissolve the powder, and with bleach, to reduce blocking. Using this process, high quality natural rubber medical gloves can be produced.

1. Field of the Invention
This invention relates to a process for making medical gloves that are substantially free of loose powder but are nevertheless easy to don.
2. Description of the Related Art
Medical gloves generally have to conform tightly to the hand of the wearer. That requirement makes it hard to don the gloves, unless they have a lubricant on their inner (skin-contacting) surface. Powder of one form or another has traditionally served this lubricating function; however, post-operative complications, such as adhesions, peritonitis, and granuloma formation have been attributed to the use of loose powder on surgical gloves and other items used in surgery.
To avoid the potential complications, there have long been efforts to reduce or eliminate the need to use powder to facilitate donning of medical gloves. A number of approaches have been tried, including halogenating the gloves, blending rubber and resin latex, and depositing granular material on the inner surface of the gloves. These attempts, and their drawbacks, have been summarized in U.S. Pat. No. 4,143,109, issued on Mar. 6, 1979, to Stockum, and the disclosure of that patent is incorporated herein by reference. Stockum's patent discloses yet another approach to avoiding the need to use loose dusting powder to permit easy donning of gloves. His approach involves having an inner layer of the glove that is bonded to the outer, elastomeric layer. The inner layer has embedded in it particles that are distributed throughout and that are greater in size than the thickness of the inner layer. Thus, the particles protrude from the inner surface, while remaining secured to the surface and not being easily abraded off. A problem with that approach is that the number of particles to be contained in the inner layer has to be carefully controlled. If too few particles are embedded, donning remains difficult. If too many particles are used, some loose particles could remain and could possibly cause the undesirable medical effects.
Another approach to facilitating medical glove donning is disclosed in U.S. Pat. No. 4,499,154, issued on Feb. 12, 1985 to James et al. That approach makes use of a skin-contacting coating of a lubricating hydrogel bonded to the inner surface of the glove and treated with a surfactant to improve its lubricity. However, it is not capable of providing gloves that are as easy to don as powdered gloves.

Process for forming powder-free medical gloves


A conditioner and a method are disclosed for the production of food or animal foodstuffs. The conditioner includes at least one detention element and a mixer which is located thereabove, and is provided with a dosing element. The mixer and the detention element have the same face plates enabling them to be connected to each other on at least one front side.

The present invention relates to a conditioner, in particular for the production of conditioned foodstuffs or animal foods.
Conditioners are used individually as processors or in conjunction with pressing or expander plants in the preparation of animal foodstuffs or foodstuffs. These are generally mixers, in which a product for processing is processed over a certain period thermally or hydrothermally. This processing serves to render the products hygienic, and to improve the nutritional value and/or the product structure.
Such mixers are known for example from EP-B-231764 and EP-B-610789. In this example a dosing device is connected upstream of such a mixer and a compression mould or an expander is supplied from the mixer. The mixer is provided with a heating mantle and contains a rotating shaft, which is equipped with mixing and conveying elements.
Such units are either tailored to use in pressing or expander plants, or can be used stand-alone only, since the expense of adapting them is high.
According to EP-B-610789, for warming the product-guiding parts and units, an air cycle is provided with a ventilator, a connecting line, an air heater, a lower air connection arranged on the side of the product output channel with an air inlet channel, an air input channel with an upper air connection arranged on the side of the product supply channel, whereby the air is guided from the product output channel via the compression mould, the product supply channel, the feeder and mixer to the products input channel.
Solutions to energy recovery are also known in processors, in which for example the waste heat of an expander plant is utilized.


An image processing apparatus includes an image reading unit 3 that reads a front side image and a rear side image from a front side and a rear side of a medium, respectively, a mark detecting unit 42 that detects a combination instruction mark present in a predetermined position of at least one of the front side image and the rear side image, and an image combining unit 44 that combines, when the combination instruction mark is detected, a front side sliced image and a rear side sliced image sliced from predetermined positions of the front side image and the rear side image in a predetermined direction to obtain one image.

In an image processing apparatus in which an image reading apparatus such as a scanner is connected to a personal computer, there has been proposed a method of reading an original of a size (for example, A3) larger than a readable size (for example, A4) of an original mainly considering a setting area for the scanner (see, for example, Patent Document 1). In this example, after folding one original into two to read images, the images are combined to obtain original one image.
Note that it is proposed to hold an original between a pair of transparent carrier sheets in order to surely and easily read an original having images printed on both sides (see, for example, Patent Document 2). In this example, the images on the front side and the rear side are not read substantially simultaneously. The original is reversed together with the carrier sheet to read the image on the rear side after the image on the front side is read.
Patent Document 1: Japanese Patent Laid-Open No. 7-283933
Patent Document 2: Japanese Patent Laid-Open No. 11-32160

Image processing apparatus and method for using mark detection to combine multiple images present on the front and rear surfaces of a medium


Disclosed is a task map providing apparatus for displaying one or more tasks, the apparatus including a memory and a processor electrically connected with the memory. The processor may be configured to generate the one or more tasks by receiving, from a task instructor who instructs recording a note through the one or more tasks, information on a task performer instructed to record the note corresponding to the one or more asks, generate progressive bars to correspond the one or more tasks, the progressive bar representing how many days have passed and remain with respect to a note recording due date by which the task performer needs to record the note.

The present disclosure relates to a work management technology and more particularly to a technology for providing a work progress informing tool by providing a task map in a manner in which visual information for multiple tasks required for one task is provided on one screen so that arrival of due dates may be notified and schedule management may be possible.
An existing task management program has provided a function of displaying a list of entire tasks to improve task management efficiency. In addition, a technology of transmitting a reminder upon due date setting has been already used. This is to set a due date of a specific task and provide a reminding messages to a user based on the due date. However, when providing the reminder, the existing technology does not reflect a situation of a recipient, which may change in real time, or a progress status of a task. In particular, there is a drawback that the overall progress status of multiple tasks occurring simultaneously cannot be provided in an intuitive way.

Task map providing apparatus and method thereof


An organic light emitting display apparatus includes a substrate, a display portion on the substrate, the display portion including a plurality of emission regions, each including an organic light emitting diode (OLED), and a plurality of non-emission regions protruding from between the plurality of emission regions, an encapsulation substrate facing the substrate, a sealing material bonding the substrate and the encapsulation substrate and sealing the display portion, and a filling material on a surface of the encapsulation substrate facing the display portion, the filling material being spaced apart from the OLED and being formed of a cured polyimide (PI).

1. Field
Embodiments relate to an organic light emitting display apparatus and a method of manufacturing the organic light emitting display apparatus, and more particularly, to an organic light emitting display apparatus including a filling material and a method of manufacturing the organic light emitting display apparatus.
2. Description of the Related Art
Recently, display apparatuses have been replaced with portable thin flat panel display apparatuses. Among the flat panel display apparatuses, organic or inorganic light emitting display apparatuses are self-emissive display apparatuses having wide viewing angles, excellent contrast ratios, and high response speeds, and thus, are regarded as next-generation display apparatuses. Also, an organic light emitting display apparatus, including an emission layer formed of an organic material, has excellent luminosity, driving voltage, and response speed characteristics compared to inorganic light emitting display apparatuses, and may provide a color image.

Organic light emitting display apparatus and method of manufacturing the same


A device for removing body hair, which includes a housing a hair-plucking portion which is rotatably mounted to the housing. The hair-plucking portion includes one or more disc assemblies, each of which includes a pair of complementary discs, each of which has one or more radially extending arms which terminate in a flattened peripheral portion. When the corresponding portions of the two discs are pressed together, they form a trap for the hair. The disc assemblies also include a hub which accommodates a pair of discs, one on each of its axial faces. The hub has shoulders for engaging the arms of each of the discs so as to impart rotational motion to the discs upon the rotation of the hub. The hub also has at pairs of protrusions which extend axially beyond the plane of arms of each disc. The hub further has an edge which is perpendicular to its axis such that each pair of arms of the pair of discs is pivotable about the edge so as to alternately bring the corresponding flattened peripheral portions of the discs together to form a trap and apart to eject the removed hair. The hubs may be mounted on a fixed curved shaft and may be connected so that each hub transfers the rotational motion to the adjoining hub. Alternatively, the hubs may be mounted on a rotatable straight shaft which imparts rotational motion to each hub.

The present invention relates to depilatory devices for removing body hair and, more particularly, to devices for removing unwanted body hair by uprooting the hair.
A large number of depilatory devices have been proposed through the years. Depilation can be effected in one of two basic processes. In one process, implemented by shavers of various types, strands of hair are cut, typically in the vicinity of the skin, leaving the roots intact and in place beneath the skin surface. In the other basic process, which will henceforth be referred to as `hair removal`, hair is removed without cutting the strands, typically by vigorously pulling the hair strands so as to uproot the hair and remove the entire hair, including the roots.
In a number of applications, such as in the depilation of women's legs, it is considered preferable to uproot hair rather than to cut it since the removal of the roots considerably slows, and to some extent permanently thwarts, the growth of replacement hair, and leaves the skin relatively smooth and virtually free of hair for relatively long periods of time. By contrast, cutting the hair, as by shaving, does nothing to interrupt or disrupt the hair growth and often leads to the early appearance of unsightly stubble as the cut hairs continue to grow.
Processes for the mechanical uprooting of hair generally involve grasping one or more strands of hair and vigorously pulling on the hair so as to remove the entire hair, including its roots. Care must be taken that the hair thus grasped and pulled is not inadvertently cut in the process. Care must also be taken to ensure that the pulling of hair occurs sufficiently quickly that the user does not sense an unacceptable amount of pain or discomfort. As may well be appreciated, everything else being equal, the quicker the pulling action, the less painful is the uprooting.
Various devices for accomplishing hair removal have been described and reviewed in my earlier U.S. Pat. Nos. 4,935,024 and 5,057,115 which are incorporated herein by reference for all purposes as if fully set forth herein.
Several of the proposed hair removal systems involve the use of tilted discs which come together at a point to grasp one or more strands of hair. In such systems, strands of hair are grasped at the point where the two discs momentarily come together and are pulled as the discs continue to rotate. Further rotation of the discs causes the distance between the discs to increase, allowing the uprooted hair to drop from the device.
Such systems generally suffer from at least two disadvantages. First, the pinching of a strand of hair at the point of contact between the two discs often results in the undesired cutting of the hair, rather than in its desired uprooting. Second, since the discs are only in contact momentarily and at a single point, a hair which is grasped at the point of contact will be released soon thereafter as the discs continue to rotate. Often, such release will occur before the hair has been displaced sufficiently to be uprooted. The result is that the hair will remain in place, firmly attached to the skin by its root. Such a phenomenon is unfortunate since, not only does the hair remain in place unremoved but the user has also had to suffer needless discomfort or even pain as the hair was pulled partially prior to being released.
Other of the proposed hair removal systems involve the use of cams to alternately bring discs, or similar members, together and apart periodically to effect the grasping and releasing of strands of hair. In some cases, the discs or other members are flattened at their outer periphery so as to provide a region where hairs can be grasped which is larger than the single point afforded by a pair of ordinary discs. All such cam-based systems suffer from the disadvantage that the use of cams induces an undesirable vibration in the device, which is transmitted to the user and reduces his or her level of comfort.
In addition, some cammed systems involve the slight displacement of the traps from their undisplaced position, such the trap is effected in a location which is slightly displaced from where the trap elements were prior to the formation of the plate. A difficulty with this arrangement is that shorter hairs which are initially introduced into the trap area may escape the trap before the trap is closed because of the slight displacement of the trap elements.
Efforts have been made to increase the size of the regions over which hair can be grasped by using discs or similar elements which are in some sense resilient. One such system is disclosed, for example, in U.S. Pat. No. 4,807,624. However, such systems are also not free from difficulties. Specifically, since such a system has a certain amount of resiliency, or `give`, once hair has been grasped, the grasping member has a tendency to be pulled by the hair toward the skin. This prolongs the act of uprooting the hair and accordingly increases the amount of discomfort or pain experienced by the user.
Recently, Philips N.V. has been marketing a hair remover under the name of New Satinelle which attempts to overcome many of the above-described limitations. The Philips device features a number of discs which are stacked on a rotatable assembly made up of three straight parallel shafts. The two end walls which touch the outer discs, which are different in construction from the intermediate discs, are angled so as to tilt one portion of each of the outer discs approximately perpendicular to the shafts. Each of the discs of the Philips device is made up of a metal portion and a complex integral plastic portion which includes a number of complicated protrusions and recessions designed to transfer the tilt of the outer discs to the intermediate discs. The tilt produces regions where adjoining discs alternately come together to form a temporary trap for the hair and move apart to release the uprooted hair.
While the Philips device appears to overcome several of the disadvantages of the previously known systems, the device displays at least three difficulties. First, the Philips design calls for the use of two different disc assemblies, which unnecessarily complicates the assembly and maintenance of the unit. Second, close inspection of the Philips disc assembly reveals that the assembly provides only one hair trap per rotation of each disc, which makes it necessary to use a relatively large number of rather closely-spaced discs. Finally, it is to be noted that the Philips device is asymmetrical and operates properly only when the discs are rotated in one sense and not the other.
There is thus a widely recognized need for, and it would be highly advantageous to have, an inexpensive and rugged hair removal device which is capable of efficiently grasping hair over a large trap area, without undesired displacement, and which can then hold the trapped hair long enough to quickly, and relatively painlessly, uproot the hair, which device will provide a relatively large number of traps per rotation of each disc, will be symmetrical and therefore function equally well in either rotational sense, and will make use a plurality of disc assemblies which are all identical, for easy assembly and maintenance.


A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.

Error detection and correction codes are codes utilized in a wide variety of digital electronic systems to detect and correct errors in stored and communicated data. Using such codes, the value of one or several erroneous bits can be restored to a correct value or values after a storage or a transmission
FIG. 1 is a block diagram of a typical memory system 10 including memory 8 for storing data, where the term data includes any type of stored information including program instructions and data generated by or associated with such instructions. When the memory system 10 stores a data word 2, the data word is first presented to error correcting code (ECC) logic 4 before being written into the memory 8. The ECC logic 4 generates error checking and correction bits using the data word 2, and these additional error bits are then stored in memory 8 along with the data word 2. In the following description, the error detection and correction bits may be referred to as check bits, and the original data word 2 in combination with the check bits may collectively be referred to as a code word. The data word 2 and check bits are stored in specific locations in the memory 8 as programmed by redundancy logic 6 which redirects data to redundant storage locations in the memory to thereby replace defective storage locations, as will be described in more detail below. In this way, the redundancy logic 6 replaces defective storage locations to which data was initially directed with redundant storage locations, as will be understood by those skilled in the art. When data is subsequently read from the memory 8, the data is again presented to the ECC logic 4 to ensure the data as read is the same as the data word 2 initially stored in the memory.
The memory 8 is designed to maximize the number of bits available (storage capacity) without sacrificing too much memory speed (the time it takes to store or access the data). Thus, memory cells that store individual bits are packed as closely together as possible through a variety of different techniques, such as by reducing the number of transistors per memory cell and by making the transistors smaller. Typically, the smaller a memory cell the longer it takes to access the cell due to the small voltages and currents that must be properly sensed. Thus, there is a trade off in using more and larger transistors to increase the speed of the memory 8 but at the same time reducing the storage capacity of the memory. As a result, the memory system 10 typically includes a combination of relatively slow but high-capacity memory cells such as dynamic random access memory (DRAM) cells, and also includes lower-capacity but faster memory cells such as static random access memory (SRAM) cells.
An array of memory cells includes a plurality of rows and columns of memory cells, with an address being associated with each memory cell in the array. In high-capacity arrays such as those formed from DRAM cells, the address is typically divided into a column address and a row address. The row address is typically sent first, and in response to the row address the data stored in an entire row of memory cells in the array is sensed and stored in circuitry in the memory 8. The column address is provided to the memory 8 after the row address, and selected ones of the memory cells in the addressed row are selected in response to the column address. If data is being fetched from a series of consecutive column addresses within the same addressed row of memory cells, the data stored in these consecutive columns of memory cells can be accessed from the circuitry that previously sensed and stored the data of the addressed row.
The memory 8 is typically manufactured with spare or redundant bits, and the redundancy logic 6 is programmed to substitute any defective memory cells with redundant memory cells. The redundancy logic 6 is typically programmed during initial testing of the memory 8. Referring to FIG. 2, the memory 8 of FIG. 1 is considered as a memory array 12 of rows and columns of memory cells (not shown). The main approaches to the substitution of defective memory cells in the array 12 with redundant cells utilize laser blown fuses, electrical fuses, or one-time-programmable MOSFETs. Laser fuse based repair is still a common approach, although this type of repair increases test costs substantially since a 3-step test process of test, laser repair, and retest is required. Electrical fuse based repair can be performed as a single process using a tester, which tests, electrically repairs, and retests while the memory 8 is coupled to the tester.
The repair process for substituting redundant memory cells for defective memory cells typically consists of identifying the proper laser programmable fuses, electrically programmable fuses, or one-time-programmable MOSFETs needed to deactivate a defective column 14 of memory cells, deactivating the defective column or group of columns containing a defective cell or cells), activating a redundant column 16 or group of redundant columns of memory cells, and programming the redundancy logic 6 to assign the array address corresponding to the defective column 14 to the address of a redundant column 16. After the defective column 14 is disabled and the redundancy logic 6 programmed, whenever the defective column 14 is addressed the redundant column 16 will be accessed instead, allowing data to be read from and written to the memory cells in the redundant column 16. In this way, every time a subsequent read or write operation addresses the defective column 14, the redundant column 18 is accessed instead of the defective column. The circuitry, operation, and processes for redundancy programming to replace defective memory cells with redundant cells is well understood by those skilled in the art, and thus will not be described in more detail.
Modern computer systems typically contain hundreds of megabytes (MB) of memory for storing programming instructions and associated data. With so much memory now being contained in computer systems, the likelihood of defective memory cells has increased. For example, 128 MB of DRAM is a typical amount contained in present personal computer systems. Each byte of memory typically includes 8 bits and thus is stored in 8 individual memory cells. Accordingly, there are over 1×109 DRAM memory cells required to store the desired 128 MB of data. Moreover, these DRAM memory cells are typically accessed hundreds of millions of times per second. Given such a large number of memory cells and the frequency with which the cells are accessed, the probability that an error will occur in data being read from or written to the memory cells is fairly high.
As previously mentioned, the ECC logic 4 adds error bits to the stored data word 2, with the error bits being redundant information that allows errors in the data stored in the memory 8 to be detected and in some cases corrected. Referring again to FIG. 1, the ECC logic 4 performs error-correcting operations on data words 2 used by application programs (not shown) accessing the memory 8. In general, referring to FIG. 3 a typical embodiment of the ECC logic 4 is shown in more detail to describe the conventional way errors are detected and corrected. A data input signal DI, which corresponds to the data word 2 in FIG. 1, is a word M bits long and there are an additional K bits added to the word that are used to detect and correct data bit errors. An encode function 72 is the algorithm used to generate or properly set the additional K bits based upon the original M bits. After encoding of the data word DI by the encode function 72, M and K are both stored in memory 8. At some subsequent time, M and K are both read from memory 8, such as by an application program, and the read M bits are presented to a buffer 80 in a corrector unit 78 and are also presented to an encode function 74, which is identical to encode function 72 and generates K bits based on the bit values of the read M bits. The compare unit 76 compares the K bits generated by encode function 74 to the K bits read from memory 8. If the two sets of K bits have identical values the compare unit 76 signals the corrector unit 78 to release the M-bits from buffer 80 without change as a data out signal DO. If, however, the compare unit signals the corrector unit 78 that the two sets of K bits have different values, the corrector unit corrects the M bits in buffer 80 based on a correction algorithm and then releases M from buffer 80 as corrected as the data out signal DO. The compare unit 76 also generates an error signal ES in this case, which is utilized by other circuitry (not shown) in the memory system 10 (FIG. 1).
The ECC logic 4 may execute a variety of different error detection and correction algorithms. One common algorithm is an algorithm that utilizes a code known as a Hamming code, which is an error detection and correction code used in many fields. An example of a Hamming code and its use for data storage in a memory 8 will now be described in more detail for the case where the data words 2 to be stored are 16-bit words. Let X be the data word 2 to be stored. X can be represented by a vector Xe, the 16 components X0 to X15 of which correspond to the 16 bits of the data word 2 to be stored. Five error check bits C1(C0 . . . C4) are obtained by multiplying a parity control matrix H called a Hamming matrix, of dimensions 5×16, by the vector Xe in the form of a column vector.
FIG. 4A illustrates the Hamming matrix H for 16 bit data words 2 and the corresponding vectors Xe, and FIG. 4B illustrates the way to obtain the error check bits C1 by performing matrix multiplication of H*Xe. Calling hij the elements of matrix H, the error check bits C1 are given by:
            C      i        =                  ∑                  j          =          0                15                                    h          ij                *                  X          j                      ,with Xj being the jth component of vector Xe.
During a write data transfer, 21-bit words formed by the 16 data bits Xj forming the vector Xe and by the 5 check bits C1 generated from the matrix H and the vector Xe are written into the memory 8. In a read data transfer, the read word includes 16 bits Xr corresponding to the data bits read from the memory 8 and 5 bits Cr corresponding to the check bits read from the memory. It is possible for Xr and Cr not to be equal to Xe and C1, respectively, if errors have occurred between the write and read data transfer operations.
To detect and/or correct possible errors in the read bits Xr and Cr, a syndrome S with five components S0, . . . S4 is calculated by multiplying a determined matrix H′ of dimensions 5×21 by a read column vector or "read word" with 21 elements formed by the 16 bits Xr and the 5 check bits Cr.
FIG. 5A illustrates the matrix H′. The first 16 columns and all 5 rows of matrix H′ correspond to the 16 columns of matrix H as indicated by the dotted lines. The 5 following columns, namely columns 17-21 each include a single "1" on a diagonal from the top left column to the bottom right column as shown. Thus, the 17th column has its "1" in the first row, the 18th column has its "1" in the second row, and so on until the 21st column, which has its "1" in the fifth row. These last five columns of the matrix H′ form a 5×5 identity matrix and are used to determine possible errors in the check bits Cr.
FIG. 5B illustrates the calculation of a syndrome S.
If syndrome S has all its elements equal to 0, the storage of the read word formed by the 16 bits Xr and the 5 check bits Cr occurred with no errors and all the bits of the read word, be they data bits of the vector Xr or the check bits Cr, are correct.
If the syndrome S is different from 0, the read word includes one or more errors. If a single bit of the read word is erroneous, the obtained syndrome S enables correcting the error. Indeed, the syndrome S corresponds in this case to the column in the matrix H′ having had its elements multiplied by the erroneous bit. In other words, when a single bit in either the 16 bits Xr or the 5 check bits Cr is erroneous, the syndrome S will have a value corresponding to one of the columns in the matrix H′. Each column in the matrix H′ is associated with a particular one of the bits in Xr and Cr and thus the non-zero value of the syndrome indicates the erroneous bit. The matrix H′ has columns 1-21 from left to right where the bits X0-X15 and C0-C4 are associated with the columns 1-21, respectively. For example if the calculated syndrome is equal to:
      S    =          (                                    0                                                                                0                                                                              0                                                                                1                                                1                              )        ,then the syndrome corresponds to the first column of the matrix H′, which is associated with the first bit X0 of the vector Xr. Thus, this syndrome indicates that the first bit X0 of the vector Xr is erroneous.
Similarly, if the calculated syndrome is equal to:
            S      ″        =          (                                    1                                                                                0                                                                              0                                                                                0                                                0                              )        ,then the syndrome S corresponds to the 17th column in the matrix H′ which is associated with the first detection bit C0. In this example, the syndrome means that the first detection bit C0 is erroneous. By knowing the erroneous bit from the syndrome S, the erroneous bit can be corrected simply by taking the complement of that bit. For example, if the syndrome S indicates the first bit X0 of the vector Xr is erroneous, then the corrector unit 78 (FIG. 1) may correct this bit by simply inverting the value of bit, such that if the bit is a "0" it is changed to a "1" and if the bit is a "1" it is changed to a "0."
The above-described Hamming code cannot detect two errors. Thus, if an error has occurred in bits X1 and X2, the obtained syndrome S is equal to the sum modulo 2 of the syndromes corresponding to errors on X1 and X2, that is, to:S′=(00101)+(00110)=(00011).
The obtained syndrome S′ indicates an error in bit X0, which is wrong since the errors actually occurred in bits X1 and X2.
Indeed, the above Hamming code is known to gave a minimum code distance d=3 and a linear code like the Hamming code is known to be able to correct L errors and to detect L+1 errors if its minimum code distance d is strictly greater than 2 L+1. Accordingly, for the above Hamming code L=1 and thus the code can detect two errors (e.g., in the above example of bits X1 and X2 being erroneous the syndrome S was non zero and thus indicated that an erroneous bit was present) but can correct only a single error. A linear code is a code in which the sum of two read words equals a valid read word of an overall group of read words that collectively make up the code, as will be understood by those skilled in the art. Similarly, one skilled in the art will understand that the minimum Hamming code distance is the minimum number of bits by which all pairs of read words differ for all pairs of words that collectively make up the code.
To improve the above code and allow more errors to be detected, the minimum distance of the code must be increased. For example, to convert the above code into a code having a minimum code distance d equal to 4, a total parity bit P may be added to each read word.
The total parity bit P for each read word is calculated by adding modulo 2 all the data bits X0-X15 and all the check bits C0-C4 or each read word that is part of the overall code. The total parity bit P is added to each word to be stored, and the word to be stored X0-X15 the check bits C0-C4, and the total parity bit P are all collectively stored as a word in the overall code.
In a read data transfer, the read word is multiplied by parity control matrix H″ shown in FIG. 6A. The matrix H″ has one more row and one more column than the matrix H′. The matrix H″ includes, to the top left, that is, on the first five lines and on the first 21 columns, a block identical to the matrix H′. The last row D of matrix H″ only includes "1 s" and the last column of matrix H″ only includes "0 s", except for the last line row which in the row D and is therefore a "1."
The obtained syndrome S′ is illustrated in FIG. 6B and has six components S0 to S5 obtained by multiplying the matrix H″ by a column vector formed by the 22 bits of the read word. The 22 bits in the read word are the 16 read data bits Xr, followed by the five read check bits Cr, and finally the read total parity bit Pr. The code obtained using the matrix H″ is a so-called "Single Error Correction"-"Double Error Detection" ("SEC-DED") code. This code has a minimum code distance d equal to four and can detect two errors in all cases, two errors being indicated by the fact that the last component of the syndrome, S5, is zero while the syndrome S is different from the zero vector.
While the above SEC-DED code allows single errors to be corrected and double errors to be detected, the calculation of the total parity bit P is required. This calculation requires a large number of adders, since all data bits Xr and check bits Cr must be added modulo 2. Further, the calculation of the total parity bit P cannot be performed in parallel with the calculation of the check bits Cr, since it requires the previous knowledge of the check bits. Accordingly, it must be awaited that all check bits Cr have been calculated to calculate total parity bit P, which wastes time.
Upon decoding, the calculation of the last syndrome element, S5, requires a large number of additional adders, and this increases the circuitry required for decoding each stored read word which, in turn, increases the area consumed by such decoding circuitry in an integrated circuit. Furthermore, since each addition requires some time, the calculation of the last syndrome element S5 has a relatively long duration and thus undesirably increases the overall decoding time of each read word. This is true of the sixth row of matrix H″ in particular because this row consists of all binary "1"s, and each binary "1" requires an associated adder circuit while a binary "0" in the matrix does not require such an adder circuit, as will be understood by those skilled in the art and as will be discussed in more detail below.
It should also be noted that, in the above-described Hamming code, the Hamming matrix is neither symmetrical, nor regular. Thus, considering that the elements of a column in the matrix H″ correspond to the binary representation of a number, the variation of this number is not regular from column to column but instead includes jumps. This makes difficult the forming of a circuit implementing the parity control matrix H″ as well as the syndrome S decoding.—Systems have been developed using parity control matrices having characteristics that simplify circuitry for implementing the matrix and associated syndrome. For example, FIG. 7A illustrates an example of a parity control matrix M for calculating the check bits C for 16-bit read words in an error correction/detection code. The number of check bits C is equal to 6 and matrix M is a matrix of dimension 6×16. Each column of matrix M is different from every other column and the columns are linearly independent two by two. Furthermore, each column of matrix M is complementary to an immediately adjacent column, except for the first two columns.
The matrix M can be decomposed into eight couples Ai of two adjacent columns, with i ranging from 0 to 7. The couple A0 corresponds to the columns of rank 0 and of rank 1, couple A1 to the columns of rank 2 and of rank 3, and so on through couple A7 to the columns of ranks 14 and 15. In the example of matrix M shown in FIG. 7A, the two columns of a couple Ai are complementary, except for couple A0. The couples A1 to A7 of the matrix M are formed as follows. The first four elements of the first column of a couple correspond to the binary representation of rank i of the couple Ai. Thus, the first column of couple A3 has its first four elements equal to "0011", which is the binary representation of the number 3.
The first four elements of the first column of couple A0 (column of rank 0) are chosen to be equal to "0011". This choice is not critical. The first four elements of the column of rank 0 may indeed have any value, provided that the column of rank 0 once completed is different from any other column of matrix M or from the columns relative to the check bits of the matrix used for the decoding, M′, which will be described hereafter. The choice of ("0011") has the advantage of using a small number of binary "1s", which simplifies the coding and decoding circuits for implementing the matrix M because, as previously mentioned, the number of binary "1s" determines the number of adders required in the coding and decoding circuits. The last two elements of each first column of a couple Ai (columns of even rank) are equal to "10", except for the first and last couples Ai (columns of rank 0 and 14), where they are equal to "01".
Except for the first couple, A0, each second column of a couple Ai is complementary to the first column of the couple. In other words, except for the column of rank 1, the elements of each column of odd rank are the complements of the elements of the immediately preceding column of even rank, and vice versa. For example, the elements of the first column (rank 8) of couple A4 are equal to "010010" and the elements of the second column (rank 9) of this couple are "101101". In FIG. 7A, couple A0 has "001101" as its first column and "111110" as its second column.
It should be noted that the penultimate row of matrix M, referred to as K, having as elements "0110101010101001", is complementary to the last row of matrix M, referred to as L, having as elements "1001010101010110". This provides advantages when calculating a total parity bit, as will be described in more detail below.
When matrix M is multiplied by a column vector of sixteen components X0-X15 corresponding to the bits of the word to be coded and six check bits C0-C5 are obtained, which are added to the word to be coded to form a 22-bit coded word. FIG. 7B illustrates a matrix M′ used for the decoding the 22-bit coded word to generate the corresponding syndrome S. At decoding, a vector having 22 components, corresponding to the 22 bits of the coded word being decoded (16 data bits X0-X15 and 6 check bits C0-C5 after any processing, for example, a storage of the coded word in memory or a transmission of the coded word), is multiplied by matrix M′ to form a syndrome S having six components S0-S5. The matrix M′ is a matrix of dimension 6×22 with the first sixteen columns forming a block identical to the matrix M. The first five rows of the five next columns (ranks 16 to 20) form a block A of dimension 5×5 that is an identity matrix having "1s" on a main diagonal and "0s" elsewhere. Under block A, the elements of the last row of the columns of rank 16 to 20 are chosen to be equal to "11110", to correspond to the inverses of the elements of the last row of block A ("00001"). The last column of matrix M′, which enables correcting an error on the sixth detection bit C5, includes "0s" in the first five rows and a "1" in the last row.
In the matrix M′, the columns corresponding to the data bits (i.e., ranks 0-15 of the block corresponding to the matrix M) are complementary two by two, except for the first two, . Further, the last two rows of the matrix M′ are also complementary. If the sum modulo 2 of the last two syndrome components, S4 and S5, is calculated, the sum modulo 2 of all the data bits and the check bits of the word to be decoded, that is, a total parity bit Pr is obtained. The total parity bit Pr is here simply obtained and is calculated in approximately half the time as in the case of the corresponding Hamming code previously discussed with reference to the matrix H″ of FIG. 6B. Further, upon coding, in contrast to the Hamming code using the matrix H″, no total parity bit P is calculated.
If the syndrome S is equal to the zero vector, there are no errors, either in data bits X0-X15 or in the 6 check bits C0-C5. If the syndrome S is different from the zero vector and total parity bit Pr is equal to 1, this means that there has been a single error, which can be corrected. Indeed, the syndrome S elements in this case correspond to the elements of the column of matrix M′ corresponding to the erroneous bit. If the syndrome is different from the zero vector and total parity bit Pr is equal to 0, two errors are present, which are detected but which cannot be corrected since it is not known which two columns of matrix M′ correspond to the erroneous bit in the data bits X0-X15 or in the 6 check bits C0-C5.
FIG. 8A schematically shows the principle of a circuit used for the coding the data bits X0-X15 to thereby calculate the check bits C0-C5. A coding circuit 100 includes 16 inputs E0 to E15, which receive the 16 data bits X0 to X15 of the word to be coded. The circuit 100 also includes 6 outputs C0 to C5 providing the six check bits. Each input E is connected to a column of rank i of the circuit 100 and each output Cj is connected to a row of rank j of the circuit. An adder modulo 2 Gi,j schematically indicated herein by a circle marked with a cross may be present at the intersection of column i and of row j in the circuit 100. The adders modulo 2 Gi,j may be any adders, and formed for example by XOR gates.
An embodiment of one of the adders modulo 2 Gi,j is shown in FIG. 8B and includes two inputs ei,j1 and ei,j2 often respectively called e1 and e2 hereafter for ease of reference. The input e1 is connected to input E1 and input e2 receives the signal present on row j to the left of adder Gi,j. The adder Gi,j also includes an output si,j located on row j to the right of adder Gi,j, which will simply be referred to as s hereafter. When there is no adder Gi,j at the intersection of column i and row j, column i and row j cross with no influence upon each other. This means that the bit X0-X15 provided to the concerned input E0-E15 is not used to calculate the corresponding detection bit Cj, which simplifies the circuitry required to form the circuit 100. An additional column, a (FIG.8A), located to the left of the column of rank 0 connects input e2 of each first adder Gi,j of a row to ground GND.
The operation of circuit 100 will be explained for the calculation of detection bit C4, corresponding to the row of rank 4. Starting from the left, the first encountered adder is adder G1,4. The input e2 of adder G1,4 is grounded via column a and the input e1 of adder G1,4 receives data bit X1 via input E1 of the circuit 100. At the output of adder G1,4, s=0⊕X1, which is equal to X1. The signal provided by adder G1,4 is applied to the input e2 of adder G2,4 in the next adjacent column to the right, and this adder calculates the value X1⊕X2. This process continues from left to right for the adders Gi,j in the row of rank 4, until the adder G15,4 performs the addition modulo 2 of the result provided by adder G12,4 and the data bit X15. Thus, C4=X1⊕X2⊕X4⊕X6⊕X8⊕X10⊕X12⊕X15, which corresponds to the multiplication of the fifth row of matrix M by a vector having as elements the bits X0-X15 of the word being coded. Generally speaking, the circuit 100 has the structure of matrix M with the circuit rows and columns corresponding to the rows and columns of matrix M, and an adder modulo 2 Gi,j being located in each row where the matrix M includes a "1". In other conventional encoder circuits, an adder Gi,j is formed for each element in the matrix M and thus is located at an intersection of each row and column.
The advantages provided for the circuit 100 by the fact that adjacent columns of the matrix M are complementary will now be described. Because the columns of the matrix M are complementary except for the first two columns, the adders modulo 2 Gi,j of circuit 100 need not be formed in adjacent columns except possibly for the first two columns rank 0 and 1. As a result, each adder Gi,j can laterally (i.e., in the direction of the rows) occupy the place of two adders in prior art circuits requiring an adder at the junction of each row and column. Making the adders Gi,j larger means components forming the adders, such as transistors, can be physically larger so that the overall operation of the adder is faster. This is desirable because the circuit 100 slows the rate at which code words can be encoded and decoded and thereby lowers the throughput of the data bits X0-X15, which is the data being accessed or communicated.
FIG. 8C illustrates the row of rank 4 of the circuit 100, which generates the detection bit C4. Each adder Gi,j in this row is shown in the form of a rectangular block. The first adder Gi,j encountered is adder G1,4 with its input e2 grounded via column a and its input e1 receiving bit X1 via input E1. In FIG. 8C, the columns of the circuit 100 that are not connected to an input of an adder Gi,j of the row of rank 4 are shown as dotted lines. The output si,j of each of the adders Gi,j supplies the input e2 of the next adjacent adder to the right, and the last adder G15,4 provides the detection bit C4 of the circuit 100. The row of rank 4 of the coding circuit 100 thus includes eight adders (G1,4, G2,4, G6,4, G8,4, G10,4, G12,4, and G15,4), with the data bits being used to calculate the detection bit C4 being X1, X2, X4, X6, X8, X10, X12, and X15. All the adders Gi,j of the row of rank 4 have a double surface area as compared to prior adders that had to be positioned at the intersection of each row and column of the matrix M.
Although in FIG. 8C, the input e1 of an adder Gi,j is located either to the left, or to the right of the adder, all circuit adders may have the same physical structure. In this case, each input e1 is arranged at a same determined location of an adder Gi,j such that a set of vias or connections can couple the input to the desired input E to supply the required bit X. The circuit 100 is thus formed of 48 adders Gi,j (8 adders per line), all having a same silicon surface area, which is twice that provided by adders positioned at the intersection of each row and column. Furthermore, due to the fact that the coding matrix M has two complementary lines, no total parity bit P is ever calculated upon coding. The 6 check bits C0 to C5 may be calculated in parallel and added to the word X being coded with no additional time loss, as is the case when generation of the total parity bit P is used.
FIG. 9 schematically shows a decoding circuit 110 used for decoding code words formed by the bits X′0 to X′15 and the six check bits C′0 to C′5. The circuit 110 includes 22 inputs E′0 to E′21 receiving the 22 bits of the word to be decoded (16 data bits X′0 to X′15 and 6 check bits C′0 to C′5). The circuit 110 includes six outputs S0 to S5, each providing a component of a generated syndrome S. The circuit 110 shown herein is directly made at the output of a memory, of which only a row 12 of 22 sense amplifiers SA0 to SA21 is shown. The sense amplifiers SAi are each located at the end of a bit line (not shown) and at the end of two complementary bit lines for a DRAM (not shown), and each sense amplifier provides a bit X′0 to X′15 of the word X′ to be decoded. The sense amplifiers SA0 to SA15 provide data bits X′0 to X′15 and sense amplifiers SA16 to SA21 provide check bits C′0 to C′5. The decoding circuit 110 is formed on the same silicon chip as the memory (not shown) in which the coded word including bits X′0 to X′15 and C′0- C′5 is stored, and may be an integral part thereof. Each of the inputs E′i of the circuit 110 is spaced apart from another input by the interval separating two sense amplifiers SAi.
An examination of FIG. 9 shows that almost all adders Gi,j of the decoding circuit 110 occupy a surface area which is double that provided by other adders as previously discussed, and adders of double surface area can operate much faster than adders having half their surface area and thereby the decoding circuit operates much faster.
It should further be noted that the number of adders Gi,j per row is reduced as compared to prior circuits, resulting in an additional increase in operating speed of the decoding circuit 110. As a comparison, reference will be made to the last row of matrix H″ of FIG. 6A, formed of 22 consecutive "1s". Thus, the last row of the corresponding decoding circuit must include 22 small adders Gi,j connected in series. In contrast, with the matrix M′ the last row of the decoding circuit 110 only includes 13 adders Gi,j, 9 of which have a surface area which is double that of the adders that would be utilized to implement the matrix H″. The increased operating speed of the circuit 100 is thus present at two levels: 1) physically larger and thus faster adders Gi,j; and 2) fewer adders per row and thus reduced operating time of these series-connected adders. Since the overall calculation time of the decoding circuit 110 corresponds to the sum of the processing times for each of the adders Gi,j, the circuit operates much faster than a decoding circuit implementing the matrix H″ and including many more adders connected in series. Furthermore, the larger surface area of the adders Gi,j enables them to operate more reliably.
The code words X, C for the encoding circuit 100 of FIG. 8A and decoding circuit 110 of FIG. 9 are not limited to codes intended for 16-bit data words X0 to X15. Indeed, it is possible to define codes enabling the coding words X having any number of bits, as long as at least two consecutive columns are complementary to thereby enable reducing the processing time of the adders for by these columns. For example, it is possible to generalize matrix M of FIG. 7A to code any data word X including an even number of m bits. The number r of check bits C must be at least greater by 2 than the number necessary to binarily represent the number of bits of the word X to be coded. Preferably, r will be equal to its minimum value, to minimize the number of bits required for the code and thereby avoid making the code too "heavy". Thus, when m is equal to 16, four bits are required to binarily represent sixteen possibilities and r is chosen to be equal to 6, as seen previously. For m=32, the number of check bits is chosen to be equal to 7, with there being 5 bits to binarily represent the 32 bits in each word X being coded plus the two additional bits. As another example, for m=128 the number of check bits is equal to 9, with 7 bits representing the 128 bits in each word X being coded plus the two additional bits. The same process applies to words X having any number of bits m, as will be understood by those skilled in the art.
To generalize the matrix M, the number r of necessary check bits is first determined. Then, the matrix M used for the coding is built, so that the first r−2 elements of each column of even rank indicate, except for the first column, the rank of the couple to which the column belongs (a couple Ai of rank i is formed of the column of even rank 2i and of the column of odd rank 2i+1. The rank of the first column is 0, and that of the last columns is m−1. The last two elements of the columns of even rank are equal to "10", except for the column of rank 0 and the column of rank m−2, where they are "01". The first column of the matrix M may be formed of r−4 elements equal to "0", followed by elements "1101". Thus, in the first column of rank 0 in the matrix M, the first two rows are "0"s (r−4=6−4=2) and the elements in rows 2-5 are "1101." The second column of the matrix M, which is the column of rank 1, may be formed of r−4 elements equal to "1" followed by the elements "111O". Accordingly, the in the second column of the matrix M the first two rows are "1"s and the elements in rows 2-5 are "1110." In the matrix M, the columns of odd rank are, except for the column of rank 1, complementary to the immediately preceding column of even rank. It should be noted that the last row of the matrix M is complementary to its penultimate line.
With regard to the matrix M, it should also be noted that the first r−2 elements of the first column of rank 0 may be identical to the r−2 elements of any other column of the matrix M (which is the case in the matrix M of FIG. 7A where the columns of rank 0 and rank 6 have the same elements "0011" in their first four (r−2) rows. This is true as long as the first column is different from all other columns of matrix M and the first four elements of the first column must not be all "0s" and must include more than one "1" so that the column is different from the columns of the matrix M′ used upon decoding which correspond to the check bits (i.e., the columns of rank 16-20 corresponding to the identity matrix A in FIG. 7B).
To form the matrix M′ used for decoding, the parity control matrix M is used and completed to the right by a square sub-matrix R of dimension rxr. The sub-matrix R includes "1s" on its main diagonal from upper left to lower right and "0s" everywhere else except in its last row, where the elements are the complement of those of the penultimate row of the sub-matrix R. The last row of the sub-matrix R thus includes "1s" everywhere except at the penultimate column.
The code using matrixes M and M′ has a minimum code distance equal to four, which enables correcting one error and detecting two errors. Upon decoding, the obtained syndrome S has r components. A total parity bit P is obtained by adding modulo 2 the last two syndrome components. If the syndrome S is the zero vector, there is no error in the data word X or check bits C. If the syndrome S is different from the zero vector and the total parity bit is equal to "1", there is a single error. This error is easily corrected since the syndrome S corresponds to the matrix column having had its elements multiplied by the erroneous bit. If the syndrome is different from the zero vector and the total parity bit is equal to "0", two errors are present and, while detected, cannot be corrected.
FIG. 10, as an example, illustrates a matrix M′32 used to decode 32-bit data words. The matrix M′32 has dimensions 7×39, and its first 32 columns correspond to the matrix M32 used upon coding. The matrices M32 and M′32 are formed on the model of what has been previously described. The corresponding coding and decoding circuits, not shown, are easily deduced from matrixes M32 and M′32 by means of the principles defined in relation with FIGS. 8A-8C and 9.
Any row permutation in a parity control matrix formulated according to this process may be utilized Similarly, any column permutation in such a matrix may also be done provided that at least two consecutive columns remain complementary. The number N of bits of the word to be coded may be even or odd. If the number N is odd, a matrix M such as described above with an even m equal to N+1 may first be formed, and then the matrix N to be used upon coding can easily derive from matrix M by suppression of any column, such as the first column.
Typically the ECC logic 4 (FIG. 1) that implements the matrices M and M′ is performed on the data word X of the width used by the application. A problem with using Hamming codes on relatively short words is that a larger percentage of storage capacity is required for the check bits. For example, if the application utilizes 8-bit data words, then 5 check bits are required for the SECDED logic executed by the ECC logic 4, which accounts for 62% of the total memory storage capacity. A 256-bit word, however, requires only 10 check bits for SECDED logic, which is only 4% of the memory storage capacity. Thus, there is a need for applying wide data words X to the ECC logic 4 to minimize the percentage of overall memory that is used by the codes generated by the ECC logic.
In the matrix M of FIG. 7A, the first two columns are not complementary. This is contrary to the one of the primary goals of this matrix, which is uniform density of "1s" and "0s" so that the distribution and operation of the adders Gi,j is improved. Particularly when the ECC logic 4 operates on wide data words X, uniform density is even more important to the large number of bits in each data word and the potential for delays caused by additional adders Gi,j, as well as the improved physical layout of the adders that is possible when the density of the "1s" and "0s" is uniform.
Another issue when dealing with wide data words X using the matrix M is the number of gates and adders Gi,j needed to implement encoding matrix M and decoding matrix M′. There is a particular need to minimize the number of components in ECC logic 4 operating on wide data words X in order to conserve space on semiconductor memory chips in which such circuits must be formed, and to reduce the costs associated with the manufacture of such chips.
There is a need for a parity control matrix for encoding and decoding wide data words and that allows for the formation of ECC logic having a reduced number of components and having relatively uniform distribution of such components to improve operation of such logic.