To provide a thermoelectric conversion material having semiconductor-like temperature dependence, that is, the property that electric resistivity decreases with increasing temperature, and having high thermoelectric performance. The present invention is a thermoelectric conversion material including a semiconductor phase having a layered bronze structure expressed by a formula of Ay(Co1-xRhx)O2, where A is an alkaline-earth metal, y is 0.2 to 0.8, and x is 0.4 to 0.6.

1. Field of the Invention
The present invention relates to a thermoelectric conversion material for performing energy conversion between electric energy and thermal energy, using thermoelectric effect, and a thermoelectric conversion element using the material. The present invention also relates to an electronic apparatus using thermoelectric generation induced by the material and a cooling device using thermoelectric cooling induced by the material.
2. Description of the Related Art
Thermoelectric generation is a technology for directly converting thermal energy into electric energy by Seebeck effect, a phenomenon in which a temperature difference in opposite ends of a substance causes thermal electromotive force proportional to the temperature difference. This electric energy can be used as electric power when a load is connected thereto and a closed circuit is constituted. This technology has found practical applications in power sources for remote areas, for space, for military use, and the like.
Thermoelectric cooling is a technology for causing heat absorption by Peltier effect, a phenomenon in which application of an electric current through a circuit made of different substances connected to each other causes heat absorption in one junction and heat generation in the other junction. This effect is thought to be derived from the characteristic that the ratio between the electric current carried by electrons and a heat current carried thereby differs between the substances when two kinds of substances each of which is different in carrier polarity, a p-type semiconductor and an n-type semiconductor, for example, are thermally connected in parallel and electrically connected in series, and the electric current is applied therebetween. The thermoelectric cooling technology has found practical application in local cooling devices such as for cooling electronic devices in a space station, and wine coolers.
To date, desired is a thermoelectric conversion material exhibiting a good thermoelectric conversion characteristic (thermoelectric performance) in a wide range of temperatures from room temperature to high temperature. Various materials, most of which are semiconductors, are under consideration.
The thermoelectric performance is generally evaluated by a figure of merit Z, or a figure of merit ZT that is made dimensionless by multiplying Z by absolute temperature T. ZT can be expressed as ZT=S2/ρκ, where S is a Seebeck coefficient, ρ is electric resistivity, and κ is thermal conductivity. That is, in order to allow the thermoelectric conversion material to exhibit excellent thermoelectric performance, large thermal electromotive force, small thermal conductivity, and small electric resistivity are desired. In the conventional thermoelectric conversion materials, however, it can not be said that sufficient ZT is obtained. This is because S, ρ, and κ are basically functions of carrier density, and thus, difficult to vary independently, which gives rises to difficulties in finding the appropriate solution.
The thermoelectric conversion materials developed until today include a Bi2Te3-based semiconductor. With this material, thermoelectric performance on a practical level at room temperature can be obtained. In addition, there have been developments toward the practical application on materials having a complicated structure such as a Skutterudite compound, and a clathrate compound.
JP 8(1996)-186294 A (reference 1) discloses a thermoelectric conversion material expressed by a formula of Co1-xMxSb3 (x is 0.001 to 0.2 in the reference 1) in which one portion of Co, which is an element constituting a CoSb3 compound having a Skutterudite structure, is substituted with at least one element M selected from Pd, Rh, and Ru. The thermoelectric conversion material disclosed in the reference 1, however, has a problem in that in a high-temperature range, the thermoelectric performance of the material deteriorates due to oxidization.
JP 9(1997)-321346 A (reference 2), JP 2003-218411 A (reference 3), and WO03/085747 (reference 4) disclose a thermoelectric conversion material referred to as a so-called "AMO2-type oxide" (in the references 2 to 4, A is an alkali metal or an alkaline-earth metal, and M is Co). These materials do not easily suffer from damage or oxidization even under a high-temperature environment, and exhibit excellent thermoelectric performance. The thermoelectric conversion material disclosed in the references 2 to 4 are materials having a so-called "layered bronze structure" described later. It is well known that an AMO2-type crystal, typical of the layered bronze structure, has metallic properties, that is, the property that the electric resistivity increases with increasing temperature.
WO2004/095594 (reference 5) discloses a thermoelectric conversion material including a Half-Heusler alloy expressed by a formula of QR(L1-pZp) (in the reference 5, Q is a group 5 element, R is at least one element selected from Co, Rh and Ir, and p is 0 (zero) or more, and less than 0.5).
JP 2005-64407 A (reference 6) discloses a thermoelectric conversion material expressed by a formula of SrxRh2Oy (in the reference 6, x is 0.7 to 1.0, and y is 4.0 or more), and describes that the electric resistivity of the material exhibits the above-described metallic property (see paragraph number [0020], for example).
The thermoelectric performance of these thermoelectric conversion materials, however, is not yet satisfactory, and is lower than that of the Bi2Te3-based semiconductor that has entered a practical stage. This calls for further improvement of the thermoelectric performance. In addition, while it is expected that the thermoelectric generation in a temperature range higher than conventional produces a greater electric energy, the thermoelectric conversion material exhibiting metallic properties increases the electric resistivity of the material with increasing temperature, thereby resulting in a larger loss.

Thermoelectric conversion material, thermoelectric conversion element using the same, and electronic apparatus and cooling device comprising the element

Matsushita Electric Industrial Co., Ltd.


In accordance with one or more aspects of the present invention, a wireless sensing system is disclosed, where the system has particular application to sensing the speed of a vehicle wheel, for example. To sense wheel speed, a sensing unit senses changes in magnetic flux and wirelessly relays a signal indicative thereof back to a base station or control unit.

It can be appreciated that difficulties exist with regard to utilizing (e.g., positioning, associating and/or accessing) sensors in certain environments. In automotive applications, for example, sensors may be located in remote locations relative to a control unit. Such sensors may also be located in hard to reach places and/or harsh operating environments that are difficult to access, particularly after the vehicle is in operation. For example, sensors may be located in and/or on a tire to sense tire pressure, within a seat to sense seat position and/or the presence, absence and/or weight of a passenger in a seat, on an undercarriage or frame to sense a ride height of a vehicle, in a carburetor and/or engine to sense temperatures and/or pressures therein (e.g., of an accelerant such as gasoline), in a fluid compartment (e.g., gastank, oil pan, radiator, etc.) to sense fluid levels, etc.
Additionally, wiring along with associated wiring harnesses are generally utilized to carry output signals from the sensors and/or to supply operating power to such sensors. It can be appreciated that installing the sensors and making all the necessary wiring connections can be time consuming and labor intensive. Moreover, the physical connections can become overstressed and fail so that communications and/or electrical operations are interrupted. As such, it can be appreciated that there are an abundance of cost, reliability and/or safety issues that would make it desirable to facilitate wireless communications, particularly in automotive sensing applications.


Provided are rapidly bioavailable solid oral dosage forms of acute pain medications, and moisture resistant packaging that enables the formulation of such rapidly bioavailable dosage forms.

The bioavailability of pharmaceutical products is a critical concern in rational drug design. The pharmacokinetics of a drug, which measure the time it takes a drug to become bioavailable and its concentration profile in serum over time, can have a significant effect on the effectiveness of a drug, as well as its safety. Pharmacokinetics are of particular concern for drugs that require an immediate onset of action, such as drugs used in the treatment of acute pain.
Various factors can influence the time it takes for a drug to become bioavailable in therapeutically effective concentrations. For orally administered solid dosage forms, some of the most important parameters include the disintegration/dissolution time of the drug, the stability and solubility of the molecule in the gastrointestinal tract, and first pass metabolism, to mention just a few. For some drugs such as potassium diclofenac the pH of the formulation can also affect its bioavailability. For example, it is known that diclofenac potassium has a tendency to precipitate in an acidic environment, thereby making it less bioavailable. This problem is highlighted in bioavailability studies of Cataflam, a commercially marketed form of diclofenac potassium, which exhibits two concentration peaks in the bloodstream when orally ingested.
When rapid bioavailability is desired, preferred modes of administration include parenteral, inhalation, mucosal and buccal administration. Tablets and capsules are generally available only in immediate release, extended release, and delayed release formats, and are not typically employed when rapid bioavailability is desired because of the time it takes for the dosage form to dissolve, and the resulting delay in gastrointestinal absorption. A novel delivery system for orally delivering diclofenac in a rapidly bioavailable tablet has been proposed in PCT/EP97/02709 (published as WO 97/44023), but solid oral dosage forms based on this type of platform are clearly the exception and not the rule.

Moisture resistant container systems for rapidly bioavailable dosage forms


The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn transistors, and a second step that, over time, fully turns on the structure.

1. Field of the Invention
The present invention relates to silicon-controlled rectifier structures and, more particularly, to silicon controlled rectifier structures with reduced turn on times.
2. Description of the Related Art
A silicon-controlled rectifier (SCR) is a device that provides an open circuit between a first node and a second node when the voltage across the first and second nodes is positive and less than a breakdown voltage. When the voltage across the first and second nodes rises to be equal to or greater than the breakdown voltage, the SCR provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the SCR maintains the current path as long as the voltage across the first and second nodes is equal to or greater than a holding voltage that is lower than the breakdown voltage.
As a result of these characteristics, SCRs have been used to provide electrostatic discharge (ESD) protection. When used for ESD protection, the first node becomes a to-be-protected node, and the second node becomes a grounding node. The SCR operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected node, and a minimum voltage (also known as a latch-up voltage) defined by any DC bias on the to-be-protected node. The breakdown voltage of the SCR is then set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the to-be-protected node and the grounding node is less than the breakdown voltage, the SCR provides an open circuit between the to-be-protected node and the grounding node. However, when the to-be-protected node receives a voltage spike that equals or exceeds the breakdown voltage, such as when an ungrounded human-body contact occurs, the SCR provides a low-resistance current path from the to-be-protected node to the grounding node. In addition, once the ESD event has passed and the voltage on the to-be-protected node falls below the holding voltage, the SCR again provides an open circuit between the to-be-protected node and the grounding node.
FIGS. 1A–1B show views that illustrate a prior-art, silicon controlled rectifier (SCR) 100. FIG. 1A shows a plan view of SCR 100, while FIG. 1B shows a cross-sectional view taken along line 1B—1B of FIG. 1A. As shown in FIGS. 1A–1B, SCR 100 has an n− well 112 which is formed in a, p− semiconductor material 110, such as a substrate or a well.
In addition, SCR 100 has a p+ finger region 114 that is formed in n− well 112 to have a first length L1, and an n+ finger region 116 that is formed in n− well 112 to have a second length L2 that is substantially equal to the first length L1. P+ and n+ finger regions 114 and 116, which are parallel to each other and approximately 100 microns in length, are both electrically connected to a to-be-protected node.
SCR 100 further has a trench isolation region STI that includes a first isolation section STI1 that contacts n− well 112 and p+ finger region 114, and a second isolation section STI2 that contacts n− well 112, p+ finger region 114, and n+ finger region 116. In addition, trench isolation region STI also includes a third isolation section STI3 that contacts p− material 110. The first, second, and third isolation sections STI1, STI2, and STI3 are substantially parallel.
As further shown in FIGS. 1A–1B, SCR 100 also has a p+ finger region 122 and an n+ finger region 124 that are formed in p− semiconductor material 110. P+ and n+ finger regions 122 and 124, which have third and fourth lengths L3 and L4, respectively, both contact and are located on opposite sides of the third isolation section STI3.
In addition, n+ finger region 124 contacts the first isolation section STI1. As additionally shown in FIGS. 1A–1B, the first, second, third, and fourth lengths L1, L2, L3, and L4 of p+ finger region 114, n+ finger region 116, p+ finger region 122, and n+ finger region 124, respectively, are substantially equal.
Further, SCR 100 includes a first layer of metal silicide 126A that is formed on p+ finger region 114, a second layer of metal silicide 126B that is formed on n+ finger region 116, a third layer of metal silicide 126C that is formed on p+ finger region 122, and a fourth layer of metal silicide 126D that is formed on n+ finger region 124.
SCR 100 additionally includes a layer of isolation material 128, and a number of contacts 130 that are formed through isolation layer 128 to make electrical connections with p+ finger region 114, n+ finger region 116, p+ finger region 122, and n+ finger region 124. SCR 100 also includes a first metal region 132 that is formed on isolation layer 128 to make an electrical connection with the contacts 130 that are connected to p+ finger region 114 and n+ finger region 116.
SCR 100 further includes a second metal region 134 that is formed on isolation layer 128 to make an electrical connection with the contacts 130 that are connected to p+ finger region 122 and n+ finger region 124. In addition, first metal region 132 is electrically connected to the to-be-protected node, while second metal region 134 is electrically connected to the grounding node.
In operation, when the voltage on metal region 132 is greater than the voltage on metal region 134 by a difference voltage that is less than the breakdown voltage, the voltage reverse biases the junction between n− well 112 and p-type material 110. The reverse-biased junction, in turn, blocks charge carriers from flowing from metal region 132 to metal region 134. However, when the voltage on metal region 132 spikes up to be equal to or greater than the breakdown voltage, the reverse-biased junction breaks down due to avalanche multiplication.
The breakdown of the junction causes a large number of holes to be injected into p− material 110, and a large number of electrons to be injected into n− well 112. The increased number of holes increases the potential of p− material 110 in the region that lies adjacent to n+ region 124, and eventually forward biases the junction between p− material 110 and n+ region 124.
When the increased potential forward biases the junction, a npn transistor, which utilizes n+ region 124 as the emitter, p-type material 110 as the base, and n− well 112 as the collector, turns on. When turned on, n+ (emitter) region 124 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n− well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 116.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor, thereby providing the base current.
The electrons that are injected and swept into n− well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 114, and eventually forward bias the junction between p+ region 114 and n− well 112. When the decreased potential forward biases the junction between p+ region 114 and n− well 112, a pnp transistor formed from p+ region 114, n-well 112, and material 110 turns on.
When turned on, p+ emitter 114 injects holes into base 112. Most of the injected holes diffuse through (base) n− well 112 and are swept from (base) n− well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 are then collected by p+ region 122.
A small number of the holes injected into (base) n− well 112 recombine with electrons in (base) n− well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n− well 112 as a result of the broken-down reverse-biased junction, and n− well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 124. Thus, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 124 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 114 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
One variation of the standard SCR structure, such as SCR 100, is to incorporate an NMOS transistor into SCR 100 to provide low-voltage triggering. FIGS. 2A–2B show views that illustrate a prior-art, low-voltage triggering SCR (LVTSCR) 200. FIG. 2A shows a plan view of LVTSCR 200, while FIG. 2B shows a cross-sectional view taken along line 2B—2B of FIG. 2A. LVRSCR 200 and SCR 100 are similar and, as a result, utilize the same reference numerals to designate the structures that are common to both devices.
As shown in FIGS. 2A–2B, LVTSCR 200 differs from SCR 100 in that LVTSCR 200 has an n+ (floating drain) finger region 210 that is formed in both p− material 110 and n− well 112, and a channel region 212 that is located between n+ (source) finger region 124 and n+ (floating drain) finger region 210. In addition, LVTSCR 200 includes a gate oxide layer 214 that is formed on p− material 110 over channel region 212, a gate 216 that is formed on gate oxide layer 214, and a layer of metal silicide 218 that is formed on n+ finger region 210. N+ (source and drain) finger regions 124 and 210, gate oxide layer 214, gate 216, and metal silicide layer 218 define a NMOS transistor 220 which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10–15 volts.
Since NMOS transistor 220 is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region 210 and p− material 110 breaks down at the same time that the to-be-protected MOS transistors experience junction break down as a result of an ESD pulse. Once the reverse-biased junction between n+ region 210 and p− material 110 breaks down, the break down triggers LVRSCR 200 to operate the same as SCR 100.
Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, LVTSCR 200 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction break down voltage, which is less than the voltage level that causes destructive gate oxide break down, functions as the breakdown voltage.
In addition, other techniques, such as reducing the width of channel region 212, can be used to lower the breakdown voltage so that the n+ region 210 to p− material 110 junction breaks down before the to-be-protected MOS transistors experience junction break down. Thus, LVTSCR 200 provides a SCR with a significantly lower turn on voltage that allows MOS transistors to be protected from ESD events.
In addition to SCR 100 and LVRSCR 200, another well known SCR type structure is a bipolar SCR (BSCR). FIGS. 3A–3B show views that illustrate a prior-art, bipolar SCR (BSCR) 300. FIG. 3A shows a plan view of BSCR 300, while FIG. 3B shows a cross-sectional view taken along line 3B—3B of FIG. 3A.
As shown in FIGS. 3A–3B, BSCR 300 includes a p− substrate 310, an n+ buried layer 312 that is formed in the top surface of substrate 310, and an n− epitaxial layer 314 that is formed on the top surface of substrate 310. BSCR 300 further has a trench isolation region STI that includes a first isolation section STI1, a second isolation section STI2, and a third isolation section STI3 that are formed in, and contact, n− epitaxial layer 314. The first, second, and third isolation sections STI1, STI2, and STI3 are spaced-apart and substantially parallel.
In addition, BSCR 300 includes a p− base finger region 316 that is formed in the top surface of epitaxial layer 314 to have a first length L1, and a p+ surface finger region 320 that is formed in the top surface of epitaxial layer 314 to have a second length L2 that is substantially equal to the first length L1. BSCR 300 also includes an n+ sinker finger region 322 that is formed in epitaxial layer 314 to have a third length L3 that is substantially equal to the first and second lengths L1 and L2.
BSCR 300 further includes an n+ polysilicon emitter region 324 that is formed on and along a region of the top surface of p− base region 316. In addition, outdiffusion from n+ emitter region 324 forms a small n+ region 326 in the top surface of p− base region 316. In addition, BSCR 300 includes a first metal silicide layer 328A that is formed on and along an edge of p-base region 316, a second metal silicide layer 328B that is formed on p+ surface finger region 320, a third metal silicide layer 328C that is formed on n+ sinker finger region 322, and a fourth metal silicide layer 328D that is formed on polysilicon emitter region 324.
BSCR 300 also includes a layer of isolation material 332 that is formed over epitaxial layer 314, and a plurality of contacts 334 that are formed through isolation layer 332 to make an electrical connection with p− base region 316 via metal silicide layer 328A, p+ surface finger region 320 via metal silicide layer 328B, n+ sinker finger region 322 via metal silicide layer 328C, and n+ poly emitter region 324 via metal silicide layer 328D.
Further, a first metal region 340, which can function as the anode of an ESD diode structure (where the anode is connected to a to-be-protected device, such as the gate of a MOS transistor), is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to p+ surface finger region 320 and n+ sinker finger region 322.
In addition, a second metal region 342, which can function as the cathode of the ESD diode structure (where the cathode is connected to a grounding node), is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to n+ poly emitter region 324. A third metal region 344, which can be resistively connected to second metal region 342, is formed on isolation layer 332 to make an electrical connection with the contacts 334 that are electrically connected to p− base region 316.
BSCR 300 forms an npn bipolar transistor that utilizes n+ region 326 as the emitter, p− base region 316 as the base, and n+ buried layer 312, n− epitaxial layer 314, and n+ sinker finger region 322 as the collector. BSCR 300 also forms a pnp transistor that utilizes p+ surface finger region 320 as the emitter, n+ buried layer 312 and n− epitaxial layer 314 as the base, and p− base region 316 as the collector.
In operation, when a voltage on the anode of BSCR 300 rises with respect to the voltage on the cathode, the voltage on n+ sinker finger region 322 and n− epitaxial layer 314 rises with respect to the voltage on p− base region 316, thereby reverse biasing the pn junction between p− base region 316 and n− epitaxial layer 314. As a result, BSCR 300 blocks a current, other than a leakage current, from flowing from the anode to the cathode until the anode-to-cathode voltage exceeds a breakdown voltage.
When the rising voltage on the anode exceeds the breakdown voltage, avalanche multiplication causes large numbers of electrons to be injected into n− epitaxial layer 314 and large numbers of holes to be injected into p− base region 316. The electrons injected into n− epitaxial layer 314 follow a current path through n− epitaxial layer 314, n+ buried layer 312, and n+ sinker region 322.
The increased number of electrons in n− epitaxial layer 314 reduces the potential at the pn junction between p+ surface finger region 320 and n− epitaxial layer 314 which, in turn, forward biases the pn junction between p+ surface finger region 320 and n− epitaxial layer 314, thereby allowing p+ surface finger region 320 to inject holes into n− epitaxial layer 314.
In addition, the holes injected into p− base region 316 increase the potential in p− base region 316 which, in turn, forward biases the pn junction between p− base region 316 and n+ emitter region 326. When forward biased, n+ emitter region 326 injects electrons into p− base region 316.
Further, the accumulation of positive charge in p− base region 316, and the accumulation of negative charge in n− epitaxial layer 314 due to the injection of large numbers of holes and electrons, respectively, reduces the magnitude of the reversed biased junction until the pn junction between p− base region 316, and n− epitaxial layer 314 switches and becomes forward biased. Once the pn junction between p− base region 316 and n− epitaxial layer 314 becomes forward biased, a large current flows from the anode to the cathode, while the anode-to-cathode voltage drops to a holding voltage that is substantially lower than the breakdown voltage.
One problem with large SCR structures, such as SCR 100, LVTSCR 200, and BSCR 300, is that it takes a reasonably long time to turn these structures on due to the capacitance associated with the structures. Thus, there is a need for a large SCR structure that has a reduced turn on time.

Silicon controlled rectifier structures with reduced turn on times


Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal.

All references cited in this specification, and their references, are incorporated by reference herein where appropriate for teachings of additional or alternative details, features, and/or technical background. More specifically, U.S. Pat. No. 7,741,921 "Trigger-Mode Distributed Wave Oscillator" (TMDWO) of Ismailov, US Pub. 2012/0169427, "Force-Mode Distributed Wave Oscillator and Amplifier Systems" (FMDWO) of Emira, and U.S. application Ser. No. 12/374,165 "Pumped Distributed Wave Oscillator System" (PDWO) of Tekin are incorporated by reference which form the core oscillators of this application.
Disclosed is a Traveling Wave Based High Speed Sampling System. This is in response to today's many communication and data interface systems that employ sampling system front-ends to represent analog-in-nature continuous signals around us as digital stream of samples with best approximation to the original analog-in-nature signal.
Within a spectrum ranging from the likes of SERDES (Serializer-Deserializer) serial communication links to Digital to Analog Converters (DACs), these systems require well defined time intervals to represent the target signal without corrupting the content. With the ever increasing signal speeds, the accuracy of these timing signals defining the sampling event becomes more and more critical in the overall system performance. The sampling circuitry disclosed herein employ fully-symmetric dual-loop traveling wave oscillators such as the TMDWO, FMDWO and PDWO for enabling architectures that represent original target signals without corrupting the content.
Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly. In non-dock-forwarded communications systems, data streams are transmitted to receivers without transmitting separate, distinct dock signals. In such systems, a receiver can perform dock-and-data-recovery (CDR) processing to recover a clock signal from each data stream, where the dock signal is derived based on the timing of the data represented in the data stream. A typical CDR circuit comprises a sampling clock generator, such as a phase-locked loop (PLL) or a delay-locked loop (DLL) that generates one or more sampling clocks used to sample the received data stream. In some communications systems, a single receiver may receive multiple, different data streams, potentially having different data rates. Such a receiver will typically have a different CDR circuit for each different data stream. Implementing multiple CDR circuits, each with its own sampling clock generator can require too much layout area and/or operating power for some integrated circuit applications.
In U.S. Pat. No. 7,599,457 B2 Johnson, et al., describe a clock-and-data-recovery (CDR) system has a multi-phase dock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered dock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock Input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered dock signal is generated from the selected phase-offset clock signal.
More specifically, Johnson, et al., show a block diagram of a clock-and-data-recovery (CDR) system 100 as depicted in FIG. 1. CDR system 100 has a multi-phase dock generator 10 and N CDR channel circuits 20.1-20.N, where N Clock generator 10 generates a multi-phase set of clock signals 35 (i.e., multiple versions of a dock signal sequentially separated from each other in phase over one dock period by a specified phase-offset increment). For example, in one implementation, clock generator 10 generates 16 clock signals, each having the same frequency, but separated in phase from the previous dock signal by about 22.5 degrees. Clock signals 30 are all applied to each CDR channel circuit 20.1-20.N, which uses the set of clock signals 30 to generate a (different) recovered dock signal 40.1-40.N and a (different) output data 50.1-50.N stream from a corresponding (different) input data signal 60.1-60.N, potentially having different data rates.
It will be known to those skilled in the art that one of the intensively used digital CDR architectures is the over sampling CDR (OSCDR). It samples the received data at a rate higher than the data rate. As explained by Nobunari Tsukamoto, et al., in EP 1,898,548 A1, input data is sampled by multi-phase clock signals generated from a reference clock to obtain a bit string of samples for each data bit. A digital phase picking (DPP) algorithm selects which sample is the optimum to be used as the received data.
Usually, a phase locked loop (PLL) or a delay locked loop (DLL) circuit is used to generate the multi-phase docks necessary for oversampling. In a PLL, a ring voltage controlled oscillator (VCO) can be used to generate the required multi-phase clocks. This is implemented using delay elements (inverters) in a feedback fashion. In a DLL, delay elements are also used but in a feed-forward fashion. In order to support higher data rates, the phase difference of the required multi-phase clocks becomes very small and hence the individual delay of delay elements becomes very small also. That small delay can be beyond the technology limit or can result in a considerable amount of power consumption. This can be mitigated at the circuit level by using circuit techniques including reducing power consumption, or on the system level using architectural techniques via multiple channels.
In order to achieve very high data rates in a technology with limited circuit speed, parallelism has been applied using a multi-phase oscillator and distributed interleaved samplers as shown by Amoud Van der Wel et al., in EP 2,469,714 A1. The VCO is built using identical structural cells coupled in a ring providing multi-phase docks. The feedback loop includes data samplers, that receive the multi-phase docks, and a phase detector coupled to a phase alignment circuit receiving output signals generated by the data samplers and generating control signals to the VCO.
Many high speed serial communication standards require supporting more than one data rate. Thus, the oversampling interval changes with different data rates. For example, in PCI Express (Peripheral Component Interconnect Express, bus standard) 3 data rates are supported: 2.5 Gbps, 5 Gbps, and 8 Gbps. This results in 1 unit interval (UI) of 400 ps, 200 ps, and 125 ps, respectively. For an oversampling ratio of 8, the multi-phase dock intervals are 50 ps, 25 ps, and 15.625 ps respectively. This is more than 3× of change between the minimum and maximum oversampling dock intervals. Generally, the variation of the delay value in the delay element used in a PLL or a DLL is small and thus it is difficult to support different data rates. An oversampling circuit that can switch between oversampling intervals is described in U.S. Pat. No. 8,537,947 B2. A phase difference of the multi-phase serial data is set to be a sum of an oversampling interval and an integral multiple of a phase difference of the multi-phase docks. Thus, speed of the delay elements for generating the multi-phase serial data and speed of circuits for generating the multi-phase oversampling docks can be eased that leads to reduction of the power consumption.
In U.S. Pat. No. 8,340,619 Alireza Shirvanl-Mahdavi et al., describe "Phase synchronization of Phased Array or Multiple Receiver/Transmitter Systems," in which a prior art system 200 is shown (FIG. 2) for generating different phases of a local oscillator signal in accordance with a conventional technique. System 200 includes a local oscillator (LO) 210, a phase generator 220, and transceiver blocks 230a-230c. Local oscillator 210 is configured to generate a local oscillator signal, such as a high frequency local oscillator signal. Phase generator 220 receives the local oscillator signal, generates all the required phases of the local oscillator signal, and distributes the LO signals with different phases to each transceiver block 230a-230c.
According to Alireza Shirvani-Mahdavi et al., four local oscillator signals with four different phases are generated. Each local oscillator signal is transmitted to each transceiver block 230a-230c through a distribution line. However, having a distribution line for sending each phase to each transceiver block 230a-230c requires a lot of area. Also, each distribution line generally needs to be of an equal length to provide the LO signal to transceiver blocks 230a-230c with accurate phases. For example, a LO signal with a first phase is sent to all three transceiver blocks 230a-230c. If a distribution line to transceiver block 230c is longer than a distribution line to transceiver block 230a, then the LO signal received at transceiver block 230c will have a different phase from the LO signal received at transceiver block 230a. Thus, an accurate phase shifted LO signal has not been provided to each transceiver blocks 232a-230c. An additional problem with using distribution lines is that coupling between the distribution lines may alter the phases of the LO signals. Alireza Shirvani-Mahdavi et al., therefore, propose in one embodiment, a local oscillator configured to generate an LO signal. A transmission line receives the LO signal from the local oscillator and transmits the LO signal. A first set of taps and a second set of taps tap the transmission line to receive the LO signal. A plurality of transceiver blocks is configured to receive and transmit a plurality of phase-shifted radio frequency signals. Each transceiver block is coupled to a first tap and a second tap. Each LO signal received for a transceiver block is received with a different phase. However, the same reference phase may be calculated from a first LO signal received from the first tap and a second LO signal received from a second tap. Each transceiver block receives the reference LO signal having the reference phase determined from the first LO signal and the second LO signal.
Prior art has certainly shown improvements in an attempt to represent analog-in-nature continuous signals as digital streams of sample packets having the characteristics of the original signal as dose as possible. Primarily this has been achieved by resorting to such techniques as forming well defined time intervals and traveling wave based specific multi-phase sampling methods, especially as the demand for faster data rates has been increasing. However, prior art has been mostly using delay based ring oscillators. What is needed is a system comprising fully-symmetric dual-loop traveling wave oscillators configured in a manner described further below in the Detailed Description section of the present disclosure.

Traveling-wave based high-speed sampling systems


An automated banking machine is located adjacent a vehicle drive-up lane. The machine includes a card reader device, a cash dispenser device, and a robotic item handling device having a gripper. An item transfer area is accessible to both a machine user and the robotic item handling device. The item transfer area includes a card slot. A card sensing device is located adjacent the card slot. A machine controller can cause the robotic handling device to grip a card inserted in the slot and move it to the card reader device, responsive to the card sensing device sensing the inserted card. The machine controller can also cause the robotic handling device to grip cash dispensed by the cash dispenser and move it to the item transfer area.

Automated banking machines are known in the prior art. A common type of automated banking machine is an automated teller machine ("ATM"). ATMs have been developed which are capable of performing a variety of transactions. Such transactions may include dispensing currency or accepting deposits from a user. Other types of transactions include providing tickets, travelers checks, vouchers or gaming materials. Other types of automated transaction machines enable check cashing, bill payment, printing account statements, dispensing postage and receiving or providing other items of value. Other types of automated banking machines may be operated by a service provider such as a cashier or bank teller. Such automated banking machines may include bill counters, check acceptors, passbook printers and other types of devices. Automated banking machines generally carry out transactions while causing appropriate charges and credits to be applied to the respective accounts of a user, a machine owner and/or a provider of value, such as cash, goods or services, which are effectively transferred through operation of the machine. For purposes of this disclosure, an automated banking machine will be considered to refer to any machine capable of carrying out transactions which involve transfers of value.
Most automated banking machines are limited to being used by only one user at a time. For example when one user operates most ATMs, others are required to form a queue and wait until it is their turn to use the ATM. This may pose an inconvenience for both customers and the ATM operator.
To serve plural customers simultaneously a number of ATMs may be installed at a given facility. However, such additional ATMs take up more physical space. Physical space may be at a premium in some facilities. Providing additional machines may also be expensive. Significant additional costs may be incurred both in acquiring and servicing machines to assure that they are operating properly. When numerous machines are installed at one location, each includes components which are generally duplicative of components in the other machines. In addition, when one machine is upgraded or improved it is usually advisable to apply the same upgrade or improvement to all of the machines. This may add further cost and complexity for the owner of the machines.
A further limitation of most existing ATMs is the limited variety of transactions which may be performed at a single machine. Each machine enclosure is of limited size and may only accommodate a range of transaction function devices that can be fit within the enclosure. It may be desirable in some instances to add additional capabilities to an ATM machine. However, the space required to include the transaction function devices necessary to carry out a new type of transaction may not be available within the machine enclosure unless other transaction function devices are removed. As a result, it is sometimes not feasible to add a transaction function that would be desirable.
At present when additional transaction functions are incorporated into ATMs, it is often necessary to provide larger enclosures. Such larger enclosures are not only necessary to house the devices but to also provide the necessary interfaces for delivering or receiving items from the customer. It is common for each added transaction function device such as dispensers for tickets, receipts, coupons and the like, to have a separate delivery opening in the user interface. Likewise, when a user is enabled to deposit several types of items in the machine it is common to have a separate opening or access mechanism to receive each type of item from the user. Providing these capabilities further adds to the size and complexity of the machine.
In some instances it may be desirable to add the capability to an automated banking machine to communicate with and/or exchange items with a human service provider. Such activities may be desirable for particular types of transactions that cannot be carried out on an automated basis. However, such capabilities may be difficult to add to existing machines not originally built to include such capabilities. Automated transaction machines such as medication dispensers may also benefit from being able to communicate with a human service provider. In such machines it may also be desirable to include a larger range of medications which can be provided to authorized users. Other types of transactions which involve the dispense or receipt of items are commonly not carried out with automated transaction machines because of space requirements of associated dispensing and receiving mechanisms.
Thus there may exist a need for an automated banking machine apparatus and system that may be capable of carrying out more types of transactions on an automated basis. There may further exist a need for an automated banking machine apparatus and system that is capable of being more readily reconfigured to add or delete functions and transaction types. There may further exist a need for an automated banking machine apparatus and system that may serve customers more efficiently including serving a plurality of customers simultaneously. There may further exist a need for an automated banking machine apparatus and system that is relatively compact, reliable and economical to operate.

Card reading arrangement involving robotic card handling responsive to card sensing at a drive-up automated banking machine


An ultrasonic observation apparatus in which the frame rate can be made higher than that in a mechanical or conventional electronic scan method. The ultrasonic observation apparatus includes: an ultrasonic endoscope including ultrasonic transducers; a transmission aperture setting unit for setting ultrasonic transducer groups as transmission apertures; a transmission frequency setting unit for setting respective frequencies of drive signal groups for the transmission apertures; a drive signal generating unit for generating the drive signal groups having the set frequencies; a reception aperture setting unit for setting ultrasonic transducer groups as reception apertures; a signal processing unit for performing signal processing on reception signal groups respectively outputted from the ultrasonic transducer groups; and a control unit for controlling the transmission aperture setting unit to sequentially change regions of the ultrasonic transducer groups to be set as the transmission apertures at a predetermined time interval.

1. Field of the Invention
The present invention relates to an ultrasonic observation apparatus having an ultrasonic endoscope capable of being inserted into a body of a patient and taking ultrasonic tomographic images for medical diagnoses.
2. Description of a Related Art
Recent years, an ultrasonic endoscope to be used by being inserted into a body cavity of a patient has been developed for medical diagnoses based on ultrasonic tomographic images around the body cavity of the patient. In an ultrasonic endoscope, a mechanical radial scan method has been generally adopted which performs the scan with viewing angle of 360° by mechanically rotating an array including plural ultrasonic transducers (ultrasonic vibrators) for transmitting and receiving ultrasonic waves.
Further, an electronic radial scan method has been proposed which performs the scan with viewing angle of 360° by electronic scan. For example, Takeda et al., "The Experience of Electric Radial Endoscopic Ultrasonography on Gastroenterology", Jpn J Med Ultrasonics, Vol. 31, Supplement (2004), 77-C062 discloses results from studies on efficacy and problems of an electronic radial ultrasonic endoscope based on experiences in using the electric radial ultrasonic endoscope (ER-EUS) for various digestive system diseases.
Furthermore, in the radial scan method, acquisition of high quality ultrasonic images by simultaneously transmitting plural ultrasonic waves having frequencies different from one another in plural different directions has also been proposed.
As a related technology, Japanese Patent Application Publication JP-P2001-333902A discloses an ultrasonic diagnostic apparatus for obtaining plural pieces of echo data for observation by performing ultrasonic scan while varying an ultrasonic wave frequency. This ultrasonic diagnostic apparatus includes as main parts an ultrasonic observation unit, an image processing unit for performing various kinds of image processing, an ultrasonic probe having ultrasonic vibrators for transmitting and receiving ultrasonic waves, and a driving unit for driving the ultrasonic probe, and the ultrasonic vibrators are wideband vibrators such that driving frequencies can be changed (page 1). In the ultrasonic diagnostic apparatus, the ultrasonic observation unit includes a transmission and reception part for transmitting ultrasonic waves having different driving frequencies to the ultrasonic vibrators and receiving reflection waves of the ultrasonic waves, and a frame memory for receiving and storing the reflection waves as echo data. The selection among the various driving frequencies generated in the transmission and reception part is controlled by a system controller, and the selected driving frequency and echo data when employing the driving frequency are stored in association with each other.
Japanese Patent Application Publication JP-A-8-173420 discloses an ultrasonic image processing apparatus for synthesizing plural ultrasonic images having different frequency characteristics to make a smooth image and displaying the smooth image. This ultrasonic image processing apparatus includes ultrasonic transmitting and receiving means having different frequency characteristics from one another, control means for driving the plural ultrasonic transmitting and receiving means, and display means for weighting reception signals outputted from the plural ultrasonic transmitting and receiving means according to distances from positions within a screen corresponding to the ultrasonic transmitting and receiving means and synthesizing the reception signals to display the image in one screen (page 2).
Japanese Patent Application Publication JP-A-5-56980 discloses an ultrasonic diagnostic apparatus for easily performing frequency selection so as to deal with ultrasonic attenuation caused by higher frequency. This ultrasonic diagnostic apparatus includes an ultrasonic transducer shared among at least two center frequencies for obtaining reception signals by transmitting and receiving ultrasonic pulses having respective center frequencies, and means for independently collecting the reception signals for each center frequency by using the ultrasonic transducer (pages 1 and 2).
Japanese Patent Application Publication JP-P2001-170046A discloses a living tissue property diagnostic apparatus including signal analysis means for receiving an ultrasonic pulse reflected or transmitted within a living body and converting it into an electric signal, and diagnosing the living tissue property from an amount of characteristic of the electric signal in order to make correct diagnoses regardless of targets of measurement. In this living tissue property diagnostic apparatus, the signal analysis means has pulse width setting means for setting a pulse width of an electric signal, region extracting means for extracting plural signal regions which are different at least in part from one another, waveform characteristic value calculating means for calculating a predetermined waveform characteristic value in each of the extracted regions, difference computing means for computing the difference between the calculated waveform characteristic values, and corresponding time determining means for relating the result of the difference computation to the position of the living tissue that has generated the reception ultrasonic pulse by associating the result of the difference computation with the reception time of the ultrasonic pulse.
Thus, according to the mechanical or electronic radial scan method, there is an advantage that a wide viewing angle can be obtained. However, in comparison to a scan method of performing scanning with viewing angle of 90° by using a convex ultrasonic transducer array, for example, in the case where conditions of sound ray density, scan depth, and so on are set equal, there is a problem of reduction in frame rate because scan time (frame period) for obtaining an image for one frame becomes longer.
Further, as disclosed in JP-P2001-333902 and JP-A-8-173420, there is an advantage that the high resolving power (resolution) in the shallow part and penetration (focal depth) of ultrasonic waves to the deep part are consistent with each other by synthesizing plural ultrasonic images obtained by using ultrasonic waves having different frequencies from one another. However, in JP-P2001-333902 and JP-A-8-173420, only the mechanical radial scan method is used but it is not considered to use the electronic scan method.
On the other hand, JP-A-5-56980 suggests use of the electronic scan method when respectively transmitting plural ultrasonic waves having different frequencies from one another in plural different directions (page 3), but no specific aspect is revealed. In the case where the electronic scan method is adopted thereto, it is conceivable that the number of connecting lines to ultrasonic transducers becomes larger, but there is no disclosure about the measure against the problem. Also, there is no disclosure about combination of plural ultrasonic images obtained based on ultrasonic waves having different frequencies from one another to display the image, nor combination with an ultrasonic image generation method such as Doppler method other than B-mode image.
Further, JP-P2001-170046A does not specifically disclose an aspect of a probe to be used for extracting frequency components.

Ultrasonic observation apparatus having multi-beam scan function


A multiplexer circuit comprises a plurality of circuits for decoding digital timing signals, and a plurality of circuits for passing an one of the analogue voltage potentials to an output terminal corresponding to the decoded result of the decoding circuits, and preventing the passing circuits from passing more than one signal simultaneously.

1. Field of the Invention
This invention relates to a CMOS multiplexer circuit capable of receiving a plurality of digital signals and then producing an analog potential corresponding to those digital signals.
2. Description of the Related Art
To drive the liquid-crystal panels of image processing systems, for example, CMOS multiplexer circuits are generally used to supply a suitable driving potential to the panels. The multiplexer circuit is supplied with analog potentials of different magnitudes, and is also supplied with a select signal, mostly a digital signal. The select signal selects and turns on one of the supply gates each connected to the analog potentials to supply an analog potential to, for example, the liquid-crystal panel connected.
when the digital select signals pass through the logic circuits for decoding, the transfer gates are not always controlled by the respective control signals with the same timing. Delays in timing are ascribed to the circuit configuration of the inverter circuits or NAND circuits for logical processing, the capacitance, and others. Such timing delay leads to the faulty operation of the multiplexer's supply gates turning on at the same time. In the multiplexer circuit, when the supply gates turn on simultaneously, this causes the analog potentials to short-circuit one another, resulting in the improper output. The change of the well potential due to the short circuit makes the potential of the p-type substrate higher than the n-type substrate potential, creating the problem of permitting the CMOS IC of the multiplexer to latch up.

Multiplexer circuit less liable to malfunction


A device for assembling and locking two tubes has a radially symmetrical central member having a cylindrical screwthread on a front part and a cylindrical peg at the rear. The latter is inserted in a first tube. The front part is covered by two half-shells with a cylindrical outside wall, bearing on each other along a rectilinear ramp surface. One of the half-shells is unable to move in translation. The other is entrained in translation by the screwthread when the tube is rotated, which tends to move the two half-shells away from the central member, although they remain parallel to each other, until they come into contact with the inside wall of the second tube. The contact surface is cylindrical. The invention is useful, for example, in manufacture of telescopic rods.

1. Field of the Invention
The invention concerns a device for assembling and locking two tubes, in particular two tubes sliding one within the other.
It is more particularly concerned with a device for assembling and locking tubes in which locking is obtained by relative rotation of the tubes about a common axis of symmetry.
It also concerns the application of a device of this kind to the manufacture of a telescopic rod.
In the context of the invention, the expression "telescopic rod" must be understood in its widest sense: rod proper, sliding mast, etc.
By way of non-exhaustive example, the field of application of a telescopic rod of this kind concerns gardening. The telescopic rod may be fitted at one end with a tool of the secateurs or similar type, for example.
2. Description of the Prior Art
Many devices for assembling and locking two tubes of the above (rotational) type are known in themselves.
A first device known in itself comprises an eccentric cam and screw system. Upon relative rotation of the two tubes, the cam comes into contact with one of the tubes and frictionally engages its inside wall. However, this device is very complex and therefore costly and is of limited effectiveness. The contact area is small, resulting in a low coefficient of friction. Also, the cam being small, the mechanical strength is low.
Another known device comprises a screwthreaded central member surrounded by two half-cylinders. To be more precise, the screwthread is conical and entrains the two members when the central member is rotated about its axis of symmetry. The two half-cylinders are then moved apart angularly like two wings, and their ends frictionally engage the inside wall of one of the tubes.
FIGS. 1 and 2 appended to this description show a prior art device of this kind in diagrammatic form.
The assembly and locking device comprises a central member 1 in two parts: a screwthreaded front part 11 and a rear cylindrical sleeve 10. The latter fits in a first tube T.sub.1 sliding in a second tube T.sub.2 the inside diameter of which is slightly greater than the outside diameter of the first tube T.sub.1. The first tube T.sub.1 abuts on a ring 14 separating the screwthreaded front part 11 from the cylindrical rear sleeve 10. The two tubes T.sub.1 and T.sub.2 and the central member 1 have a common axis of symmetry .DELTA..
As already indicated, the screwthread 15 of the front part 11 is on a conical surface. The end of the screwthreaded front part 11 has an annular abutment 13 and the diameter of the screwthread 15 in this area is smaller than in the area near the annular abutment 14.
The screwthreaded front part 11 is surrounded by an assembly 2 comprising two contiguous half-cylinders 20 and 21. At the end near the cylindrical abutment 13 they have a peripheral groove 23 so that they may be retained by an elastic band 3 or similar means.
FIG. 1 shows the assembly and locking device in an initial state. In this state the two half-cylinders are abutted against the ring 13 and are inscribed within a cylinder having a diameter less than the inside diameter of the tube T.sub.2. Accordingly, the assembly can slide freely in a direction parallel to the previously mentioned axis of symmetry .DELTA..
In FIG. 1 the tubes T.sub.1 and T.sub.2 are shown in longitudinal section. The half-cylinder 20 is partly cut away in order to show more clearly how it cooperates with the screwthread 15. To be more precise, each half- cylinder has a raised pattern on its inside wall adapted to mesh with the screwthread 15. In FIG. 1 only the raised pattern 200 on the half-cylinder 20 can be seen.
As shown more particularly in FIG. 2, when a rotation R is imparted to the tube T.sub.1 the latter entrains the central member 1. It is assumed that the cylindrical sleeve 10 is forcibly fitted into the tube T.sub.1 and that the latter has fixing means, not shown, such as screws or similar means. The raised patterns associated with the two half-cylinders 20 and 21, for example the raised pattern 200, are entrained by the rotation imparted to the screwthread 15. It follows that the combination of the two half-cylinders 20 and 21 will move in translation towards the abutment 14, i.e. parallel to the axis of symmetry (arrow f). The raised patterns (for example 200) bearing on the surface of the screwthreaded area 11 and the latter itself being conical, the diameter increasing in the direction towards the abutment 14, the two half-cylinders 20 and 21 move apart at the end near the abutment 14. They are held close together at their other end by the elastic band 3.
It follows that the two half-cylinders 20 and 21 will come into contact with the inside wall of the tube T.sub.1 and apply pressure to it. This achieves the assembly and locking of the two tubes T.sub.1 and T.sub.2.
This device requires only low-cost, for example plastics material, parts, allowing manufacture by injection molding.
However, it is readily apparent from FIG. 2, which shows the device in the locked state, that the areas in which the bearing forces, and therefore the friction, are exerted are very small: end areas Z.sub.20 for the half-cylinder 20 and Z.sub.21 for the half-cylinder 21. It follows that the locking is somewhat unreliable. Furthermore, as the device relies on a buttress effect, there is a real risk of the components breaking if the two half-cylinders 20 and 21 are subjected to an excessively high force, i.e. if the relative rotation of the two tubes T.sub.1 and T.sub.2 is accentuated to increase the areas of contact.

Device for assembling and locking two tubes, and its application to the manufacture of a telescopic rod


An impact shield for earthquake protection is described herein. The impact shield may include a canopy constructed of a puncture-resistant material, the canopy defining a first internal volume accessible via a first opening, the canopy being structured to form a semispherical shape when in an inflated state, the semispherical shape defining a space dimensioned for sheltering at least one human body; a support joined to the canopy and constructed of the puncture-resistant material, the support defining a second internal volume accessible via the first opening and a second opening, the support located within the space, the support structured to form a column when in the inflated state; and a fitting joined to the support for closing the second opening to fix the first internal volume and the second internal volume after inflation of the support and the canopy.

There are more than 500,000 earthquakes annually throughout the world. Most of these earthquakes are low magnitude earthquakes with little to no impact on building structures or people. Approximately 3,000 earthquakes are perceptible by humans annually with approximately 4.7 million people impacted each year from these earthquakes. In 2015, there were over 1,500 earthquakes with a magnitude of 5.0 or greater on the Richter scale, resulting in almost 10,000 deaths.
On average, there are seven to eleven earthquakes annually that result in significant loss of life. Also, there are approximately 20 earthquakes a year that result in more than ten deaths, more than 100 people affected, a request for international assistance, or a declaration of a state of emergency. In addition to the loss of life and injuries that can occur, the economic impact of earthquakes can be devastating. Earthquakes in the United States alone are estimated to result in building damages of over $6 billion annually.
Populations continue to increase in areas that have high level of seismic activity, especially in urban communities along the western United States, Japan, China, South America, and India. By 2030, approximately 60 percent of the global population or approximately 5 billion people are expected to live in urban areas. Building construction and the propensity for buildings to collapse significantly contribute to mortality during earthquakes. For example, in the 1976 Guatemalan earthquake that resulted in approximately 23,000 deaths and over 75,000 injuries, all deaths and serious injuries occurred during the collapse of heavy adobe brick structures.


An optical imaging lens includes an aperture stop and an optical assembly, the optical assembly includes, in order from the object side to the image side: a first lens element with a positive refractive power; a second lens element with a positive refractive power; a third lens element with a negative refractive power; the aperture stop is located between an image-side surface of the first lens element and an object to be photographed; wherein a radius of curvature of an object-side surface of the first lens element is R1, a radius of curvature of the image-side surface of the first lens element is R2, a central thickness of the second lens element is CT2, a central thickness of the third lens element is CT3, and the following conditions are satisfied:−2.0<(R1+R2)/(R1−R2)<−0.2; 2.0<CT2/CT3<4.0.

1. Field of the Invention
The present invention relates to an optical imaging lens, and more particularly to a miniaturized optical imaging lens applicable to electronic products.
2. Description of the Prior Art
In recent years, mobile devices are continuously renovated, making more and more intense competition. In addition, with the mature technology development of various components, the difference between products becomes smaller, the only competition is price. Therefore, how to reduce the manufacturing cost and maintain good quality has become the aim of manufacturer's efforts.
Currently, small imaging lens with high image quality has become the standard equipment for mobile devices. In addition, as the advanced semiconductor manufacturing technologies have allowed the pixel size of image sensors to be reduced and compact, which makes the imaging lens featuring finer resolution or providing wider angle of view by providing with more than five or six lens elements, such as the imaging lenses described in US Publication Nos. 20130265650 and 20130329306. However, the imaging lenses consisting of three lens elements disclosed in U.S. Pat. Nos. 8,743,486 and 8,094,231 have small angle of view and aperture value.
The present invention has been made in order to solve the above-mentioned problems.


A syringe having barrel defining an outer circumferential surface, and a distal end including a non-luer tip that is not connectable to an intravenous device. The syringe barrel defines a snap-in, syringe engagement feature, adjacent to its distal end, oriented on its outer circumferential surface, which is selectively insertable within a bore of a complementary enteral collar. A proximal end of the enteral collar has a snap-in, enteral collar engagement feature, in the bore of the collar. In some embodiments, the snap-in, enteral collar engagement feature includes one or more cantilever snap joints, which engage a recess in the syringe engagement feature, upon axial insertion of the syringe tip into the bore of the collar. In some embodiments, the enteral collar engagement feature includes a discontinuous-annular snap joint. The enteral collar is sized to permit connection to an enteral device and prevent connection to a device having a luer connector.

Enteral nutrition involves delivery of nutrient formula or medicine to the gastrointestinal tract. Administration of nutrients to a patient can be accomplished with an enteral feeding system, assembly or device. Enteral feeding systems typically utilize catheters inserted into a patient's nose or mouth, through which nutrients are administered to the gastrointestinal tract. A syringe or another device may be connected to the catheter to deliver the nutrients through the catheter. Nutrients and food may also be directly administered to a patient's mouth by a syringe, which may be referred to as an "oral syringe" or "oral delivery" of medication and does not require connection to a catheter or other device. Intravenous catheters are inserted into the vasculature of patients to effect intravascular treatment, which delivering medication through the circulatory or cardiovascular system by accessing any blood vessel. Such catheters include intravenous (IV) catheters, which are inserted into veins, and intra-arterial catheters, which are inserted into arteries.
Syringes are used to deliver fluids for a variety of medical applications, including, for example, oral delivery of nutrients, storage and delivery of fluid to enteral systems by connecting the syringe to an enteral connection, and intravenous delivery of fluids or medication. Delivery of medication through intravenous syringes involves connecting the distal end of a syringe to a catheter by a luer connection. A standard male luer tip or standard male connector has specifications as provided by the International Organization for Standardization (ISO) defined in ISO 594-1:1986 and 594-2:1998, including a 6% taper that increases from the open distal end to the proximal end and an outer cross-sectional diameter at the distal end of the tip measuring between about 0.1545 inches (3.925 mm) and about 0.1570 inches (3.990 mm) for rigid material and between about 0.1545 inches (3.925 mm) and about 0.1585 inches (4.027 mm) for semi-rigid material. A standard female luer hub or standard female luer connector may have a 6% taper that decreases from the open proximal end to the distal end and an inner cross-sectional diameter at the open proximal end measuring between about 0.168 inches (4.270 mm) to about 0.170 inches (4.315 mm). In devices that have standard female luer connectors that incorporate tabs or lugs for connection to a corresponding male luer lock connector, the outer cross-sectional diameter of the standard female luer connector, including the lugs, is in the range from about 0.307 inches (7.80 mm) to about 0.308 inches (7.83 mm). In devices that have standard female luer connectors that do not incorporate tabs or lugs for connection to a corresponding male luer lock connector, the outer cross-sectional diameter may be about 0.224 inches (5.700 mm) for rigid connectors and about 0.265 inches (6.730 mm) for semi-rigid connectors, based on the maximum outside diameter of the standard female luer connector at the base of the lugs of ISO 594-2. The minimum length of the standard luer tip and/or the standard luer hub is 0.295 inches (7.500 mm), according to ISO 594-1. As used herein, the phrases "standard male luer connector," "standard male luer tip," "standard female luer hub" and "standard female luer connector" shall refer to connectors having the above dimensions.
Delivery of enteral fluid such as breast milk or formula from a syringe having a barrel and a plunger in the barrel is achieved by advancing the plunger into the barrel to pressurize the fluid within the barrel and discharge the fluid from the distal tip of the syringe. Oral dose syringes have a barrel with distal tip defining a channel having a diameter substantially larger than the diameter of a needle cannula. For a typical oral syringe, the distal tip defines a smooth exterior surface that is insertable into the mouth of a patient to orally introduce medication or other fluids into a patient.
Limiting the use of standard luer tips and connectors to use with vascular access systems is one consensus accepted by device manufacturers and regulatory bodies. For example, the recent adoption of ISO 80369-3 provides a uniform standard for small bore connectors for enteral applications. However, the adoption of ISO 830369-3 will result in a variety of syringe types to deliver fluids to patients intravenously, orally and enterally. It would be desirable to provide a syringe that could be used to connect to enteral systems having enteral connections meeting the ISO 80369-3 standard and also be used as on oral syringe, while preventing connection to standard luer tips and connectors.

Syringe with snap-in enteral connection feature


A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board alongside the rows of the memory chips. A control bus connects the ECC memory chips and also the memory chips to the control chip. In a region remote from the control chip, the control bus branches in a contact-making hole into a first partial bus, to which a first group of memory chips are connected, and a second partial bus, to which a second group of memory chips are connected. The ECC memory chips are likewise connected to the control bus via the contact-making hole. Since the ECC memory chips are not arranged directly under the control chip, a bus branch directed backward is not required. As a result, space considerations on the module circuit board are eased and signal integrity on the control buses is improved.

FIG. 1 shows a conventional memory chip U, which is embodied for example as a DRAM (dynamic random access memory) memory chip. The memory chip U comprises a memory cell array SZF, in which memory cells SZ are arranged in matrix-like fashion along word lines WL and bit lines BL. A memory cell SZ comprises a selection transistor AT and a storage capacitor SC. In the case of a read or write access, the selection transistor AT is controlled to be put into an on state by a corresponding control signal on the word line WL. Consequently, the storage capacitor SC is connected to the bit line BL via the selection transistor AT controlled in the on state. In the event of a read access, data amplified by a sense amplifier (not illustrated in FIG. 1) can be fed via the bit line BL to a data terminal DIO for outputting. In the event of a write access, via the selection transistor AT controlled in the on state, data can be written to one of the memory cells SZ from the data terminal DIO via the bit line BL.
The memory chip U furthermore comprises a control circuit S with control terminals S1, S2, S3 and S4, to which external control signals CS, WE, RAS and CAS can be applied. Address terminals A0, . . . , An for application of address signals AS0, . . . , ASn are connected to an address register AR. An address signal presented at the address terminals is forwarded as a row address to a row decoder RD and as a column address to a column decoder CD.
Write and read accesses to the memory chip are synchronized to a clock signal CLK at a clock terminal T. In the event of a write access to a memory cell of the memory chip U, address signals AS0, . . . , ASn are supplied the address terminals A0, . . . , An to select one of the memory cells of the memory cell array SZF for the write access.
For selection of the memory chip U for the write access, a chip select signal CS is applied to the control terminal S1. Simultaneously with this, the row select signal RAS is applied to the control terminal S3. According to the applied row address, a word line WL of the memory cell array SZF is activated by the row decoder RD. As a result, all selection transistors AT which are connected along the activated word line are controlled to be put into an on state. For selection of a specific memory cell along the activated word line, subsequently the chip select signal CS is applied to the control terminal S1, the write enable signal WE is applied to the control terminal S2 and the column select signal CAS is applied to the control terminal S4. According to the column address applied to the address terminals, the column decoder CD activates one of the bit lines BL of the memory cell array for the write access. That memory cell that lies at a crossover point between the activated word line and the activated bit line is thereby selected for a write access.
After a precharge operation, during which all the bit lines of the memory cell array are brought to a common voltage, a read access can be made to one of the memory cells. For selection of the memory cell to be read, the address terminals A0, . . . , An are again driven by an address signal AS0, . . . , ASn containing a row address and a column address. For selection of the memory chip U for the read access, the control circuit S is driven by the chip select signal CS at the control terminal S1 and by the row select signal RAS at the control terminal S3. According to the applied row address, the row decoder RD selects one of the word lines WL and, by means of a corresponding voltage potential on the selected word line, activates all the memory cells SZ which are connected along the selected word line. Thereafter, the chip select signal CS is applied to the control terminal S1 and the column select signal CAS is applied to the control terminal S4. The column decoder CD in response selects one of the bit lines BL according to the column address. The memory cell that lies at a crossover point between the selected word line and the selected bit line is thereby selected for the read access.
Memory chips of this type are generally combined on a semiconductor memory module to form a larger memory unit. The individual memory chips on the semiconductor memory module can no longer be directly driven externally with control and address signals, but rather are shielded from the outside world by means of a control chip. A memory controller accesses the control chip, which in turn drives the individual memory chips on the semiconductor memory module for a read and write access with control signals, address signals and data signals.
FIG. 2 shows a conventional semiconductor memory module HSM, in which a control chip HC is embodied as a hub chip, by way of example, and memory chips U1, . . . , U36 are arranged on a module circuit board MP. The semiconductor memory chips in the example of FIG. 2 have a ×4 organizational form. In the case of this organizational form, four items of data are simultaneously read into the memory cells of a memory chip in the event of a write access, and four items of data are simultaneously read out from the memory cells of a memory chip in the event of a read access. Those memory chips which are simultaneously addressed by the memory controller or the control chip HC in the event of an access to the semiconductor memory module are combined in groups, so-called ranks. The number of memory chips belonging to a rank is dependent on the bus width of the access bus with which the memory controller accesses the semiconductor memory module, and on the organizational form of the memory chips on the memory module. If the control chip is driven by a memory controller via an access bus having a bus width of 72 bits and the memory chips have the ×4 organizational form, it is possible, in the event of a read or write access to the semiconductor memory module, for four items of data in each case to be simultaneously read out from 18 memory chips or for four items of data in each case to be simultaneously written to 18 memory chips. A rank therefore comprises 18 memory chips. The semiconductor memory module of FIG. 2 comprises two ranks each having 18 memory chips and therefore represents a 2R×4 module configuration.
The module circuit board MP of FIG. 2 has a top side TOP and a bottom side BOT. In accordance with an industry standard for a memory module of the 2R×4 module configuration, the control chip HC is arranged in the center on the top side TOP of the module circuit board. The individual memory chips U1, . . . , U4, U9, . . . , U12, U17, . . . , U20 and U25, . . . , U28 are arranged in two rows on the top side of the module circuit board on the left and right of the control chip.
The rest of the memory chips U5, . . . , U8, U13, . . . , U16, U21, . . . , U24 and U29, . . . , U32 are likewise arranged in two rows on the bottom side BOT of the module circuit board. The individual memory chips each contain a memory cell array SZF, as shown in FIG. 1, for storing data. The memory chips U33, U34, U35 and U36, which, in accordance with an industry standard, are positioned on the bottom side BOT of the module circuit board directly under the control chip HC, are embodied as ECC (error correcting code) memory chips. Data for error correction are stored in the memory cells of their memory cell array. When reading from a memory chip, a datum read out erroneously from a memory chip can be corrected by the control chip HC by means of such error correction data stored in the ECC memory chips.
In order to drive the individual memory chips and also the ECC memory chips with control and address signals, the control chip HC is connected to the individual memory chips and the ECC memory chips via a control bus CAB. The design of the control bus CAB for a memory module of the 2R×4 module configuration is explained hereinafter with reference to FIGS. 3 and 4.
FIG. 3 shows a conventional control chip HC. The control chip HC is connected via the control bus CAB to the memory chips U1, . . . , U4 in a row R11 on the top side TOP of the module circuit board, to the memory chips U9, . . . , U12 in a row R12 on the top side TOP of the module circuit board, to the memory chips U5, . . . , U8 in a row R21 on the bottom side BOT of the module circuit board, to the memory chips U13, . . . , U16 in a row R22 on the bottom side of the module circuit board and to the two ECC memory chips U33 and U34.
FIG. 4 shows a detail from a cross section through a conventional module circuit board MP. The control chip HC and also the two memory chips U1 and U2 are arranged on the top side of the module circuit board. The ECC memory chip U33 is arranged on the bottom side of the module circuit board below the control chip HC. The memory chips U5 and U6 are arranged on the bottom side of the module circuit board under the memory chips U1 and U2. The control chip HC is connected to a contact-making hole V0 via a short conductor track LHC on the top side TOP of the module circuit board MP. The control chip HC is connected to the control bus CAB via the short conductor track LHC on the top side of the module circuit board and the contact-making hole V0.
The control bus CAB runs on an internal layer INT1 of the module circuit board. At the contact-making hole V1, the control bus CAB branches into a partial bus CAB1 and a partial bus CAB2. The memory chips U, . . . , U4 of the row R11 on the top side of the module circuit board, the memory chips U5, U8 of the row R21 on the bottom side of the module circuit board and the ECC memory chip U33 are connected to the partial bus CAB1. FIG. 4 illustrates an example of only part of the partial bus CAB1.
The partial bus CAB1 runs on the internal layer INT1 as far as a contact-making hole V1. The memory chip U1 is connected to the partial bus CAB1 via a short conductor track L1 on the top side of the module circuit board and the contact-making hole V1. The memory chip U5 is connected to the partial bus CAB1 via a short conductor track L5 on the bottom side of the module circuit board and the contact-making hole V1. Proceeding from the contact-making hole V1, the partial bus CAB1 runs further along the internal layer INT1 to contact-making holes V11, V12 and V13. The memory chips U2 and U6 are connected to the partial bus CAB1 via the contact-making hole V11 and a short conductor track L2 on the top side of the module circuit board and, respectively, a short conductor track L6 on the bottom side of the module circuit board. The memory chips U3 and U7 are connected to the partial bus CAB1 via the contact-making hole V12 and a short conductor track L3 on the top side of the module circuit board and, respectively, a short conductor track L7 on the bottom side of the module circuit board. The memory chips U4 and U8 are connected to the partial bus CAB1 via the contact-making hole V13 and a short conductor track L4 on the top side of the module circuit board and, respectively, a short conductor track L8 on the bottom side of the module circuit board. Through a contact-making hole V14, the partial bus CAB1 is connected to the top side of the module circuit board and from there, via a short conductor track LR, to a terminating resistor R at its end ECAB1. The terminating resistor R is connected to a voltage supply Vtt.
The partial bus CAB2 runs on a further internal layer INT2 of the module circuit board. Proceeding from the contact-making hole V0, the partial bus CAB2 runs as far as a contact-making hole V2. The memory chips U9 and U13 are connected to the partial bus CAB2 via the contact-making hole V2 and a short conductor track L9 on the top side of the module circuit board and, respectively, a short conductor track L13 on the bottom side of the module circuit board. From the contact-making hole V2, the partial bus CAB2 runs further on the internal layer INT2 of the module circuit board via further contact-making holes V21, V22 and V23 as far as a contact-making hole V24. The memory chips U10 and U14 are connected to the partial bus CAB2 via the contact-making hole V21 and a short conductor track L10 on the top side of the module circuit board and, respectively, a short conductor track L14 on the bottom side of the module circuit board. The memory chips U11 and U15 are connected to the contact-making hole V22 via the contact-making hole V22 and a short conductor track L11 on the top side of the module circuit board and, respectively, a short conductor track L15 on the bottom side of the module circuit board. The memory chips U12 and U16 are connected via a short conductor track L12 on the top side of the module circuit board and, respectively, a short conductor track L16 on the bottom side of the module circuit board and the contact-making hole V23 to the internal layer INT2 and thus to the partial bus CAB2. An end ECAB2 of the partial bus CAB2 is terminated via a terminating resistor R and a voltage supply Vtt via the contact-making hole V24 and a short conductor track LR′ on the top side of the module circuit board.
A branch of the partial bus CAB1, proceeding from the contact-making hole V1, runs along the internal layer INT2 in the backward direction of the ECC memory chip U33 as far as a contact-making hole V20 positioned below the contact-making hole V0 for connecting the ECC memory chip U33 to the control bus CAB. The ECC memory chip U33 is connected via a short conductor track L33 and the contact-making hole V20 to the branch of the partial bus CAB1 which runs on the internal layer INT2. The ECC memory chip U34 is also connected to the control bus CAB in a similar manner. Proceeding from the contact-making hole V2, a branch of the partial bus CAB2 runs along the internal layer INT1 of the module circuit board in the backward direction of the ECC memory chip U34 as far as a contact-making hole V10 and from there via a short conductor track L34 on the bottom side of the module circuit board to the ECC memory chip U34.
As is illustrated in FIGS. 3 and 4, the control bus CAB branches into a partial bus CAB1 and a partial bus CAB2 in the region of the contact-making hole V0. Proceeding from the contact-making hole V1, a branch of the partial bus CAB1 runs on the internal layer INT2 back to the ECC memory chip U33 again, which is positioned under the control chip HC on the module circuit board. Likewise, proceeding from the contact-making hole V2, a branch of the partial bus CAB2 runs via the internal layer INT1 back to the ECC memory chip U34 again, which is likewise arranged under the control chip HC on the bottom side of the module circuit board.
The contact-making holes V0, V1, V2, V10 and V20 are all arranged in a narrow region around the control chip HC. FIG. 5 shows a detail from an internal layer of a conventional module circuit board with contact-making holes and conductor tracks in a region B in the vicinity of the control chip HC. As shown in FIG. 5, a shortage of space occurs in this region by virtue of the numerous terminal connections of the control chip HC and also the numerous contact-making holes and bus lines, in particular due to the bus lines that run back in the direction of the ECC memory chips for the purpose of connecting to the ECC memory chips. Therefore, it is not possible to implement the branches of the partial buses CAB1 and CAB2 (for connecting the ECC memory chips to the control chip) in accordance with the standard shown in FIG. 3. In a 2R×4 module configuration this situation arises particularly when the input and output terminals of the control chip HC do not conform to a standard. In this case, the memory module, the positioning of the memory chips on the module circuit board and the bus architecture of the control bus have to be implemented in customized fashion. This is not desirable.

Semiconductor memory module with error correction


The invention relates to a device for determining the driving behavior of a driver, the device comprising at least means for receiving data from two or more data sources, of which at least one produces data relating to changes in the state of motion of a vehicle and at least one other produces measured data on the well-being of the driver; means for scoring the received data by comparing it with data-specific reference values; means for forming a respective sub-index from each scored item of data; means for determining a driving behavior index on the basis of the formed sub-indices; and means for controlling control equipment of the vehicle on the basis of the driving behavior index and/or for storing the driving behavior index in a database.

The state and condition of a driver of a vehicle are important factors affecting safe driving. For detecting a decrease in alertness and for detecting use of drugs or alcohol, devices are available by which the driver can be instructed to take a break or, in an extreme situation, prevented from starting of the vehicle.
By said devices, factors affecting the driver's capability to drive are monitored during driving or right before starting to drive. Moreover, such devices are used for looking merely at a single factor affecting the capability to drive. Therefore, existing devices are not capable of making an overall assessment of the driver's driving behavior, considering not only the condition during driving but also factors having a more general impact on the person's driving performance.

Device, a method, and a computer program for determining the driving behavior of a driver


A floating connector comprises a movable housing, a regulating member and a plurality of contacts. Each of the contacts is made of a single metal plate. Each of the contacts has a fixed portion, a regulated portion, a held portion, an extending portion, a contact portion and a coupling portion. The coupling portion is resiliently deformable. The movable housing is movable within a predetermined range in a plane perpendicular to an up-down direction by the resilient deformation of the coupling portion. The coupling portion has a first portion, a second portion and a bent portion. Each of the first portion and second portion has a principal surface. The principal surface of the first portion faces in a first direction. The principal surface of the second portion faces in a second direction. The first direction and the second direction are different from each other.

This invention relates to a floating connector used in a state where the floating connector is mounted on a circuit board.
As shown in FIG. 36, JPA2018-116825 (Patent Document 1) discloses a floating connector 900 of this type. As shown in FIGS. 36 and 37, the floating connector 900 comprises a movable housing 920, a fixed housing main 910, or a regulating member 910, and a plurality of contacts 950. The movable housing 920 has second holding portions 922, or holding portions 922. The regulating member 910 has first holding portions 912, or regulating portions 912. Each of the contacts 950 is formed by punching out a blank from a metal plate and bending the blank. Each of the contacts 950 has a fixed portion 952, a first held portion 954, or a regulated portion 954, a second held portion 956, or a held portion 956, an extending portion 958, a contact portion 959 and a coupling portion 957. The fixed portion 952 is configured to be fixed to a circuit board (not shown). A movement of the regulated portion 954 in a pitch direction, or in a Y-direction, is regulated by the regulating portion 912. The held portion 956 is held by the holding portion 922. The extending portion 958 extends upward from the held portion 956. The contact portion 959 is supported by the extending portion 958. The coupling portion 957 couples the regulated portion 954 and the held portion 956 with each other. The contact portion 959 is brought into contact with a mating contact portion (not shown) when the floating connector 900 is mated with a mating connector (not shown). The coupling portion 957 is resiliently deformable. The movable housing 920 is movable relative to the regulating member 910 at least in a horizontal direction, or in an X-direction, by the resilient deformation of the coupling portion 957.
When a movable housing is moved in a pitch direction in a floating connector, similar to the floating connector 950 of Patent Document 1, which comprises a contact 950 formed by punching out a blank from a metal plate and bending the blank, torsional stress might occur in a held portion of the contact so that a problem might arise in the contact.

JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED


Clamping tool especially suitable for guitar repair which can be inserted into the sound hole of a guitar, with tensioning means spaced from the point at which force is applied to the instrument.

The guitar has been used for centuries, and has become one of the world's most popular instruments. In recent years, renewed interest in vintage guitars has created a demand for the repair of older instruments. One frequent need for repair of these instruments is replacement or reattachment of the bridge, which requires clamping of the guitar through the sound hole. A variety of "C" clamps have previously been used which exert force on the bridge through pressure at the ends of the clamp, the pressure being applied either through screws or lever action at the point to which pressure is desired. However, previous clamping devices have not been entirely satisfactory because of either or both of difficulty in manufacturing or lack of adjustibility.