An oil filter drainage box having a plurality of support members for holding spent oil filters. The drainage box comprises a container having four side walls, a lid and a base member. The spent oil filters are placed on the support member and the residual oil in the filters drains out due to gravitational forces. The base member is inclined slightly to allow the oil to collect in a reservoir which is situated within the base member. There is a plurality of support posts extending upwardly perpendicular to the base member for engaging the spent oil filters. The lid provides a watertight seal which prevents the oil from leaving the box and damaging the environment. The reservoir is provided with a valve assembly. The valve assembly has a coupling which is attached to the reservoir, a valve, and a hose. The hose is attached to an oil vacuuming unit, which is preferably mobile and carries a complement of storage tanks and air compressor/vacuuming units. When the valve is opened, the oil is vacuumed out of the reservoir with little possibility of oil contaminating the ground.

1. Field of the Invention
The present invention relates to an apparatus for collecting spent oil filters and the oil contained therein. More specifically, the invention is a box having a self sealing lid, drainage posts and a reservoir for storing waste oil for use with a oil tank and vacuuming system.
2. Description of the Related Art
When an oil change is performed, people go to great lengths to ensure that not a single drop of oil reaches the ground. However, what most people fail to realize is that a significant amount of oil remains in the oil filter. Often these filters are discarded as ordinary trash, and the waste oil contained therein eventually finds its way to land fills and ultimately into the ground.
Several patents have addressed the issue of changing motor oil and retrieving waste oil from the oil filters. Patents that disclose apparatus for changing lube oil are U.S. Pat. No. 3,867,999 (Method and Apparatus for Changing Lube Oil) issued on Feb. 25, 1975 to Cox; U.S. Pat. No. 5,154,775 (Integrated Method for Cleaning and Flushing an Internal Combustion Engine) issued on Oct. 13, 1992 to Bedi; U.S. Pat. No. 5,476,154 (Powered Oil Change Apparatus) issued on Dec. 19, 1995 to Sage; U.S. Pat. No. 5,562,181 (Apparatus and Method for Automatically Performing Engine Fluid Changes) issued on Oct. 8, 1996 to Elkin et al.; and Canadian Patent No. 643,749 (Internal Combustion Engines) issued on Jun. 26, 1962.
U.S. Pat. No. 5,168,959 issued on Dec. 8, 1992 to Davis discloses a container with a lid which has apertures therethrough which are adapted for receiving the nozzles of fluid bottles such as oil containers. The Davis patent does not disclose housing spent oil filters within a drainage container to prevent the containers from easily tipping. Further, Davis does not teach a method for removing fluid from the container using a vacuuming means.
U.S. Pat. No. 5,299,714 issued on Apr. 5, 1994 to Kilgore discloses a tool for removing oil from a spent oil filter. The tool has a sharp end which pierces the outer casing of the oil filter and the oil drains through a tube in the shaft of the tool. Kilgore does not teach the use of draining posts for draining oil filters into a reservoir which is ultimately vacuumed out as in the present invention.
U.S. Pat. No. 5,477,897 issued on Dec. 26, 1995 to Scofield discloses a recovery system for new oil including a container with ports therein for receiving the nozzle end of one quart oil containers. The oil drains into a larger container which can be used for various purposes. The patent to Scofield does not teach the use of an enclosed container for housing spent oil filters in order to provide a watertight stable environment to prevent the oil from damaging the environment.
U.S. Pat. No. 5,489,042 issued on Feb. 6, 1996 to Ewald discloses a container for storing waste oil and a stand for holding an oil filter within the container such that its contents may drain over time. There is a lid provided with a recess therein adapted for receiving the oil filter such that the lid can be securely fastened while the oil filter is in the container. Ewald does not teach a means for capturing the waste oil such that it can be readily drained out by a vacuum or similar means.
U.S. Pat. No. 5,505,295 issued on Apr. 9, 1996 to Whittington discloses a container capable of holding motor oil. The top surface of the container has pegs for holding oil bottles and filters and apertures through which waste oil can drain into the container. Whittington does not disclose a container which houses the spent oil filters or oil bottles such that they are stable and not subject to contact with the environment. Further, Whittington does not teach the use of a vacuuming or similar means to drain the waste oil from the container.
U.S. Pat. No. 5,524,356 issued on Jun. 11, 1996 to Lutz discloses an apparatus for low cost extraction of oil residue from oil filters. The filters are strapped to a mounting apparatus which is oscillated by a mechanical means whereby the oil which is not drained by gravitational forces is shaken free. The oil is collected in a separate pan located beneath the apparatus. Lutz does not teach the use of an integrally connected reservoir to collect waste oil which is then removed from the reservoir by vacuuming or similar means.
U.S. Pat. No. 5,611,377 issued on Mar. 18, 1997 to Maguire discloses a device for facilitating the draining of residual oil or fuel remaining in an oil or fuel filter. The filters are placed on a screen through which the oil can drain. There is no means for supporting the filters such that they are prevented from tipping over inadvertently.
U.S. Pat. No. 5,647,414 issued on Jul. 15, 1997 and U.S. Pat. No. 5,653,271 issued on Aug. 5, 1997 to Brittain et al. discloses an oil filter recycle apparatus comprising a bucket having a support therein for holding the oil filters. There is no means for supporting the oil filters as in the present invention. Further, there is a drain assembly that can be inserted in the bucket to remove the waste oil once the filters have completely drained, but the drain assembly is not always in place as in the present invention.
U.S. Pat. No. 4,420,023 issued on Dec. 13, 1983 to Cislak discloses an apparatus for collecting viscous fluid for future use from a bearing or similar device. The invention in Cislak does not disclose a container which is suitable for draining spent oil filters.
World Patent WO 89/09362 published on Oct. 5, 1989 discloses a fluid collection and drainage pan. The pan does not disclose a vacuuming or similar means for draining the collected fluid as in the present invention.
British Patent No. 1,432,610 published on Apr. 22, 1976 discloses a container adapted for receiving spent motor oil from the crankcase of a car. The oil is then forced out of the container by operating a pump with compressed air. The patent does not teach or describe a constant vacuum connected to the outlet of the container that can be activated by simply opening a valve.
Other patents which are generally related to the present invention are U.S. Pat. No. 5,406,691 (Apparatus for Recycling Oil Canister Filters) issued on Apr. 18, 1995 to Thorne; and British Patent No. 1,416,096 (Container for Waste Engine Oil) published on Dec. 3, 1975.
None of the above inventions and patents, taken either singularly or in combination, is seen to describe the instant invention as claimed. Thus an oil filter drainage box solving the aforementioned problems is desired.

Oil filter drainage box and recovery system


Apparatus and methods of controlling call establishment are described. A user equipment (UE) may determine to establish a call. In an aspect, the UE may detect a Wireless Local Area Network (WLAN) access node and receive, from a Wireless Wide Area Network (WWAN) access node, WWAN load-related information. Based on UE call establishment rules and the WWAN load-related information, the UE may determine whether to establish the call on the WWAN access node or the WLAN access node. In another aspect, the UE may determine WLAN access node characteristics associated with a received signal from a WLAN access node. The UE may forward a call establishment request, including the WLAN access node characteristics to a WWAN access node. The UE may receive a redirection command to redirect the call establishment request to the WLAN access node.

1. Field
Aspects of the present disclosure relate generally to wireless communication systems, and more particularly, apparatus and methods of controlling call establishment.
2. Background
Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such networks, which are usually multiple access networks, support communications for multiple users by sharing the available network resources. One example of such a network is the UMTS Terrestrial Radio Access Network (UTRAN). The UTRAN is the radio access network (RAN) defined as a part of the Universal Mobile Telecommunications System (UMTS), a third generation (3G) mobile phone technology supported by the 3rd Generation Partnership Project (3GPP). The UMTS, which is the successor to Global System for Mobile Communications (GSM) technologies, currently supports various air interface standards, such as Wideband-Code Division Multiple Access (W-CDMA), Time Division-Code Division Multiple Access (TD-CDMA), and Time Division-Synchronous Code Division Multiple Access (TD-SCDMA). The UMTS also supports enhanced 3G data communications protocols, such as High Speed Packet Access (HSPA), which provides higher data transfer speeds and capacity to associated UMTS networks.
It may be desirable for a radio access network (RAN) Node, such as a cellular or Wireless Wide Area Network (WWAN) base station or NodeB, to offload traffic to another radio access technology (RAT) access node, such as a WiFi or Wireless Local Area Network (WLAN) access point, capable of supporting the traffic. Existing solutions include a network access stratum (NAS)-based function, referred to as an access network domain selection function (ANDSF), and upper layer/operating system (OS)-based functions. Such existing solutions make determinations based on static rules for call establishment.
As such, in such conventional systems, it is not possible to control, from within the cellular RAN, an idle UE that is camping on the cellular network, in order to direct the idle UE to establish a new packet-switched (PS) call using, for example, a WiFi access point, rather than a cellular access point. Similar issues exist for UEs in some reselection states in, for example, UMTS. In other words, a UE cannot be dynamically directed to establish a call using a non-cellular-based access point in order to offload new traffic related to a newly-established call from the RAN node when possible.
Thus, improvements in call establishment are desired.


In apparatus for wavelength stabilizing and spectrally narrowing an output beam of a diode-laser, a cylindrical lens is arranged to collimate the beam in the fast axis of the diode laser without reducing divergence in the slow axis of the diode-laser. An optical fiber is arranged to receive the fast-axis collimated beam from the lens. The optical fiber has a multimode core surrounded by a first cladding, the first cladding being surrounded by a second cladding. The core of the optical fiber includes a wavelength selective Bragg grating and has a numerical aperture of about 0.06 or less. The optical fiber has a numerical aperture of about 0.15 or greater. The fast-axis collimated beam and the relatively low numerical aperture of the core provide that the Bragg grating only reflects light that propagates about parallel to the longitudinal axis of the fiber. Light reflected from the grating is fed back to the diode-laser for stabilizing the wavelength and spectrally narrowing the diode-laser output beam.

Diode-laser light is commonly used for optically pumping solid-state lasers and fiber lasers. As light from a single diode-laser is often insufficiently powerful for such pumping, it is usual to use light from a plurality of diode-lasers arranged in a linear array. Such an array is commonly referred to by practitioners of the art as a diode-laser bar. The light from the diode-lasers in the bar must be collected by an optical arrangement that makes the sum of the outputs of the diode-lasers available for pumping.
Light is emitted from a diode-laser as a diverging beam. The beam diverges strongly, for example at about 35 degrees, in one axis, termed the fast axis, and diverges weakly, for example at about 10 degrees, in an axis (the slow axis) perpendicular to the fast axis. In a diode-laser bar, individual diode-lasers (emitters) are arranged, spaced apart, linearly, in the slow axis direction. In a high power diode-laser of the type used for optical pumping, light is emitted in a plurality of modes (multimode output). A preferred method of collecting the outputs of the plurality of emitters of a diode-laser bar is to couple the individual emitter outputs into a corresponding plurality of multimode optical fibers having entrance ends thereof arranged in a linear array aligned with the slow axis of the diode laser bar. A cylindrical microlens is used to collimate the emitter output in the fast axis. The fast-axis-collimated output is coupled into the fibers. Output ends of the optical fibers are formed into a bundle. Light output from the bundle can be collected by a lens and focused directly into a solid-state gain medium or into a single optical fiber. The single optical fiber can be a transport fiber or a fiber laser to be pumped.
In the gain medium of a solid-state laser or a fiber laser, absorption of optical pump light can often only occur in a narrow band of wavelengths, for example, about 1 nanometer (nm) wide. This narrow band of wavelengths is centered on a fixed, peak absorption wavelength that is characteristic of the gain-medium (active layer material) of the diode-laser. Absent any constraint, diode-laser light is emitted in a relatively broad spectrum of wavelengths, for example between 2 nm and 5 nm. Accordingly, for optimizing optical pumping efficiency, it is preferable to provide a constraint that narrows the emission bandwidth and stabilizes the center wavelength of this narrowed emission bandwidth at the characteristic peak absorption wavelength of the gain-medium.
One arrangement that has been used to narrow the bandwidth and stabilize the wavelength of the output of a single mode diode-laser coupled into the core of a single mode fiber, is to write a fiber Bragg grating into the core of the fiber. The refractive index modulation and the period of modulation of the Bragg grating are selected such that the grating reflects back into the diode-laser a few percent (usually less than 10%) of radiation propagating in the core. The radiation is reflected in a bandwidth less than about 1 nm about a peak-reflection wavelength determined by the modulation period of the grating. This forces the diode laser to emit at the peak-reflection wavelength of the grating and with a bandwidth about equal to the reflection bandwidth of the grating.
This method, however, is not suitable for use with multimode fibers, as a multimode fiber supports all the directions (angles) of propagation within its numerical aperture. The peak reflection wavelength of a fiber Bragg grating depends not only on the modulation period but on the angle of incidence of light on the grating. Accordingly, in a multimode fiber core, a Bragg grating would have a reflection bandwidth broadened by the plurality of angles at which the multimode light was incident thereon. The grating would provide neither adequate-bandwidth narrowing nor adequate wavelength stabilization. There is a need for an arrangement for stabilizing the wavelength and narrowing the bandwidth of the output of a multimode-fiber-coupled, multimode diode-laser bar.

Wavelength-locked fiber-coupled diode-laser bar


An aspect of the present invention provides a magnetic sensor which is operated better at a high temperature range not lower than 300° C. compared with a conventional magnetic sensor. A operating layer having a heterojunction interface is formed by laminating a first layer made of GaN whose electron concentration is not more than 1×1016/cm3 at room temperature and a second layer made of AlxGa1-xN (0<x≦0.3). Therefore, in a two-dimensional electron gas region, carrier mobility is further enhanced while a carrier concentration is further lowered. Accordingly, there is realized a Hall element which can be used with measurement sensitivity similar to that at room temperature by constant-current drive even at a high temperature, while having the high measurement sensitivity in both the constant-current drive and constant-voltage drive at room temperature.

1. Field of the Invention
The present invention relates to a magnetic sensor whose operating layer is made of a group-III nitride semiconductor.
2. Description of the Background Art
It is known that magnetic sensors such as a Hall element and a magnetoresistive effect element whose operating layer is made of a semiconductor material exhibit higher sensitivity with increasing carrier mobility of the semiconductor material used. Therefore, conventionally compound semiconductors such as InSb and InAs which exhibit high electron mobility have been used for the operating layer of the magnetic sensor (refer to, e.g., "Physical properties of InSb single-crystal thin film and magnetic sensor application", IEEJ Transactions on Electrical and Electronic Engineering E, Vol. 123, No. 3 (2003), pp. 69-78). For example, the Hall element in which Hall effect of a thin-film of InSb or InAs is utilized is extensively used as a magnetic sensor of DC brushless motor.
There is also known a magnetic sensor whose operating layer is made of a group-III nitride semiconductor having a wide bandgap (refer to, e.g., Japanese Patent Application Laid-Open Nos. 2003-060255 and 2006-080338). This magnetic sensor has an advantage that a characteristic change is hardly generated even at a high temperature although it is inferior in the carrier mobility and sensitivity to the magnetic sensor for which InSb or InAs is used. Particularly, Japanese Patent Application Laid-Open No. 2006-080338 discloses that a magnetic sensor whose operating layer having an AlxG1-xN/GaN (0.3<x≦0.5) heterostructure can well operated at 300° C. or more (in a range of 0° C. to 800° C.).
There is also known a technique of suitably controlling a donor concentration in forming an N-type group-III nitride semiconductor layer (refer to, e.g., Japanese Patent Application Laid-Open No. 2005-035869).
As described in Japanese Patent Application Laid-Open No. 2003-060255, in the case of the magnetic sensor for which InSb or InAs is used, there is widely known a drawback that the magnetic sensor cannot be used at a high temperature because of temperature dependence of a Hall voltage measured under a condition of constant magnetic flux density.
Japanese Patent Application Laid-Open No. 2003-060255 specifically discloses only the fact that the magnetic sensor whose operating layer is made of the group-III nitride semiconductor operates in a temperature range not more than 200° C. There is disclosed no specific fact that the magnetic sensor functions well at a high temperature range not lower than 300° C. or no requirement to realize the magnetic sensor well operated in the high temperature range not lower than 300° C. That is, Japanese Patent Application Laid-Open No. 2003-060255 does not disclose the magnetic sensor well operated in the high temperature range not lower than 300° C. The same holds true for Japanese Patent Application Laid-Open No. 2006-080338.
On the other hand, in Japanese Patent Application Laid-Open No. 2006-080338, a range of x≦0.3 is excluded in the AlxG1-xN/GaN heterostructure constituting the operating layer of the magnetic sensor. For the case of the AlxG1-xN/GaN heterostructure, because the electron mobility in the range of x≦0.3 is larger than that in the range of 0.3<x≦0.5, the higher-sensitivity magnetic sensor which is well operated at 300° C. or more is realized if the range of x≦0.3 is utilized.

Magnetic sensor, hall element, hall IC, magnetoresistive effect element, method of fabricating hall element, and method of fabricating magnetoresistive effect element


A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.

1. Field of the Invention
The present invention relates to a signal processing circuit including a memory circuit in which a stored logic state is not lost even after power is turned off, and to an electronic device using the signal processing circuit. Further, the present invention relates to a method of driving a signal processing circuit including a memory circuit in which a stored logic state is not lost even after power is turned off.
2. Description of the Related Art
Signal processing circuits such as central processing units (CPUs) vary in structure depending on the intended use. A signal processing circuit generally has a main memory for storing data or a program and other memory circuits such as a register and a cache memory.
A register has a function of temporarily holding data in order to carry out arithmetic processing or hold a program execution state, for example. In addition, a cache memory is located between an arithmetic circuit and a main memory in order to reduce access to the low-speed main memory and speed up the arithmetic processing.
In a memory circuit in a signal processing circuit, such as a register or a cache memory, data writing and data reading need to be performed at higher speed than in a main memory. For this reason, in general, a flip-flop circuit is used as a register, and a static random access memory (SRAM) is used as a cache memory. That is, as a memory circuit such as a register or a cache memory, a volatile memory circuit in which data is lost after supply of power supply voltage is stopped is used.
Further, in order to suppress power consumption, a method in which supply of power supply voltage to a signal processing circuit is temporarily stopped in a period during which data is not input/output has been suggested (e.g., see Patent Document 1).
In Patent Document 1, a non-volatile memory circuit is located in the periphery of a volatile memory circuit such as a register or a cache memory. Data is temporarily stored in the non-volatile memory circuit while supply of power supply voltage to a signal processing circuit is stopped.
Meanwhile, in recent years, metal oxides having semiconductor characteristics (also referred to as oxide semiconductors) have attracted attention. Oxide semiconductors can be applied to transistors (e.g., see Patent Documents 2 and 3).

Semiconductor Energy Laboratory Co., Ltd.


An illumination device generally comprises a housing, a light source, and a scattering member. The housing includes a base portion and a side wall, which collectively defines an interior cavity with an open end having a predetermined shape. A light source is positioned within the interior cavity, along with an electric connecting member adapted to connect the light source to a remote power source. A scattering member having substantially the same predetermined shape as the open end of the housing is positioned adjacent the light source at the open end of the interior cavity. The scattering member has a light-emitting surface and is composed of a material which causes light entering the scattering member to be directed through a portion of thereof before being scattered and emitted, such that a substantially uniform light pattern is perceived along the light-emitting surface of the scattering member in the predetermined shape.

Channel letters are commonly used to provide signage on buildings, specifically when it is desirable to view the signage at night or from a distance. A common channel letter is constructed of an enclosure that outlines the desired shape, such as the shape of a letter or other alphanumeric character. This enclosure has a substantially flat rear surface for attachment to a building, and more importantly, is designed to house a light source such as an incandescent lamp, fluorescent lighting, or neon lighting. Finally, the front of the enclosure is open and adapted to receive a substantially translucent lens. The lens is commonly tinted and diffuses light emanating from the light source, at least to some extent, and thus provides an illuminated letter or other shape.
The light sources typically used in channel letters, such as fluorescent lighting or neon lighting, provide uniform and bright light typically devoid of hot spots; however, they have a variety of shortcomings. For example, such light sources often have a relatively short life, operate at high voltages, consume large amounts of energy, and/or are fragile. Additionally, with regard to neon lighting, it is both fragile and heavy, primarily due to its supporting infrastructure, making it expensive to package or ship. Moreover, it is extremely awkward to initially handle, install, and/or replace neon lighting.
The recent introduction of lightweight and breakage resistant point light sources, as exemplified by high-intensity light-emitting diodes (LEDs), have shown great promise to those interested in alternate light sources for various illumination devices. LEDs are not only lightweight and resilient, but, when compared to other light sources, have a long life, operate at low voltages, and consume small amounts of energy. Despite these benefits, the attributes of uniformity and brightness have proven to be difficult to produce in illumination devices incorporating LEDs. For example, the lenses often used in channel letters do not sufficiently diffuse the light emanating from each LED to eliminate hot spots. Additionally, LEDs are currently available in only a finite number of colors.
Accordingly, there remains a need in the art for an illumination device for simulating channel letters which satisfactorily addresses these problems.

Illumination device for simulating channel letters


It is provided a computer system comprising a management computer to be coupled to a management subject resource managed by the management computer, which includes at least one of a server apparatus, a storage apparatus or a network apparatus, and a display computer coupled to the management computer. The management computer includes a memory storing at least one workflow program including a work procedure, and a CPU configured to execute the at least one workflow program. The work procedure changes a configuration of the management subject resource, and acquires information from the management subject resource. The CPU executes prior verification processing of verifying an operation environment of the management subject resource to operate the work procedure included in the at least one workflow program before execution of the at least one workflow program, and displays an execution result of the prior verification processing on the display computer.

This invention relates to a computer system for executing a workflow program including work procedures, and more particularly, to a computer system for executing prior verification processing of verifying an operation environment of a management subject resource for an operation of the work procedure.
When a computer system including management subject resources (information technology (IT) resources) including at least one of a server, a network, or a storage is operated, work for changing a configuration of the management subject resource is necessary. The work for changing the configuration of the management subject resource includes work of installing software, and a setup work for software including setting of parameters. If a worker manually carries out the configuration change work, a work period may increase due to additional work caused by a work error due to unfamiliarity and inattentiveness of the worker. The following automated processing is prevailing. Specifically, in order to prevent the work period from extending, a management computer included in the computer system converts the manual configuration change work into an automatic operation flow such as a script in advance. Then, a small number of parameters are input to the management computer, and the management computer carries out an automated operation flow, thereby carrying out the configuration change work in a short period requiring almost no human intervention. The automated processing is realized by the management computer carrying out the automated flow based on the automated flow or job describing in which sequence and on which host various procedures of the automated processing such as execution commands, command lines, and scripts are executed when a predetermined condition is satisfied. It should be noted that the predetermined condition includes a case where a predetermined time has elapsed after the automated flow has been once carried out, a case where a schedule set in advance is reached, and a case where a predetermined event is generated.
Work for checking whether the automated flow is carried out on schedule, or is carried out without a problem is necessary for the management computer to surely carry out the automated flow without a problem.
As the background art of this technical field, there are known Japanese Patent Application Laid-open JP 2008-234276 A and International Patent Publication WO 2010/050524 A.
In Japanese Patent Application Laid-open JP 2008-234276 A, there is a description (refer to Abstract) that "If a scheduled operation of a job needs to be executed at time and date other than system time and date of a host, instructions of the time and date and a progress speed of time are issued from the local time and date and progress speed instruction part 102. The virtual time management part 103 calculates local time and date while using information on the instructed time and date and progress speed of time and system time and date 104 as inputs, and notifies the schedule management part 105 thereof. The schedule management part 105 reads the schedule definition 107, and requests a notification of a notification time list 109 listing start times of jobs which can be executed starting from the local time and date from the virtual time and date management part 103. If jobs which can be executed at the local time and date exist, the schedule management part 105 notifies the execution part 110 of the jobs, and controls the execution part 110 to read a job execution definition 108 from the job information storage part 10 and execute the job execution definition 108."
Moreover, in International Patent Publication WO 2010/050524 A, there is a description (refer to Abstract) that "This invention provides a computer system for managing a batch job. The computer system includes: a storage part for storing at least one job template; and an execution part for executing generation or update of a job net definition following a condition defined in the at least one job template, generation or update a job net, or discovery of a conflict of a job by using at least one attribute or a relationship in a set of data including at least one predetermined attribute of a configuration element and a relationship between the configuration element and another configuration element, the set of data being held in a repository and updatable by discovery of detecting information on a configuration element."

Computer system and program for prior verification of a workflow program


A multi-well diode is disclosed which can be used with other electronic components as an electronic neuron circuit. The multi-well diode has an S-shaped current-voltage characteristic curve at forward bias whereby it remains in a low conductance state until its threshold voltage is exceeded, then switches through an unstable region of its characteristic curve into a high conductance state. The multi-well diode remains in the high conductance state until its bias voltage and current drops below its holding condition, at which time it switches into a low conductance state. The multi-well diode can be used in a pulse-mode input circuit, thereby generating a pulse-mode output signal which can have a different amplitude and frequency than the input signal. Such pulse-mode input circuits can be either excitatory or inhibitory in operation. The multi-well diode can also be used in a direct current input circuit, having a pulse-mode output signal having a frequency which is related to the input signal's voltage or current. Such circuits emulate biological neurons in electrical characteristics. Such circuits also can have multiple inputs and outputs, and those inputs and outputs can be individually weighted (which is also similar to the operation of biological neurons). The electronic neuron circuits can alternatively be used with optical input or output signals rather than electrical input/output signals. Such circuits can be integrated into neural systems.

The architectural organization and signal processing functions of the human brain and nervous system are distinctly different and offer particular advantages over conventional, von Neumann digital electronic (computer) systems for a number of important applications, such as pattern recognition for speech and image analysis, and content addressable memory. The computational capabilites of these biological neural systems arise from the collective interaction of many neurons (signal processing elements) which are massively interconnected in a complex network. While the characteristic time associated with individual neuron operation is of the order of a millisecond, neural systems can outperform digital systems for certain applications, even though the characteristic operation time for current digital computer elements is of the order of nanoseconds. Current research in developing artificial neural systems is primarily directed along two lines: (1) simulating in software running on conventional digital computers the signal processing algorithms employed in neural systems, and (2) the development of custom hardware to implement the neural systems approach to signal processing. The first approach suffers from the problem of simulating the largely parallel, asynchronous operation of neural systems on a serial, synchronous computer. The second suffers from inefficiency in replicating the operation of the neuron and its interconnections.
While biological neural systems use a pulse-mode form of signal transmission, wherein information is communicated by varying the frequency of pulses, most approaches to neural hardware implementation utilize conventional digital circuit architecture (digital approach), wherein the information is transmitted and processed in binary form, or use conventional analog circuits (analog approach) such as operational amplifiers where the information is processed as an analog voltage or current. In a few instances the neuron's pulse-mode operation has been replicated, but only with relatively complicated circuits. However, in virtually all of these implementations, conventional transistor-based circuits have been employed so that the electronic equivalent of an individual barriers to the development of complex neural systems employing large numbers (thousands to millions) of electronic neurons, including limitations on integration due to power, area, interconnections, cost and reliability.
The more conventional approach, based on transistors such as silicon MOSFET types and employing standard circuit configurations, typically requires tens to hundreds of transistors plus additional devices per neuron so that the device area is correspondingly quite large. This translates into higher cost and increased complexity in design, and also limits the number of artificial neurons that can be integrated into a monolithically integrated system. This is important in artificial neural systems where the power of the neural approach is achieved by the simultaneous operation of large numbers of relatively slow individual neurons. The drawback in using GaAs-type semiconductor materials is that the technology for compound semiconductor device fabrication is not as well developed (and as inexpensive) as for silicon, although it is certainly adequately advanced so that commercial devices, e.g. semiconductor lasers, are readily available.
A unique approach to mimicking the pulse-mode operation of the neuron in developing a custom artificial electronic neuron is disclosed in Semiconductor Electronic Concepts for Neural Network Emulation, by D. D. Coon and A. G. U. Perera, Int. J. Electronics (1987), in which a p-i-n semiconductor diode is operated as a switching element in a relatively simple set of circuits. The operation in these circuits replicates a number of important characteristics of the biological neuron, including threshold behavior, temporal integration, memory, synaptic weighting, excitation and inhibition, summation over multiple inputs, and distribution to multiple outputs. However, a substantial barrier to its implementation is its requirement of extremely low temperatures (4.2.degree. K. or -269.degree. C.) for operation of the p-i-n diode. Such low temperatures preclude integration of the device with other conventional devices such as resistors and transistors, and add considerable cost and complexity to its utilization, making this approach impractical.
In the approach of Coon and Perera to mimic the pulse-mode operation of the biological neuron, a p-i-n semiconductor diode is operated as a switching element in a relatively simple set of circuits. The starting point of the switching mechanism is the fact that electrons are trapped at their parent donor atoms in the weakly n-type i-region of the device while in the low conductance mode. When the bias is raised sufficiently, electrons injected into the i-region from the cathode are accelerated and gain sufficient energy to produce impact ionization of trapped electrons from these parent donors. An avalanche multiplication of mobile electrons results, with each electron freed by this impact ionization process leaving behind a positively charged, immobile donor atom. The buildup of this positive charge in the i-region enhances the cathode electric field which ultimately accounts for the switch into a high conductance mode of device operation. The avalanche multiplication process is thus responsible for the device switching from the low to high conductance state.
While the above described mechanism is used by Coon and Perera to produce a p-i-n diode which can switch between low and high conductance current modes, a substantial barrier to its practical implementation is its requirement of extremely low temperatures (4.2.degree. K. or -269.degree. C.) for operation as described above. These very low temperatures are required to ensure that electrons are initially trapped at the donor atoms in the i-region, since the depth of the potential energy well (binding energy) for the electrons is only approximately 25 meV. To ensure binding of electrons at the donors, the mean thermal energy (which is approximately=kT--Boltzmann's constant times temperature) must be much less than the binding energy. For such shallow potential energy wells, switching operation is only possible at extremely low temperatures. At 4.2.degree. K. the mean thermal energy is kT=0.36 meV, but the mean thermal energy at room temperature is kT=26 meV. Such low temperatures (4.2.degree. K.) preclude integration of the device with other conventional devices such as resistors and transistors since this same effect (electron trapping) interferes with normal device operation. Hence, implementation of Coon and Perera's approach based on the low temperature operation of the p-i-n diode adds considerable cost and complexity to its utilization, thereby making this approach impractical.
By comparison, to overcome the low temperature limitations of Coon and Perera's p-i-n diode, a practical diode can be constructed having multiple quantum wells. To construct such a practical diode which can be used in a circuit to emulate a biological neuron, the depth of the quantum wells used to confine the electrons in the low conductance mode should be of the order of hundreds of meV (e.g., 300 meV), which is more than an order of magnitude larger than the binding energy of the donors in the i-regions of Coon and Perera's device. As a result, the operation of such a practical multi-quantum well injection mode diode (multi-well diode), can occur at much higher temperatures, including room temperature where the mean thermal energy is approximately kT=26 meV.
Another reference, Tunneling-assisted impact ionization for a superlattice, by Chuang and Hess, J. Appl. Phys. (Feb. 15, 1987), discloses an avalanche photodiode which consists of a multi-quantum well structure having several alternating layers of undoped, wide-gap semiconductor and heavily doped, n-type narrow-gap semiconductor layers, having about equal thicknesses. This multi-layer structure is sandwiched between an n+ cathode and a p+ anode which are formed with a narrow-gap semiconductor. Ohmic contacts made to the n+quantum wells are needed so the avalanche photodiode can replace electrons lost to impact ionization, to maintain the sensitivity of the device to incoming light.
The avalanche photodiode of Chuang and Hess is designed to detect light (photons), and to produce an output electrical signal (current pulse) proportional to the intensity of the incoming light or rate of arrival of photons. In contrast, a practical multi-well diode used to emulate operation of a biological neuron preferably is designed for use in the dark, and to produce an electrical output pulse, wherein its operation in various circuit configurations would be designed to produce a set of output pulses of essentially uniform height and shape, with the output information carried by the frequency of the pulses.
The avalanche photodiode of Chuang and Hess is operated in reverse bias. When the avalanche photodiode is operated at high reverse bias in the dark, minimal leakage current is desired which is constant in time and as small as possible. Since the applied bias is sufficient to produce the avalanching effect, the injection of electrons into the multi-quantum well region must be held to practically zero to prevent premature (in the absence of light) avalanching. To accomplish this the reverse bias mode is used. If the reverse leakage current is not small enough (even temporarily), then avalanching may occur even in the absence of light, producing an unwanted output electrical pulse. These undesirable electrical pulses thus constitute noise in the output signal which can mask the detection of true, optically generated signals.
A practical multi-well diode and the avalanche photodiode of Chuang and Hess are similar in construction, both employing multiple quantum wells and employing the avalanche effect. The avalanching effect in the Chuang and Hess photodiode, however, is not desirable except in the presence of light. While undesirable spontaneous avalanches in the absence of light cannot be completely eliminated in the avalanche photodiode of Chuang and Hess, in contrast, such spontaneous avalanches in the absence of light are the desired effect in a practical multi-well diode used to emulate operation of a biological neuron.
The avalanche photodiode of Chuang and Hess has certain similarities to that required in producing a practical multi-well diode which can be used to emulate a biological neuron. The avalanche photodiode and the multi-well diode, however, are constructed somewhat differently, are biased in a different fashion in their operation, and are employed for different purposes. The avalanche photodiode, as related above, requires ohmic contacts to its n+ quantum wells, whereas the practical multi-well diode does not require such contacts. In fact, such contacts would preclude the proper operation of the multi-well diode in switching to the high conductance mode, since such contacts would prevent the formation of positive space charge in the quantum wells.
The purpose of the avalanche photodiode of Chuang and Hess is to detect photons and produce an electrical output that is proportional to the rate of arrival of the photons. The purpose of a practical multi-well diode is to emulate the operation of a biological neuron in a mode of operation which is not dependent upon the multi-well diode directly receiving any given amount of optical energy.
The avalanche photodiode of Chuang and Hess is operated in reverse bias, whereas a practical multi-well diode is operated in forward bias to encourage electron injection from the cathode to initiate the avalanching effect. The operation of the multi-well diode is similar to the parasitic breakdown mode of operation of the avalanche photodiode.
A further reference, Mechanism of an S-shaped current-voltage characteristic in a Multilayer Isotypic GaAs-AlGaAs heterostructure, by Alferov et al., Sov. Phys. Semicond. (March 1987), discloses a multi-hetero-structure having an S-type current-voltage characteristic, which is associated with electron transport across alternating lightly doped, n-type AlGaAs barriers and heavily doped, n-type GaAs layers. A theoretical description of the negative resistance phenomena is given based on collective heating of electrons in the GaAs layers by electrons accelerated in the AlGaAs barriers. The weak temperature dependence observed in the current-voltage characteristics is explained wherein electron tunneling through the AlGaAs barriers is the dominant transport mechanism in the AlGaAs barrier layers. Experimental results are presented which show a weak negative differential resistance region having a threshold voltage of 6-7 volts, and a holding voltage of 5-6 volts.
The threshold and holding voltages of a practical multi-well diode used to emulate operation of a biological neuron are preferably much lower than the 6-7 volts and 5-6 volts disclosed in the above Alferov et al. reference. Biological neurons operate with voltage pulses in the range of several hundred millivolts, and a practical multi-well diode circuit which is to be interfaced with actual biological neurons would have to operate within the same voltage range. In addition, the lower the voltage required for operation, the lower the power required to supply such a practical multi-well diode circuit, and the closer such circuits could be packaged together to make integrated circuit packages having multiple practical multi-well diode circuits.

Multi-quantum well injection mode device


Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which are located in two memory pages in a virtual memory system, such that one of the pages does not permit execution of the instructions located therein, are identified and then executed under temporary permissions that permit execution of the identified instructions. In various embodiments, the temporary permissions may come from modified virtual memory page tables, temporary virtual memory page tables which allow for execution, and/or emulators which have root access. In embodiments, per-core virtual memory page tables may be provided to allow two cores of a computer processor to operate in accordance with different memory access permissions. in embodiments, a physical page permission table may be utilized to provide for maintenance and tracking of per-physical-page memory access permissions. Other embodiments may be described and claimed.

Many computer systems utilize virtual memory for security, stability and/or other purposes. In various virtual memory systems, a virtual machine monitor ("VMM") may control direct use of memory and/or computer processors in a computer system. The virtual machine monitor, which may be implemented in software and/or hardware, may allow guest software to run only in guest virtual machines, each containing their own guest address space defined by virtual memory addresses.
Thus, in many systems, a guest virtual machine may perform memory accesses using what appears, to the guest virtual machine, to be physical memory. These guest physical memory addresses may be mapped, in turn, to actual physical memory addresses through the use of page tables controlled by the virtual machine monitor. In some systems, these page tables may specify access permissions for memory pages (hereinafter, may simply referred to as "page"). Thus, a page table may define, for each page of virtual memory presented to a piece of guest software, whether the guest software may 1) execute instructions from that locations in that page, 2) read from locations in that page, and/or 3) write to locations in that page. In various systems, multiple page tables may he used, or switched to during execution, in order to allow particular accesses, as determined by the VMM. In various systems, additional page tables may be defined at the level of a guest virtual machine, where the page table may translate the guest virtual machines's virtual memory addresses to guest physical addresses. This may be separate, in some systems, from page tables used at the virtual machine monitor level, where the page tables may translate guest physical memory addresses to real physical memory addresses.
As an example, pages W and X may hold trusted data, while pages Y and Z may hold trusted code sections. To enable code in pages Y and Z to access data in pages W and X, but prevent code in other pages from accessing data in pages W and X, a page table may provide execute permission for pages Y and Z, and read/write permission for pages W and X.
However, in some scenarios, current page table utilization may introduce problems. In one scenario, an instruction may be large enough mall in memory locations that straddle two different pages. If a page table does not allow execution of instructions for one of the pages, processor that seeks to execute the instruction may find itself unable to proceed, despite the fact that the instruction is at least partially found in memory for which execution is allowed.
In another scenario, modification of page tables may provide for inefficiencies. For example, during execution, the VMM may determine that a processor, or a hardware thread executing on a processor, may be desired to execute instructions in accordance with different permissions. In some such scenarios, page table used by the processor may be modified, or the processor may be pointed to a different page table in order to utilize the different permissions. However, in a situation where only a single hardware thread requires different permissions, modification or switching of the page table for the processor can cause every other thread operating on the processor to utilize the new page table as well. This can cause inefficiencies, as the other hardware threads may not be appropriate to operate under the different permissions, and/or the other hardware threads may find themselves paused or otherwise waiting while the page table is modified.
In yet another scenario, support may not exist in a VMM or in hardware for a VMM-level page table that keeps track of physical-page-level permissions. For example, in some existing systems, permissions are only kept at a guest VM level, and may be controlled at that level by the VMM. This may cause inefficiencies, however, because the VMM may not have a facility for keeping track of permissions on a per-physical-page level, and for manipulating permissions at this level. This may prevent the VMM from exercising the same degree of control and protection as may be desired.


Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, facilitate cross-platform content muting. Methods include detecting a request from a user to remove, from a user interface, a media item that is provided by a first content source and presented on a first platform. One or more tags that represent the media item are determined. These tags, which indicate that the user removed the media item represented by the one or more tags from presentation on the first platform, are stored in a storage device. Subsequently, content provided by a second content source (different from the first content source) on a second platform (different from the first platform) is prevented from being presented. This content is prevented from being presented based on a tag representing the content matching the one or more tags stored in the storage device.

This specification relates to cross-platform content muting.
A user can access content (e.g., news, music, social media) on multiple different content platforms (e.g., search engines, social media platforms, news platforms, data aggregator platforms, etc.). The content on each content platform can be provided by a single content source or by multiple different content sources. In some instances, the same type of content (or even the same item of content) may be provided by different content sources on the same or different content platforms.

This patent is subject to a terminal disclaimer.


A toothbrush sterilizing container for holding and sterilizing the bristles and handle of a toothbrush includes a storage canister for receiving and holding the bristles of a toothbrush immersed in a sterilizing solution while the toothbrush handle extends through the open top end of the canister. A reservoir of sterilizing solution supplies fresh solution to the canister and a spout allows used solution to be drained from the canister. A lid has a slot for receiving the toothbrush handle and a supply of disinfectant in the lid maintains the handle in a sterile environment.

1. Field of the Invention
This invention relates to apparatus for storing and sanitizing toothbrushes between uses and, more particularly, to a holder useful to store toothbrush bristles in individual canisters containing sterilizing solution which may be flushed by removing used sterilizing solution and adding fresh sterilizing solution, and having a lid for storing the toothbrush handle in a sterile environment.
2. Description of the Prior Art
Toothbrushes are customarily stored when not in use in relatively unsanitary conditions. For example, after being used, toothbrushes are typically stored uncovered on shelves or in non-sanitized holders where they are exposed to any insects and germs or contaminants in the air. Toothbrushes stored in this manner are wet and possibly contain germs and food particles from the user's mouth, which are conditions that attract insects and promote the growth of bacteria and the spread of germs.
The problem of unsanitary storage of toothbrushes has been recognized, and toothbrush holders which perform a sanitizing function by exposing the bristles of the brush to a germicidal agent are known in the art. Examples of such prior art are the disclosures in U.S. Pat. Nos. 5,086,916 and 4,585,119. In spite of these prior attempts to remedy the problem of unsanitary storage, studies show that unsanitary storage of toothbrushes remains the norm. This suggests that the prior art attempts at solutions have been defective in some way or unacceptable to toothbrush users for some reason.
An object of this invention is to improve the apparatus of toothbrush sanitizing holders.
A further object of this invention is to a provide a toothbrush sanitizing holder which is both simple and user friendly in its method of operation so as to promote the use of toothbrush sanitizing holders among toothbrush users.
A further object of this invention is to a provide a toothbrush sanitizing holder which has individual storage chambers for preventing cross-contamination by direct contact between the individual toothbrushes.
A further object of this invention is to provide a sterilizing toothbrush holder having a flush feature to facilitate the removal of used sterilizing solution and the addition of fresh sterilizing solution.
A further object of the invention is to provide a toothbrush sanitizing holder having a replaceable reservoir of sterilizing solution of known and constant strength for repeatedly replenishing the solution in the storage chambers with solution of known and constant efficacy.
A further object of the invention is to provide a toothbrush sanitizing holder which stores both the bristles and handle of the toothbrush in sterile environments while preventing the evaporation and contamination of the sterilizing solution.

Toothbrush holder and sanitizer flush apparatus


An LED module 101 is provided with an LED chip 200 that includes a sub-mount substrate 210 made of Si and a semiconductor layer 220 laminated on the sub-mount substrate 210. The module also includes white resin 280 that does not transmit light from the semiconductor layer 220 and that covers at least part of a side of the sub-mount substrate 210, where the side is connected to the surface on which the semiconductor layer 220 is laminated. These arrangements enhance the brightness of the LED module 101.

FIG. 33 shows an example of conventional LED module (see Patent Document 1, for example). The LED module 900 shown in the figure includes an LED chip 902 mounted on a substrate 901. The LED chip 902 is surrounded by a reflector 905 in the form of a frame. The space surrounded by the reflector 905 is filled with sealing resin 906. The LED chip 902 includes a sub-mount substrate 903 made of Si and a semiconductor layer 904 laminated on the sub-mount substrate 903. The semiconductor layer 904 is electrically connected to the substrate 901 via the sub-mount substrate 903.
The sub-mount substrate 903 is made of Si, which may absorb light of e.g. blue emitted from the semiconductor layer 904. Thus, some of the light, emitted from the semiconductor layer 904 and traveling toward the sub-mount substrate 903, will be absorbed by the sub-mount substrate 903. Unfavorably, this hinders enhancement in brightness of the LED module 900.
Patent Document 1: JP-A-2004-119743


An endpoint determines whether a client is authorized to access data. A database stores separate authorizations of a permission model in a data table along with the data. Mapping templates of the endpoint convert a client request for data into a database query for client authorization and the requested data. In response to the query, the database returns to the endpoint the requested data as well as an indication of authorization from the data table. The mapping templates of the endpoint are then used to generate an appropriate response to the client. When the database response indicates the client is authorized, the endpoint can return the requested data to the client. When the database response indicates the client is not authorized, the endpoint can return an error. In some embodiments, the endpoint is an application programming interface (API) gateway that conforms to representational state transfer (REST) software architecture.

Access to cloud-based resources can require authentication and authorization. Authentication is the process of verifying the identity of the user. It can be based on user credentials, for example, through use of a unique identification in combination with a secret key password, or token, or cryptographically verifiable signature. In contrast, authorization is the process of verifying that the user has permission to access a specific resource or perform a specific function. For example, in response to a request from an authenticated user, a system can check with a permission model to determine if the user is authorized to access data within the database. Typically, the system employs a compute service (e.g., a server computer or serverless computing platform) to perform the authorization check. However, the use of a compute service for the authorization check may introduce undesirable latency for accessing data within the database.


An unburned carbon and other combustibles monitoring and control system for a fly ash producing fossil-fueled boiler, such as a pulverized coal fired boiler. An infrared imaging camera counts the moving hot particles entrained in the hot gases downstream of the furnace region of the boiler and provides a first signal representative of the number of hot particles in the hot gases over a predetermined period of time. A signal processor is connected to the infrared imaging camera for counting the hot particles for receiving the signal representative of the number of particles in the hot gases and providing a second signal representative of the mass flow of unburned carbon and other combustibles content of the fly ash produced by the boiler, the second signal being a function of the first signal. In the preferred embodiment, the apparatus includes at least one air/fuel control element for controlling the air/fuel ratio of the fossil-fueled boiler and a control system connected to the control element for receiving the second signal representative of the mass flow of unburned carbon and other combustibles content of the fly ash produced by the boiler and a predetermined set point for the mass flow of unburned carbon and other combustibles content of the fly ash produced by the boiler, the control system being operable to adjust the air/fuel control element in response to the second signal and the set point.

(1) Field of the Invention
The present invention relates generally to combustion monitoring systems and, more particularly, to an apparatus for precisely monitoring the unburned carbon and other combustibles, such as hydrogen and sulfur, content produced by a fossil-fueled boiler.
(2) Description of the Prior Art
Loss on Ignition (LOI) measurements are becoming increasingly important for utility coal fired plants for several reasons. For example, the low NOx burners that are being installed by a large percentage of coal fired plants produce higher LOI than the burners being replaced, even when the new burners are optimally tuned, and excessive amounts when the burners are poorly tuned. If the LOI of the fly ash increases, the plant must burn more coal to produce the same power (degrading plant heat rate). In addition, the higher carbon content fly ash may not be salable for use as building material, loadings on the bottom ash and fly ash systems will increase, and stack opacity may increase. Accordingly, it has become important to obtain reliable and timely mass flow of unburned carbon and other combustibles content (M.sub.UBC) measurements.
Most plants currently determine LOI by extracting an ash sample from the precipitator or baghouse hoppers or by isokinetic samples located, typically, downstream of the air heater and then use an ASTM procedure (% weight loss) to determine the unburned carbon and other combustibles content. Typically, this determination is performed once a day. The ASTM procedure takes about 4 hours to complete. Since real time information is not currently available, burner tuning and control to balance emissions (NOx) and efficiency (LOI) is very difficult at best.
There have been several attempts to provide an automatic LOI system on the market. These systems attempt to automatically extract an ash sample from the boiler and conduct the ASTM procedure on-line to produce a semi-real time indication. However, these systems have generally been unreliable and expensive due to mechanical problems associated with extracting hot and abrasive particles from a boiler. Specifically, the ash lines clog and corrode due to heat. Also, there is the question of whether a single measurement which, at best, produces only a single point value rather than a real time measurement is representative or not.
Thus, there remains a need for a new and improved M.sub.UBC, monitor which is operable to provide a real time indication of fly ash LOI.

Unburned carbon and other combustibles monitor


A fence pole clip, comprising two clip sections, the sections having portions configured to conformingly attach to two fence poles, and means swingably interconnecting the sections between the end portions, whereby the sections can be relatively swung to allow positioning of the two clip sections and portions adjacent one of the poles.

Fences installed around swimming pools commonly employ flexible mesh retained to spaced poles, as displayed for example in U.S. Pat. No. 6,893,007B2. Such poles may be upwardly removed from lower end anchorage in underground receptacles, for storage, the mesh fencing being wrapped about the poles. However, when clips are attached to adjacent poles, wrapping of fencing about such adjacent poles is difficult and produces a very bulky and clumsy package. There is need for a simple effective way to eliminate or reduce bulkiness in fence wrapped pole packages. Also there is need for an improved clip that will facilitate fence wrapping about a single pole, and in the very effective manner as discussed herein.


A MEMs actuator device and method of forming includes arrays of actuator elements. Each actuator element has a moveable top plate and a bottom plate. The top plate includes a central membrane member and a cantilever spring for movement of the central membrane member. The bottom plate consists of two RF signal lines extending under the central membrane member. A MEMs electrostatic actuator device includes a CMOS wafer, a MEMs wafer, and a ball bond assembly. Interconnections are made from a ball bond to an associated through-silicon-via (TSV) that extends through the MEMS wafer. A RF signal path includes a ball bond electrically connected through a TSV and to a horizontal feed bar and from the first horizontal feed bar vertically into each column of the array. A metal bond ring extends between the CMOS wafer and the MEMS wafer. An RF grounding loop is completed from a ground shield overlying the array to the metal bond ring, a TSV and to a ball bond.

Relevant devices to which this disclosure finds application include MEMS electrostatic actuators (also known as capacitive actuators) which have a first electrode (bottom plate) fixed to a substrate and a second electrode (top plate) supported in elevated position above the substrate for selective controllable movement toward and away from the first electrode. A voltage applied between the electrodes creates an attractive force, drawing the electrodes together. Applying an opposing voltage and/or a mechanical spring action creates a restorative force, driving the electrodes apart. A thin layer of dielectric material applied over the first electrode prevents shorting.
Additional background is described in Gupta et al. application Ser. No. 13/614,936 "MEMS ELECTROSTATIC ACTUATOR" filed Sep. 13, 2013, the entirety of which is incorporated by reference herein.

MEMS electrostatic actuator device for RF varactor applications


An apparatus for the representation of an area on the three-dimensional surface of a patient's body, with a control device which provides three-dimensional coordinates of at least one area to be represented on the surface of the patient's body, wherein the area pre-sets a desired intersection area of a radiation area on the surface of the patient's body, characterized in that at least one projection device featuring a laser is provided, by which the desired intersection area can be projected to the three-dimensional surface of the patient's body on the basis of the provided coordinates, while at least one laser beam generated by the laser can be guided along the contour of the desired intersection area sufficiently rapidly, so that the impression of a closed contour around the desired intersection area results.

The present invention is related to an apparatus and a method for the representation of an area on the surface of a patient's body, and relates to the field of radiation therapy with ionising radiation for treating cancer. In this, usually plural rays from different directions are directed to the body to be treated, so that they intersect in an isocentre. Here acts the summed-up radiation dose of the different ionising rays directed to the isocentre. In this way, the adverse effect to the surrounding tissue is minimised.
As the first step of a radiation therapy, a computer tomography (CT) mapping of the patient positioned and fixed on a positioning aid, like a treatment table, is established. Based on this mapping, a 3D-model of the patient is made and the tumour to be treated is localised and an irradiation plan is set up. This comprises contouring the target volumes as well as the calculation of the dose for the irradiation, and in this the determination of the number and location of the radiation areas of the irradiation machine in particular, so that the tumour is irradiated as desired.
During the execution of this irradiation planning, the patient is no more on the positioning aid. Furthermore, a plurality of irradiation dates (usually up to 30 fractions) takes usually place in the frame of such a radiation therapy. Therefore, a transfer of the radiation areas calculated on the basis of the established 3D-model of the patient to the real patient is repeatedly necessary. This step is also called "simulation". In particular, the patient must be reproducibly laid on the treatment table such as he/she lay when the CT mapping was established.
In order to do this, it is known to perform a positioning of the patient by means of 3D bone radiography ("Cone Beam"), wherein bones of the patient constitute the reference points for an alignment of the patient, for instance. The advantage of this method is a high accuracy. In addition, no reference marks or the like have to be affixed on the patient's skin. The disadvantage of this method is a high x-ray radiation dose for the patient, because the x-ray positioning is required before each treatment fraction. Thus, in the frame of a radiation therapy, this may usually take place up to 30 times. This radiation dose applied to the body in a great volume can induce a new cancer again in the long term, in younger patients in particular.
According to a known alternative method, the patient can be positioned on the positioning aid by means of three reference points on its skin, which are formed by suitable retro reflectors, for instance. Such a method is known from DE 44 18 216 A1, the entire contents of which is incorporated herein, for instance. After performing the irradiation planning, the intersection points of the irradiation areas with the surface of the skin which are necessary for the desired irradiation are calculated. The intersection points are then at hand in the form of a 3D coordinate table. After newly positioning the patient on the basis of the three reference marks, the coordinates from the table can then be represented on the body surface of the patient one after the other with a laser system. The approach to the coordinates can be controlled by an operator through an infrared remote control for instance. The respective points represented by the laser are then manually drawn in on the skin of the patient, with a pencil for instance. The desired intersection area for the irradiation results by connecting the points.
Such a method is known from DE 44 21 315 A1 or DE 195 24 951 A1, the entire contents of which is incorporated herein by reference, for instance. The laser device used for this consists of five motor movable lasers in particular, wherein two lasers adjustable in the height direct a horizontal line along the treatment table to the patient, at the right and at the left side from the treatment table, respectively. The remaining three lasers are mounted in a plate which is situated above the treatment table, a CT table for instance. In this, one laser is movable transversely to the table's long side direction and directs a line along the table to the patient. The two remaining lasers in the plate are coupled with each other and direct a common line to the patient, transversely to the table's alongside. By the coupling of two lasers, even such coordinates can be represented on the skin of the patient which otherwise would be shaded below the transverse diameter of the patient. With the described system, it is possible to approach almost arbitrary coordinates on the skin of the patient, wherein one coordinate is always indicated by a cross of two laser lines. Such a laser system is offered by the applicant under the name "Dorado CT4".
However, the described method is relatively time-consuming and thus expensive, because usage time in the CT-room is very expensive. In addition to this, manual drawing in the points is not always sufficiently accurate, depending on the adiposity of the patient in particular. In particular, skin marks can shift. Therefore, marks of the intersection areas on the skin are performed only partially in practice. Correspondingly, the correct irradiation of the patient is not always secured in a sufficiently accurate way.
The simulation is not only an assignment of the irradiation plan to the patient, but also an important element in the context of the quality assurance. The irradiation plan is checked for its plausibility for the last time before the therapy and it is determined whether the ray areas can be reproducibly adjusted to the desired planned target volume.
Based on the clarified state of the art, the present invention is based on the objective to provide an apparatus and a method of the kind indicated in the beginning, by which the simulation process of the radiation therapy is possible in a simple, more rapid and precise way and without danger for the health of the patient at the same time.

Apparatus and method for the representation of an area on the surface of a patient's body


Valves having an inner assembly comprising: a base plate spaced apart from a top plate to define therebetween an open side, the base plate defining an outlet; an outer assembly comprising solid side walls and being movable relative to the inner assembly between open and closed positions, an upper portion of the solid side walls seal with the top plate only when the outer assembly is in the closed position, a lower portion of the solid side walls seal with the base plate only when the outer assembly is in the closed position, wherein the open position allows flow through the valve via the open side portion and the outlet of the outer assembly; and an actuator mounted to the inner assembly and connected to the outer assembly to move the outer assembly between the open and closed positions in response to electrical control signals.

Helicopter carried dump-buckets are well known for use in fighting forest fires. These buckets, at their simplest, may comprise a rigid or flexible reservoir or body for holding a volume of water, a sling to suspend the reservoir from a helicopter, a valve, and an actuator which is controlled from inside the helicopter to operate the valve to release the water from the reservoir over the fire.
In some prior art buckets, the valve may consist of a simple flapper valve located on a bottom interior surface of the reservoir and operated by a remotely controlled actuator, for example. A flapper valve typically includes a base plate having an outlet therein, a flat flapper member disposed over-top of the base plate so as to block the outlet, and a hinge connected between an edge of the flapper member and the base plate to hingeably connect the flapper member to the base plate permitting the flapper member to alternately block and expose the outlet.
In other prior art buckets, the valve may consist of a butterfly valve, which typically includes a longitudinally extending axle having first and second coplanar plates extending laterally therefrom. The butterfly valve may be connected to a bottom portion of the bucket and located in an opening therein. When closed, the first plate may seal against an interior surface of the bucket while the second plate may seal against an exterior surface of the bucket. The valve may be opened by rotating the first and second plates about the axle and may be fully opened by rotating the plates to a position perpendicular to their closed position.
There are problems associated with each of these valves. With the flapper vales, there are significant forces imparted to the valve by a full head of water that tend to resist the hinging of the flapper member and thereby resists the opening of the flapper valve, which requires a powerful motor to actuate the flapper, resulting in increased weight and power consumption. High electrical power demands in a helicopter is undesirable since the onboard equipment need to undergo rigorous testing and certification, and the associated cabling needed for such high demands increases the weight of the equipment substantially. Furthermore, the operation of the flapper valve may create turbulent flow, causing the water to disperse laterally as it is dumped. In fire-fighting, lateral dispersal may be undesirable as the water may be more susceptible to evaporation before reaching the ground and also because some of the water may overshoot the desired target. With the butterfly valves, they tend to cause lateral dispersal when operated as a metering valve and may be difficult to seal as one plate may be located inside the bucket and the other plate may be located outside the bucket.
To address some of the shortcomings of flapper valves and butterfly valves, U.S. Pat. No. 6,192,990 to Brooke discloses a multi-dump metering valve having an outer assembly and an inner assembly in which the outer assembly is moveable between open and closed positions, and the outer assembly has a reduced surface area on those surfaces which are disposed normally to a direction of movement. The outer assembly is thereby adapted to be less affected by hydrostatic and hydrodynamic forces directed so as to oppose its movement. U.S. Pat. No. 6,192,990 is in its entirety incorporated herein by reference. While the subject matter disclosed in Brooke is an improvement over the prior art, nevertheless, it would be desirable to even further reduce the surface area on those surfaces which are disposed normally to a direction of movement so as to be even less affected by hydrostatic and hydrodynamic forces directed so as to oppose its movement. With an even further reduced surface area, the force required to actuate the valve would be considerably less with the advantage that the actuating hardware may be reduced to achieve considerable weight reduction and that motors with a reduced power demand may be used with the advantage of a reduced electric power demand. In addition, it would be desirable for the valve apparatus to be more easily serviceable so that the seals in the apparatus are more easily replaced when worn or damaged.


Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correction stages to correct a soft error using the fetched unit of information and the associated error correcting codes. By extending the pipeline, soft error correction does not stall the pipeline and hence system performance is improved in the face of soft errors from an error correcting memory subsystem.

1. Field of the Invention
The present invention relates generally to pipelined processor operation in the presence of soft errors in memory and in particular relates to methods and structure for correcting soft errors found in information (program instructions and/or data) read from an attached memory subsystem.
2. Related Patents
This application claims the benefit of U.S. provisional patent application Ser. No. 60/535,005 filed on Jan. 8, 2004 which is hereby incorporated by reference.
3. Discussion of Related Art
It is common practice in present day computer processor architectures to utilize pipelined architectures for improving performance. In particular, present-day processors utilize pipelined architectures in accessing memory subsystems. Programmed instructions and data are fetched and/or read from a memory in a pipelined fashion so as to optimize processor performance in fetching and executing instructions.
In general, "pipelined architecture" refers to an architecture of, for example, a computing processor in which various stages of the instruction and/or data memory read operations are substantially independently operable and thus may be overlapped with other processing stages within the processor to decode instructions, determine addresses of operands, reading operand data from memory and execute the instructions. The particular stages of a pipeline and the degree of independence of the pipeline stages are matters of design choice for the processor designer. By so overlapping various stages of processor instruction fetching and execution and related data reading and decoding, the processor may most effectively utilize available bandwidth from the memory subsystem. In other words, a next memory read or fetch operation may be initiated a while later stages of a previous fetch or read continue to completion. The overlapped operations of the various stages of memory access allow a new memory access as often as every clock period of the memory subsystem. Such pipelined architectures are well known to those of ordinary skill in the processor and memory architecture arts.
Memory subsystems coupled to such pipelined processors are rapidly evolving as measured by both capacity and performance. As memory speeds and densities increase, so to does the susceptibility of such memories to "soft errors". A "soft error", in general, is one that may be corrected by applying error detection and correction techniques and circuits. Such a soft error may be manifested as, for example, a flipped bit. In other words, a bit value previously stored in memory as a zero value is flipped to a one value, or vice versa, or otherwise erroneously read back. Such errors are most commonly caused by radiation of various types and frequencies that interfere with the persistent storage of data in the memory semiconductor circuits.
Processors may encounter such soft errors during instruction fetch or data read operations. When soft errors are encountered in a pipelined processor architecture, the overlapped sequencing of the pipeline stages mat be stopped or disrupted (i.e., "stalled"). The pipeline stage may then need to be emptied and re-started to achieve the desired synchronization and overlap of stages of the memory interface pipeline. This stalling of the pipeline and the associated restarting thereof negatively impacts overall system performance.
However, the frequency of such soft errors is extremely rare as compared to the frequency of memory access due to the typical, error-free, pipelined instruction fetch and execution processes. Though somewhat infrequent, it remains an ongoing problem to reduce the frequency of encountering such soft errors or to correct them when detected.
One current solution to soft error problems in a memory subsystem is to add an error correcting code to all stored data and associated error detection and correction logic. Often such logic is embedded within the memory controller device used by the processor to interface with the memory subsystem. The error code is stored along with data written to the memory. When data is read from memory, the associated error code is also read and may be used to detect the presence of an error and to correct the error. For example, one common error detecting and correcting code utilizes a six bit Hamming code associated with each of stored 32 bit value in the memory subsystem. Such a six bit Hamming code is capable of detecting multiple bit errors in the corresponding 32 bit stored value and is further capable of correcting any single bit error in the corresponding 32 bit stored value. During a write operation in such an enhanced, error correcting memory subsystem, the processor writes a new 32 bit value to the memory subsystem and the error correction logic associated with the memory subsystem generates the corresponding six bit Hamming code such that a 38 bit value is then stored in the identified memory subsystem location (32 bit value supplied by the processor and six bit hamming code generated by the error correction features of the memory subsystem). During a read operation, the memory subsystem uses the retrieved 38 bits to produce a corrected 32 bit value even in the presence of any single bit error since the previous write operation.
However, such "in-line" correction typically slows the memory subsystem read performance for all memory accesses. In general, such error correcting techniques and logic add one or more "wait states" to every read or fetch operation. In view of the relative infrequency of such soft errors, imposing such a wait state penalty on every read or fetch operation is problematic and slows overall operation of the corresponding system.
Another presently known technique for reducing the frequency of soft errors is to provide a so called scrubbing engine. A scrubbing engine is an element operable as a background process that periodically reads each location in the memory, checks for errors using error correcting and detecting codes and techniques, and corrects any detected errors by writing the corrected value back to the memory location from which the read erroneous value was read. Such a scrubbing engine may impose one or more wait state delays on the memory subsystem performance but only when but the scrubbing engine detects an error and attempts to write a corrected value back to the memory subsystem. While the scrubbing engine architecture can improve performance over an in-line error correcting memory subsystem design, the scrubbing engine architecture does not eliminate all possible soft errors but merely reduces the probability or frequency of such soft errors arising.
Yet another present solution for reducing system performance impact due to soft errors in a memory subsystem suggests that an in-line error correcting memory subsystem architecture may overlap the correction error detection in correction logic with presentation of the fetched data to the requesting processor. If it is later determined that the value returned from the memory subsystem to the requesting processor included a correctable error, the memory subsystem may in some manner interrupt the processor to cause invocation of appropriate error handling procedures within the processor. For example, the processor may be interrupted and provided with a corrected memory data value. Processors adapted for such a memory architecture may receive the interrupt signal and restart execution of the instruction corresponding to the erroneously fetched information. While such a process eliminates the wait state penalty of the above discussed in-line error correcting memory architecture, the re-execution or restart sequencing, per se, is complicated and can impose significant design tradeoffs within the processor pipeline architecture. Specifically, the processor pipeline design is complicated due to the lateness of the error signal relative to the processor's fetching and execution of the earlier, erroneous instruction or data.
All presently known solutions for reducing or eliminating soft errors in a memory subsystem incur certain performance penalties or complexities in a processor pipeline design. In-line error detection and correction architectures may add wait states to all memory accesses and thereby impose a significant cost on all memory read operations (regardless of whether an error is detected or corrected). Imposing such wait state delays on all memory accesses significantly diminishes overall system performance despite the relative infrequency of memory soft errors.
Failure to correct detected soft errors in-line (i.e., in real time as they are fetched or read) may impose other performance obstacles in that the pipelined fetch/read operations may be stalled when an error is detected and/or corrected thereby requiring restart of the pipeline architecture. Such pipeline architecture stalls and restarts cause other performance problems in the overall system and add design complexities. A processor pipeline stall and restart generally entails emptying the pipeline of multiple instruction and data read operations in various stages and then restarting the fetch/read operations so purged from the pipeline.
It is evident from the above discussion that a need exists for improved memory subsystem and processor pipeline architectures that permit detection and correction of memory soft errors with minimal impact on processor and system performance.

Methods and structure for error correction in a processor pipeline


A low-pressure mercury discharge lamp having emission maxima in three spectral regions, provided with a gastight, radiation-transmitting discharge vessel with a gas filling comprising mercury and rare gas. A luminescent layer comprises at least a first luminescent material with an emission maximum in the 590-630 nm region and a second luminescent material with an emission maximum in the 520-565 nm region. The first luminescent material contains a compound defined by the formula EQU M1.sub.x M2.sub.(1-x-y)BO.sub.3 : Eu.sup.+3.sub.y,. in which M1 is selected from the group consisting of Sc, In and Lu, and M2 is selected from the group consisting of Sc, Y, La, Gd, Ga, In and Lu, in which M1 differs from M2, in which x.gtoreq.0 and 0.01.ltoreq.y.ltoreq.0.2, and in which the compound has the calcite lattice structure.

The invention relates to a low-pressure mercury discharge lamp having emission maxima in three spectral regions, provided with a gastight, radiation-transmitting discharge vessel with a gas filling comprising mercury and rare gas and provided with a luminescent layer which comprises at least a first luminescent material with an emission maximum in the 590-630 nm region and a second luminescent material with an emission maximum in the 520-565 nm region.
Low-pressure mercury discharge lamps with emission maxima in three spectral regions are known from U.S. Pat. No. 4,176,294 and Netherlands Patent 164,697. To achieve these maxima in three spectral regions, the low-pressure mercury discharge lamps comprise a first (red-)luminescing material with an emission maximum in the 590-630 nm region and a second (green-)luminescing material with an emission maximum in the 520-565 nm region. The required emission in the third spectral region, i.e. the 430-490 nm region, is supplied in many cases by a third (blue-)luminescing material. The visible radiation emitted by the mercury vapour discharge itself, however, also offers a contribution (i.e. the emission of the 436 nm mercury line) in this spectral region, so that the presence of a blue-luminescing material in the luminescent layer is not always necessary. The low-pressure mercury discharge lamps emit white light at a given colour temperature, i.e. the colour point (x, y in the CIE chromaticity diagram) of the emitted radiation is situated on or adjacent the Planckian locus. In addition to the requirements to be imposed on the luminescent layer as regards the properties mentioned above relating to the colour temperature of the light radiated by the low-pressure mercury discharge lamp the luminescent layer also has to meet particular requirements regarding colour rendering and luminous efficacy.
A red-luminescing material which is frequently used in practice is yttrium oxide activated by trivalent europium (YOX). This material complies satisfactorily with the requirements listed above. Low-pressure mercury discharge lamps comprising YOX in their luminescent layer are widely used for general lighting and have the advantage that they have a good general colour rendering (colour rendering index R(a,8) of at least 80). A disadvantage, however, is that this good general colour rendering is not necessary in every application of a low-pressure mercury discharge lamp while this good general colour rendering is generally achieved at the cost of the luminous efficacy of the lamp.

Low-pressure mercury discharge lamp having specific luminescent composition


A module (10) for validating deposited media items is described. The module comprises: illuminating means (24) for illuminating a deposited media item (20); directing means (34) for directing illuminations from the illuminating means (24) to an examination area (22); optical detecting means (26) for detecting emissions from the deposited media item (20) at the examination area (22), where the emissions are caused by the illuminations; and processing means (32) for processing the detected emissions. The processing means (32) is operable in either a first mode, in which the deposited media type is known, or in a second mode, in which the deposited media type is not known. The illuminating means (24) includes ultra-violet radiation, infra-red radiation, and discrete primary colors.

The present invention relates to a module for validating media items. In particular, the invention relates to a module for validating different types of deposited valuable media items, for example banknotes, tickets, cheques, and such like. The invention also relates to a self-service terminal, such as an automated teller machine (ATM), including such a media validating module.
Many ATMs include one or more depository modules for receiving and validating valuable media items. For example, an ATM may include:
(i.) a cheque depository module that receives and validates cheques input by a user, and
(ii.) a note depository module that receives and validates banknotes input by a user.
Each depository module includes various elements, for example: a slot for receiving a media item, an imaging device for imaging an inserted media item, sensors for detecting the position of an inserted media item, a processing engine for validating an inserted media item, an interface for coupling the module to a self-service terminal to allow transfer of data, and such like.
Providing a depository module for each type of media item to be validated is both expensive and an inefficient use of space because similar elements are included in each depository module. However, different types of media require different validation tests to be performed. These different tests involve different illumination sources, different image resolutions, and such like.

Module for validating deposited media items