A method for sculpting art including preparing an artistic line drawing of interconnected lines having varying widths. The artistic line drawing is converted to a format suitable for computer numeric controls for guiding cutting means. The sculpture is cut out of a piece of material using cutting means suitable for defining holes around the artistic line drawing. The sculpture and mounting means are finished. The mounting means provides a mechanism for spacing the sculpture from and attaching the sculpture to a structure. The mounting means are substantially invisible to a viewer when positioned on the structure. The sculpture having a combination of varying weight lines which appear to be drawn by a felt tipped pen.

1. Technical Field
The present disclosure relates to methods for creating sculptures. More particularly, the present disclosure relates to methods for creating sculptures using devices being directed by computer numeric controls and the sculptures themselves.
2. Background of Related Art
Traditional sculptures fabricated by hand require great skill and large quantities of time to produce a work of art. Modern sculpturing processes have benefited from the reliability and accuracy provided by current industrial processes which can greatly reduce the time required to produce a similar work of art. Sculptures can now be shaped using computer numeric controls to cut, etch or carve precision forms in materials such as glass, wood composites, stone, plastic, and metal. Technological improvements patented in this area range from increasing the automation of the processes for cutting materials to cutting three dimensional signs of wood.
In U.S. Pat. No. 5,584,016 to Varghese et al., an improved cutting device control system is described. The improved control system analyzes drawings and uses devices such as algorithms and constraints in the software program to create lower level computer instructions to fully automate the cutting process, Specific steps in the process include (a) loading a pattern from a known format into a computer memory location, wherein the pattern includes one or more draw primitives; (b) applying a set of predetermined rules to the draw primitives to determine a cutting path along the one or more draw primitives without operator intervention; and (c) determining cutting instruction from the cutting path. Varghese et al. however, is limited by its focus on automating a cutting process and fails to address a creative process for manually tailoring the artistic drawing in the computer to ensure the artistic intent for the piece to touch and flow smoothly is adequately represented by the computerized image.
In U.S. Pat. No. 5,701,251 to Yoshimura, a blank cutting process is described using sequential and continuous high speed cutting around the perimeter of adjacently positioned blanks. This advantageously reduces the cost of mass producing blanks. Yoshimura, however, is limited in the effectiveness of its application to specific angular optimal blank geometries. Thus, the methods of Yoshimura cannot be readily applied to artistic creations having irregular lines that frequently have defined unconnected ends.
A method for rapidly producing a contoured part is taught in U.S. Pat. No. 5,872,714 to Shaikh et al., wherein (a) a computer graphic representation of a part is produced; (b) sectioning the graphic model into graphic members configured as blocks or slabs; (c) carving a solid member for each graphic member that is proportional to and envelopes the graphic member by carving out two or more sides of the solid graphic members to duplicate the corresponding graphic member; and (d) securing the carved solid members together to replicate the graphic model as a usable unitary part. This multiple step process produces a mold suitable for casting complex part configurations. Shaikh et al., however, is overly complex and the process focuses on reproducing three dimensional parts and it is not conducive to replicating ornate sculptures of artistically line drawings having interrelated arcuate and straight lines.
In U.S. patent application No. 2002/0092389A1 to Feldman et al. a method is described for accurately cutting pieces from a closely packed marker containing tangency points and common lines so as to minimize cutting time and the use of the raw material. Feldman et al. is limited, however, by its focus on automating a cutting process and fails to address a creative process for manually tailoring the artistic drawing in the computer to ensure the artistic intent for the piece to touch and flow smoothly is adequately represented in a computerized image.
In U.S. patent application No. 2002/0095236A1 to Dundorf, methods and apparatus are disclosed for carving signs having three dimensional surfaces. Dundorf uses a computer-aided design system to produce a three dimensional graphic model of the signage work having three-dimensional surfaces to be carved in a sign board. Material is removed using a carving tool under the computer-aided machining system to leave a three dimensional carved pattern corresponding to the three dimensional model of the signage work having surface properties and features characteristic of a hand-crafted gold-leafed wood carved signs. Dundorf however, does not teach a process suitable for taking an artistic line drawing and transitioning the line drawing to a computer aided drawing, using the computer ensure the touch and flow of the artistic intent for the piece is smoothly and adequately repesented in the computerized image, and defining the artistic line in the medium by cutting through holes around the artistic lines.
A continuing need exists for a method for creating a sculpture of an artistic line drawing using computer numeric controlled cutting devices to shape the sculpture.


Disclosed herein is a moisture-reactive composition having a moisture-reactive polysiloxane having a main chain and one or more side chains, wherein the main chain and/or the one or more side chains has a group represented by the formula: —MXmYn; and wherein M is selected from the group consisting of a multivalent metal atom, B, and P═O; X is a hydrogen atom, a substituted or nonsubstituted alkyl, alkenyl or alkoxy group; Y is a substituted or nonsubstituted alkoxy, siloxy, carboxyl, or diketolate group; m is from 1 to 3; and n is from 0 to 2.

An organic EL element utilizes electroluminescence of an organic material and is formed by laminating an organic charge transport layer and an organic luminescent layer between an anode and a cathode. Much attention has been paid to organic EL elements as high-intensity luminescence by low voltage direct current driving may be obtained therewith. Moreover, organic EL elements can be formed out of solids making them useful in flexible displays.
Luminescence properties such as luminescence brightness, luminescence efficiency, and luminescence uniformity of an organic EL element are often deteriorated after being driven for long periods of time. Causes of such deterioration include: oxidation of the electrodes due to penetration of oxygen into the organic EL element; oxidation decomposition of the organic material caused by heat generated during driving of the element; and oxidation of the electrodes and modification of the organic material caused by moisture in the air which penetrates into the element. Luminescent properties may also be deteriorated by peeling at an interface of the organic EL element. Peeling may be caused by oxygen and moisture, or by heat which generates stress due to differences in thermal expansion coefficients of the components of the element.
In order to reduce deterioration of luminescent properties, many technologies for sealing an organic EL element have been investigated in order to prevent the element from being contacted with oxygen and moisture. For example, Japanese Unexamined Patent Publication (Kokai) No. 9-148066 discloses a method comprising covering a pixel area formed by arranging an organic EL element as shown in FIG. 1. The element comprises transparent electrode 3, organic functional layer 4, metal cathode electrode 5 on substrate 1, with sealing cap 2 having a water-absorbing agent 6 affixed to the inner wall thereof. The interior of the element is filled with nitrogen gas, and sealing cap 2 is fixed to substrate 1 with adhesive 7. For another example, Japanese Unexamined Patent Publication (Kokai) No. 7-169567 discloses a method comprising using an oxygen-absorbing agent in place of the water-absorbing agent.
Various substances have been examined as water-absorbing agents. In particular, alkaline earth metal oxides such as barium oxide (BaO) and calcium oxide (CaO) have been widely investigated because the oxides differ from such water-absorbing agents that physically adsorb water as silica gel and zeolite in that the oxides can surely catch water molecules by chemical reactions, and because the oxides do not release the water molecules at high temperature. These oxides, however, are in the form of particles which must be affixed in a recess inside of the organic EL element which undesirably adds to the thickness of the element. Alkaline earth metal oxides can be applied to a so-called bottom emission type display apparatus from which display light is taken out of the substrate 1 side. However, alkaline earth metal oxides are not suitable for use in so-called top emission type display apparatus from which display light is taken out of the sealing cap 2 side opposite to the substrate 1. This is because they are opaque and thereby hinder emission of the display light. If oxides are to be used, they must be arranged so as not to cover the pixel area, and a new arrangement site must be provided.
Several proposals have been made in order to apply a water-absorbing agent to a top emission type display apparatus. For example, transparent, water absorbing polymers such as poly(vinyl alcohol) and nylon may be used, although these polymers physically adsorb water, which is not satisfactory as explained above. Japanese Unexamined Patent Publication (Kokai) No. 2001-357973 describes an organic EL element having a top emission structure and an arrangement of a particulate water-absorbing agent to such a degree that light transmission is not hindered. Japanese Unexamined Patent Publication (Kokai) No. 2002-56970 describes use of a plastic substrate in which a water-absorbing agent having a particle size smaller than the luminescence wavelength of the organic EL element. However, because inorganic particles are utilized as water-absorbing agents in both references, the water-absorbing agents are hardly arranged, and the primary particles thereof are hardly dispersed. As a result, light is scattered which undesirably lowers light transmission.
Japanese Unexamined Patent Publication (Kokai) No. 2003-142256 discloses use of a water-trapping film that absorbs little visible light and can be formed by coating a specific metal compound with a solvent. However, when this water-trapping film is applied to a flexible substrate, problems arise because the film is formed out of a low molecular weight compound, and thus is not flexible. Furthermore, in order to protect the element from both moisture and oxygen, respective trapping agents must be used. As a result, the problem that the arrangement sites of these agents are still more restricted arises.

Moisture-reactive composition and organic electroluminescent element having same


The present invention provides a vertical batch type wafer cleaning apparatus comprising a wafer bearing apparatus in a cleaning tank. The wafer bearing apparatus comprises three parallel upstanding racks and a plurality of wafer shelves arranged up and down between the three racks. Three deflections are uniformly formed at edge of each of the wafer shelves. The three racks have two cover bodies at two ends thereof to connect two rotators. The wafer bearing apparatus is driven to rotate by synchronous rotation of the two rotators. A flow distributor is provided in the cleaning tank to connect an output pipe of the cleaning solution supply tank so that cleaning solution can be distributed and transferred to between the wafer shelves. Two filter pipes are provided between the cleaning tank and the cleaning solution supply tank to let cleaning solution be used in recirculating way. The present invention has advantages of enhanced cleaning efficiency and reduced cost.

The present invention relates to a wafer cleaning apparatus and, more particularly, to a vertical batch type wafer cleaning apparatus, which can effectively increase wafer cleaning efficiency.
In the fabrication process of large-scale integrated circuits, wafer cleaning technique and cleanliness are important factors affecting yield and device quality. The object of wafer cleaning is to remove contaminants from surfaces of wafers and to remove particles and organic and inorganic impurities. Therefore, before silicon wafers enter a high. temperature oven for performing a thermal process such as diffusion or oxidation, and before or after chemical vapor deposition is performed, wafers must undergo a cleaning process to let fabricated semiconductor electronic devices conform to designed electrical characteristics.
In the prior art, a plurality of wafers are placed on a boat and dipped into a cleaning tank along with the boat so that the wafers can be cleaned using flow of injected chemical cleaning solution. However, in this cleaning method, flow of cleaning solution will be restricted between wafers so that cleaning solution and surfaces of the wafers cannot effectively interact, letting wafer cleaning effect be bad. In the prior art, a rocking or shaking means is exploited to enhance flow of cleaning solution, but the wafer cleaning effect is still not good enough. Moreover, breakage of wafers may occur because of too large rocking or shaking force. In consideration of the above problems, the present invention aims to propose a wafer cleaning apparatus, which can enhance wafer cleaning efficiency.
The primary object of the present invention is to provide a vertical batch type wafer cleaning apparatus, which can effectively increase velocity of cleaning solution flowing by surfaces of wafers to enhance wafer cleaning efficiency.
Another object of the present invention is to propose a vertical batch type wafer cleaning apparatus to let there be flow of cleaning solution between every two wafers so that each wafer can be cleaned by the cleaning solution. Still another object of the present invention is to propose a vertical batch type wafer cleaning apparatus, in which cleaning solution can be used in recirculating way, thereby reducing the cost.
According to the present invention, a wafer bearing apparatus and a flow distributor are provided in a cleaning tank. The wafer bearing apparatus is formed by arranging a plurality of wafer shelves up and down between three parallel upstanding racks. Three deflections are uniformly formed at the edge of each of the wafer shelves. The three racks have two cover bodies at two ends thereof to connect two rotators, respectively. The flow distributor is connected to a cleaning solution supply tank via an output pipe so that cleaning solution can be distributed and transferred to between the wafer shelves. Two filter pipes are further provided between the cleaning tank and the cleaning solution supply tank.

Vertical batch type wafer cleaning apparatus


An image retrieving apparatus having a reading unit for reading the image of an original, a comparing unit for comparing the image data of the original outputted from the reading unit with a plurality of image data stored in a storage medium, and a retrieving unit for outputting one of the image data generally coincident with the image data of the original from the storage medium, and the discrimination information for discriminating the image data generally coincident, in accordance with the comparison result by the comparing unit.

1. Field of the Invention
The present invention relates to an image retrieving apparatus for retrieving an image stored in a storage medium.
2. Related Background Art
In retrieving an image stored in a storage medium of a conventional electronic filing system, a file name or key word assigned when storing the image, is designated to display it on a display screen. A user visually confirms whether the retrieved and displayed image is a desired one. If it is a desired one, the image is printed out on a recording sheet, and if not another image is retrieved.
Such a conventional retrieving method is associated with very complicated works. If a user forgets the file name or key word of an image because it is impossible to reduce the number of image files to be checked, a very large number of image files are required to be read by trial and error.
In one method of eliminating such inconveniences, as disclosed in U.S. patent Ser. No. 038,239, images stored in a storage medium are reduced in size and stored as index images in the storage medium. A plurality of such index images are read at a time and displayed. A user designates an index image to read a desired image file.
With this method, however, if there are too many index images, efficient retrieval is not possible. If the number of index images to be displayed is to be reduced, a key word or the like is required to be entered for the retrieval of index images. Therefore, if a user forgets a key word, it is impossible to reduce the number of index images to be checked.
In another method of dealing with such inconveniences, as disclosed in U.S. patent Ser. Nos. 477,470, 478,250, 601,445 and the like, each image file is assigned an optional image index instead of a conventional character index (key word). In retrieving an image file, an image index is designated to obtain a desired image file.
With this method, an image index is required to be assigned to each image file in advance, in order to allow the retrieval using image indices. If such an image index is inadvertently not assigned to some image files, efficient retrieval is impossible.


A two stroke cycle internal combustion engine (10) is provided which has a one-piece cylinder housing (14) removably secured to a valve drive housing (12) at a top section thereof and a crank housing (16) at a bottom section. The overall combination of the valve drive housing (12), the cylinder housing (14) and the crank housing (16) are formed in a substantially symmetrical manner about a vertical axis line (18). An intake valve member (30) is positioned in a top section of cylinder housing (14) with an exhaust port (62) located at the bottom of a piston (44) travel within a combustion chamber (54). The valve member (30) opens on a downward stroke of the piston (44) which feeds compressed air into chamber (54) and forces spent gases through the exhaust port (62).

FIELD OF THE INVENTION
This invention relates to a two stroke cycle engine. In particular, this invention relates to a two stroke cycle internal combustion engine. Still further, this invention directs itself to a two stroke cycle engine which includes a unitarily formed cylinder housing releasably secured to a unitarily formed valve drive housing. Still further, this invention relates to an overall two cycle engine where the main components include a valve drive housing, a cylinder housing and a crank housing which are substantially symmetrical about a vertically directed axis. More in particular, this invention pertains to a two stroke cycle engine where a valve drive housing is threadedly coupled to a unitarily formed cylinder housing. Still further, this invention pertains to a two cycle engine which is modularly constructed for ease of construction and removal of the contained elements making up the engine components. Further, this invention pertains to a two cycle engine where the intake valve is controlled by an electromagnetic system including an electromagnetic device acting in magnetic cooperation with a permanent magnet attached to the stem of the intake valve. Further, this invention directs itself to a two cycle engine where a fluid jacket may be threadedly secured to a cylinder housing for ease of construction. More in particular, this invention relates to a two cycle engine whereby the cooperation of a valve drive housing in threaded securement to a cylinder housing forms a symmetrical air plenum for insertion of air into the combustion chamber of the two cycle engine. Further, this invention relates to a two cycle engine whereby a fluid jacket in threaded cooperation with the cylinder housing forms a coolant chamber at least partially surrounding the cylinder housing. This invention further pertains to an internal combustion engine which is easily adapted to a diesel engine application using a glow plug in place of a spark plug. Further, this invention relates to an engine system which through a modular design permits greater electronic manipulation to allow wide ranges of parameter changes associated with fuel intake, firing times, valve open/close duration times allowing varied power and torque combinations.


A quantum decoder receives a syndrome from a quantum measurement circuit and performs various decoding operations for processing-efficient fault detection. The decoding operations include generating a decoding graph from the syndrome and growing a cluster around each one of multiple check nodes in the graph that correspond to a non-trivial value in the syndrome. Each cluster includes the check node corresponding to the non-trivial value and a set of neighboring nodes positioned within a distance of d edge-lengths from the check node. Following cluster growth, the decoder determines if, for each cluster, there exists a solution set internal to the cluster that fully explains the non-trivial syndrome bit for the cluster. If so, the decoder identifies and returns at least one solution set that fully explains the set of non-trivial bits in the syndrome.

The scalability of decoders for quantum error correction is an ongoing challenge in generating practical quantum computing devices. Hundreds or thousands of high-quality qubits with a very low error rate (e.g., 10−10 or lower) may be needed to implement quantum algorithms with industrial applications. Using current or near-term quantum technologies, these specifications cannot be met without using thousands of high-quality qubits that are each individually encoded in thousands of physical qubits such that there may exist millions of qubits running each computation of the quantum computer. Obtaining error rates currently required by industrial applications requires correcting, at regular intervals, errors that accumulate over these millions of qubits. Detecting and correcting these errors entails processing a massive amount of data, leading to significant challenges in bandwidth and hardware resource allocation.
Classical Low Density Parity Check (LDPC) codes are ubiquitously used for error identification and correction in modern communication devices, as these codes achieve a high rate of information storage, a large minimum distance allowing for greater error correction capability, and are equipped with a linear time decoder. LDPC codes could bring similar advantages to quantum computing; however, common LDPC decoders such as those using the belief propagation (BP) decoder achieve poor performance in the quantum setting due to the presence of a short cycle in the Tanner graph of quantum LDPC codes. Alternative strategies, such as the flip min set decoder, have been proposed for specific families of quantum LDPC codes; however, these alternative strategies are not universally available to use with all LDPC codes.


A closed-loop MIMO system includes a receiver for forming a new predefined set by using elements of a previous predefined set, selecting a certain matrix of the new predefined set, and feeding back an index of the matrix, if the number of transmit antennas increases, and a transmitter for performing signal transmission by multiplying the matrix of the feedback index to a transmission signal. Although the number of transmit antennas increases, candidate matrices can be simply obtained by using candidate matrices of a previous set. Moreover, to by proposing a reference for selecting an optimal solution with a small amount of calculation, burden on a system can be considerably reduced.

1. Field of the Invention
The present invention relates to a MIMO (Multiple Input Multiple Output) system of mobile communication and, more particularly to a method for constructing and transmitting feedback information in a closed-loop MIMO system.
2. Description of the Related Art
The MIMO system is a technique for increasing capacity and high data rate transmission.
A closed-loop MIMO system feeding back channel information to a transmitter can acquire larger capacity and a lower bit error rate.
In spite of the advantages of the closed-loop scheme, system designers are reluctant to apply the closed-loop scheme for a physical system because the closed-loop scheme requires the very large feedback data and thus encroaches on one capacity of uplink and downlink.
The reason why the capacity of the feedback data is so large is because the feedback data is a matrix including complex numbers as elements and a dimension of the matrix is the product of the number of transmit antennas and the number of receive antennas.
In order to solve such a problem, a receiver of a related art closed-loop MIMO system feeds back only an index of an optimum solution.
FIG. 1 illustrates the construction of a general closed-loop MIMO system.
As shown in FIG. 1, a receiver 200 of the closed-loop MIMO system obtains Coptimal by using a matrix (H) indicating a wireless channel environment, compares a distance between Coptimal and elements of a predetermined matrix set (referred to as 'predefined set', hereinafter), and selects the closest element as a matrix with optimal performance (referred to as 'optimal solution', hereinafter).
Equation (1) shown below is an equation of an SVD (Singular Value Decomposition), one of methods used for obtaining Coptimal, in which 'U' means Coptimal.HHH=UΣUH  (1)
After the optimal solution is obtained, the receiver 200 feeds back information on the optimal solution to a transmitter 100. Because the transmitter 100 and the receiver 200 share information on the predefined set, the receiver 200 feeds back only the index of the optimal solution.
In FIG. 1, {C1, C2, C3, . . . , CL} defines the predefined set and each element of the predefined set is a matrix. Guides of the matrices {C1, C2, C3, . . . , CL} are orthonormality and have a maximum minimum distance. The orthonormality means CmHCm=I and the maximum minimum distance means that the predefined set should be formed with matrices whose minimum distance is the maximum. In order to determine elements of the predefined set, the receiver 200 searches every matrix and then determines matrices whose minimum distance becomes the maximum as candidate matrices of the predefined set.
However, the afore-mentioned related art has the following problems.
That is, first, in order to form the predefined set only with two guides, numerous orthogonal matrices are to be randomly selected as many as an arbitrary number and matrices whose minimum distance is the maximum are to be picked up, for which, thus, the arbitrary number must be considerably large. Namely, the related art method for forming the predefined set is ineffective because it lacks a structure and regularities.
Second, the processes are to be repeatedly performed whenever the number of transmit antennas is changed, making it difficult to immediately cope with a change in the system.
Third, elements of the predefined set are determined by searching every matrix one by one, which is very ineffective.

Signal transmission method of closed-loop MIMO system


A composite structure for electronic components, having a base substrate with a flat side provided with a depression, and having a cover layer which is disposed on the flat side structured by the depression, and the depression being covered to form a hollow structure. The depression in the base substrate is created prior to the deposition of the cover layer and has a clear width measured parallel to the flat side that is less than one-half of its clear depth measured before the cover layer is applied. The vapor phase deposited cover layer is formed from a material which has a sufficiently high surface tension to promote three-dimensional growth of the vapor phase deposited layer.

This invention relates to a composite structure for electronic components comprising a base substrate formed with a depression on one flat side and a cover layer disposed on the flat side structured by the depression to cover the depression and form a hollow structure. The invention further relates to a method for producing a composite structure of the foregoing type in which a flat side of a base substrate is provided with a depression, and the flat side of the base substrate structured by the depression is then covered with a cover layer to form a hollow structure.
In microelectronics, electronic components are known which have various functions and applications, such as integrated circuits, vacuum diodes or flat-panel displays for flat video screens. They have hollow structures, some of them open and some of them fully enclosed. The hollow structures are generally made by first creating depressions in one flat side of a base substrate, especially by selective etching, and then covering them with a layer which is applied to the flat side of the base substrate which has thus been structured by the etching, and then enclosed at least in the direction of the structured flat side, in a manner forming the hollow structures.
In the aforementioned hollow electronic component structures, the application of the layer covering the depressions is very expensive and also problematic, because in applications in the microelectronic field, even the slightest impurities can result in the rejection of the component and therefore must be avoided.
Furthermore, some components of this kind, especially flat panel displays, are difficult and expensive to produce, since the structuring operations required to manufacture them are difficult to carry out, and since it is also necessary that the structuring of the flat side of the base substrate, and hence the topography of the components, be extremely precise.

Composite structure and method for the production thereof


Some embodiments of the present disclosure are directed to an antenna system for an airplane. The antenna system including an antenna system enclosure and a desiccant enclosure within the antenna system enclosure and having desiccant material positioned between an outside air pipe and an inside air pipe, the inside air pipe extending from the desiccant enclosure to open to an interior air volume of at least one component of the antenna system within the antenna system enclosure, the outside air pipe extending from the desiccant enclosure to ambient air outside the antenna system enclosure, and the desiccant material is configured to absorb moisture in the ambient air flowing from the outside air pipe to the inside air pipe through the desiccant enclosure while air pressure is being equalized from outside to inside the antenna system enclosure.

Airborne RF antenna devices typically have internal air volumes. For example, air cavities typically exists within the interior volumes of the antenna aperture, waveguides, and other elements. It is generally not possible to environmentally seal the interior air volumes of airborne RF antenna devices because of the substantial ambient air pressure changes occurring between ground and cruise altitudes that are repeated during the lifespan of an aircraft. Attempts to seal the interior air volume would usually result in bursting of the seals or other surfaces thereby allowing moisture to enter in an uncontrolled manner. Therefore, typically an array type airborne RF antenna device is vented to the ambient air.
Such venting facilitates pressure equalization between the internal air volumes and ambient air. However, the cycling of air pressure over repeated flights functions to pump moisture into the internal air volumes where it accumulates to the detriment of components of the RF antenna device. For example, water corrodes metal components of the RF antenna. Water can also substantially degrade performance of high frequency antenna components. For example, performance of RF waveguides can be severely degraded if water is located at certain locations on the RF waveguides and antenna aperture components, such as on the power dividers where RF current densities can be the highest. This can be particularly true in Ku and, in particular, Ka band frequency RF antenna devices.
Therefore, there exists a need to prevent condensation and/or reduce moisture in the air in the internal air volumes of RF antenna devices of this type.

Apparatuses for reducing air condensation in components of satcom antenna subsystem


An electron-emitting device comprises: (A) a first electrode; (B) an electron-emitting film which is provided on the first electrode; and (C) a second electrode which is provided above the electron-emitting film across a distance H from the electron-emitting film, and includes an opening which exposes at least a part of the electron-emitting film, wherein an area of the second electrode is at least four times larger than an area of the opening, and a ratio H/W of the distance H to a width W of the opening is not less than 0.07 but not more than 0.6.

1. Field of the Invention
The present invention relates to an electron-emitting device, an electron source, an image display apparatus and a television apparatus.
2. Description of the Related Art
FE (field emission) type electron-emitting devices are getting attention as devices which emits an electron from a metal surface, by applying an intense electric field of 106V/cm or greater to the metal.
FIG. 15 is an exemplary diagram of a Spindt-type electron-emitting device as an example of the FE-type electron emitting device. In FIG. 15, the Spindt-type electron-emitting device includes a substrate 111, a gate electrode 112, a cathode electrode 113, an insulating layer 114 and an emitter 115. In the Spindt-type electron-emitting device, electric field concentration occurs on the tip of the sharpened emitter 115 so as to emit an electron, upon application of a positive voltage higher than that of the emitter 115 to the gate electrode.
As other structures, Patent document 1 (Japanese Patent Application Laid-Open (JP-A) No. HEI9-221309) discloses an electron-emitting device including a carbon fiber (e.g. a carbon nano-tube, etc.) used for the emitter. Patent document 2 (JP-A No. 2000-353467) discloses an electron-emitting device including diamond or diamond-like carbon (DLC). FIG. 16 is a diagram showing an electron-emitting device for performing electron emission, upon giving of an appropriate positive level of potential to an electrode 212 facing an emitter electrode 211.
Patent documents 3 and 4 disclose an electron-emitting device wherein a carbon nano-tube is formed in a small hole. FIG. 17 is a diagram showing the example wherein a carbon nano-tube 315 is formed in the small hole (Patent document 4).
[Patent document 1] JP-A No. HEI9-221309 (U.S. Pat. No. 5,773,834 A)
[Patent document 2] JP-A No. 2000-353467
[Patent document 3] JP-A No. HEI10-12124
[Patent document 4] JP-A No. 2000-86216

Electron-emitting device, electron source, image display apparatus and television apparatus


A support provides a relatively stable support surface for a first disk having an angled surface and a center hole. A second disk having an angled surface and a center portion is inserted into the center hole of the first disk, and a tensioning band encircles a portion of the first disk and the second disk to fix their relative position to one another by friction between the disks. An optical element such as a mirror or lens is mounted to the second disk. By angularly rotating the first and second disks relative to one another, the relative angular alignment of the optical element can be adjusted and fixed by use of the tensioning band.

Generally, as illustrated in FIGS. 7A and 7B, cells 735 such as mirrors 712 mounted in a dish or on a plate with clips 730, are supported on a structural support 731 with a set of spaced, opposing screws 732 located on concentric rings 733, 734 on the base of the cell. When adjusted, some of the screws push the cell from the structural support and the other screws pull the cell to the structural support thereby changing the angle of the cell relative to the support. Adjustments in the mirror's angle relative to the structural support are achieved by balancing the extensions of the opposing screws. Sometimes, as illustrated in FIGS. 8A and 8B, a spike or ball 836 is surrounded with a single ring 833 of screws 832 extending through the structural support 831 and cell 835. Adjustments are made by balancing the tensions of these screws 832 against the compression of the spike or ball 836. Other times, as illustrated in FIGS. 9A and 9B, a single ring 933 of screws 932 which extend through springs 937 between the cell 935 and the structural support 931 will provide the adjustment since the tensions on the screws 932 will balance the compressions on the springs 937.
All of the above techniques possess the same disadvantages. By using screws and elastic elements such as springs to provide the necessary adjustments, the above designs can release their adjustments over time as a result of the affects of temperature variation and vibration.

Method and system for mounting optical elements


The present invention is to provide a sheet conveying apparatus capable of reliably detecting a full-load state of a storage section for storing sheets discharged from a sheet conveyance path when an abnormality such as multi feed is detected, a sheet feed apparatus is provided with a multi feed sheet storage section disposed below a common conveyance path to store multi-fed sheets with multi feed detected, and a flap member rotating between a first rotation position for supporting a sheet in the common conveyance path to be able to convey to the downstream side in a conveyance direction, and a second rotation position for guiding to the multi feed sheet storage section, and determines that the multi feed sheet storage section is in a full-load state in detecting that the flap member does not return to the first rotation position.

Generally, there is a known image forming system provided with an image forming apparatus such as a copier and printer, and a sheet feed apparatus arranged parallel with the image forming apparatus. The sheet feed apparatus includes paper feed cassettes for storing a plurality of sheets to be able to supply sheets to the image forming apparatus, as a sheet conveying apparatus.
In Patent Document 1 is proposed an image forming apparatus provided with an escape tray in an upper portion of a sheet feed unit. A sheet with an abnormality such as multi feed and skew detected by an abnormality detecting sensor is conveyed to an escape conveyance path side branched off from a common conveyance path, and is discharged to the escape tray.
In Patent Document 2 is described an image forming system provided with a paper feed apparatus with a purge box provided below a sheet conveyance path for conveying sheets to an image forming apparatus. In the case where an abnormality such as a jam is detected during sheet conveyance, since a sheet remaining on the sheet conveyance path is discharged to the purge box by controlling a purge guide, the user is capable of omitting operation for removing from the paper feed apparatus.


A method for on-line channeling of milk based on predicted coagulation properties where the method comprises sampling raw milk from a milk line between a milking station and a collection point, performing spectral analysis of one or more of optical transmission, optical reflectance, scatter and fluorescence on the raw milk sample, predicting at least one coagulation parameter on-line based on the spectral analysis, and channeling milk from the milking station on-line to one of a plurality of destinations based on the at least one coagulation parameter.

The coagulation properties of milk supplied by the dairies are of great importance to the cheese industry. Milk with favorable coagulation characteristics, e.g. short coagulation time and high curd firmness, may produce higher cheese yield with a desirable composition as compared to milk with less favorable properties.
In the article "Review of systems for monitoring curd setting during cheesemaking" by O'Callaghan et al., published in the Journal of Dairy Technology, Vol. 55, No. 2, May 2002, pp. 65-74, which is incorporated herein by reference in its entirety, known methods for detecting coagulation properties of milk are described. The methods described are based on physiochemical changes that occur in milk during rennet coagulation. Typically, rennet is added to milk samples extracted from a general collection tank in a dairy and coagulation properties of the coagulating milk are measured.
In the article "A comparison of the methods for determination of the rennet coagulation properties of milk", by KÜBARSEPP et al, published in Acta Agriculturae Scand Section A, 2005; Vol. 55: pp. 145-148, which is incorporated by reference in its entirety, there is described two known technologies for measuring coagulation properties: the formagraph and the optigraph.
According the article by KÜBARSEPP et al., the formagraph measures tiny forces exerted by a pendulum when samples of coagulating milk are exposed to linear oscillations. The recorded measurements are firmness and time. Firmness is typically defined as a combination of viscosity and elastic characteristics of the coagulating milk.
According the article by KÜBARSEPP et al., the optigraph is based on measuring Near InfraRed (NIR) signal attenuation emitted from the coagulating milk as the coagulation process develops.
Both methods require adding enzyme prior to performing the measurement and are therefore destructive. The analysis duration of these methods may be longer than the milking session and are therefore are implemented for evaluation of the milk at a dairy in the general tank.
International Patent Application Publication WO03040704 entitled "Spectroscopic Fluid Analyzer" which is incorporated herein by reference in its entirety, describes an NIR spectroscopy fluid analyzing system for determining concentrations of component parts of fluid. The system uses a series of Light Emitting Diodes (LEDs) for illuminating a sample of fluid and photo-detectors for measuring the transmission absorbance through the sample and the reflectance or scattering from the sample for the wavelength range of each LED. The concentration of component parts of the sample is expressed in the form of a polynomial which is a function of the measured transmitted and/or reflected intensities, and of empirical coefficients, which are extracted by prior statistical analysis on measured intensities obtained from a large number of test samples having known concentrations of the component. Also described in WO03040704 is a sample chamber capable of being used to perform optical absorption measurements on a flowing sample of fluid.

System and method for on-line analysis and sorting of milk coagulation properties

S.A.E. Afikim Milking System Agricultural Cooperative Ltd


One aspect of the invention is a coverage metric to identify that part of a state space which is covered by properties verified by model checking. In each property, a signal is identified (or a proposition on several signals) as the observed signal in that property. The coverage metric measures the coverage of a set of properties with respect to the observed signal. The coverage metric identifies the reachable states in which the value of the observed signal determines the validity of the verified properties. Then a model checking algorithm can be used to check the correctness condition on the observed signal in these xe2x80x9ccoveredxe2x80x9d states to prove or disprove the property.

The present invention is related to computer-aided design (CAD), and more particularly to property coverage in formal verification of integrated circuits.
One of the problems with modem logic design is the verification that the design actually works in the way it was intended to work. Undetected errors in the logic design may cause costly redesigns, or even loss of consumer confidence in the product if the product has been released on the market.
Model checking is one method of verifying designs. Model checking is a formal verification (FV) technology for property verification. A property specifies the desired values of particular circuit signals at various points in time in relation to other signals. Given a model of a design and some desired properties, a model checker like Symbolic Model Verifier (SMV) verifies whether the model satisfies all the desired properties under all possible input sequences. The properties are specified in a property specification language such as Computation Tree Logic (CTL). Although model checking is an exhaustive FV technique, a bug can escape the model checking effort if the properties specified by the user do not check for the erroneous behavior caused by the bug. Such erroneous behavior usually occurs in some obscure corner case that has been missed by the user. This is quite common when the specification has to be manually decomposed into a set of smaller, more tractable properties that are verifiable by the model checker. To reduce bug escapes, the user needs to continuously strengthen existing properties and specify new properties, without knowing if the additional verification is insufficient or redundant.
Logic simulation is another method of verifying designs. In existing simulation-based verification methodologies, coverage metrics are used to improve the quality of a test suite and estimate the progress of the verification task. For example, a common coverage metric for simulation is xe2x80x9ccode coveragexe2x80x9d, which measures the fraction of hardware description language (xe2x80x9cHDLxe2x80x9d) statements exercised during simulation. An xe2x80x9cobservability based code coveragexe2x80x9d enhances this metric by factoring potential error propagation to observability points. xe2x80x9cTransition coveragexe2x80x9d is another metric for control state machines. Such coverage metrics are effective in reducing bug escapes by pointing out coverage holes in the test suite.
However, the existing coverage metrics for simulation do not apply directly to model checking, e.g., a naive interpretation of the code coverage or transition coverage metric on a model checking task gives a meaningless coverage of 100% for every property. Logic simulation is dynamic and its coverage is driven by input simulation vectors, whereas model checking is static without any notion of circuit execution. Unlike logic simulation, the likelihood of having a bug escape detection in a model checking effort depends solely on the quality of the properties verified. Therefore, what is needed is a coverage metric that estimates the xe2x80x9ccompletenessxe2x80x9d (i.e. the quality) of a set of properties against which the design has been verified.
For example, consider the CTL formula for count, a modulo-5 counter, with stall and reset as external inputs:
AG[((-stallxcex9-resetxcex9(count=C)xcex9(C less than 5))xe2x86x92AX(count=C+1)]
This formula specifies that if the stall and reset signals are deasserted and the counter value is less than 5, then the counter increments by 1 in the next step. The model checker explores the entire reachable state space to verify the property. However, in reality, it ascertains the correctness of the condition on count (that it increments correctly) only in those states that are immediate successors of states satisfying the antecedent. The actual checking of the correctness condition on the model state space is thus constrained by the CTL formula. Thus, this property cannot be said to provide 100% coverage. This example illustrates the need to define a coverage measure for formally verified properties.
For this and other reasons, there is a need for the present invention.
One aspect of the present invention is a method of measuring coverage of a formal verification property. The method includes receiving a model of a logic design wherein the model has a plurality of states. The method also includes receiving a property verified for the model of the logic design and receiving one or more observed signals for the property. The method further includes providing a set of covered states in which checking a value of the one or more observed signals is sufficient to determine the validity of the verified property.
A further aspect of the present invention is an alternate method of measuring coverage of a formal verification property. The method includes receiving a model of a logic design wherein the model has a plurality of states. The method also includes receiving a property verified for the model of the logic design and receiving one or more observed signals for the property. The method further includes providing a set of covered states for the observed signal of the property, wherein the set of covered states comprise each one of the states in which changing a value of the observed signal in the state causes the property to fail.

Property coverage in formal verification


There is disclosed a printed wiring board comprising: an electrically insulating flexible layer which has on one of its opposite sides a protrusion which forms a corresponding recess on the other side of the flexible layer; an electrically conducting layer formed on the protrusion; and a wire formed on the flexible layer, connected to the conducting layer, and extending in a direction. The conducting layer has a shape long in the direction of extension of the wire.

1. Field of the Invention
The invention relates to a printed wiring board for transmitting drive signals, and an electric device using such a printed wiring board.
2. Description of Related Art
Unexamined Japanese Utility Model Application No. 4-33560 discloses an inkjet printer having an inkjet head unit including an actuator unit in the form of an inkjet printhead comprising a plurality of piezoelectric patches for pressurizing ink in a plurality of pressure chambers in the printhead, and a flexible printed wiring board or a flexible printed circuit board (FPC) comprising a base turn and a conductor pattern comprising a plurality of conductors each consisting of a conducting layer or terminal and a wire, formed on a side of the base film. Each terminal is disposed to be opposed to the piezoelectric patches. On the side of the base film which is opposed to the printhead, there is further formed an insulating film to cover the conductor pattern, except places where the terminals are disposed and therearound. Each of the terminals has a portion protruding toward the piezoelectric patches, and this protrusion is pressed against an outermost one of the piezoelectric patches so that each of the conducting layers of the FPC and the outermost piezoelectric element are electrically connected.
In the conventional arrangement disclosed in the above-mentioned publication, the insulating film is not formed around the terminals, causing a problem that the conducting layers tend to separate from the base film upon formation of the protrusions in the terminals of the conducting layers on the FPC by pressing, due to the stress imposed on a bonding surface between the base film and the terminals.

Printed wiring board and electric device using the same


A special tabbed pattern is integrated into a series of forms. The forms may be cookie cutters adapted to cut baked dough or other material set to desired density to provide a series of panels corresponding to the cutters. Alternatively, the forms may be molds, e.g, adapted to receive melted chocolate which is allowed to cool and set to form a series of panels corresponding to the molds. The panels are adapted to be joined together to form a decorative structure. The tabs are sized and positioned to provide a dovetail joint along each edge of the structure. The protruding tabs or ends are of a slightly smaller dimension than the notches that they fit inside of to provide a secure fit. This self-interlocking design allows each individual piece of the structure to be fitted together, one at a time, while maintaining an acceptable degree of stability throughout the assembly process.

Decorative structures, particularly edible decorative structures, such as gingerbread houses, are well-known. Such structures are routinely made and displayed, especially for specially occasions, such as birthdays or Christmas. Children, in particular, enjoy participating in the decorating process. Historically, assembly of a gingerbread house has been an awkward and time-consuming task. Icing, in particular icings having an egg white base, such as royal icing, have traditionally been used to bond the individual panels of a structure together. The icing method is difficult to implement due to the amount of drying time required. Gingerbread house builders typically need a great degree of patience and may rely upon some sort of makeshift propping system to help stabilize the structure while the icing is setting. The icing assembly method can therefore be a frustrating experience for both adults and children. The frustration often limits enjoyment of the finished structure and may even prevent completion of the structure.
The need therefore remains for systems and methods for creating a decorative structure that are time and cost-efficient. The need further remains for systems and methods that permit ease of assembly while maintaining an acceptable degree of stability throughout the assembly process.

Systems and methods for building an interlocking decorative house


A system for keeping the imperfectly machined surfaces of bearings apart at rest. The system includes a first bearing surface which moves facing a second bearing surface, the first surface having a distribution of discrete diamond-like carbon (DLC) pads deposited upon an adhesion layer. The DLC pads are at a height which is approximately the height of the roughness or imperfections of the surfaces. The pads are distributed over the surface at approximately three pads to forty pads or more per square inch. The pads keep the bearing surfaces from coming in contact. Also disclosed is a hydrodynamic bearing having a thrust plate having hydrodynamic grooves and DLC pads on a thrust surface, and a rotor member having an end facing the thrust plate, and a ball and socket bearing having DLC pads deposited on either the socket surface or ball surface.

The present invention relates to the field of mass storage devices. More particularly, this invention relates to improving the tribological performance of bearings in a disc drive.
One of the key components of any computer system is a place to store data. Computer systems have many different places where data can be stored. One common place for storing massive amounts of data in a computer system is on a disc drive. The most basic parts of a disc drive are a disc that is rotated, an actuator that moves a transducer to various locations over the disc, and electrical circuitry that is used to write and read data to and from the disc. The disc drive also includes circuitry for encoding data so that it can be successfully retrieved and written to the disc surface. A microprocessor controls most of the operations of the disc drive as well as passing the data back to the requesting computer and taking data from a requesting computer for storing to the disc.
The transducer is typically housed within a small ceramic block. The small ceramic block, also referred to as a slider, passes over the disc in a transducing relationship with the disc. The transducer can be used to read information representing data from the disc or write information representing data to the disc. When the disc is operating the disc is usually spinning at relatively high revolutions per minute (RPM). These days common rotational speeds are up to 10,000 RPM. Higher rotational speeds are contemplated for the future. The small ceramic block, or slider, is usually aerodynamically designed so that it flies over the disc. The best performance of the disc drive results when the ceramic bock is flown as closely to the surface of the disc as possible. Today""s small ceramic block or slider is designed to fly on a very thin layer of gas or air. In operation, the distance between the slider and the disc is very small. The fly height is the thickness of the air lubrication film or the distance between the disc surface and the transducing head. Currently, fly heights are about 0.5-1.0 micro inches. In some disc drives, the slider passes through a layer of lubricant rather than flying over the surface of the disc.
Information representative of data is stored on the surface of the memory disc. Disc drive systems read and write information stored on tracks on memory discs. Transducers, in the form of read/write heads attached to the sliders, located on both sides of the memory disc, read and write information on the memory discs when the transducers are accurately positioned over one of the designated tracks on the surface of the memory disc. The transducer is also said to be moved to a target track. As the memory disc spins and the read/write head is accurately positioned above a target track, the read/write head can store data onto a track by writing information representative of data onto the memory disc. Similarly, reading data on a memory disc is accomplished by positioning the read/write head above a target track and reading the stored material on the memory disc. To write on or read from different tracks, the read/write head is moved radially across the tracks to a selected target track. The data is divided or grouped together on the tracks. In some disc drives, the tracks are a multiplicity of concentric circular tracks. In other disc drives, a continuous spiral is one track on one side of a disc drive. Servo feedback information is used to accurately locate the transducer. The actuator assembly is moved to the required position and held very accurately during a read or write operation using the servo information.
The memory disc rotates upon a spindle. The spindle assembly contains bearings such as hydrodynamic bearings or ball and socket bearings. Bearings are generally used in numerous applications to allow two surfaces to be supported, guided, or rotated in relation to each other. Hydrodynamic bearings are bearings in which a fluid barrier, such as a lubricant or air, is created between the stator or stationary bearing surface and the rotor or dynamic bearing surface which faces the stator surface. One problem encountered using hydrodynamic bearings is that, during start up of the bearing, before the fluid barrier is formed, machined imperfections on the two facing bearing surfaces, such as machining burrs and imperfect flatness, come into contact with each other. This localized pressure causes a jerky and unpredictable rotation. Also, when the bearing slows down and the two surfaces come into contact again, the burrs can cause unpredictable behavior and may also cause further damage to the other surface.
Ball and socket bearings are bearings in which a ball rotates within a socket and a boundary lubricated interface is developed between the two surfaces. Ball and socket bearings are used in many devices beyond disc drives such as in diverse machinery, automobiles, and knee replacement joints. One problem encountered using ball and socket bearings is that, before the lubricant boundary is formed, the machined imperfections on the surfaces of the ball and the socket strike each other during a period called break-in. The broken material then causes Lewis acids to form, which cause a break down of the lubricant itself. Another problem with bearings in general is that when the stator surface and the rotor surface are made out of different materials, the tribological performance is unpredictable.
A general solution to these problems is to reduce the machined imperfections on the bearing surfaces. However, it is not technologically feasible to machine surfaces that are theoretically perfect and without defects. At a microscopic level, protuberances and imperfections are always present and inherent in the materials. Also, from an economic perspective, it is expensive to attempt to machine surfaces with such minuscule tolerance for error. Furthermore, even if two surfaces were theoretically flat, the problem of inherent static friction at start up would still be a problem since the surfaces would be in complete contact with each other, and this real surface contact would lead to a high localized pressure throughout the contacting surfaces. Thus, a flat surface itself can lead to unpredictable performance.
Thus, what is needed is an economically feasible system that permits the smooth and predictable takeoff and landing of hydrodynamic bearing surfaces, avoids the break-in period of ball and socket bearings, and permits bearing designers to use dissimilar bearing materials while achieving predictable performance.
The present invention provides a system for minimizing contact between the surfaces of bearings at rest. Thus, there is a smooth and predictable take-off period and landing period for hydrodynamic bearings, and a clean break-in period for ball and socket bearings. The system includes a first bearing surface which moves against a second bearing surface, the first surface having a distribution of diamond-like carbon (DLC) pads or bumps. The DLC pads are at a height that is approximately the height of the roughness or imperfections of the surfaces. Thus, the pads help keep the bearing surfaces from coming in contact. The DLC pads are distributed over the bearing surface such that there are enough pads to provide support to the other bearing surface, yet not so many that the pads form a continuous surface and thereby undesirably effect the tribological performance of the bearing.
In further embodiments, the system provides a hydrodynamic bearing having a stator member having hydrodynamic grooves and DLC pads on a thrust plate surface, and a rotor member having an end facing the thrust plate. In another embodiment of the system, a ball and socket bearing having DLC pads is provided.
The present system advantageously provides a system to keep hydrodynamic and other bearing surfaces from coming in contact when the rotor bearing surface is at rest or at a slow speed. This provides the advantage that the imperfections on the surfaces will not come in contact with the other bearing surface and cause unpredictable performance or hinder development of the hydrodynamic boundary.

Hydrodynamic bearings and boundary lubricated system with DLC bumps


Methods for backup and recovery are disclosed. The method includes determining, based on attributes of at least one of one or more files included in data to be backed up, priorities of data blocks associated with the at least one file and storing the data to be backed up and indications of the determined priorities of the data blocks to a second storage device. The methods may determine data blocks that are more important for recovery while backing up data, so that backup data can be recovered faster in future.

With the development of cloud computing and virtualization technologies, more and more Internet service providers host their servers and business data to virtual machines of computing infrastructures located in a cloud and regularly back up their data to data warehouses. When it is necessary to recover from a data warehouse, for example, when a computing infrastructure in the cloud unfortunately fails, the data that has been backed up is requested from the data warehouse and stored locally to restart a virtual machine and recover a service.
Although infrequent, it is still expected that the service can be recovered as soon as possible after the interruption. Since the volume of backup data is usually hundreds of gigabytes (GBs) or even more, the time to recover the service is long, and the usual recovery time objective (RTO) is as long as several hours or even days, which cannot meet business needs. This poses a challenge for cloud computing and cloud storage technologies.


An image display device and a method for operating the same are disclosed. The method for operating the image display device including a plurality of backlight lamps arranged on upper and lower sides of a rear surface of a display panel includes receiving a 3-Dimensional (3D) image, alternately aligning a left-eye image and a right-eye image of the 3D image, and alternately displaying the aligned left- and right-eye images. In the displaying step, the backlight lamps arranged on the upper side of the panel and the backlight lamps arranged on the lower side of the panel are turned on in a portion of a period of the left-eye image or the right-eye image.

1. Field of the invention
The present invention relates to an image display device and a method for operating the same, and more particularly to an image display device, which is capable of reducing crosstalk when a 3-Dimensional (3D) image is displayed, and a method for operating the same.
2. Description of the Related Art
An image display device includes a function for displaying a viewable image to a user. The user can view a broadcast using the image display device. The image display device displays a broadcast, which is selected by the user from broadcast signals transmitted from a broadcast station, on a display. Currently, analog broadcasting is being phased out in favor of digital broadcasting.
A digital broadcast refers to a broadcast for transmitting digital video and audio signals. The digital broadcast has low data loss due to robustness against external noise, advantageous error correction, high-resolution screen, as compared with an analog broadcast. In addition, the digital broadcast can provide a bidirectional service unlike the analog broadcast.
Recently, research into stereoscopic images has been actively conducted. In addition, in various environments and technologies as well as a computer graphics field, the stereoscopic image technology has become increasingly common and put to practically use.

Image display device and method for operating the same


A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.

It will be appreciated that fuse memory cells are increasingly being used in integrated circuits, in particular in semiconductor memories, such as DRAMs, for example. A fuse memory cell essentially comprises a metal-metal connection having a low contact resistance, which can be interrupted after the actual production process, whereby the contact resistance of the fuse memory cell is increased. The fuse memory cell can thus assume the programming states "conducting" and "non-conducting", that is to say that it represents either a logic 1 or a logic 0.
The metal-metal connection of a fuse memory cell is interrupted as required either by the application of a current or by the action of a laser beam. Depending on the method by means of which their metal-metal connections can be interrupted, fuse memory cells are referred to as electrical fuse memory cells or as laser fuse memory cells.
Furthermore, so-called antifuse memory cells also exist, in the case of which an electrical connection is not interrupted, rather such a connection is provided after the actual production process for programming purposes. No distinction is made hereinafter between fuse and antifuse memory cells. Instead, the term "fuse memory cells" is understood to mean both types of fuse memory cells.
In the German-language specialist literature the terms "Schmelzbrücken" ["fusible links"], "auftrennbare Schmelzbrücken" ["interruptible fusible links"] or "Sicherungen" ["fuses"] are occasionally used for fuse memory cells. However, even in the German-language specialist literature, the term "Fuse" [fuse"] is significantly more common. Therefore, the text hereinafter will refer to fuse memory cells.
Conventional electrical fuse memory cells have a resistance of 7 kΩ in the case of an interrupted fuse connection and a resistance of 300Ω in the case of an intact fuse connection. The high resistance value of a blown fuse memory cell is obtained by means of a high fusing voltage that is present at the fuse memory cell during the interruption operation. For a high fusing voltage to be applied to the fuse memory cell, the oxide substrate on which the fuse memory cell is situated must have a certain minimum thickness. However, such an oxide thickness is generally not required by the remaining components arranged on the same substrate. Accordingly, high additional costs are associated with a high resistance value of a blown fuse memory cell.
Conventional read-out circuits by means of which the programming state of a fuse memory cell is read out compare the resistance of the fuse memory cell with the resistance of the source-drain path of a MOS transistor arranged in the measurement path. The measured resistance of the fuse memory cell also depends on fluctuations during the production of the transistor.
A further disadvantage of conventional read-out circuits for fuse memory cells is static currents that flow through the fuse connection during the reading of a blown fuse memory cell. In addition to the increased current consumption, these currents also pose a safety problem for the associated circuit.

Differential read-out circuit for fuse memory cells


Method and system for protecting data in a PCI-Express device is provided. The method includes adding error correction code (ECC) to every byte of data that enters a PCI-Express Transaction Handler (“PTH”) Module and is destined for a host system memory or destined to another device, before the data is aligned within the PTH module; verifying the ECC code for every byte of the data before the data leaves the PTH module; and generating the ECC code for a data block size, wherein the data block size depends on the destination of the data.

1. Field of the Invention
The present invention relates to computing systems, and more particularly to maintaining data integrity in PCI-Express devices.
2. Background of the Invention
Conventional computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output ("I/O") devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems are used in various network applications, including storage area networks ("SANs"). In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters. Host systems often communicate with storage systems via a host bus adapter ("HBA", may also be referred to as a "controller" and/or "adapter").
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect ("PCI") interface, a local bus standard that uses parallel data transfer, or the extension of PCI known as PCI-X. Both the PCI and PCI-X standard specifications are incorporated herein by reference in their entirety.
More recently, PCI-Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X. PCI-Express is an Input/Output ("I/O") bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI Express bus.
HBAs (a PCI-Express device) that are placed in SANs, receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing. HBAs operate as a transmitting device as well as a receiving device.
When data is moved from host system memory to storage systems and vice-versa, it needs to be protected. This is because memory in electronic devices has the potential to return incorrect information. There are two types of errors, "hard" and "soft". A hard error may occur when a bit may be stuck so that it always returns "0". A soft error occurs when a bit reads back wrong information once and then functions properly. Soft errors are more difficult to detect versus hard errors.
Data can be protected using parity and error correction code ("ECC"). Parity checking is a rudimentary way of checking single bit errors. Parity adds a bit of data to every 8-bits (or other sizes) of data. When parity checking is enabled, a logic circuit called a parity generator/checker examines every byte of data and determines whether the data byte has an even or an odd number of ones. If it has odd number of ones, the ninth bit is set to one; otherwise it is set to zero. When data is read, the parity circuit operates as a checker and determines if there are odd or even number of ones to determine if there is a bit-error. Parity checking provides single-bit error detection, but does not handle multi-bit errors, and does not correct errors.
ECC is used to detect single/multiple bit errors and corrects errors. A special algorithm (for example, SECDED (Single Error Correction with Double Error Detection) algorithm) is used to encode information in a block of bits that contains enough detail to permit recovery of a single bit error in the protected data. ECC typically uses 8 bits of code to protect 64 bits of data.
HBAs operating in networks use ECC to protect data when data is moved from host system memory to HBA memory and then sent to a storage system (i.e. in the transmit path). ECC is also used to protect data when it is received from a storage system and sent to host system memory via the HBA (receive path).
Often data has to be aligned, padded and/or shortened (by removing padding) at the HBA level when data is being moved through a data path in the HBA. ECC has to be generated/re-generated depending on how data is being aligned and handled. This requires ECC data to be checked and re-generated for each re-alignment option at each transition in transmit/receive data paths. As the number of re-alignments increase, the number of gates required to re-generate and check ECC increases. This increases cost and complexity and is hence undesirable.
Therefore, there is a need for a method and system that can efficiently generate and verify ECC in an environment where data is aligned/re-aligned.

Byte level protection in PCI-Express devices


Multimodal multilabel tagging of video content may include labeling the video content with topical tags that are identified based on extracted features from two or more modalities of the video content. The two or more modalities may include (i) a video modality for the object, images, and/or visual elements of the video content, (ii) a text modality for the speech, dialog, and/or text of the video content, and/or (iii) an audio modality for non-speech sounds and/or sound characteristics of the video content. Combinational multimodal multilabel tagging may include combining two or more features from the same or different modality in order to increase the contextual understanding of the features and generate contextually relevant tags. Video content may be labeled with global tags relating to overall topics of the video content, and different sets of local tags relating to topics at different segments of the video content.

Multiple hours of video content are published every day for users to stream via different video delivery platforms. The video content can cover a variety of subjects and/or topics.
Some of the video content may not be labeled with tags. Other video content may be incorrectly labeled with one or more tags that are not sufficiently descriptive of the topics, content, subject matter of the video content.
The tags may allow search engines to find relevant videos based on user provided search criteria, specified user interests, temporal relevance, and/or contextual relevance. Video delivery platforms may also use the tags to provide customized feeds or streams of video content to keep users engaged based on known preferences of the users and/or previous viewing behavior. Accordingly, accurate tagging of video content leads to an improved user experience.

This patent is subject to a terminal disclaimer.

Systems and methods for multimodal multilabel tagging of video


An inverter component layout and mounting bracket are disclosed which allow for electrical components, or the inverter as a whole to be replaced easily in the field. The disclosed mounting bracket and component layout also improve the heat rejection properties of the inverter.

The solar energy industry is expanding at a rapid pace. Much of that expansion is due to increases in residential and small commercial photovoltaic (PV) installations. Increasingly these installations are directly connected to the utility grid without the use of batteries. Inverters are the power electronics equipment that converts DC electricity produced by PV panels (collectively a PV array) into AC required by the grid.
An inverter can be a complex device, difficult to install and repair. An inverter is often heavy and can be difficult to hold in place while mounting on a wall. An inverter can contain many components, which are often tightly packed within an enclosure. With such an inverter, field servicing is impractical and shipping the inverter to a service center is required, resulting in many days or weeks with the inverter out of service.
It would be advantageous to provide an inverter that is easy to mount on a wall and which is easy to service in the field.


Techniques are described for protecting information in a convenient and useful way. A user transmits information from a mobile device to an ambient display, so that other users may receive the information from the ambient display. A display controller detects a presence of a potentially unauthorized user relative to the ambient display, and modifies the outputting of the information at the ambient display so as to hide portions of the information that should not be seen by the potentially unauthorized user. The information, including the hidden portion, is nonetheless output, using one of a plurality of output channels of one or more secondary devices, either to the user and/or the other users. In this way, authorized users may continue to receive the information, and, moreover, may input an indication as to whether an extent of the hidden portion is sufficient to provide adequate security with regard to the information.

Presentation systems allow a user of a device to present content on a separate device. For example, a user of a laptop computer may wish to present contents of the laptop computer to other users, where the content may include, for example, a presentation, an image, an audio recording, or a text document. It may be inconvenient, however, for all of the viewing users to view the content on the screen of the laptop computer. In this case, the laptop user may make use of a larger screen or display that may be present, in order to present the content in a manner that is easily and comfortably viewable by everyone present.

Information control in federated interaction


Disclosed herein is a current sense amplifier (ISA) circuit with increased speed, less insensitivities to process variation, better stability and improved output signal swing. According to one embodiment, the ISA circuit described herein may include a pair of output nodes and a first pair of load transistors, each coupled between a different one of the output nodes and ground for pulling the output nodes down to a first voltage value at the beginning of a sense cycle. In addition, a pulse generation circuit is included for activating the first pair of load transistors at the beginning of the sense cycle and deactivating the first pair of load transistors once the first voltage is reached. When activated, the first pair of load transistors provide a relatively low resistance current path between the output nodes and ground. This decreases the output node discharge time and increases the overall speed of the sense amp without compromising circuit stability and output swing.

1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to pulse generation circuits that may be used in a current sense amplifier (ISA) for improving speed and robustness without compromising circuit stability or output swing.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many semiconductor memories employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. These differential amplifiers and sense circuits are commonly known as sense amplifiers (or "sense amps"). In addition to memory devices, sense amplifiers may be used in programmable arrays and other applications. A wide variety of sense amps are known in the art, including current sensing and voltage sensing variations.
For example, dynamic random access memory (DRAM) devices usually employ voltage sense amplifiers (VSAs) for detecting the state of a DRAM memory cell. In voltage sensing, the bitline is precharged before the memory cell is activated. When the memory cell is activated, the memory cell charges or discharges the bit line to maintain or change the voltage of the bit line. However, the bit line may be quite long and loaded by a large number of memory cells in some memory devices (e.g., large memory arrays), resulting in a large capacitive load for the memory cell. In some cases, the memory cell may not be able to provide enough cell current to quickly discharge or charge a large bit line, and an excessive amount of time may be needed to read the memory cells. Therefore, voltage sensing may not be the preferred sensing scheme in all memory devices.
For this reason, current sense amplifiers (ISAs) are sometimes used in memory device circuits. Because current sense amplifiers provide sensing speeds that are independent of the capacitive loads on the bit lines, they are well suited in large memory arrays that are subject to large loads on the bit lines. Located in a sense amplifier cell, the current sense amplifier measures a current and turns this into a small voltage difference output. In some cases, the output of a current sense amplifier may be passed to a voltage sense amplifier (VSA), which is also located in the sense amplifier cell for amplifying the low voltage signal into a higher voltage signal. The output of the voltage sense amplifier may then be passed as the output of the sense amplifier cell.
FIG. 1 illustrates one embodiment of a current sense amplifier 100, which may be used for detecting a current differential between the complementary bit lines of a memory array (such as memory array 150). In the embodiment shown, ISA 100 is coupled for receiving a pair of differential currents (IBL, IBLB) from one or more complementary bit lines (BL, BLB) of memory array 150. In some cases, ISA 100 may be coupled for receiving a pair of differential currents from only one column of memory cells, as shown in FIG. 1. In other cases, ISA 100 may be coupled for receiving a pair of differential currents from more than one column of memory cells (not shown). If the memory array includes more than one column of memory cells, column multiplexers (COLMUX) are generally used to switch between the different pairs of bit lines.
As shown in FIG. 1, current sense amplifier 100 may include a pair of PMOS cross-coupled transistors (M2a, M2b), a pair of PMOS load transistors (M3a, M3b), a pair of PMOS pull-up transistors (M4a, M4b) and an NMOS enable transistor (M5). When employed within a memory device, differential bit line currents (IBL, IBLB) may be supplied to the source terminals of cross-coupled transistors M2a and M2b during a read operation. To be "cross-coupled," the gate terminal of PMOS transistor M2a must be coupled to the drain terminal of PMOS transistor M2b, and vice versa. The drain terminals of cross-coupled transistors M2a and M2b may then be coupled to ground through load transistors M3a, M3b and enable transistor M5. Pull-up transistors M4a and M4b are used for precharging the output nodes (out, out_b) of the current sense amplifier before the read (or "sense") operation begins. Once the sense amplifier is enabled (e.g., when an active enable signal, "en," is supplied to transistor M5), ISA 100 converts the pair of differential currents into a pair of differential voltages by allowing load transistors M3a, M3b to discharge the output nodes before a voltage difference is allowed to develop there between. In some cases, the pair of differential voltages may be supplied to a voltage sense amplifier (not shown). If used, the VSA may amplify the differential voltages (e.g., up to CMOS levels) and use the amplified voltages to generate a single-ended sense amplifier output voltage.
In FIG. 1, cross-coupled PMOS devices M2a and M2b provide a virtual short between the bit lines. This enables current from the memory cell to immediately begin flowing into the source terminals of these devices. This cross-coupled topology and the virtual short it creates makes the current sensing approach relatively insensitive to bit line loading, and hence, faster for large memory arrays as compared to conventional voltage sensing schemes.
The PMOS load devices (M3a and M3b) coupled below cross-coupled devices M2a and M2b serve two purposes. The first purpose is to convert the cell current into a voltage difference between output nodes out and out_b, which may then serve as inputs to a subsequent voltage sensing stage. The delay attributed to the current sensing stage may be described as the time it takes for the voltage difference to develop into a value, which is large enough for the voltage sensing stage to detect and amplify (e.g., the delay of the current sensing stage must account for input offsets of the voltage sensing stage with room for extra overdrive). The second purpose of the PMOS load devices (M3a and M3b) is to stabilize the current sense amplifier circuit. For example, if the resistance of load devices M3a and M3b is too low, a negative impedance may be created at the inputs of cross-coupled transistors M2a and M2b, which may cause the circuit to oscillate. Therefore, load devices M3a and M3b are generally required to have a large resistance in order to provide the desired signal swing and circuit stability.
However, a trade-off arises between load resistance and the delay of the current sensing stage. For example, when the bit lines are inactive, all nodes are precharged to a power supply voltage (vpwr) by the pull-up transistors (M1a and M1b) in the memory array and the pull-up transistors (M4a and M4b) in the ISA. Assuming that the memory array is initially disabled when the sense amp is enabled, nodes out and out_b (which are initially at vpwr) will start to discharge. The output node voltages will eventually settle to a maximum common mode value that is given by a voltage division between the resistances above and below the output nodes. Since the output node voltages started at vpwr, the output capacitance discharges through PMOS loads M3a and M3b with a common mode time constant, which is proportional to the PMOS load resistance. Once the output node voltages settle to the maximum common mode value, the memory cell current flows through the PMOS loads to create the voltage difference between output nodes out and out_b.
The tradeoff is that in order to satisfy the stability and voltage swing criteria listed above, the PMOS load resistances have to be made large. If the PMOS load resistances are made large, the common mode settling time of output nodes out and out_b is increased. This common mode settling delay directly adds to the delay of the current sensing stage. This is shown in FIG. 2, where the delay in reaching the maximum common mode voltage (before the output nodes begin to split) is almost 50% of the total delay of the current sensing stage (which is approximately 6 ns to 8 ns in FIG. 2). As used herein, the total delay of the current sensing stage is defined as the time needed for the difference in the out and out_b voltages to reach 100 mV. This number is based on the expected input offset voltage of the following voltage sensing stage.
Therefore, it would be desirable to provide a current sense amplifier scheme where speed is not compromised for stability or for developing the desired differential split between the output nodes.

Pulse generation scheme for improving the speed and robustness of a current sense amplifier without compromising circuit stability or output swing


A step-by-step motor able to carry out up-and-down motion includes a housing, a bearing, a connecting member, a magnet, a rod unit, a right-handed coil, a reverse coil and a bayonet socket combined together. After the electric wires of the bayonet are electrically connected, the right-handed coil and the reverse coil respectively connected with the electric wires will be electrified to actuate the magnet and the connecting member to rotate clockwise or counter-clockwise. Simultaneously, the rod unit will be driven by the connecting member to move up or down linearly, able to carry out transmission effectively, small in size and taking less space.

1. Field of the Invention
This invention relates to a step-by-step motor able to carry out up-and-down motion, and particularly to one provided with a bayonet socket having electric wires respectively connected with a right-handed coil and a reverse coil. After the electric wires are electrically connected, the right-handed coil or the reverse coil will be electrified to actuate a magnet and a connecting member to rotate clockwise or counterclockwise. The present invention drives drive a top rod to move up or down linearly, and is able to carry out transmission steadily and effectively, small in size and occupies less space.
2. Description of the Prior Art
Generally, the headlamp of an automobile is installed with a step-by-step motor for adjusting the radiating height of the headlamp. A conventional step-by-step motor, as shown in FIGS. 1 and 2, includes a threaded rod 11 threadably combined with the threaded hole 121 of a shaft bushing 12. The shaft bushing 12 has one end extending outward and forming a polygonal bulging block 122 to be engaged with the engage hole 131 of a gear disk 13. An adjusting rod 14 intersecting at right angles with the threaded rod 11 has its lower end engaged with a gear 15 that is engaged with the gear disk 13. Then, all the members mentioned above are disposed in the interior of a fixing base 16 and a positioning base 17, and the adjusting rod 14 and the threaded rod 11 have their outer ends respectively extending out of the fixing base 16 and the positioning base 17. When the adjusting rod 14 is turned around, the threaded rod 11 will be driven to shift by interaction of the gear 15, the gear disk 13 and the shaft bushing 12. However, the conventional step-by-step motor has to be additionally provided with a transmission device at the exterior of the adjusting rod 14 for driving the adjusting rod 14 to rotate, thus enlarging the whole dimensions, taking too much space and failing to control operation precisely.

Step-by-step motor able to carry out up-and-down motion


A computer-implemented method and system for a customer experience resource facility for scheduling a time-based resource on a commerce processing device and accepting an input for a product-based resource, and processing a payment in respect of the time-based resource and the product-based resource using a payment processing facility on the commerce processing device, where the payment processing facility processes payments through the commerce processing device based at least in part on an input received from the customer experience resource facility.

Dimensions of managing a customer interaction are typically accommodated through multiple applications, such as for appointment scheduling, payment processing, personnel management, facility scheduling, and the like, causing inefficiencies by forcing a merchant to operate simultaneously in multiple applications to satisfy the needs of managing a customer experience, including the payment processing aspect traditionally provided at point-of-sale.
Therefore, there is a need in the art for methods and systems that support integration within a point-of-sale process for the multiple functional dimensions associated with managing a customer experience.

Integrated customer experience functionality in point of sale