A processing system comprises a processor and a memory having computer readable instructions stored thereon. The computer readable instructions, when executed by the processor, cause the system to obtain a reference tree of nodes and linkages based on a reference three dimensional volumetric representation of a branched anatomical formation in a reference state. The computer readable instructions also cause the system to obtain a reference three dimensional geometric model based on the reference tree and detect deformation of the branched anatomical formation due to anatomical motion based on measurements from a shape sensor. The computer readable instructions also cause the system to obtain a deformed tree of nodes and linkages based on the detected deformation and create a three dimensional deformation field that represents the detected deformation of the branched anatomical formation.

Minimally invasive medical techniques are intended to reduce the amount of tissue that is damaged during interventional procedures, thereby reducing patient recovery time, discomfort, and deleterious side effects. Such minimally invasive techniques may be performed through natural orifices in a patient anatomy or through one or more surgical incisions. Through these natural orifices or incisions clinicians may insert interventional instruments (including surgical, diagnostic, therapeutic, or biopsy instruments) to reach a target tissue location. To reach the target tissue location, a minimally invasive interventional instrument may navigate natural or surgically created passageways in anatomical systems such as the lungs, the colon, the intestines, the kidneys, the heart, the circulatory system, or the like. Teleoperated interventional systems may be used to insert and position the interventional instrument within the patient anatomy. During navigation of the interventional instrument, the anatomical passageways may deform due to, for example, anatomical motion (e.g. cardiac motion, respiration motion) or a force applied by the interventional instrument. Systems and methods are needed to dynamically deform anatomical passageway models for display to a user while navigating the actual patient anatomical passageways with the interventional instrument.

This patent is subject to a terminal disclaimer.

Systems and methods for non-rigid deformation of tissue for virtual navigation of interventional tools


A method for fabrication of modified poly-buffered LOCOS without positive charges trapping at the beak of the field oxide. The method employs DIW (Deionized Water) to be sprayed onto the wafer before gate electrode forming to eliminate the trapping of positive charges and reduce the undesired charge breakdown thereby increasing the yield of devices not containing this defect.

1. Field of the Invention
The present invention relates generally to the field of Local Oxidation of Silicon Isolation (LOCOS) forming technology, and more particularly, to a method of fabrication of modified poly-buffered LOCOS which can eliminate positive charge trapping at the beak of the field oxide.
2. Description of the Prior Art
LOCOS technology is currently employed most in the fabrication of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Bipolar Circuits to form the field oxide which acts as an isolation layer between active areas. A number of patents have addressed the LOCOS forming technology. U.S. Pat. No. 3,970,486 to E. Kooi, the entire disclosure of which is herein incorporated by reference, describes the processing steps as follows: A P-type substrate is provided, after which a layer of SiO.sub.2 and a layer of silicon nitride are deposited. The pattern of said silicon oxide and silicon nitride is formed by conventional lithography technology. The wafer is thermally oxidized to make the field oxide--the silicon nitride layer here acts as an oxidation mask to avoid the undesired oxidation of the active area. The P-type doping is usually implanted before or after field oxide forming. B.sup.+2 ions are implanted to build a P-type area in order to avoid the unwanted appearance of an inversion layer beneath field oxidation so it is helpful for insulation. The dose implanted before depositing of the oxidation layer is about 1E13 atoms/cm.sup.2 to 5E13 atoms/cm.sup.2 and the energy is of between about 110 to 130 KEV. The dose implanted after depositing of the oxidation layer is of between about 1E12 atoms/cm.sup.2 to 5E12 atoms/cm.sup.2 and the energy is of between about 170 to 190 KEV.
However, a so called "bird's beak" usually happens during LOCOS forming. Both the thinner silicon oxide layer and the thicker silicon nitride layer cause a longer bird's beak, and deteriorate the Crystal Defect of the silicon substrate. The lack of thickness of the bird's beak decreases the isolation ability of LOCOS as well. On the other hand, the active area is insufficient if the bird's beak is too thick. The bird's beak increases in thickness with the thickness of field oxide which increases during conventional processing. The thickness of the field oxide layer is usually increased in order to get enough threshold voltage and avoid leakage between devices, but a bird's beak of excessive length occurs at the same time. It affects the characteristic of the device and limits the ability to obtain high packing density.
U.S. Pat. No. 4,508,757 to Karen A. Fabricus, the entire disclosure of which is herein incorporated by reference, describes a method of manufacturing a minimum bird's beak recessed oxide isolation structure and approach called Poly-Buffered LOCOS process. The process steps are as follows: a silicon dioxide layer, a poly-buffered layer and a silicon nitride layer are formed in sequence. These layers are patterned by conventional lithography technology. The wafer is then subjected to an oxidation step employing said silicon nitride as an oxidation mask. The silicon nitride itself oxidizes very slowly, but is not penetrated by the oxygen. As a result, it protects the underlying silicon from oxidizing, while allowing a thermal SiO.sub.2 layer to grow on regions of exposed silicon. Then the nitride and poly-buffered layers are stripped and the other processes for formation of the device are continued. The poly-buffered layer of the '757 patent decreases the length of the bird's beak by providing a thinner silicon dioxide and thicker silicon nitride layer. Compared to the conventional length of the bird's beak (0.5 micrometer), the length of the bird's beak in devices employing the poly-buffered layer is about 0.1 micrometer. Therefore, it provides an approach to obtain high packing density devices. However, the process still has some undesired aspects because the poly-buffered layer tends to form SiO.sub.2 on its surface. For example, there is a significant level of positive charge traps at the PBLOCOS edge which cause early failure by charge breakdown.

Modified poly-buffered locos forming technology avoiding the positive charge trapping at the beak of field oxide


An electrical connector (1) comprising, an insulative housing (2), conductive contacts (4, 5) within an interior of the housing (2), insulative wiping surfaces (61) on a mating end (12) of the housing (2), and conductive surface areas (60) on the contacts (4, 5) being rearward of the wiping surfaces (61) and offset laterally of the wiping surfaces (61) to engage unwiped surface areas of mating contacts (4, 5) of another, mating connector (1).

An electrical connector, known from U.S. Pat. No. 3,760,335, comprises, an insulating housing and conductive signal contacts. The contacts are grouped in pairs, with an insulative divider of the housing separating one contact of the pair from the other contact of the pair. Multiple pairs of the contacts are distributed along the insulative divider. The pairs of contacts are especially suitable for connection to twisted pair wires used in the communications industry for data and voice transmission. Each pair of the twisted pair wires are connected to one pair of the contacts. To shield the connector from ESD, electrostatic discharge, a conductive metal shell surrounds the insulative housing of the connector. For example, a shielded connector is disclosed in U.S. Pat. No. 5,158,481.
A desirable shielded connector provides ESD protection for the electrical contacts of the connector during mating connection of the connector with another, mating connector. During mating connection of two mating connectors, an electrostatic voltage charge on one or both of the connectors should be discharged to ground electrical potential via the shield on one or both of the connectors, whereby the voltage charge is shunted away from electrical contacts in the connectors.

Electrical connector with protection for electrical contacts


An improved adjustable skimmer belt having a belt of two layers at least one of which has an outer surface of non-absorbent oleophilic-oriented hydrophobic loop-type fibers, vertical and horizontal stitching creating a repeating pattern and used to attach the layers, a plurality of apertures transversing the layers following the repeating pattern thereby creating liquid-collecting pockets between the two layers, and a connector and adjustor formed by the pattern and used to cut and adjust or repair the belt as needed.

This invention relates to oil skimmers, specifically to tramp-oil skimmer belts used in association with a variety of oil-skimming apparatus Tramp-oil generally comprises hydraulic oils, lubricants, and other undesirable oils.
Industrial work which involves metal working such as milling, tooling, machining, boring, and the like, uses high-speed power tools for that purpose A variety of industrial solutions are used to lubricate and to cool the work piece and the machine or tool associated with that work piece. Industrial solutions, such as coolants, are costly When invariably, and unavoidably, tramp-oil becomes mixed with industrial solution, the useful life of the industrial solutions is greatly diminished A need exists to remove tramp-oils from the industrial solution (generally a water miscible cutting and grinding fluid).
The purpose of removing tramp-oil from another industrial solution is to maintain that industrial solution in a contamination-free state and to thereby reduce bacterial growth potential therein. Many apparatus and belts used in association with tramp-oil removal work well in situations where tramp-oil is prevalent in great concentrations and is visible. The belts have an oleophilic hydrophobic quality which is suitable to the purpose. In instances where tramp-oil is in an emulsified state, these belts come up `dry` thereby leaving traces of emulsified tramp-oil in the industrial solution for extended periods of time. Left in this state leads to bacterial growth, contamination, and costly replacement of the industrial solution.
Tramp-oil, even in trace amounts, provides a food source for bacteria and thereby contributes to its growth. Because of such growth, the work place becomes filled with an undesirable rancid and foul-smelling order. Tramp-oil is also the source smoke-mist and oil-mist in the work place. Quality of the work place suffers. These are valid health-related, environmental, and quality-of-life concerns for the well-being of the worker. Quality of work is also affected by the presence of tramp-oil. Tramp-oil reduces the useful life of the machine tool and the useful life of the industrial solution used in the machining process. It provides a means by which undesirable residues are retained in the work place and desposited on the work piece and the machine tool. Overall, the product suffers in time expended to produce it and in the quality of finished product itself. The presence of tramp-oils also results in increased maintenance requirements in the work place. Tramp-oil is the scourge to industry and any efficient means of eliminating tramp-oil will greatly enhance the quality of finished products and quality of life in the work place for the machinist.
Generally, contaminated industrial solutions, even with trace amounts of contaminate, will last for a short period of time. After that, the contaminated fluid is disposed-of and replaced. The problems associated with this method are two-fold--this cure incurs a double cost. One cost for the proper packaging of the contaminated industrial solution and its proper disposal and another for the cost of new industrial solution. A third, indirect but associated problem is final disposal. In an already crowded eco-sphere, limiting waste streams becomes crucial. Disposing of industrial solutions before their time adds to rather than decreases our waste stream.
Adding a bactericide to the industrial solution to kill the bacteria is yet another attempt at curing some problems associated with the presence of tramp-oil. In this cure, one problem was substituted for another since it was found that most bactericides irritated human skin. The problems associated with trace amounts of tramp-oil remain unabated.
Pick-up belts currently used for the purpose of removing tramp-oil are made of a synthetic rubber or rubber-like material. They are non-absorbent and pick-up tramp-oils based on their respective oleophilic and glue-like qualities. Because of their glue-like qualities to oils, these belts are suited for use in industrial solutions with high degrees of oil contamination. These belts are typically associated with the Oylbelt Skimmer.TM. and the Scrounger.RTM., Jr. In industrial solutions where tramp-oil is emulsified, these belts run dry leaving the industrial solution, with its contaminating tramp-oil, in the industrial solution's container. Within a short period of time, bacterial growth is fostered and the quality of the industrial solution, working environment, and work piece suffers. Not only does this type belt fail to pick-up the industrial solution, it is extremely costly.
A less costly belt, made from the loop-like fibers of a hook-and-loop fastening material positioned on both sides, also works well in tramp-oil saturated situations but not in those situations where tramp-oil is emulsified. Most prior art inventions involve a complete skimming apparatus. The type of belt used is peripheral to the invention.
Koller (U.S. Pat. No. 4,274,957) discloses a self-contained skimmer utilizing a flexible endless belt made of a neoprene fabric and having a mat finish. The outer surface of the belt should be wettable by the liquid to be removed.
Threadgill (U.S. Pat. No. 4,652,372) discloses a liquid separator having an endless belt for skimming oils from a liquid body. The belt is made of material wettable by oil and that which exhibits oleophilic characteristics on its surface. It is oleophilic on both sides of the belt.
Lewan (U.S. Pat. No. 5,062,953) discloses a belt-type skimmer apparatus which utilizes an endless belt which is engaged between pincher rollers and weighted down in liquid.
Kaylor (U.S. Pat. No. 5,200,083) discloses a skimmer apparatus whose oil removal capabilities are enhanced by use of an oil-avid non-woven mat of oleophilic fibers, preferably a polyolefin or polypropylene, and preferably backed on one side with a heavy polyolefin film cover, on its liquid-contact member. The primary contacting member is the drum. In belt-type skimmers, the belt is composed similarly as is the drum.
Bronnec, et. al., discloses a hydrocarbon extractor of the belt-skimmer type. The belt is an endless belt made of oleophilic material, such as a polyester coated with polyurethane. The opposite outer surfaces of the belt are modified by abrasion.
None of these prior art concepts utilizing a belt has grasped the loop-type belt concept, as taken from the hook-and-loop type fasteners, wherein two loop sides are connected by their respective backsides thereby exposing both loop sides to the liquid, as a viable means of skimming oils from liquids. None that is except Betts, et.al. (U.S. Pat. No. 4,876,011). Betts discovered, must like applicant, that loop sides so configured make a surprisingly good skimming material. The belt is an endless belt fashioned of hydrophobic non-absorbent material. The sewing of two such materials, back-to-back, exposing the loop sides for oil skimming is where the similarity ends. Though such a belt performs reasonably well where the amount of oil is heavy, it does not perform well where oil quantities are low or partially emulsified or emulsified. It has been discovered that strategic placement of stitching and apertures enhance the liquid collection and skimming capabilities of such a belt and permit it to gather emulsified oils. Moreover, none of the prior art disclosures reveal or suggest adjustability, selective repairability, or selective replaceability as does the current invention.
None of the prior art belts can draw out industrial solutions which contain tramp-oils in trace, emulsified amounts. Likewise, none of the prior art belts are configurable at the work place into endless loops or adjustable in the manner of the present invention.
The essence of the present invention lies in its stitching configuration, its versatility and adjustability, and the hydrophillic absorption quality of the otherwise hydrophobic-oriented belt which is created by the plurality of apertures configured throughout which also create liquid-collecting pockets in between the two layers. The improved adjustable skimmer belt not only solves the problems associated with prior art belts, but is it less costly, lasts longer, and is adjustable. It can be easily fitted into any workplace and to any work piece. If any section of the belt becomes damaged, the damaged section or sections can be easily removed and the belt can be easily reconnected for continued and virtually uninterrupted use.


In accordance with one embodiment, a method for scheduling the servicing of job requests in a point-to-point communication system having a central server providing job requests to a plurality of local channel servers. In a first step, the method receives a new job request at a central server. A performance of each local channel server is measured, and the job request is dispatched to one of the local channel servers for servicing thereby dependent upon the performance of each of the local channel servers. In one embodiment, the job request is dispatched to the local channel servers having the lowest current average flow time. In another embodiment, the job request is dispatched to the local channel server having the lowest current maximum stretch value, wherein a stretch value is a ratio equal to an amount of time required to service a job request while also serving other uncompleted job requests, divided by an amount of time required to service said job request if no other job requests were required to be serviced.

This invention relates generally to communication systems, and more particularly to the scheduling of job requests to be serviced in a multiple-channel, point-to-point system.
The boom in the Internet and the rise of new network technologies have focused attention on designing faster and more efficient data networks. A key component of the data network is the data server. Data servers are the engines that store and feed content to diverse clients over the network media. Data servers can take many forms, such as infestations, wireless gateways, web servers or specialized servers such as traffic or weather information servers. Increasingly, data servers employ a multiple-channel, point-to-point model.
For example, FIG. 1 illustrates a typical multiple-channel communication system of the prior art, which satisfies job requests in a point-to-point, or unicast, fashion. In a point-to-point system, each client""s request for data is required to be individually satisfied, even if more than one client makes a job request for the same data item. In this regard, a point-to-point system is different from a broadcast system, which is used to advantage by satisfying all of the pending job requests for a data item with a single broadcast of the data item. One of many examples of a point-to-point system is an Internet server which provides web page data in response to requests from different Internet users.
In FIG. 1, devices 30a through 30w make requests for data which are delivered to central server 10 by any method. Specifically, device 30a makes a job request for data item a, device 30b makes a job request for data item b, and device 30w makes a job request for data item w. Central server 10 receives the job requests and retrieves the requested data from either an internal database or an external database (as will be shown below). Central server 10 then transmits the job request to one of a plurality of local channel servers, designated as 40-1 through 40-k. Each local channel server has a corresponding data channel, designated as 44-1 through 44-k. When the job request is received by one of the local channel servers, the local channel server then services the job request by transmitting the requested data to the requesting device via its corresponding channel.
Additionally, a scheduling method is employed by the system. The scheduling system determines the order in which the job requests are serviced. In the prior art, one method which is typically employed for this purpose is a centralized scheduling method. According to a centralized scheduling method, the central server has a corresponding queue and employs a scheduling algorithm in order to determine which of the jobs pending in its queue are sent to the local channel servers to be serviced. However, a centralized scheduling arrangement has a high overhead. Specifically, a large amount of memory is required to store the pending job requests in the central server""s single queue, and the computational complexity of scheduling all of these jobs simultaneously requires very high processing power.
Another method of the prior art which is typically employed for this purpose, and which imposes fewer overhead costs, is a localized scheduling method. According to a localized scheduling method, each local channel server has a corresponding queue, designated as 42-1 through 42-k. When a job request is received by one of the local channel servers, that local channel server stores the job request in its corresponding queue along with other pending job requests which it has received from central server 10 but which have not yet been serviced. Central server 10 determines which local channel server to dispatch the job request to by employing a load balancing algorithm. Although there are various definitions of xe2x80x9cloadxe2x80x9d, generally a central server which employs a load balancing algorithm assigns each new job to the local channel server that has the fewest pending bytes in its queue waiting to be serviced. In another prior art scheme, the central server employs a load balancing algorithm and assigns each new job to the local channel server that has the fewest number of jobs in its queue waiting to be serviced.
Additionally, according to a localized scheduling scheme, each local channel server also employs a scheduling algorithm in order to determine which of the jobs pending in its corresponding queue are to be serviced first. One scheduling algorithm which is typically employed by the local channel servers is a first-in first-out scheme. However, this arrangement may be unsatisfactory, specifically with widely heterogeneous data requests, because a large job request which arrives early may prevent small, later-arriving job requests from being serviced until after the large job request has been completely serviced (heterogeneous data requests are data requests of varying sizes).
Another scheduling algorithm which is typically employed by the local channel servers is the xe2x80x9cShortest Remaining Processing Timexe2x80x9d (hereinafter referred to as xe2x80x9cSRPTxe2x80x9d) algorithm. The SRPT algorithm produces a schedule which minimizes the time it takes to process all of the uncompleted jobs in a queue when there is a single processor that schedules a queue of pending jobs for service via a single channel. The SRPT algorithm is typically employed when jobs arrive in a continuous stream, and is based upon a sum-flow metric. The relevant parameter of the sum-flow metric is the time a job spends in the system. The SRPT algorithm employs the sum-flow metric by summing the time that all jobs spend in the system, and schedules the pending jobs so as to minimize this summed amount of time.
However, the SRPT algorithm has the drawback that it leads to starvation. Starvation occurs when some job request to the server is delayed to an unbounded extent. For instance, starvation may occur when the servicing of a pending job request is continually delayed because the SRPT algorithm determines that incoming job requests are serviced prior to the pending job request. Although the SRPT algorithm can be desirable in some circumstances, the fact that specific job requests are delayed to an unbounded extent is unfair to the person who made the request which is delayed. Furthermore, the fact that some job requests are delayed to an unbounded extent prevents the owner of the server system from being able to make a quality-of-service guarantee to each user that the schedule will be responsive to each job and avoid starvation of any job.
Although the above-referenced scheduling methods have attempted to address data server performance issues, there is an ever increasing need for improved scheduling methods that provide satisfactory performance. Therefore, there exists a need for a system and method for optimally scheduling the transmission of data items in multiple-channel, point-to-point communication system.
In accordance with one embodiment, a system and method is disclosed for scheduling the servicing of job requests in a localized point-to-point communication system having a central server providing job requests to a plurality of local channel servers. In a first step, the method receives a new job request at the central server. A performance of each channel is measured based upon a predetermined performance metric, and the job request is dispatched to one of the channels for servicing thereby dependent upon the performance of each of the channels. In this context, a performance metric is a quantitative measure of data flow through each channel.
In one embodiment, referred to as the minimum flow algorithm, the job request is dispatched by the central server to the local channel server having the lowest current average flow time. Flow is a measurement of the amount of time required to service a job. Thus, flow is equal to the difference between an arrival time of a job request and a completion time of a job request. When a job request is completed by a local channel server, the server calculates the flow for that job, then calculates an average flow for all of the jobs that the server has completed so far.
In another embodiment, referred to as the minimum stretch algorithm, the job request is dispatched by the central server to the channel having the lowest current maximum stretch value. A stretch value is a ratio equal to an amount of time required to service a job request while also serving other uncompleted job requests, divided by an amount of time required to service the same job request if no other job requests were required to be serviced. In other words, a stretch value provides an indication of the delay experienced by each job request to complete, when the server processes many job requests concurrently. Each local channel server maintains a record of its current maximum stretch value in order to schedule the job requests pending in its queue.
Additionally, each local channel server also employs a scheduling algorithm in order to determine which of the jobs pending in its corresponding queue are to be serviced first. According to one embodiment, an SRPT scheduling algorithm is employed by a local channel server, which sums the time that all jobs spend in the system and schedules the pending jobs so as to minimize this summed amount of time. According to another embodiment, a MAX scheduling algorithm is employed by a local channel server, which schedules the pending jobs inits queue so as to minimize the stretch experienced by each job request serviced thereby.
Both the minimum stretch and the minimum flow algorithm of the present invention outperform the prior art load balancing algorithm with respect to the average stretch and the average response time experienced by the job requests in the system.

System and method for scheduling data delivery using flow and stretch algorithms


For segments having the number of IOs exceeding a threshold, a data collection unit connects adjacent segments whose distance is within “s” to each other and extracts the connected segments and segments in the range of “s” from outside of the connected segments as an n_segment. A workload analysis unit then determines a target whose data is moved from an HDD to an SSD in units of n_segments.

When a workload analysis of a storage device such as an HDD (Hard Disk Drive) is performed, a load is often biased to some areas. FIG. 14 is an example of a workload analysis. In FIG. 14, the vertical axis indicates an offset in a downward direction and the horizontal axis indicates an elapsed time. The offset represents a difference from a head address of a volume allocated to a user. The elapsed time is measured in the unit of minutes.
In FIG. 14, the black part is a high load area. Three blocks are present as the high load area in FIG. 14. Among the high load areas, for an area that is generated similarly on a daily basis, static hierarchical control is effective. The static hierarchical control is a technique of moving data of a high load area to a storage device such as an SSD (Solid State Drive), which works at a speed higher than that of an HDD, by using previous statistical information at a pre-determined time on a daily basis.
For example, in FIG. 14, when a block A and a block B among the three blocks are generated similarly on a daily basis, data corresponding to the blocks A and B are moved to an SSD, so that frequently accessed data is accessed at a high speed. Therefore, by using the static hierarchical control, the performance of an information processing system can be improved.
Meanwhile, in FIG. 14, when a block C is generated only on a particular day, the block C cannot be moved to the SSD by using the static hierarchical control. Accordingly, dynamic hierarchical control that moves data of a high load area to the SSD based on a load that is measured in real time is executed on the block C (see, for example, Kazuichi Oe, Kazutaka Ogihara, Yasuo Noguchi, and Toshihiro Ozawa, "Proposal for a hierarchical storage system that can move a spike to high-speed storage in real time", the Annual Symposium on Advanced Computing Systems and Infrastructures (SACSIS2012), Kobe, Japan, May 2012).
There has been a conventional technique in which, when a highly-frequently accessed file is accessed, based on related information such as a sector used by the file, a disk array device reads data that is stored in a sector in a predetermined neighborhood of the sector used by the file in a hard disk into a cache. Furthermore, there has been a conventional technique of, when a presence density that is the rate at which an accessed logical track is present is increased or equal to or larger than a certain value, determining as sequential access or generally sequential access and pre-reading a neighborhood of a block in which data is present from an external storage device. Further, there has been a conventional technique in which, in a disk control device including a cache, a neighboring part of an accessed physical area is also loaded.    Patent Document 1: Japanese Laid-open Patent Publication No. 2002-207620    Patent Document 2: Japanese Laid-open Patent Publication No. 2002-182978    Patent Document 3: Japanese Laid-open Patent Publication No. 06-119244
By applying the conventional techniques of moving data of a neighborhood of a high load area to dynamic hierarchical control that moves data of a high load area to an SSD based on a load measured in real time, the performance of an information processing system can be improved. However, in order to move the data of the neighborhood of the high load area to the SSD, an area that is appropriate as the neighborhood needs to be selected.

Control program of storage control device, control method of storage control device and storage control device


A microprocessor includes a control register having a predetermined bit which is unconditionally writable to either a first state or a second state. Additional bits of the control register are writable to either the first or second state when the predetermined bit has the first state. Each additional bit is not writable when the predetermined bit has the second state. The microprocessor further includes at least one circuit controlled by the state of a corresponding one of the additional bits of the control register. The writability of the additional bits is preferably further conditioned upon the state of a machine status register, which is unconditionally writable to either the first state or the second state. A primary AND gate and a secondary AND gate corresponding to each additional bit control the writability of the additional bits. The secondary AND gates may further condition the writability of the corresponding additional bit on the state of a secondary machine status register, the current privilege level or other microprocessor status signals or plural additional inputs. Each bit of the control register is written into a corresponding bit of the shadow register upon writing the second state into the machine status register.

It is known in the art to differentiate between microprocessors of the same family via whether a control register bit is both readable and writable. In particular, it is possible to distinguish between various generations of the Intel x86 family of microprocessors (including the 8086, 80286, 80386, 80486, Pentium and Pentium Pro microprocessors) using this technique. U.S. Pat. No. 5,426,767 METHOD FOR DISTINGUISHING BETWEEN A 386-TYPE CENTRAL PROCESSING UNIT AND A 286-TYPE CENTRAL PROCESSING UNIT issued Feb. 6, 1996 discloses a method to determine if a particular microprocessor is an Intel 80286 or an Intel 80386. This method detects whether bits 12, 13 and 14 of the EFLAGS register may be set to "1". The method generally includes: a write to the EFLAGS register with bits 12, 13, and 14 of the write data set to "111"; a read of the EFLAGS register; and an examination of bits 12, 13, and 14. In an Intel 80286, these bits cannot be set to "1" but are always read as "0". Thus if these bits are "0", the microprocessor is a 80286. In an Intel 80386, these bits may be written set to "1" via a register write instruction. In subsequent reads of the EFLAGS register, these bits would be read as "1". Thus if these bits are read as "1", then the microprocessor is a 80386.
Intel has a practice of employing more bits of the EFLAGS register with each new generation of microprocessors in this family. Thus the new generation of microprocessor changes particular bits from nonwritable/readable only as "0" to both readable and writable as compared with the prior generation. In some cases the particular EFLAGS bits are used for expanded functions in the higher generation. In other cases, the mere fact that a particular bit in the EFLAGS register is both readable and writable indicates that some other expanded function is available in the higher generation. This is the case for the CPUID instruction as disclosed in UK published patent application GB 2,270,176 A entitled "IDENTIFYING A COMPUTER MICROPROCESSOR." Therefore in general, it is possible to distinguish between adjacent pairs of processor generations in the Intel x86 family by whether particular bits of the EFLAGS register are both readable and writable. Independent software developers writing programs for computers using the Intel x86 family of microprocessors typically employ a series of such EFLAGS bits tests to determine the generation of a particular microprocessor within the family. This permits the independent software developer to select between program modules based upon the detected generation. Thus programs may be written to take advantage of features of later generations of the microprocessor family, which are presumably more powerful, and switch to alternate presumably less powerful code for earlier generations without the later added feature. This permits compatibility with plural generations of the microprocessor family while employing more powerful features of later generations.
Recently the possibility of construction of a single chip microprocessor with patchable microcode has become feasible. Thus the possible functions of the microprocessor need not be fixed upon manufacture. U.S. Provisional Patent Application Ser. No. 60/013,043 entitled SINGLE CHIP MICROPROCESSOR CIRCUITS, SYSTEMS, AND METHODS FOR SELF-LOADING PATCH MICRO-OPERATION CODES AND PATCH MICROINSTRUCTION CODES and U.S. Provisional Patent Application Ser. No. 60/013,058 entitled MICROPROCESSOR WITH CIRCUITS, SYSTEMS, AND METHODS FOR OPERATING WITH PATCH MICRO-OPERATION CODES AND PATCH MICROINSTRUCTION CODES STORED IN MULTI-PURPOSE MEMORY STRUCTURE, both filed Mar. 8, 1996, disclose a single chip microprocessor in which external systems enable microcode patches. These microcode patches enable change of the functionality of the microprocessor after manufacture. Such microcode patches may be used to correct bugs in the original microprocessor after manufacture even in the possession of the end user. Such bugs include erroneous or anomalous operations produced by errors in the original design. One infamous example of such a bug is the erroneous operation of the floating point divide instruction in response to some data patterns in the Intel Pentium microprocessor. These microcode patches may also be used to add functionality to the microprocessor after manufacture. Depending upon the particular added feature, this microcode patch technique may be capable of adding additional features first implemented by Intel in later generations of the microprocessor family. However, software produced by independent software developers may not be able to take advantage of this microcode patch. Programs developed to take advantage of the new feature would ordinarily check the newly read/writable EFLAGS bit of that generation of microprocessors to determine if the particular microprocessor is of a generation that supports this new feature. An older generation microprocessor with the new feature implemented in patched microcode would fail this test. Thus the independently developed program would not use the new feature implemented in patched microcode because it would not realize the microprocessor supports the new feature.

Method and circuit for redefining bits in a control register


Embodiments of the invention are generally directed to systems, methods, and apparatuses for the direct duty cycle calibration of a receiver clock. In some embodiments, an integrated circuit includes a receive (RX) data path, a RX clock path, and a control path. In some embodiments, the control path uses RX latches, a majority detector, and digital duty cycle control logic to calibrate the duty cycle of the clock signal. Other embodiments are described and claimed.

High-speed input/output (IO) circuits (e.g., those that support a double data rate, "DDR") use both the rising edge and the falling edge of a clock signal (or simply, clock) to sample data. If the clock does not have a good duty cycle, the rising edge and the falling edge of the clock cannot be properly aligned to sample data at the same time. The purpose of "receive clock duty cycle correction" is to properly align both the rising and falling edges of a clock with the data that is sampled.
Conventional IO circuits use analog detectors to perform receive clock duty cycle correction. These analog detectors typically include a differential amplifier (e.g., a front-end differential amplifier) connected with a differential clock. The output of the amplifier may be connected to an analog integrator (e.g., using a capacitor). These analog circuits typically consume a large die area. In addition, they are typically "always on" because their long settling time prohibits frequent power management of the clock distribution, which may consume a fair amount of power.

Duty cycle calibration for receiver clock


Xylaria grammica EL 000614 strain has a nematicidal activity against root knot nematode. A method for controlling root knot nematode includes treating a crop, a crop seed, or a field for cultivation with a nematicidal microorganism formulation. The method has very little possibility of having a problem related to environmental contamination, and exhibits a high mortality and activity of inhibiting egg hatching for sweet potato root knot nematode (M. incognita). It is expected that the strain can be very advantageously used as an innovative biological control agent which enables prevention of problems associated with environmental contamination.

Plant parasitic nematodes feeding on nutrients after their invasion of plant root are known as a pathogen that attacks a crop. Production loss of representative 40 crops caused by nematode infection makes up 10% of the loss of the entire production amount of crops, and the damage cost tends to increase every year. As the plant parasitic nematodes causing a damage on crops all over the world, there is a root knot nematode as a representative example. The root knot nematode (Meloidogyne spp.) has a broad host range like infecting about 2,000 kinds of plants, and, while parasitizing inside a root of a plant, it completes its life cycle by feeding on nutrients from the plant. In accordance with an increase in cultivation in facilities, number of the root knot nematodes has also increased dramatically, thus causing rapid increase in damage to crops. As four kinds of the nematodes that are taken seriously in agriculture, there are sweet potato root knot nematode (Meloidogyne incognita), carrot root knot nematode (Meloidogyne hapla), Java root knot nematode (Meloidogyne javanica), and peanut root knot nematode (Meloidogyne arenaria). Among them, Meloidogyne incognita is particularly problematic in cultivation facilities in South Korea.
Meanwhile, as a conventional method for reducing or controlling a damage to crops caused by nematode infection, there are soil fuming, soil over-humidification, artificial increase of temperature inside a green house, crop rotation, or the like. However, as those methods exhibit an influence on crops and cannot control completely the nematodes, it cannot be said that they are a favorable method. Other than those, a method of using chemical pesticide has been developed, but it also has a problem like toxicity for human body and environment. Accordingly, to replace those methods, various studies are currently carried out. As a representative example of the study for controlling nematodes, there are studies as follows: 1) study of nematode control by using plant-derived resistant gene, 2) study using proteins and peptides which exhibit toxicity for nematodes, 3) study of nematode control by using a natural product or a plant metabolite, 4) study using nematode-repelling material and plant, 5) environment-friendly control method, and 6) study of nematode control using genetic information and protein information of nematodes. Accordingly, studies of selecting the strains with nematicidal activity by nematicidal activity screening for culture of various microorganisms and developing strains for controlling diseases that are caused by plant parasitic nematodes are continuously under progress.
Meanwhile, in Korean Patent Registration No. 0574348, "Xylaria sp. AH001 strain producing griseofulvin, formulation for controlling plant diseases containing same, and method for controlling plant diseases by using same" is disclosed, and in Korean Patent Application Publication No. 2010-0116562, "Bacillus velezeneis G341 strain and method for controlling plant disease using same" is disclosed. However, nothing has been described with regard to Xylaria grammica having nematicidal activity against root knot nematode as described in the present invention.

INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY

NATIONAL INSTITUTE OF BIOLOGICAL RESOURCES


A plug connector assembly for mating with a complementary connector includes a printed circuit board (PCB) defining a plurality of conductive pads, a pair of metal members mounted on two sides of the PCB and soldered with the PCB for electrically connecting with the complementary connector, an inserting member electrically connected on a front end of the PCB to connect to the complementary connector, and a housing enclosing the PCB. The PCB includes a front portion, an opposite rear portion, and a middle portion connecting the front portion and the rear portion. The conductive pads include a plurality of first pads disposed on the front portion. The inserting member includes an insulative member and a plurality of terminals held on the insulative member. The terminals are soldered with corresponding first pads.

1. Field of the Invention
The present invention relates to a plug connector assembly, and more particularly to the assembling structure of the plug connector assembly. This application relates to the copending application Ser. No. 14/477,889 filed Sep. 5, 2014 having the same assignee with the instant application
2. Description of Related Arts
China Patent No. 203193000, issued on Jan. 28, 2013, discloses a plug connector comprising an insulative body, a plurality of terminals held in the insulative body, a shielding member assembled around the insulative body, and a printed circuit board (PCB) soldered with the terminals and cable wires. Each terminal comprises a contacting portion and a soldering portion extending beyond the insulative body and soldered with the PCB. The shielding member also performs the function of latching the complementary connector.
U.S. Pat. No. 8,794,981, issued on Aug. 5, 2014, discloses a plug including a PCB (printed circuit board). The PCB includes signal contact pads, a plurality of pins electrically coupled and attached to the signal contact pads on a top and lower surfaces of the PCB, interior nodes on two sides thereof, and power nodes coupled to the interior nodes by, for example, soldering. An overmold is applied to the PCB to expose the pins and the power nodes for electrically connecting with a mating connector.
An improved plug connector assembly is desired to offer advantages over the related art.

Durable plug connector assembly and method of assembling the same


A display substrate, a method for driving a display substrate and a display device are provided. The display substrate includes a display area, pixel units are arranged in the display area, the display area includes a first area and a second area which are arranged along a second direction, quantities of the pixel units arranged along the first direction in the first area are the same, and a quantity of the pixel units in any row in the second area is less than that of the pixel units in any row in the first area; the display substrate further includes a compensation area, a load compensation unit is arranged in the compensation area, the gate line in the second area and the data line in the first area extend to the compensation area, and the load compensation unit is coupled with the gate line and the data line.

A shape of a display screen may vary, for example, may be a rounded rectangle, or may have a special-shaped area. For a round-corner rectangular display screen, quantities of pixels of adjacent rows are different at a round-corner area; for a display screen with a special-shaped area, quantities of pixels of adjacent rows at the special-shaped area are different. A load of the row with a smaller quantity of pixels is smaller, a load of the row with a larger quantity of pixels is larger, charging time durations of the rows of pixels are different due to the fact that loads of the rows are inconsistent, a difference in current of adjacent rows of pixels is relatively large due to the fact that a difference between the charging time durations of the adjacent rows of pixels is relatively large, and when the difference in current exceeds a certain specification, a display brightness of the display screen is unevenness, and a display effect of the display screen is affected.

Display substrate, method for driving the same and display device

Chengdu BOE Optoelectronics Technology Co., Ltd.


A system and method of controlling the playback of the event stream information of a particular television channel by a digital video recorder (DVR). The DVR is a computer system configured with a hard drive and video decoder/encoder devices. The hardware environment of DVR (100) includes an input interface (102), tuner (105), MPEG-2 encoder (120), MPEG-2 decoder (110), external mass storage device (125), and a central processing unit (CPU) (135), internal memory (127), operating system (140), and event stream generator (250). The system and method of controlling the playback function of the present invention is primarily implemented within event stream generator (250). Event stream generator (250) generates a new video stream for playback onto the television by incorporating the broadcasted event stream information into the selected recorded video stream.

The introduction of videocassette recording devices (VCR) was one of the most important events in the history of television. Prior to the VCR people had little control over what they watch on their television. Prior to VCR's there was no such thing as video stores. Today VCR's are commonplace and are an integral part of the television watching activity. The VCR is merely a recording tool utilizing a blank cassette tape. In 1999, Digital Video Recorders (DVRs) hit the market providing television viewers recording capabilities far beyond the limits of the VCR. At the heart of the DVR system is a computer hard drive that stores television programs as digital files. Since the DVR internally stores digital files, the user is provided with more options with regard to the program recoding function and the program playback function.
In addition to the main content of a television program, many programs have a news ticker usually displayed at the bottom portion of the screen. The ticker provides up to date information about various news related items. The ticker event data is a continuous stream of text data embedded in the video stream and displayed on the lower portion of the television screen. Normally, ticker event data is used on popular news television stations such as CNN and ESPN. Currently the DVR records the television program and stores the ticker event data as part of the recording. At a later time, during the playback of the prior recorded video stream, the ticker event data is usually stale. As a result, the viewer has to watch tracker information that is already known and not of much use. Thus, what is needed is a method and system that displays the current ticker event data during the playback of the previously recorded video stream. This method and system should also have the capability of omitting a previously recorded stale ticker during the playback of the recorded stream.

Digital video recording device ticker playback system and method

International Business Machines Corporation


The present invention relates to a multi-lens camera that can be used for both 3-D photography and 2-D photography. When the camera is used in the 3-D mode, a series of slightly different two-dimensional images of the scene are exposed by all the taking lenses onto the film in the respective film planes in a half-frame format. When the camera is used in the 2-D mode, a wider frame image is exposed onto the film by one of the taking lenses. The negative is exposed in all film planes in the camera when used in the 2-D mode. When the camera is used in the 2-D mode, lens attachments change the angle of view of the taking lens and viewfinder.

1. FIELD OF INVENTION
The present invention relates to a camera that can be utilized for three-dimensional (3-D) photography and two-dimensional (2-D) photography.
2. PRIOR ART
In lenticular type three-dimensional (3-D) photography, a plurality of two-dimensional (2-D) views of the scene are taken from a number of horizontally-spaced vantage points and the series of 2-D images is then compressed and printed at the focal plane of each of the lenticules of the lenticular screen to form a 3-D composite image of the field.
In order to take a series of 2-D images at a number of vantage points, one generally takes one of two approaches: 1) using a single-lens camera to take one image at a time at each of the vantage points, or 2) using a multi-lens camera to simultaneously capture a series of 2-D views at one snap. Because the first approach requires special equipment which is usually expensive and bulky, a second approach is more practical for consumer uses.
Multi-lens cameras have been disclosed in a number of U.S. patents which include U.S. Pat. No. 4,800,407 (Lo) where the invention of 3-D cameras with three lenses is disclosed, and U.S. Des. Pat. No. 264,343 (Che) where the invention of 3-D cameras with four lenses is disclosed. Multi-lens cameras are currently available on the market.
The multiple images exposed by a multi-lens camera are a series of regular 2-D images of the same scene photographed at slightly different viewing angles. These regular 2-D images are necessary, as a group, for the composing of a 3-D print but anyone of them can also be used to produce conventional 2-D photographs. Logically, a multi-lens camera should be capable of being utilized as a 3-D camera or as a 2-D camera so that the consumer will not be required to have two cameras, one dedicated to 2-D picture taking and another dedicated to 3-D picture taking. However, all existing consumer 3-D multi-lens cameras adopt a half-frame negative format and this format cannot cover the same field of view normally covered by a full-frame format used in a regular 35mm full-frame camera.
3-D multi-lens cameras are designed to simulate the binocular vision of the human eyes. Therefore, in the design of a consumer 3-D multi-lens camera, the separation between the two endmost lenses must be kept roughly equal to or smaller than the separation distance between the eyes. This lens separation is used in order to assure a good 3-D effect and, at the same time, to avoid excessive parallax which causes a 3-D photograph to become out-of-focus. Since the eye separation distance of the average adult is between 63 and 70mm, the separation between the two endmost lenses in a consumer 3-D multi-lens camera is usually less than or equal to 70mm. This spacing varies depending on the number of lenses on the camera. Furthermore, as all consumer 3-D multi-lens cameras are designed to use a 35mm film, the format for each of the multiple images is about 18mm by 24mm or about half of the regular 35mm full-frame format. Under normal photographic conditions, this relatively narrow format is inadequate for covering the field of view normally covered by a full-frame 2-D camera.
It would be very advantageous for a consumer camera to be capable of exposing multiple images for 3-D photography and also provide a larger image format for 2-D photography. With such a design, the consumer will need only one camera for both 2-D and 3-D picture taking.

Dual-mode 3-D and 2-D camera with movable baffles


A tube and shell steam generator in which a series of rods having a diameter substantially equal to that of the heat exchange tubing in the tube bundle are placed on either side of the tube lane to buffer the flow in the tube lane from the heat exchange tubes to attenuate turbulent forces on the first several rows of heat exchange tubes adjacent to the tube lane.

1. Field
This invention relates generally to U-tube and shell steam generators and more particularly, to such generators that buffer the heat exchange tubes from the high velocity flow of recirculation fluid and feedwater within the tube lane.
2. Description of Related Art
A pressurized water nuclear reactor steam generator typically comprises a vertically oriented shell, a plurality of U-shaped tubes disposed in the shell so as to form a tube bundle, a tube sheet for supporting the tubes at the ends opposite the U-like curvature, a divider plate that cooperates with the tube sheet and a channel head forming a primary fluid inlet header at one end of the tube bundle and a primary fluid outlet header at the other end of the tube bundle. A primary fluid inlet nozzle is in fluid communication with the primary fluid inlet header and a primary fluid outlet nozzle is in fluid communication with the primary fluid outlet header. The steam generator secondary side comprises a wrapper disposed between the tube bundle and the shell to form an annular chamber made up of the shell on the outside and the wrapper on the inside and the feedwater ring disposed above the U-like curvature end of the tube bundle.
The primary fluid having been heated by circulation through the reactor enters the steam generator through the primary fluid inlet nozzle. From the primary fluid inlet nozzle, the primary fluid is conducted through the primary fluid inlet header, through the U-tube bundle, out the primary fluid outlet header and through the primary fluid outlet nozzle to the remainder of the reactor coolant system. At the same time, feedwater is introduced into the steam generator secondary side, i.e., the side of the steam generator interfacing with the outside of the tube bundle above the tube sheet, through a feedwater nozzle which is connected to a feedwater ring inside the steam generator. In one embodiment, upon entering the steam generator, the feedwater mixes with water returning from moisture separators. This mixture, called the downcomer flow, is conducted down the annular chamber adjacent the shell until the tube sheet located at the bottom of the annular chamber causes the water to change direction passing in heat transfer relationship with the outside of the U-tubes and up through the inside of the wrapper. While the water is circulating in heat transfer relationship with the tube bundle, heat is transferred from the primary fluid in the tubes to water surrounding the tubes causing a portion of the water surrounding the tubes to be converted to steam. To differentiate this steam/water mixture from the single phase downcomer flow, the fluid flow surrounding the tubes is designated as the tube bundle flow. The steam then rises and is conducted through a number of moisture separators that separate entrained water from the steam and the steam vapor then exits the steam generator and is typically circulated through a turbine to generate electricity in a manner well known in the art.
Since the primary fluid contains radioactive materials and is isolated from the feedwater only by the U-tube walls, the U-tube walls form part of the primary boundary for isolating these radioactive materials. It is, therefore, important that the U-tubes be maintained defect free by being well supported so that no breaks will occur in the U-tubes that will cause radioactive materials from the primary fluid to enter the secondary side, which would be an undesirable result. Support for the U-tubes is mainly accomplished by a plurality of transverse, spaced, tandem tube support plates that are positioned axially along the height of the tube bundle and through which the heat exchange tubes pass with their ends extending through and being affixed to the tube sheet. The holes in the support plates typically have lands that laterally support the heat exchange tubes, and lobes between the lands that permit the passage of the tube bundle flow and steam. However, tube wear has been reported at the tube support plates of steam generator units after extended periods of operation and possibly having tube and/or tube support plate fouling. The largest indications have a 28% depth. Of 79 total indications reported in one steam generator, 58, equivalent to 73% of the total number of indications, occur in rows 1-5 of the heat exchange tubes. Of these 79 total indications, 34% occur on row 1 tubes. Most of these occur at higher tube support plate elevations, where damping decreases and velocities are increased. These rows are adjacent to the tube lane region, centered between the tube hot and cold legs, and are subject to higher velocities and, thus, may experience turbulence-induced buffeting. It is well known that turbulence forces are attenuated rapidly within the first few rows of the heat exchange tubes, and the data evidences the presence of this phenomenon by the distribution of wear indications.
Accordingly, it is an object of this invention to reduce heat exchange tube wear at the tube support plates adjacent the tube lane in a tube and shell steam generator.
Furthermore, it is an object of this invention to reduce heat exchange tube wear within the vicinity of the tube support plates adjacent the tube lane without reducing the efficiency of the steam generator.
Additionally, it is an object of this invention to reduce heat exchange tube wear within the vicinity of the upper tube support plates within the first few rows of heat exchange tubes adjacent the tube lane.


In a circuit for generating timing of a reference plate line in the nonvolatile ferroelectric memory device, wherein a nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a first period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal to the reference plate line.

This application claims the benefit of Korean Application No. P2000-68112 filed on Nov. 16, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit for generating timing of a reference plate line in a nonvolatile ferroelectric memory device and a method for driving a reference cell. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving a sensing margin by stabilizing a reference level in the nonvolatile ferroelectric memory device.
2. Discussion of the Related Art
Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM), has a data processing speed equal to a dynamic random access memory (DRAM) and is able to retain data even in power off. For this reason, the nonvolatile ferroelectric memory has received much attention as a next generation memory device.
The FRAM and DRAM are memory devices having a similar structure, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic.
The residual polarization characteristic permits data to be maintained even if an electric field is removed.
FIG. 1 shows a hysteresis loop of a typical ferroelectric.
As shown in FIG. 1, even if the electric field is removed from the polarization induced by the electric field, data is maintained at a certain amount (i.e., xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states) due to a residual polarization (or spontaneous polarization).
A nonvolatile ferroelectric memory cell is used as a memory device by corresponding the xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states to xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99, respectively.
However, a related art ferroelectric hysteresis loop according to the related art reference cell operation has problems deviated from the hysteresis characteristics of the typical ferroelectric.
For a better understanding of the background technology, a cell array block, a main cell, and a reference cell of the nonvolatile ferroelectric memory device to apply a driving method of a reference cell will be explained hereinafter.
FIG. 2 shows a schematic diagram of a cell array block according to a nonvolatile ferroelectric memory device applicable to a driving method of a reference cell.
FIG. 3 is a schematic diagram of a main cell of FIG. 2, while FIG. 4 is a detailed circuit diagram of a reference cell of FIG. 2.
The cell array block includes a plurality of sub cell arrays. A sensing amplifier S/A is formed between adjacent top and bottom sub cell arrays sub_T and sub_B.
Each of the sub cell arrays includes bit lines Top_B/L and Bot_B/L, a plurality of main cells MC connected to the bit lines Top_B/L and Bot B/L, a reference cell RC connected to the bit lines Top B/L and Bot_B/L, and a column selector CS.
The reference cell RC within the top sub cell array sub_T S/A is simultaneously accessed when the main cell MC within the bottom sub cell array sub_B is accessed.
Similarly, the reference cell RC within the bottom sub cell array sub_B is simultaneously accessed when the main cell MC within the top sub cell array sub_T is accessed.
The column selector CS selectively activates a corresponding column bit line using Y (column) address.
If the column selector CS is in high level, the corresponding bit line is connected to a data bus, so as to enable a data transmission.
The main cell MC is constructed as shown in FIG. 3. A bit line B/L is formed in one direction, and a wordline W/L is formed to cross the bit line B/L. A plate line P/L is spaced apart from the wordline W/L in the same direction as the wordline W/L. A transistor T is formed with a gate connected to the wordline W/L and a source connected to the bit line B/L. A ferroelectric capacitor FC is formed in such a manner that a first terminal is connected to a drain of the transistor T and a second terminal is connected to the plate line 2/L.
The respective reference cell is constructed as shown in FIG. 4.
As shown in FIG. 4, the reference cell of the nonvolatile ferroelectric memory device includes a bit line B/L formed in one direction, a reference wordline REF_W/L formed across the bit line B/L, a switching block 51, a level initiating block 52, and a plurality of ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , and FCn. The switching block 51 is controlled by a signal of the reference wordline REF W/L to selectively transmit a reference voltage stored in the ferroelectric capacitors to the bit line B/L. The level initiating block 52 selectively initiates a level of an input terminal of the switching block 51 connected to the ferroelectric capacitors. The ferroelectric capacitors are connected to the input terminal of the switching block 51 in parallel.
The switching block 51 includes an NMOS transistor (hereinafter, xe2x80x9cfirst transistorxe2x80x9d) T1 with a gate connected to the reference wordline REF_W/L, a drain connected to the bit line B/L, and a source connected to a storage node SN.
The level initiating block 52 is controlled by a reference cell equalizer control signal REF_EQ which is a control signal for initiating the storage node SN of the reference cell. Also, the level initiating block 52 includes an NMOS transistor (hereinafter, xe2x80x9csecond transistorxe2x80x9d) T2 connected between the source of the first transistor T1 and a ground terminal Vss.
The plurality of ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , and FCn include first and second electrodes, and a ferroelectric material formed between them. The first electrode of the ferroelectric capacitors is connected to the source of the first transistor T1, and the second electrode is connected to the reference plate line REF_P/L.
Herein, the number of the ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , and FCn is determined by the capacitor size of the reference cell. Thus, the number of the ferroelectric capacitors can freely be adjusted by changing the capacitor size of the reference cell.
The storage node SN is connected with first terminals of the ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , and FCn in parallel.
The reference cell equalizer control signal REF_EQ initiates the storage node SN to a ground voltage level. Namely, if the reference cell equalizer control signal REF_EQ is in high level, the second transistor T2 is turned on so that the storage node is maintained at a ground voltage level.
Operation of the aforementioned reference cell will now be described.
Qs and Qns of hysteresis loop in FIG. 1 denote switching charges of the ferroelectric capacitor, and non-switching charges of the ferroelectric capacitor, respectively. The reference cell of the present invention is based on Qns.
That is, the reference wordline REF_W/L within the operation cycle is transited to high level together with the reference plate line REF_P/L. Accordingly, charges equivalent to Qns X the size of ferroelectric capacitor are supplied to the bit line B/L.
At this time, the reference wordline REF_W/L is transited to low level before the sensing amplifier S/A is operated, so that the reference cell is not affected by a voltage of the bit line B/L.
Meanwhile, the reference plate line REF_P/L is maintained at high level, and transited to low level when the reference wordline REF_W/L is sufficiently stabilized to low level.
Since non-switching charges Qns are used, a separate restoring operation is not required during a precharge period. Accordingly, high level is no longer required in the reference wordline REF_W/L.
Since the reference level is affected by an initial level of the storage node, the second transistor T2 of FIG. 4 is used to stabilize the storage node, and the reference equalizer control signal REF_EQ is used to initiate the storage node to the ground voltage level.
Therefore, since the initial level of the storage node is maintained at the ground voltage level, the reference level can be stabilized.
Hereinafter, a hysteresis characteristic of the related art ferroelectric and a driving method of the reference cell of the related art nonvolatile ferroelectric memory device will be explained with reference to FIG. 5 and FIG. 6.
FIG. 5 shows a hysteresis characteristic of the related art ferroelectric, while FIG. 6 is a timing chart illustrating the operation of the related art reference cell.
The related art operation timing chart of the reference cell will be described as follows.
As shown in FIG. 6, an operation cycle begins when a chip enable signal CEBpad is transited to low level, so that active periods A, B, and C are formed. A precharge period D begins when the chip enable signal CEBpad is transited to high level. One cycle is completed by passing through the precharge period D.
If an active period of a chip begins, an address is decoded during the periods A and B. Also, all control signals are activated, and the reference wordline REF_W/L and the reference plate line REF_P/L are transited from low level to high level.
The reference cell data are transmitted to each bit line as the reference wordline REF_W/L and the reference plate line REF_P/L are transited from low level to high level in the period C.
The reference plate line REF_P/L is transited to low level in the precharge period D. Accordingly, a voltage is not applied between both electrodes of the ferroelectric capacitors of the reference cell as the reference plate line maintains low level in the rest of the precharge periods.
At the moment that the reference plate line REF_P/L is transited from high level to low level, the reference plate line is transited from xe2x80x98axe2x80x99 state to xe2x80x98bxe2x80x99 state as time passes.
Therefore, a non-destructive charge is charged between Qns and Q""ns depending on how much time has passed since the reference plate line REF_P/L is transited from high level to low level.
Since the non-destructive charge is not constant, the reference bit line REF_B/L level maintained by the non-destructive charge is also changed.
Accordingly, since the reference level is not constant and varied due to the Qns and Q""ns, a sensing margin is reduced. This is because that the ferroelectric capacitor is damaged during an annealing process for a long time at a high temperature.
However, the aforementioned reference driving method of the related art nonvolatile ferroelectric memory device has the following problems.
Since the non-destructive charge is not constant, the reference bit line level is also changed. As a result, the reference level is not constant and changed due to Qns and Q""ns, thereby reducing a sensing margin.
Accordingly, the present invention is directed to a circuit for generating timing of a reference plate line in a nonvolatile ferroelectric memory device and a method for driving a reference cell that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a circuit for generating timing of a reference plate line in a nonvolatile ferroelectric memory device and a method for driving a reference cell that improves a sensing margin by stabilizing a reference level.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in a circuit for generating timing of a reference plate line in a nonvolatile ferroelectric memory device, wherein the nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a certain period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal to the reference plate line.
In another aspect of the present invention, in a method for driving a reference cell of the nonvolatile ferroelectric memory device, wherein the reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and a reference plate line, the method includes transiting a chip enable signal from high level to low level by an external control signal, and activating the reference plate line to low level for a first period where the chip enable signal is transited to low level, and activating the reference wordline to high level for a second period where the reference plate line is transited from low level to high level while the chip enable signal is activated to low level.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Circuit for generating timing of reference plate line in nonvolatile ferroelectric memory device and method for driving reference cell


Systems and methods are provided to facilitate an analysis of a commercial mortgage backed security portfolio. According to one embodiment, base information associated with the portfolio is determined. Information associated with an additional mortgage loan to be added to the portfolio is then determined, and a loan spread is calculated for the additional mortgage loan in accordance with a contribution of the additional mortgage loan to the portfolio. For example, a real time pricing server may calculate the loan spread based on a desired profitability associated with the additional mortgage loan.

A Commercial Mortgage Backed Security (CMBS) is a bond or other financial obligation associated with a pool or "portfolio" of mortgage loans secured by commercial assets (e.g., a hotel or office building). A CMBS portfolio is typically divided into a number of different credit rating categories, with certain categories being, by design, less likely to suffer defaults (e.g., a CMBS portfolio may have a less risky "AAA" category and a more risky "AA" category). Each of these credit rating categories is associated with a category size. For example, a CMBS portfolio may have a "AAA" credit rating category with a size of 75% (i.e., 75% of the total portfolio assets are in the "AAA" category), a "AA" category with a size of 15%, and a "A" category with a size of 10%.
Note that different credit rating categories may be associated with a different loan "spreads" representing the difference between an interest rate paid to investors and a known index (e.g., a number of basis points between the interest rate paid to investors and the rate currently associated with, for example, a ten year US treasury note). A less risky credit rating category will generally have a lower loan spread while a more risky category will have a higher loan spread.
Each loan in the CMBS portfolio is also associated with a loan spread, with a higher loan spread indicating a higher profitability of the loan. When creating a CMBS portfolio, the value or profitability of a loan that might be added to the portfolio is often of interest. That is, the loan spread that will be required to produce a desired level of profitability may need to be determined. Because CMBS portfolios can be associated with a significant amount of capital (e.g., $800 MM), an accurate and timely determination of this information is important.
This type of calculation, however, can be very complex (e.g., because different loans that might be added to a CMBS portfolio may effect the overall credit rating category sizes in different ways) and time consuming. Unfortunately, the calculation may need to be performed frequently (e.g., on a daily basis) because some of the variables that effect the relationship between the loan spread and the profitability of the loan constantly change (e.g., treasury rates, investor opinions, and competition in the CMBS market). Moreover, the calculation may need to be performed for a significant number of different property types (e.g., associated with different commercial assets securing additional loans) and risk parameters (e.g., debt service coverage ratio information and loan to value information). All of these factors can make the accurate and timely determination of an appropriate loan spread difficult.

Systems and methods to facilitate analysis of a commercial mortgage backed security portfolio based on a contribution of an additional mortgage loan


The device for heating by electromagnetic induction of a metal strip (A) comprises at least one inductor coil (B) which surrounds an area of the strip in a transversal manner in relation to the longitudinal direction of the strip. The coil (B) comprises at least one monoturn (1) whose median plane (P) is orthogonal in relation to the longitudinal direction (D) of the strip.

Such a heating device is used for example in metal strip treatment lines, especially for drying a coating, such as a layer of paint, or for heating prior to galvanizing, or heating prior to annealing, applied to this strip, which runs through the induction coil or coils along its longitudinal direction.

Device for heating by induction of metal strip


A vehicle backlit panel includes a base substrate, an electroluminescent element and an outer substrate. The electroluminescent element is disposed on one side of the base substrate. The outer substrate overlies the electroluminescent element. The outer substrate includes a translucent substrate portion having areas of different thicknesses as measured in a direction of illumination through the outer substrate to form a three-dimensional graphic image with a three-dimensional appearance resulting from different translucency levels of the areas of different thicknesses.

1. Field of the Invention
The present invention generally relates to a vehicle backlit panel. More specifically, the present invention relates to a vehicle backlit panel having an electroluminescent element that provides backlighting to an outer substrate formed with a three-dimensional image.
2. Background Information
Vehicles are typically provided with various types of decorative trim portions, such as real wood finishes on doors or radio bezels with chrome laminated film trim. Such trim portions are not noticeable in darker conditions.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for improved decorative elements that are visually appealing and that can be illuminated. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.

Nissan Technical Center North America, Inc.


Nanoparticles to treat autoimmune diseases and HIV infection are provided. The nanoparticles comprise a biocompatible polymer and a complex, wherein the complex is a major histocompatibility complex (MHC) class I antigen E (HLA-E) linked to a peptide, and wherein the HLA-E-peptide complex is linked to the surface of the nanoparticle. The present invention also relates to methods for treating autoimmune diseases and HIV infection.

Achieving a balance between induction of protective immunity against pathogens and maintenance of self-tolerance is a central feature of the adaptive immune system. Although negative selection in the thymus removes the majority of clones that express T cell receptors (TCR) with high affinity for self-peptide MHC products, this process is incomplete. A significant fraction of mature peripheral T cells that respond to self-peptide-MHC complexes may differentiate into effector cells in the context of inflammatory stimuli (Bouneaud et al., 2000; Goldrath and Bevan, 1999; Slifka et al., 2003). Although this process is constrained by abortive or defective TCR signaling resulting in cellular elimination (AICD) or inactivation (Martin et al., 1999; Kearney et al., 1994), these cell-intrinsic mechanisms may not suffice to prevent the development of autoimmune disorders (Anderton et al., 2001; Panoutsakopoulou et al., 2001). There is increasing evidence that self-tolerance may also depend on inhibitory interactions between effector T cells and regulatory or suppressive cells (Littman and Rudensky, 2010). A regulatory subset of CD8+ T cells, termed CD8+ Treg cells, has been found to inhibit follicular T helper cell responses, which are essential for production of autoantibodies and formation of ectopic germinal centers (GC). However, the potential contribution of CD8+ Treg cells to the pathogenesis and treatment of autoimmune disease is not well understood. Due to the severity and breath of autoimmune diseases such as lupus and rheumatoid arthritis, there is a great need for effective treatments of such diseases.

Targeted expansion of Qa-1-peptide-specific regulatory CD8 T cells to ameliorate arthritis


The present invention provides for facilitating synchronization in a data source/data destination environment using data replicas. When a plurality of destinations request synchronization with a source, a first destination selected for synchronization is processed such that differences between the first destination data and source data is determined and persisted in a partition update. After updating the first destination, the synchronization process continues only for those remaining destinations that will be affected by the partition change, as determined by the persisted data, and then as updated by the persisted data.

The advent of global communication networks such as the Internet has facilitated widespread dissemination of information through corporate enterprise(s) in the form of disparate databases typically utilized by separate corporate entities or branch-offices at various geographic locations. Merging such heterogeneous data sources into a homogeneous database heretofore poses a significant system-intensive process that results in duplication of many system processes.
Disparate databases can be converged by means of replication—replication is a process that copies and distributes data and database objects from one database to another, and then synchronizes information between the databases for consistency.
Merge replication is a difficult replication type. Merge replication capability enables disconnected and mobile users to run applications offline, and then periodically reconnect to synchronize with a main database. It makes possible autonomous changes to replicated data on a source (also called a publisher) and on a destination (also called a subscriber) while connected or disconnected, and then merging the updates between sites when the sites are connected. With merge replication, a server captures incremental data changes in the source database and in the destination database, and reconciles conflicts according to preconfigured rules or via employing a custom resolver to resolve the conflicts.
Merge replication is typically used in support of autonomous changes of replicated data at the source and/or destination. The data is synchronized between servers either at a scheduled time or on demand. Updates are made independently (e.g., no commit protocol) at more than one server; so same data can be updated by the source or by more than one destination. Consequently, conflicts can occur when data modifications are merged. Merge replication includes default and custom choices for conflict resolution that can be defined when a merge source is configured. When a conflict occurs, a merge agent invokes the conflict resolver to determine which data will be accepted and propagated to other destination sites. Options available with merge replication include filtering source data horizontally and vertically, including employment of join filters and dynamic filters, using alternate synchronization partners, optimizing synchronization to improve merge performance, validating replicated data to ensure synchronization, and utilizing attachable subscription databases.
Merge replication supports horizontal, dynamic, and join filtering, all of which enable an administrator to create partitions (or tables) of data to be replicated. Filtering of replicated data allows for at least the following: a minimization of the amount of data sent over a network; reduction in the amount of storage space required at a destination replica; customization of data sources and applications based upon individual destination replica requirements; and avoidance or mitigation of conflicts because the respective data partitions can be sent to different destination replicas. Even though merge replication allows multiple replicas to update the same data, filtering of the data such that replicas receive disjoint sets, ensures that no two replicas to a single destination will be updating the same data values.
Traditionally, merge replication has supported techniques to keep a partition of a source replica consistent with a destination replica. However, existing algorithms introduce significant performance degradation of a system by requiring concurrent synchronization sessions between the source and destination replicas. In conventional servers, merge replication has had to support very sophisticated partitioning techniques to allow destination replicas to receive only a subset of the data of the source replica. These techniques require a high number of CPU cycles at the source replica, and thus create a bottleneck for expanding a network by increasing the number of simultaneous synchronizations required for maintaining destination database replication. Intensive hardware and software processor functions are associated with "partition computation" algorithms that prepare a list of changes needed to keep the partition of the destination replica consistent with that of the source replica.
Under a conventional partition computation approach, when a client requests database synchronization with a server, the partition computation function of the server includes computing the partition membership of rows that have not been synchronized in order to determine differences between the two databases. Since the client database is typically a subset of an overall database residing on the server, the computation function further includes reviewing substantially all current changes at the source replica that may potentially need to be propagated to the destination replica, and then determine which of those changes are relevant to the destination replica. For instance, rows that qualify according to the destination replica filter criteria belong to the destination replica and must be updated or inserted at the destination replica. Rows that have undergone updating and no longer satisfy the filer criteria, no longer belong to the destination replica and hence, must be deleted. This implies that an update at the source replica could be propagated as a delete operation to the destination replica. Further, rows that have undergone updating and now belong to the destination replica may need to be expanded, if there are join filters, to obtain the related rows from the joined tables.
Some negative aspects from a performance and scaling point of view of the "per synchronization session partition computation" approach are as follows. Conventional systems are burdened with redundant processing, since for every change, irrespective of whether there is partition update or not, a conventional synchronization session needs to evaluate whether the changed row belongs to the destination replica or not. If a row changes before each synchronization session, every subsequent synchronization session evaluates again, whether that row belongs to the destination replica, by establishing new partition membership metadata for that row. The knowledge about a row's previous partition membership is not remembered between synchronization sessions. This leads to redundant processing for each synchronization session. To illustrate the process intensive aspects of the conventional system by example, consider a network with one thousand destination replicas. If a row is determined by the source to have undergone a change and requires publication to the destinations, the one thousand destination replicas synchronize to be more up-to-date. If the row changes again, another one thousand synchronization sessions follow, and this process is repeated until the row has changed one thousand times. In the end, all of the synchronization sessions will have executed a combined total of one million partition computation functions for the same row.
Conventional systems exhibit poor concurrency behavior; since for every row change, each destination replica is required to perform its own evaluation. In the presence of multiple simultaneous synchronizations between the source and destination systems, there will be multiple instances of the partition computation executing simultaneously, causing high CPU consumption in the source server.
The partition computation algorithm that prepares the list of changes needed to keep the partition of the destination replica consistent with that of the source replica tends to be the most CPU and query processor intensive functions that are executed in any given synchronization session. If the filtering used to define the set of replicated data were not optimal, the performance of concurrent partition computation functions would further degrade the capabilities of the source server.
Faster hardware and more efficient replication configuration can address this issue to a certain degree. But even in a perfectly designed and tuned application, every Publisher server has an upper limit with respect to the number of simultaneous Subscriber merge processes it can handle effectively.
One solution to this problem is to coordinate the timing of the source merge processes so that the processes are staggered. If all destinations currently connect at the beginning or end of their work day to merge changes, merge processes can be required to be performed at off-peak times during the day. If there is no control over when destinations perform merge processes, an upper limit can be defined to limit the number of destination that are allowed to merge at the same time.
Another way to reduce the demands on a source server is to spread processing load across more sources. A common technique is to use several servers in a republishing hierarchy. For example, if a single server currently acts as a source for all sales representatives in the country, two more source servers could be added to distribute the load associated therewith, wherein a Central Publisher publishes data to East and West Subscribers, an East Subscriber republishes data to the sales representatives on the East coast, and a West Subscriber republishes data to the sales representatives on the West coast.
However, none of the conventional solutions provide a cost effective and efficient architecture for addressing the problem associated with a large number of synchronizations. Conventional systems propagate irrelevant metadata over the network. Since there is no persisted membership metadata even after synchronization sessions have computed partitions, all changes at the source replica will be considered relevant for propagation to the destination replica. This approach contributes to the scaling problem, since the list of changes to be considered grows if a large number of destination replicas propagate changes to the source replica. Moreover, if the source replica records any additional metadata during one synchronization session with a destination replica, there might be a need to propagate this metadata to other destination replicas. Hence, the scaling characteristics of the current approach are less than desirable. There is a need in the art to minimize the amount of metadata that is considered and propagated over the network during the synchronization session. Based upon deficiencies in the prior art to support many concurrent synchronizations sessions, there is a need to eliminate expensive partition computation functions during the execution of every synchronization session.

Architecture for partition computation and propagation of changes in data replication


A scrubber attachment for spray nozzles or sprayer heads provides for the offset attachment of the scrubber portion from the spray nozzle. The attachment may be easily and quickly installed on existing spray nozzles in order to provide for mechanical scrubbing of dishes and other utensils, in addition to the water spray provided by the spray nozzle. As the scrubber portion is radially offset from and does not completely surround the outflow of the nozzle, the scrubber can be made of relatively dense, firm and semi-porous material in order to achieve better scrubbing action than would be attained by the standard concentric brush or sponge with which such spray nozzles are generally equipped.

Dishwashing is generally considered to be an onerous task. It can be especially difficult and tedious to clean dishes and related utensils thoroughly and completely, especially when burned, dried or other hardened residue has become stuck to the utensils. As a result, numerous devices have been developed to assist in the cleaning of dishes, silverware and related cooking utensils and articles, such as automatic dishwashers.
However, for various reasons (e.g., lack of space) many persons have installed a spray nozzle or spray head connected by means of a hose to an existing water supply at a kitchen sink, in order to ease the burden of dishwashing. While these devices provide some advantage over other manual dishwashing systems, they are still limited by the water system pressure and the maximum water temperature which can be withstood by the user of the device. As a result, it can be difficult to remove residue which is stuck to eating or cooking utensils when cleaning such utensils with such a sprayer.
Due to the above limitations, it has been found that a fair amount of additional mechanical scrubbing must often be used to remove hardened deposits which have stuck to the various utensils. Accordingly, many devices have been developed to provide this function in combination with a spray nozzle. However, most of these devices include a brush or scrubbing device as an inseparable part of the spray nozzle. Of those few scrubbing or brushing devices which are removable from the nozzle, all impede at least some of the water flowing from the nozzle and thus require a fair amount of porosity in order to allow for the flow of water therethrough. Accordingly, they must be relatively soft and pliable and are thus limited in their ability to remove hardened materials mechanically from utensils.
The need arises for a scrubbing device which is attachable to an existing spray nozzle or spray head, which provides sufficient mechanical strength to remove stuck deposits readily from cooking and eating utensils. The device must be attached in a manner which does not appreciably block any of the outflow from the nozzle in order to provide adequate flow during the washing operation.