A semiconductor device (100) including a die (110) electrically connected to a substrate (120), wherein the substrate has a novel interconnect routing structure. The routing structure has a plurality of interconnects (122) including a plurality of intermediate vias (140), including both intermediate vias associated with supply interconnects and signal interconnects, that are clustered together to reduce undesirable mutual loop inductance (L.sub.m) and reduce switching noise (.DELTA.I). A plurality of first printed wires (128a) and a plurality of second printed wires (128b) may incorporated in the substrate for routing of the plurality intermediate vias in cluster form. The substrate may have a plurality of clusters of the intermediate vias.

As is known in the art, modern semiconductor packages take on various forms, including pin grid arrays (PGAs), ball grid arrays (BGAs), die-scale packages (CSPs), etc. In such types of packages, the semiconductor die may be flip-chip mounted to a substrate, wherein the active surface of the semiconductor die is bumped and bonded to an underlying substrate, and wire-bonded to the substrate, wherein bond pads formed on the active surface of the substrate are connected to conjugate bond pads on a substrate via wire-bonds. The substrates for such types of packages may take on various forms, including ceramic, plastic, and metal having an insulating coating (so called "metal core substrates"). As is known in the art, the substrate includes a plurality of interconnects that electrically interconnect die terminals to respective substrate terminals, the substrate terminals being arranged in an array fashion at a relatively large pitch for electrical connection to a printed circuit board, for example. This type of structure is more clearly shown in connection with FIG. 1, described below.
FIG. 1 depicts a packaged semiconductor device 1 including semiconductor die 10 which is provided on and electrically connected to substrate 20. As is known in the art, the semiconductor die 10 includes a semiconducting substrate, such as doped silicon, on which is formed a plurality (i.e., literally thousands) of transistors. A plurality of dielectric layers and higher-level metal layers are lithographically defined and deposited on the semiconducting substrate so as to form a complete semiconductor die, which is coated with a passivation layer. The particular details of the semiconductor die are known in the art and are not essential for an understanding of the structure shown in FIG. 1. Semiconductor die 10 includes a plurality of die terminals 12 that electrically connect the semiconductor die 10 to the substrate 20. The die terminals 12 are formed to overlie an active surface of the die. The die terminals shown include die pads 14, on which are formed solder bumps 13 by the known Controlled Collapse Chip Connection (C4) technology. The die terminals 12 are electrically connected to substrate pads 21. The die pads 14 include signal pads 14a (also known as I/O pads), power pads 14b, and ground pads 14c, the power and ground pads 14b and 14c collectively forming supply pads.
The die terminals 12 provide electrical and mechanical connection by reflow of the solder material of the solder bumps 13 with a flux so as to provide electrical connection between the semiconductor die 10 and the substrate.
Turning to the substrate 20, a plurality of interconnects 22 are provided to effect electrical connection between the die terminals 12 and substrate terminals 30. The interconnects include signal interconnects 22a, power interconnects 22b, and ground interconnects 22c. The power and ground interconnects 22b and 22c are generically referred to as supply interconnects. Each interconnect 22 includes die-scale vias 24 which are connected to respective printed wires 28, and to respective package-scale vias 26. The die-scale vias 24 are arranged at a pitch corresponding to the pitch of the die terminals 12, which is a relatively fine pitch. The printed wires 28 are provided in respective layers of the substrate, and serve to fan-out electrical connection to package-scale vias 26, which are arranged at a pitch greater than die-scale vias 24. In the structure shown in FIG. 1, the substrate is formed of a plurality of ceramic layers, wherein the printed wires 28 are formed on respective ceramic layers, and vias 24 and 26 are lithographically defined and formed. The printed wires 28 take the form of printed lines when formed as a component of a signal interconnect 22a, but take the form of ground planes and power planes when used in connection with ground interconnects and power interconnects, 22b and 22c, respectively.
Substrate terminals 30 include signal terminals 30a, power terminals 30b, and ground terminals 30c. Power terminals 30b and ground terminals 30c are collectively described as supply terminals. In the structure shown in FIG. 1, the substrate terminals 30 include landing pads 32, having associated solder balls 34 for electrical connection to a printed circuit board.
The present inventor has recognized numerous shortcomings with the prior art semiconductor device depicted in FIG. 1. Particularly, it has been found that the substrate is responsible for a certain degree of switching noise, caused by relatively high mutual loop inductance (L.sub.m) between supply interconnects and signal interconnects. Accordingly, a need exists in the art to provide an improved packaged semiconductor device, particularly, an improved interconnect structure of a substrate of the packaged semiconductor device, for reducing mutual loop inductance (L.sub.m).

Semiconductor device including a substrate having clustered interconnects


Device for shaping a laser beam for an atomic sensor, comprising a retroreflector prism with an entrance area, an exit area and two reflection surfaces forming a right angle therebetween. The device for shaping includes a linear polarizer disposed upstream from the entrance area of the retroreflector prism for linearly polarizing a laser beam entering into the retroreflector prism by the entrance area, and a form birefringence plate disposed downstream from the exit area of the retroreflector prism to circularly polarize a laser beam exiting from the retroreflector prism by the exit area.

The atomic sensors are in particular atomic clocks, micro-magnetometers and even micro-gyrometers. Such atomic sensors may, for example, be intended for telecommunication, navigation and defense systems.
Such sensors are sometimes described as "micro-atomic clocks", "micro-magnetometers" and "micro-gyrometers". Throughout the text, the term "micro" must be understood in the context and with the meaning indicated.
The operation of these atomic sensors rests on optical spectroscopy of gas atoms filling the cavity provided with an optical window. The gas is usually an alkaline vapor, such as cesium or rubidium. With this spectroscopy, one or more spectral quantities can be measured associated with the one or more physical quantities that the sensor observes, for example a frequency, temporal period, magnetic field or acceleration.
Such atomic sensors are attractive because they are small, energy-efficient and have very good measurement precision and stability.
A typical atomic sensor according to the invention is a chip-scale atomic clock, known under the acronym CSAC. One such example is the CSAC called SA.45s from Microsemi which has a volume of 16 cm3, a mass of 35 g and requires only 120 mW power.
In the case of a micro atomic clock, the operation of the sensor is usually based on the measurement of the frequency of a specific microwave transition of the atoms of the gas, called clock transition and uses the principle of atomic resonance for coherent population trapping, known under the acronyms CPT.
Such a micro atomic clock is also known from the work of the Mac-TFC consortium, the FEMTO-ST (acronym for Franche-Comté Electronique Mecanique Thermique et Optique—Sciences et Technologies) which developed a very compact (a few mm3) cesium vapor cell, with MEMS micro-machining (acronym for Micro-ElectroMechanical Systems) with silicon and anodic welding (see for example "New Approach of Fabrication and Dispensing of Micromachined Cesium Vapor Cell" by L. Nieradko, C. Gorecki, A. Douahi, V. Giordano, J. C. Beugnot, J. Dziuban et M. Moraja Published in the JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, August 2008). Such a cell has an optical window diameter of about 2 mm.
The cell has an architecture referred to as "transmissive", where the laser, a vertical cavity laser known under the acronym VCSEL (for Vertical Cavity Surface Emitting Laser), and photodetector, (photodiode) are located on either side of the cell itself, with the laser beam passing through it from one side to the other, entering it by the first glass cover and exiting it by the second glass cover.
The beam coming from such a vertical cavity laser is characterized by relatively small divergence (FWHM of) 10-15°) and size (of order 20 μm near the exit mirror).
Thus, the distance required for reaching a beam diameter corresponding to the optical window of the cell and allowing lighting all of the atoms, if possible with equivalent intensities (uniform illumination), is therefore high if no additional device is added; this limits the minimum size of the atomic sensor.
To do that, in the context of the MAC-TFC Consortium, a telescopic system was developed with which to increase the divergence of the beam and to collimate the beam before entry thereof into the cell.
The bulk can be reduced with such a solution but it implies an alignment of several optical components which is a delicate operation at the dimensions of the cell.
Another solution is in particular known from the document U.S. Pat. No. 7,619,485 and shown in particular on FIG. 6 from that document. This solution consists of folding back the laser beam coming from the vertical cavity laser using mirrors or a prism but without changing the divergence values of the beam.
With such a solution several alignment constraints can be overcome. In fact, unlike lenses, poor positioning of the folding system (in translation) is no more harmful than would be the same positioning error of the source or the cell.
In this respect, using a prism is attractive compared to dielectric mirrors (also having low absorption) for providing excellent control of the orientation of the reflecting surfaces. In fact, the angular tolerance is in general specified at ±15 arcsec (±0.004°) even for prisms of a few millimeters on edge.
However, spectroscopy on the alkaline vapor by coherent population trapping requires a laser beam entering the cell with circular polarization.
Further, reflections of the laser beam in the prism can substantially change the polarization of the laser beam. In fact, even if the light beam does not leave the prism when the angle of incidence is greater than the critical angle defined above (i.e. there is no energy flux through the optical surface), the electromagnetic field on the other hand slightly enters into the exterior medium, with various penetration depths depending on the orientation of the electric field (parallel or perpendicular to the plane of incidence). The two components of the laser beam experience different phase shifts, a linearly polarized laser beam will for example become elliptically polarized after a total reflection. The article "Polarization properties of retroreflecting right-angle Prisms" by A. M. A. Azzam that appeared in the journal Applied Optics, vol. 47, p. 359 (2008) in particular describes this phenomenon in more detail.
Thus there is a need for a laser beam shaping device guaranteeing a size and controlled polarization of a laser beam at the entrance to the cell of an atomic sensor. Also there is a need for a device which has a limited power loss from the laser beam during shaping. Finally, there is a need for such a device which is the smallest possible and whose fabrication and integration into an atomic sensor is easy, in particular by limiting the number of constraining optical alignments to be implemented.

Device for shaping a laser beam for an atomic sensor having retroreflector prism, linear polarizer, and form birefringence plate

CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE—CNRS


A unit and a method of programming mounted programmable memories by a programming boundary scan component/unit being directly coupled to the programmable memory and directly coupled to a boundary scan test system. Directly coupling the memory to the programming boundary scan component Thereby eliminates having to serially clock information to and from the programmable memory through a number of other boundary scan components/units. The drive routines for programming the programmable memory by means of a boundary scan test system only needs to be modified as to the length of the serial boundary scan cell chain.

The methodology of programming programmable memories, such as proms, eproms, eeproms, and flash memories, has changed through the years. In the beginning programmable memories were programmed in a special apparatus, a prom programmer, before the programmable memory was mounted on a circuit board it was meant to operate on. During approximately the same time period, circuit boards were first tested as to their electrical copper tracks, and then after all components had been mounted, their functionality was tested by placing the circuit boards in different test jigs. This type of testing, referred to as in-circuit tests, where components were contacted via bed-of-nail fixtures, has become more and more difficult to realize due to increased complexity. This prompted a replacement of physical contacting via nails with design-integrated pin electronics, electronic nails. An IC's functional core logic is isolated by having scan cells integrated directly on the silicon boundary, functionally commonly between the IC's functional core logic and the IC's physical pins. Scan cells can thus either be transparent, i.e. functionally removed, or intercept outgoing and incoming signals to and from physical pins or the core logic. Further, the scan cells are serially coupled together in a scan cell chain. Scan cells are available in various types, such as capture cells for measurements only and universal cells for measurements and stimulation, and comprises a number of clocked latches.
The scan cells' line interconnection, the scan cell chain, allows test vectors to be serially shifted on to the IC's physical pins as well as allowing scanning and shifting out of externally applied information. Standard IEEE 1149.1 defines a uniform, chip-internal test control logic as well as a standardized bus interface, a testbus. The testbus only needs four lines, with an optional fifth reset line, for complete control. Using this boundary scan architecture, manufacturing faults such as opens, shorts and misplacements are easily detected and localized. The potential of the boundary scan architecture has expanded its fields of application to also include in-system programming of programmable memory devices. A circuit board can thus be manufactured with all components mounted, including programmable memories, and then be tested and programmed for use. Which means that first when a circuit board has to be delivered, its programmable memories are programmed with the latest upgraded software.
Unfortunately as memory sizes increase so does the programming time. Attempts have been made to come to grips with these ever-increasing programming times, for example by increasing the serial clock rate of the boundary scanning. This method of decreasing the programming times is unfortunately heavily dependent on the boundary scan components and their maximum clock rate, and the boundary scan test system's maximum clock rate. There is still room for improvement on how to decrease programming times in a boundary scan environment.

Method and a unit for programming a memory


A cushioning corner pad is placed on the corners of furniture or the like to protect it during shipment. The corner pad is die-cut, prescored, and folded from a single piece of corrugated paper board to a three-dimensional form consisting of three connected triangular hollow cells which fit the corner of the article to be protected. The thickness of the cells, and thus the corner pad, is determined by sections which are perpendicular to, and sections diagonal to, the parallel sides of each of the connected cells when folded. The corner pad is thus hollow and fits over the corner of an artical with a cell adjacent to each side of the corner.

This invention is a corner protector for use in the shipping of an item, such as furniture or a speaker cabinet, which when applied to the corners of the item being shipped and placed in a shipping carton protects the corners of the item and holds the item intact during shipment.
Before this invention, corner protectors made of several layers of corrugated material construction, corner protectors of a single face laminated built-up construction, or a corner protector made of a pre-formed molded synthetic resin foam construction, had been applied to the corners of items such as furniture or speaker cabinets for shipping protection. In the case of the layered corrugated material, the item frequently broke or was damaged when dropped, due to its high rate of energy transfer. The latter two corners had a tendency to crush or break during shipment thus resulting in the item being loose inside the shipping container and leaving it vulnerable to further damage. When this happened, the stacking capability of the loosened items within their shipping container was diminished. There has been a need for a corner protector which could balance the importance of noncrushability and low energy transfer, be relatively inexpensive, and could be shipped in a spaced saving configuration (flat) for use, all of which are represented by this invention.


Transmission information indicating transmittance of light of a printing medium used in image formation is acquired, a reduction ratio with respect to a maximum amount of mounted color materials used in the image formation is set based on the transmission information, and a fixing index indicating a fixing state of the color materials with respect to the printing medium is set based on the transmission information.

1. Field of the Invention
The present invention relates to image processing for improving a viewing density of an image and for reducing the amounts of consumed color materials.
2. Description of the Related Art
As an apparatus for forming an image on a printing medium (to be also referred to as "printing paper" hereinafter), an image forming apparatus for executing image formation based on an electrophotography system (electrophotographic printer) is known. The electrophotographic printer forms an image by transferring toners as color materials onto a printing medium, and fixing the toners on the printing medium by heating and pressing the transferred toners.
In recent years, the use application of the electrophotographic printer is extended from a normal copying machine and printer to POD (Print On Demand) as a light printing range. Accordingly, a toner consumption amount reduction requirement to reduce running cost, and a further image quality enhancement requirement to improve the worth of a printed product itself are increasing.
A wide variety of types of printing media are used for the electrophotographic printer. For example, plain paper (high-quality paper, recycled paper, etc.) is used in an office, and actual printing paper (art paper, coat paper, lightweight coat paper, etc.) is used in POD. Various kinds of such paper which have paper weights as weights per unit area ranging from about 50 g/m2 to 300 g/m2 or more are available, and are set as supported paper in various electrophotographic printers.
In general, as paper has a lower paper weight, it has higher transmittance (transmissivity). Paper having high transmittance causes a phenomenon that when printed paper sheets are stacked, an image printed on an underlying paper is seen through, and when paper is viewed from a backside (reverse) face side, an image printed on a front (obverse) face is seen through (to be referred to as "show-through" hereinafter).
Various techniques have been proposed to suppress occurrence of show-through when double-sided printing is executed using printing paper having high transmittance. As one of these techniques, a corrected image is generated by multiplying, by correction coefficients, an image obtained by mirror-reversing an image to be printed on a backside face of printing paper (to be referred to as "backside image" hereinafter), and pixel values of the corrected image are subtracted from those of an image to be printed on a front face of the printing paper (to be referred to as "front image" hereinafter). Also, in another technique, after one face of printing paper is printed, transmittance of that printing paper is detected, and when the transmittance is high, one of processes for "inhibiting double-sided printing", "changing an image density", and "changing a fixing temperature" is executed. Furthermore, in still another technique, after one face of printing paper is printed, transmittance of the printing paper is detected, and an exposure amount upon printing an image on the other face is controlled.
As a problem caused by the transmittance of printing paper, not only the aforementioned show-through but also a problem of a viewing density change is posed. With this problem, transmitted light intensity difference from the backside face due to transmittance difference influences densities and colors viewed on a printed product.
A general viewing environment of a printed product includes light which is reflected by a wall, desk, or the like and enters the backside face in addition to directly illuminated light on a viewing face of a printed product. This phenomenon will be described below with reference to FIG. 1.
FIG. 1 is a conceptual view of a state in which a printed product is illuminated with light when viewed from a side sectional direction of the printed product. In FIG. 1, the printed product includes printing paper 101 and a toner layer 102 fixed on that paper. A light ray 103 comes from an illumination such as a ceiling illumination or illumination stand and directly enters on a viewing face (front face) of the printed product. A light ray 104 is reflected by a wall, desk, or the like, and enters the backside face of the printed product. As shown in FIG. 1, the light ray 103, which enters the front face of the printed product, is absorbed or scattered by the toner layer 102, or is transmitted through the toner layer 102 and is reflected by the front face of the printing paper 101, and is viewed as a reflected light ray 105 from the printed product.
The light ray 104, which enters the backside face of the printed product, is transmitted through the printing paper 101 and toner layer 102, and is viewed as a transmitted light ray 106. As will be described in detail later, a light ray 107 is scattered by the toner layer 102, and returns to the backside face of the printed product. Light intensity of the transmitted light ray 106 from the backside face to the front face depends on transmittance of the printing paper 101, and increases with increasing transmittance. Light intensity, which is actually viewed by the user as the printed product formed by the toner layer 102, includes that of the reflected light ray 105 and that of the transmitted light ray 106. Therefore, printing paper having higher transmittance has larger light intensity, and a density (viewing density) viewed as the toner layer 102 consequently lowers.
Also, the transmitted light intensity from the backside face to the front face of the printed product varies depending not only on the transmittance of the printing paper but also that of toner fixed on the printing paper. The transmittance of toner varies depending on a fixing state of toner although the mounted amount (applied amount) of that toner (a weight of toner per unit area) remains the same. This is because a void ratio and spatial density of pigment in the toner layer change depending on heat and pressure differences in a fixing process, and degrees of absorption and scattering of light on the toner layer change.
As described above, image quality deterioration caused by the transmittance of printing paper includes the show-through and viewing density change. As a technique for suppressing image quality deterioration, a technique for taking a measure against the show-through like in the aforementioned technique has been proposed. However, a technique for taking a measure against the viewing density change is not available.
Also, as for the toner consumption amount reduction requirement, a technique so-called a toner saving mode, which reduces a toner consumption amount at the sacrifice of a formed image density, is known. However, a technique which reduces a toner consumption amount while maintaining a viewing density of an image is not available.

Image processing apparatus and method having viewing-density priority and color material saving modes


The invention is directed to a method and apparatus for evaluating and correcting rhythm of audio data. Embodiments of the invention are capable of obtaining preferred rhythm in audio data, and strategically correcting the portions of audio data resulting an enhancing rhythm. A system embodying the invention may detect each transient in audio data, compute an ideal time for the transient and determine the time deviation from the expected ideal time. The system may correct for the time of the transient by altering the audio data before or after the transient. The system utilizes one or more methods to correct for the timing while preserving the audio quality of the signal.

Time and Pitch are fundamental components of music. Rhythm is concerned with the relative duration of pitch and silence events in time. In fact, the quality of a music performance is largely judged by how well a performer or group of performers keep the time. In music compositions, time is divided into intervals that the musician follows when playing music notes. The closer the onset of the notes to the beginning of a time interval, or to a subdivision thereof, the more agreeable the music sounds to the human ear. In order to learn to keep time, musicians use a time keeping device, such as a metronome while playing music. With practice, skilled performers are able to play notes in relative timing with each metronome tick. However, in other cases the performer may keep an average time over the length of a performance, whereas the notes may individually deviate from each expected ideal tick, this is known as rubato. The human ear is sensitive to even small deviations in time and is able to judge the quality of the performance due to these deviations.
Modern digital data processing applications offer tools to correct or enhance audio data. These applications are capable of reducing background noise, enhancing stereo effects, adding or removing echo effects or performing other such enhancements to the audio data. However, these existing applications do not provide a mechanism for correcting inaccurate rhythm events in the audio data. Because of this and other limitations inherent in the prior art, there is a need for a process that can reduce rhythmic deviations in audio data.
Embodiments of the invention provide a mechanism for enhancing the rhythm of an audio data stream or audio stream for short. For instance, systems adapted to implement the invention are capable of enhancing rhythm in audio data by obtaining the underlying rhythm information, determining for each audio data event an ideal time, and correcting significant deviations from the ideal time.
Audio data waveforms generally show periods of relatively low amplitude and periods of high amplitude. Transient events occur between relatively low amplitude and high amplitude audio waveform portions of the audio data and generally correspond to beats in the music that are expected to occur at regular intervals. The relation of these events in time has a significant impact upon the quality of the performance. Embodiments of the invention detect deviations from an ideal time for each event and alter the timing of each transient event to achieve this ideal timing.
Embodiments of the invention may utilize a conversion function to represent the energy in audio signal. From an audio energy viewpoint, transients are regions where the energy abruptly increases. By detecting local increases of energy, an embodiment of the invention is able to detect each transient and determine a number of timing parameters for each transient. For example, the system may determine the time at which a transient reaches a given threshold level, the time the transient reaches a local peak, the time of the onset of the transient, and any other time related information that may be garnered from the audio signal.
Embodiments of the invention compare one or more time references for each transient with time data of an ideal time event (that may for example correspond with a time tick of a metronome) and compute a deviation between the occurrence of the transient and its expected ideal time. A determination as to whether to correct the deviation may then be made based on one or more correction criteria.
The system may apply one or more techniques for correcting time deviations. In one embodiment of the invention, when the transient is to be moved to an earlier point in time, the system may compress one or more portions of the audio data ahead of the transient. In the case when a transient is to be delayed, the system may expand audio data ahead of the transient in question.
Expansion and compression by inserting and deleting audio data may lead to unpleasant sound effects which are known as artifacts. Embodiments of the invention employ methods for manipulating the audio data either by introducing no artifacts or by applying further methods to remove the artifacts. To this end, embodiments of the invention may utilize cross-fading methods to correct for transitions between segments after a portion of the audio data has been removed, which may have created discontinuities in the signal. In other cases where a portion of the audio data is to be expanded, an embodiment of the invention may utilize cross-fading among a number of successive segments to achieve expansion without introducing a repetitive pattern that may be detected by the human ear and judged unpleasant.
By obtaining a preferred rhythm for a performance, detecting an ideal time for each transient and correcting significant deviations from the ideal time, embodiments of the invention provide a powerful tool to enhance music quality as perceived by the human ear.

This patent is subject to a terminal disclaimer.

Evaluating and correcting rhythm in audio data


A light shielding structure of a zoom lens barrel includes an outer ring, an intermediate ring and an inner ring which are concentrically arranged, the intermediate ring being movable relative to the outer ring and including at least one through-slot, the inner ring being movable relative to the intermediate ring, and the inner ring including at least one projection which is formed on an outer peripheral surface of the inner ring to be engaged in the through-slot. The light shielding structure is in the form of a light shielding sheet including a fixing portion which is fixed to the inner ring, and at least one resilient light-shielding tongue which projects radially outwards from the fixing portion to pass through the through-slot so that a radially outer end portion of the resilient light-shielding tongue comes in contact with an inner peripheral surface of the outer ring.

1. Field of the Invention
The present invention relates to a light shielding structure of a zoom lens barrel.
2. Description of the Related Art
In conventional zoom lens barrels, it is common practice to linearly guide lens frames, which support lens groups, in an optical axis direction by a linear guide mechanism. Although various types of such linear guide mechanisms have been proposed, it is basically the case that a set of linear guide grooves which extend parallel to an optical axis are formed on a stationary member while a set of followers which are respectively engaged in the set of linear guide grooves are formed on a movable member (e.g., a movable lens frame).
In zoom lens barrels produced in recent years, there has been a growing tendency for the aforementioned set of linear guide grooves to be formed as a set of linear guide slots (through-slots) for the purpose of miniaturizing the zoom lens barrel, especially for reducing the diameter of the zoom lens barrel. However, using such through-slots raises a possibility of harmful light such as stray light entering into an optical path of the zoom lens barrel through the linear guide slots, and hence, reaching the picture plane (e.g., an imaging surface of an image pickup device or a sensitive surface of silver-salt film). Specifically, since the relative position of a plurality of lens frames varies in a zooming operation, harmful light which has nothing to do with the photographing operation may reach the picture plane through the set of linear guide slots in some specific relative position of the plurality of lens frames to impair an obtained object image. To prevent this problem from occurring, it is common practice to provide a light shielding structure for preventing such harmful light from entering into an optical path of the zoom lens barrel to reach a picture plane. However, it is difficult to obtain a simple light shielding structure which is effective over the entire zooming range because the relative position of the plurality of lens frames in the optical axis direction varies in a zooming operation.

Light shielding structure of a zoom lens barrel


A data word is error correction encoded to provide a worst case codeword without bit transitions between worst case codeword bits. A modulation bit is calculated as a function of the worst case codeword. The modulation bit has a bit polarity opposite a bit polarity of the worst case codeword bits. The worst case codeword bits are added with the modulation bit to form a modulated code word.

In data storage devices such as disc drives, data is read from a disc by a read operation that involves a mechanical scanning motion of a disc moving relative to a read head. The read data was originally in synchronization with the mechanical motion during writing, but this original synchronization is not available at a later time during readback. The read back data needs to be resynchronized with a readback clock as the data is read and processed by a computer. This process of resynchronization is accomplished by a timing recovery circuit. The timing recovery circuit includes an oscillator that is repeatedly synchronized by the time position of transitions of the read data.
Known data storage devices use DC free coding (such as run length limited (RLL) coding) to set limits on the length of time between transitions which ensures that the oscillator does not drift too far between transitions and to limit the bandwidth of the read back signal to a narrow frequency band. Run length limited or DC free coding, however, adds undesired overhead such as slow coding rates and time delays due to decoding the DC free coding.
With the use of perpendicular recording, readback signals can be obtained that include DC levels of bits as well as transitions between bits. The need for DC free coding is considerably reduced or eliminated, however, there is a need for oscillator synchronization with perpendicular recording.
A method and apparatus are needed to avoid the high overhead of existing DC free coding schemes while providing the timing recovery needed to keep a read oscillator synchronized. Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.

Modulation bit added to worst case codeword


A method to control thermal energy transport uses mobile coherent interfaces in nanoscale ferroelectric films to scatter phonons. The thermal conductivity can be actively tuned, simply by applying an electrical potential across the ferroelectric material and thereby altering the density of these coherent boundaries to directly impact thermal transport at room temperature and above. The invention eliminates the necessity of using moving components or poor efficiency methods to control heat transfer, enabling a means of thermal energy control at the micro- and nano-scales.

Thermal energy transport across interfaces is a topic of great recent interest. Largely this resurgence is motivated by a necessity to control heat generated in microelectronics and to develop new higher-performance thermoelectric materials for cooling applications and energy harvesting. The interfaces in these materials, however, are static and immobile without gross material deformation. Separately, there has been a need for appropriate materials or nanosystems where thermal conductivity can be actively altered or rectified. Typically this is provided by mechanical means (physical separation) or through the use of one-dimensional materials (nanowires) that can only carry minute amounts of thermal energy.
It is well known that as material characteristic dimension (thickness, grain size, etc.) scales toward nanometer length scales, the role of interfaces on thermal transport become increasingly important. This phenomenon is driven largely by the fact that the bulk of heat is carried by phonons with mean free paths of 1-100 nm. See D. G. Cahill et al., J. Appl. Phys. 93, 793 (2003). Therefore, as material dimensions approach these length scales, they become comparable to the phonon wavelengths. This trend has fueled a substantial recent increase in studies into preparation of thermoelectric materials with fine grain sizes and superlattice structures where a high density of incoherent, highly disordered interfaces has been shown to scatter phonons and decrease thermal conductance. See Z. J. Wang et al., Nano Lett. 11, 2206 (2011); S. K. Bux et al., Adv. Funct. Mater. 19, 2445 (2009); G. Joshi et al., Nano Lett. 8, 4670 (2008); B. Poudel et al., Science 320, 634 (2008); W. J. Xie et al., Appl. Phys. Lett. 94, 102111 (2009); Y. C. Lan et al., Adv. Funct. Mater. 20, 357 (2010); W. S. Capinski et al., Phys. Rev. B 59, 8105 (1999); R. Venkatasubramanian et al., Nature 413, 597 (2001); and S. M. Lee et al., Appl. Phys. Lett. 70, 2957 (1997).
Coherent and semi-coherent interfaces, those where there is atomic registry across the interface with limited dislocation densities, have been shown and calculated to decrease thermal transport in many systems. See R. M. Costescu et al., Phys. Rev. B 67, 054302 (2003); G. J. Riedel et al., IEEE Electron Device Lett. 30, 103 (2009); P. E. Hopkins et al., ADDI. Phys. Lett. 98, 231901 (2011); and M. Kazan et al., Surf. Sci. Rep. 65, 111 (2010). The resulting thermal boundary resistance associated with these coherent interfaces is commonly modeled with acoustic mismatch or diffuse mismatch models where differences in the phonon dispersion spectra of the two materials results in scattering of phonons at the coherent interface. Interestingly, it has also been shown that coherent interfaces in chemically homogeneous systems can also possess an interface thermal boundary resistance. This has been successfully modeled using molecular dynamics simulations of Σ3 (111) boundaries in silicon. See S. Aubry et al., Phys. Rev. B 78,064112 (2008). A discontinuous change in the temperature gradient across the coherent boundary was predicted that amounted to a ˜1% decrease in absolute temperature across the boundary. While the thermal boundary resistance computed for the coherent boundary was an order of magnitude less than that computed across an incoherent grain boundary, this work did show that even boundaries where crystalline coherence is maintained can scatter phonons and decrease thermal conductivity.
In addition to interface effects on thermal conductivity, where an interface can effectively introduce a thermal resistance to heat transport, strain can also affect thermal conductivity. Just as reducing the characteristic material dimensions to length scales similar to those of heat-carrying phonon wavelengths can decrease thermal transport by increasing interactions with interfaces, decreasing material dimensions can also result in increased strain effects. This is particularly true in thin film materials, where layers thinner than the critical thickness for strain relaxation are routinely prepared. It has been predicted that the presence of strain causes shifts in phonon dispersion curves that dictate phonon group velocities and specific heats and, ultimately, thermal conductivity. See X. B. Li et al., Phys. Rev. B 81, 195425 (2010). Materials in compressive strain tend to have increased thermal conductance; those in tensile strain tend to have decreased thermal conductivity. Simulations predict that films under tensile strains of less than 10% display as much as a factor of two lower thermal conductivity than films in an unstrained state.
The majority of recent thermal conductivity studies have been focused on semiconductor and metallic systems—those typically encountered in microelectronics where thermal energy control is a significant challenge for device scaling. Less studied are the thermal properties of ferroelectric materials. Given the preponderance of ferroelectric and piezoelectric materials in applications where heat production and control must also be closely controlled (for example in medical ultrasound transducers and as circuit elements in microwave devices), this lack of study is somewhat surprising.
The linkage of ferroelectricity and phonon dispersion is well documented. It is the condensation of a transverse optical "soft" phonon mode that results in the stabilization of the dipole moment that gives rise to the reorientable polarization that is the hallmark of ferroelectric response. In spite of the significant computational and experimental studies on this optical phonon response, the study of thermal properties of these materials remains limited. The thermal properties that have been measured are typically done so on bulk ceramic or single crystalline samples. These studies have shown that ferroelectric materials tend to possess relatively low thermal conductivities with values at room temperature ranging from ˜20 W−m−1-K−1 for KTaO3 to ˜1 W-m−1-K−1 for the relaxor Pb(Mg1/3Nb2/3)O3 (a relaxor ferroelectric is a single crystal or engineered ceramic with extraordinarily high electrostrictive constants). See M. Tachibana et al., Appl. Phys. Lett. 93, 092902 (2008); and M. Tachibana and E. Takayama-Muromachi, Phys. Rev. B 79, 100104 (2009). It has been observed that there are discontinuities in the thermal properties at the paraelectric/ferroelectric and ferroelectric/ferroelectric phase transitions that are the result of the latent heat associated with the first order phase transitions. The very low amorphous-like thermal conductivities of the relaxor ferroelectric materials has been attributed to the existence of nanoscale composition fluctuations, which also give rise to polar nano-regions and complexities associated with 'soft' optical phonon modes interacting with the phonon modes responsible for heat conduction.
Domain boundaries are coherent interfaces in ferroelectric materials separating regions of differing polarization. As ferroelectricity is only possible in non-centrosymmetric crystal structures, these boundaries cannot be atomically abrupt owing to differing lattice parameters along the crystal axes. Rather, these boundaries are graded, as shown in FIGS. 1A and 1B, and typically span several unit cells, or approximately 1-2 nm in thickness. See S. Stemmer et al., Philos. Maq. A-Phys. Condens. Matter Struct. Defect Mech. Prop. 71, 713 (1995). The several unit cells are required to accommodate strain across the domain boundary, as shown in FIG. 1C. Regardless of this distortion, no bonds are broken across the interface, which therefore remains coherent. These domain boundaries form to minimize the energy of the system; domains will form to the point where the energy cost of forming domain walls surpasses the energy cost of not having walls. In a mono-poled ferroelectric single crystal, for example, an electric field will form across the crystal as a result of surface charges that develop to compensate for the polarization. This results in a destabilizing of the polarization. There are several mechanisms that can occur to compensate for this depolarization field, including compensating charges from the surrounding environment, polarization gradients through the thickness of the crystal, or formation of domains. Randomly oriented domains would possess no net polarization and therefore remain stable. In mechanically constrained crystals, such as within ceramic grains or thin films, domain structures can also form to minimize the mechanical strain energy in the system.
Domain boundaries have previously been observed to decrease the thermal conductivity of bulk ceramic and single crystalline ferroelectric materials in a very limited number of studies. See A. J. H. Mante and J. Volger, Physica 52, 577 (1971); Q. Lin and D. M. Zhu, Phys. Rev. B 49, 16025 (1994); and M. A. Weilert et al., Phys. Rev. Lett. 71, 735 (1993). In these previous studies, it was observed that at cryogenic temperatures—temperatures where the phonon mean free paths are quite long—the existence of domain walls resulted in a decreased measured thermal conductivity compared to samples where the domain wall concentration was reduced. For example, an applied electric field has been shown to reduce the thermal conductivity of a barium titanate (BaTiO3) single crystal at cryogenic temperatures. See A. J. H. Mante and J. Volger, Physica 52, 577 (1971). The application of the electric field acts to reduce the domain wall density by providing a driving force to align ferroelectric dipoles by growth of favorably aligned domains into less favorably aligned domains. At ˜10K, there was an 80% difference in thermal conductivity between poled (electric field of 11 kV/cm) and un-poled BaTiO3. As the thermal conductivity values reported for all materials only spans a few orders of magnitude (˜1 W-m−1-K−1 for WS2 to ˜2000 W-m−1-K−1 for diamond), this modification of nearly an order of magnitude constitutes a significant change in thermal conductivity. In each of these studies the domain wall dependence of thermal conductivity was only observed at temperatures lower than the onset of Umklapp scattering. This is consistent with the likely large domain wall spacing in these single crystals only disrupting long wavelength phonons. Once enough thermal energy exists in the system to allow for multi-phonon Umklapp processes, the effect of long wavelength phonon scattering on overall thermal conductivity is limited. Therefore, this effect was only present up to the temperature where Umklapp scattering became the dominant phonon scattering mechanism (˜30 K) and heretofore was limited to cryogenic temperature regimes.
It is well known that as the dimensions of ferroic crystals and grains decrease, the density of domain walls increases. See G. Catalan et al., J. Phys.-Condes. Matter 19, 022201 (2007); and C. Kittel, Physical Review 70, 965 (1946). This domain density scaling effect is known as Kittel's Law, and has been widely observed in a broad range of ferromagnetic and ferroelectric single crystals, ceramics, and thin films. For ferroelectric thin films in particular, as the thicknesses decrease to less than a micron, the mean domain wall spacing decreases to 102 nm and below. Therefore, as shown in FIG. 2B, as the ferroelectric layer thickness decreases the domain boundary spacing is smaller than the phonon mean free paths over a broad temperature range, as shown in FIG. 2A. For a 100 nm thick PbTiO3 film, the domain wall spacing (about 20 nm) is estimated to be equivalent to the phonon mean free path at room temperature. See M. Tachibana et al., Appl. Phys. Lett. 93, 92902 (2008); G. Soyez et al., Appl. Phys. Lett. 77, 1155 (2000); G. Catalan et al., J. Phys.-Condes. Matter 19, 022201 (2007); and A. G. Beattie and G. A. Samara, J. Appl. Phys. 42, 2376 (1971).
However, a need remains for a ferroelectric material wherein the thermal conductivity can be actively tuned at temperatures greater than 30 K and therefore requires domain boundary spacings that are significantly narrower than available in single crystals and most polycrystalline ceramics.

Voltage tunability of thermal conductivity in ferroelectric materials


There is provided system for monitoring spontaneous breathing of a mechanically ventilated target individual, including: a feeding tube for insertion into a distal end of an esophagus of the individual, sensor(s) disposed on the feeding tube at a location such that the sensor(s) is located at the distal end of the esophagus of the individual when the feeding tube is in use, wherein the sensor(s) is positioned for sensing values by contact with the tissue of the esophagus including a lower esophageal sphincter (LES) and/or tissue in proximity to the LES, and code for computing an indication of a frequency band of diaphragm movement of the individual according to an analysis of values sensed by the sensor(s), and for adjustment of parameter(s) of a mechanical ventilator for mechanically ventilating the individual, wherein the instructions for adjustment are computed while the feeding tube is in use.

The present invention, in some embodiments thereof, relates to treatment of mechanically ventilated patients and, more specifically, but not exclusively, to systems and methods for tracking spontaneous breathing of a mechanically ventilated patient.
Adjustment of ventilation to specific patient needs is a key element in patient survival and recovery. Prolonged mechanical ventilation is associated with significant morbidity and mortality. Patients should be weaned off mechanical ventilation as soon as possible. It is estimated that 40% of the duration of mechanical ventilation is dedicated to the process of weaning.

Systems and methods for tracking spontaneous breathing in a mechanically ventilated patient


A system, method, and computer program product are provided for receiving device instructions from one user to be overlaid on an image or video of the device for another user. In use, at least one of an image and video of a device is received from a first user via a network. Additionally, at least one instruction for the device is received from a second user, in response to the receipt of the at least one of the image and video of the device. Furthermore, the at least one instruction is provided to the first user for display as an overlay to the at least one of the image and video of the device.

Traditionally, when a user has desired to receive instructions for a device, namely for configuring and/or operating the device, the user has been required to review an instruction manual for the device or call customer service to speak with a customer service representative (CSR). Unfortunately, these methods for receiving instructions have been associated with various limitations. For example, both reviewing the manual and calling a CSR can be time consuming, inefficient, etc.
There is thus a need for addressing these and/or other issues associated with the prior art.

System, method, and computer program for receiving device instructions from one user to be overlaid on an image or video of the device for another user


A semantic-based search system includes a log generating unit configured to generate a common log storing knowledge corresponding to general knowledge and a user log stored by reflecting user preference, an instance analyzing unit configured to analyze vector characteristics corresponding to an instance among interpretation alternatives according to a keyword input by a user, a weighted value calculating unit configured to calculate weighted values of confidence values and cosine similarity values of interpretation alternatives including vector characteristics of the instance with respect to at least an one of the common log and the user log, and an aligning unit configured to align rankings of the interpretation alternatives according to the keyword input on the basis of the calculated weight values of the confidence values and the cosine similarity values.

1. Field of the Invention
The present invention relates to a semantic-based search system and a search method thereof and, more particularly, to a semantic-based search system providing an interpretation alternative of a keyword according to a keyword input, and a search method thereof.
2. Related Art
In an existing search method of a Web searching engine, when a user inputs a keyword desired to be searched, a search statement denoting a keyword conforming to a keyword within content of the search statement (or content) or meta-data added to a search sentence is searched. Thus, since a search sentence identical to a keyword is searched according to an input of a keyword, there is no need to interpret a meaning of a search sentence expressed by a relationship between keywords.
However, an existing keyword conformity-based search method has confronted with a limitation according to simple searching, so a semantic-based search scheme has been studied. Here, the semantic-based searching scheme is a searching scheme of interpreting a meaning of a search sentence on the basis of relationships between and among entities denoted by input keywords, and searching data conforming to the interpretation.
Also, terminal devices with which users execute search application extend to terminal devices having restrictions to a sentence input interface, such as a smart phone, a tablet personal computer (PC), a smart TV, and the like, in addition to a PC. In a terminal environment of these terminal devices, a search sentence is input through a Qwerty keyboard, or the like, displayed on a small screen because they do not have a dedicated keyword for inputting a keyword. In case of recent enlarged terminal devices, a keyword is input through a Qwerty keyboard, or the like, displayed on a small screen, only a key word (or a necessary word), while omitting a verb, or the like, rather than inputting a complete natural language sentence, is input in order to minimize the number of times of inputting a keyboard. Thus, input of only a key word according to the input scheme in the limited input environment makes it difficult to interpret a meaning thereof because there is no information regarding a sentence structure.
Meanwhile, Korean Patent Laid Open Publication No. 10-2012-0053253 entitled "Hybrid semantic search system and method" discloses a semantic-based search system using a semantic-based searching scheme.
The related art "Hybrid semantic search system and method" includes determining a type of a query received from a user terminal, performing keyword searching on a query when the query input by a user is a free query; determining whether to perform semantic-based searching on the query on the basis of keyword search results with respect to the query and performing semantic-based searching using ontology on the query, and providing results of the performed semantic-based searching to the user terminal.
However, in the case of the related art "Hybrid semantic search system and method", the number of keywords input by a user is fixed and a partial graph conforming to a combination of types of knowledge base entities to which each keyword is mapped, e.g., a combination of an instance, properties, and a number of classes, is searched from a knowledge base, having a problem in that interpretation alternatives of a keyword a user wants to substantially search cannot be accurately derived.

Semantic-based search system and search method thereof

ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE


A receive attenuation system for a trainline communication system utilizing an intra-consist electrical cable has an analog front end amplifier, a trainline communication processor, an adjustable attenuator, and a gain controller. The trainline communication processor is configured to generate a receive gain control signal configured to control receive gain of the analog front end amplifier. The adjustable attenuator is capable of being coupled to the intra-consist electrical cable and configured to variably attenuate signals received from the intra-consist electrical cable before transmitting the signals to the analog front end amplifier. The gain controller is coupled to the adjustable attenuator and configured to detect the receive gain control signal generated by the trainline communication processor, determine a supplemental attenuation control value based on the detected receive gain control signal, and control the adjustable attenuator according to the supplemental attenuation control signal.

A consist includes one or more locomotives that are coupled together to produce motive power for a train of rail vehicles. The locomotives each include one or more engines, which combust fuel to produce mechanical power. The engine(s) of each locomotive can be supplied with liquid fuel (e.g., diesel fuel) from an onboard tank, gaseous fuel (e.g., natural gas) from a tender car, or a blend of the liquid and gaseous fuels. The mechanical power produced by the combustion process is directed through a generator and used to generate electricity. The electricity is then routed to traction motors of the locomotives, thereby generating torque that propels the train. The locomotives can be connected together at the front of the train or separated and located at different positions along the train. For example, the consist can be positioned at the front, middle, or end of the train. In some instances, more than one consist can be included within a single train. In some consists, the locomotives include computer systems for maintaining operations of the locomotive.
Because the locomotives of a consist must cooperate to propel the train, communication between the locomotives can be important. Historically, this communication has been facilitated through the use of an MU (Multi-Unit) cable that extends along the length of the consist. An MU cable is comprised of many different wires, each capable of carrying a discrete signal used to regulate a different aspect of consist operation. For example, a lead locomotive generates current within a particular one of the wires to indicate a power level setting requested by the train operator. When this wire is energized, the engines of all trailing locomotives are caused to operate at a specific throttle value. In another example, when one locomotive experiences a fault condition, another of the wires is energized to alert the other locomotives of the condition's existence.
In some consists, locomotives communicate via their respective computer systems on an Ethernet network formed over the MU cables, or other intra-consist electrical cables. With this configuration, network data can be transmitted from the computer system in the lead locomotive to the computer systems in the trail locomotives, and vice-versa. The network data includes data that is packaged as data packets and uniquely addressed to particular computer systems, or portions of the computer systems. The network data can be, for example, vehicle sensor data indicative of vehicle health, commodity condition data, temperature data, weight data, and security data. The network data is transmitted orthogonal to conventional non-network (i.e., command) data that is already being transmitted on the MU cable.
Traditionally, communication over a MU cable or other intra-locomotive cable was limited to voltage levels for individual wires within the MU cable. For example, a high voltage applied to an individual wire might indicate one value, while a low or zero voltage applied to the individual wire might indicate a second value. While MU cables provide an existing infrastructure that can be used by the computer systems of locomotives to communicate network data, MU cables were not designed for network data communication. For example, the wires within a MU cable are not shielded or twisted and are subject to interference. As a result, signal strength can degrade significantly as the signal propagates the length of a MU cable. For example, in a locomotive consist, the locomotive computer system adjacent to the signal's origin might receive the signal at 10 dBm, a locomotive further away in the consist might receive the signal at −30 dBm, which may be too weak to effectively transmit network data.
The signal degradation can be overcome by increasing strength of the signal when it is transmitted. While increasing the transmit signal allows for adequate signal strength to reach locomotive computer systems far away from the origin of the signal, it can overload the components of locomotive computer systems that are located close to the origin of the signal. For example, increasing the signal strength might produce a received 10 dBm signal at a locomotive further away from the origin of the signal, but might overload a locomotive computer system close to the origin of the signal with a 20 dBm signal.
Thus, one solution for overcoming signal degradation is to increase the strength of the transmit signal, but attenuate the signal on the receive end so as to not overload computer systems receiving the signal. Such a solution is described in U.S. Patent Publication No. 2012/0163201 (the '201 publication) filed by Williams et al. and published on Jun. 28, 2012. The '201 publication describes a cable modem auto-attenuation system capable of taking a high-power signal from the cable plant's service line, dropping the power value down to a usable level and transmitting the signal to a cable modem. Although the system of the '201 publication may minimally solve the problem of overcoming signal degradation over cable, the system would not be adequate for a trainline communications systems because it is not adapted to interface with trainline communication hardware and does not provide the granularity of attenuation control needed for trainline communication systems.
The disclosed system is directed to overcoming one or more of the problems set forth above.

Receive attenuation system for trainline communication networks


A camera-integrated VTR is arranged to detect an image shake according to a control error signal of a driving control system provided for recording or reproduction by moving a tape and a head relative to each other and to correct the image shake by supplying the result of detection to an image-shake correction circuit.

1. Field of the Invention:
This invention relates to an image-shake detecting device and an image-shake correcting device and more particularly to an image-shake detecting device and an image-shake correcting device adapted for a camera-integrated type video recording apparatus.
2. Description of the Related Art:
Image-shake correcting devices of varied types have come to be used for the camera-integrated type video A recording apparatus which is sometimes called a camcorder. The basic principle of the image-shake correcting device is to detect the motion of a camera body due to a shake of a camera holding hand and to correct an image shake resulting from the motion of the camera body by moving a picked-up image in the direction of offsetting the motion according to the vector of the motion.
For this purpose, it has been known to detect the motion vector in one of three different manners, including a pure circuit arrangement which detects the motion vector by carrying out an arithmetic operation for matching temporally adjacent pictures with each other, an arrangement using a sensor which electromechanically detects a shake of the camera body, such as an angular velocity sensor, and an arrangement which combines the two arrangements mentioned above.
As for means for offsetting the motion of the camera body according to the detected vector of the motion, two different arrangements have been known. One is optical means arranged to vary and control the apex angle of a variable angle prism in such a way as to offset the vector of the motion. The other is electronic means which is arranged to store a picked-up image on an image memory and to move and change the image reading range on the memory in such a way as to offset the motion vector.
The arrangement to detect the motion vector solely from the picked-up image is advantageous in respect to a reduction in size of the apparatus. This arrangement is, however, apt to perform a faulty action according to the state of the object of shooting. For example, in a case where an image of the object spreads all over a pickup image plane, it is hardly possible to correctly ascribe some movement taking place within the pickup image plane to a movement of the object of shooting itself or to a shake of the image of the object.
Another motion vector detecting arrangement which uses an electromechanical sensor is free from the possibility of the above-stated faulty action. However, that arrangement generally necessitates the use of a plurality of such sensors. These sensors not only require spaces for them but also cause an increase in cost of manufacture.

Electronic apparatus having image-shake correcting device


Provided is a sensing amplifier driving/controlling circuit for supplying pull-up/down voltage to a sensing amplifier of a semiconductor memory device, including: a first switching device for connecting internal voltage to the first driving line which in turn applies high voltage to the sensing amplifier; a second switching device for connecting an external voltage to the first driving line which in turn applies high voltage to the sensing amplifier; a third switching device for connecting ground voltage to a second driving line which in turn applies ground voltage to the sensing amplifier; a comparator having an inverse input terminal which is connected to the first driving line and a non-inverse input terminal which receives a reference voltage and thus the comparator is enabled when receiving first and second control signals; an inverter for inverting the first control signal and applying the inverse signal to the control input terminal of the first switching device; and a NAND gate for receiving the outputs of the comparator and the first control signal with its input terminals and performing a NAND operation.

1. Field of the Invention
The present invention relates to a bit line sensing amplifier driving/controlling circuit, specifically, to a circuit for rapidly supplying pull up/down voltages to a bit line sensing amplifier, thereby reducing power consumption.
2. Discussion of Related Art
As illustrated in FIG. 1, in semiconductor devices, a memory includes a cell array CA for storing data and a bit line sensing amplifier array BSAA for amplifying the data of the cell array CA.
In the memory cell array CA, the data cells C are arranged in a N.times.M matrix. Each cell is connected to a word line WL and a bit line BL. The even cells are connected to one bit line BL (BL1) and the odd cells are connected with an associated bit line (/BL1). Where the cells in the cell array CA are arranged in an N.times.M matrix, the cell array CA has M word lines, WL1 through WLM. There is a pair of bit lines in every column. Therefore, n pairs of bit lines, BL1 and /BL1 through BLN and /BLN, form the cell memory.
A bit line sensing amplifier array BSAA, made of n bit line sensing amplifiers BSA1 to BSAN, is connected to CA. Each of the sensing amplifiers is connected to a pair of bit lines (BL:/BL) to amplify the potential difference (voltage) between the two bit lines, thus sensing data held in the cell. These sensing amplifiers comprise pull-up devices made of first and PMOS transistors P1 and P2, connected in series with pull-down devices, made of first and second NMOS transistors M1 and M2, between the first and second driving lines SPC and SNCB. The gates of the first and second PMOS transistors P1 and P2 being connected to the first and second bit lines BL and /BL, respectively, and the gates of the first and second NMOS transistors M1 and M2 being connected to the first and second bit lines /BL and BL, respectively.
A bit line driver BLD is connected to the bit line sensing amplifier array BSAA through driving lines SPC and SNCB, thus supplying the voltage for driving the bit line sensing amplifiers BSA1 to BSAN. The PMOS transistors serving as the pull-up devices for the sensing amplifiers are commonly connected to the first driving line SPC of the bit line driver BLD, and the NMOS transistors serving as the pull-down devices are connected to the second driving line SNCB of the bit line driver. The bit line driver BLD applies a positive operational voltage VCC to the first driving line SPC and grounds the second driving line SNCB according to a control signal generated by the bit line controller BLC.
The operation of the previously described driving/controlling circuit, as illustrated in FIG. 1, will be described with reference to FIG. 3.
When high state voltage data is stored in a cell in the memory cell array, the bit line /BL, which is paired with another bit line BL connected to the cell C and is preset to a voltage which is of a half potential level (VBLP), receives a driving voltage applied to the word line connected to the cell. When this occurs, a pass transistor MC corresponding to cell C is turned on and the charge in a capacitor CAP is discharged to bit line BL1. In other words, a charge redistribution occurs. The potential of the bit line BL preset to VBLP differs from the potential of the bit line /BL, to which the charge of the capacitor CAP is applied and produces a potential difference .DELTA.V between the two bit lines. Thus the bit line driver BLD applies VCC to the first driving line SPC and VSS (i.e., ground) to the second driving line SNCB.
As illustrated in FIG. 3, when the potential of BL1 is increased and the potential of /BL1 is decreased so that the data stored in capacitor CAP is read through the data bus connected to the sensing amplifier; the same data can be stored in the cell. Thus, if the driving voltage is applied to the sensing amplifier, the voltage Vgs between the gate and the source of the second NMOS transistor M2, serving as a pull-down transistor in the sensing amplifier and connected to the second driving line SNCB, is higher than the Vgs of the first NMOS transistor M1 by .DELTA.V. Therefore, the second NMOS transistor M2 is turned on before the first NMOS transistor M1, and the charge of the second bit line /BL1 is discharged before first bit line BL1. Accordingly, the vgs value of the first NMOS transistor M1 is decreased and the discharge path of the first bit line BL1 is cut off.
In contrast, the PMOS transistor serving as the pull-up device for the sensing amplifier operates as follows.
As the Vsg of the first PMOS transistor P1, whose gate is connected to the first bit line BL1, is higher than that of the second PMOS transistor P2, whose gate is connected with the second bit line /BL1, the first PMOS transistor P1 is turned on earlier. Consequently, the first bit line /BL1 is pulled up and the discharge current path is cut off. The pull-up transistor P2 is turned off and cuts off the supply of positive voltage to the bit line /BL1. The positive voltage VCC is applied to the bit line BL1, thereby increasing the bit line BL1 voltage to a predetermined level.
FIG. 2 illustrates an example embodiment of the sensing amplifier driving/controlling circuit which has the bit line driver BLD for a driving the bit line sensing amplifier, and the controller BLC.
The conventional sensing amplifier driving/controlling circuit has a voltage generator 1 for generating a predetermined reference voltage VREF; a comparator 2 having a non-inverse data input terminal + for a receiving reference voltage generated by voltage generator 1, and an inverse data input terminal -, connected to the first driving line SPC, to thereby compare the two signals; NAND gate 3 for receiving an output signal of the comparator 2 and a control signal SN, that is externally input, to perform a NAND operation on the two signals; an NMOS transistor MN5 that turns on or off according to the control signal and selectively connects the second driving line SNCB to the ground voltage; and a PMOS transistor MP4 that turns on or off according to the output of the NAND gate 3 and selectively connects the positive voltage VCC to the first driving line SPC.
With reference to FIG. 3, the operation of the described sensing amplifier driving/controlling circuit is described below.
After the word line WL is enabled, when the control signal SN of the bit line sensing amplifier BSAA is converted from a low state into a high state, the NMOS transistor MN5 is turned on so that the potential of the second driving line SNCB, which is charged at 1/2 VCC as well as the bit line; is discharged and reduced to the ground voltage. Furthermore, as the output signal of comparator 2 is in a high state, because the output voltage of the voltage generator 1 is set higher than the 1/2 VCC, the output of the NAND gate becomes high when the control signal SN is in a low state. If the control signal is switched from a low state to a high state, the output of the NAND gate changes from the high state to the low state, thereby turning on PMOS transistor 4. Accordingly, as the PMOS transistor 4 is turned on, positive voltage VCC is applied to first driving line SPC, pulling up the first driving line SPC from the 1/2 VCC state to the VCC state.
In this way, the voltage applied to the first driving line SPC is input to the inverse data input terminal - of the comparator 2. Comparator 2 compares it to the reference voltage VREF, applied through its non-inverse data input terminal +, and if it is higher than reference voltage VREF, comparator 2 applies the low state signal to one input terminal of the NAND gate NAND 3, converting the output of the NAND gate 3 into the high state. Consequently, PMOS transistor 4 is turned off, cutting off the VCC supply to the first driving line SPC. The voltage of the reference voltage VREF is determined by the expected voltage of the first driving line SPC, and is generally set to a level suitable for being restored in the cell similar to the level of the positive voltage VCC.
As illustrated in FIG. 3, the voltage applied to the first driving line SPC oscillates continuously because the voltage is controlled by the output of the comparator 2 while the control signal SN is in a high state.
The technique for driving/controlling the bit line of the described conventional driving/controlling sensing amplifier has a problem with consuming excessive power because the comparator 2 is always in the active state.
To overcome the problems with the conventional sensing amplifier driving/controlling circuit resulting in excessive power consumption, a technique described in U.S. Pat. No. 5,258,950 has been developed. The technique employs the circuit of FIG. 4. The operation of the circuit is described below with reference to FIG. 5.
After a word line WL is enabled, and if a control signal SN of a bit line sensing amplifier BSAA is switched from low to high, an NMOS transistor 41, is turned on and discharges the second driving line SNCB to the ground voltage.
The control signal SN becomes low after passing through a second inverter 42, and is applied to the gate of a second PMOS transistor 43 to turn on the transistor. Accordingly, the internal voltage VDD is applied to the first driving line SPC. Furthermore, the control signal SN changes from high to low by passing through a pulse generator SP1 and a latch circuit having first and second NAND gates NAND1 and NAND2, and therefore is used for turning on the first PMOS transistor 44. The first driving line SPC is pulled up rapidly with the internal voltage VDD and the external voltage VCC by turning on the first and second PMOS transistors 44 and 43.
The voltage pulled up in the first driving line SPC becomes higher than the reference voltage and similar to the internal voltage VDD. Thus, the VREF voltage is set lower than the external voltage VCC and higher than the internal voltage VDD. Under these conditions, a current mirror typed comparator 45 changes the voltage of the output line connected to a short low pulse generator 46, where the first driving line SPC is at a VDD level, to generate a short low pulse using short low pulse generator 46, the pulse to the second NAND gate NAND2. In accordance with this, the signal input to the gate of the first PMOS transistor 44 becomes high.
At the initial stage of the operation, the first and second PMOS transistors 44 and 43, respectively connecting the external voltage VCC to the first driving line and the internal voltage VDD to the second driving line, operate at the same time. If the voltage applied to the first driving line SPC is higher than the reference voltage VREF, only the second PMOS transistor 43, operating with the internal voltage VDD, is continuously in the "ON" state, and the first PMOS transistor 44, for supplying the external voltage VCC to the first driving line SPC, is turned off to thereby reduce power consumption while maintaining the voltage of the first driving line SPC. The first PMOS transistor 44, supplying the external voltage VCC to the first driving line SPC, is turned off to reduce power consumption, thus maintaining the voltage level of the first driving line.
FIG. 5 illustrates the wave form of the voltage applied to each signal line when operating the sensing amplifier driving/controlling circuit.
To solve the problem of the conventional art, the circuit is designed to operate the comparator 45 only during an initial stage of the pull-up operation. As the first driving line SPC is not a simple passive device, as illustrated in FIG. 5, the voltage of the first driving line SPC is drastically decreased when the first PMOS transistor 44 is turned off, thus its wave form is peak-shaped. Consequently, even though the power consumption is reduced, it takes too much time to pull up the first driving line SPC to a stable internal voltage VDD level.
Additionally, if the voltage applied to the first driving line SPC is not higher than the reference voltage VREF while the bit line sensing amplifier BSAA is enabled, output from the latch circuit is not converted even though the enable signal SN is reset. As the output signal of the first inverter maintains the low state, excessive power consumption results. Furthermore, the construction of the latch circuit may be complex.
With memory devices a burn-in test is performed under conditions of high-voltage and high-temperature to detect devices having poor reliability. Here, the external high voltage directly applied to the cell inside the chip through the VCC line may damage the devices.

Circuit for driving/controlling sensing amplifier


The invention relates to a method for storing code symbols and additional control information in a processing means of an encoder of a communication system. In particular, the invention relates to the storing of code symbols together with additional control information in an interleaving memory (IM) of an interleaver. According to the invention, a combining means (COM) combines respective data bits (I, Q) forming a respective code symbol with their associated control bits into a control information/code symbol data word of a predetermined number (K) of bits. A control information/code symbol encoding means (CI/CS-ENC) encodes the control information/code symbol data words into encoded data words of a smaller number of bits. This data word with a smaller number of bits is then stored at a particular memory location in the interleaving memory (IM).

The fact, that data information must be combined with control information before transmission is a common aspect relating generally to telecommunication systems. In particular, this problem becomes severe, when a great plurality of user channels needs to be processed as it is the case in a CDMA system. A base transceiver station BTS of a CDMA system, to which the invention is applicable, is generally shown in FIG. 1.
Briefly summarized, the block diagram in FIG. 1 shows a base transceiver station BTS of a CDMA-system comprising a baseband transmitter TX, a baseband receiver RX and a HF section. In the transmitter TX, user data, for example in the form of ATM packets, is input into a channel encoder unit ENC via an ATM switch and a corresponding interface ATM IFX/IFC. The coded (and also interleaved) data is then modulated and spreaded by a baseband transmitter unit BBTX. The modulated data is then filtered and converted to an analog signal in the unit TRX-DIG, upconverted to the desired carrier frequency in the unit TRX-RF, amplified by a power amplifier unit MCPA and finally transmitted to an antenna ANT via a duplex filter.
In the receiving part of the HF section, two antennas (diversity reception) are commonly used in each sector to receive the signal which is then amplified in the unit LNA, downconverted in the unit TRX-RF, A/D converted and filtered in the unit TRX-DIG. Then the data is demodulated by a RAKE receiver/despreader in the receiver unit BBRX while random access channels (branched off by an intermediate filter unit BBIF) are detected and demodulated in the unit BBRA. The user data US are then decoded in the decoder unit DEC and transmitted to the ATM switch via an ATM interface ATM IFX/IFC.
In the CDMA base transceiver station BTS a bit-interleaving and de-interleaving is respectively performed in the encoder ENC in the baseband transmitter TX and the decoder DEC in the baseband receiver RX.
FIG. 2 shows a functional overview of the encoder ENC, where a plurality of data of individual user channels US1, US2, US3 are input as sequential packets including respective data bit sequences at {circle around (2)} into the ATM interface field programmable gate array FPGA ATM-IN. Upon channel coding in the FPGA CCOD-TCH interleaving is performed in the FPGA INTER-MOD at {circle around (3)}. That is, in FIG. 2 a number NUSCH of user channels (e.g. up to 300 different channels) input user data US at {circle around (2)} while control information CI for controlling the transmission of said data bit sequences is input at the digital signal processor DSP {circle around (1)} or generally by the FPGA INTER-MOD {circle around (3)}. The data bits plus their associated control information are interleaved and time-aligned in the FPGA modulator FPGA INTERMOD {circle around (3)} using a memory arrangement of 3 RAMs shown at {circle around (4)} and the interface FPGA RAM-IF1. The interleaved and time-aligned data is then transmitted to the baseband transmitter unit BBTX via the FPGA BBTX-OUT {circle around (5)}.
Thus, in addition to channel encoding and interleaving the encoder ENC in FIG. 2 combines data symbols from the user channels US1, US2, US3 . . . and control information CI, whereafter the combined information is provided to the baseband transmitter unit BBTX.
Data bits are provided in the form of code symbols representing one element of an alphabet of a digital modulation scheme such as QPSK or 16QAM. The control information associated with every code symbol is used to control other processing parts within the baseband transmitter unit BBTX. In general the BBTX unit spreads each code symbol to the common chip rate and performs a multiplication with the CDMA code and a weighting with a specific transmission power.
Furthermore, in such a transmitter, the data information of the user channel may be transmitted in individual frames. When several user channels are present, as is the case normally for example in a mobile radio communication system, then several user channels each provide digital data information which is to be inserted into the specific frames on the radio link between the transmitter of the base stations and the mobile stations. Each data frame may comprise data packets of several user channels which may arrive sequentially. Each packet is separately encoded and interleaved, before code symbols are formed and provided in parallel for all user channels to the CDMA modulator in the unit BBTX. The parallel processing towards the CDMA modulator is necessary because of the CDMA technique where all channels are added up prior to transmission.
Each packet thus contains a data bit sequence of a predetermined number of data bits (e.g. Mi bits) belonging to one user channel. The individual code symbols formed from the input data bit sequence in each packet may consist of e.g.
N=2 data bits representing the 4 possible states of a QPSK modulation (i.e. an I bit and a Q bit) and the control information CI may consist of e.g. L=4 control bits indicating specific control functions with respect to the corresponding code symbols.
As described above, in FIG. 2 a plurality of data of individual user channels US1, US2, US3, . . . are input as sequential packets comprising respective data bit sequences at {circle around (2)}. An interleaving is then performed in the FPGA INTER-MOD {circle around (3)} and the memory arrangement {circle around (4)}. In addition, control information CI is input to the DSP {circle around (1)}. Alternatively, the DSP {circle around (1)} or even the FPGA {circle around (3)} themselves may generate the control information CI. The control information is combined with the data bits, interleaved and time-aligned also in the FPGA {circle around (3)} together with the memory arrangement of the 3 RAMs shown at {circle around (4)}. The data bits in form of code symbols (representing one state of a digital modulation scheme) together with the associated control information is then transmitted to the baseband transmitter unit BBTX via the FPGA BBTX-OUT {circle around (5)}.
Although FIGS. 1, 2 show a special structure of a CDMA transmitter, generally, a digital transmitter using a frame-wise processing of data packets can be summarized as shown in FIG. 3. That is, a data source DS, provides digital data US in form of packets to a channel encoder CC. The channel encoder CC may be a convolutional encoder, however, also other codes may be used, e.g. block codes, turbo codes, etc. If the coder is a convolutional encoder it makes use of a specific rate and constraint length as predefined by the encoder polynomial. For example, the channel encoder ENC in FIGS. 1, 2 uses a convolutional coder with a rate r=1/2 and a constraint length c=9.
The channel encoded digital data output by the channel encoder CC are again data packets comprising a data bit sequence BS containing Mi data bits.
From the individual data bits of the data bit sequence code symbols each consisting of a number N of data bits are formed depending on the used digital modulation scheme. A write/read means W/R contains a selection means SM for extracting or selecting from the input data bit sequence BS data bits, which respectively belong to each other for forming such code symbols.
In a combining means COM the code symbols are combined with their corresponding control information CI (see for example FIG. 4). Then, the control information and the code symbols are provided as data bit sequence to an interleaver comprising an interleaving memory IM for performing the interleaving. Interleaving is an essential processing step in a mobile communication system to compensate errors introduced by flat fading more easily.
The write/read means W/R comprises a write means WM which writes the code symbols combined with the control information into the memory locations of the interleaving memory and a read means RM which reads out the stored information according to the interleaving scheme. The interleaved digital data sequence BS′ consisting of a specific number of code symbols Mi/N is output to the digital modulator MOD in the baseband transmitter unit BBTX which performs a modulation of the interleaved code symbols. For example, if the modulator uses a QPSK modulation, the bits are provided to the modulator as code symbols containing two bits, namely an I-bit and a Q-bit. The CDMA transmitter TX shown in FIG. 1 uses a QPSK modulation in the modulator BBTX. However, other digital modulation schemes can be used that require the provision of code symbols consisting of a different number of data bits. For example, a 16QAM method requires code symbols of four bits each and a 4QAM method requires code symbols of two bits each.
As is also seen in FIG. 3, the control information is read out together with the code symbols by the read means RM from the interleaving memory IM and is provided for example to the modulator MOD. For example, the control bits of the control information may indicate a frame start FS, a time slot start SS, a marker MA and/or a power bit PW for the respective code symbol. In particular, the power bit PW is an important control information used by the modulator MOD. Although FIG. 3 shows the provision of the control information to the modulator MOD only, this information can of course also be used in other units of the transmitter.
As described with respect to FIG. 3, the encoder ENC of the baseband transmitter TX comprises the channel coder CC, the combining means COM and a processing means formed by the interleaving memory IM and the write/read means W/R. However, having combined the control information and the code symbols in the combining means COM, a processing means may also take different forms depending on the specific processing desired in the transmitter for a specific modulation technique. However, conventionally the control information, i.e., the control bits, and the code symbols are processed separately in the processing means.
The invention should not be limited to the specific CDMA system or the transmitter shown in FIGS. 1, 2, 3, but any other processing scheme is applicable to the invention, as long as there is a need for processing the control information and code symbols, respectively data bits together.
Storage Problem of the Control Information and Code Symbols
In the course of the processing of the code symbols and the control bits in the processing means, there will always be the necessity to perform at least an intermediate storage of the information in a memory of the processing means, e.g. due to an interleaving process. Such a storage requirement may for example be satisfied by the interleaving memory IM.
Whilst the problem of how to store the data information together with the control information before transmission is thus a general problem that already occurs when considering only one user channel, of course, the problem becomes extremely severe when processing a great plurality of user channels (e.g. up to 300) as in FIGS. 1, 2, 3. The amount of data to be processed within each time interval of a frame (e.g. T=10 ms) gets very large. Therefore, the processing time and/or the memory requirements to perform channel encoding, bit-interleaving and time-alignment are very demanding.
FIG. 4 shows the conventional storage of data bits together with control bits in a memory, e.g. in the RAM memory shown in FIG. 2 or in the interleaving memory IM in FIG. 3. Such a combined storage is achieved by the conventional combining means COM as is shown in FIG. 3. The data bits and the associated control bits are listed in the rows, where each row is identified by an address. If data of a great plurality of user channels must be stored, preferably code symbols are formed before storing data to the RAM and the control bits are combined with such code symbols. This is possible as long as the control information is related to the code symbols finally transmitted over the air interface. Therefore, a set of two data bits in one row represents one code symbol of the data bit sequence which is to be transmitted.
As is shown in the example in FIG. 4, each data symbol (comprising two data bits) is used together with four control bits containing the control information and, if the memory positions only have a predetermined width of 4 bits, the complete information of 6 bits cannot be stored therein and thus the control information and the data symbols have to be stored in different memory locations (or different memories).
In addition, if the data symbols and a great variety of control information of many user channels has to be stored, a large memory, i.e., a large address space and many bits per address are necessary. Since it may be desired to store data symbols together with the control information for as many user channels as possible to keep RAM sizes and number of RAMs small, the memory should be configured such that as many memory positions as possible are available. For example, a 64 Kbit memory can be configured so as to have an address space of 16 kbit with a 4 bit width, while the same memory only has an address space of about 8 kbit with a bit width of 8. Thus, if data symbols of a specific length are to be stored together with a great variety of control information, obviously a large memory or more memories must be used or only a small number of user channels can be processed in a memory of a predetermined size.
FIG. 5 shows how conventionally each bit d0, d1 . . . of a code symbol etc. is stored at a separate memory location IM00, IM01 of an interleaving memory IM (or generally in a memory of a processing means). Already the separate storing of each individual bit of the data symbol thus requires a large memory. However, of course the situation becomes more severe, if also the control bits need to be stored in the interleaving memory together with the data bits. Furthermore, the large memory naturally increases the read/write access time to this memory as will be explained below. Moreover, if the control information (bits) belong to respective code symbols to be transmitted and each input data bit is stored separately, then the control information would have to be stored N-times (e.g. N=2 for QPSK).
Typical interleaving of an input data bit sequence BS comprising M data bits d0, d1 . . . dM−1 is shown in FIG. 5. FIG. 5 shows an interleaving matrix IM (i.e. in an interleaving memory) which is written row by row and read column by column for performing the interleaving of the data bits. Assuming that the input data bit sequence BS consists of M data bits and each bit is stored in its own memory location, then the interleaving matrix IM must have at least M memory locations IM00, IM01 etc. in an interleaver memory IM. The number of columns NW and the number of rows NR depends in fact on the interleaving depth which is here expressed as the number of columns before the writing of data bits jumps to the next row. The interleaving depth is always predetermined in an interleaver and if the interleaver depth is NW, then the storage of M data bits requires NR=┌M/NW┐ rows.
Conventionally, as is shown in FIG. 5, each data bit di of the input data bit sequence BS is stored at one memory location IMnw,nr defined by the respective row and column addresses nW=0, 1, 2 . . . NW−1 and nr=0 . . . , NR−1. As explained above, the interleaving process itself consists of a write and read process to and from the interleaving matrix in FIG. 5. Each of the processes (writing or reading) for all channels must be accomplished within a frame period when processing is performed in a frame-wise manner, but both processes have to be fast enough to be able to handle the great number of data packets of all users in the system within one frame period, even if the number of user channels US is very large.
For example, in FIG. 5, all data bits of one packet are written row by row starting in row 0 and all output bits are read column by column starting in column 0. Assuming the dimension of the bit-interleaving matrices to be M=NR*NW(number of rows*number of columns) the interleaving matrices must be filled completely by the data bit sequences contained in one frame in the predetermined time period of one frame. Afterwards the procedure is repeated in the next frame starting at rows 0 again. Therefore, in the afore-mentioned time interval of 10 ms each matrix has to be accessed (written or read) NR*NW times. And as packets arrive sequentially this writing or reading is also done sequentially.
In the conventional method during reading, the read means RM outputs the data bits as code symbols as required by the digital modulation method to the modulator MOD. For example, the read means RM may combine the bits d0 and dNW after two read cycles by accessing the respective two separate memory locations thereof and then provide the bits as code symbol to the modulator MOD.
It will be appreciated that a considerable amount of time is used to read and write the data if the number of user channels is large since all interleaver matrices are accessed sequentially. The time for accessing the matrices as well as the storage requirements for storing the matrices can therefore be very large when a great plurality of user channels is used or when the input data packets comprise a large number M of data bits. If, e.g., each data packet has M bits and U packets arrive in one frame, the total number of bits is either U*M bits (when each packet has the same length) or
      ∑          u      =      1        U                    M    u  bits (when the packets have different lengths) for u=1 . . . U.
Whilst FIG. 5 for illustration purposes only shows the storage of the data bits d, of course the situation becomes more severe concerning the storage requirements, if the input data bit sequence containing M data bits is extended to also comprise a plurality of control bits for each data bit respectively code symbol as shown in FIG. 4.

Interleaver and method for interleaving an input data bit sequence using a coded storing of symbol and additional information