A new and improved high visibility light signal apparatus for use on a bicycle includes a strobe light assembly which includes a source of electric power and a strobe lamp/driver assembly. A support assembly supports the strobe lamp/driver assembly on the bicycle. The support assembly includes a first end and a second end. The first end includes a lamp support for supporting the strobe lamp/driver assembly. The second end includes a connector for attaching the support assembly to the bicycle. The support assembly has a predetermined length; and the support assembly, in conjunction with the connector, is capable of supporting the strobe lamp/driver assembly on the bicycle in a plane spaced from and parallel to the longitudinal axis of the bicycle, such that light emitted from the strobe lamp/driver assembly is visible from the front, the left side, the right side, and the back of the bicycle and to the rider, simultaneously. The source of electric power may be an electric generator driven by rotation of a wheel of the bicycle or a battery.

1. Field of the Invention
The present invention relates generally to lights used on bicycles, and more particularly, to a light especially adapted for visibly signalling the presence of the bicycle to drivers of motor vehicles, other bicycle riders, and pedestrians.
2. Description of the Prior Art
Lights used on bicycles for visibly signalling the presence of the bicycle are well known in the art. The following U.S. patents disclose exemplary lights used on bicycles: U.S. Pat. Nos. 4,819,135; 4,860,177; 4,875,142; 4,974,124; and 5,015,918. More specifically, U.S. Pat. No. 4,819,135 discloses a plurality of flashing LED's placed in linear arrays along the bicycle frame. The LED's primarily face the side of the bicycle to provide a broadside visible signal. U.S. Pat. No. 4,860,177 has a plurality of parallel rows of lamps that flash in a moving pattern. The parallel rows of lamps face to the rear of the bicycle. U.S. Pat. No. 4,875,142 disclose bicycle safety lights that a secured to the ends of handle bars and face rearward, providing blinking light signals to drivers of vehicles at the rear of the bicycle. U.S. Pat. No. 4,974,124 discloses a headlight and accompanying electrical generator for a bicycle. U.S. Pat. No. 5,015,918 discloses a battery-powered and/or generator powered bicycle lighting system that employs circuitry for strobing LED's to provide high intensity flashes.
One problem associated with the above-described prior art bicycle light signalling devices is that the flashing signal lights are highly directional, primarily facing the rear of the bicycle or secondarily facing the side of the bicycle. They are not significantly visible from the front of the bicycle. In this respect, it would be desirable if a bicycle light signalling device were provided which directed a flashing light signal to the front of the bicycle.
Another problem associated with many conventional bicycle signal lights is that the bicycle rider is unaware when the signal light is burned out or otherwise malfunctioning. This can be a very dangerous situation. The rider may think that he is signalling his presence to drivers of motor vehicles, other bicycle riders, and pedestrians, but the signal may not be working. In this respect, it would be desirable if a bicycle signalling device were provided which gave an indication to the rider that the signal is either working or not working.
Many conventional bicycle signalling systems use large numbers of signalling elements. Such large numbers of elements can be quite expensive. Moreover, large numbers of lights may create a distraction to persons receiving the signal. In this respect, it would be desirable if a bicycle signalling device were provided which uses a single flashing signal light.
The prior art bicycle signalling devices discussed above include light signalling patterns where light alternates between on or off. During the off portion of the signal, the person being signalled may lose sight of the bicycle. Furthermore, an alternating on and off signal may be very fatiguing to the eyes of the person being signalled. In this respect, it would be desirable if a bicycle signalling device were provided which emitted two lighted state signals. That is, a first light signal having a first level of brightness and a second light signal having a second level of brightness.
As mentioned above, it is important that the bicycle rider be aware of whether as to the signalling lights are working or not. In this respect, it would be desirable, if in addition to the visible signal, a device were provided that gave an audible signal to the rider indicating that the signal light was operating.
As mentioned above, many prior art bicycle signalling lights are highly directional. In this respect, it would be desirable if a bicycle signalling device were provided that provided a visible signal in a pattern of nearly 360 degrees around the signal light.
Thus, while the foregoing body of prior art indicates it to be well known to use signal lights for bicycles, the prior art described above does not teach or suggest a high visibility bicycle light signal apparatus which has the following combination of desirable features: (1) directs a flashing light signal to the front of the bicycle; (2) gives an indication to the rider that the signal is either working or not working; (3) uses a single flashing signal light; (4) emits two lighted state signals, a first light signal having a first level of brightness and a second light signal having a second level of brightness; (5) gives an audible signal to the rider indicating that the signal light is operating; and (6) provides a visible signal in a pattern of nearly 360 degrees around the signal light. The foregoing desired characteristics are provided by the unique high visibility bicycle light signal apparatus of the present invention as will be made apparent from the following description thereof. Other advantages of the present invention over the prior art also will be rendered evident.


An exemplary system includes a sound processing unit configured to apply noise reduction to an audio signal in accordance with a noise reduction parameter, an implantable cochlear stimulator communicatively coupled to the sound processing unit and configured to apply stimulation representative of the noise reduced audio signal to a patient via one or more electrodes, and a user input facility communicatively coupled to the sound processing unit and that facilitates manual adjustment of the noise reduction parameter.

The sense of hearing in human beings involves the use of hair cells in the cochlea that convert or transduce audio signals into auditory nerve impulses. Hearing loss, which may be due to many different causes, is generally of two types: conductive and sensorineural. Conductive hearing loss occurs when the normal mechanical pathways for sound to reach the hair cells in the cochlea are impeded. These sound pathways may be impeded, for example, by damage to the auditory ossicles. Conductive hearing loss may often be overcome through the use of conventional hearing aids that amplify sound so that audio signals can reach the hair cells within the cochlea. Some types of conductive hearing loss may also be treated by surgical procedures.
Sensorineural hearing loss, on the other hand, is caused by the absence or destruction of the hair cells in the cochlea which are needed to transduce audio signals into auditory nerve impulses. People who suffer from sensorineural hearing loss are unable to derive any benefit from conventional hearing aid systems.
To overcome sensorineural hearing loss, numerous cochlear implant systems—or cochlear prosthesis—have been developed. Cochlear implant systems bypass the hair cells in the cochlea by presenting electrical stimulation directly to the auditory nerve fibers. Direct stimulation of the auditory nerve fibers leads to the perception of sound in the brain and at least partial restoration of hearing function.
To facilitate direct stimulation of the auditory nerve fibers, an array of electrodes may be implanted in the cochlea. The electrodes form a number of stimulation channels through which electrical stimulation pulses may be applied directly to auditory nerves within the cochlea. An audio signal may then be presented to a patient by translating the audio signal into a number of electrical stimulation pulses and applying the stimulation pulses directly to auditory nerves within the cochlea via one or more of the electrodes.
When a cochlear implant system is initially implanted in a patient, it is usually necessary to fit the cochlear implant system to the patient. Such "fitting" includes adjustment of a variety of control parameters governing the operation of the cochlear implant system to values that are most effective and comfortable for the patient. However, it is often difficult or impossible to determine optimal values for many control parameters because they depend on the particular listening environment in which the patient is located. For example, optimal noise reduction parameters may be different in a noisy listening environment than in a quiet environment.

Systems and methods of facilitating manual adjustment of one or more cochlear implant system control parameters


An environmentally sealed light fixture for illuminating potentially hazardous environments. The sealed light fixture includes multiple light modules that are independently rotatable to customize the direction of light emitted from the fixture. The fixture is also modular and scalable, enabling additional light modules to be added to increase lumen output or area coverage. The sealed light fixture includes sealed light chambers, electronics chambers, and sealed connections between the modules for maintaining the integrity as well as concealing the wiring and electrical connections within the light fixture.

Light fixtures such as area lights, particularly those used in outdoor applications or industrial environments, are exposed to harsh environmental conditions, including rain, dust, pollen, chemicals, temperature variations, ultraviolet light, and the like. In some indoor environments, the area lights can be exposed to dust and water. Exposure to such elements can degrade the light elements (such as light emitted diodes, "LEDs") and reduce the efficacy and light output of the area light over time. Traditionally, to protect the light elements a glass lens is added to the fixtures to keep harmful substances from entering the interior of the fixture. The glass diminishes the light output of the LEDs and even more so as it becomes scratched and/or discolored over time.
In addition, LEDs are typically mounted to a printed circuit board (PCB), with exposed electrical components that can be damaged or short-circuited by external elements, like mechanical objects or water. Moreover, wires are needed to supply power to the PCBs, and exposed wires are further susceptible to wear and tear over time. Wires also look unsightly, and the exposed surfaces of PCBs can be undesirable.
Moreover, many light fixtures designed for use in industrial or outdoor environments are formed with a single housing that houses both the light sources as well as the electrical components that power the light sources. In this way, the fixture is easier to seal and protect against the environmental elements and/or other harsh conditions. However, manufacturing limitations often limit the size that such fixtures can be. More specifically, it can be difficult to cast housings that are large enough to accommodate larger volumes of light sources and electronics desired and/or required for certain applications, such as illuminating parking lots and green spaces. Moreover, the electrical connections between the light sources and other electronics mounted to other parts of the housing require more exposed wire routing methods which require more complex assemblies for weatherproofing and aesthetic improvement to conceal aesthetically undesirable features required by the weatherproofing components.
Typical light fixtures rated for hazardous environments or rated for exposure to harsh environments are fixed and un-scalable. To the extent adjustable light fixtures have been provided, they typically are not adequately sealed against the environment to enable the use of such rotatable fixtures in harsh environments. There is a need for a light fixture that can be scaled up or down as desired to render it suitable for different applications all the while adequately protecting the fixture wiring and electronics for environmental conditions that can detrimentally impact operation of the light fixture.

Light fixture with rotatable light modules


A gravel pack completion with fluid loss control and fiber optic wet connect. In a described embodiment, a system for completing a subterranean well includes multiple assemblies installed in a wellbore. Each assembly has a fiber optic line. The fiber optic lines are operatively connected to each other after the assemblies are installed in the wellbore.

The present invention relates generally to operations performed and equipment utilized in conjunction with subterranean wells and, in an embodiment described herein, more particularly provides a gravel pack completion with fluid loss control and fiber optic wet connect.
While it is known to install a fiber optic line in a well completion, for example, to sense and monitor well parameters such as pressure and temperature in the completion, it has proven difficult to install the fiber optic line with the completion. In one system, a tube is strapped to the outside of a completion string as the string is installed in the well. The fiber optic line is then pumped down through the tube. In another system, the fiber optic line is contained in the tube or other protective sheathing as the completion string is installed in the well.
Unfortunately, such systems do not permit fiber optic connections to be made after the completion string is installed. In many situations, it may be desirable to install a completion in sections, such as when separately gravel packing intervals in a horizontal or highly deviated wellbore. In such situations, it would be beneficial to be able to connect fiber optic lines installed with the separate gravel packed sections. It would also be beneficial to be able to utilize fluid loss control devices with the separate gravel packed sections, and to utilize a travel joint for spacing out the completion string below a tubing hanger, for example.

Gravel pack completion with fluid loss control fiber optic wet connect


A device and method used to increase the resolution when imaging, measuring and inspecting wells, pipes and objects located therein. The device comprises an array of acoustic transducers that both transmit and receive acoustic signals. Scan lines may be overlapped by interlacing transmission and receiving windows thus increasing either the resolution or logging speed drastically compared to conventional approaches. The sequence of the scan lines making up an imaging frame is created by stratifying physically close lines and randomly selecting from within each stratum, preventing interference from neighboring transducers, signals and acoustic artifacts that fundamentally limit logging speed and resolution using conventional methods.

In wells and fluid carrying pipes, such as oil wells and water delivery infrastructure, there often arises a need to inspect the internal structure for integrity or obstructions. For example, hydrocarbons in production tubes may contaminate ground water if leaks Obstructions may be pipe deformations and items dropped, broken or left behind. Ultrasound is a known way of imaging such structures.
In some configurations, such as that taught in CA2989439 the ultrasound sensors are disposed radially around a collar of the device, each sensor facing generally outward towards the walls of the pipe or well. Each sensing element may be a piezoelectric transducer arranged to project most of its generated sound energy perpendicular to its top plane. This energy travels through the fluid medium and backscatters off the wall (and subsequent layers) to be absorbed by all transducers in the array.
If all the transducers are activated simultaneously and the device is centered in the well, each transducer will receive a first pulse that corresponds to its own generated pulse backscattering off the wall, following by additional pulses from the other transducers with their longer travel time. These additional pulses are confounded with each other and with each transducer's own pulses scattered from deeper layers.
Alternatively, transducers may be operated sequentially, whereby the first transducers transmits and then receives pulses before the second transducer starts transmitting. This avoids confounding of the various pulses. However, this restricts the linear scan rate of the device overall, as the device must wait for all transducers in a frame to transmit and receive before proceeding along the well.
The present invention aims to address one or more of the above shortcomings by operating transducers in a novel way.

Overlapped scheduling and sorting for acoustic transducer pulses


A dynamic random access memory (DRAM) includes a data signal input circuit configured to input a data signal in response to a data control signal, and a data strobe signal input circuit configured to input a data strobe signal in response to a data strobe control signal. A control circuit separately generates the data control signal and the data strobe control signal. A data latch circuit latches the data signal from the data signal input circuit in response to the data strobe signal from the data strobe signal input circuit. A memory cell array has a plurality of memory cells arranged in a matrix. The latched data signal is stored in a selected one of the plurality of memory cells through the data buffer, an amplifier circuit configured to amplify a data signal read out from the selected memory cell; and an output circuit configured to output the amplified data signal.

1. Field of the Invention
The present invention relates to a semiconductor memory device such as a DRAM, and a method of preventing a latch error in the same.
2. Description of the Related Art
Recently, a semiconductor memory device, e.g. a double data rate type a dynamic random access memory of (to be referred to as a DDR DRAM) is used mainly. Also, a synchronous DRAM in which a read and write operations are synchronous with a clock signal (to be referred to as an SDRAM) is popular.
FIG. 1 is a block diagram showing the configuration of a conventional DDR DRAM. Referring to FIG. 1, the conventional DDR DRAM is provided with an address circuit, a command circuit, a memory cell array 15, a data circuit and a clock circuit. The address circuit is composed of an address terminal group 10, an address input circuit 11, an address latch circuit 12, an address buffer circuit 13, and an address decoder 14. The command circuit is composed of a command terminal group (/CS, /RAS, /CAS, and /WE) 17, a command input circuit 18, a command decoder & mode register 19, a control circuit (1) 20, and a control circuit (2) 21. The clock circuit is composed of a clock terminal group (CK, /CK) 22 and 23, a clock input circuit & internal clock signal generating circuit 24, and a DLL circuit 25. The data circuit is composed of a data terminal (DQ) 26, a data strobe terminal (DQS) 27, a reference voltage (Vref) terminal 28, a data signal input circuit 30, a data strobe signal input circuit 31, a data latch circuit 32, a data signal output circuit 33, a data strobe signal output circuit 34, a data buffer & data amplifier 29, and a sense amplifier circuit 16. Although a plurality of data terminals may be provided, only one of the data terminals is shown here for convenience.
An address is supplied to the address input circuit 11 through the address terminal group 10, and then is latched by the address latch circuit 12. A part of the latched address is supplied to the command decoder and mode register 19. The latched address is supplied to the decoder 14 through the address buffer 13 and decoded and supplied to the memory cell array 15. The memory cell array 15 has memory cells arranged in a matrix and one of rows of memory cells is designated based on the decoded result. A command is supplied to the command decoder & mode register 19 through the command input terminal group 17 and the command input circuit 18. The command decoder & mode register 19 receives the address from the address latch circuit 12 and an internal clock signal (ICK) S1 from the input circuit & internal clock signal generating circuit 24 in addition to the command and outputs control signals to the control circuits 20 and 21. External clock signals CK and /CK are supplied to the clock input circuit & internal clock signal generating circuit 24 and the DLL circuit 25 through the external clock signal terminals 22 and 23. The clock input circuit & internal clock signal generating circuit 24 generates internal clock signal (ICK and /ICK) S1 and S2, and outputs the internal clock signal (ICK) S1 to the command decoder & mode register 19, the address latch circuit 12, the control circuit 21 and the data latch circuit 32, and the internal clock signal (/ICK) S2 to the data latch circuit 32. The DLL circuit 25 outputs a synchronous signal to the data signal output circuit 33 and the data strobe signal output circuit 34. The control circuit 20 outputs control signals to the address buffer 13 and the sense amplifier circuit 16. The control circuit 21 outputs control signals to the address buffer 13, the data buffer and data amplifier 29, the data signal output circuit 33 and the data strobe signal output circuit 34, and the data signal input circuit 30 and the data strobe signal input circuit 31. The data strobe signal input circuit 31 receives a data strobe signal and outputs it to the data latch circuit 32 as a signal S4. The data signal input circuit 30 receives an external data signal and outputs it to the data latch circuit 32. The data latch circuit 32 receives the data signal in response to the data strobe signal and outputs to the data buffer and data amplifier 29. The sense amplifier circuit 16 writes the data signal received from the data amplifier 29 through the sense amplifier circuit 16 into one memory cell of the memory cell array 15. A data signal read out from the memory cell array 15 by the sense amplifier circuit 16 is supplied to the data signal output circuit 33 through the data buffer and data amplifier 29. The data signal output circuit 33 outputs the read-out data signal through the terminal 26, and the data strobe signal output circuit 34 outputs the data strobe signal through the terminal 27. A reference voltage (Vref) terminal 28 is connected to the data signal input circuit 30, the data strobe signal input circuit 31, the address input circuit 11, and the command input circuit 18.
A typical operation of each section in the DDR DRAM will be described below briefly, because it is well known to a person in the art. The internal clock signals (internal ICK signal S1, internal /ICK signal S2) are generated by the clock input circuit & internal clock signal generating circuit 24 from external clock signals CK and /CK supplied through the clock signal terminals 22 and 23. The address signal is supplied to the address terminal group 10, passes through the input circuit 11 and then is latched by the address latch circuit 12 in response to the internal clock signal S1. Then, the address is generated and outputted to the memory cell array 15 from the address buffer 13 and the address decoder 14. The command signal is supplied to the command terminal group 17, and passes through the command input circuit 18 to the command decoder & mode register 19. Then, signals for various operations are generated by the command decoder & mode register 19 in synchronous with the internal clock signal ICK S1. Further, instruction or control signals for the various operations are generated by the control circuit 20 and the control circuit 21. In a write operation, the data signal is supplied to the data signal input circuit 30 and latched by the data latch circuit 32 in response to the output signal S4 from the data strobe signal input circuit 31. Then, this data signal is written into the memory cell of the memory cell array 15 from the data buffer 29. In a read operation, the data signal in the memory cell is amplified by the sense amplifier circuit 16 and the data amplifier 29, and then this data signal is outputted to the data terminal 26 from the data signal output circuit 33 in response to an output signal of the DLL circuit 25.
The data strobe signal terminal 27 is provided in the DDR DRAM for the following reasons. In the DDR DRAM, the data effective width is only 0.5 clock period which is a half of the data effective width in a conventional SDRAM. There is usually a signal timing difference in data transfer between a memory and a memory controller, thereby reducing a timing margin. Thus, as the clock period becomes faster, the timing margin for data latch becomes smaller. For this reason, a data strobe (DQS) terminal 27 is provided for a data latch signal. The data latch signal is used in a write operation, as a signal for latching the data signal on the data terminal 26 in the DDR DRAM. In a read operation, the data latch signal is outputted from the DDR DRAM in synchronization with the data signal outputted from the data terminal 26, and is used as a signal for latching the data signal on the data terminal on the memory controller side.
FIGS. 2A to 2J are timing charts showing signal waveforms of various sections of the DDR DRAM in the write operation the read operation when the burst length is 4. Referring to FIGS. 2A to 2J, the waveforms of the signals on the data terminal 26 and the data strobe terminal 27 in the write and read operations will be described below.
In the write operation, as shown in FIG. 2D, the data strobe signal on the data strobe terminal 27 goes to a low level a predetermined time after a write command shown in FIG. 2C is received. This initial low level period is called a preamble period. Subsequently, the data strobe signal on the data strobe terminal 27 toggles between the high level and the low level in accordance with data D1, D2, D3, and D4 on the data signal. An input setup time and an input hold time are set for each of data D1 to D4, as shown in FIG. 2E. In response to the data strobe signal on the data strobe terminal 27 which goes to a high level, the data D1 is latched. The data strobe signal is lastly changed from the low level state to a high impedance state when the input of the last data D4 is completed. This last low level state is called a postamble state. In the read operation, after a read command (READ) shown in FIG. 2H, four bursts of data D1, D2, D3, and D4 are outputted from the data terminal 26, following the CAS latency which is set in the mode register 19 based on a mode set command, as shown in FIG. 2J. The data strobe signal on the data strobe terminal 27 is toggled in synchronization with the clock signal after a preamble period, as shown in FIG. 2I, and then the data strobe terminal 27 returns to a high impedance state through the postamble state.
Next, the data circuit will be described. FIG. 3 is a block diagram showing the configuration of the data circuit. The data circuit includes the data signal (DQ) input circuit 30, the data strobe signal (DQS) input circuit 31, and the data latch circuit 32. The data latch circuit 32 includes D-type flip-flop circuits 321, 322, 323, 324, and 325. The data signal input circuit 30 and the data strobe signal input circuit 31 receives an input control signal S5 from the control circuit 21. Also, the data signal input circuit 30 receives the data signal (DQ) and the reference voltage signal (Vref), and the data strobe signal input circuit 31 receives the data strobe signal (DQS) and the reference voltage signal (Vref). The output of the data signal input circuit 30 is connected to data (D) terminals of the D-type flip-flop circuits 321 and 324, and the output of the data strobe signal input circuit 31 is connected to clock (C) terminals of the D-type flip-flop circuits 321 and 324. Here, the clock terminal of the flip-flop 324 receives the data strobe signal by inverting it. The data output terminal of the D-type flip-flop circuit 321 is connected to the data terminal of the D-type flip-flop circuit 322, and the data output (Q) terminal of the flip-flop circuit 322 is connected to the data terminal of the D-type flip-flop circuit 323. The data output terminal of the flip-flop circuit 323 is outputted to a data line (1). Also, the data output terminal of the D-type flip-flop circuit 324 is connected to the data terminal of the D-type flip-flop circuit 325. The data output terminal of the flip-flop circuit 325 is outputted to a data line (2). The internal clock signal /ICK S2 is supplied to the clock terminal of the D-type flip-flop circuit 322, and the internal clock signal ICK S1 is supplied to the clock terminals of the D-type flip-flop circuits 323 and 325.
The data signal input circuit 30 and the data strobe signal input circuit 31 are formed as shown in FIG. 4. The input circuit 30 or 31 includes P-channel MOS transistors 100, 101, and 105, N-channel MOS transistors 102, 103, and 104, and an inverter 106. The P-channel MOS transistor 100 and the P-channel MOS transistor 101 form a current mirror circuit. The N-channel MOS transistors 102 and 103 form a differential transistor pair. The P-channel MOS transistor 100 and the N-channel MOS transistor 102 are connected in series. Similarly, the P-channel MOS transistor 101 and the N-channel MOS transistor 103 are connected in series. The N-channel MOS transistor 104 is provided between the ground and a common emitter node between the N-channel MOS transistor 102 and the N-channel MOS transistor 103. Further, the P-channel MOS transistor 105 and the inverter 106 are connected in series such that a node between the P-channel MOS transistor 101 and the N-channel MOS transistor 103 is connected to a node between the P-channel MOS transistor 105 and the inverter 106. The reference voltage signal Vref and an input signal (the data signal or the data strobe signal) are supplied to the gates of the N-channel MOS transistors 102 and 103, respectively, and the input control signal is supplied to the gate of the N-channel MOS transistor 104 and the gate of the P-channel MOS transistor 105. Therefore, if the data strobe signal as the input signal has a glitch, the voltage of the drain of the N-channel MOS transistor 103 is changed in response to the glitch, and a pulse signal is generated by the inverter circuit 106.
FIG. 5 shows each of the D-type flip-flop circuits 321, 322, 323, and 325, and is composed of transfer gates 110, 111, 112, and 113, and inverters 114, 115, 116, 117, and 118. FIG. 6 shows the D-type flip-flop circuit 324 and is composed of transfer gates 119, 120, 121, and 122, and inverters 123, 124, 125, 126, and 127.
The data signal input circuit 30 and the data strobe signal input circuit 31 are activated in the write operation. FIG. 7 is a block diagram showing the configuration of a part of the control circuit 21 as an input control signal generating circuit that generates the input control signal S5, and includes a write control circuit 1, a NOR circuit 2, and an inverter circuit 3. The write control circuit 1 receives a write command signal, various mode signals, the internal clock signal ICK S1, and write control signals, and outputs an input control signal S9. The NOR circuit 2 receives the input control signal S9 and the write control signal S10 as one of the write control signals. The inverter circuit 3 inverts the output of the NOR circuit 2 and output a DQ/DQS input control signal S5.
Next, referring FIGS. 8A to 8R, an operation of the input control signal generating circuit shown in FIG. 7 will be described in detail. FIG. 8A shows an external clock signal CK, and FIG. 8B shows another external clock signal /CK that is obtained by inverting the clock signal CK. In the DDR DRAM, in response to the CK and the /CK, the clock input circuit & internal clock signal generating circuit 24 generates an internal clock signal ICK S1 that is synchronous with the rising edge of the clock signal CK and the falling edge of the clock signal /CK, as shown in FIG. 8F, and an internal clock signal /ICK S2 that is synchronous with the falling edge of the clock signal CK and the rising edge of the clock signal /CK, as shown in FIG. 8G. When a write command (WRITE) is inputted at a time t0 as shown in FIG. 8C, a write command signal is generated by the command decoder 19 in response to the rising edges of the internal clock signal ICK, as shown in FIG. 8H. The input control signal S9 is generated in response to the rising edges of the internal clock signal ICK, based on a mode signal indicating the burst length and generated by the mode register 19 in response to a mode set command, as shown in FIG. 8I, and the signal width of the input control signal S9 is equivalent to clock periods corresponding to a half of the burst length. Also, a write control signal S10 is generated as shown in FIG. 8J by delaying the input control signal S9 by a summation of clock periods corresponding to the write latency and one clock period. The write control signal S10 is activated during a period when data is written into the memory cell array 15.
In FIGS. 8A to 8R, the burst length is 4 and the write latency is 1. Thus, the input control signal S9 shown in FIG. 8I has the signal width of 2 clock periods, and the write control signal S10 shown in FIG. 8J is a signal obtained by delaying the input control signal S9 by 2 clock periods. A DQ/DQS input control signal S5 shown in FIG. 8K is generated based on the input control signal S9 and the write control signal S10 by the NOR circuit 2 and the inverter circuit 3. Thus, when at least one of the input control signal S9 shown in FIG. 8I and the write control signal S10 shown in FIG. 8J is in the high level, the DQ/DQS input control signal S5 shown in FIG. 8K is in the high level.
An output of the input circuit shown in FIG. 4 is fixed to a low level when an input is in the low level, whereas when the input is in the high level, a differential amplifier circuit, composed of the P-channel MOS transistors 100 and 101 and the N-channel MOS transistors 102, 103, and 104, compares the input voltage level with the voltage level Vref on the reference voltage terminal 28 to generate an output signal. Specifically, as shown in FIGS. 8A to 8R, in the data signal and data strobe signal input circuits, when the input control signal S5 shown in FIG. 8K is in the low level, an input circuit output signal 53 shown in FIG. 8M and an input circuit output signal S4 shown in FIG. 8L are fixed to the low level, whereas when the input circuit control signal S5 shown in FIG. 8K is in the high level, the input circuit output signal S3 shown in FIG. 8M and the input circuit output signal S4 shown in FIG. 8L change as a result of input of the data signal and the data strobe signal. Next, in the write operation, the data D1 is supplied from the data terminal 26 to the data latch circuit 32 as the input circuit output signal S3 shown in FIG. 8M. That is, in more detail, the input circuit output signal S3 is supplied to the D-type flip-flop circuit 321, latched by it in response to the rising edge of the input circuit output signal S4 shown in FIG. 8L, and outputted as the signal S6 shown in FIG. 8N. Subsequently, the data signal S6 shown in FIG. 8N is latched again by the D-type flip-flop circuit 322 in response to the rising edge of the internal clock signal /ICK S2 shown in FIG. 8G, transferred as a signal S8 shown in FIG. 8P to the D-type flip-flop circuit 323, then latched in response to the rising edge of the internal clock signal ICK S1 shown in FIG. 8F, and transmitted onto the data line (1) shown in FIG. 8Q. The data D3 is also processed in the same manner, Meanwhile, the data D2 is supplied from the data terminal 26 to the D-type flip-flop circuit 324 as the data signal input circuit output signal S3 shown in FIG. 8M, and latched by the D-type flip-flop circuit 324 in response to the falling edge of the input circuit output signal S4 shown in FIG. 8L. The data output terminal signal as a signal S7 shown in FIG. 8O is latched by the D-type flip-flop circuit 325 in response to the rising edge of the internal clock signal ICK S1 shown in FIG. 8F, and then transmitted to the data line (2) shown in FIG. 8R.
Next, an operation will be described in a case that the data strobe signal has a glitch on the change of the output from the postamble period state to the high impedance state. Referring to FIGS. 9A to 9N, a glitch waveform in the write operation appearing when the data strobe signal is reset to the high impedance state after the postamble period will be described in detail.
Portions surrounded by circles of dotted line shown in FIG. 9D shows a glitch waveform of the data strobe signal. The data strobe signal input circuit 21 generates the glitch waveform at around a time t6, and changes the data strobe signal input circuit output signal S4 shown in FIG. 9H at around the time t6. In the DDR DRAM, the data strobe signal is permitted to shift from side to side with respect to the external clock signal CK. Thus, the shift of 0.3 clock period is permitted in the DDR DRAM called DDR 1. FIG. 9D is a timing chart showing the signal waveform of the data strobe signal being shifted to the left with respect to the CK so that a malfunction due to the data strobe glitch waveform is likely to occur.
The data signal S3 is supplied to the data signal terminal 26 and latched by the D-type flip-flop circuits 321, 322, and 324 in order as mentioned above. Also, the data signal S3 is latched by the D-type flip-flop circuits 324 and 325 in order as mentioned above. However, the signal S3 is latched by the D-type flip-flop circuit 324 in response to the rising edge of the data strobe signal input circuit output signal S4 shown in FIG. 9H. For this reason, a latter half of the data D4 is latched again in response to the glitch waveform to be overwritten, as shown in FIG. 9K. Therefore, the data D1 and D3 are transferred to the data line (1) as shown in FIG. 9M in response to the rising edge of the next internal clock signal ICK S1 shown in FIG. 9F. Also, the data D2 is properly transferred to the data line (2) as shown in FIG. 9N although the overwritten data D4 is not transferred thereto. Therefore, a problem is caused that the data D1, D2, and D3 are properly written into the memory cells, but the data D4 is not properly written into the memory cell.
In conjunction with the above description, Japanese Patent No. 3317912 discloses a semiconductor memory device. In this conventional example of the semiconductor memory device, a synchronization signal input section inputs a synchronization signal for data acquisition and outputs an internal synchronization signal. An acquiring section acquires data in synchronous with the internal synchronization signal. A storing unit stores the data. A control section sets the synchronization signal input section to an enable state or a disable state in response to input of a write command for writing the data into the storing unit. The control section sets the synchronizing signal input section to the enable state to output the internal synchronization signal, when the write command is inputted, and also starts counting the number of clock of the internal synchronization signal. Also, the control section sets the synchronizing signal input section to the disable state when the count reaches a certain reference number of times.
Japanese Laid Open Patent Application (JP-P2000-156083A) discloses a semiconductor device. In this conventional example of the semiconductor device, a serial data signal as external data signals is successively latched in synchronization with a data strobe signal. Also, the latching of the serial data signal in the internal circuit is inhibited in response to a timing of change in the data strobe signal corresponding to the final bit of the serial data signal.
Japanese Laid Open Patent Application (JP-P2003-59267A) discloses a semiconductor memory device. In this conventional example of the semiconductor memory device, 2N (N is natural number) data signals are successively received in synchronization with N pairs of leading and trailing edges which are contained in an external clock signal. Also, an external data strobe signal has the N pairs of leading and trailing edges in synchronization with the 2N data signals and is set to a reference voltage after the passage of the postamble period following the last trailing edge. The 2N data signals are latched in synchronization with the N pairs of leading and trailing edges which are contained in the external data strobe signal. Further, in the semiconductor memory device, an input buffer outputs an internal data strobe signal in accordance with the external data strobe signal. A gate circuit receives the internal data strobe signal outputted from the input buffer and inhibits the passage of the internal data strobe signal in response to inactivation of a first control signal. A latch circuit sequentially latches the 2N data signals in response to each of the leading and trailing edges contained in the internal data strobe signal that has passed through the gate circuit. A control circuit sets the first control signal to an inactivated level in response to the Nth trailing edge included in the internal data strobe signal.
As described above, a conventional input control circuit suffers from a problem that, when a data strobe signal is received in a manner to be shifted with respect to the clock signal CK, a proper data signal cannot be written into a memory cell. The cause of the occurrence of this problem is as follows. This is because the data strobe signal input circuit operates in response to a glitch waveform after the postamble of the data strobe signal.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent application (JP-P2003-272379A). In this conventional example, a memory cell array is provided. A clock generating circuit generates first and second internal clock signals in synchronization with the rising and falling edges of an external clock signal. A clock selecting circuit selects as a first operation clock signal, one of the first and second internal clock signals in accordance with the number of cycles from reception of a data read command from the memory cell array to start of output of the read data from the memory cell array, and selects the other as a second operation clock signal. One or more signal recovering circuits recover a signal outputted from the clock selecting circuit. An output circuit outputs the read data in synchronization with the first and second clock signals which are subjected to the recovery by the signal recovering circuits.

Semiconductor memory device with no latch error


The present system and method transforms an input data stream in a first data format of a plurality of first data formats to an output data stream in a second data format of a plurality of second data formats. A plurality of input connector modules receive respective input data streams and at least one input queue stores the received input data streams. A plurality of job threads is operatively connected to the at least one input queue, each job thread, in parallel with at least one other job thread, formatting a stored input data stream to produce an output data stream. At least one output queue respectively stores the output data streams from the plurality of job threads. A plurality of output connector modules is operatively connected to the at least one output queue, the output connector modules supplying respective output data streams.

The field of the invention relates to data transformation, and more particularly, to apparatus and method for transforming an input data stream in a first data format of a plurality of first data formats to an output data stream in a second data format of a plurality of second data formats.
Businesses communication has become increasingly complex. The demands of business trends such as Customer Relationship Management and Supply Chain Management combined with emerging communication technologies, which allow business partners to share information instantly, are mainly responsible for this communication evolution. The number of business partners and the means with which they collaborate (using e-mail, fax, public internet and mobile devices) are steadily increasing. Adding to this complexity, a growing number of customers and suppliers require that the communication be tailored to their specific needs. In short, businesses today need to provide communication processes that are automated and personalized. Meeting this challenge requires a new understanding of business communications in the age of the Internet. Thus, there is a need for better control of the complexity of business communication.

Method and system for transforming input data streams


An immunoassay plate for an immune complex transfer immunoassay, comprising a well type solid phase and a dip stick type solid phase which can be inserted into said well type solid phase, wherein the dip stick type solid phase is coated with either substance (A) or (B) to be mentioned below and the well type solid phase is coated with the other, remaining substance, and these solid phases are used as the two solid phases to be used for an immune complex transfer immunoassay:. (A): a substance having a reactive group which specifically binds to a functional group previously introduced onto a substance, which specifically forms an immune complex with a test substance PA1 (B): a substance having a reactive group capable of specifically binding to the test substance in the immune complex, a substance which specifically forms an immune complex with the test substance, or a functional group conjugated in advance with said substance, provided that the moiety which binds to the reactive group of (A) does not bind to the reactive group of (B) and vice versa. According to the present invention, an immune complex transfer immunoassay can be markedly simplified. Consequently, a highly sensitive immune complex transfer immunoassay can be conducted with ease and with high precision.

An immunoassay is an advantageous method for determining and analyzing an antibody substance or an antigenic substance in that it is simple and has high specificity.
In particular, an immune complex transfer immunoassay is known to suitably suppress adsorption of contaminant protein onto solid phase and thereby-caused occurrence of background signals, which are the defects of sandwich method, and enable high sensitivity assay of an antibody substance or an antigenic substance in a test solution.
As used herein, the antibody substance or antigenic substance to be assayed in a test solution is referred to as test substance.
An immune complex transfer immunoassay is an immunoassay comprising, for example, two cycles of trapping using a pair of solid phases. The operation thereof is schematically explained by referring to an assay of antibody, as an example, from among the test substances. For the explanation's sake, one solid phase from the pair of solid phases, which is used for the first trapping, is referred to as the first solid phase and the other solid phase used for the next trapping is referred to as the second solid phase.
The typical immune complex transfer immunoassay comprises the following steps.
(a) An antigen modified with a functional group and a labeled antigen are bound to a target antibody to form an immune complex having a structure of "functional group-antigen-antibody-antigen-label" as shown, for example, in FIG. 5(a) with a reference number 50.
(b) The immune complex is trapped on a first solid phase via a certain moiety (functional group bound to the antigen in this case) in the immune complex. The immune complex may be trapped after being formed in a test solution or may be completed with respect to one end (functional group) thereof trapped earlier on a solid phase.
(c) The immune complex is released from the first solid phase in a solution used for transferring the immune complex.
(d) The immune complex is trapped on a second solid phase. The moiety of the immune complex which is used for the trapping is different from the moiety used in (b).
(e) The target antibody in the immune complex is assayed using the label conjugated in (a).
More detailed explanation and working examples of immune complex transfer immunoassay are found in the following literature.
(1) ISHIKAWA, E., HASHIDA, S., KOHNO, T., Development of ultrasensitive enzyme immunoassay reviewed with emphasis on factors which limit the sensitivity, MOLECULAR AND CELLULAR PROBES, 5, pp 81-95 (1991) PA1 (2) ISHIKAWA, E., HASHIDA, S., KOHNO, T., et al., Principle and applications of ultrasensitive enzyme immunoassay (Immune complex transfer enzyme immunoassay) for antibodies in body fluids, J. CLIN. LABORATORY ANALYSIS, 7, pp 376-393 (1993) PA1 (3) U.S. Pat. No. 5,236,849 and EP 303229 entitled Method of high sensitivity immunoassay PA1 (4) U.S. Pat. No. 5,236,830 and EP 368273 entitled Novel method for assaying antigen PA1 (5) ISHIKAWA, Eiji, Ultrasensitive enzyme immunoassay, Gakkai Shuppan Center (1993) PA1 (a) a step comprising coating an antibody on a dip stick type solid phase, and dipping the dip stick type solid phase in a test solution in a well type solid phase to trap the assay target, and PA1 (b) a step comprising rinsing the dip stick type solid phase, dipping same in a marker solution placed in a different well type solid phase and assaying the assay target. PA1 (a) coating a sustained release marker dissolved in a sucrose solution and the like on a well type solid phase, PA1 (b) placing a test solution in the well type solid phase, and PA1 (c) dipping an antigen-bound dip stick type solid phase in said test solution, thereby trapping the assay target antibody and simultaneously binding the marker. PA1 (A): a substance having a reactive group which specifically binds to a functional group previously introduced onto a substance which specifically forms an immune complex with a test substance PA1 (B): a substance having a reactive group capable of specifically binding to the test substance in the immune complex, a substance which specifically forms an immune complex with the test substance, or a functional group previously introduced onto said substance, provided that the moiety which binds to the reactive group of (A) does not bind to the reactive group of (B) and vice versa. PA1 (C): at least three positions determined on the periphery of the body of the dip stick type solid phase, wherein the distance between the positions is that which prevents the body of the dip stick type solid phase from contacting the well type solid phase when protrusions are formed at all of these positions.
In the conventional immune complex transfer immunoassay, plastic balls called beads having a diameter of about 3 mm are used as the first and the second solid phases. The beads are stirred in a test tube to perform the above-mentioned immune complex transfer immunoassay comprising the steps (a) to (e).
This method requires each one of the beads to be removed from and placed into test tubes with tweezers upon visually discriminating the two kinds of beads, thus raising problems in terms of handling easiness and the possibility of contamination of test tubes caused by carrying immune complex between test tubes with tweezers.
In addition, the possibility of a trace amount of immune complex released from the first solid phase contacting the second solid phase is very low, and only when a substance coated on the second solid phase has high affinity for the binding site of the immune complex, sufficient trapping is accomplished, which in turn results in a tendency that the amount of signals becomes less.
For conventional immunoassay, there have been known assay plates wherein a dip stick type solid phase and a well type solid phase are combined.
U.S. Pat. No. 3,826,619 describes:
The dip stick type solid phase used in these steps functions merely as a means for trapping the assay target, and the well type solid phase is nothing but a container to keep a solution.
Japanese Patent Application under WO 82/00058 teaches a special one step sandwich immunoassay using the above-mentioned assay plate wherein the dip stick type solid phase and the well type solid phase are combined, which comprises:
This method rather resembles the method using the immunoassay plate of the present invention in that it uses a well type solid phase and a dip stick type solid phase in combination. However, the well type solid phase only functions as a marker carrier, and to improve assay target-marking performance.
In contrast to the immunoassay using conventional plates, an immune complex transfer immunoassay comprises a specific process of transferring an immune complex containing a trace amount of an assay target from the first solid phase to the second solid phase, but an immunoassay apparatus capable of sufficiently accomplishing the transfer process has not been known.
Hence, there has been a demand for the development of an immunoassay apparatus capable of performing immune complex transfer immunoassay with ease and at high sensitivity, which can be suitably applied to clinical tests.

Sumitomo Pharmaceuticals Company, Limited.


An ankle brace comprising ankle anchor strap (7) adapted to attach to the ankle of a user above the ankle joint and a heel support (5) adapted to fit under and support the heel of the user. A first bracing strap (11) extends from a point at or adjacent to a rear portion of the heel support (5) to a point at or adjacent a front portion of the ankle anchor strap (7) when each is fitted to the foot of said user. A second bracing strap (11) extends from a point at or adjacent to a front portion of the heel support (5) to a point at or adjacent a rear portion of the ankle anchor strap (7) when each is fitted to the foot of said user said first and second bracing straps (11) extending around an outer side of the user's ankle in use and each adapted, in use, to apply a tensile force to the heel support (5) so as to seek to raise the outer side of the user's heel.

Summarized below are six different types of devices used for supporting, bracing and splinting ankles. A brief critique on each type is also provided in an attempt to bring to light their limitations. Orthotic type devices with rigid and semi-rigid moulded heel cups are not discussed here since they require specialized preparation, are not off the shelf products, and require--customized fitting. This type is also the most restrictive of athletic performance.
Type-1: All purpose elastic or neoprene wraps (long strips with hook and loop-type closure options)
This type is claimed to be a universal device which is used for applying compression to the effected area (the ankle in this case) by wrapping tightly. In the case of the neoprene it also provides thermal support. This type offers very little structural support and is both difficult and time consuming to apply. In cases of self application it is especially difficult if one suffers from injury pain and/or due to a lack of agility has limited reach. Tight wrapping may effect circulation. Any firmness in fit achieved is reduced significantly soon after use. It can become bulky (especially the neoprene straps) and there is no adjustment of fit possible once applied. They can become complicated since the tail end must come to rest at a certain point to complete closure (typically by hook and loop-type fasteners).
Type-2: Figure-eight elastic sock with open toe and heel.
This type is also for applying compression. They are simpler, less bulky and much easier and less time consuming to put on than Type-1. Once again it offers token structural support. The device is fixed for a given size and allows no provision to adjust or control the final fit. In cases where the user is experiencing pain in the region it is very difficult to put on and to take off. There are not enough device sizes to effectively fit the wide range of ankle/foot size variations. The device assumes that the foot is symmetric in geometry without complicated topography. This leads to uneven distribution of applied compressive pressure due to uneven stretching of the elastic.
Type-3: Neoprene or neoprene like material sock types with a variety of options. Some with open toes and/or heels, some with a zipper or hook and loop-type fasteners on the front or the side for easier access.
These are simple devices designed mainly to provide thermal support and some compression. They are softer and more comfortable than plain elastic, offer less compression and little structural support. With additional features they can become bulky. The devices are usually symmetrically prepared (assuming the lateral foot topography is identical to the interior) making them applicable to either the left or the right foot. Since this is not a realistic assumption an uneven distribution of compressive pressure is established. As in the previous case, most of these devices have no control features for achieving a desired final fit once applied. There are not enough device sizes to effectively fit the wide range of ankle/foot size variations. They are very difficult to put on and take off if the wearer suffers pain in the region (this includes the type with closures on the front or sides).
Type-4: Various Combinations of Types 2 and 3
This type of device provides a neoprene sock base onto which an elastic system is overlapped. It proposes a bulkier solution to the previous but with better control of final fit. The restraint provided is still very little and only compressive pressure onto the ankle region may be adjusted for. These devices suffer from identical limitations outlined in Types 2 and 3 above.
Type-5: Non stretch canvas or nylon or synthetic leather based braces with lace-up hook and loop-type fasteners and buckle combination frontal closure options and with thin plastic plate or flexible metal inserts.
These are currently claimed to be the most support providing splints in the market. Their potential of preventing injury and providing after injury support seems to be grossly overrated when the difficulties presented and their limitations imposed upon general performance are investigated.
They offer only passive restraint. They are heavy, bulky, very cumbersome and take a long time to put on. They require a fair degree of forcefulness to apply and if already injured and suffering pain then it is close to impossible to apply. Since they are made from non stretch materials, the splints are incapable of forming perfectly onto the lower leg, ankle and foot topography all at once. This produces uneven compression on the applied region. The plastic inserts are plate-like and incapable of perfectly forming to the region. The flexible metal inserts do little to provide stability. Both insert types and other typical rigid fixtures such as buckles and lace eyelets cause discomfort soon after application. In most cases, the base component onto which all other attachments are sewn on to are symmetrically cut and composed, once again wrongly assuming a symmetric foot topography. This fact further limits the effectiveness of the final fit. They appear not to facilitate any traction between the inner shoe and the outer splint surfaces since all outer surfaces are both shiny and slippery. They are complicated in design requiring many components and a wide range of specialised sewing processes to manufacture. They are expensive and not user friendly. All final fit adjustments must be made outside the shoe. In order to alter the fit, one must begin the lacing or hook and loop-type strapping process all over again. General performance is compromised for those using the splints as an injury prevention measure due to mainly the rigid nature of the designs and the inherent restrictions that they impose. The designs possess no reactive features that tend to recover the foot to the healing position when it experiences forced adverse movement such as inversion. Furthermore, even though the splints are tightly laced up or hook and loop-type strapping is applied tightly, there still appears to be some freedom of movement within the splint. There is only token traction between the outer ankle/foot and the inner splint surfaces to stop local movement from taking place. General professional feedback perceives this type to be ineffective and totally awkward.
Type-6: Traditional taping by skilled trainers, sports conditioners and physiotherapists.
Perceived generally by athletes to be the most effective for protection and prevention purposes. There is less slippage experienced. It takes extremely long to apply. One must be a trained professional to apply it correctly. It cannot be self applied effectively due to the reach factor. There needs to be good communication between the applier and the user for continuous adjustment during application. Further corrective adjustments cannot be made once application is completed. New strapping tapes must be used every time. Even though individual tapes are inexpensive, when one considers accumulated costs over time of the tapes and the time of a paid trainer who applies it, then the costs become very significant very quickly. Taping provides only passive restraint. The effect of such restraint is reduced dramatically after only a short period of exercise leading to increased play and possibly becoming slippery inside the shoe.
The present invention seeks to overcome or least ameliorate the problems and disadvantages of the prior art outlined above.


A temperature monitoring device for an injection unit of an injection molding machine is provided with a heater to heat a nozzle and a heating cylinder, a temperature sensor to detect a current temperature of the nozzle and the heating cylinder or around the heating cylinder, and an electromagnetic locking device to prohibit a safety door from opening when the current temperature detected by the temperature sensor exceeds a predetermined opening operation prohibited temperature.

1. Field of the Invention
The present invention relates to a temperature monitoring device for a heating cylinder of an injection molding machine.
2. Description of the Related Art
In general, an injection device of an injection molding machine comprises a heating cylinder and a nozzle. The heating cylinder is used to heat and melt a molding resin and maintain the molten state of the resin. The nozzle is attached to the distal end of the heating cylinder and serves to inject the resin melted in the heating cylinder into the cavity of a mold. The temperatures of the heating cylinder and the nozzle are controlled without deviation to a preset temperature such as to maintain the molten state of the resin, by using temperature measuring unit such as a thermocouple or heating unit such as a heater. The necessary temperature of the heating cylinder for the maintenance of the molten state of the resin is determined to be, for example, 200 to 450° C., depending on the type of the resin. A stable molding operation can be continuously performed by maintaining this necessary temperature.
If an operator touches the heating cylinder or the nozzle at such a high temperature as to molt the resin, during the molding operation or in a stop mode, he/she may possibly get burned. In some cases, moreover, the resin heated and melted in the heating cylinder may be ejected from the nozzle, and the operator may be burned by touching the ejected resin.
Conventionally, a protective cover as a unit configured to covert a heating cylinder to avoid the possibility of a burn or the like described above is attached to the heating cylinder (Japanese Patent JPH9-1613A and JP2000-108187A). During a molding operation, however, a resin melted in the heating cylinder is injected into the cavity of a mold through the tip of a nozzle. Therefore, the operation must be performed with an injection device advanced by the drive of a nozzle-touch motor or a hydraulic device and with the nozzle on the distal end of the heating cylinder pressed against the mold on a stationary platen of an injection molding machine. Accordingly, part of the heating cylinder or the nozzle is not covered by the protective cover.
In some cases, therefore, openable safety doors are attached around a heating cylinder or a nozzle. Some openable safety doors are designed to entirely cover a heating cylinder and a nozzle or an injection device. Other openable safety doors are designed to cover a heating cylinder and a nozzle only partially.
In a technique disclosed in Japanese Patent JP2007-225019A, a machine is provided with an electromagnetic lock as a unit configured to lock openable safety doors. The operation of this machine can be stopped to release the electromagnetic lock by opening the safety doors. According to this technique, the electromagnetic lock can be released to allow the safety doors to open when the machine is stopped. If the machine is stopped so that the safety doors can be opened, however, the temperature of the heating cylinder is not always reduced to a safe level.
Specifically, even if temperature control by heating devices is suspended as the operation is stopped, the current temperature of the heating cylinder continues to be high for a while and will not be reduced to a safe level such that an operator can touch the cylinder. Further, it is necessary to start the temperature control of the heating cylinder by the heating devices before the start of the operation so that the resin in the heating cylinder is melted in advance. In some cases, therefore, the heating cylinder may stay hot even when the machine is stopped.
Japanese Patent JP2003-191308A discloses a technique in which a display device displays an indication to the effect that a heating cylinder is hot or an operation command to lock safety doors. However, there is no disclosure to the effect that the safety doors should be locked based on the current temperature of the heating cylinder.
In the prior art techniques, as described above, the safety doors can be opened and closed without considering the current temperature of the heating cylinder or the nozzle, so that the possibility of an operator getting burned by touching the heating cylinder cannot be eliminated.

Temperature monitoring device for injection molding machine


A continuous-flow steam generator includes a combustion chamber having a number of burners for a fossil fuel and a gas-tight containment wall formed from at least approximately vertically disposed evaporator tubes through which a flow passes upwards from below on the feed-water side. A method and a system for starting up the continuous-flow steam generator avoid start-up losses by setting a water level in the evaporator tubes and a ratio of the fuel stream to the feedwater stream in such a way that the water evaporates completely during passage through the evaporator tubes, so that water is no longer present at the evaporator outlet. A start-up system having a setting device for setting the water level in the evaporator and for setting the ratio of the fuel stream to the feed-water stream, is used for this purpose.

FIELD OF THE INVENTION
The invention relates to a method for starting up a continuous-flow steam generator including a combustion chamber having a number of burners for a fossil fuel and a gas-tight containment wall formed from at least approximately vertically disposed evaporator tubes through which a flow passes upwards from below on the feed-water side. The invention also relates to a start-up system for carrying out the method.
In a continuous-flow steam generator, the heating of vertically disposed tubes of an evaporator, which form a gas-tight containment wall of a combustion chamber, leads to a complete evaporation of a flow medium in the evaporator tubes in one pass. Conventionally, during start-up, a circulating stream is superposed on the continuous stream through the evaporator and frequently also through a preheater or an economizer disposed in the continuous-flow steam generator and is heated by flue gas. As a result, the tubes are to be reliably cooled through the use of correspondingly high velocities in the tubes. In that case, with regard to vertically disposed tubes in the containment walls of the combustion chamber, a minimum stream including the continuous stream and the superposed circulating stream is between 25% and 50% of the full-load stream. Accordingly, during start-up, the steam generator load first has to be increased to at least 25% to 50% before reaching continuous-flow operation that is advantageous in terms of efficiency, with its high steam outlet temperatures.
Therefore, as is known from Published European Patent Application 0 054 601 A1, a quantity of flow medium to be conveyed by a feed pump is conventionally preferably kept constant for the start-up and in a load range lying below a specific limit load of 50% of the full load. In that case, the conveying stream of the feed pump is equal to the evaporator throughput. In that mode of operation, the start-up times commencing with the ignition of a first burner of the continuous-flow steam generator and terminating when continuous-flow operation with its high steam temperatures is reached, are very long. That results in relatively high start-up losses since their magnitude is influenced essentially by the start-up times.
High start-up losses also arise from a water excess. That occurs, on one hand, as a result of a mass water flow which is high in comparison with the heat supplied and, on the other hand, as a result of the so-called water ejection. The latter in turn occurs when evaporation commences in the middle of the evaporator and pushes out the water quantity that is present downstream (water plug). Consequently, a continuous-flow steam generator conventionally has a separation device, out of which excess water is drawn off and either supplied again to the evaporator through the use of a circulating pump or discarded. The end of evaporation is thus fixed in that separation device during start-up. A start-up system having a separation device of that type and an additionally required separating vessel, valves and a circulating pump, along with the high technical outlay, necessitate high investment costs which increase sharply when the implementation of high and very high steam pressures is desired.

Method and system for starting up a continuous flow steam generator


A bitumen mixture for high-performance overlayment roofing membranes having an only minimally higher SBS rubber content, compared with simple roofing membranes, and a comparatively high filler content. The bitumen mixture provides high-quality overlayment roofing membranes having a distinctly reduced SBS rubber content, compared to prior art overlayment roofing membranes, coupled with a nonetheless high filler content.

1. Technical Field
The invention relates to a bitumen mixture for high-quality built-structure waterproofing systems, namely a bitumen mixture for an overlayment roofing membrane comprising at least distillation bitumen, SBS rubber and at least one filler.
2. Prior Art
Built-structure waterproofing systems comprising bitumen mixtures are used as roofing membranes, bridge waterproofing systems, basement envelopes and the like. Roofing membranes are used as roof waterproofing systems in the flat-roof sector in particular. Such roof water-proofing systems are generally made multilayered by disposing an overlayment roofing membrane on at least one underlayment roofing membrane. The overlayment roofing membrane, which is exposed to the elements and in particular high mechanical and thermal stresses, has to meet particularly high requirements. Therefore, overlayment roofing membranes, like other highly stressed built-structure waterproofing systems, are produced from high-quality bitumen mixtures. Such high-quality bitumen mixtures are based on polymer-modified bitumen. Polymer-modified bitumen is appreciably more costly than oxidic bitumen, used for example to produce roofing membranes which have to meet lower requirements, such as underlayment roofing membranes for example.
Both oxidic bitumen and polymer-modified bitumen are based on distillation bitumen. In the case of polymer-modified bitumen, distillation bitumen is modified with suitable polymeric materials of construction, such as SBS rubber or APP (atactic polypropylene), while in the case of oxidic bitumen the distillation bitumen is progressively oxidized at high temperatures of about 280° C. by addition of oxygen.
Distillation bitumen is inherently very soft and therefore cannot be used alone as bitumen material for high-quality built-structure waterproofing systems, in particular overlayment roofing membranes. To meet the requirements of high-quality built-structure waterproofing systems, the SBS rubber content has to be at least 10% by weight. Because SBS rubber is very costly, this greatly adds to the cost of the bitumen mixture.
Bitumen mixtures are admixed with fillers to reduce cost. The most common fillers are slate flour or limestone flour. Owing to the high viscosity, it is generally not possible to produce bitumen mixtures having a filler content of more than 30% by weight. This holds for high-quality built-structure waterproofing systems in particular.


The present invention provides a new human GPI2 homolog (GPI-2h) and polynucleotides which identify and encode GPI-2h. The invention also provides expression vectors, host cells, antibodies, and antagonists. The invention also provides methods for the prevention and treatment of diseases associated with expression of GPI-2h, as well as diagnostic assays.

A wide range of cell-surface proteins, including enzymes, coat proteins, surface antigens, and adhesion molecules, are attached to plasma membranes via glycosyl-phosphatidylinositol (GPI) anchors. GPI anchors are also proposed to function in protein targeting, transmembrane signaling, and in the uptake of small molecules (endocytosis). GPI anchors of plasma membrane proteins are present in eukaryotes from protozoa and fungi to vertebrates (Doering, T. L. et al. (1990) J. Biol. Chem. 265:611-614; McConville, M. J. et al. (1993) Biochem. J. 294:305-324).
GPI anchor precursor molecules are synthesized in the endoplasmic reticulum (ER) by the sequential addition of carbohydrate and other moieties to phosphatidylinositol (PI). The GPIs are transferred to the C-termini of proteins in the ER lumen. The GPI-anchored proteins are then transported to the cell surface via the secretory pathway.
The first step in GPI assembly is the transfer of N-acetylglucosamine (GlcNAc) from UDP-GlcNAc to PI to form the intermediate GlcNAc-PI. In both yeast and mammals this process involves at least three proteins (Leidich, S. D. et al. (1994) J. Biol. Chem. 269:10193-10196; Hyman, R. (1988) Trends Genet. 4:5-8). The genes encoding three proteins involved in GlcNAc-PI formation in the yeast S. cerevisiae, GPI1, GPI2, and GPI3, have been cloned. The isolation of conditionally-lethal mutants of these three proteins has demonstrated that the first step in GPI assembly is essential for yeast viability (Leidich, et al. (1994), supra; Leidich, S. D. et al. (1995) J. Biol. Chem. 270:13029-13035). Human homologs of GPI1 and GPI3 have been cloned and expressed (Watanabe, R. et al. (1996) J. Biol. Chem. 271:26868-26875).
Paroxysmal nocturnal hemoglobinuria (PNH) is a disorder linked to defective GPI anchor biosynthesis. PNH is an acquired blood disorder which results from a somatic mutation in hematopoietic stem cells. Red blood cells arising from the PNH stem cells are highly sensitive to complement-mediated lysis and are prone to intravascular hemolysis. PNH may evolve to aplastic anemia or to acute leukemia. PNH cells are deficient in membrane surface GPI-anchored proteins due to defects in GPI biosynthesis (Hillmen, P. et al. (1993) Proc. Natl. Acad. Sci. USA 90:5272-5276).
GPI anchors play a role in sorting and directing proteins to distinct regions of the plasma membrane (reviewed in Turner, A. J. (1994) Essays Biochem. 28:113-127). GPI anchoring normally correlates with localization to the apical rather than the basolateral surface of polarized epithelial cell lines. In hippocampal neurons, the GPI-anchored Thy-1 glycoprotein is directed exclusively to axonal membranes. The GPI anchor may direct transport of the modified proteins to the apical cell surface by way of apical transport vesicles from the trans-Golgi network. A similar mechanism may operate in neuronal cells (Turner, supra).
GPI anchors also play a role in clathrin-independent endocytosis of small molecules into cells. GPI-anchored receptors for these small molecules cluster on the plasma membrane surface in specialized regions called the caveolae. These caveolae appear as flask-shaped invaginations in electron micrographs. Binding of ligand, for instance 5-methyltetrahydrofolate to the folate receptor, induces the caveolae to close, pinch off, and internalize the receptor and its ligand. Small molecule uptake is facilitated by GPI-anchored enzymes on the surface of the caveolae which hydrolyze peptides, nucleotides, and carbohydrates so that the digested products are concentrated in caveolae and internalized (Turner, supra).
Protozoan parasites cause widespread and debilitating diseases in humans and domestic livestock throughout the tropics. Examples of these diseases include malaria (caused by Plasmodium falciparum), African sleeping sickness and the cattle disease nagana (caused by Trypanosoma brucei), Chagas' disease (caused by Trypanosoma cruzi), and kala azar, espundia, and Oriental sore (caused by Leishmania sp.). There are no vaccines against these diseases, and most of the available drug treatments are toxic and/or ineffective. Recently, the emergence of drug resistant Plasmodium have placed malaria back into this category. The World Health Organization has identified the development of new and safer treatments for these diseases as a major priority.
Carbohydrate structures fixed into the parasite membrane by GPI membrane anchors play vital roles in the life cycles of these parasites. The use of GPI anchors is far more pronounced in parasites than in animal cells; in fact, GPI-anchored proteins dominate the molecular architecture of the parasite cell surface. In several cases, GPI-anchored proteins, such as the variant surface glycoprotein (VSG) of the African trypanosomes, or GPI-related glycolipids, such as the lipophosphoglycan (LPG) of Leishmania, are known to be essential for parasite survival and infectivity (Ferguson, M. A. et al. (1994) Parasitology 108: S45-54). Functional differences between some GPI-anchor biosynthetic enzymes of protozoan parasites compared to mammals have been noted (Guther, M. L. et al. (1994) J. Biol. Chem. 269:18694-18701).
Fungal infections are also major health problems, especially among immunocompromised individuals, such as those patients receiving immunosuppressive therapy to prevent transplant rejection or to treat neoplastic diseases, inflammation, or human immunodeficiency virus (HIV). Infectious agents which do not normally cause disease in immunocompetent hosts cause serious disease in those who lack a complete immune system. For example, pulmonary infections by fungi such as Histoplasma sp. and Coccidioides immitis may be fatal in immunocompromised individuals, young children, or elderly patients. Patients with diabetes mellitus or hematologic malignancy, or those receiving broad-spectrum antibiotics or high doses of adrenal corticosteroids, are especially susceptible to tissue invasion by Candida. Aspergillus is another widespread fungus which does not commonly cause disease except in immunocompromised patients.
Discovery of a new human GPI2 homolog and the polynucleotides which encode it satisfies a need in the art by providing new compositions useful in diagnosing, preventing, and treating disorders associated with GPI-anchored proteins. Knowledge and expression of sequences encoding human GPI2 homolog is also useful for developing therapeutic agents to prevent or treat diseases associated with fungal and parasitic infections.


A heat transfer assembly comprising of an electronic component attached to an attachment point located on a circuit board and a clamping mechanism which applies a downward force against a block. In return, the block applies force against a heat transfer device which contacts the electronic component. The interface between the block and the heat transfer device contain a number of tongues and grooves to allow for positive location of the block against the heat transfer device while the clamping mechanism is fastened to the support. The positive location is configured for applying a localized force against a specific area on the electronic component.

1. Field of the Invention
The present invention relates to mounting a block on a heat transfer device, and more particularly, for proper placement of the block over the heat transfer device to increase thermal transfer between an electronic component and heat transfer device.
2. Description of the Related Art
Typically, removing heat generated from electronic components is a primary concern particularly when electronic components are located in enclosures with poor to little ventilation. Failure to remove excess heat results in malfunction of the electronic component. By attaching a heat transfer device to an electronic component, the device will transfer thermal energy away from the electronic component. A heat transfer device can consist of a simple piece of metal or a cold plate. Fans used in conjunction with metal heat transfer devices circulate hot air away from the electronic component. A cold plate heat transfer device consists of a pair of hoses and an inlet and outlet tube which allows liquid coolant to pass through it. As hot air is transferred from the electronic component through the base of the cold plate, liquid coolant entering an inlet valve of the cold plate removes the hot air and passes it through an outlet valve. Liquid coolant is applied to the cold plate through a hose attached to the inlet valve. Likewise, an additional hose is connected to the outlet valve for removing the liquid coolant from the cold plate. In either type of heat transfer device used, it is critical that sufficient pressure is applied the heat transfer device to ensure adequate contact with the electronic component.
Prior art heat sink assemblies disclose a number of ways of forcing a heat transfer device against an electronic component to ensure sufficient contact and pressure. To provide for adequate contact and pressure between the electronic component and a heat transfer device, a clamping mechanism applies a downward force that forces the heat transfer device against the electronic component.
An example of such a heat sink assembly is disclosed in the U.S. Pat. No. 6,665,188 to Chen. The Chen patent discloses two contact members that engage with each other and are moveable over the surface of the heat transfer device. Each contact member has a bolt and arm to facilitate moving the contact members against each other. As the two contact members engage one another, a downward force is applied against the heat sink, which applies a force against the electronic component and establishes contact between the heat sink and the electronic component. The dialing of the bolts is time consuming and may not reliably ensure sufficient contact during mass production of heat sink assemblies. Therefore, what is needed is a heat sink assembly that can distribute sufficient force across a heatsink to a localized position of the electronic component reliably and in a timely manner for mass production. Particularly when localized regions of the electronic component generate more heat than other regions.

Simplified mounting configuration that applies pressure force to one central location


A rotor blade for a wind turbine is disclosed. The rotor blade may generally include a shell having a pressure side and a suction side. The shell may define an outer surface along the pressure and suction sides over which an airflow travels. The rotor blade may also include a spoiler having a fixed end and a free end. The fixed end is connected to the outer surface so as to enable a hinge action, such as a living hinge. The free end includes a top flange and a bottom flange configured to engage opposite sides of the shell and is pivotal relative to the fixed end between a recessed position and an elevated position. The free end has a range of motion limited by contact of the top flange and the bottom flange with the shell. Further, the spoiler is configured to separate the airflow from the outer surface when the spoiler is in the elevated position.

Wind power is considered one of the cleanest, most environmentally friendly energy sources presently available, and wind turbines have gained increased attention in this regard. A modern wind turbine typically includes a tower, a generator, a gearbox, a nacelle, and one or more rotor blades. The rotor blades capture kinetic energy from wind using known foil principles and transmit the kinetic energy through rotational energy to turn a shaft coupling the rotor blades to a gearbox, or if a gearbox is not used, directly to the generator. The generator then converts the mechanical energy to electrical energy that may be deployed to a utility grid.
The particular size of wind turbine rotor blades is a significant factor contributing to the overall efficiency of the wind turbine. Specifically, increases in the length or span of a rotor blade may generally lead to an overall increase in the energy production of a wind turbine. Accordingly, efforts to increase the size of rotor blades aid in the continuing growth of wind turbine technology and the adoption of wind energy as an alternative energy source. However, as rotor blade sizes increase, so do the loads transferred through the blades to other components of the wind turbine (e.g., the wind turbine hub and other components). For example, longer rotor blades result in higher loads due to the increased mass of the blades as well as the increased aerodynamic loads acting along the span of the blade. Such increased loads can be particularly problematic in high-speed wind conditions, as the loads transferred through the rotor blades may exceed the load-bearing capabilities of other wind turbine components.
Certain surface features, such as spoilers, are known that may be utilized to separate the flow of air from the outer surface of a rotor blade, thereby reducing the lift generated by the blade and reducing the loads acting on the blade. However, these surface features are typically designed to be permanently disposed along the outer surface of the rotor blade. As such, the amount of lift generated by the rotor blade is reduced regardless of the conditions in which the wind turbine is operating.
Additionally, U.S. Pat. No. 4,692,095 describes wind turbine blades with active spoilers on the low pressure side of the blade that rapidly deploy to control an overspeed condition. The spoilers are connected to an electrically operated clutch, which normally holds the spoilers in a flush-mount position. In an overspeed condition, the clutch releases the rope and the spoiler opens via a spring. The spoiler, however, opens against the force of the airflow over the blade and the spring must be of sufficient size and strength to hold the spoiler open as the rotor slows. Likewise, the clutch must be of sufficient size and power to retract the spoiler against the force of the spring.
Accordingly, the industry would benefit from a wind turbine rotor blade having a simple and cost-effective actuatable spoiler to reduce lift. More specifically, a rotor blade having an actuatable spoiler with a living hinge would be advantageous.

Wind turbine rotor blade having a spoiler


A diffractive optical element (DOE) is designed to implement both a collimation function with respect to an input divergent beam and a beam shaping function with respect to an output divergent beam. The phase designs of the collimation function and the beam shaping function are independently produced in the phase domain. These phase designs are then combined using a phase angle addition of the individual functions and wrapped between 0 and 2π radians. The diffractive surface of the DOE is then defined from the wrapped phase angle addition of the individual functions.

Reference is made to FIG. 1 showing a conventional geometry for an optical system 10. The system 10 includes a light source 12 generating a collimated beam 14 of light with a planar wavefront that is propagated toward a beam shaping diffractive optical element 16. The diffractive optical element (DOE) 16 is a shaping (for example, circularly homogenizing) optical element designed to generate a desired non-collimated output beam 18 forming an output field 20 with a desired output intensity distribution. Due to small errors in the diffractive surface of the diffractive optical element 16 (e.g., surface defects introduced during manufacture), there is possibility for a high intensity zeroth order leakage 22 of the collimated beam 14 of light through the diffractive optical element 16 into the output field 20. In this context, reference to "high intensity" means dangerous in that the leakage has a beam divergence and power that is dangerous (see, for example, British standard BS EN 60825-1:2014 or international standard IEC 60825-1:2014, both incorporated by reference).
Reference is made to FIG. 2 showing a conventional geometry for an optical system 10′. The system 10′ includes a light source 12′ generating a divergent beam 26 of light that propagates toward a collimating lens 28. The collimating lens 28 functions to collimate the divergent beam 26 and output a collimated beam 14 of light with a planar wavefront that propagates toward a beam shaping diffractive optical element 16. The diffractive optical element 16 is a shaping (for example, circularly homogenizing) optical element designed to generate a desired non-collimated output beam 18 forming an output field 20 with a desired output intensity distribution. Due to small errors in the diffractive surface of the diffractive optical element 16 (e.g., surface defects introduced during manufacture), there is possibility for a high intensity zeroth order leakage 22 of collimated beam 14 of light through the diffractive optical element 16 into the output field 20.
The high intensity zeroth order leakage 22 in FIGS. 1 and 2 is ostensibly an unmodified portion of the collimated beam 14 present in the output field 20. The effect of this is illustrated, for example, in FIG. 3 which shows an image (with inverted contrast) of a square homogenized output field 20 that is corrupted by high intensity zeroth order leakage 22. If the light source 12 or 12′ is, for example, a laser light source, this zeroth order leakage 22 is a safety risk that will have a direct effect on the permitted operating power of the light source 12 or 12′. In response the existence of or chance for such leakage, the power level of the light source 12 or 12′ must be reduced to ensure safe operation, and no benefit is gained from using the diffractive optics.
Evaluation of the beam shaping diffractive optical element 16: There are many sources of error that can degrade the form factor of the diffractive optic with respect to the initial design form. If magnitudes of these errors are set to limits expected in manufacture, the error in the height of the module (i.e., the depth error) is recognized as the key contributor to degradation of optic performance. FIGS. 3A-3C illustrate simulated results of the element 16 with a nominal depth error (i.e., less than or equal to 5%) in FIG. 3A, a 10% depth error in FIG. 3B and a 15% depth error in FIG. 3C. It will be noted that with more significant depth errors homogenization is affected and the zeroth order leakage characteristic (reference 22) becomes more dominant.
Diffractive optics allow the optical system designer to manipulate a wavefront in ways that cannot be achieved with refractive optics. This allows a greater flexibility of the functionality of the optic and enables applications that are not supported by refractive optics. There is a need, however, for an improved diffractive optical element that is not susceptible to surface errors which would permit passage of high intensity zeroth order leakage. As a result, operation of the optical system at higher power levels would be possible.

Diffractive optical element and method for the design of a diffractive optical element

STMicroelectronics (Research & Development) Limited


A surface drive is provided mounted from the stern of a hull for up and down swinging movement in the manner of an outdrive unit, but wherein the surface drive includes a forwardly and upwardly inclined propeller shaft with a forward extension thereof coupled, through the utilization of a universal joint, to the rear end of a power shaft journaled through and projecting rearwardly of the transom of the associated hull and with which the propeller is generally aligned, the surface drive being laterally stabilized and including an upstanding rudder oscillatably supported therefrom rearward of the surface drive propeller.

1. Field of the Invention
This invention relates to a marine surface drive unit of the type utilizing an inboard engine driving a propeller disposed rearward of the transom of an associated boat hull and at an elevation such that the water level immediately rearward of the hull transom, during high speed operation of the hull, is generally registered with the center of the hub portion of the propeller, the propeller and an oscillatable rudder disposed rearward thereof being mounted from a front to rear extending support arm mounted from the transom for up and down oscillation of the rear end thereof, the rudder being carried by the support arm rear end and the propeller being journaled from a depending strut carried by the support arm forward of the rear end thereof.
2. Description of Related Art
Various different forms of outdrive-type boat propulsion systems including some of the general structural and operational features of the instant invention here-to-fore have been provided. Examples of these previous known propulsion systems are disclosed in U.S. Pat. Nos. 2,956,536, 2,999,476, 3,253,569, 4,089,289, 4,382,796, 4,403,969 and 4,432,737. However, these previously known propulsion systems do not comprise surface drive propulsion systems, nor do they offer the convenience of a vertically raiseable and lowerable marine propeller propulsion system incorporating an inboard engine and devoid of gearing exteriorly of the associated hull.


A simplified Viterbi detector for maximum likelihood detection of nine-bit QPSK symbols, employing a difference metric and two comparators, instead of using two state metrics and four comparators. The detector is used to process the outputs of synchronously sampled matched filters. A multiplexer is employed to select the difference metric from amongst the input sample, the fed back value of the difference metric itself, or the inverses of either, depending on decision signals output from the comparators, which in turn compare the difference metric with the input sample and it's inverse. The even path history then represents the most likely value of the detected symbol.

1. Field of the Invention
The invention relates to a simple demodulator for a proposed wireless standard. More particularly, the invention relates to a simplified detector for nine bit even parity QPSK symbols.
2. Background
The IEEE 802.16 Broadband Wireless Access Working Group has a proposal entitled "PHY layer proposal for BWA," IEEE 802.16.1pc dated Feb. 25, 2000. A required modulation format in this proposal is QPSK (Quadrature Phase Shift Keying). In Section 126.96.36.199.1 of the proposed standard, forward error correction employing a Reed Solomon (RS) code over Galois Field GF(256) is proposed. The RS encoder encodes k user bytes and appends r redundant bytes to form systematic codewords, each consisting of n=k+r bytes. A well-known property of RS codes is an errors-only RS decoder can correct any combination of t erroneous bytes provided that 2t<=r. It is possible to extend the power of the RS code by utilising a demodulator which marks bytes suspected of being in error with an erasure flag. In this case, an errors-and-erasures RS decoder can correct any combination of t erroneous unflagged bytes and v flagged bytes provided that 2t+v<=r. Three choices for k and r are proposed, as shown in Table 1.
TABLE 1FEC ParametersPortionkrControl and data transport12810Registration146Contention54
In section 188.8.131.52.2 of the proposed standard it is proposed that each eight-bit byte of the RS code is appended with a single parity bit. In a system which uses these parity bits, a total of nine bit symbols are transmitted over the channel for each byte.
QPSK is detected by decomposing the received waveform into I and Q (In-phase and Quadrature) signals, each of which is match-filtered and synchronously sampled. With a perfect estimate of the carrier phase, there is no crosstalk or interference between the signals. The simple threshold detector can be used on each of the sampled outputs of the matched filters.
As a baseline for comparison, the error performance of a system transmitting 8-bit symbols without the parity bits of section 126.96.36.199.2 of the proposed standards can be characterised (before and after errors-only RS decoding) as a function of a Signal-to-Noise Ratio (SNR) of the received signal.
By monitoring the detected bits of the nine bit symbols in a system using the parity bits of section 18.104.22.168.2, an erasure flag can be generated wherever the parity of the detected symbols is incorrect. An errors-and-erasure RS decoder using these flags offers improved performance over the baseline system. This improved performance requires extra complexity in the receiver, since a high throughput errors-and-erasure RS decoder is typically twice the complexity of an errors-only decoder.
It is desirable to have a modulation scheme which achieves similar or better performance without the need for extra complexity in the RS decoder.

Simple detector and method for QPSK symbols