A laundry dryer is provided with an air recirculation channel which recirculates air from an air exhaust channel to an air supply channel. The air recirculation channel comprises a recirculation air filter which removes debris from the recirculated air before it is redirected to the air supply channel. The recirculation air filter is removably accessible behind an access door at a peripheral region of an access passage to the drying chamber such that it may be easily serviced by a user of the laundry dryer. In some embodiments, the air recirculation channel may comprise a nozzle with an outlet which is concentrically arranged at an inlet of the air supply channel. In these embodiments, the nozzle may direct the recirculated air to the air supply channel such that it is enveloped by fresh air entering from within a cabinet of the laundry dryer.

During operation, a conventional vented tumble dryer draws air from the surrounding area, heats it, and directs it into the drying chamber or drum of the dryer. The dryer then exhausts the air and retained water vapor through a channel to the outside. As shown in FIGS. 1-3, a known vented dryer 100 generally includes a rotatable drum 102; an air supply channel 104 which introduces fresh air from within the dryer housing or cabinet 106 into the drum 102 via manifold 204; a heater 202 supplied at air supply channel 104, which heats the air introduced into the air supply channel 104; and an air exhaust channel 108 to exhaust hot air and water vapor from the dryer, typically to the outside of the house or other building in which the dryer is located. A process air fan or blower 110 is provided downstream of the drum 102 for drawing air through the system and out the exhaust channel 108. A lint filter 206 for collecting lint and other debris in the air is placed between the drum 102 and the exhaust channel 108. In such a vented tumble dryer 100, the sole heat source is the heater 202 upstream of the drum 102. Further, heat recovery may take place by a slight warming of the air in cabinet 106 before it is drawn into heater 202, by virtue of the heat in the cabinet 106 generated by continued operation of the dryer 100.
Some dryer systems use partially recirculated air in addition to the conventional heater to improve energy efficiency. These systems mix a portion of the exhaust air with the air being introduced into the drum. For example, commonly owned U.S. patent application Ser. No. 13/437,499, filed on Apr. 2, 2012, and titled "Dryer With Air Recirculation Subassembly," which is hereby incorporated by reference in its entirety, describes a dryer system using recirculated air to increase efficiency. In these systems, the warm, moisture-laden exhaust air holds the potential to absorb additional molecules of water when recirculated through the dryer, and thus the heat energy of that air can be reutilized to improve operating efficiency.
FIG. 4 illustrates an example vented recirculation dryer 400 with portions of cabinet 406 removed, which redirects at least a portion of exhausted air back to air supply channel 404 and ultimately to drum 402. Specifically, the recirculation dryer 400 is similar to vented dryer 100, except recirculation dryer 400 comprises air recirculation channel 414 connecting air exhaust channel 408 with air supply channel 404. Process air fan or blower 410 pulls air from drum 402 through a conventional lint filter 412. A first portion of this air is exhausted through exhaust channel 408, similar to the operation of exhaust channel 108 of vented dryer 100. However, a second portion of the air is recirculated back to air supply channel 404 via air recirculation channel 414, which is then combined with fresh air entering from cabinet 406 at inlet 416 and ultimately supplied back to drum 402 through air supply channel 404. Accordingly, during operation, air passing through air supply channel 404 (and across a heater within air supply channel 404, not shown) comprises air from cabinet 406 and recirculated air pulled from drum 402. In the right proportions, use of such a combination may increase the overall efficiency of vented dryer 400.
However, one concern with using recirculated air is that the recirculated air may contain lint and debris, even after passing through a conventional lint filter 412. That is, when heated air is pulled across articles in drum 402 by blower or fan 410, it may collect lint or debris from the articles. Although most dryers have a standard lint filter (e.g., lint filter 206 of vented dryer 100 shown in FIG. 2 or lint filter 412 of recirculation dryer 400 shown in FIG. 4) to remove most of this lint, some fine debris may inevitably remain in the exhaust air flow. Recirculating a portion of this exhaust air back toward the heater thus poses the risk that accumulated lint may ignite in the heater and be carried into drum 402.
Some recirculation dryers thus include a recirculation air filter, positioned in the air recirculation channel, to remove particulates left in the recirculated air. However, such filters require periodic cleaning and/or replacement, which can be difficult and require complex systems due to the location of the recirculation air channel. For example, with respect to recirculation dryer 400, a recirculation air filter may be located at the junction between exhaust channel 408 and air recirculation channel 414. But because exhaust channel 408 and air recirculation channel 414 meet in cabinet 406 below drum 402, the recirculation air filter is not readily accessible by a user. Thus, recirculation dryer 400 must be partially disassembled in order to service the recirculation air filter, or, alternatively, internal cleaners must be employed.
As a further example, G.B. Patent Appl. Publ. No. 1,369,713, filed Feb. 23, 1973, and titled "Improvements in or Relating to Direct-Air Tumbler-Driers and Air-Recirculatory Conversion Means Thereof," describes a recirculation air filter that may be periodically serviced through a service hatch provided in recirculation ductwork. Further, U.S. Pat. No. 8,240,064, filed Nov. 24, 2009, and titled "Dryer with Recirculated Air Proportion and Method for Its Operation," describes a recirculation air filter that is cleaned internally by internal scrapers and/or internal rinsing agents, or externally (although it is not clear how). Each of these solutions may add considerable cost or complexity to the dryer. Thus, there remains a need for an accessible recirculation air filter in a vented dryer employing air recirculation, which allows a user of the dryer to easily clean and/or replace the recirculation air filter.

Laundry dryer with accessible recirculation air filter


An air conditioner according to the present invention includes: an air flow path through which air flows; a temperature control unit that controls a temperature of air in the air flow path; a humidifier capable of supplying vapor to the air flow path; a blower that has a suction port connected to a downstream opening of the air flow path, and a discharge port from which air sucked from the suction port is discharged; a chamber that has a communication port connected to the discharge port, and a plurality of duct connection ports configured to be connectable to ducts so as to let out air coming from the discharge port through the ducts; and a baffle plate part 8 disposed in the chamber, the baffle plate part overlapping at least partly with the discharge port when seen along a flow direction of air passing through the discharge port.

In a pattern formation step upon manufacture of semiconductors, photolithography is sometimes used. In the photolithography, a photosensitive resist is firstly applied to a wafer, and then the resist is exposed to light corresponding to a desired pattern. Then, when the resist is a photosetting photosensitive material, an area of the resist, which is not exposed to light, is removed by means of a solvent or the like. Thus, a desired pattern can be formed (developed) in the resist.
In the aforementioned photolithography, it is required to control the temperature and the humidity of the resist uniformly to desired values. This condition is required to make constant a thickness of the resist on the wafer. In a semiconductor manufacturing facility, an air conditioner fulfills the function for satisfying the requirement. Such an air conditioner performs temperature control and humidity control of a resist by supplying an apparatus for applying a resist (referred to as resist application apparatus herebelow) with air whose temperature and humidity are controlled. In the field of an air conditioner of this type, many techniques for improving temperature and humidity control accuracy have been proposed (for example, JP2009-63242A).


A two point door latch device having a master latch assembly, an auxiliary latch assembly, a linkage operationally joining the master latch assembly and the auxiliary latch assembly, and a handle for operating the master latch assembly. Both the master latch assembly and the auxiliary latch assembly have bolts with beveled heads that extend from their respective housings or brackets when in a locked state, and both include springs which tend the bias the bolts to their unlocked states absent the handle being in the lock position. Furthermore, if the linkage becomes disconnected from the master latch assembly and/or the auxiliary latch assembly, or the linkage breaks, the springs will cause the bolts of the master latch assembly and the auxiliary latch assembly to be retracted to an opened state.

Door latching mechanisms with at least two latch assemblies are useful in certain applications where it is desirable to have multiple latch points. One such increasingly important application is in the area of walk-in bathtubs. Walk-in bathtubs feature a door with a gasket. The door opens either inwardly or outwardly. When the door is open, the user can basically walk into the bathtub without having to step over the otherwise relatively high wall of the bathtub. When the door is shut, its gasket will ride against a complementary opening is the tub, thereby forming a watertight seam. Walk-in bathtubs are growing in popularity with invalid patients, people with ambulatory problems, and those who simply prefer easy ingress and egress from a bathtub.
When a walk-in bathtub is filled with water, a considerable amount of water pressure builds up from the 40-50 gallon capacity contained therein. If the door of a walk-in accidental pops open, or the gasket leaks, there is a potential for considerable water damage. Even a slight leak or any dripping whatsoever is unacceptable to manufacturers and consumers alike of walk-in bathtubs. Accordingly, many walk-in bathtubs are fitted with more than one latch to ensure good sealing along the entire door/door frame interface. For ease of operation, some prior art multi-latch door latching mechanisms had one latch assembly carry the door handle (master latch assembly) with the other latch assembly (slave latch assembly) being operably connected to the master latch assembly with a linkage.
With prior art door latching mechanisms having at least two latch assemblies connected with a linkage, if the linkage breaks, gets out of alignment, or otherwise becomes disabled, it is possible that one or more of the latch assemblies can become stuck in a locked position, preventing the door from being opened. Another problem with prior art door latching mechanisms having at least two latch assemblies is that they are not generally designed to provide for even closing of the door along the location of each latch, and thus, leakage along the seal can sometimes occur.
There accordingly remains a need for new designs of door latching mechanisms having at least two latch assemblies that prevent inadvertent locking of the door upon failure of the linkage, and also provide even sealing of a door with a door frame.


The present invention relates generally to a method for analyzing the surface and the near-surface layers of a solid and, more specifically, to a method that utilizes activating actions to analyze the physical and the chemical properties of the layers. The instant abstract is neither intended to define the invention disclosed in this specification nor intended to limit the scope of the invention in any way.

1. Field of the Invention
The present invention relates generally to a method for analyzing the surface and the near-surface layers of a solid and, more specifically, to a method that utilizes activating actions to analyze the physical and the chemical properties of the layers.
2. Description of the Related Art
Physical and chemical properties vary substantially between a surface or a near-surface layer of a solid and the bulk of its structure. In many respects, the properties comprised for the surface layer govern the behaviors of the solid in different media and in the fields of various forces. A basic understanding of these properties paves the way for scientifically based modifications of the surface layer for the purposes of scientific and medicinal progress. Information obtained from an analysis of the surface layer additionally provides a means for industries to control the surface quality of products with a greater precision. Examples of industries include those in the fields of protective coatings, microelectronics or nanoelectronics.
It is important that the surface layer of a solid is preserved for the purposes of analyzation. The present invention teaches a method to preserve and to analyze a surface layer. A search of the prior art revealed no references that teach the claims of the present invention; however, the steps taught in U.S. Pat. No. 5,683,179 to Lowry are related.
Lowry discloses a method to detect the conductive state in an energized superconductor. Lowry teaches the following consecutive steps: (1) cooling a superconducting device to a preselected operating temperature; (2) activating a thermoluminescent sensor by irradiating the sensor with periodic pulses at a preselected radiation; and, (3) energizing the superconducting device by means of heating the sample. Lowry utilizes well-known and classic methods of thermoluminescense to accomplish the protection of superconductive devices. The activation steps taught in the present method alternatively vary in order and in quantum to preserve the surface layer of a solid for the purpose of analyzing the properties.
A method for analyzing physical properties of the surface layer of a solid is known, involving the activation of the surface layer of a solid by low-temperature plasma (LTP) followed by deactivation of the surface layer during which a thermoluminescence spectrum is recorded. The LTP used in this method is ignited by an unmodulated voltage with a frequency of 40.68 MHz at a 10-Pa pressure of a plasma-generating gas, the duration of the sample activation by LTP being from 10 s to 9 min (see A. A. Kalachev, etc., "Plasma-induced Thermoluminescence—a New Method for Investigating Supramolecular Architectures and Temperature Transitions in Polymers and Other Solid Surfaces", Applied Surface Science 70/71 (1993), pp. 295-298 (a copy is attached)).
This engineering solution is taken as a prototype of the variant of the method as per claim 3 of the present invention.
The disadvantage of the prototype method is a modifying influence of the LTP with said parameters upon the surface layer of the sample investigated, which results in insufficiently reliable information on physical and chemical properties of this layer. First of all, this is due to strict plasma parameters used in the prototype, namely, a high pressure of a plasma-generating gas (10 Pa) and relatively long (10 s and more) duration of plasma activation. Both factors lead to overheating of the surface layer and a decay of arising active states already in the course of plasma treatment. For example, as seen from FIG. 4 of the prototype, the luminescence intensity typically falls with increasing treatment time. Moreover, said strict plasma parameters lead to other physical-chemical changes in the surface layer being analyzed.
In addition, in the mode of isothermal luminescence (see FIG. 3, paper by A. A. Kalachev etc.) the curves obtained according to the known method and illustrating the dependence (decrease) of thermoluminescence on time from the moment the LTP activation of the sample is over have no characteristic features; therefore, during this period of time no useful information on the surface structure or surface physical-chemical processes was obtained using said method. The curves are only used as a means for the determination of the moment when heating aimed at deactivation of the surface layer of a solid has to be started.

Method to analyze physical and chemical properties on the surface layer of a solid


A system includes a body portion having rear portion having a fluid intake port and a nose portion having a fluid discharge port. The body portion contains an omni-directional vibratory device, a pump, a fluid conduit that is coupled to the pump and the fluid discharge port, and a power source that is electrically connected to the vibratory device and the pump. The body portion may also contain control circuitry and two end caps rigidly fixed therein, wherein the fluid conduit passes through each end cap. The vibratory device and the pump may be activated by a sensor such as a hydrostatic pressure sensor, an accelerometer, or an altimeter. The body portion may also contain communications circuitry that remotely controls the vibratory device and the pump. The body portion is configured to house a payload such as a sensor system, a battery pack, or a ballast for anchoring.

Some submerged-based applications require a device to be buried in the sea floor. An example of one such application is an anchor for various buoys types, offshore platforms, or navigational nodes for unmanned underwater vehicles. It is often desirable to entirely embed a device into the sea floor to conceal the device and/or prolong the survivability of the device by protecting it from the harsh submerged environment. Currently existing burying devices are not self-contained and do not have the capabilities to house a payload or be remotely controlled. Such features are useful and desirable in many commercial and military applications operating in marine environments. A need exists for a burying device having such features.

Self-contained burying device for submerged environments

The United States of America as represented by the Secretary of the Navy


Detection of oil pollution on water surfaces includes providing echo signals obtained from optical radiation of a clean water area at two wavelengths, optically radiating an investigated water area at two wavelengths and obtaining echo signals from the optical radiation of the investigated water area at the two wavelengths, comparing the echo signals obtained from the radiation of the investigated area at two wavelengths with the echo signals obtained from the radiation of the clean water area, and based on the comparison, determining presence or absence of oil pollution in the investigated water area.

The present invention relates to a method of and a device for detecting oil pollutions on water surfaces.
A method of detection of oil film on water surface is known from inventor's certificate of the USSR # 1,354,073. In the method the investigated water surface is illuminated by pulsed optical beam and the reflected signal is received. Comparison of signals from clean and from investigated water areas is conducted. Amount of pulses, which exceeds the threshold of the analyser, is selected as comparison parameter. If N≧Nb then it is supposed that oil film is present, and if N<Nb then oil film is not present. Nb is a quantity that specifies probability of signal reception in roughness conditions. A disadvantage of this method is low reliability of detection.
Another method of oil pollution detection is disclosed in patent Russian Federation No. 2,143,108. Water surface is irradiated by pulsed optical beam and the reflected signal is received. Comparison of signals from clean and from investigated water areas is conducted. Energy of echo pulses are selected as comparison parameters. It is supposed that oil film is present if both conditions are fulfilled:W>W0τ<τ0where W1 W0 and τ<τ0 are energies and widths of echo pulses reflected from investigated and clean water areas correspondingly. A disadvantage of this method is false detection of oil pollution in the presence of areas with smoothed wind roughness on clean water surface.

Method of and device for detecting oil pollutions on water surfaces

The United States of America as represented by the United States Department of Energy


An apparatus which includes an optical system and a driving member. The optical system is shiftable from an origin position coinciding with an optical axis of the apparatus, to reduce image vibration affecting the apparatus. The driving member is movable from a first position to a second position. When the driving member is in the first position, the optical system is unlocked and is therefore shiftable to reduce image vibration. When the driving member moves from the first position to the second position and the optical system is not at the origin position, the driving member guides the optical system to, and then locks the optical system at, the origin position.

1. Field of the Invention
This invention relates to an image vibration reduction apparatus best suited as a hard vibration reduction apparatus for a camera.
2. Related Background Art
In an image vibration reduction apparatus of this kind according to the prior art, a lock mechanism for locking an image vibration reduction optical system has not generally been used. Also, even an image vibration reduction apparatus having a lock mechanism, design has been made such that an image vibration reduction optical system is moved to the central portion and then is locked.
However, when the image vibration reduction optical system is to be protected from vibration, or when the image vibration reduction optical system is moved under the influence of noise or the like and causes image vibration, it is preferable to lock the image vibration reduction optical system. Further, as the lock mechanism, it is preferable that the image vibration reduction optical system need not be moved to the central portion and can be locked at whatever position it may be.
There is known a vibration reduction apparatus in which vibration created in a camera, a video camera or the like is detected by an angle-velocity sensor or the like and a vibration reduction optical system which is a portion of a photo-taking optical system is moved in a direction opposite to the direction of the detected vibration and the optical axis thereof is varied to thereby reduce image vibration. To effect such vibration reduction, it is necessary to know the fiducial position (origin) of the vibration reduction optical system. This fiducial position is memorized in advance in a memory portion such as a ROM.
However, the aforedescribed vibration reduction apparatus according to the prior art has suffered from the following problems.
In the setting of the fiducial position of the vibration reduction optical system, the characteristic of a position detecting sensor is varied by environment (such as temperature and humidity), and this has led to the problem that when vibration reduction is effected on the basis of the preset fiducial position, an error occurs.
To solve this problem, there is known a method of actually mounting a temperature detection circuit or the like in the apparatus and changing the fiducial position in conformity with temperature. In this method, however, a discrete circuit such as the temperature detection circuit becomes necessary, and this leads to the problem that the apparatus becomes bulky and costly.
There is also the problem that if the fiducial position of the vibration reduction optical system cannot be detected accurately, highly accurate vibration reduction cannot be effected.

Apparatus having an image vibration reduction optical system which is guided to, and locked at, an origin position by a driving member


The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. The receive path of the signal being transferred in the wireless channel in these communication system need to be compensated for various very dispersive conditions occurring in the wireless channel. Some of these conditions include multipath reflection, multipath resilience, ISI (Inter Symbol Interference), channel capacity, strategies for frequency diversity scheduling, etc.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel devices and P-channel devices (MOS device) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS devices. Current channel lengths are 40 nm, the power supply of VDD equals 1.2V and the number of layers of metal levels can be 8 or more.
CMOS offers the computing power to perform many of the required compensation techniques requires overcoming the adverse conditions of the wireless channel. Yet, the computing power must be used in a power efficient manner to insure that the dissipated power is low enough to allow these important building blocks of the transceiver fabricated in CMOS to be used in mobile applications. This helps to insure that the energy drawn from the limited power contained in the battery is minimized while achieving the optimum performance.
Orthogonal frequency division multiplexing (OFMA) is a multi-carrier system that has been used in various communication Standards such as 802.11 (Wi-Fi), digital video broadcasting (DVB), asymmetrical digital subscriber lines (ASDL), etc. However, OFDM suffers from several deficiencies including peak to average power ratio (PAPR), sensitivity to amplifier nonlinearities, and effects of frequency offsets. Single carrier (SC) communication systems, however, overcome these several deficiencies and offer several benefits over OFDM systems.
SC communication systems is a single-carrier transmit signal that partitions their wideband channel into a large number of parallel narrowband subcarriers and has a lower PAPR resulting in design parameters in the transmit path that are simpler to achieve when compared to OFDM.
In the transmitter side as illustrated in FIG. 1, the input signals are mapped 1-2 into symbols, then the symbols are converted from a serial path into parallel blocks with a series to parallel (S/P) converter 1-3 so a cyclic prefix 1-4 can be added to each block. A parallel to serial (P/S) converter 1-5 recombines these blocks into a serial link which is zero padded and filtered 1-6. A digital to analog (D/A) converter 1-7 converts the digital serial link to an analog signal and presented to an analog transmitter 1-8. The signal is sent over the wireless channel 1-9 which time disperses the signal and introduces noise 1-21 into the signal. A receiver front end 1-10 receives the distorted wireless signal and converted to a digital signal with an analog to digital (A/D) converter 1-11. The signal is then filtered 1-12. The prefix is removed 1-13 and a S/P converter 1-14 generates a time domain of parallel block signals that are converter by an fast Fourier transform (FFT) 1-15 in to the frequency domain. A frequency domain equalizer 1-16 is applied to each of the transmitted subcarriers where the channel distortion caused by the channel is compensated for each subcarrier by the frequency domain equalizer. The FFT and frequency domain equalization requires less computation power than an equivalent performing time-domain equalization. An inverse FFT (IFFT) 1-17 generates the time domain representation of the frequency compensated transmitted signal to a de-mapper unit 1-18. The De-mapper feeds its output to a low density parity check (LDPC) decoder 1-22. The LDPC, invented by Gallager "R. G. Gallager, Low Density Parity Check Codes, Cambridge, Mass., MIT Press, 1963, is a well-known linear error code correcting code that approaches the Shannon limit and therefor called a capacity approaching code. After the LDPC, the recovered messages are then applied to a descrambler 1-23 to recover the symbols which are then applied to a P/S converter 1-19. The output signal is applied to the baseband circuitry of the receiver to extract the signals from the transmitter. The combination of the de-mapper, LDPC decoder and de-scrambler is contained within the dotted box 1-24 and will be described in more detail shortly.
A parity-check decoder allows error correction allows messages which are transmitted over a noisy transmission medium to be captured and recovered at a receiver with a noise threshold that can approach the upper bound of the channel noise. These messages comprise codewords [C] that are generated with additional bits for redundancy. These additional bits are called check bits and are placed in the codewords making each codeword distinct from another codeword. This error recovery decoder is required where the codewords as sent by the transmitter are altered in transit to the receiver. The medium which interconnects the transmitter to the receiver can be noisy and can alter the value of the bits contained within the codewords. An example of a hostile medium is a wireless connection between the transmitter and the receiver. Such a wireless medium suffers from noise of the environment, other transmitters in the local area competing for the limited available spectrum, multiple path reflections from buildings and structures, signal loss, and etc.
A Hamming distance separates the codewords from one another and is the number of bit positions that are different. For instance, the codeword [0 1 0 0 1 1 0 1] differs from the codeword [0 1 1 0 1 0 1 0] by three positions: 4th, 5th, and 8th. This large Hamming distance helps to identify the proper codeword during error recovery of a decoder since the decoder would pick the closest one after the algorithm has completed.
A spare matrix H called a parity-check matrix determines the codewords of the source message that satisfies the following equation:HC=0  (EQ. 1)over the Galois field GF(2).
                    H        =                              [                                                            1                                                  1                                                  0                                                  1                                                  0                                                  0                                                                              0                                                  1                                                  1                                                  0                                                  1                                                  0                                                                              1                                                  1                                                  1                                                  0                                                  0                                                  1                                                      ]                    =                      [                                                            A                                                                      I                                          n                      -                      k                                                                                ]                                              (                  EQ          .                                                    2                )            where n=length of codeword and k=bits in the message. I is the identity matrix and AThe constraints for the parity-check matrix H are:c0+c1+c3=0;c2+c3+c5=0;c1+c2+c3+c6=0;  (EQ. 3)A good received codeword at the transmitter satisfies the following equation:HyT=0  (EQ. 4)where yT is the received codeword at the receiver.
A generator is required to create these codewords at the transmitter. Gauss-Jordan elimination on H can be used to find the generator G by inverting [A In-k] to reach [I A−1] or:
                    G        =                              [                                                            1                                                  0                                                  0                                                  1                                                  0                                                  1                                                                              0                                                  1                                                  0                                                  1                                                  1                                                  1                                                                              0                                                  0                                                  1                                                  0                                                  1                                                  1                                                      ]                    =                      [                                                            I                                                                      A                                          -                      1                                                                                ]                                              (                  EQ          .                                                    5                )
The source message S is combined with the parity check bits to generate a codeword C for that source message S at the source. The interconnect medium contributes noise to the message such that the received message Y now contains noise N, or Y=C+N. The spare matrix is known at both the source and destination and the destination and is used to calculate the vector Z=HY=HC+HN at the receiver, and from EQ. 1, Z=HN. This last relationship is used by the decoding process to find the equation which solves HN=Z to determine the noise component n. This noise estimate is subtracted from the received signal y to recover the codeword C. Once the codeword, as sent by the transmitter is recovered at the receiver, the original source message S can be extracted and provided to the transmitter.
Several methods of decoding a LDPC code are available some use the hard values while others use the soft values. The binary erasure channel and bit-flipping decoding use the hard values to determine the value of the corrupted bit. The sum-product decoding method uses soft values. Soft values comprise the sign of the bit values and the magnitude of the bit values, while hard values only look at the sign of the bit value. These iteratively decoding algorithms like the sum-product algorithm are called by different names: the belief propagation algorithm, and the message passing algorithm.
A description of several decoders including the LDPC is provided. Data that has been transmitted satisfies an LDPC code uses a parity-check representation of a binary linear (n, k) block code C where C is the set of all binary n-tuples that satisfy the following (n-k) parity check equation,bHT=0  (EQ. 6)where H is a sparse (n-k) (n) parity check matrix. There are (n) observed bits b, (k) linearly independent generators or constraints in C. The densities of ones in the matrix should be sparse so that the iterative sum-product can be performed quickly to decode the information.
A Tanner graph of a parity check representation for an (8, 4, 4) code is presented in FIG. 2A. This Tanner graph shows a graphical representation of an elementary linear behavior realization of a linear (n, k) block code over Fq of a system and is defined by its trajectories of local constraints. There are (n) variable nodes, (n-k) constraint (zero-sum) nodes which are linearly independent generators in C. The number of edges in the Tanner graph is equal to the number of ones in the parity-check matrix H. These trajectories are the codewords which satisfy those particular constraints. In this graphical representation you could have an observed symbol (n) within the code word. A hidden symbol (u) which represents the state. And you could have the constraints which are the linear homogeneous equations on the subset of the variables.
First the elementary realizations of linear (n, k) block codes over a finite field Fq are illustrated. The code C is the set of all linear combinations Σiuigi over the finite field where the set of generators gj where j is less than or equal to k.
For the (8, 4, 4) code, G is the generator matrix and is shown in EQ. 7, where the n is the number of bits in the codeword, m is the number of parity-check equations, and k is the number of information bits. The code for G is:
                    G        =                              [                                                            1                                                  1                                                  1                                                  1                                                  0                                                  0                                                  0                                                  0                                                                              0                                                  1                                                  0                                                  1                                                  1                                                  0                                                  1                                                  0                                                                              0                                                  0                                                  1                                                  1                                                  1                                                  1                                                  0                                                  0                                                                              0                                                  0                                                  0                                                  0                                                  1                                                  1                                                  1                                                  1                                                      ]                                              b                              0                                                                                b              1                                                                                b              2                                                                                b                              3                                                                                b                              4                                                                                b                              5                                                                                b              6                                                                                b              7                                                          (                  EQ          .                                                    7                )            the columns are labeled b0 . . . b7 along the top, while the rows would be labeled (not shown) as c1, c2, c3, and c4 from top to bottom. FIG. 2A illustrates the parity-check realization of the generator matrix EQ. 7. The (n) variable nodes are shown on the left range from b0 to b7 and the (n-k) constraints range from c1 to c4. Each of the blocks with the (+) calculates the exclusive or of the inputs such that they should equal to zero if the codeword is unaltered.
The set of bits in the j-th parity check equation of the code is determined using the generator matrix G and setting the constraint equations in columns b0 . . . b7 equal to the summation of those positions where the matrix has a one for the state variables; c1, c2, c3, and c as:b0=c1;b1=c1+c2;b2=c1+c3;b3=c1+c2+c3;b4=c2+c3+c4;b5=c3+c4;b6=c2+c4;b7=c4;  (EQ. 8)The Tanner graph of the 4th bit relation of EQ. 8 is depicted in FIG. 2A.
The parity-check equations are determined from EQ. 7 and provides the 4 constraint linear homogeneous equations that summing each row as a function of the 8 constraint variables x0 . . . x7 to zero:x0+x1+x2+x3=0;x1+x3+x4+x6=0;x2+x3+x4+x5=0;x4+x5+x6+x7=0;  (EQ. 9)
At the start of the first cycle, the sum product decoding of LDPC broadcast the bit nodes bi to the check-nodes ci. For example, the b0 equals the intrinsic value y0 received from the channel, the b1 equals the intrinsic value y1 received from the channel, the b2 equals the intrinsic value y2 received from the channel, and the b3 equals the intrinsic value y3 received from the channel as illustrated in FIG. 2B. Each of the values bi received at parity-check nodes ci are used in the parity-check equations to further the calculations. The arrow 2-10 indicates that the movement of data is from the bit-nodes 2-2 to the constraint-nodes 2-3.
For instance in FIG. 2C, the input values: b0, b1, and b2 are sent to parity-check node c1 and are used to calculate the value of c′1. Once calculated, the parity-check c1 2-5 sends the result to the bit node b3 2-4. After bit node b3 receives the value of c′1 calculated by the parity-check c1. The bit-node b3 stores the message of c′1 as E1,3 at bit-node b3. The arrow 2-11 indicates that the movement of data is from the constraint-node 2-5 to the bit-node 2-4.
In FIG. 2D, the input values: b1, b4, and b6 are sent to parity-check node c2 and are used to calculate the value of c′2. Once calculated, the parity-check c2 2-6 sends the result to the bit node b3 2-4. After bit node b3 receives the value of c′2 calculated by the parity-check c2. The bit-node b3 stores the message of c′2 as E2,3 at bit-node b3. The arrow 2-11 indicates that the movement of data is from the constraint-node 2-6 to the bit-node 2-4.
In FIG. 2E, the input values: b2, b4, and b5 are sent to parity-check node c3 and are used to calculate the value of c′3. Once calculated, the parity-check c3 2-7 sends the result to the bit node b3 2-4. After bit node b3 receives the value of c′3 calculated by the parity-check c3. The bit-node b3 stores the message of c′3 as E3,3 at bit-node b3. The arrow 2-11 indicates that the movement of data is from the constraint-node 2-7 to the bit-node 2-4.
A majority-rule is presented in FIG. 2F. Node b3 performs a modulo 2 addition on the values of E1,3, E2,3 and E3,3. In a first case, the result generates a "1" then the extrinsic value of y3 must be a "1" to maintain that overall parity-check of all inputs: E1,3, E2,3 and E3,3, and y3 must generate a "0" to insure that the parity-check condition is maintained. In a second case, if the modulo 2 addition on the values of E1,3, E2,3 and E3,3 results in a "0", then the extrinsic value of y3 must be a "0" to maintain that overall parity-check of all inputs: E1,3, E2,3 and E3,3, and y3 must generate a "0" to insure that the parity-check condition is maintained. In both cases, if the parity-check condition is maintained, then the extrinsic value is correct. If the parity-check condition is maintained for all bit-node b0-bn, then EQ. 1 is satisfied and the iterative cycle can stop. Otherwise, in the next cycle all the values of the previous cycle regarding the calculation of the modulo 2 addition of all values of Ej,i, at a particular bit-node bi is substituted for yi and the next cycle begins.
The extrinsic message c′j from the parity-check node j to bit-node i is the probability that bit i causes the parity-check at parity-node constraint j to be satisfied when bit i=1. This probability is given as:
                              P                      j            ,            i                    1                =                              1            2                    -                                    1              2                                                                  ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                (                                  1                  -                                      2                                                              P                                              c                        ′                                            1                                                                      )                                                                        (                  EQ          .                                                    10                )            where Pc′1 is the current estimate for the bit=1 during the current cycle. The product is taken over the message edges between the bit-node and all connected check-nodes ci. The probability that the parity-check equation is satisfied when bit i=0. This probability is given as:
                              P                      j            ,            i                    0                =                              1            -                          P                              j                ,                i                            1                                =                                    1              2                        +                                          1                2                                                                            ∏                                                            c                      i                      ′                                        ≠                                          c                      j                                                                                (                                      1                    -                                          2                                                                    P                                                  c                          ′                                                1                                                                              )                                                                                (                  EQ          .                                                    11                )
The log likelihood ratios (LLR) Ej,i is the LLR of EQ. 11 or:
                              E                      j            ,            i                          =                              LLR                                      (                              P                                  j                  ,                  i                                1                            )                                =                      log            (                                          1                -                                  P                                      j                    ,                    i                                    1                                                            P                                  j                  ,                  i                                1                                      )                                              (                  EQ          .                                                    12                )            where the log is loge and using EQ. 10 gives:
                              E                      j            ,            i                          =                  log          (                                                    1                2                            +                                                1                  2                                                                                ∏                                                                  c                        i                        ′                                            ≠                                              c                        j                                                                                (                                          1                      -                                              2                                                                          P                                                      c                            ′                                                    1                                                                                )                                                                                1                2                            -                                                1                  2                                                                                ∏                                                                  c                        i                        ′                                            ≠                                              c                        j                                                                                (                                          1                      -                                              2                                                                          P                                                      c                            ′                                                    1                                                                                )                                                                                )                                    (                  EQ          .                                                    13                )
With the aid of EQ. 12,
                                          1            -                          P                              j                ,                i                            1                                            P                          j              ,              i                        1                          =                  ⅇ                      j            ,                          i              ′                                M                                    (                  EQ          .                                                    14                )            solving for Pj,i1 gives:
                              P                      j            ,                          i              ′                                ′                =                              1                          1              +                              ⅇ                                  j                  ,                                      i                    ′                                                  M                                              =                      (                                          Pr                                                  [                                                            c                      ′                                        =                                          0                      |                      y                                                        ]                                                            Pr                                                  [                                                            c                      ′                                        =                                          1                      |                      y                                                        ]                                                      )                                              (                  EQ          .                                                    15                )            where Pr[c′=0|y] is the probability of event [c′=0] given the event y and Pr[c′=1|y] is the probability of event [c′=1] given the event y. Determining (1−2Pc′1) gives:
                              (                      1            -                          2                                            P                                  c                  ′                                1                                              )                =                              1            -                          2                              1                +                                  ⅇ                                      j                    ,                                          i                      ′                                                        M                                                              =                                                    ⅇ                                  j                  ,                                                            i                      ′                                        -                    1                                                  M                                            ⅇ                                  j                  ,                                                            i                      ′                                        +                    1                                                  M                                      =                          tanh                                            (                                                      M                                          j                      ,                                              i                        ′                                                                              2                                )                                                                        (                  EQ          .                                                    16                )
Substituting EQ. 16 into EQ. 13 gives:
                              E                      j            ,            i                          =                  log          (                                                    1                2                            +                                                1                  2                                                                                ∏                                                                  c                        i                        ′                                            ≠                                              c                        j                                                                                tanh                                                              (                                                                        M                                                      j                            ,                                                          i                              ′                                                                                2                                            )                                                                                1                2                            -                                                1                  2                                                                                ∏                                                                  c                        i                        ′                                            ≠                                              c                        j                                                                                tanh                                                              (                                                                        M                                                      j                            ,                                                          i                              ′                                                                                2                                            )                                                                                )                                    (                  EQ          .                                                    17                )
The following is a fundamental logarithmic identity:
                              2                                                                                tanh                              -                1                                                                (                                                M                                      j                    ,                                          i                      ′                                                                      2                            )                                      =                  log          (                                    1              +                              (                                                      M                                          j                      ,                                              i                        ′                                                                              2                                )                                                    1              -                              (                                                      M                                          j                      ,                                              i                        ′                                                                              2                                )                                              )                                    (                  EQ          .                                                    18                )            EQ. 18 can be used in EQ. 17 to provide:
                              E                      j            ,            i                          =                  2                                                                                tanh                              -                1                                      (                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                tanh                                                  (                                                            M                                              j                        ,                                                  i                          ′                                                                                2                                    )                                                      )                                              (                  EQ          .                                                    19                )            Ej,i is the extrinsic LLR message from each check-node cj to a particular bit-node bi which also receives an a priori LLR from the ith bit position of the input codeword yi. The total LLR of the probability include all the check-nodes satisfying one of the parity-check equations and the ith bit position of the input codeword yi:Li=LLR(Pi1)=ri+ΣjεAiEj,i  (EQ. 20)where ri is the LLR of the a priori of the ith bit position of the input codeword yi:
                              r          i                =                  (                                    Pr                                            [                                                      c                    i                                    =                                      0                    |                    y                                                  ]                                                    Pr                                            [                                                      c                    i                                    =                                      1                    |                    y                                                  ]                                              )                                    (                  EQ          .                                                    21                )
The message Mi,j sent from a bit-node bi to check-nodes c′ indicates the LLR excluding the check-node cj and is given as:Mi,j=−ri+Σj≠j′Ej′,i  (EQ. 22)
For a additive white Gaussian noise (AWGN) channel, the a priori LLR is given by
                              r          i                =                              4                                      y              i                                                                  E                s                                            N                o                                              =                                    2                                            y                i                                                    σ              2                                                          (                  EQ          .                                                    23                )
Log likelihood ratios (LLR) are used in the sum-product algorithm. Let R have the elements (0, 1) in the GF (2) field. The LLR of a binary random variable R, L(r), is then defined as:
                              L                                (                          r              i                        )                          =                  log                                (                                          Pr                                                  [                                                            r                      i                                        =                                          0                      |                      y                                                        ]                                                            Pr                                                  [                                                            r                      i                                        =                                          1                      |                      y                                                        ]                                                      )                                              (                  EQ          .                                                    24                )            L(ri) then indicates the probability that the random variable R takes on the value ri. The magnitude of the log-likelihood ratio L(ri) determines the so called "soft" value (αj,i′) of the random variable R while the hard decision is determined by the sign (βj,i′=|Mj,i|) of the magnitude |L(ri)| and is the reliability of this decision.Substituting
                                          tanh                                                                                (                                                M                                      j                    ,                                          i                      ′                                                                      2                            )                                =                                    (                              α                                  j                  ,                                      i                    ′                                                              )                                                                                tanh                                            (                                                      (                                          β                                              j                        ,                                                  i                          ′                                                                                )                                    2                                )                                                                                ∏                                                c                  i                  ′                                ≠                                  c                  j                                                                                tanh                                            (                                                      M                                          j                      ,                                              i                        ′                                                                              2                                )                                              =                                    [                                                ∏                                                            c                      i                      ′                                        ≠                                          c                      j                                                                                α                                      j                    ,                                          i                      ′                                                                                ]                        [                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                tanh                                                  (                                                            β                                              j                        ,                                                  i                          ′                                                                                2                                    )                                                      ]                                              (                  EQ          .                                                    25                )            Placing EQ. 25 into EQ. 19 gives:
                              E                      j            ,            i                          =                              [                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                α                                  j                  ,                                      i                    ′                                                                        ]                              2                                                                          tanh                          -              1                                                                                log                          -              1                                                                                log            [                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                tanh                                                  (                                                            β                                              j                        ,                                                  i                          ′                                                                                2                                    )                                                      ]                                              (                  EQ          .                                                    26                )            distributing the log−1 log term provides:
                              E                      j            ,            i                          =                              [                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                α                                  j                  ,                                      i                    ′                                                                        ]                              2                                                                          tanh                          -              1                                                                                log                              -                1                                                                                [                                          ∏                                                      c                    i                    ′                                    ≠                                      c                    j                                                                                log                                                                                tanh                                                        (                                                                  β                                                  j                          ,                                                      i                            ′                                                                                2                                        )                                                                        ]                                              (                  EQ          .                                                    27                )            The sum-product algorithm of the LDPC can be further simplified by partitioning the LLR ratio into a magnitude component and a sign component. Furthermore, a product term can be replaced with an additive term by utilizing logarithms.
                              ψ                                (                          β                              j                ,                                  i                  ′                                                      )                          =                  log                                                                          (                          tanh                                                                                                  β                                          j                      ,                                              i                        ′                                                                              2                                                                      )                                              (                  EQ          .                                                    28                )            and solving for βj,i′ in EQ. 28 provides:βj,i′=2 tan h−1 log−1[ψ(βj,i′)]  (EQ. 29)substituting EQ. 28 and EQ. 29 into EQ. 27 leaves:
                                          E                          j              ,              i                                =                                    [                                                ∏                                                            c                      i                      ′                                        ≠                                          c                      j                                                                                α                                      j                    ,                                          i                      ′                                                                                ]                                    2                                                                                tanh                              -                1                                                                                log                                  -                  1                                            [                                                ∑                                                            c                      i                      ′                                        ≠                                          c                      j                                                                                ψ                                                        (                                          β                                              j                        ,                                                  i                          ′                                                                                )                                                              ]                                                                                and                                                                        tanh                                                                                      β                                      j                    ,                                          i                      ′                                                                      2                                                            =                                    log                              -                1                                                                ψ                                            (                                  β                                      j                    ,                                          i                      ′                                                                      )                                                                        (                  EQ          .                                                    28                )            where solving for βj,i′ gives:Ej,i=−[Πc′i≠cjαj,i′]ψ[Σc′i≠cjψ(βj,i′)]  (EQ. 29)
The final equations that are used are arrived at by setting Rj,i=Ej,i; βj,i′=L(qj,i′); αj,i′=sign L(qj,i′); in EQ. 29:Sj,i=[Πc′i≠cjαj,i′]=Πc′i≠cj[sign L(qj,i′)]  (EQ. 30)andAj,i=[Σc′i≠cjψ(βj,i′)]=Σc′i≠cjψ(L(qj,i′))  (EQ. 31)Rj,i=−Sj,iψ[Aj,i]  (EQ. 32)setting ΣjεAiEj,i=L(qj,i); ri=Rj,i; Li=L(qj)=Mi,j; EQ. 20 becomes:L(qj,i)=L(qj)−Rj,i  (EQ. 33)Using EQ. 22, and EQ. 23, the message Mj,i sent from a bit-node bi to check-nodes c′ indicates the LLR excluding the check-node cj and is given as:
                              L                                (                          q              j                        )                          =                              -                                          2                                                  y                  i                                                            σ                2                                              +                                    ∑                              j                =                                  j                  ′                                                                                R                              j                ,                i                                                                        (                  EQ          .                                                    34                )
The received bits represent probabilities at each bit node or input node. These bit-nodes are combined with the constraints-nodes in a Tanner graph to perform the belief propagation procedure. In the first iteration, these probabilities are passed from the bit-nodes to the constraint-nodes and are updated according to the parity check constraints. These values become updated and the new probabilities are send back to the symbol nodes which also performs the parity check constraint. At the bit-nodes, the values are again updated and if EQ. 4 is satisfied, then the process stops; otherwise, the recalculated probabilities at each bit-node or input nodes are passed from these bit-nodes to the constraint-nodes again in additional iterative manner and are updated according to the parity check constraints. These newer values become updated and the newer probabilities are send back to the symbol nodes which also performs the parity check constraint again. Then, at the bit-nodes, the values are again updated and if EQ. 4 is satisfied, the process is stopped and the correct codewords have been determined. The source message can then be extracted from the codeword.
FIG. 3A and FIG. 3B illustrate a generator realization and parity-check realization for the (8, 4, 4) code. FIG. 3A illustrates the b1 to b7 bit values 2-2 broadcast their value to the parity-check 2-3 so that these blocks can compute the sum-product constraint. Once the sum-product constraint has been computed, the network then causes the newly calculated c1 to c4 parity bit values 2-5 to send their value to the (n) symbols 2-4. The majority rule calculates the bit values in a second cycle. The flip from a generator realization to a parity-check realization is understood by comparing FIG. 3A and FIG. 3B. Now the (n) symbols are broadcast back to the (n-k) constraints once the (n-k) constraints have calculated their value, the network flips back to a generator realization and continually does an iterative loop until the number of loops is exceeded beyond a set value or the values of the (n) symbols x0 through x7 have arrived at their final value.
FIG. 4A illustrates the (n) symbols being in the broadcast mode are coupled to an interleaver block also known as a π network. The interleaver block then couples to the (n-k) constraints being in the zero-sum mode. The number of ports arriving from the (n) symbols to the interleaver is PL while the number of ports between the interleaver and the (n-k) constraints is PR. The interleaver requires that PL equals PR to operate properly.
FIG. 4B illustrates a trellis block diagram for another decoding system called the Belief Propagation decoder and algorithm. This figure illustrates the flow of messages and computations using a sum-product algorithm to calculate the values. The values x0 to xn generate the input messages i0-in which are the intrinsic a posteriori probabilities (APP) vectors derived from the observation. The output messages eo-en are the extrinsic APP vectors and are provided at x0 to xn. The blocks Co-Cn 4-2 capture the intrinsic data and proceeds to independently calculate the forward (α1 to αn) and backwards (βn to β1) directions simultaneously. In the forward direction, the messages flows from C0 to Cn while in the backwards direction the messages flows from Cn to C0. Once the forward message reaches Cn and the backward message reaches C0, the BCJR algorithm is complete and the extrinsic data is output to x0-xn. This algorithm uses a sum-product rule within each of the blocks Co-Cn4-2.

Method and apparatus of a fully-pipelined layered LDPC decoder


A light projection system includes a light source configured to emit image light and an optical assembly configured to provide positive optical power to the image light and optically correct the image light. The optical assembly comprises a plurality of optical elements configured to correct differential distortion related to the image light across a field of view (FOV) within a threshold amount. The differential distortion is corrected based in part on asymmetry of the plurality of optical elements relative to an optical axis shared by the plurality of optical elements.

The present disclosure generally relates to optical collimators, and specifically relates to a light projection system that includes an optical assembly for correction of differential distortion.
Headsets in artificial reality applications typically display image content via some form of display. For artificial reality applications it is desirable to have a light headset of a small form factor. But, designing a display for such a headset is difficult. In particular, in cases where the headset is something akin to a set of eyeglasses. A light headset can be implemented by coupling a strip source for emitting image light with a scan mirror for scanning of a viewer scan field to build a scene for the viewer. However, a projection system based on the strip source coupled to the scan mirror introduces image distortion across a field of view as a result of the scanning process.

Light projection system including an optical assembly for correction of differential distortion


Aluminum bearing alloy uses Bi having a higher melting point than Sn as a low melting point metal, and also utilizes a selected element(s) which are simultaneously added as well as the amount of such addition. In this manner, aluminum bearing alloy exhibiting fatigue strength and seizure resistance which are excellent than those of conventional Bi-containing aluminium bearing alloy is provided.

Aluminium bearing alloy finds its application in sliding or plain bearing of an internal combustion engine, but there is an increasing demand on improving the seizure resistance and fatigue strength thereof recently as higher load and temperature requirements are imposed upon the plain bearing with an increase in the speed of operation and the output of such engine. An improvement in the seizure resistance or fatigue strength requires an improved surface characteristics of the plain bearing, for which the use of a low melting metal, such as Sn, Pb, Bi or the like, for example, is essential.
The use of Sn as a low melting point metal in an aluminium bearing alloy is known in the prior art, as exemplified by Japanese Patent Publication No. 14,990/1989, and another aluminium bearing alloy using Bi as a low melting point metal is also known (see Japanese Laid-Open Patent Application No. 235,436/1987).
Generally, the use of a low melting point metal contributes to improving the seizure resistance and fatigue strength, but if the amount of low melting metal used is excessive, its grains are too large, or a melting point is too low with respect to an environment in which the bearing is to be used, there is an adverse effect in that the fatigue is likely to occur. By way of example, Bi has a higher melting point than Sn, and is effective generally in achieving a higher melting point for Al matrix, but this is influenced by the kind of other elements added as well as the amount of such addition, with consequence that a simple addition of Bi cannot assure an excellent seizure resistance or fatigue strength.

Aluminium bearing alloy containing bismuth


This invention is concerned with 2-ureido-benzamide compounds of the formula (1) ##STR1## in which R.sup.1 is H, halogen atom, (C.sub.1 -C.sub.4)alkyl, (C.sub.1 -C.sub.4)alkoxy or (C.sub.1 -C.sub.4)dialkylamino and R.sup.2 is H, halogen atom, hydroxy, nitro, (C.sub.1 -C.sub.4)alkyl, (C.sub.1 -C.sub.4)alkoxy, (C.sub.3 -C.sub.6) cycloalkylmethoxy, (C.sub.1 -C.sub.4) alkylthio, (C.sub.1 -C.sub.4) alkylsulfinyl, (C.sub.1 -C.sub.4)alkylsulfonyl or ##STR2## wherein j is an integer of from 0 to 2 and R.sup.3 and R.sup.4 are each independently H, (C.sub.1 -C.sub.4)alkyl, (C.sub.1 -C.sub.4)alkanoyl, (C.sub.1 -C.sub.4)alkylsulfonyl or (C.sub.1 -C.sub.4)alkylcarbamoyl, NR.sup.3 R.sup.4 can to form a pyrrolidine, piperidine, morpholine, imidazole or pyrazole ring;. X is a (C.sub.3 -C.sub.15)alkyl, (C.sub.3 -C.sub.6) cycloalkyl, (C.sub.3 -C.sub.6) cycloalkylmethyl, .omega.-(C.sub.1 -C.sub.4) alkoxy-(C.sub.1 -C.sub.4) alkyl group or ##STR3## wherein k is an integer of from 1 to 4 and R.sup.5 and R.sup.6 are each independently H,. Y is H or (C.sub.1 -C.sub.4)alkyl and Z is ##STR4## wherein m is an integer of from 0 to 4.

1. Field of the Invention
The present invention relates to novel 2-ureido-benzamide derivatives having potent acyl coenzyme A:cholesterol acyltransferase (ACAT: EC188.8.131.52) inhibiting activity, to pharmaceutical composition containing these compounds and to use thereof for the treatment and prevention of atherosclerosis.
Ischemic circulatory diseases such as myocardial infarction and cerebral infarction resulting from atherosclerosis have been a major cause of human death. The studies on atherosclerosis have been carried out in the various fields for long years.
Recently, it has been found that esterification of intracellular cholesterol is effectively catalyzed by the enzyme: ACAT which is found later in various tissues such as liver, intestine, adrenal and macrophages. It is said that ACAT may be present in all tissues The Enzymes, 16, 523-539 (1983)!.
In intestine, ACAT plays a key role in the gastrointestinal absorption of cholesterol. In intestinal mucosal cells, dietary and biliary cholesterol derived from the diet and biosynthesis must be esterified by the action of ACAT before it can be incorporated into the chyromicron particles which are then released into the blood stream Eur. J. Clin. Invest., 9, 55 (1971)!. Thus inhibition of ACAT in intestinal mucosa appears to block intestinal absorption of cholesterol, resulting in the decrease of blood cholesterol level. However, such an intestinal ACAT inhibitor may involve unfavorable increase of the endogenous cholesterol synthesis and possible ineffectiveness of such inhibitor on patients having no hyper-function in cholesterol absorption.
Although the role of ACAT in liver, especially in human, is less clearly known, the ACAT may participate in the synthesis and secretion of VLDL and the control of biliary excretion of cholesterol J. Lipid Res., 26, 647 (1985)! and inhibition of the liver ACAT may result in lowering of the blood lipid level.
Cholesterol esters are a major component of atherosclerotic lesions and also a major storage form of cholesterol in arterial wall cells. Accumulation of cholesterol esters is linked to the form cell formation which is catalyzed by ACAT in macrophages. Thus, inhibition of the macrophage ACAT may prevent directly the progression of atherosclerotic lesion formation by decreasing the form cell formation without unfavorable effects as in the case of ACAT inhibition in intestine.
2. Description of the Prior Art
Certain phenylurea derivatives having ACAT inhibiting activity are disclosed as shown below.
(a) U.S. Pat. No. 4,623,662 (1986) discloses substituted urea and thiourea compounds such as ##STR5##
(b) EP Publication No. 477,778 (1992) and J. Med. Chem., 36, No. 11, 1641-1653 (1993) disclose benzene, pyridine and pyrimidine derivatives such as ##STR6##
(c) EP Publication No. 370,740 (1990) discloses diaryl compounds as inhibitors of ACAT such as ##STR7##
(d) U.S. Pat. No. 5,116,848 (1992) discloses N-phenylalkyl(thio)urea derivatives such as ##STR8##
(e) A variety of urea compounds can be found in the other literatures, for example, in EP Publication Nos. 335,375 (1989), 405,233 (1991) and 447,116 (1991) and in U.S. Pat. Nos. 4,923,896 (1990), 5,015,644 (1991) and 5,106,873 (1992).
On the other hand, phenylurea derivatives having other pharmacological or agricultural activities such as blood sugar lowing activity, 5-HT M-receptor antagonist activity and herbicidal activity are disclosed in JP Unexamined Publication No. 59-181,257 (1984) Chem. Abst., 102, No. 78735 (1985)!, EP Publication No. 235,878 (1987) and U.S. Pat. No. 3,812,168 (1974), respectively. And some organic reactions for phenylurea derivatives are disclosed in literatures such as Indian J. Chem., 266 No. 12, 1133-1139 (1987) and Mh. Chem., 98, No. 3, 633-642 (1967).
However, there are no known literature references disclosing such 2-ureido-benzamide derivatives as those in this invention and their use as ACAT inhibitors for the treatment of atherosclerosis.
The present inventors synthesized various novel 2-ureido-benzamide compounds having substituents on both of amide and urea(ureido) nitrogen atoms and intensively investigated their activities, and, as the result, found that the useful as a drug for atherosclerosis and related diseases.


An improved method for modeling electrical behavior in a MOSFET semiconductor device is disclosed wherein a rate equation qualitatively predicts electrical behavior, including electron migration and current, across a boundary imposed by the difference in doping the source and the channel. Quantitative values of the electrical behavior are skewed when doping levels in the device are unknown. However, the qualitative result may be used, regardless of knowledge of the doping levels, to design MOSFET devices which exhibit more desirable electric behavior. The rate equation may further be used to simulate the behavior of a MOSFET device in a computer simulation program. Because mobility and diffusion factors, which break down with shrinking gate dimensions, are eliminated from the instant rate equation, the electrical behavior of smaller devices is simpler to calculate than with classical rate equations.

The present invention relates generally to measuring electrical behavior in semi-conductor devices and relates more particularly, to simulating current in MOSFET devices based on an improved barrier model rate equation.
The trend in modern semiconductor manufacturing has been to produce semiconductor chips in ever-decreasing sizes. This, in turn, allows electrical components, such as computers, cellular telephones, compact disc players and the like, to be made smaller and more compact as well as faster in operation. The miniaturization of electrical components is deemed to be advantageous in the sale and marketing of the same, since consumers tend to prefer smaller components over similarly priced, yet bulkier models.
In order to achieve this overall miniaturization, it becomes necessary to create smaller versions of the internal elements that make up these electrical components. Much attention has been directed to creating smaller, more densely-packed transistors in order to create, for example, smaller microprocessors as well as other semiconductor chips. In order to design such smaller transistors, it is preferable to be able to model and simulate the behavior of a theoretical design prior to its manufacture.
A semiconductor device, such as a MOSFET, having a source region, a gate region, a drain region and a channel region associated with it, have been successfully modeled in the past. However, as the device is made smaller, the dimensions of these associated regions necessarily decrease. As channel lengths shrink in particular, it has been realized that classical transport concepts, such as drift, diffusion, or other quantities become less reliable. Consequently, the transport equations used to model these devices, and which rely on these factors, are of limited accuracy. Thus they lose their useful in the simulation and design of smaller MOSFETs.
Thus, there is a need to develop an improved model for simulating electrical behavior in semiconductor devices, such as MOSFETs, which provides accurate and useful results, while discounting factors such as electron mobility, diffusion and velocity which become unreliable for modeling in smaller devices.
The instant invention demonstrates the viability of modeling the current in a short-channel MOSFET without the use of mobility, diffusion or classical electron velocity. Such a model is useful where the uncertainty in the velocity of electrons that traverse the channel becomes comparable to the saturation velocity of electrons in the device. This unfavorable characteristic is present in silicon-based metal-oxide semiconductor field-effect transistors (MOSFETs) currently manufactured. The instant rate-equation model is particularly useful for short-channel MOSFETs, where comparable transport equations have not previously been applied. Results, including current-voltage (I-V) characteristics generated by the instant rate equation (or barrier model), compare well qualitatively to experimental data, as well as to results from electrical device computer simulation programs such as PADRE or SPICE. Furthermore, the instant barrier model replicates features of the current-voltage curve that are often ascribed to variations in the mobility, although mobility is not included in the rate equation.
According to a first aspect of the instant invention, a method for determining a current-voltage characteristic for a semiconductor device having a source region, a drain region and a channel region, comprises: assigning one of a plurality of fixed values to each of at least one of a plurality of model variables including a gate-to-source voltage (VGS) to be applied to the device, a drain-to source voltage (VDS) to be applied to the device, a first Fermi level (F1) corresponding to the source region of the device, a second Fermi level (F2) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (Eqv) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in a z-direction for electrons in a channel valley (mzv); assigning a plurality of differing values for each of the remaining model variables; and determining, for each of the plurality of differing values, a current value (I12) from a rate equation modeled after the source-channel barrier. In the above variables, the subscript v denotes a particular valley, and z denotes the direction along the width of the channel.
According to a second aspect of the instant invention, a computer-readable medium encoded with processing instructions is disclosed for implementing a method, performed by a computer, for simulating current-voltage behavior in a semiconductor device having a source region, a channel region and a drain region, the method comprising: receiving an input including one of a plurality of fixed values for each of at least one of a plurality of model variables including a gate-to-source voltage (VGS) to be applied to the device, a drain-to source voltage (VDS) to be applied to the device, a first Fermi level (F1) corresponding to the source region of the device, a second Fermi level (F2) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (Eqv) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in a z-direction for electrons in a channel valley (mzv); assigning a plurality of differing values for each of the remaining model variables; and determining, for each of the plurality of differing values, a current value (I12) from a rate equation modeled after the source-channel barrier.
According to a third aspect of the instant invention, an apparatus for simulating current-voltage behavior in a semiconductor device having a source region, a channel region and a drain region, comprises: a processor; a memory connected to the processor, the memory storing a program to control the operation of the processor; and the processor operative with the program to: receive an input including one of a plurality of fixed values for each of at least one of a plurality of model variables including a gate-to-source voltage (VGS) to be applied to the device, a drain-to source voltage (VDS) to be applied to the device, a first Fermi level (F1) corresponding to the source region of the device, a second Fermi level (F2) corresponding to the channel region of the device, a width (W) of the channel region, an operating temperature (T) of the device, a quantization energy level (Eqv) of the device, a height (Vo) of a source-channel barrier of the device, and a mass in the z-direction for electrons in a channel valley (mzv); assign a plurality of differing values for each of the remaining model variables; and determine, for each of the plurality of differing values, a current value (I12) from a rate equation modeled after the source-channel barrier.

Rate equation method and apparatus for simulation of current in a MOS device