An encoder (103) encodes image data using a first parameter Q1, and a re-encoder (107) re-encodes the encoded result of the encoder (103) using a second parameter Q2. When the encoded data size obtained by the encoder (103) exceeds a predetermined size, Q1 is replaced by Q2, and encoded data streams previously encoded by the re-encoder (107) are saved in a buffer (108) as those encoded by the encoder (103) after the parameter is changed. Upon executing a re-encoding process, the re-encoder (107) re-encodes encoded data streams previously encoded by the re-encoder (107) using a parameter that can assure a higher compression ratio than Q2.

Many existing digital imaging apparatuses have a compression-encoding function for still images. As a typical one of such digital imaging apparatuses, a digital camera is known. In addition, a digital color copying machine is one of the digital imaging apparatuses with such function. In the digital color copying machine, upon transferring document image data scanned by a document scanner to a printing unit, the document scanner has a compression-encoding function for the scanned document image data so as to reduce the data size to be transferred, and the printing unit has a decompression-decoding function for the encoded document image data stream.
The encoded data size of the document image data stream encoded by the compression-encoding function of the document scanner can be reduced to a fraction of the document image data before the compression-encoding process, i.e., the data size of the scanned document image data. The upper limit of the degree of reduction of the data size of such encoded document image data stream to the document image data before the compression-encoding process, i.e., that of the compression ratio is set to be a value at which encoding distortion is not readily visually recognized from the decoded and reconstructed image. On the other hand, the allowable lower limit value of the compression ratio can be uniquely determined according to various restrictions in that system such as the maximum data size of document image data that the document scanner can scan per unit time, the maximum data transfer size of compressed-encoded data stream upon transferring data from the document scanner to the printing unit, and the like.
Even when the allowable upper and lower limit values of the compression ratio of document image data are set, it is not easy to perform a compression-encoding process to make the compression ratios of all input document image data regulate within the range specified by these upper and lower limit values. This is because even when a compression-encoding process is performed using identical encoding parameters (e.g., a quantization tables), the obtained compressed-encoded data stream have arbitrary data sizes for respective document image data stream, i.e., the compression ratio varies for respective scanned document image data.
That is, individual scanned document image data have different states and levels of deviation of their information entropy in terms of spatial frequency, and the compression-encoding process for such document image data adopts various schemes for removing redundancy of image data to be compressed (e.g., runlength encoding for a series of transformed coefficients with values "0", and entropy encoding using variable-length codes). Therefore, in order to perform the compression-encoding process to make the compression ratios of all document image data regulate within the range between the allowable upper and lower limit values, encoding parameters to be applied to each document image data must be changed adaptively, i.e., for each image data to be compressed.
In general, in order to execute the compression-encoding process to obtain constant compression ratios, encoding control called rate control is used. As practical methods of the rate control, two schemes, i.e., a feedforward scheme and feedback scheme, are known.
In the feedforward scheme, the dynamic range, power of entropy, and various kinds of statistical values are independently calculated from source image data which is input as image data to be compressed and encoded before the compression-encoding process, so as to predict optimal encoding parameters on the basis of these calculated values, and an actual compression-encoding process is performed using the predicted encoding parameters. By contrast, in the feedback scheme, optimal encoding parameters are predicted based on the actual size of the encoded data stream obtained by executing trial compression-encoding processes, and a final compression-encoding process is performed using the predicted encoding parameters. Of these two schemes, since the feedback scheme that predicts optimal encoding parameters from the actual size of the encoded data stream obtained by trial compression-encoding processes directly uses the actually obtained size of the encoded data stream in prediction calculations, it can obtain a predicted value of encoding parameters that can be used to generate a target encoded data size with higher accuracy than the feedforward scheme. However, an extra elapsed time is consumed by trial compression-encoding processes.
In a system that allows an increase in processing time even when a compression-encoding process is repeated until an encoded data stream with a target compression ratio is obtained, i.e., a system that requires neither severe realtimeness nor higher throughput, a repetitive algorithm described in Japanese Patent Publication No. H8-32037 "Image Data Compression Apparatus" can be applied. However, a digital imaging apparatus such as a digital camera, digital color copying machine, or the like normally requires realtimeness and high-speed performance. Therefore, it is required to minimize the elapsed time consumed by trial compression-encoding processes for predicting optimal encoding parameters, and to assure higher accurate prediction result.
In order to improve the prediction accuracy of optimal encoding parameters in the rate control using the feedback scheme, it is effective to execute trial compression-encoding processes using many encoding parameters, and to obtain many references that have correspondence between these encoding parameters and actually obtained encoded data sizes. However, conventionally, in order to minimize the elapsed time, arithmetic operation circuits or processing circuits so many as the number of encoding parameters used in trial compression-encoding processes are equipped, and are parallelly operated to execute trial compression-encoding processes.
As described in reference 1 "60 to 140 Mbps compatible HDTV coding", Video Information, January 1992, pp. 51–58, as an example of such parallel circuit scheme, N sets of quantization tables are used as a plurality of encoding parameters, a compression-encoding apparatus which comprises N quantization circuits and N generated code size measurement circuits accordingly is provided, and curve approximation is done based on N encoded data sizes obtained by this encoding apparatus to obtain an optimal set of encoding parameters, i.e., an optimal set of quantization tables.
As a devise for suppressing an increase in area of circuit although a similar arrangement is adopted, for example, Japanese Patent No. 02523953 "Encoding Apparatus" describes that three quantization circuits are equipped to parallelly execute quantization processes using five sets of quantization tables in trial compression-encoding processes, and to obtain five encoded data size values.
In video compression-encoding that adopts an encoding scheme which can sequentially execute compression-encoding processes while adaptively changing an encoding parameter (more particularly, a scaling factor for a set of quantization tables) upon compression-encoding one image data, a sequential correction algorithm described in, e.g., Japanese Patent No. 02897563 "Image Compression-encoding Apparatus", can be applied.
In this prior art, an encoded data size for each block obtained by quantizing using a specific quantization scaling factor is calculated upon trial compression-encoding processes, M encoded data sizes which are expected to be obtained using M quantization scaling factors are predicted on the basis of the calculated data size, and the compression-encoding process is performed while sequentially correcting a quantization scaling factor which is used actually on the basis of the difference between the target encoded data size calculated from these M predicted values and the sum total of the data sizes of the encoded data stream which is actually output so far, i.e., a prediction error.
Furthermore, for the purpose of avoiding the actually generated encoded data size from exceeding the allowable upper limit value unexpectedly, as described in Japanese Patent No. 03038022 "Digital Camera Apparatus", when the data size of an encoded data stream obtained by actually executing quantization and variable-length encoding processes using a quantization step value derived from the encoded data size obtained upon trial compression-encoding processes has exceeded the data size assigned to each block, variable-length encoding in that block is aborted (to discard information of significant transform coefficients).
The aforementioned prior arts of the rate control using the feedback scheme have common features in that an optimal encoding parameter and the predicted encoded data size generated using the encoding parameter are derived on the basis of one or a plurality of actual encoded data sizes obtained by trial compression-encoding processes.
In a JPEG encoding scheme which is prevalently adopted as a general still image compression-encoding scheme, since a quantization step matrix as one of most typical encoding parameters, i.e., a quantization table as only one combination for one image data to be compression-encoded, is commonly applied to all blocks which comprise that image data, the sequential correction algorithm of encoding parameters described in Japanese Patent No. 02897563 "Image Compression-encoding Apparatus" cannot be applied.
Furthermore, with the algorithm described in Japanese Patent No. 03038022 "Digital Camera Apparatus" cited as another prior art, when the data size assigned to each block has been exceeded, a variable-length encoding process for that block is aborted. As a result, even when the final encoded data size obtained upon completion of compression-encoding processes of all blocks that comprise image data does not exceed the allowable upper limit value, even significant transformed coefficients which need not be discarded are discarded, and local variations of compression-encoding distortion are generated in a reconstructed image obtained by a decompression-decoding process. Hence, it is not preferable to apply this algorithm to a digital imaging apparatus.
When a compression-encoding process is done while implementing rate control using the feedback scheme with high prediction accuracy in a system that requires realtimeness and higher throughput like in a digital imaging apparatus, the parallel circuit architecture described as a prior art is, in fact, effective implementation. However, a huge circuit area and buffer size are required to implement a plurality of encoding processing circuits and to temporarily store a plurality of encoded data streams, much cost is required. Hence, it is difficult to implement parallel processes using too huge circuits.
Hence, when a digital imaging apparatus adopts a still image compression-encoding scheme such as JPEG encoding which has a limited variation in encoding parameter, it is preferable to increase the number of parallel circuits within an allowable circuit area range so as to simultaneously perform compression-encoding processes using the largest possible number of different encoding parameters, and to output an encoded data stream, which suffers the minimum encoding distortion within the allowable compression ratio range, of a plurality of obtained encoded data streams.
However, since the number of parallel circuits is finite, all encoded data streams generated using a plurality of encoding parameters may fall outside the allowable compression ratio range. In such case, a new encoding parameter must be determined to redo a compression-encoding process from the head of data to be encoded. However, the time required to redo the encoding process directly leads to a performance drop of the system.
The present invention has been made in consideration of the aforementioned problems, and has as its object to compression-encode image data to a predetermined size, to suppress compression-encoding distortion of an image obtained by decompression-decoding an encoded data stream obtained by compression-encoding, and to obtain a high-quality reconstructed image.

Method and apparatus for encoding image data in accordance with a target data size


A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.

A variety of semiconductor-based dynamic random-access memory devices are known and/or commercially available. The above-referenced '154, '890, '582, '972, and '766 applications and '481, '342, '248, '241, '326, '763, and '765 patents each relate to and describe in some detail how various aspects of semiconductor memory device technology have been and will continue to be crucial to the continued progress in the field of computing in general, and to the accessibility to and applicability of computer technology in particular.
Advances in the field of physical and structural aspects of semiconductor technology, for example various developments which have reduced the minimum practical size of semiconductor structures to well within the sub-micron range, have proven greatly beneficial in increasing the speed, capacity and/or capability of state-of-the-art semiconductor devices. Notwithstanding such advances, however, certain logical and algorithmical considerations must still be addressed.
In fact, some advances in semiconductor processing technology in some sense make it particularly important, in some cases imperative, that certain logical or algorithmical compensatory measures be taken in the designing of semiconductor devices.
For designers and manufacturers of semiconductor devices in general, and for semiconductor memory devices in particular, there are numerous considerations which must be addressed. Certain aspects of semiconductor memory design become even more critical as their speed and density is increased and their size is decreased. The present invention is directed to a memory device in which various design considerations are taken into account in such a manner as to yield numerous beneficial results, including speed and density maxmization, size and power consumption minimization, enhanced reliability, and improved yield, among others.
Memory integrated circuits (ICs) have a memory array of millions of memory cells used to store electrical charges indicative of binary data. The presence of an electrical charge in a memory cell typically equates to a binary "1" value and the absence of an electrical charge typically equates to a binary "O" value. The memory cells are accessed via address signals on row and column lines. Once accessed, data is written to or read from the addressed memory cell via digit or bit lines. One important consideration in the design of semiconductor memory devices relates to the arrangement of memory cells, row lines, and column lines in a particular layout or configuration, commonly referred to as the device's "topology". Circuit topologies vary considerably among variously designed memory ICs.
One common design found in many memory circuit topologies is the "folded bit line" structure. In a folded bit line construction, the bit lines are arranged in pairs with each pair being assigned to complementary binary signals. For example, one bit line in the pair is dedicated to a binary signal DATA and the other bit line is dedicated to handle the complementary binary signal DATA*. (The asterisk notation "*" is used throughout this disclosure to indicate the binary complement of a signal or data value.)
The memory cells are connected to either of the bit lines in the folded pair. During read and write operations, the bit lines are driven to opposing voltage levels depending upon the data content being written to or read from the memory cell. The following example describes a read operation of a memory cell holding a charge indicative of a binary "1": The voltage potential of both bit lines in the pair is first equalized to a middle voltage level, for example, 2.5 volts. Then, the addressed memory cell is accessed and the charge held therein is transferred to one of the bit lines, raising the voltage of that bit line slightly above that line's counterpart in the pair. A sense amplifier, or similar circuit, senses the voltage differential on the bit line pair and further increases this differential by increasing the voltage on the first bit line to, say, 5 volts, and decreasing the voltage on the second bit line to, say, 0 volts. The folded bit lines thereby output the data in complementary form.
One variation on the folded bit line structure is a so-called "twisted" bit line structure. FIG. 1 illustrates a twisted bit line structure having bit line pairs DO/DO* through D3/D3* that flip or twist at junctions 1 across the array. Memory cells are coupled to the bit line pairs throughout the array. Representative memory cells 2a through 2n and 3a through 3n are represented in FIG. 1 coupled to bit line pair DO/DO*. The twisted bit line structure evolved as a technique to reduce bit-line interference noise during chip operation. Such noise is increasingly more problematic as memory capacities increase and the sizes of physical structures on the chip decrease. The twisted bit line structure is therefore particularly advantageous in larger memories, such as a 64 megabit (Mbit) or larger dynamic random access memory (DRAM).
A twisted bit line structure presents a more complex topology than the simple folded bit line construction. Addressing memory cells in the FIG. 1 layout is more involved. For instance, diferent addresses are used for the memory cells on either side of a twist junction 1. As memory ICs increase in memory capacity, yet stay the same or decrease in size, noise problems and other layout constraints force the designer to conceive of more intricate configurations. As a result, the topologies of these circuits become more and more complex, and are more difficult to describe mathematically as each layer of complexity adds additional terms to a topology-describing equation. This in turn may give rise to more complex addressing schemes.
One problem that arises for memory ICs involves testing procedures. It is increasingly more difficult to test memory ICs that have intricate topologies. To test ICs, memory manufacturers often employ a testing machine that is preprogrammed with a complex boolean function that describes the topology of the memory IC. Conventional testing machines are capable of handling limited-sized addresses (e.g., 6-bits). As topologies grow more complex, however, such addresses may be incapable of fully addressing all individual cells for some test patterns. This renders the testing apparatus ineffective. Furthermore, if a user wishes to troubleshoot a particular memory device after some period of use, it is very difficult to derive the necessary boolean function for input to the testing machine without consulting the manufacturer.
The difficulties associated with memory IC testing become more manifest when a form of compression is used during testing to accelerate the testing period. It is common to write test patterns of all "1"s or all "O"s to a group of memory cells simultaneously. Consider the following example test pattern of writing all "1"s to the memory cells in the twisted bit line pairs of FIG. 1. Under the testing compression, one bit is used to address four bit line pairs DO/DO*, D1/D1*, D2/D2*, and D3/D3. Under conventional addressing schemes, the task of placing "1"s in all memory cells is impossible because it cannot be discerned from a single address whether the memory cell, in order to receive a "1", needs to have a binary "1" or "O" placed on the bit line connected to the memory cell. Accordingly, testing machines may not adequately test memory ICs of complex topologies. Conversely, it is less desirable to test memory ICs on a per-cell basis, as the necessary testing period is too long.
Another consideration which must be taken into account in the design of memory ICs arises, as noted above, as a result of the extremely small size of various components (transistors, diodes, etc . . . ) disposed on a single chip, which renders the chip susceptible to component defects caused, for example, by material impurities and fabrication hazards. In order to address such this problems, chips are often built with redundant components and/or circuits that can be switched-in in lieu of corresponding circuits found defective during testing or operation. Usually the switching-out of a defective component or circuit and the switching-in of a corresponding redundant element is accomplished by using programmable logic circuits which are activated by blowing certain fuse-type devices built into the chip's circuitry. The blowing of the fuse-type devices is normally performed prior to packaging, burn-in and delivery of the IC die.
The number of redundant circuits available in a given IC is of course limited by the space available on the chip. Allocation of IC area is balanced between the competing goals of providing the maximum amount of primary circuitry, while maintaining adequate redundancy.
Memory chips are particularly well suited to benefit from redundancy systems, since typical memory ICs comprise millions of essentially equivalent memory cells, each of which capable of storing a logical 1 or 0 value. The cells are typically divided into generally autonomous "sections" or memory "arrays". For example, in a 16 Mbit DRAM there may be 4 sections of 4 Mbits apiece. The memory cells are typically arranged into an array of rows and columns, with a single row or column being referred to herein as an "element". A number of elements may be grouped together to form a "bank" of elements.
Over the years, engineers have developed many redundancy schemes which strive to efficiently use the available space on an IC. One recent scheme proposed by Morgan (U.S. Pat. No. 5,281,868) exploits the fact that fabrication defects typically corrupt physically adjacent memory locations. The scheme proposed in the Morgan '868 patent reduces the number of fuses required to replace two adjacent columns by using one set of column-determining fuses to address the defective primary column, and an incrementor for addressing an adjacent column. A potential problem with this scheme, however, is that sometimes only one column is defective. Thus, more columns may be switched-out than is necessary to circumvent the defect.
Another perceived problem with common redundancy systems is that redundant elements serving one SAB may not be available for use by other SABs. Providing this capability using conventional techniques results in a prohibitive number of interconnection lines and switches. Because the redundant circuitry located on each SAB may only be available to replace primary circuitry on that SAB, each SAB must have an adequate number of redundant circuits available to replace the most probable number of defective primary circuits which may occur. Often, however, one SAB will have no defects, while another has more defeats than can be replaced by its redundant circuitry. In the SAB with no defects, the redundant circuitry will be unused while still taking up valuable space. The SAB having too many defects may cause the entire chip to be scrapped.
While providing redundant elements in a semiconductor memory is effective in facilitating the salvage of a device having some limited number of defects in its memory array, certain other types of defects can cause the device to exhibit undesirable characteristics such as increased standby current, speed degradation, reduction in operating temperature range, or reduction in supply voltage range. Certain of these types of defects cannot be repaired effectively through redundancy techniques. Defects such as power-to-ground shorts in a portion of the array can prevent the device from operating even to the extent required to locate the defect in a test environment. Memory devices with limited known defects have been sold as "partials", "audio RAMs" or "off spec devices" provided that the defects do not prohibitively degrade the performance of the functional portions of the memory. The value of a partially functional device decreases dramatically as the performance of the device deviates from that of the standard fully-functional device. The desire to make use of devices with limited defects, and the problems associated with the performance of these devices due to the defects are well known in the industry.
The concept of providing redundant circuitry within a memory device addresses a problem that is essentially physical in nature, and, as noted above, involves a trade-off in the allocation of chip area between primary and redundant elements. The aforementioned issue of device topology, on the other hand, provides a good illustration of a consideration which has both physical (electrical) and logical significance, since the twisted bit-line arrangement complicates the task of testing the device. Another example of a consideration which has both structural and logical impact involves the manner in which memory locations within a memory device are accessed.
Fast page mode DRAMs are among the most popular standard semiconductor memories today. In DRAMs supporting fast page mode operation, a row address strobe signal (/RAS) is used to latch a row address portion of a multiplexed DRAM address. Multiple occurrences of a column address strobe signal (/CAS) are then used to latch multiple column addresses to access data within the selected row. On the falling edge of /CAS an address is latched, and the DRAM outputs are enabled. When /CAS transitions high the DRAM outputs are placed in a high-impedance state (tri-state). With advances in the production of integrated circuits, the internal circuitry of the DRAM operates faster than ever. This high speed circuitry has allowed for faster page mode cycle times. A problem exists in the reading of a DRAM when the device is operated with minimum fast page mode cycle times. /CAS may be low for as little as 15 nanoseconds, and the data access time from /CAS to valid output data (tCAC) may be up to 15 nanoseconds; therefore, in a worst case scenario there is no time to latch the output data external to the memory device. For devices that operate faster than the specifications require, the data may still only be valid for a few nanoseconds.
Those of ordinary skill in the art will appreciate that on a heavily loaded microprocessor memory bus, trying to latch an asynchronous signal that is valid for only a few nanoseconds can be very difficult. Even providing a new address every 35 nanoseconds requires large address drivers which create significant amounts of electrical noise within the system. To increase the data throughput of a memory system, it has been common practice to place multiple devices on a common bus. For example, two fast page mode DRAMs may be connected to common address and data buses. One DRAM stores data for odd addresses, and the other for even addresses. The /CAS signal for the odd addresses is turned off (high) when the /CAS signal for the even addresses is turned on (low). This so-called "interleaved" memory system provides data access at twice the rate of either device alone. If the first /CAS is low for 20 nanoseconds and then high for 20 nanoseconds while the second /CAS goes low, data can be accessed every 20 nanoseconds (i.e., at a rate of 50 megahertz). If the access time from /CAS to data valid is fifteen nanoseconds, the data will be valid for only five nanoseconds at the end of each 20 nanosecond period when both devices are operating in fast page mode. As cycle times are shortened, the data valid period goes to zero.
There is a demand for faster, higher density, random access memory integrated circuits which provide a strategy for integration into today's personal computer systems. In an effort to meet this demand, numerous alternatives to the standard DRAM architecture have been proposed. One method of providing a longer period of time when data is valid at the outputs of a DRAM without increasing the fast page mode cycle time is called Extended Data Out (EDO) mode. In an EDO DRAM the data lines are not tri-stated between read cycles in a fast page mode operation. Instead, data is held valid after /CAS goes high until sometime after the next /CAS low pulse occurs, or until /RAS or the output enable (/OE) goes high. Determining when valid data will arrive at the outputs of a fast page mode or EDO DRAM can be a complex function of when the column address inputs are valid, when /CAS falls, the state of /OE and when /CAS rose in the previous cycle. The period during which data is valid with respect to the control line signals (especially /CAS) is determined by the specific implementation of the EDO mode, as adopted by various DRAM manufacturers.
Methods to shorten memory access cycles tend to require additional circuitry, additional control pins and nonstandard device pinouts. The proposed industry standard synchronous DRAM (SDRAM, for example, has an additional pin for receiving a system clock signal. Since the system clock is connected to each device in a memory system, it is highly loaded, and it is always toggling circuitry in every device. SDRAMs also have a clock enable pin, a chip select pin and a data mask pin. Other signals which appear to be similar in name to those found on standard DRAMs have dramatically different functionality on a SDRAM. The addition of several control pins has required a deviation in device pinout from standard DRAMs which further complicates design efforts to utilize these new devices. Significant amounts of additional circuitry are required in the SDRAM devices which in turn result in higher device manufacturing costs.
In order for existing computer systems to use an improved device having a nonstandard pinout, those systems must be extensively modified. Additionally, existing computer system memory architectures are designed such that control and address signals may not be able to switch at the frequencies required to operate the new memory device at high speed due to large capacitive loads on the signal lines. The Single In-Line Memory Module (SIMM) provides an example of what has become an industry standard form of packaging memory in a computer system. On a SIMM, all address lines connect to all DRAMs. Further, the row address strobe (/RAS) and the write enable (/WE) are often connected to each DRAM on the SIMM. These lines inherently have high capacitive loads as a result of the number of device inputs driven by them. SIMM devices also typically ground the output enable (/OE) pin making /OE a less attractive candidate for providing extended functionality to the memory devices.
There is a great degree of resistance to any proposed deviations from the standard SIMM design due to the vast number of computers which use SIMMs. Industry's resistance to radical deviations from standards, and the inability of current systems to accommodate the new memory devices tend to delay the widespread acceptance of non-standard parts. Therefore, only limited quantities of devices with radically different architectures will be manufactured initially. This limited manufacture prevents the reduction in cost which typically can be accomplished through the manufacturing improvements and efficiencies associated with a high volume product.
There is another perceived difficulty associated with performing write cycles at increasingly high frequencies. In a standard DRAM, write cycles are performed in response to both /CAS and /WE being low after /RAS is low. Data to be written is latched, and the write cycle begins when the latter of /CAS and /WE goes low. In order to allow for maximum "page mode" operating frequencies, the write cycle is often timed out, so that it can continue for a short period of time after /CAS goes high, especially for "late write" cycles. Maintaining the write cycle throughout the timeout period eases the timing specifications for /CAS and /WE that the device user must meet, and reduces susceptibility to glitches on the control lines during a write cycle. The write cycle is terminated after the timeout period, and if /WE is high a read access begins based on the address present on the address input lines. The read access will typically begin prior to the next /CAS falling edge so that the column address to data valid specification can be met (tAA). In order to begin the read cycle as soon as possible, it is desirable to minimize write cycle time while guaranteeing completion of the write cycle. Minimizing the write cycle duration in turn minimizes the margin to some device operating parameters despite the speed at which the device is actually used. Circuits to model the time required to complete the write cycle typically provide an estimate of the time required to write an average memory cell. While it is desirable to minimize the write cycle time, it is also necessary to guarantee that enough time is allowed for the write to complete, so extra delay may be added, making the write cycle slightly longer than required.
Throughout a memory device's product lifetime, manufacturing process advances and circuit enhancements often allow for increases in device operating frequencies. Write cycle timing circuits may need to be adjusted to shorten the minimum write cycle times to match these performance improvements. Fine tuning of these timing circuits is time consuming and costly. If the write cycles are too short, the device may fail under some or all operating conditions. If the write cycles are too long, the device may not be able to achieve the higher operating frequencies that are more profitable for the device manufacturers.
A further consideration to be addressed in the design of semiconductor devices that has both process and algorithmic significant relates to the relative physical locations of the various functional components on a given IC. Those of ordinary skill in the art will appreciate, for example, that including larger numbers of metallic or otherwise conductive layers within the allowable design parameters (so-called "design rules) of a particular species of semiconductor device can simplify, reduce, or mitigate certain logical hurdles. However, inclusion of more metal layers tends to increase the cost and complexity of the manufacturing process. Thus, while conventional wisdom may suggest grouping or locating particular elements of a semiconductor device in a certain area for algorithmic and/or logical reasons, such approaches may not be entirely optimal when viewed from the perspective of manufacturing and processing considerations.
Yet another consideration to be addressed in the design of semiconductor devices relates to the power supply circuitry for such devices. The design of systems which incorporate semiconductor devices such as microprocessors, memories, etc . . . is routinely constrained by a limited number of power supply voltages (V.sub.cc). For example, consider a portable computer system powered by a conventional battery having a limited power supply voltage. For proper operation, different components of the system, such as a display, a processor, and memory employ several technologies which require power to be supplied at various operating voltages. Components often require operating voltages of a greater magnitude than the power supply voltage or in other cases involve a voltage of reverse polarity. The design of a system, therefore, includes power conversion circuitry to efficiently develop the required operating voltages. One such power conversion circuit is known as a charge pump.
The demand for highly-efficient and reliable charge pump circuits has increased with the increasing number of applications utilizing battery powered systems such as notebook computers, portable telephones, security devices, battery backed data storage devices, remote controls, instrumentation, and patient monitors, to name a few.
Inefficiencies in conventional charge pumps lead to reduced system capability and lower system performance in both battery and non-battery operated systems. Inefficiency can adversely affect system capabilities causing limited battery life, excess heat generation, and high operating costs. Examples of lower system performance include low speed operation, excessive delays in operation, loss of data, limited communication range, and the inability to operate over wide variations in ambient conditions including ambient light level and temperature.
Product reliability is a product's ability to function within given performance limits, under specified operating conditions over time. "Infant mortality" is the failure of an integrated circuit (IC) early in its life due to manufacturing defects. Limited reliability of a charge pump can affect the reliability of the entire system.
To reduce infant mortality, new batches of semiconductor IC devices (e.g., it charge pumps) are "burned-in" before being shipped to customers. Burn-in is a process designed to accelerate the occurrence of those failures which are commonly at fault for infant mortality. During the burn-in process, the ICs are dynamically stressed at high temperature (e.g., 125.degree. C.) and higher-than-normal voltage (for example, 7 volts for a 5 volt device) in cycles that can last several hours or days. The devices can be tested for functionality before, after, and even during the burn-in cycles. Those devices that fail are eliminated.
Conventional pump circuits are characterized by a two part cycle of operation and low duty cycle. Pump operation includes pumping and resetting. Duty cycle is low when pumping occurs at less than 50% of the cycle. Low duty cycle consequently introduces low frequency components into the output DC voltage provided by the pump circuit. Low frequency components cause interference between portions of a system, intermittent failures, and reduced system reliability. Some systems employed conventional pump circuits include filtering circuits at additional cost, circuits to operate the pump at elevated frequency, or both. Elevated frequency operation in some cases leads to increased system power dissipation with attendant adverse effects.
During normal operation of a charge pump, especially charge pumps providing operating voltages higher than V.sub.cc (boosted voltages), certain internal "high-voltage" nodes in the charge pump circuitry reach voltages having a magnitude significantly higher than either the power-supply voltage or the produced operating voltage (so-called "over-voltages"). These over-voltages can reach even higher levels under the dynamic stress high voltages during burn-in testing. When an IC charge pump is tested during a burn-in cycle, high burn-in over-voltages in combination with high burn-in temperatures can cause oxidation of silicon layers of the IC device and can permanently damage the charge pump.
In addition to constraints on the number of power supply voltages available for system design, there is an increasing demand for reducing the magnitude of the power supply voltage. The demand in diverse applications areas could be met with high efficiency charge pumps that operate from a supply voltage of less than 5 volts.
Such applications include memory systems backed by 3 volt standby supplies, processors and other integrated circuits that require either reverse polarity substrate biasing or booted voltages outside the range 0 to 3 volts for improved operation. As supply voltage is reduced, further reduction in the size of switching components paves the way for new and more sophisticated applications. Consequently, the need for high efficiency charge pumps is increased because voltages necessary for portions of integrated circuits and other system components are more likely to be outside a smaller range.

Dynamic random access memory having decoding circuitry for partial memory blocks


A shower door hinge having a door clamping member, a wall mounting plate and a concealed knuckle device is presented. The door clamping member engages the shower door while the wall mounting plate is mounted on a side wall of the shower stall. The knuckle device, which is comprised of several parts, is enclosed within the door clamping member and thereby hidden from view. The knuckle device has, as a first and second part, a hinge and a hinge pin which form the axis of rotation about which the shower door rotates. The knuckle device also has, as another part, a spring biased pin which cooperatively acts with the hinge. The cooperative action between the hinge and the spring biased pin allow for a camming action which controls both the rate of rotation and the positioning of the shower door around the axis of rotation.

Bathroom design and interior decorating of the bathroom have achieved a significant level of importance in the overall appearance of a home. Architects and homeowners today, therefore, are insisting that every detail of the bathroom appearance be decorative and precise.
Unfortunately, when it came to installing a new shower stall or tub, available shower hinges are in many instances not in conformance with the otherwise highly decorative theme of the bathroom. Shower hinges are typically bulky, exposed mechanical devices, leaving little to the imagination. For instance, U.S. Pat. No. 5,367,745, issued to Roloff on Nov. 29, 1994, relates to a hinge for shower stall doors. The shower door hinge has two separate members held in place by a hinge pin (pintle). The first member has two axially aligned sleeves which receive an axially aligned sleeve of the second member. The hinge pin passes through the member's sleeves and defines the axis of the hinge about which the shower door can be swung. The hinge pin can be removed, having at one end an annular flange or head, while at the other end a screw thread for engagement of a screw. Thus the design of this shower door hinge leaves exposed the two member's sleeves, the pintle and screw. Further, there exists the possibility that the screw will eventually become unscrewed and work its way loose, such that the hinge pin will fall out and the shower door will fall off.
U.S. Pat. No. 5,588,181, issued to Sutton on Dec. 31, 1996, relates to hinge for a glass shower door. The shower door hinge is constructed having a "u" shaped clamping member which clamps onto the shower door, and a "h" shaped strip which attaches to a supporting wall. At the end of the "h" shaped strip away from the point of attachment to the wall, the strip is shaped to form a channel (sleeve) through which a pin is inserted. This portion of the strip has a cut-out section in which a portion of the clamping member, also shaped in the form of a channel (sleeve), is inserted. The clamping member and the strip are then connected axially by insertion of the pin. The pin creates a point of rotation for the hinge about which the shower door rotates. This shower door hinge design too leaves exposed the pin and channels in which the pin fits. Further, the pin may come loose and the clamping member, due to its design, may eventually lose its hold on the shower door with repeated use.
U.S. Pat. No. 5,448,799, issued to Stein, Jr. on Sep. 12, 1995, relates to a panel hinge structure which can be employed to rotatably join two panel members such as a shower door and a shower enclosure assembly. The first member has extending from it an elongated web terminating in an axially aligned rod. The rod itself may be encased in a sleeve. The second member has an internal keyway which includes an axially aligned tubular channel. This tubular channel rotatably captures the axially aligned rod of the first member. The fit of the rod into the tubular channel creates the axis of rotation about which the hinge swings. A separate series of pieces, referred to as gudgeon clips, at the top of each of the first and second member prevents the rod from becoming disengaged from the tubular channel. The design of this hinge leaves exposed the rod of the first member. Further, if the gudgeon clips fail to work, become dislodged themselves, or even break, the rod will become disengaged from the channel and the shower door will fall off.
Thus, there is a need for a decorative shower door hinge in which the knuckle of the hinge is not exposed and which is protective of the glass door to which it is attached. The industry, as can be seen, has heretofore failed to provide such a shower door hinge having a concealed knuckle which is aesthetically pleasing and in conformance with contemporary design features.

Outwardly swinging shower door hinge having a concealed knuckle


This invention provides a wireless transmitter circuit for mobile communication apparatus and this circuit can be configured with fewer components and is suitable for downsizing. A single PLL synthesizer serves as both RF frequency band PLL and IF frequency band PLL among three oscillators for TX, RX and IF frequency bands, which have been required in conventional mobile communication apparatus. The number of necessary oscillators occupying a large area within a chip is reduced and the number of components is decreased. Specifically, circuitry is arranged to generate local oscillation signals for RF and IF frequency bands by frequency dividing the output of a VCO of the RF frequency band PLL.

With explosive growth of mobile communication apparatus, there is a strong demand for smaller and less costly wireless apparatus. Consequently, application of a transceiver integrated circuit (IC) with enhanced integration is hoped for. One example of the transceiver IC with improved integration by prior art is a direct-conversion transceiver IC introduced by Hitachi, Ltd. in 2001 (see non-patent document 1). This uses an offset PLL transmitter circuit and, in the transmitter, there are an RF frequency band phase-locked loop (PLL), an intermediate frequency (IF) band PLL, and a transmission oscillator; altogether three oscillation circuits and PLL circuits including oscillators.
A mobile phone configuration that uses a modulation type fractional divider PLL frequency synthesizer in which a digital dither circuit is provided between a digital input and a delta-sigma (ΔΣ) modulator to supply a digital output which discretely changes from the digital input with its time-average corresponding to the digital input to the delta-sigma (ΔΣ) modulator is known (e.g., see patent document 1). Since the "delta-sigma modulator" is generally called a "sigma-delta (ΣΔ) modulator," the term "sigma-delta (ΣΔ) modulator" will be used hereinafter.
[Patent document 1] Japanese Patent Laid-Open No. 2002-152044
[Non-patent document 1] S. Tanaka et al., "GSM/DCS1800 Dual Band Direct-Conversion Transceiver IC," Proceedings of the 27th European Solid-State Circuits Conference pp. 492-495, 2001

Wireless transmitter circuit and transceiver using the same


In an apparatus for reproducing information signals from a record medium, the method for repeated reproduction of the information signals contained in a selected portion of the record medium includes the steps of counting the number of control pulses recovered for the record medium between receipt of a first control signal and receipt of a second control signal in a play mode of operation, thereby producing a count value, reversing the play direction of the record medium and subtracting the number of control pulses recovered, after the second control signal is received, from the count value until the count value is decreased to zero and restarting information signal reproduction in the play mode of operation. A method for repeat reproduction of information signals corresponding to one of information signals located on a predetermined portion of the record medium and information signals reproduced during a predetermined time period is also disclosed.

A video tape recorder (VTR) or a tape recorder is a device which records and reproduces audio and/or video signals on a magnetic tape. When one uses such a device for the purpose of linguistic drill or athletic exercise, there is often a need to repeatedly reproduce a certain portion of the recorded tape.
A typical conventional method for this purpose is performed using "endless tape (or drum, sheet)". The endless tape is a fixed-length magnetic tape which is endlessly circulated in the deck. Thus, one can record data in any section of the tape and reproduce that data repeatedly. This method cannot be used to reproduce video signals in video equipment owing to its complicated construction. Moreover, when the amount of recorded data is not equal to the endless tape's recording capacity, the wait time after reproduction increases. Thus, the less data recorded on the endless tape, the longer the wait time becomes. To solve this problem, many solutions, for example, detecting the non-recorded section and jumping to the start of the recorded section of the tape have been proposed. However, these methods are difficult to adapt to the reproduction of video signal.
Another conventional repeat reproduction method was disclosed in Japanese patent laid-open Publication No. Sho 6352356, which describes two decks in line and two magnetic tapes, each of which contains the same data. The two magnetic tapes are loaded in each deck, respectively, and the decks repeatedly reproduce the data in such a way that one tape is rewinding while the other tape is playing, and vice versa.
This method can be adapted to the repeat reproduction of not only audio signals but also video signals, but the method still has some drawbacks. In particular, it is very difficult to synchronize the advancing speeds of two tapes which are moving in opposite directions. The system cost is very high as it has two decks to pick up two tapes, respectively.

Repeat reproduction method for magnetic tape


A rigid disk drive including a rotary actuator having a lift tab extending asymmetrically from the end of the load beam which supports a slider with read/write element is disclosed. The free end of the lift tab cooperates with a cam surface on a cam assembly to provide dynamic loading and unloading of the slider while imparting a roll to the slider as it is loaded to and unloaded from the disk.

1. Field of the Invention
This invention relates to the field of information storage utilizing rigid disks, and more particularly to apparatus for dynamically loading and unloading read/write magnetic recording elements for flight above the surface of moving magnetic media.
2. Description of the Prior Art
In certain types of disk files which include rigid magnetic media it is desirable to load and unload a magnetic recording reproducing element into flight above the surface of the moving media as opposed to utilizing take off from and landing on the magnetic media where the magnetic recording element comes to rest on the disk after rotation has ceased and takes off from the disk after the disk is once again spun up. U.S. Pat. No. 4,535,374 to Anderson et al., issued Aug. 13, 1985, is exemplary or a rigid disk drive of the linear actuator type which provides for dynamic loading of magnetic read/write heads above the surface of a disk. In Anderson et al. a stationary cam follower is provided on and supported from the housing, and the load arm, which includes a magnetic recording head at its free end, is provided with a cam surface intermediate the free end and the end supported by the actuator. The cam surface cooperates with a stationary cam to lift the head above the surface of the disk when the head arm is retracted.
Another linear actuator rigid disk drive utilizing a cam arrangement to achieve dynamic loading of the magnetic recording head above the disk is illustrated in U.S. Pat. No. 4,663,682 to McNeil, issued May 5, 1987. In McNeil, a pair of cam surfaces are supported by the disk drive housing and a wing, having a pair of free ends, is attached to the load beam intermediate the actuator driving mechanism and the free end of the load beam which supports the head slider. The free ends of the wing cooperate with the cam surfaces to lift the magnetic recording head slider above the surface of the disk when the head arm is retracted. In McNeil, the direction of movement of the magnetic media beneath the magnetic recording head is such that the media is moving in a direction which is parallel to the longitudinal axis of the slider on which the magnetic recording element is supported and perpendicular to the longitudinal axis of load beam. The cam surfaces in McNeil are offset and provide pitch to the slider during the loading process when the slider is approaching the surface of the rotating media.
U.S. Pat. No. 4,933,785 to Morehouse et al., issued Jun. 12, 1990, and assigned to Prairietek Corporation, discloses a magnetic disk drive utilizing a rotary actuator. The load beams (which support the read/write elements) each include a lift button which is supported on the load beam, and positioned on the longitudinal axis of the load beam. The lift buttons cooperate with a spreader, which includes cam surfaces, to provide dynamic loading and unloading of the slider which is supported on the end of the load beam opposite of the pivot point of the load beam. The buttons and the cooperating spreader with cam surfaces are located intermediate the pivot point of the rotary actuator and the magnetic head. The button and cam surface on the spreader provide a symmetrical lift to the load beam and correspondingly symmetrical loading of the magnet head above the media, which in this configuration is rotating in the direction beneath the head which is substantially parallel to the longitudinal axis of the load beam which is supporting the slider.
A later introduced rigid disk drive from Prairietek Corporation, utilized a dynamic loading structure having a cam surface supported on the housing which contacted directly the load beam of the rotary arm having the magnetic slider on its free end. In this Prairietek hard disk drive, denominated the model 120, the cam is supported on the housing and is positioned intermediate the head slider and the pivot point of the rotary actuator. The principle distinction between the dynamic loading structure in the model 120 over the structure illustrated in the '785 patent is the elimination of the button which was included on the load beam and provided a center line lift on the load beam. In the model 120 disk drive a heavy roll torque is applied to the load beam and there is no ability to change the amount of torque and correspondingly the roll applied to load beam.
U.S. Pat. No. 3,984,873, issued Oct. 5, 1976 to Pejcha illustrates a structure for dynamically loading heads, which in one embodiment utilizes a movable channel member which is supported above the surface of the rotating rigid disk. The loading of a head above the surface of the disk is achieved by providing flat spring extensions which extend symmetrically from the free end of the load beam and are captured in the channel which is positioned in a plane above the surface of the disk such that the opening is generally parallel to the plane of the disk. With the spring extensions captured in the channel, the heads are prevented from being loaded on the disk. To load the heads the channel member is moved out of contact with the flat spring extensions and the heads move toward the surface of the associated disk. In another embodiment, the flat spring extensions on the ends of the load beam are crisscrossed and a pivoted member is moved into contact with the crisscrossed free ends to unload the heads from the disk. In a third embodiment, a cam surface is provided adjacent to the edge of the rotating disk and the magnetic head is supported on a spring member which is affixed by bolts to a rotating arm. An extension of the spring member on the end adjacent to the magnetic head is positioned at right angles with respect to the center line of the rotary arm on which the head and spring is mounted, with the spring extension having a longitudinal axis which is parallel to the longitudinal axis of the cam surface.

Rigid disk drive with dynamic head loading apparatus


A pattern size correcting device includes: a testing photomask (1) having a test pattern; a quantifying unit (2) that quantifies, using the testing photomask (1), size variation in the test pattern as a function of distance and in relation to an open area ratio; an open area ratio calculating unit (3) that divides an exposure area having a plurality of actual device patterns into a plurality of correction areas and calculates the open area ratio of the respective correction areas; a data correcting unit (4) that inputs the open area ratio calculated by the open area ratio calculating unit (3) into a result of the quantification that uses the photomask (1), calculates size variations of the actual device patterns in the respective correction areas, and corrects design data of the actual device patterns based on the calculation; and a proximity effect correcting unit correcting a proximity effect. This correcting device enables quantitative estimation of size variation occurring in a pattern exposed in lithography and easy and accurate correction of pattern size based on the estimation.

In a pattern forming technology, manufacturing of semiconductor devices using photolithography is in practice. The photolithography is a method of forming a desired pattern on a reticle being a photomask and transferring the pattern on a sample substrate via a reduction optical system. Photosensitive resin called a resist is formed on the sample substrate, and making use of a difference, between an exposed portion and an unexposed portion, in dissolving rate in a developing solution, a latent image of the transferred pattern is developed to form a pattern, and then etching follows, so that a material can be processed as desired.
In an exposure technology, in order to precisely transfer a microscopic pattern, the influence of proximate patterns is calculated and determined for correction, in addition to optimizing the wavelength of exposure light and a reticle structure. This correction is called OPC (Optical Proximity Correction), and a correction amount of a transferred image of the pattern is calculated based on the influence of an optical proximity effect obtained by calculation or by an experiment, considering lighting conditions (NA, Sigma), exposure conditions (a material of the resist, exposure wavelength) and so on of a stepper, thereby correcting the reticle size.
However, there is a factor uncorrectable by OPC, for example, size difference in scarce and dense patterns that is caused by flare of the stepper or at the time of etching, and the size of the formed patterns varies. The flare of the stepper is generated by minute irregularities of a lens or variation in refractive index of a lens, or by reflected and scattered light on a wafer surface. Further, local occurrence of flare depending on the condition of a surrounding area of each pattern has recently been recognized as a problem. This is a so-called local flare, and it is caused by peculiarity of a material of the lens depending on the wavelength (short wavelength of, typically, 193 nm) of the exposure light used and is a major factor of causing an unexpected change in shape and line width of the transferred pattern. Further, in etching, a region having a large etched area runs short of reaction gas or has increased reactive products, which causes precision deterioration of pattern formation depending on the area or the size in some region.
However, precise correction of such size variation caused by the local flare of the stepper and the loading effect in etching is difficult.
The above-described local flare should be quantified and eliminated in order to accurately form desired patterns in a semiconductor device, but this is a problem which has drawn attention just recently as described above, and therefore, currently no suitable technique of intentionally solving this specific problem of the local flare has been devised.
Further, in the optical proximity effect correction, the optical proximity effect is calculated based on patterns in a region within several μm, but time restriction makes it difficult to widen a calculation range to several ten μm as is required for the calculation of the influence of the flare, and it has been difficult to explain the influence of flare by the proximity effect of light intensity. Moreover, the influence of the loading effect in etching, as a matter of course, cannot be accounted for by optical intensity calculation.
The present invention was devised to solve the above-described problems, and an object of the present invention is to provide a pattern size correcting device and a pattern size correcting method that enable quantitative estimation of size variation occurring in patterns exposed in lithography and easy and accurate correction of pattern size based on this estimation, thereby enabling production of an extremely reliable device.

Pattern size correcting device and pattern size correcting method


An apparatus for cleaning firearms comprises a rod, a handle, a first cylindrical body portion, a second cylindrical body portion, a stick, and a fiber wad. The handle is attached to an end of the rod. The first cylindrical body portion defines a channel and a longitudinal break in a sidewall of the first cylindrical body portion. The channel and the longitudinal break extend into the first cylindrical body portion from a first end of the first cylindrical body portion, and the longitudinal break at least partially merges with the channel. At the same time, the second cylindrical body portion is attached to a second end of the cylindrical body portion and has a smaller diameter than the first cylindrical body portion. The stick is at least partially inserted into the channel. Lastly, the fiber wad is wrapped around at least a portion of the stick.

A barrel of a long gun such as a rifle or shotgun is traditionally cleaned by attaching a solvent-soaked patch to a long cleaning rod and passing the patch through the barrel of the firearm. The patch typically comprises a small square or circular section of cloth. The patch is attached to the cleaning rod by feeding it through a slotted tip attached at one end of the cleaning rod.
Nevertheless, despite their widespread use, conventional cleaning patches are not particularly well suited for cleaning firearms. Conventional cleaning patches, when being passed through a rifled barrel, for example, tend to slide over the lands and grooves of that barrel. This results in residual contamination in the barrel, even after intensive attempts at cleaning
Because of the shortcomings of conventional patches for cleaning guns, there has been recent interest in utilizing swabs as an alternative means for cleaning firearms. These swabs consist of fiber wads wrapped around the ends of wooden or plastic sticks. The fiber wads are sized to hold an appropriate amount of solvent and, at the same time, to tightly fit into the barrel of the firearm being cleaned so that the fiber wads contact the entire inner surface of the barrel. At the same time, the swabs are relatively inexpensive, and can be thrown away after just a single use. Nevertheless, while very useful for cleaning handguns with their shorter barrels, a swab would need to have a very long stick length in order to be useful for cleaning long arms. Unfortunately, the sticks used in conventional swabs are typically not of great enough strength to support this kind of extra length. That is, they would be likely to bend and break.
For the foregoing reasons, there is a need for apparatus that allow conventional swabs (with sticks) to be utilized to clean firearms having relatively long barrels.


A medium carrying device that carries a medium includes a first roller, a second roller, a rotation transmitting part that drives its rotation by a driving force transmitted from a driving force source, and moves between at a transmitting position and at a releasing position, at the transmitting position, the rotation transmitting part transmits the driving force to the first roller, at the releasing position, the rotation transmitting part does not transmit the driving force, a transmission releasing part that is connected to the rotation transmitting part. When the medium is bowed between the first and second rollers, the transmission releasing part moves the rotation transmitting part from the transmitting position to the releasing position according to the bowing of the medium.

Conventionally, a widely-available printer forms a toner image by an exposure device such as an LED head, transfers this onto a medium such as a sheet of paper, and fuses the toner image on the sheet by a fuser, thereby forming an image on the surface of this sheet.
This printer contains in its interior, for example, sheets stacked in a sheet cassette, and forms a carrying path so as to connect sequentially the sheet cassette, the exposure device, the fuser, etc. by a carrying part that carries these sheets. The carrying part comprises, for example, a guide to guide a bill, a roller to transmit a driving force to the bill, etc., sets two rollers that oppose each other across the carrying path of the bill for example as a roller pair, and disposes these roller pairs everywhere along the carrying path (see Patent Document 1 for example).
This printer employs rotating rollers etc. to separate sheets in the sheet cassette into individual sheets and hand each over to the carrying part and carries this sheet by handing it over between roller pairs along the carrying path in the carrying part.

Medium carrying device and image forming apparatus


Embodiments are disclosed for generating an infrared mark indicator comprised of security information in a printed image. Image data is rendered to a CMYK image. A black plane of the CMYK image is separated and transformed to a frequency domain wherein the frequency components are alternated to encode the watermarking message. The CMY values are selected based on the encoded black value in order to maintain a same color appearance image for the printed image under a normal visual light illuminant. The image data is printed on the substrate in accordance with the transformed planes wherein upon the resultant printed image being exposed to infrared illuminant, a print pattern is detectable as an infrared mark when scanned with an infrared sensing device.

Since print systems have been in existence, printers have sought methods for inhibiting counterfeiting and unauthorized copying of printed documents. Enhanced complexity in an engraved pattern of a press plate is one such method that most people are familiar with as a result of its everyday observation in currency bills. Bank checks, security documents, bonds and other financial documents are other examples of printed documents having complex background patterns to inhibit unauthorized reproduction. Identification documents, e.g. passports, social security cards and the like, are other examples. Credit cards not only have complex background patterns, but now also have embedded holographics to enhance verification and authentication of such a card.
It is desirable to have a way to provide for the detection of counterfeiting, illegal alteration, and/or copying of a document, most desirably in a manner that will provide document security and which is also applicable for digitally generated documents. It is desirable that such a solution also have minimum impact on system overhead requirements as well as minimal storage requirements in a digital processing and printing environment. Additionally, it is particularly desirable that this solution be obtained without physical modification to the printing device and without the need for costly special materials and media.
Watermarking is a common way to ensure security in digital documents. Many watermarking approaches exist with different trade-offs in cost, fragility, robustness, etc. One prior art approach is to use special ink rendering where the inks are invisible under standard illumination. These inks normally respond to light outside the visible range and thereby may be made visible. Examples of such extra-spectral techniques are UV (ultra-violet) and IR (infrared). This traditional approach is to render the encoded data with special inks that are not visible under normal light, but have strong distinguishing characteristics under the special spectral illumination. Determination of the presence or absence of such encoding may be thereby subsequently performed using an appropriate light source and detector. One example of this approach is found in U.S. Patent Application Publication No. US-2007-0017990 to Katsurabayashi et al., which is herein incorporated by reference in its entirety for its teachings. However, these special inks and materials are often difficult to incorporate into standard electro-photographic or other non-impact printing systems like solid ink printers, either due to cost, availability or physical/chemical properties. This in turn discourages their use in variable data printing arrangements, such as for redeemable coupons or other personalized printed media for example.
Another approach is digital watermarking, as for example U.S. Pat. No. 5,734,752 to Knox, where there is provided a method for generating data encoding in the form of a watermark in a digitally reproducible document which is substantially invisible when viewed including the steps of: (1) producing a first stochastic screen pattern suitable for reproducing a gray image on a document; (2) deriving at least one stochastic screen description that is related to said first pattern; (3) producing a document containing the first stochastic screen; (4) producing a second document containing one or more of the stochastic screens in combination, whereby upon placing the first and second document in superposition relationship to allow viewing of both documents together, correlation between the first stochastic pattern on each document occurs everywhere within the documents where the first screen is used, and correlation does not occur where the area where the derived stochastic screens occur and the image placed therein using the derived stochastic screens becomes visible.
U.S. Patent Application Publication No. US-2008-0302263-A1 discloses a system for creating an infrared mark employing the different infrared transmission characteristics of standard non-impact printing materials, specifically the different infrared transmission characteristics of the four (CMYK) or more printing colorants, whereby the application of such infrared transparent colorants on a substrate results in a high level of infrared reflectance of the combination due to the substrate reflectance characteristics. The infrared mark is created by printing the first colorant combination with a relatively high infrared reflectance in direct spatial proximity to a second colorant combination having the essentially same visual response under visible light, while having a different infrared reflectance by changing the relative amounts of the colorants in the mixture in a manner that is essentially invisible to the human eye under normal illumination.
The underlying principal is that carbon-base black toner is a good absorber of infrared light, while the other toners (e.g., cyan, magenta and yellow) are almost transparent in the infrared region. This infrared watermark and distracting background are rendered with two different GCR (Gray Component Replacement) strategies that either maximize or minimize the usage of black toner. This system is limited in that the watermark critically depends on the accurate printer characterization and might be perceptible due to the poor printer characterization or the printer drift from time-to-time. In other words, the high IR absorption component (K) color of the mark may not match the low absorption component (CMV) color under normal light conditions so that the document is not acceptable for practical or commercial use.
Watermarking in frequency domain is also known and usually involves alternating frequency components according to watermarking messages. Such techniques result in a watermark that is dispersed throughout the image. However, all such known methods are based on visible lights and so can be human perceptible as well as machine.
More particularly, there is a need for a system which is based on IR detectable security information that has advantages over conventional frequency domain watermarking in two main aspects: (1) it easily enables "blind decoding", more specifically, the original image is not necessarily required in the decoding process and as a result, the method can be used more broadly in many applications, and (2) the method is less noisy. In conventional methods, the watermark noise is one of the limiting factors in design consideration. The desired method would conceptually reach zero (visual) noise.
There is thus a need for a system which better hides an infrared watermark within a printed document without being subject to system temporal change.

Embedding frequency modulation infrared watermark in digital document


A video compression circuit comprises an input that receives an input video signal. A memory buffer, coupled to the input, temporarily stores a portion of the input video signal. A single horizontal filter bank, coupled to the memory buffer, high-pass and low-pass filters horizontal components of the input video signal. A single vertical filter bank, also coupled to the memory buffer, high-pass and low-pass filters vertical components of the input video signal. A recursion buffer, coupled to the filter banks, temporarily stores filter components of the input video signal for recursive filtering.

Data compression techniques aim to enable information to be represented as accurately as possible with a reduced amount of data (i.e., fewer bits compared to the original data). By reducing the number of bits required to be transmitted and stored by information transmission/storage systems, data compression techniques greatly reduce memory size and bandwidth (i.e., bus widths, etc.) requirements of such systems. Additionally, information recovery speed can be increased. There are many types of data compression techniques. Broadly, all data compression techniques fall into one of two categories: lossless (i.e., information preserving) and lossy. Lossy techniques can reproduce the original only imperfectly, but the loss in accuracy of reproduction may be made quite small.
One class of data compression techniques which can be used for both lossy and lossless compression implements a mathematical transform to translate a time-domain input signal to the frequency domain, thus revealing the signal's spectral components from the known temporal components. In implementing the transform, filters commonly are employed to break down the input signal into multiple frequency bands, each band having at least a portion of the information needed to reconstruct the input signal. Most approaches then remove redundant and unneeded data present among the multiple frequency bands. Various transformers are employed, depending on factors such as the type of signal being compressed, the amount of compression needed, the available processing capability and the required reproduction fidelity.
A well-known basic time/frequency transform called Fourier Transform (FT), uses orthonormal basis functions of sine and cosine waveform to provide a frequency domain representation of a time domain function. The FT technique is not well-suited for lossless video or image compression, though. Because the basis sine and cosine signals are boundless (they ideally extend infinitely in each direction), the FT works under the assumption that the original time-domain function is periodic in nature. The FT, as a result, does not accurately translate functions having transient components localized in time (i.e., signals, such as video signals, having sharp transitions). This is so because the FT frequency domain spectrum does not explicitly show the time localization of frequency components of an input function, necessary for efficient compression of input functions having transients.
While such a time localization can be obtained by suitably pre-windowing an input signal, as is done in Short-Time FT (STFT), an inherent limitation in the STFT results in a time resolution/frequency resolution tradeoff and poor discretized breakdown and reconstruction of input signals. The Gabor expansion to the STFT enables improved discretized breakdown and reconstruction of signals by using basis signals that are well localized and concentrated in time and frequency, but requires use of accurate, multi-tap, expensive filters to produce the FT frequency plot.
Discrete Cosine Transform (DCT) compression schemes, commonly used with JPEG, MPEG and H.261 video formats, do not correlate well to the broad-band nature of video images due to the use of sinusoidal reference (basis) signals. In addition, DCT compression schemes require an image to be broken down into sub-blocks for filtering and suffer from image degradation at high compression ratios due to block artifacts ("the block effect"). Other compression techniques, such as those utilizing Gaussian and Laplacian transforms, while able to yield considerable compression due to the removal of substantial redundancies among frequency sub-bands, cannot very accurately reproduce the original signal also due to such drawbacks as the "block effect". Such techniques, therefore, also are not well-suited for lossless video or image compression applications which are the principal application of the present invention.
Recently, the use of wavelet transforms has received considerable attention because, by contrast with the aforementioned techniques, their properties make them well-suited for lossless video and image compression applications. Due at least in part to the bound nature of the reference wavelet basis, as well as to the orthoganality of the wavelet basis at different frequency scales, near-perfect reconstruction of a compressed video signal can be achieved. In addition, relatively simple and compact filter banks can be constructed to implement the ("near perfect") wavelet-based decomposition/reconstruction.
Typically, during wavelet-based decomposition, a frequency band of an image signal is decomposed into a number of sub-bands by a bank of bandpass filters. Each sub-band then is translated to a lower frequency band (baseband, for example) by decimating (down-sampling) it and thereafter encoding it. During reconstruction, each encoded sub-band is decoded and then interpolated (up-sampled) back to its original frequency band. The bands then are summed to provide a replica of the original image signal.
The Mallat version of the wavelet transform enables two-dimensional decomposition/reconstruction. Due to the recursive (to achieve the multi-sub-band plot) nature of the wavelet transform, however, a considerable amount of buffer memory may be required to store temporarily information in the filter pipeline. Additionally, due to the mathematical properties of the wavelet basis and transform, most prior art approaches to wavelet-based video image compression have been implemented in software.
It is a general object of the present invention to provide a simple, yet accurate, lossless wavelet-based video image compression technique that requires a minimal amount of buffer memory and is implementable in hardware, preferably on a single monolithic substrate.

Method and apparatus for using minimal and optimal amount of SRAM delay line storage in the calculation of an X Y separable mallat wavelet transform


Disclosed are Group II metal overbased sulfurized alkylphenate compositions and in particular to Group II metal overbased sulfurized alkylphenate compositions derived from alkylphenols enriched in alkyl substituents attached to the phenol ring in an "end" position.

1. Field of the Invention
This invention is directed to Group II metal overbased sulfurized alkylphenate compositions and, in particular, to Group II metal overbased sulfurized alkylphenate compositions derived from alkylphenols enriched in substantially straight chain C.sub.10 to C.sub.16 alkyl substituents attached to the phenol ring in an "end" position.
2. State of the Art
The operation of diesel and spark ignition internal combustion engines is typically accompanied by the formation of sludge, lacquer and resinous deposits which adhere to the moving engine parts and thereby reduce engine efficiency. In order to prevent or reduce the formation of these deposits, a wide variety of chemical additives have been developed for incorporation into lubricating oils. These additives are commonly referred to as detergents and dispersants. Dispersants have the ability to keep deposit forming materials suspended in the oil so as to retard deposit formation during engine operation. Detergents have the ability to remove preexisting deposits from the engine during engine operation.
Among the many additives which have been developed for this purpose, Group II metal overbased sulfurized alkylphenate compositions have been found to be highly effective detergent/dispersants for use in lubricating oils. Furthermore, these additives are excellent oxidation and corrosion inhibitors and, by virtue of their alkalinity reserve, have the ability to neutralize acidic combustion and oxidation products. Such acidic products form during engine operation, particularly when operated on high sulfur containing fuels, and tend to accumulate in the lubricating oil. The ability of Group II metal overbased sulfurized alkylphenate compositions to neutralize such acidic products can be directly measured by determining the total base number (TBN) of the composition. Higher TBNs reflect a greater capacity for these compositions to neutralize acids generated during engine operation.
The preparation of Group II metal overbased sulfurized alkylphenate compositions is well known in the art and is described in detail in, for example, U.S. Pat. Nos. 3,178,368; 3,367,867; and 4,744,921, each of which is incorporated herein by reference in its entirety. Typically, such Group II metal overbased sulfurized alkylphenate compositions are prepared by treating alkyphenol in a suitable diluent (e.g., a lubricating oil) with an amount of an alkaline earth metal hydroxide, oxide and/or alkoxide in excess of that necessary to neutralize the phenol and then sulfurizing the resulting product optionally in the presence of a sulfurizing catalyst. The sulfurized product is then optionally treated with carbon dioxide to provide for the Group II metal overbased sulfurized alkylphenate composition.
Such Group II metal overbased sulfurized alkylphenate compositions are additive compositions which are used to prepare a fully formulated lubricant composition suitable for use in an internal combustion engine. Typically, the additive composition is prepared as a concentrate and is then shipped to a point where it is used to prepare fully formulated lubricant compositions by combining requisite amounts of several additive compositions, including a Group II metal overbased sulfurized alkylphenate composition, to a base stock.
In order to reduce shipping costs, the Group II metal overbased sulfurized alkylphenate composition is preferably prepared to contain as little diluent as possible. Additionally, in order to achieve the maximum amount of acid neutralization possible, the Group II metal overbased sulfurized alkylphenate composition is preferably prepared to contain as high a TBN as possible. However, because of viscosity considerations, these constraints cannot be totally satisfied and a balancing of the TBN and the amount of diluent employed with the viscosity of the Group II metal overbased sulfurized alkylphenate composition is required.
Specifically, when the amount of diluent is decreased, the viscosity of the composition is increased. Likewise, at constant diluent concentrations, increasing the TBN of the Group II metal overbased sulfurized alkylphenate compositions by using incremental amounts of alkaline earth metal oxide and/or hydroxide and/or alkoxide optionally in the presence of carbon dioxide is accompanied by increases in the viscosity of the composition. When the viscosity of the composition becomes too great, the composition becomes difficult to use in formulation procedures primarily because of handling problems. When this occurs, the viscosity of the composition must be reduced and this can be accomplished either during its manufacture by reducing the amount of carbon dioxide and alkaline earth metal oxide, hydroxide or alkoxide employed or after its manufacture by adding additional diluent.
Thus, while Group II metal overbased sulfurized alkylphenate compositions produced in the prior art are reported to possess TBNs of up to about 350 or more, in practice, commercial Group II metal overbased sulfurized alkylphenate compositions typically have a TBN of less than about 300, and more typically less than about 275, so as to ensure that the composition possesses acceptable viscosity.
In view of the above, it would be particularly desirable to reduce the viscosity of Group II metal overbased sulfurized alkylphenate compositions. In particular, such reductions would mean that at constant viscosity, a higher TBN could be achieved or at constant TBN, a lower viscosity could be achieved.
In this regard, Liston, U.S. Pat. No. 4,744,921, discloses that, at constant TBN, the use of a sulfurization catalyst during synthesis of the Group II metal overbased sulfurized alkylphenate composition reduces the viscosity of the composition as compared to the viscosity of the composition prepared without a sulfurization catalyst. However, notwithstanding the reductions achieved by using such sulfurization catalysts, it would be particularly beneficial to provide for alternative methods to reduce the viscosity of the Group II metal overbased sulfurized alkylphenate compositions or to provide for any incremental reductions in the viscosity of these compositions.

Low viscosity group II metal overbased sulfurized C.sub.10 to C.sub.16 alkylphenate compositions