A test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for alternately storing vector instructions read out from vector memory and bank memories; an address expander for generating an address of each of control instructions in control memory in accordance with vector instructions stored in a plurality of bank memories; and a test pattern calculator for generating test patterns based on control instructions read out from an address generated by an address expander stored in the control memory.

This patent application claims priority based on a Japanese patent application, H10-295157 filed on Oct. 16, 1998, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory testing device, and more particularly to a memory testing device, a high speed test pattern generator, and a method of generating a plurality of high speed test patterns.
2. Description of the Related Art
The conventional semiconductor memory testing device is shown in FIG. 1. The conventional semiconductor memory testing device comprises a sequence controller 62 and a pattern former 26. The sequence controller 62 controls the generating order of the test patterns for testing a semiconductor memory device. The sequence controller 62 generates an address signal 102 to be output to the pattern generator 26. The pattern generator 26 generates an address pattern signal 106, a data pattern signal 108, and a read write pattern signal 110. The address pattern 106 is input to address input pins of the memory device. The data pattern signal 108 is a data to be written on the memory device. The read and write pattern signal 110 assigns either a write cycle in which the data of the data pattern signal 108 is written on the memory device, or a read cycle in which the data written on the memory device is read out and compared with an expected signal, which is same as the data pattern signal 108.
The sequence controller 62 comprises a vector memory for storing vector instructions which indicate the generating order of the test patterns, a read out controller 14 for reading out the vector instructions from the vector memory 12, a vector cache memory including bank memories 16A and 16C, a pattern multiplexer for selecting either of the bank memories 16A and 16C to output the instructions, and an address expander 22 for generating the address signal 102 based on the instructions input from the pattern multiplexer 20. When the vector instructions read out from the vector memory 12 are being stored into one of the bank memories 16A and 16C, the vector instructions stored in the other of the bank memories 16A and 16C are read out and input to the address expander 22 via the pattern multiplexer 20.
The pattern former 26 comprises a control memory 32 for storing a pattern program to generate each of the test patterns, and a test pattern calculator 36 for generating the test patterns based on the pattern program stored in the control memory 32. The control memory 32 comprises an address control memory 32a, a data control memory 32b and a read and write control memory 32c. The test pattern calculator 36 comprises an XB register for generating an address pattern signal 106, a TP register for generating a data pattern signal 108, a multiplexer, and an XOR circuit. The address signal 102 generated by the sequence controller 62 is input to the address control memory 32a, the data control memory 32b, and the read and write control memory 32c.
The test pattern calculator 36 generates the address pattern signal 106, the data pattern signal 108, and a read and write signal 110 based on the address signal 102 and the pattern signal stored in the control memory 32c. The pattern signal 106 is calculated based on the instructions read out from the address control memory 32a. The data pattern signal 108 is calculated based on the instructions read out from the data control memory 32b and the read and write control memory 32c. The instructions read out from the read and write control memory 32c are directly output as the read and write pattern signal 110.
FIG. 2 shows instructions stored in the address control memory 32a, the data control memory 32b, and the read and write control memory 32c of the control memory 32. The instruction shown as xe2x80x9cXB less than 0xe2x80x9d indicates that the value of the XB register will be zero in the next cycle. The instruction shown as xe2x80x9cXB less than XB+1xe2x80x9d indicates that the value of the XB register increases by 1 in the next cycle. The instruction shown as xe2x80x9cXB less than XBxe2x80x9d indicates that the value of the XB register does not change in the next cycle. The instruction shown as xe2x80x9cTP less than 0xe2x80x9d indicates that the value of the TP register will be zero in the next cycle. The instruction shown as xe2x80x9cTP less than TPxe2x80x9d indicates that the value of the TP register does not change in the next cycle. The instruction shown as xe2x80x9cTP less than /TPxe2x80x9d indicates that the value of the TP register is inverted in the next cycle. The instruction shown as xe2x80x9cRxe2x80x9d indicates that the read pattern signal is generated in the current cycle, and the instruction shown as xe2x80x9cWxe2x80x9d indicates that the write pattern signal is generated in the current cycle. The instruction shown as xe2x80x9c/Dxe2x80x9d indicates that the pattern signal is inverted for output in the current cycle.
For example, when the value of the address signal 102 input to the pattern former 26 is #0, the instruction read out from the address control memory 32a to the test pattern calculator 36 is xe2x80x9cXB less than 0xe2x80x9d, and the instruction read out from the data control memory 32b to the test pattern calculator 36 is xe2x80x9cTP less than 0xe2x80x9d. When the value of the address signal 102 input to the pattern former 26 is #1, the instruction read out from the address control memory 32a to the test pattern calculator 36 is xe2x80x9cXB less than XB+1xe2x80x9d. In this case the instruction read out from the data control memory 32b to the test pattern calculator 36 is xe2x80x9cTP less than TPxe2x80x9d and the instruction read out from the read and write control memory 32c to the test pattern calculator 36 is xe2x80x9cWxe2x80x9d. The test pattern calculator 36 generates the address pattern signal 106, the data pattern signal 108, and the read and write pattern signal 110 based on the instructions input.
FIG. 3 shows an example of the sequence control instruction stored in the address expander used for generating the address signal 102. The instruction xe2x80x9cNEXTxe2x80x9d of the address #0 indicates that the instruction of the next address, the address #1 in this case, should be output. The instruction xe2x80x9cREPEATxe2x80x9d indicates that the instruction of the current address should be repeatedly output xe2x80x9cnxe2x80x9d times, and following this the instruction of the next address should be output. The instruction xe2x80x9cJNI A nxe2x80x9d indicates that the instruction of the address marked with a label xe2x80x9cAxe2x80x9d should be output xe2x80x9cnxe2x80x9d times, and then the data of the next address should be output. In the example shown in FIG. 3, the address #3 includes the instruction xe2x80x9cJNI A 2xe2x80x9d, and the address #2 is marked with a label xe2x80x9cAxe2x80x9d. The data from the address #2 is output twice at the address #3, and then the data. from the address #4 is output. The instruction xe2x80x9cSTOPxe2x80x9d indicates that the test should be terminated. The address expander generates the address signal 102 in accordance with these sequence control instructions to be output to the pattern former 26.
FIG. 4 shows compressed instructions stored in the vector memory 12. The sequence control instructions are extremely large in practical usage, so high speed memory with a large capacity. is required to store all of the sequence control instructions. Therefore, the sequence control instructions shown in FIG. 3 are compressed for storage in the vector memory 12 in order to save the capacity of the memory. The compressed instructions shown in FIG. 4 are the same as the sequence control instructions shown in FIG. 3. The sequence control instruction xe2x80x9cNEXTxe2x80x9d shown in FIG. 3 is omitted and the remainder of the sequence control instructions are stored in the vector memory 12 with each address of the instruction written next to the respective instruction.
The compressed instruction xe2x80x9cREPEAT 4 #1xe2x80x9d stored in the vector memory address #0 of the vector memory 12 indicates that the sequence control instruction of the address #1 is xe2x80x9cREPEAT 4xe2x80x9d. The compressed instruction xe2x80x9cJNI 2 #3 #2xe2x80x9d stored in the vector memory address #1 indicates that the sequence control instruction of the address #3 is xe2x80x9cJNI 2xe2x80x9d, and the instruction of the address #2 should be output twice. The compressed instruction xe2x80x9cJNI 1 #5 #2xe2x80x9d stored in the vector memory address #2 indicates that the sequence control instruction of the address #5 is xe2x80x9cJNI 1xe2x80x9d, and the instruction of the address #2 should be output. The compressed instruction xe2x80x9cSTOP #6xe2x80x9d stored in the vector memory address #3 indicates that the sequence control instruction of the address #6 is xe2x80x9cSTOPxe2x80x9d.
FIG. 5 shows instructions transferred from the vector memory 12 to the bank memories 16A and 16C. The sequence control instructions may include a plurality of loops as shown in FIG. 4. Expanding the plurality of loops into successive instructions may delay the generation of the address signal 102. Therefore, the read out controller reads out the compressed instructions stored in the vector memory 12 and expands the read out compressed instructions to be transferred to the bank memories 16A and 16B. As is understood from FIGS. 4 and 5, the instruction of the outside loop xe2x80x9cJNI 1 #5 #2xe2x80x9d is converted to a simple instruction xe2x80x9cJMP #5 #2xe2x80x9d indicating that the address of the instruction to be output jumps to the address #2 at the address #5. The instruction of the inside loop xe2x80x9cJNI 2 #5 #2xe2x80x9d is converted to two separated instructions. When the instruction xe2x80x9cJMP #5 #2xe2x80x9d is input, the address expander 22 outputs the instruction of the address #2. Because the instruction of the address #2 is xe2x80x9cNEXTxe2x80x9d, the instruction of the address #3 xe2x80x9cJNI 2 #3 #2xe2x80x9d is output as the address signal 102.
FIG. 6 shows the operation to generate the test patterns based on the compressed instructions shown in FIG. 4. The compressed instructions stored in the vector memory 12 are expanded and transferred to the bank memories 16A and 16C. The address expander 22 generates the address signal 102 in accordance with the instructions expanded in the bank memories 16A and 16C and outputs the address signal 102 to the pattern former 26. In this embodiment shown in FIG. 6, the maximum value of the XB register is #3. When the value of the XB register exceeds #3, the value becomes #0. The effective value of the TP register is #FF (F means 15 out of 16 numbers or 15/16). The value of the TP register inverts within the effective number.
Firstly, the address expander 22 accepts the compressed instruction xe2x80x9cREPEAT 4 #1xe2x80x9d of the cache memory address #0 input from the bank memory 16A. The address expander 22, then repeatedly outputs the data of the address #1 4 times. The next compressed instruction is xe2x80x9cJNI 2 #3 #2xe2x80x9d, therefore the address expander 22 outputs the data of the address #2 and #3 in order. The address expander then repeatedly outputs the data from the address #2 and #3 twice in accordance with the compressed instruction xe2x80x9cJNI 2 #3 #2xe2x80x9d of the cache memory address #1 input from the bank memory 16A. The next compressed instruction is xe2x80x9cJMP #5 #2xe2x80x9d, which means that the sequence control instructions of the address #4 is xe2x80x9cNEXTxe2x80x9d. The address expander 22 then outputs the instruction of the address #4 and #5 in order. The address expander outputs the instruction of the memory address #2 in accordance with the compressed instruction xe2x80x9cJMP #5 #2xe2x80x9d of the cache memory address #2 input from the bank memory 16A. As the sequence control instruction of the address #2 is xe2x80x9cNEXTxe2x80x9d, the address expander 22 outputs the instruction of the address #3 in order. The next compressed instruction is xe2x80x9cJNI 2 #3 #2xe2x80x9d, so the address expander 22 outputs the sequence control instructions of the address #2 and #3 twice. The next compressed instruction is xe2x80x9cSTOP #6xe2x80x9d, which means that the sequence control instructions of the address #4 to the address #6 are xe2x80x9cNEXTxe2x80x9d and address expander 22 outputs the instruction of the address #4 to #6 in order. The test is then terminated.
The pattern former 26 accepts the address signal 102 from the sequence controller 62 and outputs the control instructions stored in each of the control memories 32a, 32b, and 32c.
In the first cycle, the value of the address signal 102 is #0, therefore the XB register receives the address control instruction xe2x80x9cXB less than 0xe2x80x9d stored in the address #0 of the address control memory 32. The value of the XB register is set at #0 in this case. In the next cycle, the value of the address signal 102 is #1, therefore the address control instruction xe2x80x9cXB less than XB+1xe2x80x9d is read out from the address control memory 32a and the pattern former 26 adds 1 to the value of the XB register. This results in the value of the XB register becoming #0+1=#1. The address signal 102 having a value #1 is repeatedly output 3 times. The pattern former 26 adds 1 to the value of the XB register each time the address signal 102 having the value #1 is output. When the value of the XB register is #3 and the value 1 is added to the XB register, the value of the XB register becomes #0.
In the next cycle, the address signal 102 having the value #2 is output. Following this the address control instruction xe2x80x9cXB less than XBxe2x80x9d is read out from the address control memory 32a. The pattern former 26 keeps the value of the XB register at #0 as this is in accordance with the address control instruction xe2x80x9cXB less than XBxe2x80x9d. In the next cycle, the address signal 102 having the value #3 is output. The address control instruction xe2x80x9cXB less than XB+1xe2x80x9d is therefore read out from the address control memory 32a and the value of the XB register becomes #1. The address control instructions are read out from the address control memory 32a in accordance with the values of the address signal 102, in order. The test pattern calculator 36 generates the address pattern signals 106 in accordance with the address control instructions.
Similarly, the data control instructions are read out from the data control memory 32b and the value of the TP register is rewritten based on the data control instructions. When the address signal 102 whose data control instruction is xe2x80x9cTP less than 0xe2x80x9d is output, the data control instruction xe2x80x9cTP less than 0xe2x80x9d is read out from the data control memory 32b. The value of the TP register becomes #0. The result of this is the value of the data pattern signal 108 becomes #0. When the address signal 102 whose data control instruction is xe2x80x9cTP less than TPxe2x80x9d is output, the data control instruction xe2x80x9cTP less than TPxe2x80x9d is read out from the data control memory 32b. The value of the TP register is maintained as it is at this time. When the address signal whose data control instruction is xe2x80x9cTP less than /TPxe2x80x9d is output, the value of the TP register is inverted.
Similarly, when the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9cWxe2x80x9d, the instruction xe2x80x9cWxe2x80x9d is read out from the read and write control memory 32c. The test pattern calculator 36 outputs a read and write pattern signal 110 having the write cycle. When, on the other hand, the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9cRxe2x80x9d, the instruction xe2x80x9cRxe2x80x9d is read out from the read and write control memory 32c. The test pattern calculator 36 outputs a read and write pattern signal 110 having the read cycle. When the address signal 102 is output, whose instruction stored in the read and write control memory is xe2x80x9c/Dxe2x80x9d, the value of the TP register is inverted to be output as the data pattern signal 108. This means that the data pattern signal 108 becomes #FF when the value of the TP register is #0, and the data pattern signal 108 becomes #0 when the value of the TP register is #FF.
In FIG. 6 for example, the values of the address signal 102 from the second cycle to the fifth cycle are #1, therefore, the instruction xe2x80x9cWxe2x80x9d stored in the address #1 of the read and write control memory 32c is output 4 times. The W signal is output as the read and write pattern signal 110 at this time. In the sixth cycle, the value of the address signal 102 is #2, therefore the instruction xe2x80x9cRxe2x80x9d is read out from the read and write control memory 32c. The R signal is output as the read and write pattern signal 110. In the seventh cycle, the value of the address signal 102 is #3, therefore the read and write instruction xe2x80x9c/D Wxe2x80x9d is read out from the read and write memory 32c. The W signal is output as the read and write pattern signal 110 and the value of the data pattern signal 108 is inverted from #0 to #FF.
FIG. 7 shows another conventional semiconductor memory testing device capable of outputting address patterns at a high speed. Recently developed memory devices are operated at an extremely high frequency, making it difficult to generate address patterns at a high enough speed to allow testing of these memory devices by a single pattern former. Therefore a semiconductor memory testing device comprising a plurality of pattern formers is used to test these memory devices. The conventional semiconductor memory testing device shown in FIG. 7 comprises a plurality of pattern formers 26A and 26B to test a memory device operated with a high frequency. The pattern signals output from the plurality of pattern formers are simultaneously applied to the memory device 76. The sequence controller 62 shown in FIG. 7 is the same as the sequence controller shown in FIG. 1. The pattern formers 26A and 26B are the same as the pattern former 26 shown in FIG. 1. Therefore, the explanation will be omitted. The elements the same as the elements shown in FIG. 1 have the same marks and the explanation is therefore omitted.
FIG. 8 shows the instructions to be stored in the address control memory 32a of the pattern former 26A. The address control memory 32a comprises a normal field and an extended field. The instructions to go to the next address are stored in the normal field. The instructions not to go to the next address but to jump to other addresses are stored in the extended field. The data control memory 32b and the read and write control memory 32c respectively comprise normal fields and extended fields. This leads to the fact that the capacity of each of the memories 32a, 32b and 32c is required to be twice that of each of the control memories 32a, 32b and 32c shown in FIG. 1.
The instructions have been previously stored in the control memories 32 of the pattern formers 26A and 26B so that the desired address pattern signal 106, the data pattern signal 108, and the read and write pattern signal 110 are alternately generated by the pattern formers 26A and 26B. In the normal field of the address control memory 32a is stored an address control instruction obtained by combining two successive address control sequence instructions. For example, when the first address control sequence instruction xe2x80x9cXB less than 0xe2x80x9d and the second address control sequence instruction xe2x80x9cXB less than XB+1xe2x80x9d are combined, the value of the XB register becomes 1. Therefore, the instruction xe2x80x9cXB less than 1xe2x80x9d is stored in the normal field of the address control memory 32a.
The value of the XB register becomes 2 based on the next two address control instructions xe2x80x9cXB less than XB+1xe2x80x9d and xe2x80x9cXB less than XB+1xe2x80x9d, therefore the instruction xe2x80x9cXB less than XB+2xe2x80x9d is stored in the normal field of the address control memory 32a. Similarly, the instructions xe2x80x9cXB less than XB+1xe2x80x9d, xe2x80x9cXB less than XB+1xe2x80x9d, and xe2x80x9cXB less than XB+1xe2x80x9d are stored in the normal field. Stored in the extended field of the address control memory 32a, are the address control instructions obtained by combining two address control instructions which are not executed in sequential order. For example, in FIG. 8, the seventh sequence instruction xe2x80x9cXB less than XB+1xe2x80x9d, should be executed after the eighth sequence instruction xe2x80x9cXB less than XBxe2x80x9d is executed. When these two instructions are executed, the value of the XB register increases by 1. Therefore, the instruction xe2x80x9cXB less than XB+1xe2x80x9d is stored in the address #3 of the extended field of the address control memory 32a. The seventh instruction xe2x80x9cXB less than XB+1xe2x80x9d should be executed after the tenth instruction xe2x80x9cXB less than XBxe2x80x9d is executed. When these two instructions are executed, the value of the XB register increases by 1. Therefore, the instruction xe2x80x9cXB less than XB+1xe2x80x9d is stored in the address #4 of the extended field of the address control memory 32a.
FIG. 9 shows the data to be stored in the address control memory 32a of the pattern former 26B. The address control memory 32a of the pattern former 26B comprises a normal field and an extended field the same as the address control memory 32a of the pattern former 26A. The instructions to go to the next address are stored in the normal field. The instructions not to go to the next address but to jump to other addresses are stored in the extended field.
The combined address control instructions stored in the address control memory 32a of the pattern former 26A and the address control memory 32a of the pattern former 26B have different instructions. This means that the address control instructions stored in the address control memory 32a of the pattern former 26A should be obtained by combining the first and second address control instructions, and the third and fourth address control instructions of the address control sequence instruction. The address control instructions stored in the address control memory 32a of the pattern former 26B is same as the first address control instruction of the address control sequence instruction, obtained by combining the second and third address control instructions.
FIG. 10 shows a pattern program to be executed by the address expander 22 of the pattern generator shown in FIG. 7. One address signal 102 is generated by the pattern former 26A and the pattern former 26b, so the pattern program to be executed by the address expander becomes half. The pattern program should be set to obtain a desired pattern signal by taking the control instructions stored in the address control memories 32a and 32b of the pattern formers 26A and 26B. The pattern program is compressed for storage in the vector memory.
FIG. 11 shows an operational example of the pattern formers 26A and 26B shown in FIG. 7. The compressed instructions stored in the vector memory 12 are read out to the bank memories 16A and 16C in order and selected by the MUX 20 to be input to the address expander 22. The address expander 22 accepts the first compressed instruction xe2x80x9cJNI #3 #3 #3xe2x80x9d. When the address storing the first compressed instruction is #3, this means that the instruction xe2x80x9cNEXTxe2x80x9d is stored in the address #0, #1 and #2. The address expander 22 increases the value of the address signal 102 from 0 to 3. The value of the address #3 is output 3 times in accordance with the instruction xe2x80x9cJNI #3 #3 #3xe2x80x9d.
The value of the address signal varies by 0, 1, 2, 3, 3, 3, 3 as shown in FIG. 11. The address expander sets the value of the JFLG 104 as 1 when the value of the address is changed by the instruction xe2x80x9cJUMPxe2x80x9d. Otherwise, the value of the JFLG 104 becomes 0. The pattern former 26A outputs the address control instruction in accordance with the value of the address signal 102. At this time, the value of the extended field of the address control memory 32a is read out when the value of the JFLG 104 is 1, and the value of the normal field of the address control memory 32a is read out when the value of the JFLG 104 is 0.
The test pattern calculator 36 of the pattern former 26A changes the value of the XB register based on the address control instruction read out from the address control memory 32a and outputs the changed value. The test pattern calculator 36 of the pattern former 26B reads out the address control instruction from the address memory 32a in accordance with the address signal 102 and outputs the value. The value of the XB register of the pattern former 26B changes in accordance with the address control instruction read out from the address control memory 32a of the pattern former 26B. The high speed converter 30, shown in FIG. 7, selects either of the pattern formers 26A or 26B to output the signal. The address pattern signal shown in FIG. 11 is thus obtained. The data pattern signal 108 and the read and write signal 110 are obtained similarly.
The semiconductor memory testing device shown in FIG. 7 is capable of outputting the address patterns at a high speed. However, the control memory 32 of the semiconductor memory testing device shown in FIG. 7 is required to have a large capacity because when the instruction is xe2x80x9cREPEAT uneven numbersxe2x80x9d, an additional instruction xe2x80x9cNEXTxe2x80x9d is required to be written after the instruction xe2x80x9cREPEAT uneven numbersxe2x80x9d. Furthermore, new control instructions obtained by combining two control instructions to be stored in each of the control memories 32, the sequence control instructions and the compressed instructions have to be designed to correspond to the new control instructions. The pattern program is so large that it was difficult to design the compressed instructions in consideration of the new control instructions.
Therefore, it is an object of the present invention to provide a test pattern generator, a memory testing device, and a method of generating a plurality of test patterns which overcomes the above issues in the related art. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to solve the above-stated problem, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing a plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory, the bank memories alternatively storing the vector instructions; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a test pattern calculator for generating the test patterns based on the control instructions read out from an address generated by the address expander stored in the control memory.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a control memory for storing a plural kinds of control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a test pattern calculator for generating the test patterns based on the control instructions read out from an address generated by the address expander stored in the control memory.
Each of the vector instructions read out from the vector memory may be stored in each of the plurality of bank memories in order. The address expander may read out the vector instructions stored in the plurality of bank memories at the same time to generate an address of the control instructions in the control memory.
The test pattern calculator may comprise: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory comprising: a plurality of control memories storing substantially same control instructions to generate the test patterns; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories; an address expander for generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a test pattern generator for generating a plurality of test patterns to test a memory in a predetermined order comprising: a plurality of sub control memories each storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern, a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories; an address expander for generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a memory testing device for testing electrical characteristic of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; a test pattern calculator for generating the test patterns based on the control instructions stored in the control memory indicated by the address generated by the address expander; a pin data selector for changing the test patterns generated by the test pattern calculator so as to correspond to pin arrangements of the memory; a waveform generator for generating the test patterns changed by the waveform generator; a memory acceptor comprising a memory slot to accept the memory, applying the test patterns generated by the waveform generator to the memory, and receiving the output signal output from the memory; and a comparing unit for judging whether or not the memory is normal by comparing the output signal received by the memory acceptor with the expected signal output from the pin data selector.
Moreover, the present invention provides a memory testing device for testing electrical characteristic of a memory by comparing an output signal output. from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the control memory; a plurality of bank memories for storing the vector instructions read out from the vector memory; an address expander for generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; a test pattern calculator for generating the test patterns based on the control instructions stored in the control memory indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
Each of the vector instructions read out from the vector memory may be stored in each of the plurality of bank memories in order. The address expander may read out the vector instructions stored in the plurality of bank memories at the same time to generate an address of the control instructions in the control memory.
The test pattern calculator may comprise: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address expander may read out the vector instructions stored in the vector memory to generate an address of the control instructions in each of the plurality of sub control memories in order, for each of the plurality of sub control memories.
Moreover, the present invention provides a memory testing device for testing electrical characteristics of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a plurality of sub control memories for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal, the plurality of sub control memories storing substantially same control instructions; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of control memories; an address expander for generating addresses of the control instructions in each of the plurality of sub control memories for each of the plurality of sub control memories in accordance with the vector instructions stored in the vector memory; a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
Moreover, the present invention provides a memory testing device for testing electrical characteristics of a memory by comparing an output signal output from the memory when a predetermined signal is input to the memory with an expected signal output from a normal memory when the predetermined signal is input to the normal memory comprising: a control memory for storing a plural kinds of control instructions to generate a plurality of test patterns including the input signal and the expected signal; a plurality of sub control memories for storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least 2 cycles ahead of the new control instruction; a vector memory for storing vector instructions indicating an order of the control instructions to be read out from the plurality of control memories; an address expander for generating addresses of the control instructions in each of the plurality of sub control memories for each of the plurality of sub control memories in accordance with the vector instructions stored in the vector memory; a test pattern calculator for generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address generated by the address expander; and a memory acceptor applying the test patterns generated by the test pattern calculator to the memory, and receiving the output signal output from the memory.
The plurality of sub control memories may store substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern.
The test pattern generator may further comprise a vector cache memory for storing the vector instructions read out from the vector memory, wherein the address expander generates an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address expander may generate the address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern calculator may comprises: sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and a high speed converter for generating the test patterns by outputting the sub test patterns from pattern calculators.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a first storing step of storing a plural kinds of control instructions to generate the test patterns into a control memory; a reading out step of reading out the control instructions from a vector memory storing vector instructions indicating an order of the control instructions to be read out from the control memory; a second storing step of storing the vector instructions read out from the vector memory into a plurality of bank memories, the vector instructions being alternately stored into the bank memories; an address generating step of generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a pattern generating step of generating the test patterns based on the control instructions, indicated by the address and stored in the control memory.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a first storing step of storing a plural kinds of control instructions to generate the test patterns into a control memory; a reading out step of reading out the control instructions from a vector memory storing vector instructions, indicating an order of the control instructions to be read out from the control memory; a second storing step of storing the vector instructions read out from the vector memory into a plurality of bank memories; an address generating step of generating an address of each of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories; and a pattern generating step of generating the test patterns based on the control instructions indicated by the address and stored in the control memory.
The second storing step may store each of the vector instructions read out from the vector memory into each of the plurality of bank memories in order. The address generating step may generate an address of the control instructions in the control memory in accordance with the vector instructions stored in the plurality of bank memories at the same time.
The test pattern step may comprise steps of: generating sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and generating the test patterns by outputting the sub test patterns.
The control memory may comprise a plurality of sub control memories storing substantially same control instructions. The address generating step may generate an address of the control instructions in each of the plurality of sub control memories in order for each of the plurality of sub control memories.
The control memory may comprise a plurality of sub control memories, each of the sub control memories storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern. The address generating step may generate an address of the control instructions in each of the plurality of sub control memories in order for each of the plurality of sub control memories.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a storing step of storing substantially same instructions into a plurality of sub control memories storing to generate the test patterns; a read out step of reading out vector instructions indicating an order of the control instructions to be read out from the plurality of sub control memories from the vector memory; an address generating step of generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern generating step of generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address.
Moreover, the present invention provides a method for generating a plurality of test patterns to test a memory, comprising: a storing step of storing a control instruction for generating a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern into a plurality of sub control memories; a reading out step of reading out vector instructions stored in a vector memory and indicating an order of the control instructions to be read out from the plurality of sub control memories; an address generating step of generating an address of each of the control instructions in each of the sub control memories for each of the sub control memories in accordance with the vector instructions stored in the vector memory; and a test pattern generating step of generating the test patterns based on the control instructions stored in the plurality of sub control memories indicated by the address.
The storing step may generate substantially same control instructions to generate a new test pattern based on an earlier test pattern generated at least two cycles ahead of the new test pattern into the plurality of sub control memories.
The read out step may store the vector instructions read out from the vector memory into avector cache memory. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory may comprise a plurality of bank memories for storing the vector instructions read out from the vector memory, each of the bank memories storing each of the vector instructions in order. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The vector cache memory my comprise a plurality of bank memories for storing the vector instructions read out from the vector memory. The address generating step may generate an address of the control instructions in the plurality of sub control memories in accordance with the vector instructions stored in the vector cache memory.
The test pattern step may comprise steps of: generating sub test patterns based on the control instructions read out from the address of one of the sub control memories generated by the address expander, the sub test patterns being a part of the test patterns; and generating the test patterns by outputting the sub test patterns.
This summary of the invention does not necessarily describe all necessary features. The invention may also be a sub-combination of these described features.

Test pattern generator, a memory testing device, and a method of generating a plurality of test patterns


A processing device inputs a first processing-descriptive document and generates a second processing-descriptive document by deleting at least one description part illustrating processing performed, so as to call the next processing device, from the first processing-descriptive document. Further, the processing device calls the next processing device by using the second processing-descriptive document.

1. Field of the Invention
The present invention relates to a processing device, a processing method and a computer readable medium used therein the processing device.
2. Description of the Related Art
In the past, when a single processing step is finished by calling a plurality of Web services and making each of the Web services perform the processing, the processing step is performed mainly by a Web service that can interpret a sequential-processing-descriptive document such as a Web-services-business-process-execution-language (WSBPEL), for example. That is to say, the Web service that can interpret the sequential-processing-descriptive document receives a request including the sequential-processing-descriptive document, the request being transmitted from a client, calls different Web services in sequence and makes each of the Web services perform processing according to the sequential-processing-descriptive document, and transmits information about a result of the processing to the client. An example technology relating to the above-described configuration is disclosed in United States Patent Application No. 20040205376.
According to known methods, however, the main Web service capable of interpreting the sequential-processing-descriptive document receives the information about the result of the processing performed by the different Web service on every occasion, transfers the received processing-result information to the next Web service for calling, and makes the next Web service perform processing. That is to say, the main Web service has to receive the processing-result information every time the called Web service performs the processing. Namely, a processing load is placed on the main Web service.


A magnetic core for an electric motor has a ring-shaped yoke, teeth extending outwardly from the yoke, and a tooth tip extending from a distal end of each tooth. The core is formed from curved or coils strip laminations having teeth arranged in tooth groups. Each group has four tooth types arranged sequentially. Each tooth has left and right half tooth tips. The length of the half tooth tips vary according to tooth type. When assembled, first type tooth overlap with third type teeth and second type teeth overlap with fourth type teeth, whereby the opening of the winding slot is narrowed compared to laminations having all identical teeth.

A conventional magnetic core for a motor includes a ring-shaped yoke and a plurality of teeth extending outwardly from the yoke. Each tooth has a tooth tip at a distal end thereof. Each tooth tip has a left half tooth tip and a right half tooth tip. The length of the left and right half tooth tips are measured in the circumferential direction of the yoke and are equal.
The magnetic core is made by stacking a plurality of ring-shaped core laminations. If the core laminations are directly punched from sheet materials, a large amount of waste material will be produced.
In an improved solution, an elongated core lamination is punched from a rectangular sheet material, which elongated core lamination includes a connection portion and a plurality of teeth extending from the connecting portion. The connecting portion is bent to form a ring-shaped core lamination. A disadvantage of this method is that the length of the tooth tip is limited, which results in an unduly large opening of the winding slot of the magnetic core.

Method of making a magnetic core with tooth having overlapping short and long teeth distal ends


The present invention relates to pharmaceutical compositions with mucoadhesive and sustained release characteristics containing the association of the extract or fractions of Curcuma longa L. with curcuminoid content greater than 5% and Bidens pilosa (Bd) extract, which has an important proliferative and anti-inflammatory effect, for the treatment of inflammatory diseases of the oral cavity (stomatitis) and of the gastrointestinal tract, as, for example, mucositis induced by radiotherapy and/or chemotherapy and aphthous lesions. Additionally, inflammatory skin lesions and vaginal mucositis. These are compositions obtained from a liquid base formulation containing an aqueous-based solvent system. The subject of the present invention is, therefore, to obtain pharmaceutical preparations, to develop their obtainment processes and to establish their uses. These preparations contain an association between the Bidens pilosa (or its fractions) extract and the Curcuma longa (or its fractions) extract at 1:10 to 10:1 proportions, incorporated into semi-solid, liquid or solid pharmaceutical forms containing the synthetic or adhesive bio (mucus) component, diluents, carriers, binders, disintegrants, at the concentration ranges from 1 to 75% by weight, of the active agents of vegetable origin.

Mucositis induced by radiotherapy and/or chemotherapy is the most common complication in the treatment of malignant neoplasias, which affects 80 to 100% of patients. Mucositis is the most important acute side effect in the treatment of cancer. In patients undergoing radiation therapy with dose hyperfractionation the incidence is 100%, in conventional radiotherapy it reaches 97%, and when associated with chemotherapy it reaches 90%.
In cases of exclusive chemotherapy, the incidence reaches 22%. In bone marrow transplantation, the incidence of mucositis is 80 to 100%. The main clinical manifestations of mucositis include erythema, edema, bleeding, ulceration and pseudomembrane formation.
Ulcerations result in intense pain and almost always require nutritional support and analgesics through the parenteral route. Clinical evaluation and measurement of mucositis intensity are done using indexes proposed by WHO.
The difficulty of swallowing solid and liquid foods, limitation of speech and chewing, loss of weight and need for parenteral nutrition are complications resulting from mucositis. Another aggravating factor of mucositis is the susceptibility to infection by opportunistic microorganisms that invade damaged tissues predisposing them to severe infections and even sepsis, significantly increasing morbidity.
The painful component associated with the severity of mucositis may be sufficiently debilitating to cause a reduction of the proposed chemotherapy protocol and temporary or permanent interruption of radiotherapy.
Discontinuation of radiotherapy and changes in chemotherapy dose have been associated with increased tumor recurrence, with consequent decreased survival.
This complication results in hospitalization with increased cost of patient care. The treatments used for mucositis are palliative and diversified, involving prophylactic therapies and attempts to reduce pain.
Alternatives for the treatment of mucositis include the administration of antioxidants, such as amifostine, melatonin and allopurinol.
Mucosal protectors such as benzydamine sucralfate and anti-inflammatory drugs with anesthetic effect are also used.
However, a "gold standard" treatment for mucositis has not yet been established, and the development of new therapeutic resources that are effective and accessible to cancer patients and/or patients with an indication for bone marrow transplantation is extremely important.
Medications commonly used in cancer treatment, including methotrexate, which inhibits DNA synthesis, tend to produce mucositis. Similar effects are seen with alkylating agents, such as 5-fluorouracil, often used in the treatment of malignant tumors of the gastrointestinal tract.
The gastrointestinal cell destruction observed in the mucositis by antineoplastic and/or radiotherapy results from cell hypoproliferation, with villous atrophy, deepening of the crypts, resulting from absorption dysfunction, alteration in the secretion of electrolytes, mainly Na+ and K+, thus causing diarrhea.
Currently, some authors describe gastrointestinal mucositis as food mucositis, where it is observed inflammation, erosion and ulcerative lesions in the alimentary tract, secondary to cancer chemotherapy/radiotherapy or to previous procedures to bone marrow transplantation. In this context, vaginal mucositis in women has also been reported.
The mechanisms of food mucositis development and/or mucosal inflammatory processes have been described in four phases: initial period, restitution, inflammation, recovery. The initial phase occurs by the action of agents that block the synthesis of DNA by inhibition of topoisomerase and synthesis of the thymidylate. Alterations in the ribonucleic acid (RNA) molecule and formation of free radicals may also occur. These alterations inhibit mitotic processes, affecting cell integrity and provoking the influx of inflammatory and immune cells.
During the second phase, cell division stops for a few hours and apoptosis occurs. There is, therefore, an induction of the progressive loss of cells in the crypts, which activates the restitution processes. At this stage, there is a collapse in the depth and number of crypts, shortening of villi and depletion of goblet cells. This phase is characterized by fluid losses and bacterial colonization.
Finally, in the recovery process there is a significant cellular proliferation, which leads to the functional restoration of crypts and/or tissues. Therefore, there is a recovery of the tissue structures, such as villi, and the recovery of the absorptive surface of the intestine.
Apoptosis, or programmed cell death, in intestinal mucositis, may be physiological or induced by chemotherapy or radiotherapy. The large number of apoptotic cells generated in the intestinal crypt was observed in mice receiving chemotherapy and in intestinal biopsy samples from tumor patients who received antineoplastic treatment.
Previous studies (Sonis et al., 2004, Carl, 1995, Pico et al., 1998, Köstler et al., 2001, Epstein and Schubert 2003, Sonis, et al., 2004; Armstrong and McCaffrey, 2006) have considered that the genesis of chemotherapy-induced intestinal mucositis was correlated with apoptotic effects of cytotoxic drugs on small intestinal cells.
As an example, one can highlight cytotoxic drugs causing apoptosis in stem cells in the crypt of the small intestine, which inhibited the regeneration of the same and, therefore, created a deficit in the number of stem cells. This deficit generated morphometric alterations such as villus atrophy and crypt hypoplasia in the intestine. Thus, apoptosis plays a critical role in chemotherapy-induced mucositis.
Therefore, one of the purposes of this invention is to provide a composition which exerts inhibitory and/or controlling action on chemotherapy-induced intestinal apoptosis.
The mechanism of induction of small cell intestinal apoptosis by chemotherapy is still uncertain but may be correlated with the release of pro-inflammatory factors such as IL-1β due to pathophysiological changes of the intestinal mucosa that received chemotherapy.
Studies have shown that IL-1β has its expression significantly increased in the intestinal mucosa tissue of rats receiving chemotherapy. High IL-1β expression was also observed in animal model peripheral blood serum receiving chemotherapy (Wu et al., 2011; Wu et al., 2010).
Although IL-1β is involved in the inflammatory reaction of the organism, other studies have found that this cytokine could induce the apoptosis phenomenon in several cell types. Induction of apoptosis in various cell types occurs because IL-1β is involved in the activation of several apoptosis-related factors, such as Bax and Bcl-2 (Meirovitz, et., 2010).
The process of intestinal apoptosis induced by chemotherapy was accompanied by increased regulation of pro-apoptotic factors (Bax, Caspase-3, Bak, and P53) and decreased regulation of anti-apoptotic factors (Bcl-2 and Bcl-XL) in Small intestinal crypt cells, which led to the genesis of intestinal mucositis in small cells. Therefore, IL-1β is possibly involved in apoptosis of small intestinal crypt cells after chemotherapy.
The interleukin-1 receptor antagonist (IL-1Ra) is a naturally occurring protein that has antagonistic biological effects of IL-1, which may antagonize the inhibitory role of IL-1 on endothelial cell proliferation and promote cell growth endothelial cells through receptor binding of interleukin-1 (IL-1R). Several studies also report the inhibitory role of IL-1Ra in cellular apoptosis in different experimental models (wu, et al., 2011; Yoshida, et al., 2006).
Studies suggest that the strong increase of IL-1β in the body after chemotherapy may be involved in the activation of the apoptosis process of small intestine cells (Vissink et al., 2003; Peterson, 1999; Fall-Dickson, et al., 2007; Logan, et al., 2007).
In this context, it is important to note that several studies (Vathsala, et al., 2012; Lüer, et al., 2011) have reported on the immunomodulatory action of curcumin. Among these, some authors reported their important anti-IL-1 action.
Stomatitis is defined as any inflammatory process affecting the oral cavity. Inflammatory lesions may have several etiologies: infectious, autoimmune, traumatic, neoplastic or drug reactions. They may be presented as isolated lesions, being a local manifestation of a systemic disorder or they can be originated from the local commitment, leading, eventually, to the general affection of the individual. Oral lesions are classified according to their macroscopic appearance as white lesions, vesico-bullous, aphthous and tongue lesions.
The macroscopic aspects of the lesions are related to their etiology, for example: white lesions are associated with candidiasis, leukoplakia, lichen planus, Fordyce granules, nicotinic stomatitis, hairy leukoplakia, secondary syphilis; vesico-bullous lesions are associated with herpes simplex, herpes zoster, pemphigus, pemphigoid, erythema multiforme, Stevens-Johnson syndrome; aphthous lesions are related to recurrent atopic stomatitis, Behget's disease, systemic lupus erythematosus, mucositis, chemical burns, orthodontic appliance trauma; tongue lesions are related to fissured tongue, benign migratory glossitis (geographic tongue), median rhomboid glossos, glossodinea.
Oral ulcers, also called aphthous ulcers, atopic stomatitis or simply canker sores, are very common lesions of the oral mucosa with an inflammatory background, affecting about 20% of the population. Canker sores are usually benign lesions that do not usually cause more problems than discomfort, however, some more serious diseases of the oral cavity may manifest with very similar ulcerated lesions. An example is cancer of the oral cavity, which in the early stages may look like a cold sore. Canker sores that take more time to heal are those that appear in places where there is constant contact with teeth or with food, suffering repeated trauma throughout the day. Some people have large canker sores, called major canker sores, larger than 1 cm and deep. These take up to six weeks to disappear and can leave a scar. There is also the herpetiform canker sore, formed by multiple small ulcers that come together and become a larger lesion. These canker sores may be accompanied by lymph nodes in the neck (tongues) and sometimes of low fever and malaise.
The aphthous lesions appear to be caused by an imbalance of the immune system. Some of the known triggers are: local trauma, such as accidental bites; psychological stress; few hours of sleep; Helicobacter pylori, the same bacteria that causes gastric ulcer; some toothpaste containing sodium lauryl sulfate; gastroesophageal reflux; foods like chocolate, coffee, soft drinks, tomatoes and pineapples; cigarette; hormonal changes during the menstrual cycle; deficiency of some vitamins and minerals such as vitamin B12, vitamin C, zinc, iron or folic acid; drugs such as anti-inflammatories, rapamycin, methotrexate, aspirin and atenolol. Usually, oral ulcers caused by systemic diseases are multiple and recurrent. They usually have some different characteristics of common canker sores and are accompanied by other symptoms. In cases of lupus, canker sores are often painless and accompanied by skin lesions and joint pain, as well as systemic symptoms such as low fever and tiredness. In Behcet's disease, also an autoimmune disease, aphthae are multiple, recurrent and accompanied by ulcers also in the genitals. Eye injuries are also common. In celiac disease and Crohn's disease, canker sores come in conjunction with intestinal symptoms such as diarrhea and blood in the stool. Neutropenia, which is the fall in the number of neutrophils in the blood, is also a cause of oral ulcers. It is usually seen in patients undergoing chemotherapy but may occur in any disease or drug that causes neutropenia.
Various infections can cause mouth ulcers like canker sores:
The HIV virus can cause oral ulcers in advanced stages (when there are already criteria for AIDS) and in the acute phase of virus infection. Infection with Coxsackie virus (herpangina), very common in children, can result in sore throat, fever, small oral ulcers and lesions on the palms and soles of the feet. Syphilis, both the primary and secondary phases, can result in oral ulcers. These ulcers are usually multiple and in the secondary phase they take a long time to heal. Herpes labialis presents as vesicles that can become small ulcers after they rupture. The appearance is not much like sore throat, but can be confused by lay people. Some cancers of the oral cavity may present as ulcerations, being initially confused with common canker sores.
In addition to lesions of the oral cavity associated with inflammatory processes, cutaneous lesions caused by several etiologies, such as diabetic foot, are common and treated with substances with anti-inflammatory/proliferative potential to promote tissue repair. Among the manifestations of practically all skin diseases, the occurrence of several types of lesions that alter the appearance of the skin stands out. The cutaneous lesions are very distinct, for example, maculas, papules, loss of tissue, vesicles, blisters, pustules, crusts, among others.
Curcumin and related substances (curcuminoids) are phenolic compounds of low molecular weight characterized by yellowish coloration and which originate from the rhizome of the Curcuma longa L. plant. In Asian medicine the curcuminoids of Curcuma longa L have been used for generations for the treatment of many diseases including inflammation, skin sores, liver and biliary disorders, cough as well as tumors. Curcuma longa is reported in the literature as safe for human use (Dadhaniya, et al., 2011).
In the present invention, the term "curcumin" is understood as the substance of molecular formula C21H20O6 of high purity or in admixture with other curcuminoids present in the roots of Curcuma longa L. in different proportions, as well as in other plant species.
Likewise, in the present invention, the term "Bidens pilosa" extracts is understood to mean all preparations derived from the different parts or whole, whether or not pre-processed, of the species Bidens pilosa. These extracts can be obtained from conventional extraction processes, such as maceration, percolation and others, as well as from non-conventional extraction processes, such as extraction by ultrasound, microwave, supercritical fluid, among others. The use of atomized dried extracts, lyophilized or concentrated extracts or fractions purified by various methods is also considered.
It is therefore another subject of this invention, the utilization of Curcuma longa in compositions, acting as an immunomodulatory agent in view of its anti-IL-1 action.
Bidens pilosa (Bd) is a Brazilian plant popularly used in the form of teas for the treatment of liver diseases. It has proven anti-inflammatory, antioxidant, antiallergic, antimicrobial, healing and fibroblast inducing action.
The state of the art demonstrates that clinical studies have proven that Bd can promote the recovery of mucosal lesions. In parallel, randomized controlled double-blind clinical studies of the preparation containing Bd demonstrated an antiallergic effect of the same without clinical toxic effects (Corren et al., 2008). Preclinical toxicological studies have demonstrated that Bd does not present genotoxicity (Costa et al., 2007).
It is therefore a further subject of the present invention to provide a composition made from preparations containing Bidens pilosa (Bd), free of toxic effects and promoting various actions, in preparations employed to promote the recovery of cutaneous and mucous membranes lesions.
The use of plant resources is a strategy of great relevance for the development of new drugs, since these materials may present unique biological activities due to the associated action of different substances, which sometimes act through different and complementary mechanisms of action. The use of these materials may, in certain cases, be considered safer in relation to drug therapy with synthetic drugs.
However, there are numerous technological challenges related to the development of pharmaceutical products that contain complex mixtures of natural substances.
In fact, standardization, ensuring the stability and effectiveness of these preparations is a complex task that requires innovative development.
Previous attempts were made using associations of natural substances, among which we can highlight curcumin, a phenolic antioxidant extracted from the rhizome of the Curcuma longa plant. Such prior efforts may be represented by document WO200388986, published on Oct. 10, 2003, which relates to a combination of curcumin with an antioxidant and at least one edible oil used for the prevention and treatment of tissue damage of patients undergoing radiation therapy. Basically, priority refers to the prevention and treatment of damage to the tissues of a patient undergoing radiotherapy in laryngeal, esophagus, oral cavity, nasopharyngeal cancer treatment, resulting in radiation-induced mucositis.
The reference proposes the use of curcumin oil, associated with an antioxidant, and an edible oil, preferably a vegetable oil, such as sunflower oil, and preferably, being chosen as the antioxidant vitamin "E" or α-tocopherol.
Thus, it can be observed that the priority does not anticipate or suggest the use of a preparation based on the association of Curcuma longa, in the form of extract or fraction or isolated substance, with extracts of Bidens pilosa.
Unexpectedly, it has been observed that the associated action of Bidens pilosa (Bd) and Curcuma Longa could be advantageously employed to produce a preparation used in the production of a safe, nontoxic drug with useful pharmacological properties, capable of promoting the recovery of Lesions of the mucosa and tissues with inflammatory processes.
In the present invention, a preparation in which Bidens pilosa (picão preto) was used as a glycerol extract, which was formulated together with the extract or fraction of Curcuma longa extract having curcuminoids content greater than 5%.
Curcumin, the main representative of curcuminoids, is a phytopharmaceutical extracted from the roots of Curcuma longa L., which presents numerous therapeutic activities, among them, the activities chemoprotective, antioxidant, antimicrobial and anti-inflammatory.
Curcumin is the most abundant curcuminoid in the roots of Curcuma longa. Phenyl, hydroxylic and methyl groups are related to the biological actions of this substance.
Some aspects of great relevance should be considered to ensure proper use of this compound. A relevant problem which lacked adequate solution in the state of the art in order to obtain a composition promoting the association of the planting agents of the present invention lies in the fact that curcumin has reduced aqueous solubility in pH-media Acid and degrades rapidly in media with alkaline pH.
Its solubility/stability behavior hampers the effective administration of this substance, particularly because of its low aqueous solubility, greatly hindering the development of a medicament to be administered orally, with easy absorption and assured stability.
Therefore, it is very important, and it is a major object of the present invention to provide a composition for the prevention and treatment of inflammatory diseases, for example mucositis, capable of employing curcumin in aqueous base preparations having therapeutically suitable concentrations and Considerable stability.
Similarly, it is important to ensure proper dissolution of such substance from solid dosage forms such that the bioavailability of the drug preparation in solid form is adequate.
The extractive preparations obtained from Bidens pilosa represent other material of natural origin of great importance and that has attracted attention of the scientific community. There are many traditional uses of these extracts, including the fight against malaria, hepatitis, laryngitis, headaches and gastric problems.
The extracts obtained from Bidens pilosa (Bd) have proven antibacterial, antioxidant and immunomodulatory action. Some of these activities are probably related to the presence of flavonoids in Bidens pilosa extracts.
Other classes of secondary metabolites are also present in the extracts, for example alkaloids, saponins, triterpenes and polyacetylenes. The biological activities of Bidens pilosa (Bd) are very promising and numerous patents have been deposited protecting its use as herbicide, anti-inflammatory, cosmetic and in the treatment of metabolic syndrome.
Because of the complex composition of plant extracts and the special solubility and stability characteristics of curcumin, the combination of such agents in stable and effective formulations requires innovative technological development which is one of the main aspects of the present invention.
In addition, the formulations used in the treatment of mucositis should have characteristics that aid in therapeutic success, such as high retention, penetration and stability in the environment, for example the oral, cutaneous or gastrointestinal environment.
The present invention has demonstrated the scope of a composition with novel features containing the association of Curcuma longa (its extracts or fractions) associated with the glycerinated extract of Bd which has an important proliferative and antiinflammatory effect, and correlated formulation with results superior to the effects of these substances when Evaluated separately in animals exposed to 5-fluoracil.
Mucositis is an inflammatory condition of the mucosa, which is atrophic, swollen, erythematous and sometimes ulcerated. This condition is almost, but not exclusively, invariably observed in cancer patients undergoing radiotherapy and chemotherapy.
Inflammatory lesions on the mucosa lead to a drastic reduction in patients' quality of life and may prevent the continuation of radiotherapy or chemotherapy. In addition, the colonization of inflammatory lesions ulcerated by opportunistic pathogens, particularly the oral cavity, can lead to sepsis and death.
Due to the recognition of its importance, academic and clinical efforts have been made to improve prevention and treatment of mucositis. Despite this, prophylactic and therapeutic strategies are still very limited.
Treatments based on reliable clinical evidence can still be considered as scarce. Some prior art procedures and related medicaments with adequate clinical evidence may be used as adjuvants in the mucositis tables caused by cytotoxic chemotherapy, such as, for example, in bone marrow pre-transplantation conditioning.
The use of palifermin (fibroblast growth factor KGFF1) has recently been approved for this. The clinical benefit of cryotherapy has also been demonstrated in these cases.
On the other hand, despite the aforementioned drugs that help reduce the suffering of patients with mucositis, on the other hand, specific drugs are still not available for the treatment and/or prevention of radiotherapy-related mucositis, with curative results Of this condition.
The preparations used in the clinic are currently not registered for this purpose and/or have no use based on reliable clinical evidence.
More particularly, reliable pharmaceutical preparations consisting of the combination of glycerinated extract of Bidens pilosa and Curcuma Longa, extracts thereof or fractions thereof, with adequate aqueous solubility and stability have not been developed and therefore do not appear in the state of the art. Present effectiveness in the treatment of mucositis in patients with cancer diagnosis, under radiotherapeutic and chemotherapeutic treatment.
Within this context, it is evident the need to develop new drugs that specifically act in the prevention and/or treatment of the various mucositis.
It is therefore an object of the present invention to provide pharmaceutical compositions containing the combination of Bidens pilosa extract and Curcuma longa extract (or fractions thereof) in proportions of 1:10 to 10:1, incorporated in semisolid pharmaceutical forms, Liquids or solids containing natural or synthetic bioadhesive components, diluents, carriers, binders, disintegrants, in the concentration ranges from 1 to 75% by weight, of the active agents of vegetable origin.
It is an object of the present invention to provide bioadhesive extended release systems which ensure the solubility and stability of the various incorporated active principles.
It is yet a further object of the present invention to provide a method of producing such pharmaceutical forms/delivery systems.
It is an object of the present invention to provide methods for the prevention and treatment of inflammatory, infectious, irritative, ulcerated or non-ulcerous conditions affecting the mucosa of the digestive tract, especially the buccal mucosa, as well as other mucous membranes of the human organism or Other mammals, such as the rectal, vaginal and nasal mucosa.

Soluble, stable, anti-inflammatory, proliferative, protective and mucoadhesive pharmaceutical compositions; use thereof for treating mucositis conditions and method for producing same; base pharmaceutical composition for preparing the pharmaceutical compositions and method for producing same


Machines, systems and methods for providing remote assistance, the method comprising establishing a communications session between a local user and a visitor over a communications network, wherein the local user is positioned in a local physical operating environment and the visitor is positioned in a remote location relative to the local physical operating environment; communicating audio or video data captured at the local physical operating environment to the visitor; and receiving, at the local physical operating environment, imaging data generated as a result of the visitor interacting with a visitor application running on a visitor computing device, wherein the imaging data is used to project, by way of a projector, a first image of one or more annotations created by the visitor onto a local physical work environment to assist the local user, wherein the projector is mounted on a mechanically articulated arm.

A human operator or user (e.g., a mechanic) working on an object (e.g., a jet engine) might need assistance in performing a task when he encounters a specific problem that he is not familiar with. A user may have the option of seeking remote assistance by making a voice call to an advisor that would guide him through the task. However, often it is difficult for the advisor to provide meaningful assistance without the advisor having a real-time view of the user's environment or the ability to directly point to details present in the user's environment. In order for the remote advisor to provide effective assistance, it is desirable that the remote advisor be able to see the user's working area and provide constructive instruction, including pointing to particular areas in the user's environment.

Real-time advisor system with projected augmentable annotations


A method for making a MOSFET includes forming a gate oxide layer on a substrate; depositing and forming a polysilicon layer on the gate oxide layer; removing the polysilicon layer and the gate oxide layer in a target area by means of dry etching. The remaining gate oxide layer forms a gate oxide of the MOSFET. The remaining polysilicon layer forms a gate of the MOSFET. The method further includes performing LDD implantation on the substrate at both sides of the gate, to form a first LDD area and a second LDD area respectively; and performing SD implantation to form a source and a drain in the substrate at both sides of the gate respectively. Before one of the steps after the depositing and forming a polysilicon layer on the gate oxide layer, fluorine ion implantation is performed.

The MOSFET (hereinafter referred to as "MOS") is an electronic device widely used in analog circuits and digital circuits. Based on different carrier polarities, the MOS can be classified into "P-type" MOS and "N-type" MOS, which can be respectively referred to as PMOS and NMOS for short.
The negative bias temperature instability (NBTI) effect refers to the degradation of a series of electrical parameters caused by the application of a negative bias to the PMOS at high temperature, which results in the PMOS being prone to failure and having low reliability. Referring to FIG. 1, which shows a schematic diagram of the NBTI effect of the PMOS, it can be seen from FIG. 1 that a silicon-hydrogen (H) bond is formed at the gate oxide (GOX, which contains silicon dioxide SiO2)-substrate (which contains silicon Si) interface of the PMOS. When the PMOS is at a negative bias, under the action of a vertical electric field, holes are attracted to the interface to weaken the Si—H bond, in which case the hydrogen escapes from the silicon-hydrogen bond and diffuses into the silicon in the substrate, forming an interface trap (Dit), and thereby causing the NBTI effect.
Referring to FIG. 2, which shows a schematic diagram of the hot carrier injection (HCI) effect, it can be seen from FIG. 2 that a silicon-hydrogen bond is formed at the gate oxide-substrate interface of the NMOS. When the NMOS is in the operating state, under the action of an electric field, electrons can penetrate the interface to break the silicon-hydrogen bond, forming an interface trap, and thereby leading to the degradation of some electrical parameters of the device.
The MOS provided in the related art is liable to cause the NBTI effect or the HCI effect due to the silicon-hydrogen bond at the gate oxide-substrate interface, resulting in a reduction in the reliability of the device.


A tubular or spherical nanostructure composed of a plurality of peptides, wherein each of the plurality of peptides includes no more than 4 amino acids and whereas at least one of the 4 amino acids is an aromatic amino acid.

The present invention relates to peptide nanostructures and methods of generating and using same.
Nanoscience is the science of small particles of materials and is one of the most important research frontiers in modern technology. These small particles are of interest from a fundamental point of view since they enable construction of materials and structures of well-defined properties. With the ability to precisely control material properties come new opportunities for technological and commercial development, and applications of nanoparticles have been shown or proposed in areas as diverse as micro- and nanoelectronics, nanofluidics, coatings and paints and biotechnology.
Numerous configurations have been proposed and applied for the construction of nanostructures. Most widely used are the fullerene carbon nanotubes. Two major forms of carbon nanotubes exist, single-walled nanotubes (SWNT), which can be considered as long wrapped graphene sheets and multi walled nanotubes (MWNT) which can be considered as a collection of concentric SWNTs with different diameters.
SWNTs have a typical length to diameter ratio of about 1000 and as such are typically considered nearly one-dimensional. These nanotubes consist of two separate regions with different physical and chemical properties. A first such region is the side wall of the tube and a second region is the end cap of the tube. The end cap structure is similar to a derived from smaller fullerene, such as C60.
Carbon nanotubes produced to date suffer from major structural limitations. Structural deviations including Y branches, T branches or SWNT junctions, are frequent results of currently used synthesis processes. Though such deviations in structure can be introduced in a "controlled" manner under specific conditions, frequent uncontrollable insertion of such defects result in spatial structures with unpredictable electronic, molecular and structural properties.
Other well-studied nanostructures are lipid surfactant nanomaterials (e.g., diacetylene lipids) which self-assemble into well-ordered nanotubes and other bilayer assemblies in water and aqueous solution [Yager (1984) Mol. Cryst. Liq. Cryst. 106:371-381; Schnur (1993) Science 262:1669-1676; Selinger (2001) J. Phys. Chem. B 105:7157-7169]. One proposed application of lipid tubules is as vehicles for controlled drug release. Accordingly, such tubes coated with metallic copper and loaded with antibiotics were used to prevent marine fouling.
Although lipid-based nanotubules are simple in form, lipid structures are mechanically weak and difficult to modify and functionalize, thus restricting their range of applications.
Recently, peptide building blocks have been shown to form nanotubes. Peptide-based nanotubular structures have been made through stacking of cyclic D-, L-peptide subunits. These peptides self-assemble through hydrogen-bonding interactions into nanotubules, which in-turn self-assemble into ordered parallel arrays of nanotubes. The number of amino acids in the ring determines the inside diameter of the nanotubes obtained. Such nanotubes have been shown to form transmembrane channels capable of transporting ions and small molecules [Ghadiri, M. R. et al., Nature 366, 324-327 (1993); Ghadiri, M. R. et al., Nature 369, 301-304 (1994); Bong, D. T. et al., Angew. Chem. Int. Ed. 40, 988-1011 (2001)].
More recently, the discovery of surfactant-like peptides that undergo spontaneous assembly to form nanotubes with a helical twist has been made. The monomers of these surfactant peptides, like lipids, have distinctive polar and nonpolar portions. They are composed of 7-8 residues, approximately 2 nm in length when fully extended, and dimensionally similar to phospholipids found in cell membranes. Although the sequences of these peptides are diverse, they share a common chemical property, i.e., a hydrophobic tail and a hydrophilic head. These peptide nanotubes, like carbon and lipid nanotubes, also have a very high surface area to weight ratio. Molecular modeling of the peptide nanotubes suggests a possible structural organization [Vauthey (2002) Proc. Natl. Acad. Sci. USA 99:5355; Zhang (2002) Curr. Opin. Chem. Biol. 6:865]. Based on observation and calculation, it is proposed that the cylindrical subunits are formed from surfactant peptides that self-assemble into bilayers, where hydrophilic head groups remain exposed to the aqueous medium. Finally, the tubular arrays undergo self-assembly through non-covalent interactions that are widely found in surfactant and micelle structures and formation processes.
Peptide based bis(N-α-amido-glycyglycine)-1,7-heptane dicarboxylate molecules were also shown to be assembled into tubular structures [Matsui (2000) J. Phys. Chem. B 104:3383].
When the crystal structure of di-phenylalanine peptides was determined, it was noted that hollow nanometric channels are formed within the framework of the macroscopic crystal [Gorbitz (2001) Chemistry 7(23):5153-9]. However, no individual nanotubes could be formed by crystallization, as the crystallization conditions used in this study included evaporation of an aqueous solution at 80° C. No formation of discrete nano-structures was reported under these conditions.
As mentioned hereinabove, peptide nanotubes contributed to a significant progress in the field of nanotechnology since such building blocks can be easily modified and used in numerous mechanical, electrical, chemical, optical and biotechnological systems.
The development of systems which include nanoscale components has been slowed by the unavailability of devices for sensing, measuring and analyzing with nanometer resolution. One class of devices that have found some use in nanotechnology applications are proximity probes of various types including those used in scanning tunneling microscopes, atomic force microscopes and magnetic force microscopes. While good progress has been made in controlling the position of the macroscopic probe to sub-angstrom accuracy and in designing sensitive detection schemes, the tip designs to date have a number of problems.
One such problem arises from changes in the properties of the tip as atoms move about on the tip, or as the tip acquires an atom or molecule from the object being imaged. Another difficulty with existing probe microscope tips is that they typically are pyramidal in shape, and that they are not able to penetrate small openings on the object being imaged. Moreover, existing probe microscopes often give false image information around sharp vertical discontinuities (e.g., steps) in the object being imaged, because the active portion of the tip may shift from the bottom atom to an atom on the tip's side.
An additional area in which nanoscience can play a role is related to heat transfer. Despite considerable previous research and development focusing on industrial heat transfer requirements, major improvements in cooling capabilities have been held back because of a fundamental limit in the heat transfer properties of conventional fluids. It is well known that materials in solid form have orders-of-magnitude larger thermal conductivities than those of fluids. Therefore, fluids containing suspended solid particles are expected to display significantly enhanced thermal conductivities relative to conventional heat transfer fluids.
Low thermal conductivity is a primary limitation in the development of energy-efficient heat transfer fluids required in many industrial applications. To overcome this limitation, a new class of heat transfer fluids called nanofluids has been developed by suspending nanocrystalline particles in liquids such as water, oil, or ethylene glycol. The resulting nanofluids possess extremely high thermal conductivities compared to the liquids without dispersed nanocrystalline particles. Excellent suspension properties are also observed, with no significant settling of nanocrystalline oxide particles occurring in stationary fluids over time periods longer than several days. Direct evaporation of copper nanoparticles into pump oil results in similar improvements in thermal conductivity compared to oxide-in-water systems, but importantly, requires far smaller concentrations of dispersed nanocrystalline powder.
Numerous theoretical and experimental studies of the effective thermal conductivity of dispersions containing particles have been conducted since Maxwell's theoretical work was published more than 100 years ago. However, all previous studies of the thermal conductivity of suspensions have been confined to those containing millimeter- or micron-sized particles. Maxwell's model shows that the effective thermal conductivity of suspensions containing spherical particles increases with the volume fraction of the solid particles. It is also known that the thermal conductivity of suspensions increases with the ratio of the surface area to volume of the particle. Since the surface area to volume ratio is 1000 times larger for particles with a 10 nm diameter than for particles with a 10 mm diameter, a much more dramatic improvement in effective thermal conductivity is expected as a result of decreasing the particle size in a solution than can obtained by altering the particle shapes of large particles.
It is recognized that peptide nanotubes are natural candidates for performing the above and many other tasks in the field of nanotechnology.
However, currently available peptide nanotubes are composed of peptide building blocks, which are relatively long and as such are expensive and difficult to produce, or limited by heterogeneity of structures that are formed as bundles or networks rather than discrete nanoscale structures.
There is thus a widely recognized need for, and it would be highly advantageous to have, a peptide nanostructure, which is devoid of the above limitations.

This patent is subject to a terminal disclaimer.

Peptide nanostructures and methods of generating and using the same