A passive MMIC monopulse comparator includes a plurality of lumped element hybrids having pi and T filter structures. In one embodiment, a first hybrid receives first and second downcoverted signals and provides a first output signal to a third hybrid and second output signal to a fourth hybrid. A second hybrid receives third and fourth downconverted signals and provides respective third and fourth output signals to the third and fourth hybrids. The third hybrid provides sum and elevation channel signals and the fourth hybrid provides azimuth and G channel signals.

Not applicable.
This invention relates generally to receiver circuits and more particularly to radio frequency (RF) receiver circuits.
As is known in the art, a radar system generally includes an antenna, a transmitter and a receiver. In general overview, the transmitter generates an electromagnetic signal which is emitted or radiated through the antenna. The radiated electromagnetic signal propagates in a predetermined region of space and intercepts one or more objects in the path of the electromagnetic radiation. Portions of the electromagnetic radiation reflect off the objects and propagate back towards the radar system where the reflected signals are detected by the receiver. Such reflected signals are sometimes referred to as return or echo signals.
If the radar system employs a directive antenna, a relatively narrow beam of electromagnetic radiation is emitted and the direction from which the return signals propagate and hence the bearing of the object may be estimated. The distance or range to the reflecting object can be estimated by transmitting signal pulses and measuring the time period between the transmission of the transmitted pulse and reception of the return signal pulse.
One particular type of radar system is a monopulse radar system. A monopulse radar system refers to a radar system which obtains a complete measurement of an object""s angular position by transmitting a single signal pulse and receiving the corresponding return or echo pulse. Together with a range measurement performed with the same pulse, the object position in three dimensions is determined completely. Typically, a series or train of echo pulses is employed to make a large number of repeated measurements and produce a refined estimate of the object""s position.
A monopulse receiving system typically includes a monopulse circuit which receives signals from the antenna and forms sum and difference monopulse output signals. The sum and difference signals are formed by combining received antenna signals in a particular manner. The signals can be combined using circuits referred to as hybrid circuits. The hybrid circuits may be provided as so-called magic-T or rat race circuits which receive signals fed thereto and add and/or subtract the signals in a known manner. Such hybrid circuits can be fabricated using either printed circuit or waveguide transmission lines.
To determine the location of an object in a single angular coordinate (e.g. either azimuth or elevation), the monopulse circuit need only include a single hybrid circuit and thus the monopulse circuit is relatively compact. To determine the location of an object in two angular coordinates (e.g. both azimuth and elevation), the monopulse circuit requires multiple hybrid circuits. Thus, conventional monopulse circuits capable of determining the location of an object in two angular coordinates can become relatively large.
The monopulse sum and difference signals can be formed either at the transmitted signal frequency or, after down conversion of a return signal, at a lower frequency. The transmit signal frequency is typically in the microwave or millimeter wave frequency range. When the monopulse sum and difference signals are formed at the transmitted signal frequency, the monopulse is typically coupled directly to the antenna with relatively few, if any, circuits disposed between the antenna output ports and the monopulse input ports. The operations to generate monopulse sum and difference signals typically are performed at microwave or millimeter wave frequencies by the hybrid circuits which are typically fabricated using either printed circuit or waveguide transmission lines.
Obtaining the sum and difference signals at the transmitted signal frequency (i.e., before any down conversion) reduces the amount of additional errors which may be otherwise introduced into the signals used to form the monopulse signals by circuits (e.g. mixer circuits) coupled between the antenna output ports and the monopulse input ports. For example, to form the monopulse signals after down conversion of a return signal to a lower frequency it is necessary to couple a mixer or other frequency translation device between the antenna output ports and the monopulse input ports. Practical frequency translation devices (e.g. mixer circuits) introduce errors into the signals which are combined in the monopulse circuit to provide the monopulse output signals.
Typically, a single sum channel and a pair of difference channels are formed by the monopulse circuit to allow resolution of two angular coordinates. In systems which utilize a conventional waveguide multimode horn feed, a waveguide monopulse network can process a radar return signal to generate monopulse sum and difference signals which propagate in appropriate monopulse sum and difference channels. The radio frequency (RF) signals propagating through the monopulse channels are converted to intermediate frequency (IF) signals using waveguide mixers. The IF signals are fed to an IF receiver for additional processing.
One problem with this RF waveguide approach to implementing the monopulse network is that the monopulse circuit is relatively large and must be fabricated using relatively expensive and time consuming precision machining or electroforming techniques. This is particularly true in those system which operate in the millimeterwave frequency range. To overcome this drawback, systems operating at millimeter wavelength,frequencies can downconvert received signals to an intermediate frequency prior to monopulse processing. With this approach, monopulse processing may be performed at the intermediate frequency in lieu of monopulse processing performed at the higher fundamental or transmit frequency. While the circuit fabrication tolerances are generally less severe at lower frequencies, there is a concomitant increase in the size of waveguide circuit components. Thus, the use of waveguide transmission lines to process and convert the monopulse information (especially at millimeter wave frequencies) is not a practical low cost solution suitable for high volume production.
To further complicate matters, projectiles such as missiles and submunitions having a relatively small diameter require relatively high resolution monopulse receivers to enable accurate tracking of a target. Conventional monopulse receiving systems operating in the 1 gigahertz (GHz) to 20 GHz frequency range do not provide the angular resolution needed to accurately track targets. Furthermore, the size of RF circuit components which operate in the 1 GHz to 20 GHz range are physically too large and cumbersome to be packaged in many small projectiles. Therefore, operation at millimeter wave frequencies above 30 GHz is required.
Missile seeker systems having a relatively large diameter typically operate at microwave frequencies and form monopulse output receive signals with comparator networks provided from hybrid circuit components implemented using stripline, coaxial or waveguide transmission media. The monopulse output signals are typically fed to amplifiers having a relatively high gain and a relatively low noise figure. The amplified signals are subsequently downconverted to an appropriate intermediate frequency (IF) by a radio frequency (RF) microwave mixer module. For those applications in which the monopulse receiver must be disposed in a projectile having a relatively small diameter, however, the signal transmission losses and overall size of conventional receiver systems adversely impact seeker performance. Operation at higher frequencies such as millimeter wave (MMW) frequencies is a necessity to achieve the requisite resolution but there are limitations in the availability of receiver devices which operate at such frequency bands. For example, it is relatively difficult and expensive to provide RF devices having the performance characteristics (e.g., noise figure, power handling, power limiting, etc.) required for efficient active seeker operation in the MMW frequency range.
The complexity of radar systems operating in the millimeter wave frequency band will be appreciated when it is recognized that at an operating frequency of 94 GHz, for example, dimensions of a conventional rectangular waveguide are in the order of 0.050 to 0.100 inches, with tolerances of better than 0.001 inches required in many critical assemblies. Although it may be possible to fabricate such millimeter-wave waveguide structures at somewhat reduced cost using modem fabrication techniques, the expense associated with tuning and testing such critically toleranced hardware is often cost prohibitive.
Furthermore, the problems of packaging and tuning a millimeter-wave seeker in a conventional submunition will be appreciated when it is recognized that a monopulse seeker with a monopulse tracking capability utilizing waveguide components may well require in excess of twenty different waveguide components to control the routing and duplexing of the various signals coming from the transmitter and returning to the receivers. If a monopulse capability were required, then all of the foregoing waveguide components would be required to track from channel to channel in both amplitude and phase.
At an operating frequency of 94 GHz, each one thousandth of an inch in the length of a waveguide transmission line is equivalent to about 2xc2x0 of phase. It should, therefore, be appreciated that it is relatively difficult to obtain inexpensively the requisite phase and amplitude tracking between various receiver channels.
Another problem inherent in millimeter-wave radar seekers utilizing waveguide devices is that of providing sufficient isolation between a transmitter and receiver. This problem is exacerbated by the fact that waveguide switches and circulators which can withstand relatively high power transmit signals and provide a high degree of isolation are not generally available in a compatible size at relatively high operating frequencies.
It would, therefore, be desirable to provide a relatively compact monopulse receiver having a relatively low noise figure which operates in the millimeter wave frequency range and which can operate in a system which includes a transmitter which transmits signals having relatively high power levels.
In accordance with the present invention, a radio frequency (RF) system includes an antenna having a plurality of antenna ports and a plurality of protection circuits each of the protection circuits having a first port coupled directly to a respective one of the plurality of antenna ports and a second port. In response to a first control signal, each protection circuit allows signals to propagate from a respective one of the antenna ports to the second port of the respective protection circuit along a signal path having a relatively low insertion loss characteristic. Each protection circuit is also responsive to a second control signal in a first direction between the first protection circuit port and the second protection circuit port and responsive to a second control signal which isolates the first protection circuit port from the second protection circuit port. With this particular arrangement, a compact RF system is provided. By coupling the antenna ports directly to the ports of the protection circuit, the RF system can operate in a receive mode and be protected from transmit signal having high signal levels generated by a transmitter circuit during a transmit operating mode. To operate in a receive mode, the protection circuit is biased to provide a signal path having a relatively low insertion loss characteristic to signals propagating from the antenna ports through the protection circuit ports. During the transmit mode, the protection circuit is biased to provide a signal path having high insertion loss characteristic from signals propagating from the antenna ports. In one particular embodiment, the RF system further includes a plurality of mixers, each having a first port coupled to a respective one of the plurality of protection circuit ports and a second port for receiving a mixer bias signal and a third port for providing a frequency shifted signal. By coupling the mixers to the protection circuit ports, a compact receiver assembly is provided. An amplifier can be coupled to the third port of each mixer to thus provide a system having a relatively high gain characteristic while also providing a system which provides a relatively low noise figure. Also a monopulse can be coupled to the output ports of the amplifiers to provide an RF monopulse receiving system. In a preferred embodiment, the mixers, amplifiers and monopulse circuit are provided as monolithic microwave integrated circuits (MMICs) and thus the RF system utilizes a relatively small physical area. Furthermore the antenna can be provided as a corrugated horn having a moding structure disposed in a base portion thereof to couple signals between the antenna input and the antenna ports in the base structure of the corrugated horn which are coupled to the first port of each of the protection circuits. The receiving system may also include a calibration signal injection circuit coupled to the protection circuit to inject a calibration signal into the receiving system. In one particular embodiment, the protection circuit is a latching ferrite isolator matrix which includes a plurality of isolators each having first, second and third ports with the calibration signal injection circuit coupled to the third port of each of the plurality of isolators.
In accordance with a further aspect of the present invention, a radio frequency (RF) monopulse receiver includes a plurality of mixers, each having an RF signal port, a local oscillator (LO) signal port and an intermediate frequency (IF) signal port and each of the mixers comprising one or more mixer diode anti-parallel pairs and means for coupling RF energy to the RF signal port of each of the plurality of mixers. The RF monopulse receiver further includes a plurality of IF amplifiers, each of the IF amplifiers having an amplifier input port coupled to the IF signal port of a respective one of the plurality of mixers and an amplifier output port coupled to a respective one of a plurality of input ports of a monopulse comparator network. In response to appropriate input signals fed thereto, the monopulse comparator network provides monopulse output signals at output ports thereof. With this particular technique, a compact millimeter wave monopulse receiver having a relatively low noise figure is provided. By arranging a latching ferrite isolator matrix protection circuit between an antenna and the mixer ports, the RF monopulse receiver is protected from high power transmit signals. Furthermore the latching ferrite isolator matrix allows use of a receiver circuit architecture which allows the compact millimeter wave monopulse receiver circuit to operate in an RF radar system having a relatively high transmit power. In one embodiment, the RF monopulse receiver is suitable for use in an active missile seeker system for example. The RF receiver can be used directly in a small submunition or alternatively, can function as the monopulse receiver for a higher resolution quasi-optically fed, antenna having an aperture much larger than the diameter of the horn antenna. In one embodiment, a cryogenic cooling system is coupled to the receiver to provide a receiver noise figure which is lower than the noise figure achieved when the receiver operates at ambient temperatures.
In accordance with a still further aspect of the present invention, an RF monopulse receiver includes a circuit assembly having a plurality of RF input ports and a plurality of IF output ports. The circuit assembly includes (a) a housing, (b) a plurality of subharmonically pumped mixer circuits disposed in the housing, each of the mixer circuits having an RF signal port, an LO signal port and an IF signal port and each of the mixer circuits including: (1) a plurality of mixer diode substrates disposed in the housing, each of the mixer diode substrates having a diode mounting region and a transmission coupling region which projects into an RF feed region which is formed by providing an opening in a housing cover disposed over the diode mounting region of the plurality of substrates; (2) an antiparallel diode pair disposed on the diode mounting region of each of the plurality of mixer diode substrates; (3) an LO distribution circuit coupled between the LO signal port of each subharmonically pumped mixer circuit and an LO signal source; (4) an IF distribution circuit coupled between the IF signal port of each subharmonically pumped mixer circuit and an IF output port of the RF monopulse receiver; (c) an RF feed circuit, coupled to the housing, (d) means for coupling RF energy to the RF signal port of each of the plurality of subharmonically pumped mixer circuits; (e) a monopulse substrate; and (f) a monolithic microwave integrated circuit (MMIC) monopulse comparator network disposed on the monopulse substrate, the MMIC monopulse comparator network having a plurality of monopulse circuit input ports, each of the plurality of monopulse circuit input ports coupled to a respective one of the IF ports of the plurality of subharmonically pumped mixer circuits and having a plurality of monopulse circuit output ports coupled to the IF output ports of the monopulse substrate. With this particular arrangement, an RF monopulse receiver suitable for use in the W-band frequency range is provided. The system can further include a corrugated horn antenna having a moding structure in a base portion thereof to provide four separate antenna ports. The antenna base ports are coupled to the RF ports of the mixer circuits providing signals between the antenna ports in the base structure of the corrugated horn and the RF port of the mixer circuits. A protection circuit can be included in a waveguide signal path disposed between the antenna ports and the RF input port of the mixer circuits. In one particular embodiment, the protection circuit is provided as a latching ferrite isolator matrix which includes a plurality of isolators each having first, second and third ports. The RF monopulse receiver can also include a calibration signal injection circuit coupled to the protection circuit to inject a calibration signal into the receiver. When the protection circuit is provided as the latching ferrite isolator matrix, a calibration signal injection circuit can be coupled to the third port of each of the plurality of isolators. In response to a first control signal, the latching ferrite isolators allow signals to propagate in a first direction between a first pair of isolator ports and in response to a second control signal, the latching ferrite isolators allow signals to propagate in a second direction between a second pair of isolator ports. With such an arrangement, the RF monopulse receiver can operate without being damaged in those RF systems which include a transmitter. Furthermore, the housing may be provided as a single housing having both RF and IF circuit components disposed therein including the MMIC monopulse comparator network. Alternatively, the housing can be provided from an RF housing and an IF housing which are physically and electrically coupled together. The RF signal components including the RF mixer and an amplifier are disposed in the RF housing and the MMIC monopulse comparator network and an amplitude adjustment circuit and phase shifter are disposed in the IF housing with a plurality of RF interconnect signal paths providing RF signal paths between the RF housing and the IF housing. The use of MMIC LNA""s and a novel MMIC monopulse along with the development of a low conversion loss, low noise figure, W-Band mixer leads to a relatively small and efficient W-Band monopulse receiver which is compatible with small diameter missiles and submunitions and provides enhanced sensitivity to thus allow the seeker to accurately track targets. This enhanced sensitivity is achieved with the inclusion of cooling hardware which is used to locally cool the mixer diodes.

Radio frequency receiving circuit having a passive monopulse comparator


In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.

Microelectronic circuits for data and/or signal processing contain memories with memory cells which make it possible to store data, state variables etc. The requirements for these memories have become more stringent as processing speed increases. In particular, it has been necessary to shorten considerably both the access time to the contents of the memory (read process) and the time period for writing to the memory (write process). An important example of such memories is the SRAM (Static Random Access Memory) which can be implemented with a small area requirement and allows very rapid access to its content.
An increasing number of portable systems have come on the market recently, such as mobile telephones, palm-top computers and medical equipment (e.g. hearing aids) for example. The voltage supply for these systems is provided by batteries or rechargeable batteries. The operating time and standby time of portable equipment in this case depends on the one hand on the battery capacity and on the other hand on the power consumption of the system components. In the case of microelectronic circuits, concepts for reducing the power consumption have already been developed, in order to increase the standby time in this way. See A. P. Chandrakasan, S. Sheng, R. W. Brodersen: "Low-Power CMOS Digital Design", IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, April 1992, pp. 473-484.
The power consumption of microelectronic circuits can essentially be described by the following relationship: ##EQU1## where .sigma..sub.i is the switching frequency of the i-th node, C.sub.i is its capacitance, VDD represents the supply voltage, HUB the level change at a node (HUB=VDD in general in static CMOS logic), and i is a sequential number for all the nodes in the relevant circuit.
The following techniques for power reduction can be derived from Equation (1): lowering the supply voltage, reducing node capacitances and reducing switching frequencies.
In the case of a SRAM memory, circuits have been implemented whose power consumption has already been considerably reduced by means of the techniques mentioned above: lowering the supply voltage from 5 volts to 3.3 volts (in some cases 2.4 V), precharging the bit lines to VDD/2 instead of VDD (level reduction), minimizing the capacitance by means of a compact layout (that is to say small number of transistors and small wiring capacitances), and by dividing the memory into blocks which can thus be driven individually (that is to say reduced switching frequency).
A 6-transistor memory cell is known from D. Rhein, H. Freitag: "Mikroelektronische Speicher", Springer Press 1992, pp 50-51, 56-57, and is also illustrated in FIG. 2. The memory cell SZ comprises two inverters MN5, MP3 and MN6, MP4 with feedback. The output node A of the inverter MN5, MP3 is connected to a first bit line BL via a first selection transistor MN1 which is driven via a word line WL. The output node B of the inverter MN6, MP4 is connected to a second bit line BLQ via a second selection transistor MN2 which is likewise driven by the word line WL. The corresponding transistors in the two inverters have the same dimensions, that is to say MP3=MP4 and MN5=MN6.
An important feature of a SRAM, designed with the described 6-transistor memory cell (FIG. 2) and differentially operating read amplifiers (see Rhein, supra), is the fact that the bit lines are driven in pairs. During writing, mutually complementary levels (for example BL=1 and BLQ=0) are applied to BL and BLQ corresponding to the datum and only then can the inverter pair (comprising MN5, MN6, MP3 and MP4) with feedback be switched over (A from 0 to 1; B from 1 to 0) via the selection transistors MN1 and MN2, which are switched on by WL. At the start of a reading process, both nodes BL and BLQ are at the same potential in order that they can then be drawn to mutually complementary levels by a driven memory cell (MN1 and MN2 are switched on by WL). A differentially operating read amplifier then allows rapid assessment of the difference between BL and BLQ, and thus reliable reading.
The capacitances of the bit lines BL and BLQ are governed both by the capacitive load of a cell and by the architecture of the memory, and in general they are among the largest capacitances in a SRAM. Since one of the large bit line capacitances must be reversed (.sigma.BL=0.5, .sigma.BLQ=0.5, see Formula (1)) in each case both during the reading process and during the writing process depending on the driven memory cell, a large proportion of the power consumption of a SRAM is caused at this point.
Any reduction in the switching frequency of bit lines can accordingly lead to a considerable reduction in the SRAM power consumption.
A 6-transistor memory cell is known from IBM Technical Disclosure Bulletin Vol. 31, No. 1 June 1988, page 291, and is also illustrated in FIG. 1. The memory cell SZ comprises a memory element SPE composed of two inverters MN5, MP3 and MN6, MP4 of different dimensions and with feedback. The output node A of the weaker inverter MN5, MP3 is connected to a first bit line BL via a first selection transistor MN1 which is driven via a word line WL. The output node B of the stronger inverter MN6, MP4 is connected to a second bit line BLQ via a second selection transistor MN2 which is driven by a second word line WLS.
In the case of the known circuit, the word line WL is used for writing a bit, and the second word line WLS is used for reading a bit from the memory element SPE using a single-pole read amplifier. VDD and VSS are supply voltages. When reading from this SRAM cell, only the bit line BL experiences a level change, and only the bit line BLQ during writing. It has thus been possible to reduce considerably the switching frequency of the bit lines.
If the supply voltage VDD is lowered to EQU .vertline.Vthmax.vertline.<VDD<.vertline.Vthp.vertline.+.vertline.Vthn.vert line. (2)
(Vthp, Vthn: threshold voltage of the N(P)-channel transistors, Vthmax being the greater value of Vthp and Vthn) in order to reduce the power consumption, the operation of the memory cell according to IBM, supra, (FIG. 1) is not ensured. When writing a 1 (BL=VDD), the charge on the node A is changed only to V=VDD-Vthn, since a voltage drop .DELTA.V of .DELTA.V=Vthn occurs across the selection transistor MN1. The inverter comprising MP4 and MN6 cannot switch over with this voltage level at the node A, and storage therefore does not take place. It is not possible to use the memory cell according to IBM, supra, (FIG. 1) in the voltage range according to Rhein, supra.

Method for operating a SRAM MOS transistor memory cell


A method of treatment of liquid in a liquid treatment system comprising: at least one liquid treatment module including at least one membrane and having a feed liquid inlet at a feed side of said at least one membrane, a permeate outlet at a permeate side of said at least one membrane, and a concentrate outlet at a brine side of said at least one membrane; a high pressure pump operative for pressurizing feed liquid to be received at said feed liquid inlet; and a system controller for controlling operation of the system including providing instructions to operate said high pressure pump in one of at least two operation modes including: a first mode in which the high pressure pump maintains a fixed flow rate of the feed liquid at said feed liquid inlet or of a permeate liquid at said permeate outlet, while energy consumption of said high pressure pump being a function of variations of a first operational parameter measured in the system and indicative of salinity of liquid within said at least one liquid treatment module, and a second mode in which the high pressure pump maintains a flow rate of the feed liquid at said feed liquid inlet or of a permeate liquid at said permeate outlet, while energy consumption of said high pressure pump being a function of a second operational parameter determined so as to reduce energy consumption of the high pressure pump; said method being performed under control of said system controller and comprising steps of: pressurizing feed liquid by said high pressure pump in said first mode; circulating a concentrate from said concentrate outlet to said feed liquid inlet; providing to said system controller a third operational parameter measured in the system and indicative of salinity of liquid within said liquid treatment module; and upon detecting that a predetermined first threshold of said third operational parameter is reached, operating said high pressure pump in said second mode.

Desalination processes and/or treatment processes are well known in the art, and are configured for receiving feed liquid and, following proper treatment, to produce a first stream of 'product' liquid (e.g., fresh water) also known as permeate, and a second stream of brine (e.g., highly saline water).
Different systems and methods were devised in order to increase the efficiency of such treatment processes, including more sophisticated membranes and liquid recirculation arrangements. Some examples of prior publications are U.S. Pat. Nos. 7,628,921, 7,695,614, US 2008/217222 and U.S. Pat. No. 8,025,804.

This patent is subject to a terminal disclaimer.


An assembly structure for eyeglass lens is disclosed herein to include a one-piece lens and a frame. The frame has a connection portion in the middle thereof, from two sides of which two nose pads extend downwardly and obliquely in two opposite directions. The connection portion has a joining hole, and the lens further has a flexible snap-in element in the middle thereof for corresponding engagement with the join hole. In such a case, the lens can be easily and conveniently detachable from the frame by merely pressing the flexible snap-in element.

1. Fields of the Invention
The present invention relates to an assembly structure for eyeglass lens, especially to an one-piece structure of the eyeglass lens fitted into an eyeglass frame by flexibly engaging components for functions of easy assembling or disassembling thereof.
2. Descriptions of Related Art
At present, conventional eyeglasses are designed to enhance comfort for users in wearing thereof and to replace with any parts or components thereof in a convenient fashion. Therefore, manufacturers for eyeglasses have been dedicating to improve structures of eyeglasses used for various purposes by all means, and expect that users may feel much more comfortable in wearing eyeglasses and various practical functions to be included in eyeglasses.
Also, a pair of conventional eyeglasses commonly available in the market has only one semi-rimed frame at the upper thereof. The semi-rimed frame is combined with lenses by engagement of the upper edge on both sides of the lenses to the semi-rimed frame, but such a combination will easily result in detachment of the lens from the semi-rimed frame and further damages to the lens as dropping to the ground. Due to the above disadvantages, quite a few pairs of eyeglasses are developed to have a strengthened structure of the lens for stably fitting to eyeglasses frames, as further briefly specified below.
As referring to a Taiwan patent registration with an issue number M417563, issued on 1 Dec. 2011, an assembly for positioning eyeglasses lens is disclosed therein to comprise a single strip shaped frame, two temples separately slipped over two external sides of the frame in part and a one-piece lens. The frame further has a first engaging component in the middle thereof and two second engaging components separately formed at a predetermined position far from the first engaging component on each of the two external sides thereof. Each of the second engaging components is provided with a protruded portion on an outermost end thereof having a larger diameter than that of a portion connected to the frame, and the first engaging component is further provided with a holding portion in a radial configuration. The one-piece lens further has a first gap at the middle upper edge thereof for receipt of the first engaging component and two second gaps each at lateral upper edge thereof for receipt of each second engaging component. In such a case, the one-piece lens can be quickly disassembled for replacement as desired, and such an eyeglasses assembly can be made at a low cost.
As further referring to a Taiwan patent registration with an issue number M377605, issued on 1 Apr. 2011, it disclose a frame having a slot on a side thereof and an one-piece lens having a positioning part extended from one end thereof, in which the positioning part further has an engaging hole and the slot further has an engaging block. In this case, the lens can be quickly fixed and positioned in the frame by insertion of the positioning part into the slot and engagement of the engaging block of the slot into the engaging hole of the positioning part.
The combinations of an eyeglasses frame and lens as shown in the above prior arts all need the engaging components on all possible positions thereof to be aligned relatively for stable engagement thereof in the courses of disassembly and assembly, and even those engaging components need to be disassembled in sequence. In other words, it is much more complicated and difficult for users to disassemble or assemble lens from a frame in a pair of eyeglasses.

Hsien Chang Optical Industrial Co., Ltd.


A combination vaporize/humidifier having a bucket member for holding water, a vaporizer head and a humidifier head wherein either connectors are provided on the humidifier head and vaporizer head to directly connect the heads to the bucket member. An alternative embodiment provides for an adapter plate such that the adapter plate allows for the heads to be securely attached to the bucket member.

1. Field of the Invention
This invention relates to a device for providing moisture to the atmosphere that can be used as both a humidifier and a vaporizer. More particularly, the present invention concerns a device for providing moisture in the air substantially comprising a bucket member defining a reservoir and an opening, a humidifier head and a vaporizer head wherein the device can function as a humidifier or a vaporizer by interchanging the heads. The present invention further provides an adapter plate that allows for either the humidifier head or the vaporizer head to be securely fastened to the bucket member.
2. Description of the Related Art
The use of vaporizers and humidifiers are well known. Examples of a vaporizer and a humidifier are disclosed in U.S. Pat. No. 5,693,270 and U.S. Pat. No. 5,607,627, respectively. Vaporizers are commonly used when one desires to introduce moisture in the form of steam into the atmosphere to break-up congestion in the user's lungs or nasal passages. Also, medication is sometimes placed on the vaporizer head so that the medication can be transported by the steam to the user's respiratory system. Humidifiers are commonly used when one desires to introduce moisture in the form of a cool mist into the atmosphere to eliminate dry air soothing a sore throat or cough. In general, humidifiers are used when it is desired to only counteract dryness in the air. Whereas, vaporizers, although also used to add moisture to the atmosphere and counteract dryness in the air, are used to break-up congestion in the user's lungs or nasal passages. Because humidifiers and vaporizers are used for different purposes, a household may need to purchase both a humidifier and a vaporizer.
Nowhere in the related art is there disclosed or suggested a device which has the capacity to function as a humidifier and as a vaporizer. Therefore, there is a definite need for the present invention which performs the functions of both a humidifier and a vaporizer and eliminates the need and expense of purchasing both a vaporizer and a humidifier.


A transceiver (10) in a first embodiment includes a zero intermediate frequency (ZIF) receiver (11), which achieves high throughput operation by reducing receiver latency time due to receiver response within a receiver pass band to carrier spectral components of a modulated carrier frequency. During a receive mode, a receiver local oscillator (LO) frequency is offset from the carrier frequency within the receiver pass band, preferably as determined by worst case errors in the carrier frequency and the LO frequency. During a transmit mode, the receiver LO frequency is modulated in such a way as to suppress the LO center frequency component in the modulated spectrum.

ZIF receivers are known in the art. ZIFs directly demodulate RF (radio frequency) signals from an RF carrier to baseband, requiring a receive local oscillator (LO) input which when applied to internal mixers of the ZIF receiver down-converts the RF signals modulated on the common carrier frequency. A ZIF receiver includes baseband receiver pass band characteristics, including an undesirable null response within a narrow band of frequencies including zero Hz. The null response of the receiver pass band is commonly a consequence of AC coupled circuitry within the receiver intended to eliminate DC levels occurring in ZIF receiver internal in-phase and quadrature circuits associated with demodulation. Additional nulling circuitry may also be provided to balance any DC offset levels in the in-phase and quadrature circuits to prevent distortion of the demodulated output of the ZIF receiver.
This can be a problem, e.g., in a typical wireless system like a local area network (LAN) that has signaling patterns modulated onto a transmitted signal used to initiate a communications function (e.g., a dotting sequence). Modulating the carrier frequency with such patterns will generate spectral components having discrete frequencies at significant fractions (e.g., 1/2) of the system data rate. This is in contrast to the normal data modulation which is random and imposes a quasi-continuous, shaped spectrum on the carrier. With signaling pattern modulation, any strong carrier spectral content near the receive local oscillator frequency is down converted to a frequency near DC. Because typical system frequency errors are compatible with system bandwidths and data rates, this is significant for the center carrier frequency component. In a transient situation where a modulated carrier having such a spectrum is suddenly applied to the ZIF receiver, the spectrum initially passes through to the ZIF detector and is properly demodulated. However, after a period of time determined by both the high-pass corner of the aforementioned AC coupling circuitry and the time constant of the DC offset nulling circuitry, the carrier frequency component near DC is significantly attenuated. This can cause severe distortion in the demodulated signal pattern--generally rendering it useless for purposes such as sync and clock recovery.
Another common application affected is switched antenna diversity reception, implemented to provide the best available received signal by having two antennas alternately sampled over several repeated cycles. The sampling dwell time on each antenna is sufficient to permit an evaluation of the quality of the signal received on that antenna. The evaluation can be a simple signal strength measurement, or more complex evaluation such as an error measurement. The sampling dwell time typically includes several cycles of the aforementioned signaling pattern and can be a significant fraction of the transient response time associated with the ZIF null response. Under these timing conditions, and with the downconverted carrier frequency near DC, the antennas are switching between stronger and weaker signals, effectively presenting the ZIF with two DC levels resembling a DC-offset square wave. The equivalent high-pass action of the ZIF baseband response removes the DC offset which causes both the stronger and weaker signals to appear to have the same strength or quality so that a correct diversity decision is difficult or cannot be made.
Thus, a signal having a strong carrier frequency spectral component within the null response of the ZIF receiver can either have its modulated information destroyed or it can cause the receiver to be "blind" to significant differences in signal strength. One technique which has been employed to prevent carrier spectral content from causing such effects involves off-setting the receiver local oscillator frequency from the carrier frequency by an amount greater than the receiver half-bandwidth during transceiver receive mode (see Gehring, et. al., U.S. Pat. No. 4,944,025). This prevents down converted carrier spectral content from coinciding with the receiver null, but at the expense of receiver sensitivity and selectivity due to increased receiver noise bandwidth.
A further problem may arise in single frequency duplex transceivers, i.e., systems that transmit and receive RF signals using a common nominal carrier frequency. The problem arises during the transmit mode of the transceiver. For example, in non-voice data communications systems, it is typically necessary to minimize the transmit-to-receive turnaround time due to system throughput requirements. Unfortunately, with the transmitter operating on the same frequency as the receiver, enough DC spectral content may be generated by the down conversion to create a null-related transient desensitization condition--even though random data is being modulated and no strong carrier spectral component exists. Large amounts of isolation between the transmitter and receiver would be necessary to prevent transmit carrier spectral content from coupling to the receiver, but this may be difficult to achieve in practice. Methods of preventing desensitization which involve removing power from the receiver, disconnecting the baseband filters and holding their operating state, or shifting the frequency of the receive local oscillator to some other frequency during the transmit mode can unfortunately involve excessively long periods of time to re-establish stable operating conditions associated with the ZIF receiver and the receive local oscillator in receive mode.
To beneficially employ ZIF receiver advantages, particularly in high-throughput data communications systems, a need remains for an improved receiver architecture, including one which both prevents ZIF null-related responses from undermining receive performance, and permits fast transition from transmit mode to receive mode.

Method and apparatus for improved zero intermediate frequency receiver latency


A switchable lever arrangement is provided that includes at least one switchable lever and a rotary actuator. The at least one switchable lever includes an outer lever, an inner lever pivotably mounted to the outer lever, and a locking part that selectively locks the inner lever to the outer lever. The rotary actuator rotates about a rotational axis to actuate the locking part. The rotary actuator has a first locked position defined by a first effective actuation length, and a second unlocked position defined by a second effective actuation length, with the second actuation length different than the first actuation length.

Levers are utilized within valve trains of IC engines to facilitate translation of rotary motion of a camshaft to linear motion of an intake or exhaust valve. Switchable levers can include a locking part that can lock or unlock an inner lever to an outer lever to achieve different discrete valve lifts. The locking part can be actuated by hydraulic fluid which can require a series of hydraulic fluid galleries arranged throughout an engine. The locking part can also be actuated by an electric actuator. Use of an electric actuator instead of actuation by hydraulic fluid can offer several advantages including, but not limited to, wider operating temperature range, elimination of hydraulic fluid oil galleries, and faster actuation times. Packaging space within an IC engine can be very limited for switchable lever systems.


Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

1. Technical Field
The disclosure relates generally to integrated circuit (IC) fabrication, and more particularly, to forming of high dielectric constant (high-k) and metal gate stacks using a capping layer.
2. Background Art
In the integrated circuit (IC) fabrication industry, metal gate electrodes are being pursued for, for example, the 45 nanometer (nm) and 32 nm technology nodes as a replacement for doped polysilicon (poly-Si) gate electrodes for a number of reasons. Metal gate electrodes include a high dielectric constant (high-k) dielectric within a metal gate stack. The best known self aligned process flows for complementary metal oxide semiconductor (CMOS) fabrication with the high-k dielectrics and metal gate stack use a dual field effect transistor (FET) threshold voltage (Vt) work function tuning layers scheme to tune the threshold voltage of adjacent n-type metal oxide semiconductor (NMOS) region (for NFETs) and p-type metal oxide semiconductor (PMOS) region (for PFETs). That is, dual metal/dual dielectric gate stacks. One challenge for this technology is that the continual reduction in device dimensions that define, for example, the 45 nm and 32 nm technology nodes, impose an ever reducing distance between the different active regions, e.g., approximately 102 nm for the 45 nm node and approximately 72 nm for the 32 nm node. The reduction in device dimensions presents a problem because tuning layers for NMOS and PMOS regions are not interchangeable. As a result, in order to accommodate formation of the appropriate gate stack for each region, gate stack layers particular to each region must be formed in both regions and then the opposing NMOS and PMOS region's stack must be completely removed, which is costly and induces process variations. Since the distance between active regions is so small, etching the gate stacks and continuing to meet ground rule restrictions is currently unachievable for the 45 nm and 32 nm CMOS technology nodes, and beyond. In particular, the ability to form material layers such that they are thin enough to fill a gap between partially formed gate stacks and such that the materials can be removed from the gap to ultimately form the gate stacks in the NMOS and PMOS regions is currently unfeasible. Butted junctions are also not available using current practices because of the removal of layers between the different NMOS and PMOS gate stacks.

High-K/metal gate stack using capping layer methods, IC and related transistors


In a preferred embodiment, a precious reagent container, including; a horizontally elongated body; a plurality of vertical, aligned reagent wells defined in the body, the reagent wells having a common depth; and a common vertical channel joining the vertical, aligned reagent wells, the common vertical channel having a depth equal to the common depth. A method of using the precious reagent container is also provided.

1. Field of the Invention
The present invention relates to reagents generally and, more particularly, but not by way of limitation, to novel precious reagent container and method of use.
2. Background Art
In the field of drug discovery and genomic research, there is a need to work with small aliquots of precious reagents. A problem arises when it is necessary to work with them in high throughput applications. To meet the throughput desired in this area of work, the microplate is the de facto standard in either 96 well format or 384 well format. The 96 well format consists of wells in an 8×12 matrix on 9 mm spacing. The 384 well format is a 16×24 matrix on 4.5 mm spacing. The newest configuration to consume reagents is the 1536 well format of a 32×48 matrix on 2.5 mm spacing.
The size of the precious liquid aliquot to be transferred is normally in the range of 0.5 to 5 microliters. This is easily accomplished with the multiple well pipettors that are available. A problem arises, however, in trying to fill the multiple pipettor tips. Normally, a reservoir is used to permit multiple well pipettors to aspirate aliquots simultaneously for dispensing. Assume 5 μL of reagent A is to be aspirated and dispensed to all wells of a 384 well microplate. This requires 1920 μL or 1.92 mL total volume. The wells of the pipettor are spread over an area of 72×108 mm or 7776 mm2. That equates to 4 μL for every square millimeter of the reservoir bottom. Surface tension alone prohibits that small a volume from uniformly covering that area.
The solution most commonly used is to have individual small grooves or channels defined in the bottom of the reservoir. Then, instead of trying to cover the entire area, it is only necessary to have enough reagents to fill the channels to a suitable depth to aspirate the required volume. Another approach is to have small dimples located under each aspirating well. Theoretically, the dimples could hold the volume desired for each aspirating well. The problem reverts to how is each dimple filled. If done individually, the advantage of multiple well pipetting is lost. To fill all dimples essentially simultaneously, a small volume may be placed in the reservoir and the reservoir is then shaken or vibrated to cause liquid motion to fill the dimples.
In all cases, there is a dead volume that cannot be aspirated with the multiple well pipettor. There is a loss when this dead volume is returned to the source or storage container. This loss and the need for extra reagent to fill the dead volume inhibit the use of multiple well pipettors.
Accordingly, it is a principal object of the present invention to provide a container that can be used as both a storage unit and a reservoir for multiple well pipetting, with essentially no dead volume as described above.
It is a further object of the invention to provide such a container that can be stored at temperatures of −20° C. to −80° C.
It is an additional object of the invention to provide such a container that can be easily filled.
It is another object of the invention to provide such a container that can be easily manufactured using conventional techniques.
It is yet a further object of the invention to provide a method of using such a container.
Other objects of the present invention, as well as particular features, elements, and advantages thereof, will be elucidated in, or be apparent from, the following description and the accompanying drawing figures.

Precious reagent container and method of use


A method for presenting video content including displaying the video content at an enhanced frame rate selectively modified to interfere with a recording of the video content by a camcorder. For example, the video content can be displayed at a frame rate of 54 pictures per second or a frame rate of 66 pictures per second. For implementation of the enhanced frame rate, a first picture can be displayed within the video content a first number of times and at least a second picture can be displayed a different number of times.

1. Statement of the Technical Field
The inventive arrangements relate to the field of protecting films against illegal copying.
2. Description of the Related Art
Piracy issues in connection with the theatrical exhibition of motion picture films are well known. Once a film distributor distributes prints of a motion picture film to exhibitors for theatrical exhibition, a certain degree of control over the product is lost. In the regular course of exhibiting the film, a customer in the theater may surreptitiously record the film using, for example, a hand held camcorder. At a more sophisticated level, a person seeking to obtain an illegal copy of a film print may gain access to a theater projection booth in collusion with an employee of the exhibitor and make a copy of the film after hours in a relatively controlled environment. In such an environment, the audio from the projection equipment can be directly fed to the camcorder. A tripod can be used to ensure a clear and steady picture. As a result, an illicit copy can be made. Thus, a method is needed to reduce the quality of such illicit copies so that the copies will be undesirable to consumers.

Anticamcorder media projection using enhanced frame rate


A two-quadrant multiplier for multiplying first and second signals, which can realize wide input voltage ranges at a low supply voltage such as 3 or 3.3 V, has a multitail cell. This multitail cell contains a pair of first and second transistors having differential input ends and differential output ends, a third transistor having an input end, and a constant current source for driving the pair and the third transistor. The first signal is applied across the differential input ends of the pair, and the second signal is applied in a single polarity (e.g., either a positive or negative polarity) to the input end of the third transistor. An output signal of the multiplier is a multiplication result of the first and second signals which is differentially derived from the differential output ends of the pair. At least one additional transistor may be provided, an input end of which is coupled with the input ends of the third transistor to be applied with the second signal. Two such multitail cells may be combined to form a four-quadrant multiplier for the first and second signals.

1. Field of the Invention
The present invention relates to a multiplier for multiplying two analog input signals, which is to be realized on a semiconductor integrated circuit device and more particularly, to an analog multiplier formed of bipolar transistors and/or metal-oxide-semiconductor field-effect transistors (MOSFETs), which can operate within an expanded input voltage range or ranges even at a low supply voltage such as 3 or 3.3 V.
2. Description of the Prior Art
An analog multiplier constitutes a functional circuit block essential for analog signal applications. Recently, semiconductor integrated circuits have been made finer and finer and as a result, their supply voltages have been decreasing from 5 V to 3.3 or 3 V.
Under such a circumstance, a low-voltage circuit technique that enables to operate at such a low voltage as 3 V has been required to be developed. In the case, the input voltage ranges of the multiplier need to be wide as much as possible.
The Gilbert multiplier cell is well known as a bipolar multiplier. However, the Gilbert multiplier cell has such a structure that bipolar transistor-pairs are stacked in two stages and as a result, it cannot respond to or cope with such the supply voltage reduction as above. Therefore, a new bipolar multiplier that can operate at such the low supply voltage has been expected instead of the Gilbert multiplier cell.
Besides, the Complementary MOS (CMOS) technology has become recognized to be the optimum process technology for Large Scale Integration (LSI), so that a new circuit technique that can realize a multiplier using the CMOS technology has been required.
To respond such the expectation as above, the inventor, Kimura, developed multipliers as shown in FIGS. 1, 4 and 7, each of which has two squaring circuits. One of the squaring circuits is applied with a differential input voltage (V1+V2), and the other thereof is applied with another differential input voltage (V2-V1), where V.sub.1 and V.sub.2 are input signal voltages to be multiplied. The outputs of these two squaring circuits are subtracted to generate an output voltage V.sub.OUT of the multiplier, which is expressed as EQU V.sub.OUT =(V.sub.1 +V.sub.2).sup.2 -(V.sub.2 -V.sub.1).sup.2 =4V.sub.1 .multidot.V.sub.2
From this equation, it is seen that the output voltage V.sub.OUT is proportional to the product V.sub.1 .multidot.V.sub.2 of the first input voltage V.sub.1 and the second input voltage V.sub.2, meaning that the circuit having the two squaring circuits provides a multiplier characteristic.
The squaring circuits are arranged along a straight line transversely not in stack, to be driven at the same supply voltage.
The above prior-art multipliers developed by Kimura were termed "quarter-square multipliers" since the constant "4" of involution contained in the term of the product was changed to "1".
Next, the Kimura's prior-art multipliers will be described below.
First, the Kimura's prior-art multiplier shown in FIG. 1 is disclosed in the Japanese Non-Examined Patent Publication No. 5-94552 (April, 1993). In FIG. 1, this multiplier includes a first squaring circuit made of bipolar transistors Q51, Q52, Q53 and Q54 and a second squaring circuit made of bipolar transistors Q55, Q56, Q57 and Q58.
In the first squaring circuit, the transistors Q51 and Q52 form a first unbalanced differential pair driven by a first constant current source (current :I.sub.0) and the transistors Q53 and Q54 form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor Q51 is K times in emitter area as large as the transistor Q52 and the transistor Q54 is K times in emitter area as large as the transistor Q53.
Emitters of the transistors Q51 and Q52 are connected in common to the first constant current source, and emitters of the transistors Q53 and Q54 are connected in common to the second constant current source.
In the second squaring circuit, the transistors Q55 and Q56 form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0) and the transistors Q57 and Q58 form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor Q55 is K times in emitter area as large as the transistor Q56 and the transistor Q58 is K times in emitter area as large as the transistor Q57.
Emitters of the transistors Q55 and Q56 are connected in common to the third constant current source, and emitters of the transistors Q57 and Q58 are connected in common to the fourth constant current source.
Bases of the transistors Q51 and Q53 are coupled together to be applied with a first input voltage V.sub.x, and bases of the transistors Q52 and Q54 are coupled together to be applied with a second input voltage V.sub.y.
Bases of the transistors Q55 and Q57 are coupled together to be applied with the first input voltage V.sub.x, and bases of the transistors Q56 and Q58 are coupled together to be applied in opposite phase with the second input voltage V.sub.y, or -V.sub.y.
The transfer characteristics and the transconductance characteristics of the multiplier of FIG. 1 are shown in FIGS. 2 and 3, respectively, where K is e.sup.2 (.apprxeq.7.389). A differential output current .DELTA.I shown in FIG. 2 is defined as the difference of output currents I.sub.p and I.sub.q shown in FIG. 1, or (I.sub.p -I.sub.q).
FIG. 2 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 3 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Second, the Kimura's prior-art multiplier shown in FIG. 4 is disclosed in the Japanese Non-Examined patent Publication No. 4-34673 (February, 1992). In FIG. 4, the multiplier includes a first squaring circuit made of MOS transistors M51, M52, M53 and M54 and a second squaring circuit made of MOS transistors M55, M56, M57 and M58.
In the first squaring circuit the transistors M51 and M52 form a first unbalanced differential pair driven by a first constant current source (current :I.sub.0), and the transistors M53 and M54 form a second unbalanced differential pair driven by a second constant current source (current: I.sub.0). The transistor M52 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M51, and the transistor M53 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M54.
Sources of the transistors M51 and M52 are connected in common to the first constant current source, and sources of the transistors M53 and M54 are connected in common to the second constant current source.
In the second squaring circuit, the transistors M55 and M56 form a third unbalanced differential pair driven by a third constant current source (current: I.sub.0), and the transistors M57 and M58 form a fourth unbalanced differential pair driven by a fourth constant current source (current: I.sub.0). The transistor M56 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M55, and the transistor M57 is K' times in ratio (W/L) of a gate-width W to a gate-length L as much as the transistor M58.
Sources of the transistors M55 and M56 are connected in common to the third constant current source, and sources of the transistors M57 and M58 are connected in common to the fourth constant current source.
Gates of the transistors M51 and M53 are coupled together to be applied with a first input voltage V.sub.x, and gates of the transistors M52 and M54 are coupled together to be applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y.
Gates of the transistors M55 and M57 are coupled together to be applied with the first input voltage V.sub.x, and gates of the transistors M56 and M58 are coupled together to be applied with the second input voltage V.sub.y.
In FIG. 4, the transconductance parameters of the transistors M51, M54, M55 and M58 are equal to be .beta., and those of the transistors M52, M53, M56 and M57 are equal to be K'.beta..
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 5 and 6, respectively, where K' is 5. A differential output current .DELTA.I shown in FIG. 5 is defined as the difference of output currents I.sup.+ and I.sup.- shown in FIG. 4, or (I.sup.+ -I.sup.-).
FIG. 5 shows the relationship between the differential output current .DELTA.I and the fist input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 6 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter
Third, the Kimura's prior-art multiplier shown in FIG. 7 is disclosed in IEICE TRANSACTIONS ON FUNDAMENTALS, Vol. E75-A, No. 12, December, 1992. In FIG. 7, the multiplier includes a first squaring circuit made of MOS transistors M61, M62, M63 and M64 and a first constant current source (current: I.sub.0) for driving the transistors M61, M62, M63 and M64, and a second squaring circuit made of MOS transistors M65, M66, M67 and M68 and a second constant current source (current: I.sub.0) for driving the transistors M65, M66, M67 and M68. The transistors M61, M62, M63, M64, M65, M66, M67 and M68 are equal in capacity or ratio (W/L) of a gate-width W to a gate-length L to each other.
The first and second squaring circuits are termed "quadritail circuits" or "quadritail cells" in which four transistors are driven by a common constant current source, respectively.
In the first quadritail circuit, sources of the transistors M61, M62, M63 and M64 are connected in common to the first constant current source. Drains of the transistors M61 and M62 are coupled together and drains of the transistors M63 and M64 are coupled together. A gate of the transistor M61 is applied with a first input voltage V.sub.x, and a gate of the transistor M62 is applied in opposite phase with a second input voltage V.sub.y, or -V.sub.y. Gates of the transistor M63 and M64 are coupled together to be applied with the middle level of the voltage applied between the gates of the transistors M61 and M62, or (1/2)(V.sub.x +V.sub.y), which is obtained through resistors (resistance: R).
Similarly, In the second quadritail circuit, sources of the transistors M65, M66, M67 and M68 are connected in common to the second constant current source. Drains of the transistors M65 and M66 are coupled together and drains of the transistors M67 and M68 are coupled together. A gate of the transistor M65 is applied with the first input voltage V.sub.x, and a gate of the transistor M66 is applied with the second input voltage V.sub.y. Gates of the transistor M67 and M68 are coupled together to be applied with the middle level of the voltage applied between the gates of the transistors M65 and M66, or (1/2)(V.sub.x -V.sub.y), which is obtained through resistors (resistance: R).
Between the first and second quadritail circuits, the drains coupled together of the transistors M61 and M62 and the drains coupled together of the transistors M67 and M68 are further coupled together to form one of differential output ends of the multiplier. The drains coupled together of the transistors M63 and M64 and the drains coupled together of the transistors M65 and M66 are further coupled together to form the other of the differential output ends thereof.
The transfer characteristics and the transconductance characteristics of the multiplier are shown in FIGS. 8 and 9, respectively. A differential output current .DELTA.I shown in FIG. 8 is defined as the difference of output currents I.sub.P and I.sub.Q shown in FIG. 7, or (I.sub.p -I.sub.Q).
FIG. 8 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 9 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
Further prior-art multiplier is shown in FIG. 10, which was developed by Wang and termed the "Wang cell". This is disclosed in IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September, 1991. The circuit in FIG. 10 is modified by the inventor, Kimura, to clarify its characteristics
In FIG. 10, the multiplier includes one quadritail circuit made of MOS transistors M71, M72, M73 and M74 and a constant current source (current: I.sub.0) for driving the transistors M71, M72, M73 and M74. The transistors M71, M72, M73 and M74 are equal in capacity (W/L) to each other.
Sources of the transistors M71, M72, M73 and M74 are connected in common to the constant current source. Drains of the transistors M71 and M74 are coupled together to form one of differential output ends of the multipliers and drains of the transistors M72 and M73 are coupled together to form the other of the differential output ends thereof.
A gate of the transistor M71 is applied with a first input voltage (1/2)V.sub.x based on a reference point, and a gate of the transistor M72 is applied in opposite polarity with the first input voltage V.sub.x, or -V.sub.x based on the reference point. A gate of the transistor M73 is applied with a voltage of the half difference of the first input voltage and a second input voltage, or (1/2)(V.sub.x -V.sub.y). A gate of the transistor M74 is applied with the voltage (1/2)(V.sub.x -V.sub.y) in opposite polarity, or (-1/2)(V.sub.x -V.sub.y).
The transfer characteristics and the transconductance characteristics of the Wang's multipliers which were obtained through analysis by the inventor, are shown in FIGS. 11 and 12, respectively. A differential output current .DELTA.I shown in FIG. 11 is defined as the difference of output currents I.sub.L and I.sub.R shown in FIG. 10, or (I.sub.L -I.sub.R).
FIG. 11 shows the relationship between the differential output current .DELTA.I and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter. FIG. 12 shows the relationship between the transconductance (d.DELTA.I/dV.sub.x) and the first input voltage V.sub.x with the second input voltage V.sub.y as a parameter.
The prior-art bipolar multiplier of FIG. 1 has input voltage ranges that is approximately equal to those of the conventional Gilbert multiplier cell. Each of the prior-art MOS multipliers of FIGS. 4, 7 and 10 has input voltage ranges of superior linearity that is comparatively wider than those of the Gilbert multiplier cell.
However, on operating at a low supply voltage such as 3 or 3.3 V, all of the prior-art multipliers cannot expand their input voltage ranges of superior linearity due to causes relating their circuit configurations.


A display apparatus according to the present invention includes: a measuring unit that measures an image displayed on a screen; a first determining unit that determines a first display setting by executing a single unit calibration; a second determining unit that determines a second display setting by executing a link calibration; and a determining unit that determines, during display of an external input image, which is an image based on an image signal input from an external apparatus, whether or not an output setting of the external apparatus or the second display setting differs from a setting during display of a previous external input image. The second determining unit executes the link calibration when the determining unit determines that the output setting of the external apparatus or the second display setting differs from the setting during display of the previous external input image.

1. Field of the Invention
The present invention relates to a display apparatus and a control method thereof.
2. Description of the Related Art
A high definition medical monitor (a display apparatus for displaying medical images) typically displays medical images output from an external apparatus such as a PC (personal computer). It is predicted, however, that in the future highly sophisticated medical monitors on which medical images can be displayed simply by a monitor alone will be developed. It is also predicted that a portable monitor (display apparatus) will be developed as this type of medical monitor. By using this type of medical monitor, it will be possible to perform a normal reading operation using a sophisticated PC (software stored on the PC) and the monitor, and to provide explanations and the like to a patient using the monitor alone (by displaying medical images simply using the monitor). It is also predicted that this type of medical monitor will be connected to a network. Accordingly, it is predicted that a medical monitor which obtains images from the network and displays the obtained images will be developed.
In the case of a monitor such as that described above, an appearance (a display characteristic) of a displayed image must be matched to a target value. However, an image input from a PC (an external input image hereafter) may vary according to a characteristic of a graphic board provided in the PC and processing performed in the PC (image processing performed in the PC, for example). In other words, an identical image may exhibit a different display characteristic as an external input image and an image displayed by the monitor alone (a single unit display image). To solve this problem, it may be necessary to perform both calibration (link calibration hereafter) of the display characteristic of the external input image and calibration (single unit calibration hereafter) of the display characteristic of the single unit display image as display characteristic calibration.
Related art pertaining to calibration is disclosed in Japanese Patent Application Publication No. 2002-057911 and Japanese Patent Application Publication No. 2005-208548, for example.
More specifically, Japanese Patent Application Publication No. 2002-057911 discloses a technique for correcting a result of a soft calibration on the basis of a result of a device calibration. The soft calibration is performed on the basis of data obtained by reading a printing result of a printer using a scanner. The device calibration is performed automatically in the printer on the basis of a potential of a latent image formed on a photosensitive drum and a density of a toner image.
Japanese Patent Application Publication No. 2005-208548 discloses a technique in which a photometry unit provided to face a liquid crystal display unit performs photometry, whereupon calibration is performed on the basis of a difference value between a result of the photometry and a predetermined ideal value.

Display apparatus and control method thereof


An image forming device includes a paper dust removal unit that removes paper dust from a photosensitive member. The paper dust removal unit includes a brush-shaped member affixed to a plate by a two-sided tape. The brush-shaped member is peeled off from the plate so as to re-use the plate and the like of the paper dust removal unit. The tensile strength of the two-sided tape is greater than the shear adhesive strength between the two-sided tape and the plate, so that the two-sided tape is prevented from tearing partway when the brush-shaped member is peeled off.

1. Field of the Invention
The present invention relates to a process cartridge that is provided with paper dust removal means for removing paper dust from an image holding member, and also to an image forming device that includes the process cartridge.
2. Related Art
Japanese Patent Application-Publication No. 2001-159839 proposes a process cartridge that is provided with a paper dust removal device for removing paper dust from a photosensitive member. The paper dust removal device has a brush-shaped member that is formed of fibers and disposed between a transfer roller and a charger. A charge is applied to a brush of the brush-shaped member, so that the brush can trap paper dust by the force of the resultant electrical field. Paper dust is generally negatively charged and also charged to the opposite polarity of the toner by a bias applied during a transfer operation. Therefore, if a positively charged toner is used, then the paper dust is strongly negatively charged. Applying a voltage of the same polarity as that of the toner to the brush enables the brush-shaped member to efficiently trap paper dust without trapping the toner. The brush-shaped member is usually fixed by two-sided tape onto an electrically conductive plate, such as an aluminum plate. The two-sided tape includes a non-woven fabric and bonding layers on both sides of the non-woven fabric. The non-woven fabric exhibits electrical conductivity on absorbing moisture. Using a non-woven fabric as a substrate of the two-sided tape facilitates the transfer of charge to the brush, increasing the paper dust trapping capability of the brush.
However, the abovementioned technique has a problem in that when peeling off the brush-shaped member from the plate, the two-sided tape could tear partway and fragments of the two-sided tape could be left on the plate, so that a large amount of manual work is required for removing the two-sided tape from the plate completely.
Recent concern for protecting the environment has led to a trend towards reclaiming and reusing components in various electrical and electronic appliances, with the objective of saving resources and energy and reducing garbage.
In the process cartridge used in an image forming device, such as a printer, the brush of the brush-shaped member can become dirty or damaged whereas the holder including the plate to which the brush-shaped member is affixed is not particularly susceptible to damage and can be reused. Thus any tearing of the two-sided tape during the removal of the brush-shaped member will necessitate manual work in its removal, adversely affecting the feasibility of recycling the process cartridge.

Process cartridge including paper dust removal member


Terminal shields are provided that are configured to protect an optical terminal device. The terminal shield comprises a first portion configured to be secured with respect to the optical terminal device. The terminal shield further comprises a second portion pivotally attached to the first portion. The second portion is configured to be pivoted relative to the first portion between an open orientation to provide access to an area of the optical terminal device and a closed orientation with the terminal shield disposed about a portion of the optical terminal device.

1. Field of the Invention
The present invention relates generally to terminal shields, and more particularly, to a terminal shields and optical assemblies including a terminal shield.
2. Technical Background
Conventional optical terminal devices are known to house optical components including interconnections between optical fibers. Such conventional devices are frequently suspended from a support cable and are effective to protect the housed optical components from debris and outside weather conditions. However, conventional devices may fail to include structure sufficient to prevent damage caused by animals such as birds and rodents. Without such protection, animals may damage the outer housing and/or sensitive optical components within the optical terminal device.

Terminal shields for protecting optical components in optical assemblies


A gas detector is disclosed which includes a CO sensor and a processor. The CO sensor senses an environmental CO concentration and provides a variable electrical output in response. The processor receives digitized samples of the sensor's electrical output and computes, with each measurement sample, a COHb level of a hypothetical person exposed to the CO concentration sensed. The computation involves determining an equilibrium COHb level for each measurement sample, which is compared with a previously computed COHb level associated with previously measured samples. The previously computed COHb level is updated based on the comparison. When the computed COHb level is above a predetermined danger threshold, the processor preferably causes an audible and visual alarm to be activated to alert any persons present. The gas detector can further include a CH.sub.4 sensor coupled to the processor for independently sensing CH.sub.4 levels such that an alarm is activated when the CH.sub.4 levels are above a predefined threshold. A hydrophobic zeolite filter is disposed on the sensor elements of one or both of the CO and CH.sub.4 sensors to prevent erroneous readings.

Natural gases and liquefied petroleum gases are widely used as fuels for domestic, commercial and industrial purposes, e.g., for heating and/or cooking. As a result, there is often a danger that leakage of such gas from piping and other apparatus will contaminate the surrounding environment, creating a dangerous condition. For example, alkane gases such as methane are extremely combustible and furthermore could poison individuals if present at too great a level in enclosed surroundings. Moreover, small quantities of carbon monoxide can escape from such flowing gas streams into the environment, or could be generated by incomplete combustion of natural gas. Carbon monoxide is odorless and colorless, so that the contaminating levels are not readily observable by individuals. However, carbon monoxide is absorbed by an individual's lungs and reacts with the hemoglobin in the blood to form carboxyhemoglobin (COHb), reducing oxygen carrying capacity of the blood. Therefore, presence of carbon monoxide in an environment above certain levels is extremely dangerous and can easily poison individuals unaware of its presence.
Accordingly, there is a need to provide for suitable detection and concomitant alarm of unwanted fluid, i.e., gaseous contaminants in order to prevent unsafe or dangerous conditions from developing, e.g., in an enclosed environment. In this regard, various detectors for carbon monoxide and alkanes such as methane gas have been developed.
Various residential carbon monoxide gas detectors are found in the prior art and typically function to sound an audible alarm when a specified environmental CO concentration is detected. Carbon monoxide sensing elements employed within such detectors typically comprise a metal oxide layer on a ceramic substrate. When the ceramic substrate is heated to a high temperature, e.g., 200-400.degree. C., the resistance of the metal oxide varies as a function of the environmental CO concentration. The sensing element can thus be employed as a variable resistor in a calibrated detection/alarm circuit which continuously monitors the environmental CO concentration and sounds an alarm upon the detection of hazardous levels.
Methane detectors which employ metal oxide semiconductor sensors are also in the prior art. As with CO sensors, many methane sensors also operate by maintaining the ceramic substrate at a high temperature such that the resistance of the metal oxide predictably changes as a function of ambient CH.sub.4 concentration. Methane sensors are available which are relatively insensitive to the presence of carbon monoxide, and vice versa.
False alarms and/or gas detection inaccuracies due to the presence of airborne contaminants are often a problem with CO and CH.sub.4 detectors. The sensing elements are typically sensitive to the presence of airborne gases and vapors such as alcohols, solvents and water vapor. In the common household environment, the use of cleaning agents, paints, turpentine, solvents, etc., produce vapors which can alter the resistance of the sensing element, thereby causing false alarms in the detection of the target gas.
When carbon monoxide enters a person's bloodstream, it reacts with hemoglobin (Hb) to form carboxyhemoglobin (COHb). A person is in danger of carbon monoxide poisoning when the person's COHb level exceeds a specific level, such as the levels promulgated by Underwriters Laboratories UL2034 carbon monoxide exposure specification. An individual's COHb level is a function of their exposure time to the environmental CO concentrations. False alarms are particularly a problem in prior art CO sensors because these sensors do not accurately model the COHb level that would be present in the exposed person's bloodstream. For example, a relatively high environmental CO concentration that is present for only a very short time duration often causes an alarm to be sounded in prior art CO sensors when such exposure would actually produce a COHb level well below the danger level.
U.S. Pat. No. 4,896,143 to Dolnick et al. discloses a CO sensor which is operatively connected to a microprocessor for calculating doses of carbon monoxide. The values of CO are accumulated over time, with the dose measurement being made by adding a measured value of CO concentration, which may be weighted, to a memory register each time the value is determined. An alarm is issued if the accumulated value reaches a predetermined value. A drawback of this technique is that the physiological response is not accurately modeled, which may lead to false alarms and/or under-detection of CO.


A structure for installing an information processor into an electronic equipment includes a biasing unit provided in the information processor; and a projection portion provided in a housing of the electronic equipment. In the structure, the protruding portion biases the biasing unit and the biasing unit applies a predetermined pushing force to the housing via the protruding portion when the information processor is installed in the housing.

1) Field of the Invention
The present invention relates to a structure of installing an information processor such as a hard disk drive (HDD) in an electronic equipment such as a disk array device.
2) Description of the Related Art
So-called residual vibrations arise before a head (data reader) of an actuator of a hard disk drive (hereinafter, "HDD") is positioned at a center of a target track. The residual vibrations are generated when the actuator of the HDD moves, or a medium of the HDD rotates. The residual vibrations are also generated, due to external vibrations, when an installed rocker shakes or another HDD installed in the same electronic equipment vibrates.
The head sometimes comes off the target track due to such vibrations, which is called the off-track phenomenon, and the performance of the device thereby deteriorates. Accordingly, in order to reduce such residual vibrations, the vibration of the HDD must be suppressed. A known technique for suppressing vibrations of the HDD is shown in FIGS. 10 and 11.
FIG. 10 is a side view of a conventional installation structure of an information processor, and FIG. 11 is an enlarged view of a portion C shown in FIG. 10. As shown in FIG. 10, an HDD 10 is installed between an upper chassis 120 and a lower chassis 130 of the electronic equipment. An interval between the upper chassis 120 and the lower chassis 130 is set to be slightly larger than a height of the HDD 10.
A U-shaped supporting member 15 is provided at the HDD 10 so as to surround a ceiling surface, a front surface, and a bottom surface thereof. Plate springs 140 and 150 are provided at a front portion and a rear portion of the ceiling surface of the supporting member 15, respectively.
As shown in FIGS. 10 and 11, when the HDD 10 is inserted between the chassis 120 and 130 and after insertion is completed, the plate springs 140 and 150 abut the upper chassis 120 so as to reduce the residual vibrations by biasing forces of the plate springs 140 and 150. Japanese Patent Application Laid-Open No. 2001-202767 discloses such a technique of installing the HDD in the electronic equipment by using a plate spring.
The plate springs 140 and 150 may be made stiff in order to reduce the residual vibrations. However, if the plate springs 140 and 150 are merely made stiff, frictional force between the plate springs 140 and 150 and the upper chassis 120, and frictional force between the HDD 10 and the lower chassis 130 increase. Therefore, it becomes difficult to insert the HDD 10 between the chassis 120 and 130, and the usability deteriorates.
Another problem occurs in a disk array device. A disk array device is an electronic equipment in which a plurality of HDDs are installed. The disk array device is often equipped with a residual-vibration countermeasure mechanism and a security mechanism (locking mechanism) such that the HDDs cannot be easily taken-out and data security is maintained.
However, the residual-vibration countermeasure mechanism and the security mechanism (locking mechanism) are not integral, and these mechanisms are provided separately. Therefore, the number of parts is large and the device structure is complex.

Structure of installing information processor


A wireless power transmission system according to an embodiment of the present invention is a wireless power transmission system performing non-contact power transmission from a wireless power feeder selectively to a plurality of wireless power receivers, and each of the plurality of wireless power receivers comprises a power receive resonance circuit including a power receive coil and a power receive capacitor, and the wireless power feeder comprises a power feed coil and a control circuit supplying AC power to the power feed coil. The control circuit in the wireless power feeder performs power supply selectively to the plurality of wireless power receivers by changing frequency of the AC power on the basis of a magnetic field resonance effect between the power feed coil and the power receive coil.

1. Field of the Invention
The present invention relates to a wireless power transmission system for performing power transmission by a non-contact method.
2. Related Background Art
Japanese Patent Application Laid-Open Publication No. 2010-63245 discloses a non-contact power feed apparatus (wireless power transmission system) comprising: a power feeding source (wireless power feeder) including a power feeding source resonance element having a variable mechanism changing a resonance frequency discretely or continuously, a power feeding source excitation element (excitation coil) coupled to the power feeding source resonance element by electromagnetic induction, and an AC power source applying AC current having the same frequency as the resonance frequency to the excitation element; and plural power feeding destinations (Wireless power receivers) each including a power feeding destination resonance element having a specific resonance frequency, a power feeding destination excitation element (load coil) coupled to the power feeding destination resonance element by electromagnetic induction, and an output circuit outputting current induced in the power feeding destination excitation element, wherein the non-contact power feed apparatus changes the resonance frequency of the power feeding source and performs power feeding selectively to the power feeding destinations having the respective specific resonance frequencies different from one another. Thereby, it is concluded that selective power feeding to a specific power feeding destination can be performed.

Wireless power transmission system for selectively powering one or more of a plurality of receivers


Novel tools and techniques for defining a search range for conjugate points in a set of images. In one technique, an intra-overlap area in two images can be used to define a search range in which a conjugate point can be found; in an aspect, this search range might be expressed as a distance range from a station at which one or both of the two images were captured. That distance range can be used to narrow the search range in an image captured from another station, substantially reducing both the computation time to identify a conjugate match and the likelihood of identifying an incorrect match.

Photogrammetry is a computational technique in which a plurality of images (such as stereo images) can be used to determine the location of points captured in the images relative to the position of the sensor that captured the images. To perform such analysis, however, the multiple images must first be oriented with respect to one another; such orientation defines the spatial and angular relationships between the two scenes in the captured images (or, conversely, the spatial and angular relationships between the sensors when capturing the respective images).
One technique for orienting a plurality of images (such as stereo images) is termed, "bundle adjustment," which is the technique of simultaneously refining the three-dimensional coordinates describing the scene geometry of each captured image, and/or relative orientations of the image capture system(s) that captured the images. Essentially, bundle adjustment attempts to optimize (minimize) the reprojection error between the image locations of observed and predicted image points; this error can be expressed as the sum of squares of a large number of nonlinear, real-valued functions.
Accordingly, bundle adjustment is computationally expensive, because it requires first the identification of conjugate points in the several images (i.e., grid locations in each image of the same real-world feature captured in all of the images) and then the optimization of the equations expressing the positions of those conjugate points in each image. The step of identifying these conjugate points (termed "conjugate matching") is especially compute intensive because it involves identification of similarities in groups of adjacent pixels in each of the image, which requires comparison of huge numbers of pixels in each image against one another to identify conjugate candidates, which can then be analyzed to determine whether the respective points depicted by the pixels in each image actually represent conjugate points.
Currently the methods for conjugate point matching on stereo images can be divided into two groups: area based matching and feature based matching. The methods of area based matching require very accurate initial position of conjugate candidates. The methods of feature based matching also need a general area of the potential candidates. Although the employment of epipolar geometry can reduce the search scope for correct conjugate point from two dimensions to one dimension, the one dimensional search range is still very large for large imagery data. For instance, the size of a single image from a typical camera is 2592 by 1944. Without a pre-determined search range, the method has to go through each pixel on the epipolar line on one of the images to identify a point on the other image. Therefore, to find the conjugate points from one image capture position/orientation (i.e., a "station") to another station is a tremendously processing-intensive task involving comparison along the entire epipolar line.
To alleviate this problem, one might attempt to reduce the search range (i.e., the portion of an image that is searched for conjugate matches) arbitrarily. An incorrect search range, however, results in an incorrect or failed match, while a large search range may increase the both possibility of a wrong match (due to the large number of potential conjugate candidates) as well as computation time.
Currently-known feature based methods always avoid the problem of determining the search range, and directly begin with an assumption that the area of conjugate points is known, or at least roughly known. The area based methods are usually applied in conjugate point matching on aerial or satellite images in which, the overlap between stereo images, flight height of aircraft, and general terrain configuration are available, which allows relatively inexpensive computation of the position of correct conjugate points can be accurately.
Neither of these types of methods, however, can efficiently handle conjugate matching on panoramic images taken at ground level. For example, provisional U.S. Patent App. No. 61/710,486, filed Oct. 5, 2012 by Grässer et al. and titled "Enhanced Position Measurement Systems and Methods," as well as U.S. patent application Ser. No. 13/332,648, filed Dec. 21, 2011 by Grässer et al. and titled "Enhanced Position Measurement Systems and Methods" (both of which are hereby incorporated herein by reference and which are collectively referred to herein as the "Incorporated Applications") describe position measurement systems that feature a suite of panoramic cameras that provide, in some cases, up to 360° photographic coverage around a capture point.
Unlike the targets in aerial or satellite images, which are approximately on the ground plane and have a predictable distance to the camera in the aircraft, the distance from targets in panoramic ground images, such as building facades, captured by such a ground-based position measurement system can vary according to different targets. Consequently, it is almost impossible to predict the position of the conjugate points in the stereo images. Therefore, the traditional point matching methods, area based or feature based, usually fail in conjugate point matching for such panoramic images, because the search algorithm has no clue about where to search for the correct match.
Accordingly, there is a need for more robust point matching techniques. It would be particularly helpful if such techniques could be employed in the context of panoramic stereo images.

Use of overlap areas to optimize bundle adjustment