The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers (G1-G10) having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line (VCDL2) in which differential buffers (H1-H8) having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector (S2) that extracts a clock signal from any stage of voltage-controlled delay line (VCDL1) and outputs to the first stage of voltage-controlled delay line (VCDL2); and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line (VCDL2). This digital phase control circuit (10) feedback-controls voltage-controlled delay line (VCDL1) and voltage-controlled delay line (VCDL2) by delay locked loops (DLL1) and (DLL2), controls the phases of clock signals with the difference 40 ps between 160 ps and 200 ps as the resolution; and therefore is a power-saving, compact, and high-resolution digital phase control circuit that suppresses increase in power consumption and increase in the area occupied by circuits to a minimum.

1. Field of the Invention:
The present invention relates to a digital phase control circuit that receives reference clock signals having a prescribed frequency and outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal.
2. Description of the Related Art:
A digital phase control circuit that receives reference clock signals having a prescribed frequency and that outputs one or more clock signals in which phase is controlled in units of a prescribed delay difference (resolution) with respect to the reference clock signal is configured similar to an example of the prior art, digital phase control circuit 100, that is shown in FIG. 1.
This digital phase control circuit 100 of the prior art is configured such that: input selector S1 having four input terminals is connected to delay locked loop DLL 1 that includes a voltage-controlled delay line VCDL 1 that is composed of ten stages of differential buffers G1-G10 and the differential buffer is a kind of delay buffer; and moreover, output selector S2 is connected to the output of each of differential buffers G1-G10. Delay locked loop DDL1 is composed of: voltage-controlled delay line VCDL1; phase detector PD1; charge pump CP1; and low-pass filter LPF1.
The composition and operation of this prior-art digital phase control circuit is next explained using numerical values.
Clock signals CLK1-4 (reference clocks) of 325.5 MHz (with a period of 3200 ps) in a total of four phases with phase differences of 800 ps are supplied to the four input terminals IN of selector S1. In other words, two clock signals CLK1 and CLK3 having a half-period phase difference (1600 ps) with respect to each other form one differential pair, and similarly, another two clock signals CLK2 and CLK4 having a relative half-period phase difference (1600 ps) form a differential pair.
These clock signals CLK1-CLK4 are controlled in advance by, for example, a phase-locked loop that is not shown in the figure such that the frequencies of the four clock signals CLK1-CLK4 and the phase differences between them (800 ps) are equal and are then supplied to input terminals IN.
Selector S1 selects and extracts a differential pair from the plurality of input terminals IN. In other words, selector S1 selects a pair of differential clock signals from the four types of differential clock signals CLK1-3, CLK3-1, CLK2-4, and CLK4-2, and outputs to voltage-controlled delay line VCDL1 and phase detector PD1.
In a case in which differential clock signals CLK1-3 are selected, clock signal CLK1 is outputted to one of the two output terminals OUT, and clock signal CLK3 is outputted to the other.
The operation is equivalent in cases in which differential clock signals CLK3-1, CLK2-4, or CLK4-2 are selected. However, the output terminals OUT to which differential clock signals CLK1 and CLK3 are outputted when differential clock signals CLK1-3 are selected is the reverse of that for a case in which differential clock signals CLK3-1 are selected. The same relation holds for differential clock signals CLK2-4 and differential clock signals CLK4-2.
The ten stages of differential buffers G1-G10 that make up voltage-controlled delay line VCDL1 each have propagation delay times of 160 ps and are controlled by the feedback control of delay locked loop DLL1 such that their delay times are uniform. The feedback control of delay locked loop DLL1 is carried out as follows:
A clock signal having the total delay of all buffers G1-G10 is outputted from differential buffer G10. In a case in which differential clock signals CLK1-3 are selected by selector S1, for example, phase detector PD1 both receives clock signals CLK1 and CLK3 that have passed through voltage-controlled delay line VCDL1 and have the total delay of all buffers G1-G10 and receives direct clock signals CLK1 and CLK3 (reference clocks) that have not passed through voltage-controlled delay line VCDL1. Phase detector PD1 compares the phases of clock signal CLK1, which has the total delay, and clock signal CLK3 (the reference clock) that precedes passage through voltage-controlled delay line VCDL1, compares the phases of clock signal CLK3 having the total delay and clock signal CLK1 (the reference clock) that precedes passage through voltage-controlled delay line VCDL1, and detects the phase differences. Phase detector PD1 outputs an UP signal to charge pump CP1 if the phase of clock signal CLK1 (CLK3) having the total delay is behind the phase of clock signal CLK3 (CLK1) that precedes passage though voltage-controlled delay line VCDL1; and outputs a DOWN signal to charge pump CP1 if the phase of clock signal CLK1 (CLK3) is ahead. The operation is equivalent for cases in which differential clock signals CLK3-1, CLK2-4 or CLK4-2 are selected by selector S1.
Charge pump CP1 and low-pass filter LPF1 generate control signals such that each buffer maintains a propagation delay time of 160 ps in accordance with the signals from phase detector PD1 and sends these control signals to each of differential buffers G1-G10.
By means of this feedback control, the delay times of the ten stages of buffers in voltage-controlled delay line VCDL1 are kept uniform. In other words, the period of 160 psxc3x9710 stages=1600 ps is constantly corrected in voltage-controlled delay line VCDL1.
Clock signals having a resolution of 160 ps with respect to the reference clocks are outputted from output terminals OUT through the combination of selections of selectors S1 and S2.
Taking for example a case in which differential buffer G5 is selected by selector S2 as the base state, the output delay of delay locked loop DLL1 at this time will be the delay time 160 psxc3x975 stages 800 ps, if the delay of selectors S1 and S2 is ignored.
In contrast to this base state, the delay becomes 160 psxc3x976 stages=960 ps if differential buffer G6 is selected by selector S2. In other words, delay (phase) is delayed with respect to the total delay of the basic state at a resolution of 160 ps.
Still further delay of the phase of the clock signal can be realized by selecting, by means of selector S2, a differential buffer having a higher number in delay locked loop DLL1. Conversely, an advance in the phase of the clock signal can be realized by selecting, by means of selector S2, a buffer having a lower number in delay locked loop DLL1. Thus, in digital phase control circuit 100 of the prior-art example, the delay (phase) resolution coincides with the propagation delay time (160 ps) of the buffers in voltage-controlled delay line VCDL1, i.e., resolution is determined by the buffer propagation delay time.
However, the prior art has the following problems:
Since resolution is determined by the propagation delay time of the buffers, the propagation delay time of the differential buffers must be decreased (made high-speed) to obtain a more minute resolution. However, there are limits to the buffer delay time, and currently, constructing buffers having a delay time of less than 50 ps is technologically extremely difficult. There is consequently the problem that a resolution smaller than the propagation delay time of a buffer cannot be obtained. Since the amount of phase control that is necessary for clock recovery for high-speed data of 2.5 Gbps is on the order of 40-50 ps, the realization of a digital phase control circuit that is capable of controlling phase at a resolution of less than 50 ps is crucial for realizing the high-speed data communication that is now being sought.
In addition, since feedback control is effected by delay locked loop DLL1 such that the total delay of all buffers in voltage-controlled delay line VCDL1 matches the delay (1600 ps) of half-period portions of the received reference clocks, the number of inserted buffers must be increased to the extent that resolution is decreased. If the resolution is reduced to xc2xc, for example, the number of buffers must be increased fourfold. Accordingly, there is the problem of the increase in circuit current required to increase the buffer speed. There is also the problem that power consumption increases due to the additional circuit current needed for the additional buffers. There is the further problem that the area occupied by circuits increases due to the number of additional buffers.
Delay circuits have been disclosed in Japanese Patent Laid-open No. 18304/97 and Japanese Patent Laid-open No. 18305/97 for freely setting resolution and correcting for variations that arise from fabrication and temperature. These inventions involve delay circuits of a path switching type in which delay times are switched by selecting one of a plurality of paths having different delay times. These delay circuits enable the free setting of resolution, which is produced by the time difference between the delay time of a variable delay gate that is controlled by a first delay time compensation unit and the delay time of a variable delay gate that is controlled by a second delay time compensation unit. In addition, variations in resolution are equalized because the delay time generation circuit and paths are arranged in proximity to each other.
In these delay circuits of the path-switching type, however, there is the problem that the number of selectors and the number of buffers in each stage must be increased to raise resolution. The problems of increase in power consumption and increase in the area occupied by circuits caused by increase in the number of buffers cannot be solved in these path-switching delay circuits.
The increase in the number of selectors in particular creates a problem because the harmful effects caused by deviations in switch timing when switching selectors must be prevented.
In these path-switching delay circuits, moreover, although first and second delay time compensation units for controlling delay times are feedback-controlled by a delay locked loop to correct resolution, the delay processing unit (delay time generation circuit) that actually delays clock signals is not feedback-controlled by a delay locked loop and merely receives delay control signals from the first and second delay time compensation units. Thus, when the delay time compensation unit is separated from the delay processing unit and the feedback system for propagating delay control signals is lengthened, there is the problem that variations in resolution (delay time) are produced by the positions of buffers due to the voltage drop of the control signals.
Finally, in these path-switching delay circuits, both the selectors and the clock frequencies for phase comparison must also be changed in order to change resolution. In concrete terms, the frequency of the reference clocks is changed by a PLL in Japanese Patent Laid-open No. 18304/97 and by a synthesizer in Japanese Patent Laid-open No. 18305/97. In other words, these path-switching delay circuits are analog circuits, and clocks of two different frequencies are generated within the same circuit. As a result, not only is there a danger of generating detrimental resonance, but there is the problem that the circuits cannot be applied to devices having a fixed frequency.
The present invention was achieved in view of the above-described problems in the prior art, and has as an object the provision of a power-saving, compact, high-resolution digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals of a prescribed frequency that can obtain a resolution that is more minute than the propagation delay time of buffers and that suppresses to a minimum both increase in power consumption and increase in the area occupied by circuits.
It is another object of the present invention to provide a digital phase control circuit that is capable of suppressing the number of selectors to a minimum and thus reduce the harmful effects resulting from variations in switch timing of a plurality of selectors.
It is yet another object of the present invention to provide a digital phase control circuit that can operate with high reliability below a fixed frequency and continuously control clock signals at a resolution (delay time) that is accurate and free of variations.
The first invention of this application that solves the above-described problems is a digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to a received reference clock signal of a prescribed frequency, that is provided with:
prescribed numbers of each of two or more types of delay buffers, each type having a different propagation delay time; wherein, by varying the number of each type of delay buffer through which said clock signals are caused to pass, the total delay time of said clock signals is changed in units that are more minute than the propagation delay times of said delay buffers to control the phase of said clock signals.
In this case, the difference in the types of delay buffers refers to the difference in the propagation delay times of the delay buffers.
The number of each type of delay buffer though which clock signals are caused to pass is assumed to include xe2x80x9c0.xe2x80x9d
Thus, the digital phase control circuit of the first invention of this application is provided with prescribed numbers of two or more types of delay buffers, each type having a different propagation delay time, wherein, by varying the number of each type of delay buffer through which said clock signals are caused to pass, the total delay time of said clock signals is changed in units that are more minute than the propagation delay times of said delay buffers to control the phase of said clock signals; and the digital phase control circuit of the first invention therefore has the advantage of making the resolution smaller than the delay time of the delay buffers. The invention therefore has the advantage of allowing a resolution to be obtained that is even more minute than the minute delay time that is the limit of the delay buffers.
Furthermore, there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution, whereby the drawback can be eliminated that the number of delay buffers must be increased in order to obtain smaller resolution.
As a result, the increase in power consumption that accompanies higher speed of the delay buffers and the increase in power consumption that accompanies increase in the number of delay buffers are both avoided, and moreover, the increase in area occupied by circuits, which accompanies increase in the number of delay buffers, can also be avoided. The invention therefore has the merit of enabling a power-saving, compact, high-resolution digital phase control circuit.
Since there is no need to decrease the delay time of the delay buffers (increase speed) in order to obtain a smaller resolution, there is no need for high-level design or high-performance processing to obtain higher speed. As a result, a high-resolution digital phase control circuit can be constructed without increasing the design load or processing load.
Additional advantages include enabling operation below a fixed frequency with high reliability and continuous control of clock signals at a resolution (delay time) that is accurate and free of discrepancies.
The second invention of this application is the digital phase control circuit of the first invention of this application provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives reference clock signals;
a second voltage-controlled delay line that is composed of delay buffers having a second type of propagation delay time concatenated in a plurality of stages;
a first selector that extracts a clock signal from any stage of the first voltage-controlled delay line and outputs this extracted clock signal to the first stage of the second voltage-controlled delay line; and
a second selector that extracts and outputs a clock signal from any stage of the second voltage-controlled delay line.
The third invention of this application is a digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals of a prescribed frequency, and that is provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives reference clock signals;
a second voltage-controlled delay line that is composed of delay buffers having a second type of propagation delay time concatenated in a plurality of stages;
a first selector that extracts a clock signal from any stage of the first voltage-controlled delay line and outputs this extracted clock signal to the first stage of the second voltage-controlled delay line; and
a second selector that extracts and outputs a clock signal from any stage of the second voltage-controlled delay line;
wherein the first voltage-controlled delay line and the second voltage-controlled delay line are each feedback-controlled by a respective delay locked loop;
the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time; and
the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution.
The digital phase control circuit of the third invention of this application therefore has the merit that resolution is smaller than the delay time of the delay buffers because the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time, and the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution. The invention therefore has the merit that a resolution can be obtained that is even smaller than the minute delay time that is the limit of the delay buffers.
In addition, eliminating the need to decrease the delay time of the delay buffers in order to obtain smaller resolution eliminates the drawback that the number of delay buffers must be increased in order to obtain smaller resolution.
The invention therefore has the merits of avoiding the increase in power consumption that accompanies higher speed of delay buffers, the increase in power consumption that accompanies increase in the number of delay buffers, and further, the increase in area occupied by circuits that accompanies increase in the number of delay buffers, thereby enabling a power-saving, compact, high-resolution digital phase control circuit.
Furthermore, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution, there is no need for high-level design or high-performance processing for higher speed. The invention therefore has the merit of enabling the construction of a high-resolution digital phase control circuit without increasing the design load or processing load.
The invention further has the merit of suppressing the number of selectors to a minimum, thereby reducing the harmful effects caused by discrepancies in the switch timing of a plurality of selectors.
The invention is also advantageous because it enables operation below a fixed frequency with high reliability and continuous control of clock signals at a resolution (delay time) that is accurate and free of discrepancies.
The fourth invention of the present application is the digital phase control circuit of the first invention of this application that is provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in h stages and that receives reference clock signals;
i second voltage-controlled delay lines that are each connected to an output of i stages of outputs of the first voltage-controlled delay line and that are each composed of delay buffers having a second type of propagation delay time concatenated in j stages;
a third voltage-controlled delay line that is composed of delay buffers having the second type of propagation delay time concatenated in k stages; and
a selector that extracts a clock signal from any stage of the first voltage-controlled delay line and second voltage-controlled delay lines and outputs this extracted clock signal to the first stage of the third voltage-controlled delay line.
The fifth invention of the present application is a digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals of a prescribed frequency, and is provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in h stages and that receives reference clock signals;
i second voltage-controlled delay lines that are each connected to an output of the i stages of outputs of the first voltage-controlled delay line and that are composed of delay buffers having a second type of propagation delay time concatenated in j stages;
a third voltage-controlled delay line that is composed of delay buffers having the second type of propagation delay time concatenated in k stages; and
a selector that extracts a clock signal from any stage of the first voltage-controlled delay line and the second voltage-controlled delay line and outputs this extracted clock signal to the first stage of the third voltage-controlled delay line;
wherein the first voltage-controlled delay line and the third voltage-controlled delay line are each feedback-controlled by a respective delay locked loop, and a delay control voltage or current for maintaining the resolution that is generated by the delay locked loop that feedback-controls the third voltage-controlled delay line is supplied to each of the delay buffers of each second voltage-controlled delay line;
the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time; and
the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution. Here, h, i, j, and k are natural numbers wherein h and i have the relation that h is equal to or larger than (i-1).
The digital phase control circuit of the fifth invention of this application has the merit that the resolution is smaller than the delay time of the delay buffers because the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time, and the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution. This invention therefore has the merit of enabling a resolution that is smaller than the minute delay time that is the limit of the delay buffers.
In addition, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain smaller resolution, there is no drawback that the number of delay buffers must be increased in order to obtain smaller resolution.
The invention therefore has the merits of avoiding increase in power consumption that accompanies higher speed of the delay buffers, the increase in power consumption that accompanies increase in the number of delay buffers, and further, the increase in area occupied by circuits that accompanies increase in the number of delay buffers, thereby enabling a power-saving, compact, high-resolution digital phase control circuit.
Furthermore, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution, there is no need for high-level design or high-performance processing to obtain higher speed. The invention therefore has the merit of enabling the construction of a high-resolution digital phase control circuit without increasing the design load or processing load.
The invention further has the merit that only one selector is included, thereby eliminating the harmful effects of discrepancies in the switch timing of a plurality of selectors.
The invention is also advantageous because it enables operation below a fixed frequency with high reliability and continuous control of clock signals at a resolution (delay time) that is accurate and free of discrepancies.
In particular, the digital phase control circuit of the fifth invention of the present application has the merits of suppressing variations in the propagation delay times that arise from the positions of the delay buffers and improving the accuracy of resolution because the first voltage-controlled delay line and the third voltage-controlled delay line are each feedback-controlled by a respective delay locked loop, and a delay control voltage or current for maintaining the resolution that is generated by the delay locked loop that feedback-controls the third voltage-controlled delay line is supplied to each of the delay buffers of each of the second voltage-controlled delay lines.
The sixth invention of the present application is the digital phase control circuit of the fifth invention of the present application in which at least one voltage-controlled delay line of the second voltage-controlled delay lines is feedback-controlled by a delay locked loop, and a delay control voltage or current for maintaining resolution that is generated by the delay locked loop that feedback-controls the one voltage-controlled delay line is supplied to each delay buffer of the other second voltage-controlled delay lines to control the phase of clock signals.
Thus, in addition to the merits of the fifth invention of this application, the digital phase control circuit of the sixth invention of this application has the merits of maintaining the propagation delay time of the delay buffers that constitute the voltage-controlled delay lines to a fixed level, suppressing variations in the propagation delay time that are caused by the positions of the delay buffers, and further improving the resolution accuracy.
The seventh invention of the present application is the digital phase control circuit of the first invention of this application provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives reference clock signals;
a second voltage-controlled delay line that is composed of delay buffers having a second type of propagation delay time concatenated in a plurality of stages;
a cyclic delay circuit that is connected to the input side of the second voltage-controlled delay line and that is composed of variable delay buffers, for which the propagation delay time can be switched between the first type of propagation delay time and the second type of propagation delay time, concatenated in a plurality of stages; and
a selector that extracts a clock signal from any stage of the first voltage-controlled delay line and outputs this extracted clock signal to the first stage of the cyclic delay circuit.
The eighth invention of the present application is a digital phase control circuit that outputs one or more clock signals in which phase is controlled at a prescribed resolution with respect to received reference clock signals of a prescribed frequency and that is provided with:
a first voltage-controlled delay line that is composed of delay buffers having a first type of propagation delay time concatenated in a plurality of stages and that receives reference clock signals;
a second voltage-controlled delay line that is composed of delay buffers having a second type of propagation delay time concatenated in a plurality of stages;
a cyclic delay circuit that is connected to the input side of the second voltage-controlled delay line and that is composed of variable delay buffers concatenated in a plurality of stages; and
a selector that extracts a clock signal from any stage of the first voltage-controlled delay line and outputs this extracted clock signal to the first stage of the cyclic delay circuit;
wherein the first voltage-controlled delay line and the second voltage-controlled delay line are each feedback-controlled by a respective delay locked loop;
each delay buffer of the first voltage-controlled delay line is supplied with a first delay control voltage or current that is generated for maintaining resolution by the delay locked loop that feedback-controls the first voltage-controlled delay line and a second delay control voltage or current that is generated for maintaining resolution by the delay locked loop that feedback-controls the second voltage-controlled delay line;
each variable delay buffer of the cyclic delay circuit is supplied with either the first delay control voltage or current or the second delay control voltage or current; and a switch circuit is provided for switching between whether or not the other delay control voltage or current is to be supplied whereby the propagation delay time can be switched between the first type of propagation delay time and the second type of propagation delay time;
the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time; and
the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution.
The digital phase control circuit of the eighth invention of this application therefore has the merit that the resolution is smaller than the delay times of the delay buffers because the time difference between the first type of propagation delay time and the second type of propagation delay time is set smaller than both the first type of propagation delay time and the second type of propagation delay time, and the phases of clock signals are controlled with the time difference between the first type of propagation delay time and the second type of propagation delay time as the resolution. This invention therefore has the merit of enabling a resolution that is smaller than the minute delay time that is the limit of the delay buffers.
In addition, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain smaller resolution, there is no drawback that the number of delay buffers must be increased in order to obtain smaller resolution.
The invention therefore has the merits of avoiding the increase in power consumption that accompanies higher speed of the delay buffers, the increase in power consumption that accompanies increase in the number of delay buffers, and further, the increase in area occupied by circuits that accompanies increase in the number of delay buffers, thereby enabling a power-saving, compact, high-resolution digital phase control circuit.
Furthermore, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution, there is no need for high-level design or high-performance processing to obtain higher speed. The invention therefore has the merit of enabling the construction of a high-resolution digital phase control circuit without increasing the design load or processing load.
The invention affords the additional advantages of enabling operation below a fixed frequency with high reliability and continuous control of clock signals at a resolution (delay time) that is accurate and free of discrepancies.
In particular, the digital phase control circuit of the eighth invention of the present application has the merits of suppressing variations in the propagation delay times that arise due to positions of the delay buffers and improving the accuracy of resolution because each variable delay buffer of the cyclic delay circuit is supplied with one of a first delay control voltage or current and a second delay control voltage or current, and is selectively supplied with the other delay control voltage or current.
In addition, the invention has the merit of enabling the construction of a high-resolution digital phase control circuit having few buffers and selectors by adopting variable delay buffers in which the propagation delay time can be switched between a first type of propagation delay time and a second type of propagation delay time.
Since only one selector is employed, the invention has the merit of eliminating the harmful effects arising from variations in switch timing of a plurality of selectors.
The ninth invention of the present application is a digital phase control circuit of any one of the first to eighth inventions of the present application in which the resolution is set to 1/n (where n is an integer) of the period of the reference clock signals.
The present invention according to the foregoing description has the following advantages:
The present invention is provided with prescribed numbers of two or more types of delay buffers each having a different propagation delay time, and, by varying the numbers of each of the types of delay buffers through which clock signals are passed, controls the phases of the clock signals by changing, in units that are more minute than the propagation delay times of the delay buffers, the total delay time of the clock signals. The present invention therefore has the merit that resolution is even smaller than the delay time of the delay buffers. The invention therefore has the merit of enabling a resolution to be obtained that is even smaller than the minute delay time that is the limit of the delay buffers.
Eliminating the need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution eliminates the drawback that the number of delay buffers must be increased to obtain a smaller resolution.
The invention therefore has the merits of avoiding the increase in power consumption that accompanies higher speed of delay buffers, the increase in power consumption that accompanies increase in the number of delay buffers, and further, the increase in area occupied by circuits that accompanies increase in the number of delay buffers, thereby enabling a power-saving, compact, high-resolution digital phase control circuit.
Furthermore, since there is no need to decrease the delay time (increase the speed) of the delay buffers in order to obtain a smaller resolution, there is no need for high-level design or high-performance processing to obtain higher speed. The invention therefore has the merit of enabling the construction of a high-resolution digital phase control circuit without increasing the design load or processing load.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.


An atomizer cover which is made of glass, plastic, silicone, metal or glass-lined metal for a vaporizing device wherein a side air inlet hole through the atomizer cover is located at a lower portion of the cover, wherein upon assembly of the cover with an atomizer and an atomizer base, the side air inlet hole is located near the atomizer and atomizer base, at or below the atomizer cup level, which creates a vortex of air to increase the efficiency in pulling of the aerosol or vapor from the interior of the atomizer cover, while cooling down the aerosol or vapor which is then inhaled by the user.

The earliest electronic cigarette can be traced to Herbert A. Gilbert, who in 1963 patented a device described as "a smokeless non-tobacco cigarette" that involved "replacing burning tobacco and paper with heated, moist, flavored air." U.S. Pat. No. 3,200,819. This device heated the nicotine solution and produced steam. It was never commercialized.
Hon Lik, a Chinese pharmacist, is credited with the invention of the modern electronic cigarette. In 2003, he came up with the idea of using a piezoelectric ultrasound-emitting element to vaporize a pressurized jet of liquid containing nicotine diluted in a propylene glycol solution. This design produces a smoke-like vapor that can be inhaled and provides a vehicle for nicotine delivery into the bloodstream via the lungs. He also proposed using propylene glycol to dilute nicotine and placing it in a disposable plastic cartridge which serves as a liquid reservoir and mouthpiece.
The electronic cigarette ("e-cigarette") continued to evolve from the first generation three-part device. In 2006, the "cartomizer" (an amalgamation of cartridge and atomizer) was invented by British entrepreneurs Umer and Tariq Sheikh of XL Distributors. This is a mechanism which integrates the heating coil into the liquid chamber. The new device was launched in the United Kingdom in 2007 and is now widely adopted by the majority of 'cigalike' brands. The grant of the United Kingdom patent for the "cartomizer" was made in February 2013. UK Patent No. GB 2,465,247.
Standard vaporizing devices are comprised of four main parts: the battery, the atomizer, the atomizer base, and the atomizer cover. The atomizer has a bowl (called atomizer bowl or ceramic bowl), and the atomizer base connects to the battery. The atomizer base attaches the atomizer to the battery and provides the power bridge from the battery into the atomizer. When a user inhales or when user presses a button, a microprocessor signals the battery to charge the atomizer.
Vaporizing devices work by using a battery to power a small heating element in the atomizer which heats essential oils, and/or solid concentrates such as wax and dry herbs. The tip of the vaporizing device is placed in the user's mouth. The user's inhale breath allows air to flow through the atomizer which in turn creates vapor or an aerosol out of the essential oils and/or solid concentrates that are heated and vaporized by the atomizer.
In standard vaporizing devices, to create this aerosol or vapor, air flows through the center of the atomizer bowl, and this air typically travels from between the battery and the atomizer base, or through the side of the base, to a hole in the center of the atomizer base, to the atomizer through the center of the atomizer bowl. The problem with this is that, usually, with very little use, the hole which runs through the center of the atomizer bowl gets clogged up by oils or solid concentrates, or burnt remnants thereof, thereby blocking the hole and obstructing or preventing air flow through the hole. Many times oils will leak through this hole in the atomizer down to the top of the battery where eventually this oil will seep into the battery and cause failure of the battery.
Thus, there is a need for improvement on the efficiency of the current method for delivery of the aerosol or vapor to the user. The present invention provides a new way for air to enter the vaporizing device and more effectively flow over the atomizer to provide a more efficient manner for the aerosol or vapor to reach the user's mouth, while simultaneously cooling the aerosol or vapor during delivery. This vortex also cools down the atomizer allowing for a hotter-running atomizer to work.


An electrical interface distribution unit (10) and method for interconnecting signal cables (60, 62, 64) in a cable housing (24) within a wall defined by sheets of material (16-18) spaced apart by studs (20) to define an interior wall volume wherein large numbers of cables must fit in a small volume interiorly of the wall and be interconnected by modules (70, 80) for distribution of input and output signals in a building.

With the advent of electronics utilized in building structures, including offices, factories, and homes, the need to mount and accommodate cables for television, data, telephone, and security or sensor devices has increased. In some instances, the cables may be wall mounted or surface mounted, but in general, such mountings are aesthetically unacceptable, and in certain instances, practically undesirable by virtue of damage to such cables by the normal traffic of the buildings, including the movement of furniture, equipment, and the like. Most wall constructions include the use of studs which are nominally of 2".times.4" dimensions over which is applied drywall or paneling to result in a hollow space or volume between the sheet material defining the walls. As can be appreciated, this volume is limited in depth. Traditional practice has been to mount wall boxes or housings to accommodate cable termination to devices, to rough-wire the building while one wall is removed, through the interior wall volume, through apertures made in studs and to leave an excess of cable which may be trimmed during final installation. The practice extends to pulling the cable through the box or housing, clamping the cable to the box and terminating it to a device and then shoving it back into the box. With respect to prior practice, utilizing one or two or even three power cables, such as the so-called "Romex" cable, the ends, as terminated, can be readily, or sometimes with difficulty, fitted into a box by folding and bending, with the excess cable needed to effectively terminate the cable removed prior to termination, reducing the volume of cable which must be stuffed into the box.
With respect to applications wherein far more than two or three cables must be terminated, as for example, in the so-called distribution of television or data cables, which are coaxial in nature, and telephone cables which carry numerous wires in numbers of cables to be terminated, a problem is created. One solution employed in the prior art utilizes a fairly large box or housing of substantial interior volume to accommodate the "head end" and other cables for upstream and downstream distribution of signals through distribution cables.
Patent Application Ser. No. 07,618,766, filed Nov. 27, 1990, and directed to a convenience electrical outlet assembly represents one solution wherein power and signal outlets are combined and employed using a hybrid ribbon cable for an intelligent wiring system for a building. There, a multi-function ribbon cable is attached to a housing which has receptacles into which terminals attached to modules are plugged to effect a termination. A special module is used to accommodate data or communication cables inserted into the housing, which is fitted within a hole in the sheet material of a wall. There also, the numbers of coaxial and telephone cables are relatively limited inputs to a receptacle associated with such device. U.S. Pat. No. 4,756,695 granted Jul. 12, 1988 and drawn to a local area network interface accomplishes a similar function with respect to telephone cables. There, a wall box is made to accommodate connectors terminated to cable and plugged therein to join modules accommodated by the wall box.
The present invention has as an object the provision of a cable distribution unit and method of installation wherein relatively large numbers of cables can be accommodated in a relatively small volume within the sheet material defining a wall structure of a building. The invention has as a further object the provision of a housing and mounting arrangement which is easy to use and reduces the amount of labor for the interconnection of cables providing distribution in a building structure. Still a further object is to provide a low cost solution to the termination and distribution of cable which can readily fit within the wall of a building structure.


A pointing device for controlling the positioning, movement and operation of a cursor on the display screen. Specifically, there is a pointing stick assembly using resistive material strain gages mounted on the sides of a shaft or stick for sensing when the stick is experiencing stresses and strains therein because of an applied force to the stick. The pointing stick has a stick supporting collar securely attached to a substrate. The collar extends from the substrate to approximately around the location of the strain gages. The collar may have a beveled surface located between opposing surfaces of the collar and shaft.

1. Field of the Preferred Embodiments(s)
This invention generally relates to a pointing device for controlling the positioning, movement and operation of a cursor on a display screen. Specifically, there is a collar mounted pointing stick with a resistor based strain gages mounted thereon.
2. Description of the Related Art
Various devices are well known for controlling cursor movement over a computer display screen of a computer and for signaling a choice of computer command identified by the position of the cursor on the display screen menu. One such device is a "mouse" which has a ball on its underside rolled over a horizontal surface, with the x- and y-axis components of movement being sensed and transmitted through a connecting cable to a serial input port of the computer. The signal to the computer is varied by the amount and direction of movement of the mouse ball, and causes the cursor on the display screen to have a corresponding movement. Two "mouse" or "click" buttons located on the top of the mouse at the forward end permit the computer operator to enter a selection or other command to the computer (the command typically being shown by the position of the cursor on a displayed menu) upon pressing one or the other or both buttons, depending upon the software associated with the device. Such a device, which is separate from the computer console and keyboard and requires a connection to a computer port, requires a flat, horizontal surface, and for operation of the mouse, the computer operator must completely remove one hand from the computer keyboard.
Another cursor controlling the signaling mechanism is a "joystick" which like the mouse is completely separated from the computer console and keyboard. The joystick is typically an elongated stick that extends upwardly from a base connected to the computer console by means of a cable. The joystick is operated by tilting the upstanding stick in various directions to cause the cursor or other display element to move in a direction and usually at a speed corresponding to the direction and pressure exerted on the stick by the computer operator. The operation of a joystick, however, frequently requires that both hands be removed from the computer keyboard, one hand to hold the base while the other manipulates the joystick. A "click" button is usually located on the joystick. Although a mouse or a joystick can be used with a portable "laptop" or "notebook" size computers, such devices are cumbersome, must be carried separately and connected to the computer before use, and are not suitable for operation during travel.
Another type of cursor controlling device is a "trackball." This device, which in essence is an inverted mouse, includes a rotatable ball mounted within a housing. The ball is rotated by a finger, thumb or palm of the computer operator, and the x- and y-components of movement are sensed and input into the computer to cause corresponding movement of the cursor across the display screen. "Mouse" or "click" buttons are usually located on the trackball housing, although with some models the selection signal is input by pressing the "enter" key on the standard keyboard. This type of pointing device has been found useful with portable computers because it can be temporarily affixed to one side of the computer case for manipulation by one hand of the computer operator. However, though trackball devices can be removably attached to the computer case, they still require attachment before use and removal after use and they do not have an ergonomically positioned set of "click" buttons.
Manufacturers of portable laptop computers, recognizing the need for placing the cursor controlling device in a permanent and more convenient location, installed a small stubby, button-like joystick centrally around the keys of the computer keyboard, specifically at the juncture of the "g," "h" and "b" keys of the standard "QWERTY" keyboard. The joystick, also known as a pointing stick, was sensitive to lateral pressure, the amount and direction of which were sensed and input into the computer to cause movement of the cursor, and the speed and direction of cursor movement corresponded to the amount and direction of pressure on the joystick. That manufacturer also provided two upwardly extending "mouse" or "click" buttons immediately below the space bar.
Despite the advantages of each type of cursor control, none have been easily adapted to personal digital assistants (PDAs), palmtop computers, and the like. Specifically, current pointing stick designs are too tall to apply to PDAs. Uniquely, one major current manufacturing technology requires strain gages to be located on the pointing stick. Strain gages are devices that sense the amount and location of applied pressure placed upon the pointing stick. The sensed pressure creates electrical output signals used to direct the cursor on a display device. The maximum amount of created strain on the pointing stick is at the base of the pointing stick where it attaches to the supporting substrate. Thus, the ideal location for a strain gage is at the maximum strain point - at the base of the stick. However, current manufacturing capabilities place strain gages a required distance above the previously attached substrate surface. Therefore, the minimum height of the stick is fixed so that enough strain can be created at the location of the elevated strain gages for proper operation. This minimum height far exceeds the height maximum for application of a pointing stick onto a PDA keyboard. Based on this strain gage minimum height location criteria, the pointing stick cannot be shortened more than present designs for proper operation. Therefore, there is a need for a pointing stick, which uses side mounted strain gages, that is short enough to fit into a PDA keyboard.
3. Description of Related Art
Examples of patents related to the present invention are as follows, and each patent is herein incorporated by reference for the supporting teachings:
U.S. Pat. No. Re. 35,016, is a three-axis force measurement stylus.
U.S. Pat. No. 5,489,900, is a strain sensitive columnar transducer for a data entry keyboard contains a column upstanding from the keyboard.
U.S. Pat. No. 5,473,347, is a computer pointing device for controlling the positioning, movement and operation of a cursor on the display screen of a computer.
U.S. Pat. No. 5,407,285, is an apparatus for use in a computer keyboard for cursor control is disclosed.
U.S. Pat. No. 5,521,596, is a sensor device placed either underneath a key cap or a key on a keyboard or between two keys on a keyboard so that cursor movement may be carried out from the keyboard itself.
U.S. Pat. No. 4,876,524, is an isometric control device or the like of the type having an elastic beam and strain gauges attached to the surface of the beam characterized by at least a first group of three strain gages each having an operative axis thereof inclined with a single predetermined angle with respect to the main axis of the beam, and the strain gauges disposed at a first predetermined level along the beam.
U.S. Pat. No. 4,680,577, is a multipurpose key switch for controlling cursor movement on a CRT display and for character entry includes a key cap that moves laterally to provide cursor control and that moves vertically for character entry.
The foregoing patents reflect the state of the art of which the applicant is aware and are tendered with the view toward discharging applicant's acknowledged duty of candor in disclosing information that may be pertinent in the examination of this application. It is respectfully stipulated, however, that none of these patents teach or render obvious, singly or when considered in combination, applicant's claimed invention.


In a conventional optical device which mounts a semiconductor light emitting element, the processing is difficult and a manufacturing process cost is expensive because of the necessity of forming via holes in a substrate.

1. Field of the Invention
The present invention relates to an optical device which mounts a semiconductor light emitting element on a substrate including a light waveguide path, a method of manufacturing the same, an optical module, and an optical transmission system.
2. Related Art of the Invention
FIGS. 15 (a) and (b) show a conventional optical transmission module 160 mounting a semiconductor light emitting element 152 on a glass substrate 151 including a waveguide path 161. When the semiconductor light emitting element 152 mounted on the glass substrate 151 is an edge emitting type element and a high speed operation is required, it is arranged on the glass substrate 151 so that a surface which opposes an active layer junction surface (emitting portion) 155 of the semiconductor light emitting element 152 and has the smallest distance from the active layer junction surface 155 (i.e., active layer proximity surface 154) of the element faces upper. Via holes 162 are then formed in the glass substrate 151, heat generated in the semiconductor light emitting element 152 is radiated to a metal heat sink 153 arranged on the lower side of the glass substrate 151 through a conductive paste 163 which fills the via holes 162, and a common ground potential is simultaneously obtained.
In this case, in order to increase a heat radiation effect from the semiconductor light emitting element 152 to the heat sink 153, it will be desirable to reduce thermal resistance (i.e., increase thermal conductivity) of a thermal path to the heat sink 153 from the semiconductor light emitting element 152. That is, considering the via holes 162 and the conductive paste 163 which fills them to be a thermal resistance element, it will be desirable to decrease the glass substrate 151 in thickness where the via holes 162 are formed (i.e., shorten the thermal resistance element in length), or to increase the diameter of the via holes 162 in width (i.e., increase the diameter of the thermal resistance material in width). However, there is a limit to decreasing the glass substrate 151 in thickness since the integrity of the glass substrate 151 of its own would decrease in strength. In addition, there is also a limit to increasing the diameter of the via holes 162 in width since the glass substrate 151 would decrease in strength. Thus, the heat generated from the semiconductor light emitting element 152 has been radiated to the heat sink 153 through a plurality of the via holes 162 not by increasing the diameter of the via holes 162 in width but by forming a number of the via holes 162 on the glass substrate 151 as illustrated in FIG. 15 (See Japanese Patent gazette Laid-Open No. 2002-131593. The disclosure of the above document is incorporated herein by reference in its entirety)
However, forming a number of the via holes 162 with a high aspect ratio in the glass substrate 151 as described above has been a factor in increasing the cost because of manufacturing difficulty and an increase of manufacturing process. In addition, there have been cases where even when a number of the via holes 162 in the glass substrate 151 have been formed, the thermal resistance to the heat sink 153 from the semiconductor light emitting element 152 has not been able to be reduced, so that the heat radiation to the heat sink 153 from the semiconductor light emitting element 152 has not been enough. In that case, heat radiation from other heat radiation paths (e.g., heat radiation from peripheral air) must be depended on, in addition, the speed of heat transfer from the semiconductor light emitting element 152 to the heat sink 153 is not high enough, so it is necessary to increase the heat sink 153 by one semiconductor light emitting element 152 in size, therefore, the heat sink 153 having large area has been needed in order to manufacture one optical device, further, increasing packaging density on the glass substrate 151 corresponding thereto has not been achieved. In addition, forming a number of the via holes 162 in the glass substrate 151 reduces the glass substrate 151 in strength, resulting in upsizing the optical device and increasing the cost corresponding thereto.

Optical device, method of manufacturing the same, optical module, optical transmission system

Abstract: An optical device comprises a laser diode which needs heat radiation, a glass substrate which is integrally molded into a mold glass for arranging the laser diode, a metallic heat sink arranged at an edge of the glass substrate for radiating heat generated from the laser diode, wherein an active layer proximity surface of the laser diode is arranged to oppose the heat sink, both of them are connected with a conductive paste through a lateral groove formed in the glass substrate.


A liquid dispensing container includes a transparent or translucent vial. A base is secured to the vial and contains a light source and a battery source. The light source being monochromatic or outputting multiple colors in sequence. A switch is provided for selectively forming electrical engagement between the light source and the battery source. A printed circuit board interspersed between the light source and the battery source affords optional subcircuits including a timer, step-up voltage, or step-down voltage capabilities, or light source output color modulation.

Bottles, and in particular bottles designed as perfume containers, afford a user with an added visual stimulus to accompany the tactile and olfactory aspects of perfume application. The added size and/or volume displacement of conventional illuminated perfume bottles has limited the acceptance of such bottles. U.S. Pat. No. 6,525,402 is representative thereof. Thus, there exists a need for an illuminated perfume bottle where the lighting components are compact and do not displace contents volume.


A method of manufacturing a drum assembly associated with a digital betacam video tape machine is disclosed. The method includes providing a helical scan drum assembly having a stationary upper drum, a stationary lower drum and a plurality of rotating read/write heads disposed between the stationary upper and lower drums. The rotating read/write heads reading and writing digital information to and from a tape. The method further includes inserting air grooves in the outer peripheral surface of the upper drum. The air grooves are configured to reduce sticktion between the tape and the outer peripheral surface of the upper drum when the tape is moved around the outer peripheral surface of the upper drum. The method additional includes mounting an adjustable band to the outer peripheral surface of the lower drum. The adjustable band is configured to guide the tape around the drum assembly in accordance with helical scans when the tape is moved around the outer peripheral surface of the upper drum.

The present invention relates to video tape machines. More particularly, the present invention relates to improved techniques for manufacturing and/or refurbishing a drum assembly that is used in a video tape machine.
Videotape machines that employ drum assemblies including rotating record/reproduce heads are well known. In such machines, a recording medium in the form of tape is wrapped around the drum assembly so that rotating record/reproduce heads can record and reproduce. In general, the heads rotate while the tape is moved (or held stationary) around the drum assembly. The heads may include video heads, audio heads and control track heads and in cases where video editing is needed may also include time code heads, audio confidence playback heads, audio-only erase heads, flying erase heads, etc. The drum assembly generally cooperates with loading mechanisms, reel hubs, tape guides, sensors, erase head, capstans to form a mechanical transport assembly that provides the mechanical interface between the video tape machine electronics and the information recorded on the tape.
Videotape machines can be categorized using several criteria, including tape width (ranging from ¼ in up to 2 in), style (open reel and cassette), scanning method (transverse and helical scan) and recording format (e.g., U-Matic, B, C, Betacam, Digital Betacam, DV, etc.). Most commercially successful videotape machines are based on helical scanning methods. In helical scans, a slow moving tape is helically wrapped 180 degrees around the drum assembly that houses the rotating record/reproduce heads. The tape is positioned at a slight angle to the equatorial plane of the rotating record/reproduce heads. As such, the recorded tracks run diagonally across the tape from one edge to the other. Recorded tracks are parallel to each other but are at an angle to the edge of the tape. There are many recording formats that use helical scanning methods. In the C recording format (analog), the videotape machines use 1 inch oxide tape in open reels. In Digital Betacam recording format (digital), the video tape machines use ½ inch metal tape in cassettes. Digital Betacam is generally preferred over C recording formats because of its digital nature and the fact that it can be used for High Definition.
FIG. 1A illustrates a video tape machine 2 that includes a mechanical transport system 3 that is enclosed by a housing 4. By way of example, the video tape machine may correspond to a Digital Betacam editing recorder such as the DVW, DNW, HDW models manufactured by Sony of Japan. FIG. 1B illustrates the mechanical transport system 3 with a loaded cassette 5. By way of example, the mechanical transport system 3 may correspond to the mechanical transport system used in the DVW-500A model Digital Betacam editing recorder manufactured by Sony of Japan.
As shown in FIG. 1B, the mechanical transport system 3 includes a tape running system 6 having various components 11 including guides, capstan, pinch roller, tape cleaner and the like. The mechanical transport system 3 also includes stationary heads 8 and rotary heads 9 that are disposed in a drum assembly 10. The tape running system 6 is configured to direct a tape 7 around the drum assembly 10 so that the tape 7 engages the rotary heads 9 for recording and reproducing on the tape 7. As shown, the tape running system 6 includes at least an entrance guide 12A for introducing the tape 7 to the drum assembly 10 and an exit guide 12B for removing the tape 7 from the drum assembly 10. As should be appreciated, while the tape 7 is moved around the drum assembly 10 by the tape running system 6, the rotary heads 9 rotate at great speeds reading data from the tape 7 and writing data to the tape 7. Although not shown, the drum assembly is in a tilted position for helical scanning.
Referring to FIGS. 2A & 2B the drum assembly 10 will be described in greater detail. FIG. 2A is a perspective view of the drum assembly 10, and FIG. 2B is a side elevation view, in cross section, of the drum assembly 10. As shown, the drum assembly 10 includes an upper drum 12, an inner drum or scanner 14, a lower drum 16, a drum support 18, a spindle assembly 20, an upper base 22 and a lower base 24. The inner drum 14, which is disposed inside an opening 26 formed in the upper drum 12, is attached to the spindle assembly 20. The inner drum 14, among other things, includes a plurality of record/reproduce heads 9 configured for video recording. The record/reproduce heads 9 are disposed in a gap formed between the upper and lower drums 12 and 16. As should be appreciated, the record/reproduce heads 9 are rotated via the spindle assembly 20 to accomplish any recording or reproducing tasks. The inner drum 14 also includes a cavity 32 for allowing a slip ring assembly (not shown) to be positioned therein. Slip ring assemblies carry electrical signals between the rotating heads and other equipment with which the rotating head has relative motion. By way of example, representative slip ring assemblies may be found in co-pending patent application Ser. No. 09/721,436, which is titled "Slip Ring Assembly For Use In a Video Recorder" and filed on Nov. 22, 2000, and which is herein incorporated by reference.
The lower base 24 is structurally coupled to the upper base 22 and the upper base 22 is structurally coupled to the lower drum 16. The drum support 18 is configured to hold or support the upper drum 12 relative to the lower drum 16. As should be appreciated, the tape moves over the outer peripheral surfaces 12A and 16A of the stationary upper and lower drums 12 and 16 while the rotary heads 9 rotate in order to record or reproduce. The lower drum 16 includes a shoulder 28 for supporting the tape and guiding the tape along the outer peripheral surfaces 12A and 16A of the upper and lower drums 12 and 16 adjacent the rotary recording/reproducing heads 9. As shown in FIG. 3A, the shoulder 28 is angled about the periphery of the lower drum 16 because of the helical scanning method used in the videotape machine (e.g., enters at high point and exits at low point). The shoulder 28 is also radially tapered so as force the tape towards the surfaces 12A and 16A of the upper and lower drums 12 and 16 thereby providing better contact with the heads 9. In some cases, sticktion may be encountered when the tape is moved across the upper drum 12. In order to reduce the sticktion, the upper drum 12 includes a pair of bumps 30 that extend past the outer peripheral surface 12A of the upper drum 12 as shown in FIG. 3B. The bumps 30 provide an air gap between the top edge of the backside of the tape 7 and the outer peripheral surface 12A of the upper drum 12 (the air gap helps to reduce sticktion between the tape and the upper drum).
Referring back to FIGS. 2A and 2B, the spindle assembly 20 includes a spindle 46 and a spindle pad 48. The spindle 46 is rotatably coupled to the upper base 22 via a set of bearings 52 and powered by a motor (not shown) housed within the lower base 24. The motor is typically configured to rotate the spindle 46 along an axis 54 at speeds up to 10,000 revolutions per minute (rpm). One end of the spindle pad 48 is attached to the spindle 46 while the opposite end is attached to the inner drum 14. The spindle pad 48 includes a guide post 33 and a mounting flange 50. As shown, the guide post 33 extends into a portion of the cavity 32, and the mounting flange 50 provides a mounting surface for securing the inner drum 14 thereto. Furthermore, the guide post 33 includes a guide hole 34 configured for supporting a slip ring assembly (not shown).
Unfortunately, the design and implementation of the drum assembly 10 leads to problems which may shorten part life and the proper functioning of the video tape machine in which it is used. For example, one problem associated with the above assembly is that the upper and lower drums 12 and 16 include polished aluminum outer peripheral surfaces 12A and 16A. The polished aluminum outer peripheral surfaces 12A and 16A, which contacts the tape 7, is not very effective at preventing sticktion problems, and it is soft material that is suceptable to wear. Referring to FIG. 3A, the shoulder 28 that guides the tape 7 around the drum assembly 10 may wear as the tape 7 is moved across its surface. The wear can lower the position of the shoulder 28 thus shifting the position of the tape 7 relative to the heads 9. This may make it difficult for the heads 9 to record or reproduce. The contact between the tape 7 and the outer peripheral surfaces 12A and 16A can also produce undesirable particles 60 (from both the shoulder and the tape). These particles may adhere to the backside or data side of the tape 7 thus causing signal dropout problems. The particles 60 may also build up on the shoulder 28 possibly shifting the position of the tape 7 relative to the heads 9 (e.g., pushing the tape away from the surface) or making it more difficult for the tape 7 to move along the shoulder 28. The taper in the shoulder 28 may further trap particles 60 on the shoulder 28, i.e., no place for the particles to go. All of these problems may make it difficult for the heads 9 to record or reproduce. Another problem associated with the drum assembly is that the drums are cold plated (e.g., chemical process that occurs at the molecular level) to help protect the surfaces of the drum. The cold plating process, however, distorts the shape of the drum. For example, the upper drum may be distorted into an egg shape (e.g., the diameter is not uniform). As should be appreciated, distortions such as these may make it difficult for the heads 9 to record or reproduce. Another problem associated with the drum assembly 10 is that the bumps 30 (as shown in FIG. 3B) tends to cause tape wear as for example shedding that produces undesirable particles 60. It may also make it difficult for the heads 9 to record or reproduce since its only located at the top edge of the tape 7 (e.g., produces a deformed signal such as spikes).
In view of the foregoing, there are desired improved methods and apparatuses for manufacturing and/or refurbishing a drum assembly used in a video tape machine such as the DVW, DNW, HDW models manufactured by Sony of Japan.

Method of manufacturing a drum assembly associated with video tape machine


Machine-readable media, methods, apparatus and system for detecting a data access violation are described. In some embodiments, current memory access information related to a current memory access to a memory address by a current user thread may be obtained. It may be determined whether a cache includes a cache entry associated with the memory address. If the cache includes the cache entry associated with the memory address, then, an access history stored in the cache entry and the current memory access information may be analyzed to detect if there is at least one of an actual violation and a potential violation of accessing the memory address.

Bugs in a parallel program, such as a multi-threaded program and a multi-processed program, may be one of the most difficult to test and diagnose among all software bugs. There are some types of bugs in the parallel program, such as a data race and a data access atomicity violation. The data race may, for example, occur when two threads access, at least one of which being a write, the same data in a memory concurrently without proper synchronization. The data access atomicity violation may, for example, occur when a code region is executed in a non-atomic way in opposite to an expectation of executing it as an atomic region. Algorithm for the data access atomicity detection may depend on an observation called access interleaving invariant that is a good indication of programmers' assumptions about the atomicity of a certain code region.

Method and apparatus for detecting a data access violation


A chemical substance total management system and a chemical substance total management method which can easily manage amounts and release destination of managing substances. The chemical substance total management system includes a material composition database of component composition information of material or product in a form of database, a managing substance database in a form of a list of substance requiring management, for identifying substances constituting the material or product on the basis of the material composition database and identifying substance required management on the basis of the managing substance database for managing chemical substance contained in the material handled by a business entity or product. The system further includes release coefficient database storing weight ratio data in each transfer and release destination per the identified management required substance in a form of database.

The present invention relates to a chemical substance total management system and a chemical substance total management method for managing chemical substances contained in materials handled by business entities.
In various materials currently commercialized, several of hundreds kinds of chemical substances having significant impact to the environment are contained. When business entities handle the materials in the processes of manufacturing, transportation, storage and so forth, it has been required to know an amount of the chemical substances that is moved, an amount of chemical substance that is released to the atmosphere, soil and/or water, and an amount of chemical substance that has been provided to the market in a form contained in the products. Therefore, the business entities have to manage the chemical substances to be handled by themselves. Hereinafter, the chemical substances to be handled by the business entities will be referred to as "managing substance".
Therefore, legal system has been started to require the business entities to report quantative data of releasing and transferring the managing substances in factories, business offices or in business enterprise to the country and/or the autonomous body to estimate environmental impact of the overall country.
The conventional data collecting system has a function for inputting basic data of the managing substances per division and/or process and aggregately tabulating per unit of superior organization (business office, company). The reason is that as effective document, only this result is required.
Such prior art has been discussed in Special Edition, "Environmental Resource" of December, 1999.
For instance, it is assumed that 10 tons of xylene is released to the atmosphere as a result of aggregation in a business office. This value does not help in identification of process and in identification of material to be a cause of emission and thus does not contribute for reduction of release amount as final goal.
Also, mere aggregation of release amount of the management substance may not provide necessary data for risk communication which comes to attach importance thereto recently. In the risk communication, it is important to ease apprehension of residents concerning releasing of the managing substance. For this purpose, it is necessary to perform investigation into how the managing substance is released with identifying process and material and to have a communication with reference to feature of the process including height of the exhaust flue, security data of the material.
In aggregation of chemical substance management information, even when chemical substance information, namely composition information per product is obtained, the use amount used in own factory has to be analyzed into product depositing component, atmosphere releasing component, water releasing component, waste disposing component, soil releasing component and so forth. For this purpose, there is a task to manage managing substances, release amounts of respective managing substances, and release destinations of respective managing substances.
On the other hand, since it is unknown what substance will appear as managing substances, it is expected objective managing substances should be varied or modified from time to time. Namely, it is necessary to defend ourselves from danger of future contamination.
On the other hand, among information to be used in chemical substance management, there is a little information which can be judged by one business entity alone, there are information requiring versatile decision of country, autonomous bodies, specialized agencies and so forth, and information which the product manufacturer, material manufacturer has to make product information open. Namely, it is important to make these chemical substance management information common to interested parties.
On the other hand, considering flow of the products in the market, the products may flow in such a manner from material˜raw material treatment˜assembling process˜transportation˜sale˜consumer˜recycling business entity˜waste disposal. The chemical substance management information has to also be circulated through the same route. Wide variety of business entities, e.g. large size company, middle size company, small size company, individual, autonomous body, are associated with the circulation cycle. Unless information is commonly owned by all parties associated with the circulation cycle, highly accurate chemical substance management cannot be realized.
Furthermore, each of the parties associated with the information circulation cycle has to perform highly accurate chemical substance management.

Chemical material integrated management system and method thereof


Apparatus are provided, including a document application and a bleed creation mechanism. The bleed creation mechanism includes an image extender to automatically determine non-blank extended image information based on a location of a blank perimeter area of a page description language (PDL) file. The image extender further populates the blank perimeter area with the non-blank extended image information.

Some printed media sheets (sometimes referred to herein as "edge-to-edge printed media sheets") contain content that extends up to one or more edges of the sheet. For example, an image, a pattern, and/or text on a printed surface of a given rectangular sheet may extend, without distortion or interruption, up to all four edges of the given sheet. In other words, these printed media sheets which may be professional documents such as color documents, may contain image content that runs to the edge of a sheet of paper, and visually "bleeds" off the page.
Printing devices typically have problems printing to the edge of the paper. Printing devices may exhibit image defects near sheet edges, including paper curling near the sheet edge. Edge-to-edge printed media sheets are produced with such printing devices despite their limitations in printing near the sheet edges. This is done by printing oversized documents, which are then trimmed to the intended final dimensions.
Before printing an oversized document, a document designer typically designs the document's content virtually—e.g., using software to create a file describing the sheet to be printed and the image content in relation to the sheet. For example, an oversized page may be designed containing an image area that is slightly oversized (e.g., in some instances ⅛th of an inch beyond each edge of the desired (target) edge-to-edge printed media sheet), and trim marks may be added to indicate the intended edges of the target sheet. Page layout programs exist for this purpose, and include QuarkXpress and Adobe InDesign. These programs have features that allow for the creation of pages with bleeds.
A problem may arise when a document designer creates one or more virtual pages with image content that runs to the edge of the paper, but does not provide a slightly oversized bleed image or the associated trimming marks. This can occur, for example, if the document was designed with a composition tool that does not support bleeds, or if an existing hardcopy document is being reproduced. Print producers faced with this problem frequently compensate for the lack of bleed image by scaling up the page content to achieve a slightly oversized image. This solution may present problems, for example, when the page content has information near the edges of the paper which will be lost upon trimming, or if the page has size-sensitive information such as logos or graphic elements whose size needs to be maintained constant.


The disclosed method creates a source object for each source language element parsed by the compiler and associates each such created source object with objects created from source language elements to produce source-mapped objects. Next, the source-mapped objects are transformed into corresponding machine-instruction objects and a binary file of the machine-instruction objects is created by: i) adjusting a source data object to a source object associated with a machine instruction object, thereby identifying a lowest level of inlining where the call history of the source object differs from the call history of the previous source object to which the source data object was adjusted; ii) if the source data object identifies no differences from the previous source object, then continuing at step i) for the next machine instruction; and, iii) for each level of the call history beginning with the level returned in the preceding step and continuing through the last level, putting information obtained from the source data object in a source table stored in the binary file.

A compiler is a computer program that reads source files of another program to produce a binary file, which is required for execution by a computer. The source files describe the program using a computer language such as C, C++, COBOL or the like. The binary file produced by the compiler contains a series of binary machine instructions for a particular type of computer. Moreover, the compiler generates diagnostic messages when it detects errors in the source files. A compiler is distinguished from an assembler by the fact that each input statement does not, in general, correspond to a single machine instruction or fixed sequence of instructions. A compiler may support such features as automatic allocation of variables, arbitrary arithmetic expressions, control structures such as FOR and WHILE loops, variable scope, input/output operations, higher-order functions and portability of source code.
A source file can contain compiler directives that cause other source files to be included. A compilation unit is a single source program file given to the compiler, plus all the source program files included directly or indirectly by that file. A binary file can contain machine instructions from one or more compilation units, and a compilation unit can come from multiple source files. Sometimes the machine instructions of a single compilation unit are saved in a separate binary file, called an object file. Object files are then combined by a linker to create a final binary file.
A compiler that has been programmed with the use of objects must relate its objects (representing a program being compiled) to locations within the source files. The parsing phase of compilation creates objects representing program elements, such as functions, statements and expressions. The code generation phase of compilation involves generating machine instruction objects for the program element objects. Locations in the source files must be captured and maintained for the program element objects and then passed on to the respective machine instruction objects. A source location usually consists of a source file name and a line number within the source file.
The compiler uses the source locations of its objects in at least two cases. First, the compiler shows a source location when issuing a diagnostic message to inform the compiler's user of an error location. Secondly, the compiler places a table in the binary file with the machine instructions mapping the instructions to their corresponding source locations. This table is used for debugging when the machine instructions are loaded from the binary file into a computer system's memory and executed. If processing of the machine instructions is interrupted, a debugger or other diagnostic software can use the table to find the source location that corresponds with the current point of execution of machine instructions. If call instructions are used, the debugger or other diagnostic software can also use the table to find the source locations of the series of calls that arrived at the interrupted machine instruction. The list of source locations, starting with the point of interruption followed by the source locations of the calls that arrived there in order of the most recent call to first call, is referred to as a call history.
One type of prior art compiler processed a source file in a single pass by reading the source file and generating machine instructions at the same time. Typically included in this type of one-pass compiler are running variables holding the current source file name and line number, which are used to correlate between the original source file and the generated binary code. Such a straightforward correlation is adequate for a one-pass compiler but is too simplistic to cover most compiler requirements of today.
Many compilers today scan source files to create objects representing program elements. The compiler then makes multiple passes over the objects in order to verify correctness, find optimization opportunities and generate machine instructions. Some compilers then make one or more additional passes over the machine instructions to find still more optimization opportunities. Optimizations cause objects to be sometimes moved in their respective order and sometimes replaced by other new objects. These relocations and replacements happen to both program element objects and machine instruction objects. The prior art for relating machine instructions to source locations in typical multipass compilers uses two instance variables in each object. The first variable points at a source file name using either a memory address or an index into a table of names. The second variable holds a line number within the named file. These two variables, which must be set as objects, are created while scanning source files and then copied to other objects created in later passes, such as for optimization and code generation. In some compilers the two variables are combined into one variable that holds an index into a list of ranges of line numbers with source files.
A common and important optimization called "inlining" causes a major problem with the way source locations are managed by the prior art compilers. The term "inlining" as used herein shall mean the replacing of a function with an instance of the function's body. When a compiled program is interrupted, the locations of call instructions are used to look up source locations to build a complete call history. Inlining causes call instructions to be removed. A compiler copies the objects representing the body of an inlined function in place of a call on the function. Using the method of the prior art, each copied object can be related to only one source location. So the compiler can preserve either the location of the call or the location within the inlined function, but not both. The result is that a call history reported by a debugger or other diagnostic software is incomplete. Gaps in the call history resulting from inlining cause confusion and create misleading results.
If a compiler can track partial call histories as well as source locations for its objects, then there needs to be a way for a compiler to extract details. As the compiler goes through the sequences of machine instruction objects in order to put machine instruction codes into the binary file, it must identify changes in source location details and indicate those changes in a table also put in the binary file. When call histories change, they are likely to change more quickly at deeper levels of inlining and less frequently at shallow levels. If at each change in a call history the entire new histories are put in the table, the table is made much larger than it needs to be. An apparatus that detects not only change, but the level of change within call histories can reduce the size of the generated table.

Method for tracking changes in source locations in a compiler


A connector comprises a pair of terminals for clamping and electrically connecting to a first conductive member. A first terminal includes a plurality of first elastic arms arranged in a row, with each first elastic arm having a first contact and a third contact formed thereon. The second terminal is laminated on an outer side of the first terminal and includes a plurality of second elastic arms arranged in a row. Each second elastic arm includes a second contact formed thereon. Each second contact protrudes to an inner side of the first elastic arms from a gap between two adjacent first elastic arms. The plurality of second elastic arms respectively abut against the outer sides of the plurality of first elastic arms. The first contact, the second contact and the third contact are adapted to be in electrical contact with the inserted first conductive member simultaneously.

According to the prior art, a connector used to electrically connect an electrode of a power source to a bus bar typically includes a conductor block on which a slot is formed. The electrode of the power source is adapted to be inserted into the slot for electrically connecting to the conductor block. However, the current carrying capacity of this type of connector is insufficient, and the ability to reliably contact the electrode of the power source during an installation process is insufficient, and cannot meet the requirements of customers.
Accordingly, improved connectors for mating a power source to a bus bar are desired.


There is provided a toaster grill having a lower housing that supports a lower cooking surface and an upper housing that supports an upper cooking surface. The upper housing pivots with respect to a “U” shaped frame that is hinged with respect to the lower cooking surface. A locking hinge allows the pivoting motion of the frame to be automatically arrested in an intermediate orientation between the fully closed and fully open grill orientations. The locking hinge automatically resets when the upper housing is rotated from the fully open grill orientation to the fully closed orientation.

A sandwich press has a lower housing that supports a lower cooking surface. The upper cooking surface is carried by an upper housing that pivots about a "U" shaped frame. The "U" shaped frame further comprises a transverse handle that allows the user to raise and lower the upper housing. In a typical sandwich press, the upper and lower cooking surfaces are flat.
Similar configurations are used in electric grills. The operating temperature of an electric grill is higher than that of a typical sandwich press. In these types of grills, both the top the upper and lower cooking surfaces include parallel ribs which provide cooked meat with characteristic sear marks and also promote the run off of cooking juices. However, neither prior art sandwich presses nor prior art meat grills are known to have sandwich press as well as grill functions, providing a fully open grill orientation in which both cooking surfaces are facing upward, generally co-planar and horizontal.