Systems and methods are described for enabling routers to coordinate via a back-channel communication medium. The information exchanged over the back-channel is used to increase the number of paths considered for the routers during route optimization. The Decision Makers may assert routes and prefixes to the routers under their control. This may be done via a Border Gateway Protocol (BGP) feed. The Decision Makers, in turn, communicate separately with one another, in order to coordinate routing policy amongst themselves. This coordination may be performed over a back-channel, which may take the form of physical or logical connections between the Decision Makers.

1. Field of the Invention
This invention relates to the field of networking. In particular, the invention relates to systems and methods for coordinating routing information amongst routers.
2. Description of the Related Art
Internetworks such as the Internet are currently comprised of Autonomous Systems, which exchange routing information via exterior gateway protocols. Amongst the most important of these protocols is the Border Gateway Protocol, or BGP. BGPv4 constructs a directed graph of the Autonomous Systems, based on the information exchanged between BGP routers. Each Autonomous System is identified by a unique 16 bit AS number, and BGP ensures loop-free routing amongst the Autonomous Systems; BGP also enables the exchange of additional routing information between Autonomous Systems. BGP is further described in several RFCs, which are compiled in The Big Book of Border Gateway Protocol RFCs, by Pete Loshin, which is hereby incorporated by reference.
The Border Gateway Protocol provides network administrators some measure of control over outbound traffic control from their respective organizations. For instance, the protocol includes a LOCAL_PREF attribute, which allows BGP speakers to inform other BGP speakers within the Autonomous System of the speaker's preference for an advertised route. The local preference attribute includes a degree of preference for the advertised route, which enables comparison against other routes for the same destination. As the LOCAL_PREF attribute is shared with other routers within an Autonomous System via IBGP, it determines outbound routes used by routers within the Autonomous System.
A WEIGHT parameter may also be used to indicate route preferences; higher preferences are assigned to routes with higher values of WEIGHT. The WEIGHT parameter is a proprietary addition to the BGPv4 supported by Cisco Systems, Inc. of San Jose, Calif. In typical implementations, the WEIGHT parameter is given higher precedence than other BGP attributes.
The performance knobs described above are, however, rather simple, as they do not offer system administrators with sufficiently sophisticated means for enabling routers to discriminate amongst routes. There is a need for technology that enables greater control over outbound routing policy. In particular, there is a need to allow performance data about routes to be exchanged between routers. Additionally, system administrators should be able to fine tune routing policy based upon sophisticated, up-to-date measurements of route performance and pricing analysis of various routes.

Method and apparatus for coordinating routing parameters via a back-channel communication medium


The apparatus comprises derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different from other derived addresses in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses and is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value.

1. Field of the Invention
The present invention relates to the testing of memory devices within data processing systems in order to detect memory defects, and more particularly relates to techniques for detection of address decoder open faults in such memory devices.
2. Description of the Prior Art
It is known to provide data processing system incorporating memories with self-testing mechanisms, sometimes termed built-in self-test (BIST) mechanisms, such that when the memory devices have been fabricated they may conduct a self-test or series of self-tests to determine if there are any memory defects present that would indicate that the circuit should be rejected. It is important that memory circuits should be highly reliable and that defective circuits should be effectively identified. As memory sizes increase, the proportion of the die being taken up by the memory is also increasing and, furthermore, the high transistor density within memory means that the defect density of these memories is becoming increasingly significant.
There are various types of defect that can arise in a memory device, and typically different tests need to be performed for each of the various types of defect. In addition to the detection of errors in the cells of the memory array itself, errors may also occur in the circuit elements used to control access to the memory cells within the memory array. For example, one or more address decoders may be provided in association with the memory array to activate particular rows and/or columns of the memory array dependent on an address provided to such address decoders. An address decoder can potentially suffer from an address decoder open fault (ADOF). ADOFs are caused by open defects in the logic gates of the memory address decoders, and due to their sequential behaviour, cannot be mapped to the faults of the memory array itself.
Considering for example a row address decoder used to activate a word line in the memory array, in fault free row address decoder circuitry only one word line is expected to be active at any point in time and hence during a write operation the data the subject of the write operation should only be written to the relevant location in that activated word line. However, if an open fault defect exists in one of the transistors of the address decoder, then a situation can arise where, when a new address is provided to the address decoder, a previously selected word line is not de-selected when the new word line appropriate to the new address is activated, and accordingly two word lines may be simultaneously activated. As a result, the data value the subject of the new write access request may end up being written to two locations.
Further details of address decoder open faults are provided in the article "Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests" by J Otterstedt et al., IEEE International Test Conference 1998, Pages 53 to 62. As described therein, a basic algorithm for testing for an open fault in an address decoder is to write a data value D to one address, and then to write the inverse data value D to a different address, after which the contents at the original address are read to determine if that data is D or D. If the data at the original address is now D, that indicates the presence of an open fault in the address decoder.
Clearly the above process needs to be repeated multiple times to seek to thoroughly test for all possible open faults within the address decoder. One mechanism that may be used is to perform a single step test, where each iteration of the above-mentioned algorithm (i.e. two writes followed by a read) is performed in response to a specified test command identifying the required addresses, data, etc. However, such an approach requires a very large amount of testing time to perform all of the required tests, and involves the issuance of multiple commands to identify each single step test. An additional problem is how to identify the appropriate addresses to write to in order to thoroughly test all possible open faults in the address decoder.
In the earlier-mentioned article "Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests", a more automated test procedure is described which uses linear feedback shift registers (LFSRs) to generate required address sequences. However, in accordance with the techniques described therein, different configurations of LFSRs are required dependent on the relative width of the address bits provided to the largest subaddress decoder to the overall address width (see cases 1 to 4 set out in section 4 of that paper). Indeed for the situation of case 4, namely where k≧(n+2)/2 it is indicated that no LFSR-based solution could be found that would produce the required address sequences. In the above equation, k is the width of the largest subaddress decoder (i.e. the largest of the row decoder or the column decoder), and n is the overall address width.
Accordingly, it would be desirable to provide an improved technique for performing the required test sequence to detect address decoder open faults in a memory device.

Apparatus and method for detection of address decoder open faults


A system and method in which a plurality of dice on a semiconductor wafer are interconnected to enable efficient testing thereof. In certain embodiments a plurality of dice are interconnected in a manner that enables test data to be communicated from a tester system to a plurality of dice for concurrent testing of such plurality of dice. Depending on the amount of interconnection, all or a portion of each of the plurality of dice may be tested concurrently. In certain embodiments, a plurality of dice are interconnected in a manner that enables test data to be communicated from one die to at least one other die. In certain embodiments, a plurality of dice are interconnected in a manner that enables such dice to be tested concurrently while maintaining a repeatable pattern at the reticle level for fabricating such dice.

During typical semiconductor manufacturing processes, a plurality of integrated circuits are formed as individual dice on a semiconductor wafer. Each semiconductor wafer generally has dozens to hundreds of individual dice formed thereon. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional and which dice are not functional. In most testing procedures, each die is probed using very costly probe equipment while the dice are still on the wafer. This step is also known as "wafer sort."
The purpose of the wafer-level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less time and expense that is wasted on further processing of defective dice. That is, if it is determined that a detected defect cannot be repaired, the time and expense of completing a chip assembly will not be expended.
Traditionally, probe equipment has been capable of only testing one or a few dice at a time. In traditional testing procedures, probe equipment is used to contact each bonding pad (or "access pad") on an individual die with a separate probe needle. More specifically, in traditional testing procedures, each die is probed in order to determine whether it passes a very basic test (e.g., a test for electrical opens or electrical shorts). In most cases, a full functional test may also be performed using the probe equipment. A probe (which may be referred to herein as a "stylus") may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe may be communicatively coupled to an external Automated Test Equipment (ATE) that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly. Traditional testing procedures generally involve contacting access pad(s) of each individual die with a probe in series. That is, the dice of a wafer are generally tested one at a time in series using a probe to contact the pad(s) of each die. In some instances a probe card may be utilized that includes a sufficient number of pins to enable multiple dice to be tested concurrently. That is, a probe card may comprise a sufficient number of pins to enable access pads of multiple dice to be contacted simultaneously for testing of such multiple dice. As described further below, it is generally desirable to test a large number of dice in parallel because of the time required for moving the probe card from one die (or set of dice) to another die (or set of dice), which may be on the order of the actual testing time.
Traditional testing procedures are problematic because of their serial nature. For example, using a probe to test one die after another die results in an undesirably long time being required for testing all of the dice of a wafer, which effectively increases the overall cost of testing the dice. Probes used for testing the dice are generally very expensive, and it is therefore undesirable to have a probe tied up for a long time testing each die. Additionally, while certain probe implementations may provide a sufficient number of pins to enable a plurality of dice to be tested simultaneously, such testing is limited by the configuration (e.g., the number of pins) of the probe. For instance, a probe that comprises sufficient pins for contacting two dice simultaneously is limited to testing of two dice concurrently. Thus, if it is desired to test four dice, the probe configuration is incapable of testing all four dice simultaneously. Thus, generally the communication to the dice for testing is limited by the probe card's configuration. In addition, physical constraints may limit the amount of parallelism that may be achieved through modifying a probe's configuration (e.g., to include more pins). For example, in some instances it may not be technologically possible to arrange the pins of a probe in a manner (e.g., sufficiently close together) to enable testing of a desired number of dice, or implementing such an arrangement may not be cost effective.
Further, the life of a probe is generally measured by the number of times it touches down on dice (e.g., a probe may have a typical life of one million touch downs). Traditional testing procedures that require a probe to touch down on one (or a few) dice at a time effectively increases the wear of a probe. For instance, a probe having a life of one million touch downs that is utilized in a traditional testing procedure in which one die at a time is tested will be capable of testing one million dice. Considering the cost associated with such probes, it is generally desirable to effectively prolong the life of a probe by testing as many dice as possible during the probe's life.
More recently, testing techniques have been proposed that enable parallel testing of multiple dice of a wafer with a single probe. Examples of such parallel testing schemes that have been proposed include those described in U.S. Pat. No. 5,504,369 titled "Apparatus for Performing Wafer Level Testing of Integrated Circuit Dice" issued Apr. 2, 1996 to Dasse et al., U.S. Pat. No. 5,898,186 titled "Reduced Terminal Testing System" issued Apr. 27, 1999 to Farnworth et al., and U.S. Pat. No. 6,340,823 B1 titled "Semiconductor Wafer Having a Multi-Test Circuit, and Method for Manufacturing a Semiconductor Device Including Multi-Test Process" issued Jan. 22, 2002 to Kitade. Such parallel testing schemes proposed in the prior art generally provide for one or more wafer-level access pads arranged on a wafer external to the dice, and such access pads may be contacted by a probe to input signals and/or to receive output signals. In these testing schemes, the wafer-level access pads may each be coupled to a plurality of dice, thereby enabling input signals from a probe to be communicated to such plurality of dice in parallel and/or enabling output signals from the plurality of dice to be communicated to the probe.
Parallel testing schemes of the prior art have primarily focused on avoiding contact by a probe with access pads of an individual die in order to prevent damaging the die's access pads. While parallel testing solutions of the prior art propose communicatively coupling a wafer-level access pad to multiple dice to enable data to be communicated from the access pad to the dice in parallel (and vice-versa), such solutions do not provide a communication scheme for improving/optimizing efficiency and reliability of the testing. That is, the primary focus of prior parallel testing solutions has been to arrange wafer-level access pads that are each coupled to a plurality of dice so as to prevent damaging the access pads of the dice with a test probe, and such solutions have neglected to provide an interconnection scheme that enables test data to be communicated from one die to another die in a manner to improve efficiency and/or reliability of the testing. Further, parallel testing solutions proposed in the prior art are difficult and/or not cost effective to manufacture.
Once the wafer-level testing is completed, the dice are usually then separated or singulated into individual die using any one of a variety of singulation techniques. Typically, the dice are singulated by use of a wafer saw, which grinds the wafer along cut zones (usually referred to as "scribe lines") separating the individual die. In most cases, each die is then packaged in an integrated circuit package. Once the dice have been packaged, thorough electrical testing is typically performed on each of the packaged integrated circuits. The purpose of the thorough electrical testing is to determine whether each packaged integrated circuit properly performs the functionality specified by the designer. The packaged integrated circuits determined to function properly are then sold.
Sometimes process monitors are placed on the scribe lines and on other places of the wafer. Such process monitors typically comprise small circuitry (e.g., a ring oscillator) that is used to measure process parameters. However, this measurement cannot be used to point to certain defects on dies in isolation. It can only be used to get data about different process parameters that impact a portion of the wafer, beyond a single die.
In some cases, the packaged integrated circuits also undergo a reliability testing procedure called burn-in. Burn-in testing involves the testing of an integrated circuit for an extended period of time while its temperature is elevated above room temperature. In some cases, the heat generated by the integrated circuit itself is sufficient to elevate its temperature by a sufficient amount for the burn-in testing. In other cases, the temperature of the integrated circuit is raised by an external apparatus external (e.g. a burn-in oven in which the packaged integrated circuits are placed).
Instead of or in addition to burn-in testing, cold temperature reliability testing may be performed. Cold temperature reliability testing involves the testing of an integrated circuit for an extended period of time while its temperature is decreased below room temperature.
Semiconductor manufacturers spend a significant amount of money packaging defective dice which pass the testing performed during probing, but which do not pass the reliability testing after packaging. The cost saving goal of detecting and screening out defective dice as early as possible in the manufacturing process is especially important in the context of multi-chip modules (MCMs). Multi-chip modules (MCMs) are electronic modules that include a plurality of integrated circuit dice which are packaged together as one unit. Multi-chip modules are becoming more widely used.
For multi-chip modules, it is quite costly to replace one or more failed dice once the dice have been bonded onto a substrate. Therefore, it is desirable to determine whether a die is fully functional and is reliable before the die is packaged as part of a multi-chip module. In addition, many manufacturers of multi-chip modules are requiring that semiconductor manufacturers sell them fully tested "known good dice" that have passed reliability tests and that are not packaged in an integrated circuit package.

System and method for testing circuitry on a wafer


A method for controlling a continuous variable valve timing apparatus that can control a phase angle of a camshaft quickly and precisely according to an exemplary embodiment of the present invention may include: calculating a difference between a target phase angle and a current phase angle of a camshaft; determining whether the difference between the target phase angle and the current phase angle of the camshaft is larger than or equal to a predetermined value; calculating a base torque Tb based on the target phase angle if the difference between the target phase angle and the current phase angle of the camshaft is larger than or equal to the predetermined value; calculating an effective torque Teff by modifying the base torque Tb corresponding to engine speed and temperature of engine oil; and calculating an effective current Ieff corresponding to the effective torque Teff.

(a) Field of the Invention
The present invention relates to an engine, more particularly, a method for controlling a continuous variable valve timing apparatus that variably controls opening and closing timing of intake and exhaust valves in an engine.
(b) Description of the Related Art
Generally, a continuous variable valve timing (CVVT) apparatus changes opening and closing timing of intake and exhaust valves by changing phase angle of a camshaft that controls opening and closing of the intake and exhaust valves, according to an engine speed and load state of a vehicle. If the CVVT apparatus is used in a vehicle, ignition timing of the air-fuel mixture can be controlled effectively. Therefore, exhaust gas and fuel consumption may be reduced, and engine performance may improve.
A conventional method for controlling a continuous variable valve timing apparatus is realized by a feedback control method. That is, the CVVT is controlled by applying a current according to a difference between a current phase angle of the camshaft and a target phase angle of the camshaft to an electric clutch for controlling phase angle of the camshaft every predetermined time interval.
However, according to the conventional method for controlling a continuous variable valve timing apparatus, there is a problem that control timing is delayed since the phase angle of the camshaft is controlled based on feedback control.
In addition, since the phase angle of the camshaft changes according to the temperature of engine oil and engine speed, it is difficult to precisely control valve timing.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Method for controlling continuous variable valve timing apparatus


An energy absorbing structure for a side portion of a vehicle body includes a plastically deformable energy absorbing member which is disposed at a predetermined position in the side portion of the vehicle body against which a side portion of an upper part of a vehicle occupant's body hits during a side collision, the energy absorbing member being arranged such that a longitudinal direction thereof coincides with a longitudinal direction of the vehicle body, a cross section of the energy absorbing member being formed in the shape of a substantially hollow ellipse in which a direction of a short axis thereof is a transverse direction of the vehicle body and a direction of a long axis thereof is a vertical direction of the vehicle body, the wall thickness of the energy absorbing member being set such that the wall thicknesses of long-axis portions thereof corresponding to the long axis are greater than the wall thicknesses of short-axis portions thereof corresponding to the short axis.

1. Field of the Invention
The present invention relates to an energy absorbing structure for a side portion of a vehicle body for protecting a vehicle occupant during a side collision of a vehicle.
2. Description of the Related Art
In recent years, in vehicles, particularly in automobiles, various countermeasures against side collisions have come to be adopted to improve the performance of protection of a vehicle occupant during a side collision. As one technique of this type of countermeasure against a side collision, the provision of an energy-absorbing structure in a side door has been conventionally practiced. The Jidosha Gijutsu Jireishu (Collection of Examples of Automotive Technology) No. 95352 published by the Intellectual Property Sub-Committee of the Japan Automobile Manufacturers Association, Inc. discloses a door structure in which an air-conditioning air duct for a vehicle rear seat is disposed in that vehicle compartment-side shoulder portion of a door for a vehicle front seat which is located in the vicinity of a window, so as to absorb an impact at the time of a side collision. In addition, Japanese Patent Application Laid-Open (JP-A) No. 7-89346 discloses a structure for reinforcing a vehicle door in which a guide bar (i.e., an impact beam) in a door panel is covered with a large-diameter pipe so as to absorb impact energy during a side collision. Hereafter, consideration will be given of other examples.
In the structure shown in FIG. 9, energy absorbing members 106, each formed separately and made of urethane foam, styrene foam, or the like, are respectively disposed between an upper portion 100A of a door trim 100 and a door inner panel 104 of a side door 102 and between a lower portion (armrest) 100B of the door trim 100 and the door inner panel 104.
In accordance with the above-described arrangement, when a door outer panel 108 of the side door 102 is deformed toward the inner side of a vehicle compartment during a side collision (behavior during a primary collision), the upper part of the occupant's body moves toward the door inner panel 104 side as a reaction at that time, and hits against the upper portion 100A of the door trim 100 (behavior during a secondary collision). At this time, the energy at the time when a chest portion of the occupant undergoes the secondary collision is absorbed through the elastic deformation of the energy absorbing member 106 located on the upper side, while the energy at the time when a waist portion of the occupant undergoes the secondary collision is absorbed through the elastic deformation of the energy absorbing member 106 located on the lower side.
However, with the above-described arrangement, since the bulk compressibility of the energy absorbing member 106 is set to approximately 70% by taking into consideration the material and the energy absorption characteristic, there is a disadvantage in that the thickness D.sub.1 of the energy absorbing member 106 provided for the chest becomes large in order to obtain a deformation stroke necessary for protection of the occupant.
Meanwhile, in the structure shown in FIG. 10, energy absorbing members 110 with a substantially hat-shaped cross section, each formed integrally on the door inner panel 104 and made of a thin steel sheet or the like, are respectively disposed between the upper portion 100A of the door trim 100 and the door inner panel 104 of the side door 102 and between the lower portion 100B of the door trim 100 and the door inner panel 104.
In accordance with the above-described arrangement, the absorption of energy at the time of the secondary collision of the occupant is effected in a similar manner. In addition, since the bulk compressibility of the energy absorbing member 110 can be set to 90% or more, it is possible to secure the deformation stroke necessary for protection of the occupant without enlarging the thickness (depth) D.sub.2 of the energy absorbing member 110 provided for the chest.
However, with the above-described arrangement, as shown in FIG. 11, the load is substantially fixed irrespective of an increase in displacement even from the initial period of the secondary collision of the occupant. Here, since the characteristic indicated by the chain line in the drawing, i.e., the characteristic in which the load increases at a fixed rate with an increase in displacement, is a targeted characteristic, there is room for improvement.
Incidentally, it is conceivable to provide energy absorbing members with a circular cross section (e.g., pipes made of an aluminum alloy) instead of the energy absorbing members 110 with a hat-shaped cross section (as a disclosed example, the Jidosha Gijutsu Jireishu (Collection of Examples of Automotive Technology) No. 94602 published by the Intellectual Property Sub-Committee of the Japan Automobile Manufacturers Association, Inc. is known). In this case, however, the energy absorbing member is difficult to undergo plastic deformation (difficult to crush) in an initial period of the secondary collision, and there is a tendency that the plastic deformation subsequently proceeds at a stroke. As a result, although, as a whole, the energy absorption characteristic becomes closer to the targeted characteristic than in the case where the energy absorbing members 110 with a hat-shaped cross section are used, there is room for improvement in that the rise in the load during the initial period of the secondary collision becomes sharp.

Energy absorbing structure for side portion of vehicle body


A cooling system is provided employing at least two modular cooling units (MCUs). Each MCU is capable of providing system coolant to multiple electronics subsystems to be cooled, and each includes a heat exchanger, a first cooling loop with at least one control valve, and a second cooling loop. The first cooling loop receives chilled facility coolant from a source and passes at least a portion thereof through the heat exchanger, with the portion being controlled by the at least one control valve. The second cooling loop provides cooled system coolant to the multiple electronics subsystems, and expels heat in the heat exchanger from the multiple electronics subsystems to the chilled facility coolant in the first cooling loop. The at least one control valve allows regulation of facility coolant flow through the heat exchanger, thereby allowing control of temperature of system coolant in the second cooling loop.

Heat flux dissipated by electronic equipment, such as microprocessors and power supplies, is again reaching levels that require cooling other than simple air cooling as a means of controlling component temperature. Liquid cooling (e.g., water cooling) is an attractive technology to manage these higher heat fluxes. The liquid absorbs the heat dissipated by the component/modules in an efficient manner, i.e., with minimal temperature rise from the liquid to the component being cooled. Typically, the heat is ultimately transferred from the liquid out into the outside environment. Otherwise, the liquid coolant would continuously rise in temperature.
From the 1970's through the early 1990's, International Business Machines Corporation accomplished this task by circulating cooling liquid via a coolant distribution unit which was a single, large computer room water conditioning unit (CRWCU). The CRWCU distributed conditioned chilled water to the various electronics racks of a mainframe computer system to be cooled. Conventionally, the electronics racks of the mainframe computer included memory frames, processor frames, input/output frames, power frames, etc. Operationally, the CRWCU received customer chilled water which was then used to remove heat from conditioned cooled water to the individual electronics racks of the computer room.
The CRWCU included a primary cooling loop wherein building chilled water was supplied and passed through a control valve driven by a motor. The valve determined an amount of building chilled water to be passed through a heat exchanger, with a portion of the building chilled water possibly being returned directly to the return via a bypass orifice. The CRWCU further included a second cooling loop with a reservoir tank from which water was pumped either by one of two pumps into the heat exchanger for conditioning and output therefrom as a conditioned water source to the electronics racks to be cooled within the computer room. The computer room water conditioning unit normally stood separate from the electronics frames, and again, would supply system water (typically maintained at about 22° C.) to all electronics frames of the computer room.
The coolant distribution unit, and more particularly, the computer room water conditioning unit (CRWCU), contained a single heat exchanger, a single reservoir, a single control valve, and redundant pumps. Thus, in the case of a failed pump, the CRWCU would automatically switch to the redundant pump, but any other malfunction in the coolant distribution unit would have brought down the whole computer room mainframe system. For example, if the heat exchanger, or control valve, or building chilled water source failed, the entire mainframe system in the computer room would also fail. Redundant mainframe computers would have been on the computer room floor to allow continuation of processing (in a degraded mode) until the downed mainframe could be repaired.

Cooling system and method employing at least two modular cooling units for ensuring cooling of multiple electronics subsystems


A system and method for connecting traffic along a communications network is accomplished by rerouting traffic upon the detection of a fault condition along a primary connection path. Signals are divided into different wavelength regions labeled red and blue, respectively. The wavelength bands between transmit and receive channels are alternated between red and blue band regions and then combined, multiplexed or xe2x80x9cbundledxe2x80x9d together by a wideband wavelength division multiplexer in a single non wavelength specific transmission medium for connection to a single uni-directional Optical Cross Connect System (OCCS) port. Additionally, the receiving end of a single medium is connected to a wavelength division multiplexer which unbundles the combined red and blue band signals upon reception.

1. Field of the Invention
The present invention relates generally to communications systems and specifically to fault tolerant fiber optic communication networks.
2. Description of the Related Art
Fiber optic communication systems are traditionally deployed in a point-to-point terminal configuration along a single path. A problem occurs if the connection path is somehow interrupted either due to equipment failure or a physical disruption in the connection.
Sonet self healing ring architectures may be a solution that protects against service disruption and node failure along a given primary path. Referring to FIG. 1, a ring architecture is presented, with nodes 120, 130, 140 and 150 all residing on ring 110. If a message to be transmitted from node 150 to node 130 clockwise along path A-B of ring 110 cannot be completed due to a failure in path B, then the message is routed counter-clockwise along alternate path D-C. In fact, in this architecture messages from node 120 intended for any node are also routed counter-clockwise to the intended destination node.
Drawbacks to the above system include the requirement for having expensive add/drop multiplexers and associated support equipment present in each node.
Most installed networks are point-to-point systems. Balancing traffic around a ring can be difficult. Further, managing an all-ring network and provisioning demands across several interconnected rings is more difficult and expensive than in a point to point network.
There is accordingly a need for a new method and apparatus for inexpensively and easily rerouting traffic between nodes in a communication network when a given path becomes unusable in order to solve or ameliorate one or more of the above-described problems.
According to a preferred embodiment of the present invention, a system and method for connecting traffic along a communications network is accomplished by rerouting traffic upon the detection of a fault condition along a primary connection path.
In an embodiment of the present invention, wavelengths are divided into different regions labeled red and blue, respectively. The wavelength bands between transmit and receive channels are alternated between red and blue band regions and then combined, multiplexed or xe2x80x9cbundledxe2x80x9d together by a non wavelength specific wideband wavelength division multiplexer in a single transmission medium for connection to a single uni-directional Optical Cross Connect System (OCCS) port. The different number of regions may be any even number of regions as long as the wavelengths are alternated.
Additionally, the receiving end of a single medium is connected to a wavelength division demultiplexer which unbundles the combined red and blue band signals upon reception.
In other words, a red band signal is bundled with a blue band signal for transmission through a single medium where it is received and then unbundled into its red and blue components by a wavelength division multiplexer at the receiver.
An analogous method and apparatus is used to transmit a signal in the opposite direction when and if required for full duplex operation.
Further features of the above-described invention will become apparent from the detailed description hereinafter.
The foregoing features together with certain other features described hereinafter enable the overall system to have properties differing not just by a matter of degree from any related art, but offering an order of magnitude more efficient use of processing time and resources.
Additional features and advantages of the invention will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate preferred embodiments of the apparatus and method according to the invention and, together with the description, serve to explain the principles of the invention.

Apparatus and method for restoring fiber optic communications network connections


A dimmable LED lighting apparatus including a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the drive controller, an insulation type signal transceiver receiving a pulse width modulation (PWM) signal output from a PWM dimmer and outputting the PWM signal to the drive controller, while electrically insulating the PWM dimmer from the drive controller, a first LED group to an nth LED group, n being a positive integer of 2 or greater, receiving the drive voltage and sequentially operating under control of the drive controller, and a drive controller controlling sequential operation of the first LED group to the nth LED group according to a voltage level of the drive voltage, determining a dimming level based on the received PWM dimming signal, and controlling dimming of the first LED group to the nth LED group based on the determined dimming level.

Field
The present invention relates to a dimmable smart light emitting diode (LED) lighting apparatus and, more particularly, to a plurality of dimmable LED lighting apparatuses directly connected to one dimmer.
Discussion of the Background
In recent years, a dimmable LED lighting apparatus is widely used. Such a dimmable LED lighting apparatus is composed of a dimmer and an LED lighting apparatus, and is configured to allow control of illuminance in response to a dimming signal from the dimmer. However, a typical dimmable LED lighting apparatus and/or an illumination system including such an LED lighting apparatus have various problems. Hereinafter, the problems of the typical dimmable LED lighting apparatus and/or the illumination system including such an LED lighting apparatus will be described.
First, in order to perform dimming control of a plurality of LED lighting apparatuses at the same time, an illumination system capable of simultaneously controlling dimming levels of the plurality of LED lighting apparatuses using a single dimmer is used in the related art. In such a typical illumination system, the dimmer is directly connected to the plurality of LED lighting apparatuses via a cable line. However, such a typical illumination system has problems as follows. First, since the dimmer is connected to the LED lighting apparatuses via the cable line, a dimming signal sent from the dimmer to the LED lighting apparatuses can be distorted due to influence of external noise and the like. Generally, such an illumination system employs a dimming signal at a relatively low voltage (for example, 0.4V˜2V), the dimming signal can be negatively influenced by, particularly, surrounding noise. Second, connection between the dimmer and the LED lighting apparatuses via the cable line causes generation of electromagnetic waves during transmission of the dimming signal to the LED lighting apparatuses, thereby having a negative influence on the LED lighting apparatus. Third, since the plurality of LED lighting apparatuses is electrically connected to one dimmer via the cable line, it can be considered that the dimmer and the plurality of LED lighting apparatuses constitute a circuit. Accordingly, upon failure of a certain LED lighting apparatus among the plurality of LED lighting apparatuses, the entire illumination system stops to operate, and the other LED lighting apparatuses and the dimmer malfunction due to failure of the certain LED lighting apparatus.
Further, such a typical dimmable LED lighting apparatus has a problem in that, when a dimming signal is not sent from the dimmer to the LED lighting apparatus, the LED lighting apparatus does not operate. More specifically, when the dimmer malfunctions, when there is a problem in the connection line between the dimmer and the LED lighting apparatus, when there is a malfunction of an input terminal to which the dimming signal is input, and the like, the dimming signal is not supplied to the LED lighting apparatus. In this case, although there is no problem in terms of a lighting function of the LED lighting apparatus, the LED lighting apparatus does not operate. That is, when the dimming signal is not sent to the LED lighting apparatus for the aforementioned reasons, the LED lighting apparatus does not operate since the determined dimming level is 0%.
On the other hand, some typical LED lighting apparatuses are configured to have a jumper set to provide the dimming function or not to provide such function. Accordingly, this type of dimmable LED lighting apparatus is required to change jumper setting attached to a drive IC by disassembling the LED lighting apparatus in order to change setting as to use of the dimming function. As a result, this type of dimmable LED lighting apparatus does not allow easy setting as to use of the dimming function and is very difficult for an unskilled person to change jumper setting thereof.
On the other hand, demand for various and complicated functions of a lighting apparatus has been increasing in the related art. For example, in recent years, the lighting apparatus has been increasingly required to have a color temperature (CT) or correlated color temperature (CCT) control function that enables provision of various lighting conditions and circumstances through change of illuminance of light emitted from the lighting apparatus, rather than a simple lighting function which has been demanded in the related art. However, the aforementioned dimmable LED lighting apparatus is configured to control only light output, that is, illuminance, and thus fails to satisfy various consumer demands as described above.
Moreover, there is an increasing trend of integrally controlling a plurality of LED lighting apparatuses through integration of the plurality of LED lighting apparatuses into a monolithic LED illumination system. Representative examples of such integrated control illumination systems include a street lamp system, a tunnel lamp system, and the like. However, such LED illumination systems allow only simple on/off control of the LED lighting apparatuses or simultaneous illuminance control of all the LED lighting apparatuses, and cannot perform a systematically integrated control of the LED lighting apparatuses according to surrounding circumstances.
The present invention has been conceived to solve the aforementioned problems in the related art.
Exemplary embodiments of the present invention provide a dimmable LED lighting apparatus electrically insulated from a dimmer while allowing transmission and reception of dimming signals between the dimmable LED lighting apparatus and the dimmer such that failure of one LED lighting apparatus does not affect the other LED lighting apparatuses, thereby enabling normal operation of the other LED lighting apparatuses.
Exemplary embodiments of the present invention provide an LED lighting apparatus that can be normally operated at a maximum dimming level even upon failure of a dimmer or an interconnection line.
Exemplary embodiments of the present invention provide an LED lighting apparatus that can be normally operated at a maximum dimming level through simple manipulation in the case where a user does not want to use a dimming function.
Exemplary embodiments of the present invention provide a dimmable LED lighting apparatus capable of outputting various color temperatures through dimming control of LED groups.
Exemplary embodiments of the present invention provide a smart illumination system that includes a plurality of lighting apparatuses and is capable of performing individual dimming control of the lighting apparatuses in response to detection signals sent from a motion sensor and an illumination sensor.
The above and other objects and the following advantageous effects of the present invention can be achieved by features of the present invention, which will be described hereinafter.
In accordance with one aspect of the invention, a dimmable LED lighting apparatus includes: a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the drive controller; an insulation type signal transceiver receiving a pulse width modulation (PWM) signal output from a PWM dimmer and outputting the PWM signal to the drive controller, while electrically insulating the PWM dimmer from the drive controller; a first LED group to an nth LED group (n being a positive integer of 2 or higher) receiving the drive voltage and sequentially operating under control of the drive controller; and a drive controller controlling sequential operation of the first LED group to the nth LED group according to a voltage level of the drive voltage, determining a dimming level based on the received PWM dimming signal, and controlling dimming of the first LED group to the nth LED group based on the determined dimming level.
The drive controller may include an integrating circuit that receives the PWM dimming signal and outputs a dimming signal detected through integration of the received PWM dimming signal for a pulse period, and the drive controller may determine the dimming level based on an average voltage of the detected dimming signal.
The insulation type signal transceiver may include a light source that outputs light obtained through conversion of the PWM dimming signal from the PWM dimmer, and a photodetector that outputs an electrical signal obtained through conversion of the PWM dimming signal received in the form of light.
The insulation type signal transceiver may further include a noise filter that filters high frequency noise from the received PWM dimming signal.
The insulation type signal transceiver may further include a constant current control device that maintains current supplied to the light source at a constant level.
The insulation type signal transceiver may further include a reverse voltage protection diode that protects the LED lighting apparatus from reverse voltage applied thereto.
In accordance with another aspect of the invention, a dimmable LED lighting system includes: a PWM dimmer outputting a PWM dimming signal in response to a dimming level; and a plurality of dimmable LED lighting apparatuses as set forth above. Here, the plurality of dimmable LED lighting apparatuses is connected to the PWM dimmer.
In accordance with a further aspect of the invention, a dimmable LED lighting apparatus includes: a reverse pulse width modulation (PWM) dimmer receiving a dimming level and outputting a reverse PWM dimming signal by inverting the received dimming level; a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the drive controller; an insulation type signal transceiver receiving the reverse PWM dimming signal and outputting the reverse PWM dimming signal to the drive controller, while electrically insulating the reverse PWM dimmer from the drive controller;
a first LED group to an nth LED group (n being a positive integer of 2 or higher) receiving the drive voltage and sequentially operating under control of the drive controller; and a drive controller controlling sequential operation of the first LED group to the nth LED group according to a voltage level of the drive voltage, reinverting the received reverse PWM dimming signal into a PWM dimming signal, determining a dimming level based on the PWM dimming signal, and controlling dimming of the first LED group to the nth LED group based on the determined dimming level.
The drive controller may include an inverting circuit that outputs the PWM dimming signal by re-inverting the received reverse PWM dimming signal.
The inverting circuit may include a pull-up resistance and a clamping diode.
The inverting circuit may include an inverting amplifier.
The drive controller may include an integrating circuit that receives the PWM dimming signal and outputs a dimming signal detected through integration of the received PWM dimming signal for a pulse period, and the drive controller may determine the dimming level based on an average voltage of the detected dimming signal.
The insulation type signal transceiver may include a light source that outputs light obtained through conversion of the reverse PWM dimming signal from the reverse PWM dimmer, and a photodetector that outputs an electrical signal obtained through conversion of the reverse PWM dimming signal received in the form of light.
The insulation type signal transceiver may further include a noise filter that filters high frequency noise from the received reverse PWM dimming signal.
The insulation type signal transceiver may further include a constant current control device that maintains current supplied to the light source at a constant level.
The insulation type signal transceiver may further include a reverse voltage protection diode that protects the LED lighting apparatus from reverse voltage applied thereto.
In accordance with yet another exemplary embodiment of the invention, a dimmable LED lighting apparatus includes: a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the first lighting module and the second lighting module; an insulation type signal transceiver receiving a PWM dimming signal output from a PWM dimmer and outputting the PWM dimming signal to the first lighting module while electrically isolating the PWM dimmer from the first lighting module; a first lighting module receiving the drive voltage and the PWM dimming signal to perform illumination based on a dimming level; and a second lighting module receiving the drive voltage to perform illumination.
The first lighting module may include a first light emitting unit including at least one LED group; and a first drive controller sequentially driving the one or more LED groups of the first light emitting unit according to a voltage level of the received drive voltage, determining the dimming level based on the PWM dimming signal, and controlling dimming of the one or more LED groups of the first light emitting unit based on the determined dimming level, and the second lighting module may include a second light emitting unit including one or more LED groups and a second drive controller sequentially driving the one or more LED groups of the second light emitting unit according to a voltage level of the received drive voltage.
The first drive controller may include an integrating circuit that receives the PWM dimming signal and outputs a dimming signal detected through integration of the received PWM dimming signal for a pulse period. The first drive controller may determine the dimming level based on an average voltage of the detected dimming signal.
The insulation type signal transceiver may include a light source that outputs light obtained through conversion of the PWM dimming signal from the PWM dimmer, and a photodetector that outputs an electrical signal obtained through conversion of the PWM dimming signal received in the form of light.
A color temperature of the one or more LED groups of the first light emitting unit may be different from that of the one or more LED groups of the second light emitting unit.
The insulation type signal transceiver may further include a noise filter that filters high frequency noise from the received PWM dimming signal.
The insulation type signal transceiver may further include a constant current control device that maintains current supplied to the light source at a constant level.
The insulation type signal transceiver may further include a reverse voltage protection diode that protects the LED lighting apparatus from reverse voltage applied thereto.
In accordance with yet another aspect of the invention, a smart illumination system includes at least one sensor unit including one of a motion sensor and a photo-detection sensor; at least one dimming unit connected to the sensor unit and determining a dimming level based on a detection signal from the motion sensor or the photo-detection sensor and outputting a PWM dimming signal based on the dimming level; and at least one lighting module connected to the dimming unit and receiving the PWM dimming signal and AC power to determine the dimming level based on the PWM dimming signal and to perform illumination while controlling dimming according to the dimming level.
The dimming unit may transmit the PWM dimming signal to the at least one lighting module connected to the dimming unit. Here, the dimming unit may be electrically insulated from the at least one lighting module connected to the dimming unit.
The lighting module may include a light source that outputs light obtained through conversion of the PWM dimming signal from the PWM dimmer, and a photodetector that outputs an electrical signal obtained through conversion of the PWM dimming signal received in the form of light.
In accordance with yet another aspect of the invention, a dimmable LED lighting apparatus includes: a reverse dimmer receiving a dimming level and outputting a reverse dimming signal by inverting the received dimming level; a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the drive controller; an LED group receiving the drive voltage and operating under control of the drive controller; and a drive controller reinverting the received reverse dimming signal into a dimming signal, determining a dimming level based on the dimming signal, and controlling dimming of the LED group based on the determined dimming level.
In accordance with yet aspect of the invention, a dimmable LED lighting apparatus includes: a reverse pulse width modulation (PWM) dimmer receiving a dimming level and outputting a reverse PWM dimming signal by inverting the dimming level; a power input unit generating drive voltage through rectification of received AC power and outputting the generated drive voltage to the drive controller; an insulation type signal transceiver receiving the reverse PWM dimming signal and outputting the reverse PWM dimming signal to the drive controller, while electrically insulating the reverse PWM dimmer from the drive controller; an LED group receiving the drive voltage and operating under control of the drive controller; and a drive controller reinverting the received reverse PWM dimming signal into a PWM dimming signal, determining a dimming level based on the PWM dimming signal, and controlling dimming of the LED group based on the determined dimming level.
According to one exemplary embodiment of the invention, in the structure wherein a plurality of lighting apparatuses is directly connected to a dimmer, failure of one LED lighting apparatus does not affect the other LED lighting apparatuses, thereby enabling normal operation of the other LED lighting apparatuses.
According to another exemplary embodiment of the invention, the lighting apparatus may be turned on/off using an inverted dimming signal without application of a new dimming signal, whereby the lighting apparatus can be normally operated at a maximum dimming level even in the event where there is a problem in the dimmer or the interconnection line or when a user does not want to use a dimming function.
According to a further embodiment of the invention, illumination with various color temperatures may be realized through dimming control of only one of LED groups having different color temperatures in a single lighting apparatus.
According to yet another embodiment of the invention, an illumination system includes a plurality of lighting apparatuses, each of which is systemically associated with other lighting apparatuses while allowing individual dimming control based on various sensing data including surrounding objects or surrounding illuminance obtained using sensors therein, thereby improving illumination efficiency and user convenience.


Ozone is applied to the interior of a mushroom house through use of an ozone generator which preferably communicates with an air conditioner so that the ozone flows from the ozone generator through the air conditioner and into the mushroom house. The ozone is applied during various stages of a mushroom growing process.

The growing of mushrooms is done under controlled conditions for a lengthy period of time. Various standard techniques are known. Some of these techniques are described in U.S. Pat. No. 6,018,906, all of the details of which are incorporated herein by reference thereto. As pointed out, two common techniques for mushroom cultivation are in the use of mushroom beds or shelves and in a tray system. Other methods of growing mushrooms have been the bag system, the ridge bed system and deep trough system. These systems, particularly the bed and the tray systems include two distinct phases. Phase I is generally done outdoors and involves composting the material to be used for cultivating the mushrooms. The compost is then conveyed into a mushroom house and fills the receptacles, such as beds or trays. In general, the compost is then heated to pasteurize the compost and ensure that the compost is free from most mushroom pests and diseases. The pasteurized compost then undergoes a cool down procedure. The pasteurizing step could take up to 14 days and the cool down procedure could take about 3 days. The next operation is the spawning where the compost is inoculated with mushroom mycelia by distributing particulate material colonized with mushroom mycelia (spawn) through the compost. The spawning run might take about 14 to 16 days. Next the colonized compost is covered by a layer of nutrient poor material or casing. The casing layer holds the moisture so that the mycelium must grow through the casing layer. The next step might be considered a flash step which occurs about twenty days after the mycelium breaks through the casing layer. The flash step is the first picking of cultivated mushrooms. Finally, after the mushroom heads break through the casing layer there is a final harvesting of the mushrooms. Reference is also had to U.S. Pat. Nos. 6,073,388 and 5,503,647, all of the details of which are incorporated herein with regard to mushroom growing techniques.
In order to provide the best form of cultivated mushrooms under these controlled conditions it would be desirable if there were some assurance of having the mushroom house in a sterilized condition to prevent outside contamination interfering with the mushroom growth. It has been known in other fields to use ozone as a means of sterilization. The use of ozone in connection with the growing of mushrooms, however, has not heretofore been contemplated. One reason, perhaps is that ozone might be considered to create detrimental aesthetic and health affects if the ozone contacts the mushrooms.
Parent application Ser. No. 11/320,279 discloses providing ozone treatment to a mushroom house by having an ozone generator assembly communicating with ozone distributing structure located within the house or enclosure to feed the ozone into the enclosure and around the mushroom growing receptacles in the enclosure. As disclosed in that application the ozone generator assembly is located externally of the enclosure while the ozone distributing structure within the enclosure communicates with an inlet in the wall of the enclosure and has spaced discharged outlets. The ozone distributing structure also includes a hose within the enclosure mounted at the inlet and communicating with a plenum in the enclosure. The plenum has a heat pump and a blower to facilitate feeding the ozone into a manifold having spaced discharged outlets at spaced locations within the enclosure.
Korean patent KR2005114763A appears to disclose a structure for sterilizing the mushroom culture itself through the use of various materials including ozone which are applied directly into the mushroom culture. As illustrated in that Korean patent an ozone generator communicates with a pipeline having supply pipes that penetrate into seal grooves and the culture containers. In this manner the ozone is supplied directly into the culture containers to penetrate into the culture medium. The drawing apparently also illustrates a reduction catalyst supply, an oxygen generator, a humidifier, an air conditioner and a vacuum pump which are all constructed as part of a single circulating circuit with the ozone generator to connect the pipeline in the control chamber with the pipeline and discharge the material flowing therethrough to go directly into the culture medium. The intent is apparently to treat the spawn whereby not only ozone, but also, for example, a catalyst and oxygen are applied directly into the culture. This disclosure differs significantly from the techniques described in the parent application Ser. No. 11/320,279. In that regard, in the parent application the ozone is fed directly into the general atmosphere in the interior of and throughout the mushroom house since it is the interior of the house which is intended to be sterilized. In contrast with the Korean patent, the ozone is intended to sterilize the culture medium itself and in all likelihood would not be of sufficient quantity to flow through and exit from the culture medium to have any significant sterilizing affect on the atmosphere in the interior of the mushroom house or enclosure.


An electromagnetic accelerator arrangement includes a stationary arrangement including at least one stationary primary coil, and a movable arrangement including at least one moveable secondary coil. The planes of the stationary and the moveable coils are parallel to a direction of movement of the moveable arrangement. The coils of the stationary and the movable arrangements have approximately the same coil width in the direction of movement of the moveable arrangement and transversely thereto, as well as the same coil separation in the direction of movement of the moveable arrangement. The at least one stationary primary coil includes at least two layers between which the at least one secondary coil of the movable component is movably disposed, the distance between the layers being kept small transversely to the direction of movement of the moveable arrangement.

1. Field of The Invention
The invention relates to the field of electromagnetic accelerators, in particular to electromagnetic catapults.
2. Background Information
The acceleration of flying bodies or projectiles with the aid of electromagnetic catapults has known advantages over conventional driving methods operating on the basis of internal combustion engines or by using explosion pressure. Electromagnetic accelerators can be technologically grouped with linear drives or motors, but are characterized by very short periods of operation. Compared to the conventional design of linear motors, for example as used in automobile transportation, in electromagnetic accelerators, extraordinarily high force densities are realized if the loads occur only very briefly.
A basic electromagnetic accelerator includes a primary coil arrangement for a stationary portion and a moving translator equipped with one or a plurality of secondary coils. The respective motion state, i.e., position and velocity, of the translator must be taken into account in determining the energy requirements of the coils for operation. The necessary electrical power depends on the mechanics of the acceleration process, that is, on mass, final velocity and acceleration path. However, it is also very much determined by the efficiency of the conversion of electrical energy into mechanical energy. The latter is a function of the intensity of the interaction between the magnetic field and the electrical currents. The field-current interaction is also closely interrelated with the forces acting on the coils. Since a relatively inefficient field-current interaction requires the use of increased electrical currents to obtain the required accelerating force, this also creates power loss problems and consequently higher thermal effects. The realizability of very high performance transducers therefore depends greatly on the intensity and efficiency of the current-field interaction.
In the topology of conventional coaxial, cylindrical coil electromagnetic accelerator, in which stator coils and translator coils form a circularly cylindrical arrangement, conditions are rather unfavorable and result in inefficient electromechanical energy conversion, as well as high mechanical and thermal stresses on the coils.

Electromagnetic accelerator in flat coil arrangement


Methods, systems, and apparatuses related to edge processing of sensor data using a neural network to reduce network traffic to and/or from a server. In one approach, a cloud server processes sensor data from a vehicle using an artificial neural network (ANN). The ANN has several layers. Based on analyzing at least one characteristic of the sensor data received from the vehicle and/or a context associated with processing the sensor data, the cloud server determines to send one or more of the layers of the ANN for edge processing on the vehicle itself. In other cases, the cloud server decides to send the one or more layers to an edge server device located on a communication path between the vehicle and the cloud server. The edge processing reduces network data traffic.

Recent developments in the technological area of autonomous driving allow a computing system to operate, at least under some conditions, control elements of a motor vehicle without the assistance from a human operator of the vehicle.
For example, sensors (e.g., cameras and radars) can be installed on a motor vehicle to detect the conditions of the surroundings of the vehicle traveling on a roadway. A computing system installed on the vehicle analyzes the sensor inputs to identify the conditions and generate control signals or commands for the autonomous adjustments of the direction and/or speed of the vehicle, with or without any input from a human operator of the vehicle.
In some arrangements, when a computing system recognizes a situation where the computing system may not be able to continue operating the vehicle in a safe manner, the computing system alerts the human operator of the vehicle and requests the human operator to take over the control of the vehicle and drive manually, instead of allowing the computing system to drive the vehicle autonomously.
Autonomous driving and/or an advanced driver assistance system (ADAS) can use an artificial neural network (ANN) for the identification of events and/or objects that are captured in sensor inputs. Examples of sensor inputs include images from digital cameras, lidars, radars, ultrasound sonars, etc.
In general, an artificial neural network (ANN) uses a network of neurons to process inputs to the network and to generate outputs from the network. For example, each neuron in the network receives a set of inputs. Some of the inputs to a neuron may be the outputs of certain neurons in the network; and some of the inputs to a neuron may be the inputs provided to the neural network. The input/output relations among the neurons in the network represent the neuron connectivity in the network.
For example, each neuron can have a bias, an activation function, and a set of synaptic weights for its inputs respectively. The activation function may be in the form of a step function, a linear function, a log-sigmoid function, etc. Different neurons in the network may have different activation functions. The relations between the input(s) and the output(s) of an ANN in general are defined by an ANN model that includes the data representing the connectivity of the neurons in the network, as well as the bias, activation function, and synaptic weights of each neuron.
For example, the inputs to an ANN network may be generated based on camera inputs; and the outputs from the ANN network may be the identification of an item, such as an event or an object.

Edge processing of sensor data using a neural network to reduce data traffic on a communication network


An optical beam scanning apparatus of this invention includes rotary optical element rotating on an axis of rotation and guiding optical beams incident parallel to the axis of rotation to a direction rectangular to the axis of rotation so as to scan a cylindrical surface inside a cylinder by rotating the optical beams in a peripheral direction. An anamorphic optical system rotating on a straight line substantially coinciding with the axis of rotation, for example, is disposed as optical beam rotation element on the incident side of the optical beams of the rotary optical element, and the optical beams incident into the rotary optical element are rotated at the same rotating speed as that of the rotary optical element on the straight line as the axis of rotation. According to this structure, a plurality of optical beams do not corss one another on the cylindrical surface when they are used, but form substantially parallel beam lines. Accordingly, multiple beam scanning as well as high speed recording becomes possible.

1. Field of the Invention
The present invention relates to an optical beam scanning apparatus in the field of the technique of recording images by scanning optical beams such as laser beams. More particularly, the present invention relates to an optical beam scanning apparatus of the type effective for a system where a combination of large format and a small focussed beam diameter is required, such as a plotters for graphic arts or a film plotter for generating printed-circuit-board artwork.
2. Description of the Related Art
Optical beam scanning apparatus of this kind includes an image recording method which is referred to as an "Internal drum scanning configuration: and records an image by rotating and scanning optical beams inside a cylinder in its peripheral direction with respect to a photosensitive material fitted to a cylindrical surface of a fixed drum (hereinafter referred to as the "cylinder") (Japanese Unexamined Patent Publication No. 63-158580).
According to this configuration, the photosensitive material is loaded to the cylindrical surface of the cylinder. The optical beams from a light source are allowed to be incident along a central axis of the cylinder, and are reflected in a rectangular direction inside the cylinder by an optical reflection device (hereinafter referred to as the "rotary reflection device") such as a reflecting mirror or a rectangular prism which is rotated by a motor with the central axis of the cylinder being the axis of rotation. The optical beams are then condensed by a condenser lens in an optical path, and the optical beams thus condensed are scanned (hereinafter primary scanning) on the photosensitive material loaded to the cylindrical surface of the cylinder. The motor, the rotary reflection device and the condenser lens are moved in an axial direction by a driving mechanism (hereinafter subsidiary scanning), and in this way, an image is recorded (exposed).
The photosensitive material can be fitted to the cylindrical surface by retaining it on the inner surface of the cylinder, or by retaining it on an outer surface of a cylinder made of a transparent member.
According to this configuration, the optical beams which are incident substantially parallel to the axis of rotation are reflected substantially in the rectangular direction by the rotary reflection device rotating on the central axis of the cylinder as the axis of rotation thereof, so that the photosensitive material loaded to the cylindrical surface can be scanned and exposed.
The reflecting direction of the optical beams is not necessarily right angle. If they are reflected in a direction different from the right angle, the distance between the reflection point and the exposure point becomes large, and the size of the optical beams on the cylindrical surface in the axial direction of the cylinder becomes large, as well. The reflecting direction may differ from right angle within such a range where the increases in the distance and the size described above do not exert adverse influences in practice.
The advantage brought forth by this configuration is that a rotating speed can be increased and hence, a recording speed can be increased more easily because a moment of inertia in this system is smaller than that in a rotating drum configuration.
Further, the photosensitive material can be held stably in place because it is fixedly hold on the cylinder. Subsidiary scanning can be carried out by sliding the photosensitive material on the cylindrical surface but in this case, there occur the problems in that a subsidiary scanning speed becomes unstable due to friction and the photosensitive material is likely to be damaged. Unless sliding is effected smoothly, floating of the photosensitive material might occur. In the case of multiple beam recording, the photosensitive material must be kept stably so that exposure by the final beam of multiple beams can be correctly followed by the exposure by the leading beam of a subsequent primary scanning.
Subsidiary scanning may be effected by moving a part, or the whole, of an optical system including the rotary optical means in the axial direction of the cylinder. It may be effected, too, by fixing the optical system and moving the cylinder having the photosensitive material fixed thereto as a whole, on the contrary.
Another advantage of this configuration is that a relatively large recording format can be obtained by the use of a condenser lens having a small focal length in comparison with a so-called "flat-field scanning method".
The advantage obtained by the use of a lens having a small focal length is that a small condensed beam diameter necessary for recording high image quality can be obtained easily, and the scanning line interval can be reduced, too. Furthermore, it is easy to keep the beam diameter and the beam shape on the cylindrical surface substantially constant throughout substantially the full periphery by accurately adjusting the axis of rotation of the rotary reflection device with the central axis of the cylinder. Accordingly, image quality can be improved more easily.
A scanning width of from about 70 to about 80% of the full peripheral length of the cylinder is easily obtained even when limitations from mechanical arrangement of inlet and outlet openings for the photosensitive material, the rotation mechanism of the rotary reflection device and the mechanical arrangement of the subsidiary scanning mechanism, and so forth, are taken into consideration. The focal length of the condenser lens is somewhat greater than the radius of the cylinder, and a scanning width about three times the focal length can be obtained easily. Accordingly, a recording size, too becomes sufficiently large.
By the way, the condenser lens may be disposed in the optical path between the rotary reflection device and the photosensitive material, and may be rotated integrally with the rotary reflection device. In this case, there occurs a disadvantage that the moment of inertia of the rotating members increases, but the focal length of the condenser lens can be further made smaller than the radius of the cylinder and a smaller condensed beam diameter can be obtained more easily. On the contrary, there is the advantage that the diameter of the beams incident into the condenser lens can be reduced in order to obtain a predetermined condensed beam diameter.
The explanation given above can be summarized as follows. In accordance with the internal drum scanning configuration, the moment of inertia of the rotating members is small, so that the rotating speed can be increased easily and hence, the recording speed can be increased easily. It is easy to simultaneously satisfy the requirements for image quality and the recording size, and the size of the apparatus can be reduced easily to obtain the same recording size.
As described above, the optical beam scanning apparatus according to the conventional internal drum scanning configuration has the advantages described above and can easily increase the rotating speed and hence, the recording speed. Nonetheless, in order to further increase the recording speed by a single optical beam, the rotary reflection device must be rotated at an extremely high revolution speed which usually has practical limitation. To further increase the recording speed, therefore, a multiple beam scanning method is used in combination. In this case, however, the use of multiple beams is difficult, and the recording speed cannot be increased so easily.
The multiple beam scanning method is the system which utilizes a plurality of optical fibers, etc., as a light source, and effects primary scanning several times per rotation by the use of a plurality of optical beams.
The reason why the multiple beam scanning method is difficult to use is because when a plurality of optical beams are reflected by the rotary reflection device to scan on the cylindrical surface, these optical beams cross one another at two oppositions on the cylindrical surface and do not form parallel scanning lines necessary for image recording.
Even when recording is carried out only within a part of the range of the cylinder but not throughout the full periphery, a plurality of optical beams undergo curving, even though they do not cross one another, and are not suitable for multiple beam scanning for image recording.
To solve this problem Japanese Unexamined Patent Publication Nos. 59-119960 and 57-151933 disclosed a method which mounts a plurality of light sources, or a plurality of light sources together with their driving circuits, on a rotary member disposed inside a cylinder, and rotates the rotary member with the central axis of the cylinder being an axis of rotation thereof, so as to accomplish multiple beam scanning.
According to this method, however, it is necessary to mount a plurality of light sources, an electronic circuit for modulating them, a power generator for supplying power to the electronic circuit, a power source stabilization circuit, and so forth, to the rotary member. Furthermore, a mechanism for stably holding these circuits on the rotary member must be disposed. Accordingly, when the rotary member rotates, its moment of inertia is great, and there is a limit to obtain a high rotating speed.


A microwave oven includes a protective cover for enclosing a choke PCB, on which a choke device and a fuse are mounted, whereby moisture is not formed on the choke device and fuse, and the choke device and fuse are protected against contact. The accidental protective cover has vent slots and is provided near a rear plate forming one portion of the housing of the microwave oven. Air slots, through which outside air is drawn, are formed on a portion of the rear plate that faces the vent slots of the protective cover.

(1) Field of the Invention
The present invention relates to a microwave oven, and more particularly, to a choke printed circuit board including a choke means mounted thereon, which is provided in the electric component compartment.
(2) Description of the Prior Art
Generally, a microwave oven is a cooking appliance which cooks food by frictional heat generated by making the molecules of the food being cooked move at high speeds utilizing high frequency energy. FIG. 3 illustrates the inner structure of a prior art microwave oven.
As shown in the figure, the microwave oven includes a housing 10 which consists of an inner case 12 and an outer case 11, and a cooking chamber 20 and an electric component compartment 40 which are isolated from each other by the inner case 12 for forming the cooking chamber 20 and the outer case 11. On the front side of the inner case 12 is rotatably mounted a door 30 to open and close the cooking chamber 20 and is attached a control panel 31i ncluding a display and several operating buttons. The electric component compartment 40 is provided in the space formed between the inner case 12 and the outer case 11. In the electric component compartment 40 are mounted a magnetron 41 for creating microwaves and emitting them to the cooking chamber 20, a guide duct 44 for guiding air drawn into the electric component compartment 40 to the cooking chamber 20 through the intake holes 45 formed on the side plate of the inner case 12, a high-voltage transformer 42 for applying high voltage to the magnetron 41, and a cooling fan 43 for cooling the electric components.
The cooling fan 43 is mounted in the center of the motor bracket 47 which is attached to the inner side of the rear plate enclosing the electric component compartment 40. On the top of the motor bracket 47 is mounted a choke printed circuit board 46 (hereinafter called choke PCB) which includes a choke means 46 a for eliminating noises included in the input power and a fuse 46 b to protect the electric components in the electric component compartment 40.
The choke means 46a and fuse 46b being uncovered in the electric component compartment 40 can have damaging, and possibly dangerous, results: When the cooling fan 43 operates, air is heat-exchanged with the magnetron 41, directed to the cooking chamber 20, and then discharged outside. At this time, a portion of the air passing through the microwave oven re-enters the electronic component compartment 40. Accordingly, moisture is generated in the electric component compartment 40 due to the temperature difference between the re-entered air and newly entered air. If it contacts the choke means 46a or the fuse 46b, which are exposed in the electric component compartment 40, a short circuit may be caused, thereby resulting in damage to the machine and a possible fire hazard. Furthermore, when a repair man inspects or repairs the microwave oven after disassembling the outer case 11, he may receive an electric shock by contacting the choke means 46a or the fuse 46b charged with electricity. Lastly, because the top surface of the exposed choke PCB 46 becomes covered with dust, the parts on the choke PCB 46 may not function properly.

Microwave oven with enclosed choke printed circuit board


A motorcycle stand includes first and second legs pivotable relative to one another between a maximum spread configuration, an intermediate spread configuration, and a storage configuration; the legs being generally parallel to one another when at the storage configuration. The motorcycle stand includes a biased plunger operatively coupled to the first leg and a pin operatively extending from at least one of the first and second legs. The second leg includes a first cavity configured to receive the plunger when the first and second legs are at the intermediate spread configuration. The first and second legs are maintained at the intermediate spread configuration when the plunger is received in the first cavity. The pin includes a distal segment for insertion in a motorcycle axle, the distal segment being neither parallel nor perpendicular to the first and second legs.

This invention relates generally to motorcycle stands and, more particularly, to a motorcycle stand for use in holding a motorcycle in a parked position upon uneven terrain.
Motocross type motorcycles are particularly adapted for riding in rugged off-road environments. Such motorcycles may be ridden for long periods of time in relatively remote areas where the land is not level and places to "park" the motorcycle when not being ridden are usually not available. In such circumstances, the motorcycle may have to be laid on its side or rested against a tree as motocross motorcycles typically do not have kickstands, either because it will not work well in the rugged terrain being ridden in or because it may be in the way while riding.
As an alternative, some motocross manufacturers provide a triangle shaped motorcycle stand that fits into a wheel hub to prop the motorcycle up when parked. Although assumably effective for its intended use, the triangle shaped motorcycle stand takes up an undesirable amount of space and is difficult to transport when not in use. In addition, such a stand is not effective when used on terrain that is not level.
Therefore, it would be desirable to have a motorcycle stand for propping up a motocross type motorcycle when it is parked and which is foldable for being carried easily when the motorcycle is being operated. Further, it would be desirable to have a motorcycle stand having two legs that are movable between selected spread positions and which is length adjustable for use on land that is not level.


A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.

Vertical Hall sensors have the advantage that they can be manufactured using conventional semiconductor technology (e.g. CMOS). They have, however, the disadvantage that they suffer from a relatively high offset voltage compared to horizontal Hall sensors. The offset voltage is the voltage measured when no magnetic field is present.
The measurement error due to offset voltage can be decreased by several techniques, such as for instance the spinning current technique. In this technique, the supply and readout contacts are cyclically interchanged. In one phase the offset is then added to the magnetic signal with positive sign and in the other phase with negative sign. By averaging both phases, the offset can typically be reduced more than 100 times.
A Hall sensor may be represented as a distributed resistive Wheatstone bridge. In order for the spinning current technique to be effective it is important that electrical symmetry exists within the vertical Hall sensor (i.e. that all resistors in the resistive Wheatstone bridge have about the same value). A vertical Hall element, however, does not provide this electrical symmetry by default since all contacts are on one side and since the active area (e.g. an n-well) only has a limited depth. Therefore, in practice, rather than a factor 100, the offset is only reduced by a factor 5-10 after applying the spinning current technique. Moreover, the residual offset is temperature dependent and the dependency is non-linear. This requires a time consuming calibration procedure.
EP1540748 discloses a magnetic field sensor with a Hall element that has two inner and two outer contacts arranged along a straight line. The contacts are arranged on the surface of a well of a first conductivity type embedded in a substrate of a second conductivity type. A first of the two outer contacts and a first of the two inner contacts which are not adjacent contacts act as supply contacts to which a current can be applied, and the second of the two outer contacts and the second of the two inner contacts act as sense contacts for tapping a Hall voltage. A first resistance is provided between the first contact and the second contact, a second resistance is provided between the second and the third contact, a third resistance is provided between the third and the fourth contact, and a fourth resistance is provided between the first and the fourth contact. The resistance values of the first, second and third resistances are substantially equal. An additional resistance is furthermore provided, coupled in parallel to the fourth resistance, and having a resistance value selected such that the parallel resistance value of the fourth and the additional resistance is substantially equal to the resistance value of any of the first, second or third resistances. This way, the equivalent Wheatstone resistor bridge is balanced. With proper dimensioning of the additional resistor this works and can reduce to zero the residual offset after spinning. However, this works only at one fixed operation condition concerning biasing voltage and temperature. If any of these two parameters varies, the matching is disturbed by additional effects arising from the non-perfect symmetry between inside and outside contacts, leading to a strong increase of the residual offset.
The minimum magnetic flux density which can be accurately measured depends on the offset error of the vertical Hall sensor: the smaller the offset error, the more accurately a magnetic flux density can be measured. Therefore, in view of the difficulty in reducing offset errors, there is still room for improvement in vertical Hall sensors.

Vertical hall sensors with reduced offset error


A tiled display structure having a plurality of display tiles. Each display tile comprising a tile substrate, first electrodes located on a first side of the tile substrate, light emitting or controlling materials deposited over the first electrodes, and second electrodes deposited over the light emitting or controlling material. A back panel is provided having a plurality of back-panel conductors located on a first side of the back panel. The display tiles are mounted upon the back panel with the first side of the tile substrate adjacent to the first side of the back panel and the first and second electrodes electrically connected from the first side of the tile substrate through electrical standoff connectors to the back-panel conductors.

Electronic display systems are commonly used to display information from computers. Typical display systems range in size from small displays used in mobile devices to very large displays visible to thousands of viewers. Large displays are sometimes created from tiling smaller display devices together. For example, video walls using multiple video displays are frequently seen in the electronic media and flat-panel displays are tiled to create larger displays. Multiple projector systems used to create a large, tiled, high-resolution display are also available.
Tiled displays are well known in the prior art. For example, U.S. Pat. No. 6,683,665B1 issued Jan. 27, 2004 describes tile structures wherein each tile has a display portion and an electronics portion. The tiles are fastened together into an array with the use of a frame. Alternatively, U.S. Pat. No. 6,498,592 issued Dec. 24, 2002 describes the use of a single substrate with electrical devices and a display. However, as disclosed, these designs require the use of vias (electrical connections) through the electronics substrates and are problematic for displays requiring a hermetic seal for the display components, for example in an OLED display. Vias in glass substrates are difficult to construct and the use of alternative substrates are not well-suited to sealing the display materials. Moreover, the design requires an additional frame and is not well suited to roll-to-roll manufacturing.
Another technique that relies on overlapping the display tiles is described in WO 03/042966 entitled "Display for a Large Panel Display Consisting of Tiled Displays". This method uses a complex support structure and a plurality of printed circuit boards. Moreover, tile seams may be visible when the display is viewed off angle.
Connections providing an electrical connection between two surfaces that are not physically touching are known. See for example, U.S. Publication 2004/0016568 entitled "Low-Cost Circuit Board Materials and Process for Area Array Electrical Interconnections over a Large Area between a Device and the Circuit Board" by Palanisamy published Jan. 29, 2004.
There is a need therefore for an improved tiled display system that overcomes the problems noted above.


A communications interface circuit couples a host processor to a pair of serial communications links. A shared memory is employed to pass message data and network management data between the host and the interface circuit, and each can interrupt the other through interrupt control lines. The shared memory stores a handshake segment that includes interrupt flags and acknowledge flags which enable a large number of different interrupt events to be efficiently serviced.

The field of the invention is serial communications networks and, particularly, interface circuits for connecting digital processors to serial communications networks.
There are numerous serial communications networks found in businesses and in factories. In the business environment, for example, local area networks sold under the trademark "Ethernet" link personal computers, display terminals, minicomputers, mainframe computers, printers and disk drives together into a system in which data may be transferred rapidly between its components. Similarly in the factory environment, local area networks sold under the trademark "MAP" link together cell controllers with display terminals, minicomputers, mainframe computers, computer aided design systems, computer aided manufacturing systems, computer aided engineering stations and disk drives. The types of serial communications networks have proliferated, and while efforts have been made to standardize communications in certain environments, there currently are hundreds of different networks in use and the number continues to grow.
When designing digital processors for use in a commercial environment, one must select a strategy for connecting that processor to serial communications networks. For example, where the processor has a backplane, such as "VME BUS" or "MULTIBUS", a circuit board for that backplane may be designed for each communications network. A variety of processor circuit boards and communications interface boards can be designed for the backplane and used together in any combination. On the other hand, where the digital processor does not employ a backplane, the interface to the communications network may be constructed as an integral part of the digital processor. In such case, each digital processor must be designed and constructed to operate on a particular communications network, and if many networks are encountered, a processor with integral interface circuit must be offered for each network. In other words, if a manufacturer offers a series of three digital processors of varying power and capability, and those processors must operate on three different communications networks found in their environment, then six circuit board products must be offered if a common backplane architecture is used, or nine different products must be offered if the communications interface is an integral part of the processor.
Where the manufacturer offers a wide variety of digital processor products of varying architectures and numerous communications networks are encountered in the environment in which those processors are used, difficult choices must be made. For example, the Allen-Bradley Company, assignee of the present application, manufactures small, inexpensive programmable controllers such as those disclosed in U.S. Pat. No. 4,504,927, and programming terminals such as that disclosed in U.S. Pat. No. 4,527,250, which do not employ a backplane. They also offer medium sized programmable controllers such as those disclosed in U.S. Pat. No. 4,443,865 that employ one backplane, large programmable controllers such as that disclosed in U.S. Pat. No. 4,442,504 that employ another backplane, numerical controllers such as that disclosed in U.S. Pat. No. 4,228,495 that employs yet other backplanes, and cell controllers such as that disclosed in co-pending U.S. patent application Ser. No. 928,529 filed on Nov. 7, 1986, which employs still another backplane. Obviously, it is not commercially feasible to provide communications interface modules or circuits for each of these processor products and for each of the communications networks that may be encountered by them in the factory.

Interrupt structure for network interface circuit