Provided is a cargo lift and transport device which affixes to a frame mounted motor vehicle-to-trailer hitch interface having two mounting positions. The cargo lift and transport device provides a connector that receives and locks into a female-to-female adapter which locks into the female receiver connector of the frame mounted motor vehicle-to-hitch interface. The device provides a second female connector for lockably receiving a male connector affixed to and adjacent a cargo platform. The cargo lift and transport device provides means for selectively moving the second female connector in the vertical plane with enough force to overcome the resistance of friction and the weight of the cargo to be transported. In the first mounting position, the cargo lift and transport device, so mounted, operates to lower the cargo platform to the ground level (H) for loading or unloading of the cargo, and then to raise the cargo platform to a variable, but safe, transportation height (H') of the user's selection. In the second mounting position, the cargo lift and transport device, so mounted, operates to lift the cargo platform from the H' position to a higher variable (H") position.

The trailer towing industry has adopted standardized motor vehicle-to-trailer hitch interfaces in order to simplify and make more compatible the towing-related products of various manufacturers. This standardization has contributed to the wide availability of many products, typically in the nature of trailers, that enable one to tow cargo behind a motor vehicle. Many of the motor vehicle-to-trailer interfaces provide a frame for affixing to the vehicle, and further provide an attachment having a ball joint for use in mating a trailer thereto.
Platforms and lifts are also known in the cargo handling and transportation industry. Typically, a lift, including a platform, is mounted to the back of a cargo transportation truck. Cargo may be placed on the platform, raised to the level of the truck bed, and then placed into the truck for transport. In such applications, the platform must often be stowed in a vertical position during transport. This stowing configuration is sometimes disadvantageous to the broader application and use of such devices for the reason that such devices often are not conducive to transporting the cargo upon the platform while in its, horizontal position. Additionally, such devices often are not conducive to mounting on motor vehicles other than trucks.
In an attempt to overcome some of these deficiencies, a variety of lift and tow devices have been proposed. Examples of such devices may be found by reference to U.S. Pat. No. 5,122,024 to Stokes; U.S. Pat. No. 5,366,338 to Mortensen; and U.S. Pat. No. 5,482,424 to Jones et al. In light of the present invention, however, these devices are disadvantageous. For instance, the respective platforms of Stokes, Mortensen, and Jones et al. can not be raised above the height of the automobile's trailer hitch. As a result, these devices and their cargo can be damaged during off-road maneuvers due to the close proximity to the ground. Additionally, because of the limitation in the range of motion of the above-referenced devices, their uses are also notably limited.
While devices of the above-described type may be effective for certain applications, there remains a significant need in the industry for an effective cargo lift and transport device which can be easily fit into a standard motor vehicle-to-trailer hitch interface, without significant modification to either the vehicle or the vehicle-to-trailer hitch and can lift the cargo to a safe distance from the ground, and that can additionally serve to lift a multitude of cargo for numerous applications.
In order to be effective for its purpose, such a device should be able to be mounted on motor vehicles of types other than large cargo trucks, such as automobiles, light duty trucks, sport utility vehicles, or all-terrain vehicles. Such a device should further be adjustable to allow a multitude of vertical positions to serve the purpose of a plurality of applications. Additionally, such a device should be capable of carrying a relatively heavy load, such as a motorcycle or a motorized wheelchair, in a stable and secure manner. Such a device should be semi-permanent, but easily removable for storage.
Accordingly, the several objects of the present invention are:
to provide a cargo lift and transport device that can easily fit into a standard motor vehicle-to-trailer hitch interface; PA1 to provide an effective cargo lift and transport device that can easily fit into a standard motor vehicle-to-trailer hitch interface without significant modification to either the vehicle or the vehicle-to-trailer hitch; PA1 to provide a cargo lift and transport device that is reversible to allow a greater degree of vertical mobility; PA1 to provide a cargo lift and transport device that is adjustable to provide various vertical positions to accommodate a multitude of vehicles and applications; PA1 to provide a cargo lift and transport device that can be mounted on motor vehicles of types other than large cargo trucks; PA1 to provide a cargo lift and transport device that is capable of carrying a relatively heavy load in a stable and secure manner; PA1 to provide a cargo lift and transport device that is semi-permanent, but easily removable for storage; PA1 to provide a cargo lift and transport device that is durable in construction and economical to manufacture; PA1 to provide a cargo lift and transport device that is convenient to install and to maintain; and, PA1 to provide a cargo lift and transport device that is safe and reliable in operation.
It is the solution to these and other problems to which the present invention is directed.

Cargo lift and transport device for motor vehicle


A reflector reflects a light from a light source. A projector lens projects a reflected light from the reflector ahead of a vehicle. A shade is used to switch the reflected light into a plurality of beams in a plurality of light distribution patterns. A spring member and a drive unit switch a position of the shade between an obliquely upward and backward position and an obliquely downward and forward position to obtain the light distribution patterns.

1. Field of the Invention
The present invention relates to a bifunctional-type vehicle headlamp, such as a projector-type vehicle headlamp, capable of obtaining a plurality of light distribution patterns including a low-beam light distribution pattern and a high-beam light distribution pattern.
2. Description of the Related Art
A conventional projector-type vehicle headlamp as disclosed in Japanese Patent Application Laid-open No. 2003-59311 includes a light source, a reflector, a projector lens, a shade, a spring member, and a solenoid.
When the light source lights up, a light emitted from the light source is reflected to the sides of the shade and the projector lens by a reflecting surface of the reflector. Then, the reflected light is projected ahead of a vehicle by the projector lens. At this time, a position of the shade is switched among a plurality of positions by the actions of the spring member and a retractable rod of the solenoid. As a result, the reflected light towards the projector lens is also switched among a plurality of beams in a plurality of light distribution patterns.
However, in the conventional vehicle headlamp, a position of the shade is switched in an upward direction or a downward direction (in a vertical direction), so that a direction in which a spring force of the spring member acts is also the vertical direction. Therefore, in a case in which a dome-shaped spring, for example, a spring member 60 shown in FIG. 4, is used as the spring member, a height of the spring member 60 viewed from the front and lateral sides disadvantageously increases, and thus a height of the entire vehicle headlamp also increases.


The object of the present invention is to provide a patient carrying device so adapted as to allow the patient take a comfortable posture or to freely carry the patient between the bed and the toilet, the bath-tub or otherwise desired locations.. The patient carrying device is provided with a first mobile vehicle 10A and a second mobile vehicle 10B, each capable of freely running along rails 4 with its second motor 12. Each of the first mobile vehicle 10A and the second mobile vehicle 10B is further provided with a rotating wheel 15 for winding up or down a suspending rope 17 and a first motor 12 for driving the rotating wheel 15. The first motor 12 and the second motor 13 are operated in a pre-programmed fashion by operating the button of a remote controller 30. Therefore, for example, when the "Bath" button 31 is operated, the first mobile vehicle 10A and the second mobile vehicle 10B are automatically operated to lift the patient and carry the patient to the bath-tub by adjusting the distance between their mobile vehicles, moving them along the rails 4, rolling up or down the suspending ropes 17 with the aid of the rotating wheels 15, and carrying out the otherwise actions.

The present invention relates to a patient carrying device for carrying a patient, who cannot freely travel by oneself and keeps laying on the bed, from the bed to the bath, the wheelchair, the toilet or otherwise locations nearby the bed.
The present inventor has previously proposed a bed device for a patient who cannot travel freely from a bed (Japanese Patent Publication No. 4-78,306). As shown in this publication, the bed device comprises locating X-rails 3 and 4 and Y-rails 6 and 7 over a bed 50 and transferring an X-frame 5 and a Y-frame 8 in an X-direction and a Y-direction, respectively, thereby functioning so as to transfer a lifting apparatus 2 for lifting the patient body in the identical direction and allowing the patient to be carried to the bath-tub, the toilet or otherwise locations.
However, as the proposed bed device is structured in such a manner that the patient is allowed to travel to the objective location such as the bath-tub, the toilet, and so on, by transferring the X-frame 5 and the Y-frame 8 in the X-direction and the Y-direction, respectively, the device itself becomes so complicated in structure, large in size and heavy in weight that it is difficult to be disposed in average houses.


An improved retractable court standard is described. The retractable court standard typically comprises a plurality of elongated tubular sections and an elongated top section. Each of the elongated tubular sections has a top end and a bottom end, and different dimension. Additionally, the elongated top section typically has a top end and a bottom end, and a net securing assembly coupled proximal the top end. At least one elongated tubular section is slidably and rotatably disposed within another circumferentially adjacent elongated tubular section. Importantly, the at least one elongated tubular section has one of at least one rotational locking channel and at least one securing pin. The circumferentially adjacent elongated tubular section has the other of the at least one rotational locking channel and the at least one securing pin. Methods of extending, retracting, and storing the improved retractable court standard are also described.

Court standards are used as a base or support for objects, such as nets, for use when playing a sport or game. Court standards are typically permanently mounted or removably mounted to a court. For instance, a large standard to support a volleyball net usually has large, heavy base stand that sits on the court floor to adapted to support the standard. In some instances, a small subsurface well exists into which a small portion of the large standard may be placed.
Transferring large standards such as volleyballs poles can be extremely dangerous. Such large standards are heavy and awkward to carry, particularly if a person or persons are carrying one or more large standards a relatively long distance or up and down a flight of stairs. Additionally, large standards are difficult to store as few (if any) closets or storage areas in school gymnasiums, for instance, have adequate storage space close to the actual court floor. Hence, the large standards are haphazardly placed against a wall or laid on the floor where student and faculty may trip over or otherwise injure themselves. Permanently mounting court standards for various types of sports and activities eliminates the transporting hazards and storing problems, but introduces additional issues such as limited use of the gymnasium floor when the court standard are continually exposed.
Moreover, physical education conducted in a school gymnasium typically includes a variety sports and activities including, but not limited to, volleyball, wheel chair volleyball, tennis, badminton, pickle ball, and tetherball. Therefore, associated court standards sized for the specific sport or activity is typically required. Heretofore, a court standard with a safe, quick, and easy set-up and storage thereof adapted for a plurality of uses remains a desirable apparatus for persons who regularly configure a variety of courts.

Retractable court standard and methods of use


A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output command/address signals and receives temperature codes. The second semiconductor device may sense an internal temperature if a combination of the command/address signals is a first combination, generate and output the temperature codes having a combination corresponding to the internal temperature if a combination of the command/address signals is a second combination, and adjust a period of the temperature codes in accordance with a temperature section of the internal temperature.

1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices and a semiconductor system relating to an internal temperature and temperature codes.
2. Related Art
In the electronics industry, highly integrated fast volatile memory devices such as high performance dynamic random access memory (DRAM) devices widely used as memory devices are increasingly in demand with the development of high performance electronic systems such as personal computers or communication systems. In particular, when semiconductor devices such as the DRAM devices are employed in cellular phones or notebook computers, the semiconductor devices have to be designed to have an excellent low power consumption characteristic. Accordingly, a lot of effort has been focused on reducing operation currents and standby currents of the semiconductor devices.
A data retention characteristic of a DRAM cell including a single transistor and a single storage capacitor may be very sensitive to temperature. Thus, it may be necessary to control operation conditions of internal circuit blocks in a semiconductor device according to variation of an ambient temperature. For example, DRAM devices employed in mobile systems may be designed to control a refresh period according to variation of an ambient temperature. Temperature sensors such as digital temperature sensor regulators (DTSRs) or analog temperature sensor regulators (ATSRs) have been widely used to control the operation conditions of semiconductor devices such as DRAM devices according to variation of the ambient temperature. These temperature sensors may detect a relatively high temperature and may control an operation period to reduce power consumption in a self-refresh mode. Further, the temperature sensors may monitor an ambient temperature in a normal operation mode.

Semiconductor devices and semiconductor systems


An apparatus and method for channel count reduction in solid-state-based positron emission tomography that multiplexes read-outs from photo-detectors using a sum delay circuit, including a sum channel and a delay-sum channel. The sum channel sums signals from sensors in an array and is digitized to extract the timing and energy information. A delay-sum channel includes a discrete delay line that introduces a known delay after each sensor, creating a time signature for the sensor, followed by a summing circuit that adds the delayed signals. The delay-sum channel is digitized using a high speed counters to extract location information. Start and Stop signals for the counter are derived when the sum channel output and the delay-sum channel output cross a pulse ID threshold, respectively. The pulse ID threshold is chosen to minimize the Compton scatter and not clip the photo-peak events.

PET imaging starts with the administration (mostly injection but also inhalation and ingestion) of a radiopharmaceutical to a patient, and in time, the physical and bio-molecular properties of the agent will concentrate at specific locations in the human body. The actual spatial distribution, the intensity of the point or region of accumulation, and the kinetics of the process from administration to capture to eventually elimination, are all elements that may have a clinical significance. During this process, the positron emitter attached to the pharmaceutical agent will emit positrons according to the physical properties of the isotope (half-life, branching ratio). Each positron will eventually interact with an electron of the object to get annihilated, and produce, most of the time, two gamma rays at 511 keV at substantially 180 degrees from each other. Those two gamma rays can be detected preferably using a scintillating crystal followed by a photo-detector and processing electronics.
Drawing a line between the detected locations of a pair of gamma rays, also called as a line-of-response (LoR), one can retrieve the likely location of the original annihilation event. While this process will only identify a line along which the annihilation event has occurred, by accumulating a large number of these lines, and through the tomographic reconstruction process, the original distribution of positron emitters can be estimated.
In addition to the location of the two scintillation events, if accurate timing (within a few hundred picoseconds) is available, the time it takes for the gamma ray to traverse from its point of origin to the detector electronics can be precisely calculated. This time, called time-of-flight (ToF), adds more information on the likely position of its origin, viz. the annihilation location, along the line. Limitations in the timing resolution of the scanner will determine the accuracy of the positioning along this line. Limitations in the determination of the location of the original scintillation events will determine the ultimate spatial resolution of the scanner, while the specific characteristics of the isotope (energy of the positron) will also contribute, via positron range and co-linearity of the two gamma rays, to the determination of the spatial resolution for a specific agent.
The above calculations need to be repeated for a large number of events. While every case needs to be analyzed to determine how many counts (paired events) are required to support the imaging tasks, current practice dictates that a typical 100 cm long, FDG (fluoro-deoxyglucose) study should accumulate hundreds of millions of counts. The time it will take to accumulate this number of counts is determined by the injected dose and the sensitivity and counting capacity of the scanner.
The counting capacity of the scanner is determined mainly by two factors. First, the decay time of the scintillating crystal determines the time for which the sensor will be occupied. This is an irreducible parameter and is inherent to the very nature of the crystal. The time it takes for the scintillation light to be created and integrated will determine the minimum amount of time for event processing. If another event were to occur during this period of time, the light from the second event would bias the estimation of the event, to the point of rendering the estimation of timing, energy, and position invalid, and both events might even need to be discarded.
The second variable influencing the count rate is the fraction of the total surface of the scanner "affected" or "occupied" during an event, also called a trigger zone. A second event can occur at any time during the processing of a first event if it occurs outside the trigger zone in a different location, and uses a different set of electronics channels. Consequently, the notion of trigger zones and integration time is critical in determining the counting rate capacity of a scanner.
Therefore, a desire exists to create a very small trigger zone to maximize count rate. However, this is immediately opposed by the fact that a smaller detector area will also increase the electronics channel count and, in turn, the overall system cost.
Conventional approaches typically implement multiplexing of channels when the channel count becomes too high to implement the signal processing electronics using discrete components. For example, a typical modern PET scanner will utilize only a few hundred sensors for the entire scanner, and one-to-one coupling of sensors to the processing electronics channel is clearly affordable in this case.
The use of other types of sensors, for example, multi-anode photo-multiplier tubes (PMT), photodiodes, avalanche photodiodes (APD), or more recently, solid-state photo-multipliers (SiPM, SSPM, MPPC etc) will usually result in several thousands or even tens of thousands of sensors. In this case, efforts to optimize the channel count are clearly required. Two such channel count reduction techniques are to use summing circuits by quadrant (Anger logic), or by rows and columns, as shown in FIGS. 1 and 2, respectively.
FIG. 1 shows a variation of Anger logic by quadrant, wherein a block of Bismuth Germanium Oxide (BGO) crystals is read out by 4 quadrants 101 created by summing 2×2 matrices of SiPM 103. Anger logic is applied to the outputs of these quadrants to estimate the position, energy, and timing.
FIG. 2 shows a conventional row-column read-out using row-wise and column-wise summing (Σ) channels. In this example case of a 4×4 matrix of 16 sensors 201 (or sensor cells), 4 rows and 4 columns can properly identify the location of the event in the array. This approach uses only 8 electronics channels compared to dedicated electronics channel for each sensor, where the channel count is 16. The larger the array, the more channel count reduction is achieved by this approach, e.g., in the case of square arrays where N is the number of sensors in every row and column, the difference between N×N and 2N becomes significant.
One problem with this approach is that the signal is divided into multiple summing circuits in the case of gamma interactions from multiple crystals (via Compton scattering in the first crystal). This situation is quite common. In a typical PET scanner construction with 20 mm thick LYSO and 4×4 mm2 crystals, only 78% of all interactions affect a single crystal, and the remaining 22% of the events produce light in at least two neighboring crystals. This proportion varies with the actual design of the crystal sizes and thicknesses, but remains a significant problem that needs to be addressed.
Most of these multiple-interaction events will affect the very first row of crystals around the crystal of interest, creating a possible matrix of nine crystals including the crystal of interest, centered at the crystal of interest. If partial energy deposition occurs at the left or right of the central crystal, the horizontal line should capture the sum of the two sensors affected. If it is at the top or bottom of the central crystal, the vertical line should do the same. However, any oblique interaction will distribute the signal over multiple summing lines.
The overall effect of this approach is that the system will need to analyze both horizontal and vertical lines on summed signals to find out which one contains the best signal for timing pick-off. Moreover, in the case of oblique interactions, the best signal will be degraded, thereby limiting the ability of a good timing estimation.

Apparatus and method for channel count reduction in solid-state-based positron emission tomography


A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern. The gate voltage (Vg) supplied to a control terminal in response to the control voltage (Vapc) largely changes in a region where the gate voltage (Vg) is lower than the threshold voltage (Vth) of the respective MOSFETs, and slightly changes near the threshold voltage (Vth). Also, the gate voltage (Vg) presents desired characteristics from the vicinity of the threshold voltage (Vth) to a high Vapc voltage region.

The present invention relates generally to a high frequency power amplifier module in a multi-stage configuration having a plurality of cascaded semiconductor amplifiers (variable power amplifier) and a wireless communication apparatus incorporating this high frequency power amplifier module, and particularly, to the technology which is effectively applied to improve the controllability for the output power by a control voltage.
More specifically, the present invention relates to a high frequency power amplifier module of a type which changes the transconductance by a gate bias for changing the output power of the high frequency amplifier module without a significant increase in power consumption, wherein the high frequency power amplifier module comprises a gate bias control circuit for controlling the gate bias, i.e., a drain current, for use in improving the control lability for the output power by a control voltage.
Mobile communication devices, for example, wireless communication apparatus for use in automobile telephones, portable telephones and so on typically have a built-in high frequency power amplifier module, i.e., a high frequency power amplifier circuit in a transmission output stage thereof. The high frequency power amplifier module is configured to automatically control the output (transmission power) by an APC (Automatic Power Control) circuit.
For example, a high frequency power amplifier module having a plurality of cascaded MOSFETs (Metal Oxide Semiconductor Field-Effect-Transistor) as semiconductor amplifier devices has been widely employed up to now because of its convenience in handling, resulting from the fact that the output can be readily controlled by a positive voltage (for n-channel MOSFETs) biased to the gate.
JP-A-7-94975 discloses a three-stage high frequency HIC (Hybrid IC) module, i.e., a high frequency power amplifier module, which has MOSFETs cascaded in the first, middle and last stages.
This high frequency HIC (hybrid IC) module comprises a first bias circuit configured to bias a gate of a predetermined MOSFET out of MOSFETs in a plurality of stages, based on an output control voltage; a second bias circuit for biasing gates of the remaining MOSFETs other than the predetermined MOSFET based on a fixed power supply; and a switching means for switching a path associated with the fixed power supply and a path associated with the second bias circuit in accordance with the output control voltage. This configuration is intended to improve the controllability of the output and the efficiency.
Each of the bias circuits is composed of three resistors and a capacitor.
The above-cited literature, however, does not describe any technique for controlling the gate bias, which changes in response to a control voltage vapc, in accordance with the output power.
Generally, a setting for the gate bias which changes in response to the control voltage Vapc is determined by the value of a resistor forming part of the bias circuit, for example, in such a manner that the efficiency is improved as the output power is larger.
The conventional high frequency HIC module changes the transconductance by applying appropriate voltages to the gates of the MOSFETs in the respective stages. This module is advantageous in that a variable output power can be provided in a small circuit configuration without adversely affecting the output power or efficiency.
However, since the gate bias changes at a constant rate in response the control voltage, the bias in each stage for the control voltage cannot be controlled on account of the fluctuating output power of the high frequency power amplifier module, resulting in poor controllability for the output power and inconvenience in utilization. Stated another way, although this high frequency HIC module produces the bias which merely results in good characteristics as a module, it cannot prevent the output power from abruptly changing in response to the control voltage Vapc.
The above cited literature discloses a diagram showing the correlation of the output control voltage Vapc to the output Po. FIG. 16 is a graph which shows the characteristic of an output power Pout versus a control voltage Vapc, similar to the above. This graph was derived from a test conducted by the present inventors.
As can be seen in the characteristic graph, the output power exhibits abrupt rising for a portion of the control voltage, for example, in a range of 1.1 to 1.5 volts, from which it can be understood that there is a problem in controlling the output for practical use.
This abruptly rising region is present when a gate voltage applied to a MOSFET for amplification which lastly operates (turns on) is close to a threshold voltage Vth. This is because, in this region of the gate voltage, the gain of the MOSFET largely varies, and simultaneously the impedance also largely varies, so that a matching loss of a matching circuit largely varies as well.
Further, as the transconductance g, is improved due to improved performances of recent devices, MOSFETs used in respective stages present larger gain fluctuations with gate bias, resulting in a tendency to more abrupt output power fluctuations and lower output controllability.
It should be noted that the foregoing problem of poor controllability for the output is not limited to the MOSFET but is common to other semiconductor amplifier devices which have a variable gain in response to a control bias applied to a control terminal.
It is an object of the present invention to provide a high frequency power amplifier module which has good output controllability.
It is another object of the present invention to provide a wireless communication apparatus which comprises the high frequency power amplifier module having the good output controllability.
The above and other objects and novel characteristics of the present invention will become apparent from the description in the specification and the accompanying drawings.
Within various embodiments of the invention disclosed in this application, typical aspects will be described below in brief.
A high frequency power amplifier module (power module) using MOSFETs as semiconductor amplifier devices in accordance with one aspect of the present invention comprises a bias circuit for generating a gate voltage in response to a control voltage Vapc generated based on a power control signal of a wireless communication apparatus to reduce fluctuations in output power in response to the control voltage Vpac in a region near a threshold voltage Vth of MOSFETS in respective amplification stages. This provides a power module which facilitates handling in consideration of the controllability for the output power.
Specifically, the power module controls the output power Pout outputted from an output terminal by controlling a gate voltage which is generated in accordance with a division of the control voltage vapc supplied to a bias supply terminal. The gate bias circuit has a circuit for setting the gate voltage supplied to a control terminal, which is responsive to the control voltage Vapc, so as to change largely in a region where the gate voltage Vg is lower than the threshold voltage Vth of the respective MOSFETs; to change slightly near the threshold voltage Vth; and to present desired power amplification characteristics from the vicinity of the threshold voltage Vth to a high Vapc voltage region.
When the gate bias circuit is applied to a multi-stage power module, the control voltage Vapc serves as an optimal gate bias for each MOSFET through the gate bias circuit. The timing at which the MOSFET in each stage turns on in response to the control voltage Vapc is also set in accordance with fluctuations in the gate bias of each stage with respect to the control voltage Vapc.
Next, a bias circuit for a multi-stage power module will be described particularly in terms of the timing at which the MOSFET in each stage turns on, with reference to FIG. 12 which shows changes in the gate voltages Vg of the MOSFETs in the respective stages in response to the control voltage Vapc.
FIG. 12 is a graph which shows how a first-stage gate voltage Vg1, a middle-stage gate voltage Vg2 and a last-stage gate voltage Vg3 change in response to the control voltage Vapc when the bias circuit is applied to a three-stage power module which has three MOSFETs cascaded in sequence. In the power module having the bias circuit exhibiting the gate voltage characteristics as represented by this graph, the first-stage MOSFET (Q1), which has a slight increase in gate voltage Vg1, is designed to turn from off to on lastly as the control voltage Vapc increases. In this event, the control voltage Vapc is set in a region in which the gate voltage vgl of the first-stage MOSFET, which lastly turns on, fluctuates slightly, while the remaining MOSFETs are set to a gate bias which results in small fluctuations in gain in response to the control voltage vapc. In addition, by turning the remaining MOSFETs on to operate stably prior to the first-stage MOSFET which lastly turns on, the output power of the power module gradually increases from an off-state.
In the power module comprising the bias circuit having the foregoing operation characteristics, the gate voltage Vg largely changes in response to the control voltage Vapc in a region lower than the threshold voltage Vth, and the output power of the power module can be controlled from a low Vapc voltage region, so that a variable range for the output power in response to the control voltage Vapc can be made wide from lower power to high power.
In a region near the threshold voltage Vth, the gate voltage Vg is set to change slightly, thus making it possible to reduce fluctuations in the output power in response to the control voltage Vapc.
In a voltage region higher than the vicinity of the threshold voltage Vth, the bias can be set based on desired high frequency characteristics, so that the improved controllability for the output power will never cause a degraded performance of the power module.
With the ability of setting the timing at which the MOSFET in each stage turns on, prior to the first-stage MOSFET which lastly turns on, the remaining MOSFETs are first turned on to gradually increase the output power from an off-state of the module as illustrated in FIG. 12, so that the controllability is improved in a very low output power region.
Further, the remaining MOSFETs are set in an operation range in which the gain slightly fluctuates when the first-stage MOSFET (Q1) turns on, and fluctuations in the output power are mainly adjusted by a gate voltage Vg1 of the first-stage MOSFET which lastly turns on, so that an abrupt rising of the output power can be mitigated.
As described above, according to the present invention, since fluctuations in the gate voltage Vg is reduced in a region near the threshold voltage Vth where the gain and impedance largely vary in response to the gate voltage Vg, it is possible to limit abrupt rising of the output power and therefore improve the controllability. Also, since the configuration of the present invention can set a gate voltage to simultaneously realize a high output and a high efficiency, the characteristics of the power module will not be degraded. Further, since the output is controlled by controlling the gate voltage, such a control expedient will not result in a reduction in the output power and the efficiency of the power module. In this way, the present invention provides for a good controllability for the output power and convenient handling while maintaining high output power and high efficiency of the power module.
Other objects, features and advantages of the present invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.

High frequency power amplifying module and wireless communication apparatus


Upscaling of an anti-aliased graphical element in a raster image includes generating a grid of pixels. Resolution of the grid is higher than resolution of the graphical element. Each pixel in the anti-aliased graphical element corresponds to a group of pixels in the higher resolution grid. The upscaling further includes distributing coverage of each transition pixel in the anti-aliased graphical element to the corresponding pixels in the higher resolution grid. The coverage is distributed unevenly.

Anti-aliasing is used to improve the appearance of graphical elements on computer screens. Without anti-aliasing, edges of graphical elements can appear jagged. Anti-aliasing can reduce the perceived jaggedness of the edges.
When an image is upscaled to a higher resolution, anti-aliased elements in the upscaled image can become blurred and artifacts can become visible. Consider an image of a road map that contains a number of anti-aliased graphical elements (e.g., streets, street names). While maps provided by leading Internet sites have sufficient resolution (72 ppi) to look fine on a computer screens, this resolution is not high enough for printing on standard printers, even with standard paper. Therefore, when viewed on a computer screen, edges of these anti-aliased elements appear sharp. When the elements are printed, however, edges in the print appear blurred. Many people mistakenly assume that their printers are of low quality, because their printers are "unable" to reproduce the visual quality perceived on the computer screens. In fact, the difference in perceived quality on the screen and quality of the print is due to the combination of the usually higher resolution power of the printer and paper media with the relatively low resolution of the map content.
It would be desirable to upscale anti-aliased graphical elements, while retaining perceived image quality.

Upscaling of anti-aliased graphical elements

Hewlett-Packard Development Company, L.P.


According to an embodiment of the present disclosure, a process liquid supply apparatus operating method is provided. The method includes filling a filter unit with a process liquid from an upstream side of the filter unit to a downstream side of the filter unit after newly mounting or replacing the filter unit and repeating a depressurization filtering process and a pressurization filtering process for a predetermined number of times. The depressurization filtering process depressurizes the process liquid in the downstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit. The pressurization filtering process pressurizes the process liquid from the upstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit.

A liquid process is performed in a manufacture process of a semiconductor device by supplying liquid chemicals (e.g., a resist liquid, an acid or alkali cleaning liquid, a solvent, a precursor-containing liquid for forming an insulation film, etc.) from a nozzle to a substrate. Such a liquid chemical supply apparatus is configured to remove foreign substances by a filter unit disposed in a supply passage.
Bubbles may be created in the aforementioned process due to gas dissolved in a resist or a liquid chemical. A line width of a pattern becomes finer and finer. Thus, cautious measures should be taken for fine bubbles that are not problematic in the past.
A coating apparatus for coating the aforesaid liquid chemical performs a gas removal process of removing the gas in a filter unit in order to remove foreign substances contained in a process liquid. The gas removal process makes the process liquid permeate through the filter unit (hereinafter, referred to as "a filter wetting process") when the filter unit is newly mounted or replaced. For example, as a method of performing the filter wetting process, filtering is performed under a positive pressure (pressure higher than an atmospheric pressure) using a pressure of a N2 gas or a pressure produced by a pump after setting the filter unit, and thereafter the number of defects on a substrate caused by the bubbles is monitored. Further, in the method of performing the filter wetting process, the gas in the filter unit is regarded as fully removed when the number of defects decreases to a predetermined level, and the filter wetting process is finished accordingly.
However, in this method, to reduce the cost for mass production, the process liquid amount consumed before the filter unit starts to operate should be reduced. Additionally, the operative time should be shortened.
By way of another example, the filter unit communicating with a process liquid ejecting nozzle may have a structural feature for reducing the number of bubbles in the process liquid passing through the filter unit. In this example, the filter unit may have repetitive prominences and depressions on a wall surface, but this may lead to complexity in manufacturing the filter unit.

Process liquid supply apparatus operating method, process liquid supply apparatus and non-transitory storage medium


A stackable rack may comprise: at least two rails, a cross-section of each rail having a shape resembling a staircase, first step portion of which represents a first surface upon which a reflector can be disposed; and a second step portion of which represents a second surface which can support another rail. A method of making a narrow band x-ray filter may comprise: providing a substrate; and stacking one or more reflection units in succession upon the substrate, each reflection unit including a rack (such as mentioned above) and a reflector held by the rack. An apparatus to produce a substantially narrow band x-ray beam may include such a filter. An apparatus to make an x-ray image of a subject may include: the apparatus to produce a substantially narrow band x-ray beam, e.g., as set forth above, and an x-ray detector arranged to receive the narrow band x-ray.

The copending '927 application discloses, among other things, a multi-mirror x-ray filter having left & right (or upper & lower) frames built up from discrete stacked rails, rather than each frame being formed of one integral component, respectively. For ease of discussion, the frames will be distinguished on the basis, e.g., of a left and right orientation. Each corresponding left & right rail together hold a reflector disposed thereon, with these three components comprising a reflection unit. Such an x-ray filter includes a sheaf of reflection units that can be built by stacking reflection units upon each other.
A reflection unit can be assembled as follows. A set of left and right rails can be disposed on a substrate. Then a first reflector can be disposed on corresponding support surfaces of the set of left and right rails. Additional reflection units can be incrementally assembled in this manner until a sufficient number thereof has been stacked upon each other to define the sheaf.

Reflector rack, fabrication method thereof, and narrow brand x-ray filter and system including same

Monochromatic X-Ray Filter Technologies, Inc.


The disclosure discloses a manufacturing method of tempered vacuum glass. At least one glass substrate constituting the tempered vacuum glass is reserved with an extraction opening, and the manufacturing method comprises the following steps: (1) manufacturing metalized layers, and performing tempering or thermal enhancement on the glass substrates; (2) placing a metal solder on the metalized layers; (3) superposing the glass substrates; (4) heating the overall glass substrates to 60-150° C.; (5) hermetically sealing the glass substrates under the condition of ensuring the heating temperature; (6) heating; (7) vacuumizing; and (8) closing the extraction opening, thus accomplishing the manufacturing process. The manufacturing method in the present disclosure can greatly reduce the stress when the two glass substrates are sealed, improve the soldering strength and prolong the service life of the tempered vacuum glass. The disclosure further discloses a tempered vacuum glass production line based on the above manufacturing method.

Vacuum glass with excellent heat insulation, sound insulation and energy-saving effects represents the development direction of future new-generation energy-saving architectural glass, and is increasingly widely popularized and used. Vacuum glass was first researched in the 1990s, for example, Australian Patent No. AU94192667.2 disclosed a manufacturing method of vacuum glass, which opened the door to vacuum glass research. Soon afterwards, some research had been made around this technology at home and abroad, but due to the process reasons, the manufactured vacuum glass was non-tempered vacuum glass, which did not meet the standards of architectural safety glass and greatly obstructed the application of vacuum glass in high-rise buildings and some special occasions. How to manufacture tempered vacuum glass becomes the focus of research at home and abroad. Based on these, the applicant proposed a glass plate combination sealing method in Chinese invention patent No. 201010508421.7, wherein sealing the circumference of vacuum glass with low melting point metal successfully solves the worldwide problem that other sealing processes may easily cause back tempering of tempered glass substrates, realizes processing and manufacturing of tempered vacuum glass, and propels forward the development and wide application of vacuum glass.
When the tempered vacuum glass is manufactured, the basic sealing strength of two pieces of glass is an important performance parameter of the tempered vacuum glass. Continuously breaking through the existing technical barriers, providing better solutions and propelling the development of tempered vacuum glass industry are goals continuously pursued by those skilled in the art. Therefore, how to improve the sealing strength is a goal continuously explored by those skilled in the art.

This patent is subject to a terminal disclaimer.

Methods for manufacturing tempered vacuum glass and production lines therefor


A method and a process to treat coke generated from a process application. The method includes the steps of recovering a mixture of coke particles and water or steam removed from at least one process application vessel. The mixture is directed to a cyclonic separator utilizing centrifugal force and gravity. Water is separated from the mixture in the cyclonic separator. Coke particles are separated from the mixture in the cyclonic separator and are directed to a thermal oxidizer. Coke particles are oxidized and gasified in the thermal oxidizer to produce gas and reduced particulate matter. The gas and reduced particulate matter are thereafter directed to a burner in the process application vessel.

1. Field of the Invention
The present invention is directed to a process and a system to treat coke particles generated in process and heating applications while minimizing NOx emissions and minimizing required SCR catalyst volume.
2. Description of the Related Art
In many process and heating applications, cracking is utilized whereby heavy organic molecules, such as hydrocarbons, are broken down into lighter molecules, such as light hydrocarbons. An example of such a process or heating application would be an ethylene cracking furnace. The cracking process may be initiated by heat, by catalysts, or by solvents. An early thermal cracking process may be observed in Burton (U.S. Pat. No. 1,049,667) issued in 1913 titled "Manufacture of Gasolene".
The cracking process often results in a slow deposition of coke, a form of carbon, on the reactor or vessel walls and/or on a series of serpentine tubes within the vessel or reactor. Over time, this degrades the efficiency of the process. Accordingly, a de-coking procedure is periodically utilized. The furnace or vessel is initially isolated or taken off-line from the normal process application. The accumulated coke may then be removed in a number of ways. Coke may be mechanically removed, such as by scraping or chipping. Alternatively, a fluid of hot water and/or steam is passed into and through the vessel or tubes. The steam and water are utilized to unloosen and remove the coke particles. The coke particles are thereafter removed in this manner and the vessel or furnace is then put back in to use.
The steam and/or water and coke or coke slurry must thereafter be dealt with. Some forms of coke may have value and may be reused, such as for fuel. So-called green coke may be used as fuel in refineries, cement kilns and steel industries. Other forms of coke may be used in battery terminals or other uses. Much of the coke, however, has little value; for example, it is sometimes used in filler for roadway construction and maintenance.
A later prior art development is shown in a simplified diagram in FIG. 1. A furnace, reactor or vessel 10 includes a series of internal serpentine tubes 12. A burner 14 supplied with fuel, such as natural gas, from a fuel line 16 provides heat. A portion of the heat generated in the furnace, reactor or vessel may be captured in a heat recovery unit 20. The mixture of slurry of steam and/or water and coke is removed from the furnace via a port 22. The coke particles removed from the vessel or furnace are slowly reintroduced back in to the burner 14 of the furnace via a line 24. The water and steam would be vaporized and a portion of the coke particles would be oxidized and consumed. A negative outcome of this procedure is that it generates increased NOx as emissions from the furnace 10 at an exhaust 28 depicted by arrow 26. Combustion of fossil fuels is known to generate some level of NOx emissions, which includes nitric oxide (NO) and nitrogen dioxide (NO2).
NOx may be controlled in a number of ways. Martin et al. (U.S. Pat. No. 6,003,305) illustrates an example of a method of reducing NOx products of incomplete combustion in an internal combustion engine. A selective catalytic reduction system (SCR) is disposed downstream of a flameless thermal oxidizer. SCR systems catalytically reduce NOx emissions to nitrogen and water using a catalyst, in conjunction with ammonia (NH3).
Harold et al. (U.S. Pat. No. 7,682,586) discloses an example of treatment of nitrogen oxides (NOx) in combustion flue gas with selective catalytic reduction (SCR) using ammonia and urea as reducing agents.
FIG. 2 illustrates a simplified diagram of a later prior art development following FIG. 1. A vessel, reactor or furnace 30 includes a series of internal serpentine tubes 32. A burner 34 supplied with fuel, such as natural gas, from a fuel line 36 provides heat. A portion of heat generated in the vessel or furnace may be captured in a heat recovery unit 38. The mixture or slurry of steam and/or water and coke is removed from the furnace via a port 44. The coke particles removed from the vessel or furnace are slowly introduced back in to the burner 34 via a line 46.
A selective catalytic reducer (SCR) 40 is added near the exhaust 42 of the furnace shown by arrow 48. A chosen catalyst, such as those including ammonia (NH3), would be utilized on a physical support or block having a pattern, such a honeycomb pattern. The SCR system 40 would serve to reduce the NOx emissions. In high dust situations, such as coal dust or coke particulate dust, larger SCR blocks with larger openings are required. A higher catalyst volume would be required per pound of NOx that would be treated. In some cases, two to three times the volume of catalyst would be required. This increases the size, the complexity, and the cost of the overall furnace assembly.
Assignee's prior patent, Wirt et al. (U.S. Pat. No. 8,017,084) discloses an example of a selective catalytic reduction system for heat recovery systems and fired heaters.
There remains a need to develop a process and a system to treat the coke by-products removed from a furnace, reactor or vessel efficiently.
There remains a need to develop a process and system to treat coke by-products directed to the goal of minimizing the volume of SCR required while maximizing the efficiency.

Coke treatment process and system to minimize NO


Techniques are described for determining the quality of software using fuzzy logic. The techniques include using linguistic variables to translate a numeric value of a quality attribute into a linguistic value of a quality attribute. The linguistic values of multiple quality attributes are aggregated into a quality rating of the software. The quality rating then is used to predict a performance attribute for the software. Techniques are described that may help improve the accuracy of the prediction, including refining software quality parameters based on a comparison of the parameters with software quality of the developed software. The techniques also include the ability to modify the quality attributes used based on the computing environment, the organizational environment or other characteristics.

The quality of computer software may be based on the quality of the process used to develop the computer software. The quality of computer software also may be determined based on quality indicators or attributes of the computer software itself. Examples of quality attributes include reliability, reusability, maintainability, mean time to failure, testability, usability, efficiency, understandability, complexity, modularity, and portability. Many attributes, such as mean time to failure and reliability, are only measurable after the computer software is placed in operation.

Determining the quality of computer software


A wall mount gun lock assembly having an open loop ring housing and an open loop ring. The open loop ring housing is secured to the wall of a room by lag bolts passing through the rear wall of the open loop ring housing. The front wall of the open loop ring housing has a key lock housing that is removably mounted in an aperture therein and it can be locked in place. An arcuate shaped open loop ring has its opposite end tips passing through left and right side apertures of the front wall of the open loop ring housing. The end tips of the open loop ring have annular grooves formed adjacent their ends. The key lock housing has side walls having horizontal slots that engage the annular grooves of the open loop ring when the key lock housing is pushed in to its locking position. It is impossible to rotate the open loop ring once the key lock housing has been locked in position and it is also impossible to gain access to the lag bolts that are mounting the open loop ring housing to the wall of a room. By merely unlocking the key lock housing, the open loop ring can be rotated so that the open space between its end tips is located outside the open loop ring housing which allows the open loop ring to be either threaded through or removed from the trigger guard of a firearm.

The invention relates to a locking assembly and more specifically to a wall mount gun lock assembly.
A major concern of owners of guns is the fact, children may gain unauthorized access to guns with the consequence of someone being injured or killed. Another major concern is the guns can be stolen from a person's house.
Presently there are gun lock devices on the market that have not been entirely satisfactory. Some of these lock into the trigger guard behind the trigger thereby preventing the trigger being pulled. Often times this device can be pried apart and removed. Other devices on the market allow the weapon to be secured to a wall structure. Gun cabinets that can be locked are often mounted on a wall and many of them have pane glass doors that can be broken and provide access to the guns.
It is an object of the invention to provide a novel wall mount gun lock assembly that can be easily installed and securely attached to the wall of a house.
It is another object of the invention to provide a novel wall mount gun lock assembly that is economical to manufacture and market.
It is a further object of the invention to provide a novel wall mount gun lock assembly that can be used to secure both handguns and rifles.


An instruction pipeline type microprocessor comprises an operation execution section consisting of a first operation execution section for executing instructions having no memory operand, a second operation execution section for executing instructions having a memory operand, and a third operation execution section for executing floating point instructions. A general purpose register is provided consisting of a second register group for storing data processed as a result of execution by the operation execution section in the form of a flow of programs and a first register group for storing processed data as the result of a look-forward execution of instructions which can be processed by the operation execution section. Compare logic determines whether or not succeeding instructions have been executed. The processed data held in the first register group is provided to the second register group so as to facilitate execution in the predetermined program order.

1. Field of the Invention
The present invention relates to a parallel instruction execution type microprocessor, more particularly to an instruction pipeline type microprocessor capable of rapidly executing instructions.
2. Description of the Prior Art
In the instruction pipeline type microprocessor according to the prior art, a particular register or registers are used in order to perform an operand address calculation in, for example an ADD instruction. However, as the content of the register is modified by a previous instruction such as a TRANSFER instruction, the ADD instruction can not be shifted to an operand address calculation stage before a write stage to a general purpose register is terminated, thus delaying the processing of the instruction.
Namely, FIG. 2 shows an outline construction of the instruction pipeline type microprocessor according to the prior art.
In FIG. 2, reference numeral 1 indicates a bus control section (BCU) for connecting a microprocessor P to an external circuit, numeral 2 indicates an instruction fetch section (IFU), 3 indicates a decoder (DEC) for decoding instructions, 4 an operand address calculation section (OAG), 5 an address translation section (AT) for converting a logical address into a physical address, 6 an operand fetch section (OPF) for fetching an operand, 7 an operation execution section (EXU) for executing instructions, 8 general purpose register group (GR) consisting of a plurality of registers R.sub.1, R.sub.2, R.sub.3, R.sub.4, . . . (not indicated).
When machine instructions shown in FIG. 1 are executed by the microprocessor P shown in FIG. 2 for instance, the timing of the instruction pipeline processing becomes the one shown in FIG. 3. As shown in FIGS. 1 and 3, supposing that a.sub.1 is an instruction which transfers the content of an address A to the register R.sub.1 (not indicated) in GR.sub.8, a.sub.2 is an instruction which transfers data in the register R.sub.3 in GR.sub.8 to the register R.sub.2, a.sub.3 is an ADD instruction which transfers the content of an address B which is modified by the register R.sub.2 to the register R.sub.4, and a.sub.4 is an instruction which transfers data in the register R.sub.2 to a memory indicated by address C, the content of the register R.sub.2 is used by the instruction a.sub.3 in order to perform an operand address calculation. However, the content of the register R.sub.2 is modified by the instruction a.sub.2. As a result, the instruction a.sub.3 can not move to OAG.sub.4 until the transfer of the instruction a.sub.2 to GR.sub.8 is terminated, thus delaying the processing of the instruction a.sub.3.
Since the operation execution section and the general purpose register group in the microprocessor according to the prior art are not duplicated, succeeding instructions can be executed only after the instructions for updating the general purpose register group GR.sub.8 have been completely executed.
Accordingly, the advantages of the pipeline system can not be utilized due to stagnation of the processing flow in the instruction pipeline type microprocessors according to the prior art.


A radio frequency (RF) IC card device with very high frequency comprises an IC device (102), a radio frequency interface device (103), an RF antenna (104), an IC card interface (106) and an RF interface (107). Particularly, said RF interface device (103) and the RF interface (107) operate in a frequency band of UHF (ultra high frequency) or SHF (super high frequency); said RF antenna (104) is directly integrated on an IC card (100); the RF IC card device with very high frequency exchanges data with other RF devices via the RF interface (107).

Mobile communication terminals such as cell phones have become necessary for everyday life, and new application demands for electronic wallets based on mobile terminals, cell phone passes for an access control terminal, public transit use of cell phone, cell phone VIP cards have become urgent. If the mobile communication terminals possess a mobile payment function, e.g., electronic wallet, or an expenditure application function, e.g., cell phone pass for an access control terminal, it would bring a great convenience for people's daily lives.
In order to meet these new demands, the key technical problem to be overcome is RF signal transmission and antenna arrangement. Prior technical solutions are all based on modification to mobile terminals, e.g. current near field communication (NFC) is conducted by adding an RF chip and an antenna in a mobile terminal. However, if an existing cell phone is not modified, functions such as the cell phone electronic wallet would not be achieved. Thus, these solutions have not much value in practice.
Chinese patent 200620133544.6 discloses a solution which provides a SIM card RF antenna device for a mobile communication terminal. The device includes an RF antenna, RF antenna fittings, and a flexible connection member. The antenna fittings are used for carrying the RF antenna and fixing the RF antenna at an outer side of the battery of a mobile communication terminal. The flexible connection member is used for connecting the RF antenna to a SIM card that is at the inner side of the battery of the mobile communication terminal. Thus, some users can use a mobile communication terminal to achieve non-telecommunication functions by only adding some cost and without changing the cell phone or having a customized cell phone back cover. The solution of the above patent needs modification to mobile communication terminals and needs to provide a customized antenna and a flexible connection member to every user. However, embedding an RF antenna and a flexible connection member into a mobile communication terminal is complicated in process and difficult in implementation, and high on cost. These problems will severely limit the adoption of this solution. In addition, this solution is significantly limited by the internal structure of the cell phone and thus has no versatility.
Another Chinese patent 200420121028.2 discloses a solution by adding an RF antenna to an existing cell phone terminal, adding an antenna area by modifying the cell phone, and adding an RF interface by modifying a SIM card. This solution still needs to modify a cell phone significantly, is complicated in process and costly; it has no commonality yet.
Another Chinese patent 200620026253.7 discloses a technical solution in which an RF antenna in a wireless RF payment cell phone is installed inside of a battery of the cell phone, arranged between the cell phone battery and a back cover of the cell phone, or attached to the outer surface of the back cover of the cell phone. The RF antenna is connected with a SIM card of the cell phone via contact points, connected with a smart IC card of the cell phone via contact points, or connected with a security chip in the cell phone via contact points. Same as the above, this solution is difficult to implement, costly, and has no versatility.
The technical solutions disclosed by the above patents all need to modify existing cell phones; currently, the number of existing cell phones is huge and there are 0.4 billion cell phones in China alone. There are a variety of cell phones and which are being upgraded frequently. Because these solutions have no versatility, are complicated for modification and are costly, they are difficult to be broadly adopted.
Based on this background, the present invention provides a simple, convenient, low cost method and device without the need of modification of a mobile terminal to realize wireless RF data exchange and to implement non-telecommunication functions such as cell phone wallet, cell phone pass for an access control terminal, etc., in order to solve a conflict between modification of the mobile terminal and realization of non-telecommunication functions.

Radio frequency IC card device with very high frequency


The present invention is a non-volatile memory comprising: first and second floating gate MOS transistors which are electrically written and erased and which are operatively connected between power sources serially; and an output terminal connected to the contact point of the first and second MOS transistors; wherein a first datum is stored by writing to the first MOS transistor and erasing the second MOS transistor, and a second datum is stored by erasing the first MOS transistor and writing to the second MOS transistor. With the aforementioned memory device, through current does not flow to the power source, because only one transistor will be conductive even if read voltage is applied to the control gate of both transistors. Consequently, reading time can be shortened, without leading to increased power consumption, by maintaining the control gate at the read voltage level.

1. Field of the Invention
The present invention relates to a non-volatile memory device using a MOS transistor having a floating gate, and relates to a memory device consuming little current and allowing high speed reading.
2. Description of the Related Art
Non-volatile memory, using MOS transistors having floating gates as memory cells, is widely used because the high volume of data stored is not volatile. In particular, flash memory, which has a simplified circuit structure wherein the units erased are limited to relatively large blocks, is in widespread use. This flash memory is a device having normal memory blocks for storing data, as well as a boot block with a smaller capacity. This boot block is an area that is unconditionally accessed at the startup of a system which includes flash memory, for example. Such a boot block houses a top boot block disposed on the upper address side of the block and a bottom boot block disposed on the lower address side. The only difference between these is whether the upper address or lower address is the block selection address which is initially accessed. The memory devices within the boot block are the same.
Flash memory having such a boot block must be the top boot block type or the bottom boot block type, depending on the users' requirements. Consequently, a single type of memory device is manufactured; the information about the type selected according to the users' requirements is stored in the function setting memory; and the block selection address Add1 is switched according to the function setting bit.
FIG. 6 is a figure showing an example of the constitution of the conventional function setting memory. In the constitution of the conventional memory, like in a normal memory cell, a MOS transistor T3 having a floating gate and which stores data and the load transistor T2 thereof are serially connected between the power source Vcc and ground GND. The load transistor T2 is an P-channel enhance transistor, for example; its gate is maintained at ground potential and it has a prescribed impedance and is continually in a conductive state. The MOS transistor T3 has a floating gate FG. The threshold voltage of the transistor T3 is increased by writing (programming), by adding electrons to the floating gate FG; the threshold voltage thereof is decreased by erasing, by pulling out electrons from the floating gate FG. Consequently, the application of a voltage at a level between these threshold voltages to the control gate CG causes the MOS transistor T3 to become conductive or non-conductive in accord with the stored data.
A prescribed control voltage must be applied to the source and drain of the MOS transistor T3 in order to add or pull electrons from the floating gate FG of the MOS transistor T3. However, it is difficult to apply such a control voltage because the MOS transistor T3 has the circuit structure shown along with the load transistor T2. A separate transistor T4, for writing and erasing and which shares the floating gate FG, is therefore established. The operations of adding and pulling electrons from the floating gate FG is carried out by means of this transistor T4.
This type of memory is read by applying a voltage between the aforementioned threshold voltages to the control gate CG, making the transistor T3 conductive or non-conductive, and detecting the voltage of the contact n12 of the transistors T2, T3. The voltage of the contact point n12 is read from the output OUT by means of inverters 10, 11. In the case where writing is being performed, the transistor T3 becomes non-conductive, the contact point n12 becomes H level, and the output OUT also becomes H level. In the erasing state, the transistor T3 is conductive, the contact point n12 becomes L level, and the output OUT also becomes L level.
In the memory device constitution shown in FIG. 6, when the read voltage is applied to the control gate CG with the transistor T3 in the erasing state, the transistor T3 becomes conductive and the through current flows from the power source Vcc to the transistors T2, T3, and the ground. This current brings about an increase in power consumption. In the power down state where reading is not performed, it is necessary that the control gate CG be kept at ground potential so that through current does not flow, regardless of whether the transistor T3 is in the erasing state or writing state. The potential of the CG rises from ground to a prescribed reading potential only upon transition to an active state for reading data.
Consequently, when using the function setting memory in the memory device constitution shown in FIG. 6, the access time for entering the active state becomes long, because it is necessary to raise the control gate CG of the function setting memory and read the setting information before accessing normal memory.
A redundant memory cell array is included to compensate for bad bits of high capacity flash memory. The redundant ROM stores the address of those bad bits and makes it necessary to raise the control gate CG of the memory device to read the redundant ROM each time the memory is accessed, when using the memory device as shown in FIG. 6 as the redundant ROM. Consequently, this redundant ROM is in concept a type of function setting memory and becomes an obstacle to increasing the speed of a memory device as in FIG. 6.


A structure for a field emission device and a method of making the same. The cathode electrodes are formed as a two-layered structure of chromium on top of aluminum. Photosensitive electron emission material is patterned via back side exposing, the aluminum layer serving as a mask. In receptor regions, conducting aluminum fingers form electrical contact with the emission material while spaces between the aluminum fingers serve as a window to allow for exposure of the photosensitive emission material.

1. Technical Field
The present invention relates to an electron emission device, and in particular, to an electron emission region and a method of manufacturing the same.
2. Description of the Related Art
Generally, the electron emission devices are classified into a first type where a hot cathode is used as an electron emission source, and a second type where a cold cathode is used as the electron emission source. The second type of electron emission devices include a field emitter array (FEA) type, a surface conduction emitter (SCE) type, a metal-insulator-metal (MIM) type, a metal-insulator-semiconductor (MIS) type, and a ballistic electron surface emitting (BSE) type.
The electron emission devices differentiate in their specific structure depending upon the types thereof, but basically have an electron emission unit placed within a vacuum vessel to emit electrons, and an image display unit facing the electron emission unit in the vacuum vessel to emit light or display the desired images.
With the FEA type electron emission device, electrons are emitted from electron emission regions due to the electric fields formed when driving voltages are applied to the driving electrodes placed around the electron emission regions. The FEA type electron emission device has a triode structure with cathode, gate and anode electrodes. The gate electrodes are first formed on a first substrate, and after an insulating layer is formed on the gate electrodes, cathode electrodes and electron emission regions are formed on the insulating layer.
With the above structure, there is no possibility that the gate and the cathode electrodes are short-circuited to each other during the processing thereof. As the electron emission regions are placed at the topmost area of the first substrate, a thick filming process, such as screen printing, can be easily applied thereto. The relatively simple processing steps related thereto are advantageous in making wide-screened display devices.
With the above-structured electron emission device, the electron emission regions are patterned by coating a photosensitive electron emission material onto the first substrate, and exposing it to light, followed by developing it. When ultraviolet rays are illuminate the electron emission material from the front side of the first substrate during the light-exposing step, the pattern of the electron emission regions is non-uniformly made, and the adhesion of the electron emission regions to the cathode electrodes is poor.
Accordingly, a backside exposure technique where the illumination of ultraviolet rays is made from the back side of the first substrate has been recently applied for the light exposing. However, a structure produced by such a method results in a high contact resistance between the electron emission regions and the cathode electrodes, a large voltage drop across the cathode electrodes and cracks in the insulation layer formed between the cathode and gate electrodes. All of these problems result in deteriorated image quality. What is needed is a design for a field emission device and a method of making that overcomes the above problems.

Electron emission device having a novel electron emission region design


A hard polishing pad with a porous surface for use in chemical-mechanical planarization of semiconductor wafers. The polishing pad has a body with a planarizing surface upon which a slurry may be deposited, and a plurality of particles are suspended in the body. The body is made from a continuous phase matrix material, and the particles are made from a substantially incompressible material that is soluble in the slurry. As a wafer is planarized, the particles at the planarizing surface of the polishing pad dissolve in the slurry and create pores in the pad. Also, because the particles are substantially incompressible, they reinforce the pad to provide a hard, substantially incompressible pad.

Chemical-mechanical planarization ("CMP") processes remove material from the surface of a wafer in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry solution generally contains small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. The polishing pad is generally a planar pad made from a relatively soft, porous material such as polyurethane. Thus, when the pad and/or the wafer moves with respect to the other, material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and by the chemicals in the slurry (chemical removal).
FIG. 1 schematically illustrates a conventional CMP machine 10 with a platen 20, a wafer carrier 30, a polishing pad 40, and a slurry 44 on the polishing pad. An under-pad 25 is typically attached to the upper surface 22 of the platen 20, and the polishing pad 40 is positioned on the under-pad 25. A drive assembly 26 rotates the platen 20 as indicated by arrow A, or in another existing CMP machine the drive assembly 26 reciprocates the platen 20 back and forth as indicated by arrow B. The motion of the platen 20 is imparted to the pad 40 through the under-pad 25 because the polishing pad 40 frictionally engages the under-pad 25. The wafer carrier 30 has a lower surface 32 to which a wafer 12 may be attached, or the wafer 12 may be attached to a resilient pad 34 positioned between the wafer 12 and the lower surface 32. The wafer carrier 30 may be a weighted, free-floating wafer carrier, or an actuator assembly 36 may be attached to the wafer carrier 30 to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional planarizer 10, the wafer 12 is positioned face-downward against the polishing pad 40, and then the platen 20 and the wafer carrier 30 move relative to one another. As the face of the wafer 12 moves across the planarizing surface 42 of the polishing pad 40, the polishing pad 40 and the slurry 44 remove material from the wafer 12.
CMP processes must also consistently and accurately produce a uniform, planar surface on the wafer because it is important to accurately focus optical or electromagnetic emissions in precise circuit patterns on the surface of the wafer. As the density of integrated circuits increases, it is often necessary to focus the optical or electromagnetic emissions to within a resolution of approximately 0.35-0.5 .mu.m. Focusing the circuit patterns to such small tolerances, however, is very difficult when the distance between the emission source and the surface of the wafer varies because the surface of the wafer is not uniformly planar. In fact, several devices may be defective on a wafer with a non-uniformly planar surface. Thus, CMP processes must create a highly uniform, planar surface.
The planarity of a polished semiconductor wafer is a function of several factors, one of which is the distribution of slurry between the polishing pad and the wafer. The polishing rate, which is the rate at which material is removed from the wafer, depends in part on the volume slurry between the wafer and the pad. To maintain a uniform polishing rate across the surface of the wafer and produce a uniformly planar surface, it is desirable to distribute the slurry evenly across the whole surface area of the wafer.
Another factor affecting the planarity of a polished wafer is the compressibility of the pad. Soft pads conform to the general topography of the wafer and result in a surface that retains some of the topographical features of the unpolished wafer. Relatively incompressible pads, on the other hand, do not readily conform to the topography of the wafer; as a result, hard pads planarize high points on the wafer before reaching low points to produce a more uniformly planar surface on the wafer. Therefore, it is generally desirable to provide a hard polishing pad that enhances the distribution of slurry between the wafer and the polishing pad.
One desirable technique to enhance the distribution of slurry under the wafer is to provide a porous structure in the polishing pad that holds additional slurry slightly below the polishing surface of the polishing pad. Conventional porous polishing pads have a body made from a continuous phase matrix material and a filler material made from hollow spheres or closed cell foam. The continuous phase matrix material is typically made from a compressible polymeric material, and the hollow spheres are typically made from polymers. When the pad is cut or conditioned, the center of the hollow spheres and porous structure of the closed cell foam form pores in the pad. The porosity of a pad is controlled by the density of the filler material in the continuous phase matrix material, with a higher density of filler material resulting in a higher porosity of the pad. Thus, it is generally desirable to use a higher density of filler material. One problem with conventional porous polishing pads is that the hollow spheres and closed cell foam are compressible and do not reinforce the continuous phase matrix material to provide a sufficiently hard polishing pad. The use of a higher density of filler material to provide high porosity accordingly results in a compressible pad that conforms to the topography of the wafer. Therefore, it is difficult to provide a polishing pad having both high porosity and substantial hardness.
Many techniques and structures have also been developed to increase the hardness of polishing pads. Typically, glass particles or fibers are added to the matrix material to reinforce the pad and increase its hardness. Glass reinforced polishing pads, however, do not have adequate porosity because glass is not readily soluble in solutions that may be used with polyurethane. Therefore, conventional polishing pads with glass particles and fibers do not distribute the slurry uniformly across the surface of the wafer.
In light of the problems associated with conventional porous and hard polishing pads, it would be desirable to develop a relatively hard polishing pad that has a sufficiently porous planarizing surface.

Polishing pad with incompressible, highly soluble particles for chemical-mechanical planarization of semiconductor wafers


There is disclosed a method for treating pain, comprising administering an analgesic oral dosage form comprising desmetramadol substantially free of tramadol.

In the United States 25 million people suffer from daily pain. It is common to use a numeric scale to rate pain intensity where '0' equals no pain and '10' is the worst pain imaginable. Pain intensity is broadly categorized as mild (score 4 or less), moderate (score 5 to 6) and severe (score 7 to 10). For example, the acetaminophen for injection 2015 U.S. FDA label states that it is indicated for the "management of mild to moderate pain." Currently, schedule II opioids under the Controlled Substance Act (codified at 21 USC § 801 et seq.) are the mainstay treatment for patients with moderate to severe pain (e.g., codeine, oxycodone, hydrocodone and fentanyl). However, schedule II opioids are highly addictive and can lead to misuse and lethal respiratory depression in an overdose because the same opioid receptor that controls pain transmission also controls the drive to breath. Including opioids like heroin and fentanyl, over 40,000 opioid-related deaths in 2017 in the United States led to what is now known as the Opioid Crisis.
There are unfortunately limited pharmacologic options for patients seeking an alternative to schedule II opioids who still require effective analgesia. A critical unsolved problem therefore exists to identify analgesic options for those suffering from pain that are safer and reduce the risk of treatment-related respiratory depression and death.
Tramadol is approved in the United States for moderate to moderately severe pain, and pain severe enough to require an opioid analgesic (i.e., pain with a score of 5 or greater). The ULTRAM® 2003 United States Food and Drug Administration (FDA)-approved label stated: "ULTRAM is indicated for the management of moderate to moderately severe pain in adults." In 2017, the FDA changed the label with language functionally equivalent to the 2003 label language to read: "ULTRAM is indicated for the management of pain in adults that is severe enough to require an opioid analgesic and for which alternative treatments are inadequate."
As a schedule IV analgesic, tramadol is less prone to abuse than schedule II opioids, and for reasons unrelated to its abuse potential, is safer (Raffa, 2008, J Clin Pharm Ther, 33:101-08; Dart, 2017, RADARS SYSTEM, In Lisbon Addictions, Second European Conference on Addictive Behaviors and Dependencies, Lisbon, Portugal; WHO, 2014, Expert Committee on Drug Dependence 36th Meeting, Tramadol Update Review Report, Agenda Item 6.1; WHO, 2017, Expert Committee on Drug Dependence 39th Meeting, Tramadol Pre-Review Report, Agenda Item 5.3). In contrast to schedule II opioids at therapeutic doses, tramadol does not cause clinically significant respiratory depression (Bloch, 2002, Anesthesia analgesia, 94:523-28; Grond, 2004, Clinical pharmacokinetics, 43:879-923; Houmes, 1992, Anesthesia analgesia, 74:510-14; Mildh, 1999, J clin anesthesia, 11:310-16; Tarkkila, 1997, J clin anesthesia, 9:582-85; Tarkkila, 1998, Eur J anaesthesiology, 15:64-68; Vickers, 1992, Anaesthesia, 47:291-96). A lethal oral dose of fentanyl, oxycodone and hydrocodone in opioid-naïve and nontolerant subjects can be 2, 40 and 90 mg, respectively (Purdue Pharma LP, 2016, Package Label OXYCONTIN®—Oxycodone hydrochloride tablet, film coated, extended release; U.S. National Library of Medicine: TOXNET. Toxicology Data Network, https://toxnet.nlm.nih.gov). Because a lethal tramadol dose is in excess of 5 grams (De Backer, 2010, J Analytical Toxicol, 34:599-604; Sachdeva, 1997, Amer J Emergency Med, 15:217-18; Shadnia, 2008, Human Exp Toxicology, 27:201-05), reports of lethal overdoses are rare (De Backer 2010; Spiller, 1997, J Toxicology Clin Toxicology, 35:361-64).
Tramadol is a racemate consisting of 1R,2R-tramadol [(+)-tramadol], and 1S,2S-tramadol [(−)-tramadol]. After oral administration of the racemate, both the (−) and (+) forms of both tramadol and the 0-desmethyltramadol (M1) metabolite (i.e., both the 1R,2R-isomer and 1S,2S-isomer of O-desmethyltramadol, respectively) are detected in the circulation (Grondhoumer 2004; Raffa, 2012, Expert Op Pharmacotherapy, 13:1437-49). The chemical structure and dominant pharmacology of each tramadol and M1 enantiomer are shown in FIGS. 1A-1D. The in vitro μ-opioid receptor binding affinity (Ki) is dominated by (+)-M1 (0.0034 μM), compared to substantially weaker affinities for (−)-tramadol (25 μM), (+)-tramadol (1.3 μM) and (−)-M1 (0.24 μM). The in vitro inhibition (Ki) of serotonin uptake is dominated by (+)-tramadol (0.5 μM), whereas the inhibition of norepinephrine uptake is mediated by (−)-tramadol (0.5-1.6 μM) and (−)-M1 (0.9-1.4 μM) (Driessen, 1993, Br J Pharmacol, 108:806-11; Raffa 2012).
Analgesic activity is a result of binding to μ-opioid receptors, inhibition of reuptake of norepinephrine, and inhibition of reuptake of serotonin (Raffa, 1992, J Pharmacol Exp Ther, 260:275-85). The ULTRAM® label states the following.                The relative contribution of both tramadol and M1 to human analgesia is dependent upon the plasma concentrations of each compound. . . . Opioid activity is due to both low affinity binding of the parent compound and higher affinity binding of the O-demethylated metabolite M1 to μ-opioid receptors. . . . Tramadol-induced analgesia is only partially antagonized by the opiate antagonist naloxone in several animal tests. The relative contribution of both tramadol and M1 to human analgesia is dependent upon the plasma concentrations of each compound. . . . Tramadol has been shown to inhibit reuptake of norepinephrine and serotonin in vitro, as have some other opioid analgesics. These mechanisms may contribute independently to the overall analgesic profile of tramadol.These statements are also in the ULTRACET® (tramadol plus acetaminophen combination product) label.
Consistent with non-opioid mechanisms of analgesia, tramadol-induced analgesia is only partially antagonized by the opiate antagonist, naloxone, in animals and humans (Raffa 1992; Kayser, 1991, Eur J Pharmacol, 195:37-45; Kayser, 1992, Eur J Pharmacol, 224:83-88; Collart, 1993, Br J Clin Pharmacol, 35:73P). Likewise, in a double-blind, placebo-controlled, crossover study in volunteers, tramadol analgesia was reduced by more than half by an adrenergic receptor antagonist, consistent with tramadol's non-opioid analgesic mechanism involving inhibition of neuronal uptake of norepinephrine (Desmeules, 1996, Br J Clin Pharmacol, 41:7-12).


A parallel tapped magnetic pickup for an electrical stringed musical instrument is provided. The parallel tapped magnetic pickup comprises a coil formed with at least two parallel connected wound wires. A guitar in combination with the parallel tapped pickup is additionally provided.

Electromagnetic pickup devices are used in conjunction with stringed musical instruments such as electric guitars and basses to convert the vibrations resulting from the movement or "picking" of the strings into electrical signals, for subsequent transmission to amplification devices to produce a desired sound. The pickup is generally positioned under the strings of the instrument on the base surface and the signal transmitted by an electromagnetic pickup is dependent upon the motions of each string.
The most essential components of a pickup are a permanent magnet and a coil of wire. The magnet generates a magnetic field that passes through the pickup coil and also extends into a space occupied by at least one string of the instrument. Vibration of the string changes the reluctance of the magnetic path and creates disturbances in the magnetic field proportional to the string vibration. The changing magnetic field in the pickup coil in turn induces an electrical signal in the coil. From the output of the pickup, a circuit connection is made to an amplifier.
There are several types of pickups with varying coil configurations known in the art. One type of electromagnetic pickup device is a single coil pickup. In a single coil pickup, a single coil portion has a plurality of magnetic pole pieces, with each pole piece associated with a string of the instrument. The pole pieces lie in a place spaced from the common plane of the strings, with each string disposed in a play extending through a space between two adjacent pole pieces, so that a given string at rest is located above and between two adjacent pole pieces.

Single coil parallel tapped magnetic pickup


A method can be used for facilitating a random access procedure between a first transceiver and a second transceiver within a cell. The first transceiver selects a signature sequence from a set of signature sequences, incorporates the signature sequence into a signal, and transmits the signal to the second transceiver. The set of signature sequences being obtained from a Zadoff-Chu sequence with zero correlation zone.

In most mobile communication systems of today, there are specific requirements regarding synchronization of a base station and a mobile terminal in order to secure a correct data transmission. Examples of such systems are the Universal Terrestrial Radio Access (UTRA) and Evolved UTRA.
In Evolved UTRA, Single-Carrier Frequency Division Multiple Access (SC-FDMA) may be used as multiple access scheme for the uplink communication. The transmission scheme of SC-FDMA is the so-called Discrete Fourier Transform-spread Orthogonal Frequency Domain Multiplexing (DFT-spread OFDM), which can be seen as OFDM with pre-coding. Whereas OFDM, which produces a multi-carrier signal, has a high peak-to-average ratio (PAPR), the DFT pre-coding gives a single-carrier signal with lower PAPR. The low PAPR serves to extend the coverage and to reduce the battery drain in the mobile.
In DFT-spread OFDM, cyclic prefix is used to achieve equalization in the frequency domain. However, a requirement for successful equalization in DFT-spread OFDM, as well as in OFDM, is that the signals transmitted from all mobile terminals in the cell are synchronized in such a manner that the delay spread of the signal plus the spread in the time of arrival is less than the duration of the cyclic prefix. Therefore, it is required that each transmitting mobile terminal is synchronized to within a fraction of the duration of the cyclic prefix before it can transmit data.
In Evolved UTRA, synchronization is performed both in uplink and downlink. In one step of the synchronization, downlink synchronization, the mobile terminal synchronizes (or locks) to the carrier frequency and the frame timing of the base station. This synchronization, however, is not sufficient to ensure that the base station can properly receive the signals from the mobile terminal, since mobile terminals may be located at various distances relative to the base station.
Consequently, further synchronization, uplink synchronization, is needed since the distance between a base station and a mobile terminal, and hence the round trip time, is in general unknown.
In Evolved UTRA, a random access channel (RACH) supports uplink synchronization of the mobile terminals. RACH in Evolved UTRA is contention-based, i.e. any mobile terminal within the cell may transmit on the resource allocated to RACH. Consequently, several mobile terminals may attempt to transmit synchronization signals simultaneously, and in order to reduce the risk that the base station fails to distinguish signals from different mobile terminals, a set of signature sequences is provided, wherein each mobile terminal randomly selects one signature sequence.
In UTRA and Evolved UTRA a binary pseudo-random sequence generated by a shift register is modulated by 16-bit Hadamard sequences to produce these signature sequences. Even though these signature sequences in many instances provide good correlation properties, there still exists a need for enhanced detection capabilities to detect a specific signature in presence of other simultaneous signatures, especially at low SIR values.

Method, apparatus and system for random access


A method for producing an anti-fouling coating film includes: a step (1) of applying a fine uneven layer forming agent containing at least one type of polysilazane as at least one type of silica raw material on at least one surface of a base substrate, the aforementioned at least one surface comprising at least one type of resin, to form a fine uneven layer containing silica and polysilazane; a step (2) of applying a modification layer forming agent containing a reactive organic compound and polysiloxane or perfluoropolyether on a surface of the fine uneven layer obtained in the step (1), to form a modification layer containing polysiloxane or perfluoropolyether, and a step (3) of applying lubricating oil containing silicone oil or fluorinated oil on a surface of the modification layer obtained in the step (2), to form a lubricating oil layer.

High-durability water-repellent articles having excellent water-repellent properties and hydroplaning properties (water droplet slidability), and window glasses for architecture and window glasses for vehicles applying these have been proposed. This water-repellent article is an article obtained by forming a void layer which is substantially composed of an inorganic material and which has a void structure on a base substrate, and thereafter impregnating voids of the void layer with water-repellent material. Furthermore, a foundation layer is provided between the base substrate and the void layer having the void structure. Moreover, the foundation layer is preferably composed of an inorganic material similar to the component material of the void layer, for example a ceramic material such as silicon dioxide (SiO2), alumina (Al2O3), titanium oxide (TiO2), indium oxide (InO3), tin oxide (SnO2), tantalum oxide (Ta2O5), or zirconia (ZrO2), in terms of obtaining high permeability (see Patent Literature 1.).

Method for producing anti-fouling coating film, and anti-fouling coating film