In a vertical resolution correcting circuit, a noncorrelation component in a vertical direction of a luminance signal included in a video signal is detected. In a region where it is considered that the detected noncorrelation component consists of vertical changes in the luminance signal itself, emphasis, which increases and decreases with a predetermined characteristic, is put on the level of a reproduced luminance signal. However, when the level of the noncorrelation component is higher than a level equal to the amplitude of a synchronizing pulse or an equalizing pulse of the video signal, emphasis is not put on the level of the reproduced luminance signal so as not to cause malfunction.

1. Field of the Invention
The present invention relates to vertical resolution correcting circuits and, more particularly, to a circuit for correcting vertical resolution of each of a luminance signal and a chroma signal which constitute a video signal.
2. Description of the Background Art
Conventionally, various techniques for correcting vertical resolution as well as reducing noise components of each of a luminance signal and a chroma signal which constitute a video signal are adopted for the purpose of improving picture quality in video recording and reproduction apparatus such as a video cassette recorder (hereinafter referred to as a VCR).
FIG. 1 is a schematic block diagram illustrating a structure of a reproduction system in a conventional VCR using such a vertical resolution correction technique as well as a noise reducing technique. Referring to FIG. 1, a video signal reproduced from a magnetic tape 1 by a reproduction head 2 is amplified by a pre-amplifier 3 and then applied to a high-pass filter (HPF) 4 and to a low-pass filter (LPF) 5.
A luminance signal (Y signal) is extracted from the reproduced video signal by high-pass filter 4 and applied to a luminance signal processing circuit 6. Luminance signal processing circuit 6 includes a double limiter, an FM demodulation circuit, a de-emphasis circuit, a nonlinear de-emphasis circuit, and the like, which are well known, and detailed description of them will be omitted.
Predetermined signal processing is performed on the luminance signal Y by luminance signal processing circuit 6, and the reproduced luminance signal Y is then applied to a vertical resolution correction circuit 7 and has the vertical resolution corrected. FIG. 2 is a block diagram illustrating details of a vertical resolution correcting circuit 7. Such a vertical resolution correcting circuit is disclosed, for example, in Japanese Patent Laying-Open No. 2-15784 (1990).
Referring to FIG. 2, reproduced luminance signal Y, which has been applied from luminance signal processing circuit 6 in FIG. 1 through an input terminal 20 to vertical resolution correcting circuit 7, is applied to an NH delay line (n is a positive integer, 1 in this embodiment, and H indicates a horizontal synchronization period of a video signal) 21, to a positive input of a subtracter 22, and to one input of an adder 26. Reproduced luminance signal YD, which has been delayed by a period of 1H by 1H delay line 21, is then applied to a negative input of subtracter 22 which, and subtracter 22 provides the difference between the present reproduced luminance signal Y and the reproduced luminance signal YD of 1H period before, i.e. the difference between luminance signals in two adjacent horizontal lines, as a noncorrelation luminance signal component .vertline.Y-YD.vertline. in the vertical direction. The noncorrelation signal component is applied to limiter 23 and to a positive input of a subtracter 24, while it is also applied through an output terminal 28 to vertical resolution correcting circuit 14 as illustrated in FIG. 1 to be used for vertical resolution correction of a chroma signal which will be described later. Detailed description of vertical resolution correction circuit 14 will be given later.
Limiter 23, which has a limiter level of 10.multidot.IRE, for example, passes an input having a level within the range of 0.multidot.IRE to 10.multidot.IRE as it is, and, when the level of the input is 10.multidot.IRE or more, provides a fixed output of 10.multidot.IRE. IRE is a unit expressing a level of a video signal, which expresses levels of a video signal ranging from a pedestal level to a white level of 0 to 100. The output of limiter 23 is applied to a negative input of subtracter 24. Specifically, subtracter 24 subtracts the output of limiter 23 from the input of limiter 23, so that the output from subtracter 24 is 0 when the abovedescribed noncorrelation signal component provided from subtracter 22 is at a level within the range of 0.multidot.IRE to 10.multidot.IRE, and, when the level of the noncorrelation signal component is 10.multidot.IRE or more, a signal at a level obtained by subtracting 10.multidot.IRE from the level of the noncorrelation signal component is provided. The output of subtracter 24 is multiplied by K in a K multiplying circuit 25, then applied to another input of adder 26, and added to reproduced luminance signal Y supplied from terminal 20.
FIG. 3 is a graph showing the relation between the level of the noncorrelation signal component (indicated on the abscissa) and the output of K multiplying circuit 25 (indicated on the ordinate), i.e. a characteristic of emphasis on the level of the luminance signal. Referring to FIG. 3, in view of the fact that the noncorrelation signal component .vertline.Y-YD.vertline. usually consists of only noise components in the range of 0.multidot.IRE to 10.multidot.IRE, the output of K multiplying circuit 25 is at 0 level in this range. Specifically, when the noncorrelation signal component is within the range of 0.multidot.IRE to 10.multidot.IRE, reproduced luminance signal Y is provided without emphases through a terminal 27. On the other hand, when the level of the noncorrelation signal component .vertline.Y-YD.vertline. exceeds 10.multidot.IRE, it is considered that this component is almost the original noncorrelation component of the luminance signal, so that a signal which increases according to the increase in the level of the noncorrelation component is added as an emphasis component to reproduced luminance signal Y.
As a result, in a region where the level of the noncorrelation signal component is lower than 10.multidot.IRE (a region where changes in the vertical direction of the luminance signal are even), it does not happen that the noise component is emphasized and added to reproduced luminance signal Y. However, in a region where the level of the noncorrelation signal component is 10.multidot.IRE or more, the noncorrelation signal component is added to the reproduced luminance signal, so that a contour in the vertical direction is emphasized, and resolution of the image as a whole is enhanced.
The reproduced luminance signal on which such contour emphasis processing has been performed is supplied through terminal 27 to a high-pass noise canceler (HPNC) 8 provided in a subsequent stage for reducing noise, cross modulation and beat. An output of HPNC 8 is applied to one input of an adder 9 for Y/C mixing.
A low frequency band converted chroma signal (C signal) is extracted from the reproduced video signal by low-pass filter 5 and applied to an automatic chroma controlling circuit (ACC) 10. The low frequency band converted chroma signal, which has its signal level made constant by ACC 10, has its frequency converted from 629 kHz to 3.58 MHz by a frequency converting circuit 11, to be applied through a band-pass filter (BPF) 12 to a comb filter 13. Comb filter 13 is of a well-known structure, for removing a crosstalk signal generated between adjacent tracks on a magnetic tape. An output of comb filter 13 is applied to a vertical resolution correcting circuit 14 and has the resolution in the vertical direction corrected. FIG. 4 is a block diagram illustrating details of vertical resolution correcting circuit 14. Such a vertical resolution correcting circuit is disclosed, for example, in U.S. Pat. No. 4,443,817.
Referring to FIG. 4, chroma signal C, which has been applied from comb filter 13 in FIG. 1 through an input terminal 30, is applied to one input terminal 31a of a proportional switch 31 and applied to a positive input of a subtracter 32. An output of subtracter 32 is applied to another input terminal 31b of proportional switch 31. Proportional switch 31 synthesizes the signal levels of input terminals 31a, 31b with a ratio of k.sub.1 :k.sub.2 (K.sub.1 +k.sub.2 =1) changing according to a control signal applied to a control input terminal 31c and provides the obtained signal level through an output terminal 31d. The output from the output terminal 31d is applied to a 1H delay line 34 and to one input of an adder 35, while it is also provided as a chroma signal on which vertical resolution correction processing has been performed and applied through an output terminal 42 to adder 9 (FIG. 1) for Y/C mixing in a subsequent stage.
Chroma signal CD, which has been delayed by a period of in 1H delay line 34, is applied to another input of adder 35 and also to an n multiplying circuit (n is 0.7, for example) 33. Chroma signal CD, which has been multiplied by n in n multiplying circuit 33, is applied to a negative input of subtracter 32. As described above, signal C is applied to one input terminal 31a of proportional switch 31, and C-nCD, an output of subtracter 32, is applied to another input terminal 31b, so that the signal level at output terminal 31d is expressed as k.sub.1 C+k.sub.2 (C-nCD).
Accordingly, the noise amount to be removed is increased as the value of k.sub.2 is increased. In such a case, however, the ratio of CD is relatively increased, resulting in the occurrence of chromatic blur.
The above ratio of k.sub.1 :k.sub.2 is changed according to the signal level at control input terminal 31c on the basis of the presence or absence of correlation of a video signal in the vertical direction for the purpose of preventing chromatic blur in the vertical direction in the boundary between colors on a reproduced image. Specifically, in a case where it is determined that a chroma signal has correlation in the vertical direction, the condition of k=0 and k.sub.2 =1 is realized, and an output of proportional switch 31, i.e. an output of vertical resolution correcting circuit 14, is C-nCD. On the other hand, in a case where it is determined that there is no correlation, the condition of k.sub.1 =1 and k.sub.2 =0 is realized, and the output is C. In an intermediate case between both the extreme cases, for example, in a case where the condition of k.sub.1 =k.sub.2 =0.5 is realized, the output is 0.5C+0.5 (C-nCD).
Such determination of presence or absence of correlation in the vertical direction is performed by detecting correlation of a chroma signal and correlation of a luminance signal. Specifically, referring to FIG. 4, a noncorrelation signal component of the luminance signal supplied from output terminal 28 of vertical resolution correcting circuit 7 in FIG. 2 is applied through a terminal 38 and a LPF 39 to a rectangular wave correlation detecting circuit 40 which provides a detection output when the noncorrelation signal component of the luminance signal exceeds a predetermined threshold value. The output of rectangular wave correlation detecting circuit 40 is applied to one input of an adder 41. A noncorrelation signal component of the chroma signal provided from an adder 35 is applied through BPF 36 to a rectangular wave correlation detecting circuit 37 which provides a detection output when the noncorrelation signal component of the chroma signal exceeds a predetermined threshold value. The output of rectangular wave correlation detecting circuit 37 is applied to another input of adder 41, and an output of adder 41 is applied to a control input terminal 31c of proportional switch 31.
Specifically, in this conventional technique, generation of chromatic blur in a reproduced image is prevented by changing the ratio of synthesis in proportional switch 31 according to the degree of correlation in the vertical direction in both of a luminance signal and a chroma signal on the assumption that the degree of vertical correlation of the luminance signal has relatively strong relevance to the degree of vertical correlation of the chroma signal.
The chroma signal on which such chromatic blur preventing processing has been performed is applied through a terminal 42 to another input of adder 9 (FIG. 1) for Y/C mixing. Then, a reproduced video signal on which various vertical resolution correcting processing has been performed is provided from adder 9.
The conventional vertical resolution correcting circuit 7 illustrated in FIG. 2 has a problem as described in the following. In circuit 7 in FIG. 2, if the noncorrelation signal component of a luminance signal exceeds 10.multidot.IRE, an amount of emphasis which increases according to the noncorrelation signal component increase is added to a reproduced luminance signal as described with reference to FIG. 3, and such addition is also performed in a case where the noncorrelation component exceeds 40.multidot.IRE as shown in FIG. 3.
FIG. 5 is a partial enlarged diagram of a vertical blanking period of a video signal, wherein each of the synchronizing pulses and equalizing pulses has an amplitude of 40.multidot.IRE. Accordingly, when a noncorrelation component is detected with respect to an interval of 1H period as indicated by A in a discontinuous part in the boundary between an equalizing period and a video period, the amplitude of the equalizing pulse, 40.multidot.IRE, is erroneously detected as the noncorrelation component of the luminance signal, and an amount of emphasis corresponding to 40.multidot.IRE is added unnecessarily to the video signal as indicated by a part B depicted with oblique lines in FIG. 3, so that the picture quality of a reproduced image is degraded.
The conventional vertical resolution correcting circuit 14 illustrated in FIG. 4 has a problem as described in the following. According to the conventional example illustrated in FIG. 4, an output of circuit 14 is controlled on the assumption that the degree of vertical correlation of a luminance signal has relevance to the degree of vertical correlation of a chroma signal. However, in an actually reproduced video signal, there is a case where only a chroma signal changes largely although a luminance signal changes little, and there is also a case converse to it, for example. Accordingly, in such cases, there is a problem that it is impossible to perform vertical resolution correction operation on the basis of the degree of correlation of a chroma signal in circuit 14 in FIG. 4.
In addition, circuit 14 in FIG. 4 has a problem that the circuit configuration is complicated because the ratio of the proportional switch is changed on the basis of correlation detecting results of both of a luminance signal and a chroma signal.

Vertical resolution correcting circuit for video signal


A semiconductor device having an NMOS and a PMOS device formed thereon is provided. The NMOS device has additional spacers formed alongside the gate electrode to allow the silicide region to be formed farther away from the gate electrode. By placing the silicide region farther away from the gate electrode, the effects of the lateral encroachment of the silicide region under the spacers is reduced, particularly the leakage. A method of forming the semiconductor device may include forming a plurality of spacers alongside the gate electrodes of a PMOS and an NMOS device, and one or more implants may be performed to implant impurities into the source/drain regions of the PMOS and NMOS devices. One or more of the spacers alongside the gate electrode of the PMOS device may be selectively removed. Thereafter, the source/drain regions may be silicided.

Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. Generally, the MOSFETs include a gate electrode formed on a gate dielectric, which is formed on a substrate (usually a silicon semiconductor substrate). Source/drain regions are formed on opposing sides of the gate electrode by implanting N-type or P-type impurities into the substrate. Current flowing through the source/drain regions may then be controlled by controlling the voltage levels applied to the gate electrode.
To increase switching speed and decrease contact resistance, the source/drain regions are often silicided. Typically, the source/drain regions are silicided by forming a metal layer over the source/drain regions and performing an anneal. The annealing causes the metal layer to react with the silicon substrate, thereby forming a silicide layer on the source/drain regions. The silicide layer, however, may cause problems.
One problem is lateral encroachment of the silicide region below the spacers. It has been found, particularly in the case of nickel silicide formed in a substrate doped with N-type impurities, that the silicide region may encroach laterally underneath the spacers, thereby increasing leakage current and decreasing device performance. As device sizes decrease, the lateral encroachment of the silicide region may cause the device to fail or to become unreliable.
Therefore, there is a need for a method and a device that reduce the lateral encroachment of the silicide region.

Silicided regions for NMOS and PMOS devices

Taiwan Semiconductor Manufacturing Company, Ltd.


This invention is directed toward a new type of herpesvirus particle (e.g., HSV-1), herein designated pre-viral DNA replication enveloped particles (PREPS), and methods of preparing said particles. These particles are non-infectious and can be prepared reliably to a high ratio of HSV-1 PREPS to infectious virus of at least 10.sup.7 :1. PREPS can be produced under conditions wherein viral DNA replication is blocked through the use of suitable drugs (e.g., acyclovir [ACV]; cytosine-.beta.-D-arabinofuranoside [ara C]) or by using an HSV mutant defective in viral DNA synthesis. Compositions comprising HSV-1 PREPS are disclosed wherein said particles have the following characteristics: a) the PREPS lack a viral capsid; b) the PREPS lack viral DNA; c) the PREPS contain reduced quantities of the proteins 273K (VP1-2), 82/81K (VP13/14), 57K (VP17, gD), and 40K, as compared to HSV-1 L particles; and d) the PREPS contain increased quantities of the proteins 175K (VP4, IE3), 92/91K (VP11/12), and 38K (VP22), as compared to HSV-1 L particles. These particles are useful, inter alia, for the generation of HSV-specific immunological and diagnostic reagents.

1. Field of the Invention
This invention relates to a form of herpesvirus particles suitable for use in vaccination, the preparation of such particles, and vaccines containing them.
2. Description of the Related Art
Herpes simplex virus type 1 (HSV-1) light particles (L-particles) are non-infectious virus-related particles, produced in approximately equal numbers with virions throughout the virus replication cycle in BHK cells (Szilagyi and Cunningham, 1991, J. Gen. Virol. 72, 661-668; Rixon et al., 1992, J. Gen. Virol. 73, 277-284). Similar L-particles have been isolated from pseudorabies virus (PRV); equine herpesvirus type 1 (EHV-1) (McLauchlan and Rixon, 1992, J. Gen. Virol. 73, 269-276); bovine herpes virus type 1 (BHV-1); varicella-zoster virus (VZV) (Dargan and Subak-Sharpe, unpublished) and HSV-2 (MacLean, unpublished). Because of the non-infectious nature of L-particles they have great potential as candidate vaccine materials (PCT Patent Application Publication No. 92/19748).
Comparative analysis of the protein composition of HSV-1, PRV and EHV-1 L-particles and virions show that most or all the virion tegument and envelope proteins are present in L-particles, but the nucleocapsid proteins are not present. Five phosphoproteins not detectable in HSV-1 virions are associated with HSV-1 L-particles (Szilagyi and Cunningham, 1991, J. Gen. Virol. 72, 661-668; McLauchlan and Rixon, 1992, J. Gen. Virol. 73, 269-276).
HSV-1 L-particles have been shown to be as efficient as virions in supplying functional tegument proteins to target cells. Thus, L-particles are biologically competent and have the potential to participate in the early stages of HSV-1 infections (McLauchlan et al., 1992, Virology, 190, 689-688).
Using an HSV-1 ts mutant (ts1201) (Preston et al., 1983, J. Virol. 45, 1056-1064) having a mutation in gene UL26, Rixon et al., 1992, J. Gen. Virol. 73, 277-284, demonstrated that L-particles were generated independently of virion maturation. Under non-permissive conditions ts1201 failed to make infectious virions but produced L-particles which were identical to typical wild-type virus L-particles in appearance and protein composition. Although viral DNA is synthesised normally in cells infected with ts1201 under their non-permissive conditions, viral DNA packaging into virions is blocked (Preston et al., 1983, J. Virol. 45, 1056-1064).
Although L-particles can be prepared to be substantially free of infectious virions, a typical preparation of HSV-1 L-particles containing a ratio of from 3.times.10.sup.3 :1 to 1.times.10.sup.4 :1 L-particles: infectious virions, there is a problem to improve on this ratio. Further, although the L-particles lack a capsid and the DNA within it, L-particle preparations still contain some viral DNA present in contaminating virions and/or possibly in the form of free nascent viral DNA. It would be advantageous to reduce the amount of such DNA present in the L-particle preparations, in order more easily to convince regulatory authorities of the safety of a vaccine containing them.
Additional prior art, the relevance of which becomes clear only in the context of the present invention, is referred to below after "Summary of the invention".

Herpesvirus pre-(viral DNA replication) enveloped particles


The invention can be defined in its most general form as the method for sheet material corrugation and can be used for production of aircraft curvilinear sandwich panel folded structure light corrugated core. With the aim to broaden the technological capabilities the corrugated blank is compressed from its sides to joining of ridges providing in its lateral section the curvature radius defined by the curvilinear folded structure design parameters and fixed in such condition block is thermally treated for inner stresses relief in the article material whereupon it is stretched to the curvilinear folded structure parameters given.

Known is a method for curvilinear folded structure production at geometrical conjunction of the article and the transformable dies wherewith the article is shaped. It includes, at the first stage, placing of sheet blank onto the lower shaping transformable die whereas the similar upper transformable die is placed onto the blank. Equidistantly placed the upper and the lower transformable dies consist of plane shaping elements made in the form of parallelograms; the shaping elements are connected to each other along all the sides with the use of hinges.
At the second stage, when transforming the dies, e.g. with the use of vacuum bag, the upper and the lower transformable dies embedding into the blank change the curvature whereas the blank is put into relief form with crimp design parameters given (V. I. Khaliulin, Technological schemes for sandwich structures production, KSTU, Kazan, 1999.—168 p., p. 128-133.—ISBN 5-7579-0295-7).
The main short-coming of herein-presented method for sheet blank corrugation whereat the curvilinear article is attained is that with the aim to provide the given folded structure curvature defined with the use of mathematical computation are the distance between the upper and the lower transformable dies, the curvature radius required for imparting to the blank before shaping, and the dimensions of transformable dies shaping elements ridges. In addition, geometrical dimensions of the upper and the lower dies have different linear parameters. It results in labor-consuming mutual placement of dies at the first stage of shaping. It is impossible to attain the calculated value of the article curvature at failure to execute the strict geometrical conjunction of the upper and the lower shaping dies.
Known is a method for production of curvilinear corrugated core including the marking-out of protrusions and recesses zigzag lines on the blank development whereat the angles of vertexes are accordingly equal to 2α and 2β whose values are related to definite zigzag corrugated core design parameters, and further bending of blank along the marked-out lines (Inventor's certificate No. 1,785,154 USSR, Int. C1. B 32 B 15/00, Method for production of curvilinear sandwich panel with zigzag corrugated core, Bulletin No. 42 of Nov. 16, 1992). The given method is taken as a prototype.
The main short-coming of herein-presented method is that it is possible to produce folded structures only with longitudinal direction of zigzag crimps, e.g. in direction of cylinder generatrix. Yet, in production, e.g. of aircraft fuselage panels, it is necessary that the core should have lateral direction of crimps and should meet the use requirements for condensate removal from panels inner cavities.

Method for curvilinear folded structure production

Otkrytoe Aktsionernoe Obschestvo “Kazansky Nauchno-Isledovatelsky Institute Aviatsionnoi Tekhnologii”


A bun laner sorts buns into a predetermined number of lanes, for providing buns to a packaging unit. The bun laner detects when some lanes are filling faster than other and closes those lanes while the other lanes fill. A vacuum may be used to hold buns in a filled lane in order to close the lane. An optical detection unit may be used to determine when a bun has been stationary at a certain position in the lane for a predetermined amount of time.

1. Technical Field
This invention relates in general to food packaging equipment and, more particularly, to equipment for sorting buns into lanes.
2. Description of the Related Art
Commercial bakeries use high-speed packaging equipment to bag hamburger rolls, hot dog rolls, and other bread products (collectively, "buns"). Typically, the buns are packaged in arrays of one or more layers; for example, a sixteen bun package may package the buns in a four-by-four array and a 32 bun package may package the buns in two four-by-four layers.
In order to arrange the rolls in an array, a bun laner is used. The bun laner takes randomly arranged buns on a conveyer and aligns the buns into rows or "lanes". When a sufficient number of buns are in each lane, a group is transported to a packaging machine.
Unfortunately, the randomly arranged buns do not evenly fill the lanes under normal circumstances. If a certain lane is not being filled as quickly as the other lanes, then the packaging machine must wait, slowing the packing process. Accordingly, the bun laner generally requires human intervention to direct the buns to the lanes evenly. Manual supervision of the machines, of course, increases the cost of packaging the buns and wastes human resources on a tedious chore.
Therefore, a need has arisen for a bun laner that does not require human supervision.


The present invention relates to polyurethane foam-forming composition containing polysilsesquioxanes that provide high resilience flexible polyurethane molded foams having improved foam dimensional stability.

In the art of making flexible polyurethane foam, it is known that by utilizing foam-forming formulations incorporating a highly reactive organic polyisocyanate and a high molecular weight polyol having a certain level of primary hydroxyl group content, a foam with improved resilience and other desirable physical properties can be accomplished. Such resulting foams have come to be referred to in the art as "high resilience" foams. Resilience is defined as the ability to return readily to original shape and dimensions after a deforming force has been applied and removed from a body. In polyurethane foam technology, the industry generally considers "Sag factor" to be the characteristic which differentiates high resilience foams from conventional foams. This Sag factor is a measure of support provided by a cushioning material and it represents the ratio of indent load deflection, ILD, at 65 percent deflection to that at 25 percent deflection (as per ASTM D-1564-64T). According to SPI standards, conventional, flexible foams exhibit a Sag factor of about 1.7 to 2.2, while high resilience foams display a factor of above about 2.2 to about 3.2.
High resilience foams have found widespread application as cushioning material in furniture and automotive seating. Most significantly, these foams have been utilized in the automotive industry for making molded auto seats. Most of the already established polyurethane foam techniques can be readily applied to high resilience foams. However, foam stabilization and collapsing, one particular area of technology, has been found to be markedly non-transferable. Due to the highly reactive nature of the reaction mixture from which the high resilience foams are prepared, such foams have been found to exhibit characteristic shrinkage upon demolding and cooling. Conventional foam reaction mixture components, which serve to stabilize the composition as it reacts, foams, and solidifies, are ineffective to prevent shrinkage in high resilience foaming reactions.
To meet the stabilization requirements of high resilience foams, there have been developed various approaches in which so-called "cell-openers" are incorporated in the foam. These added ingredients generally take the form of particles having diameters of about 2 micrometers or smaller. One technique involves the formation of "polymer-polyol" systems, which are produced from ethylenically unsaturated monomers and polyols, as exemplified by the disclosures in U.S. Pat. Nos. 3,383,351; 3,652,639 and 3,823,201. These polymer-polyols commonly are mixed with conventional polyether polyols and used as the starting polyol reactant.
Another U.S. Pat. No. 4,278,770, teaches that polyol compositions containing effectively dispersed particulate material featuring critical dispersion characteristics can be used to stabilize foam reaction in preparing high resilience polyurethane foam.
In U.S. Pat. No. 4,374,209, polymer particles are formed in a polyol by reacting an organic isocyanate with an olamine, an organic compound containing one or more hydroxyl groups and one or more amine groups. While this may provide a dispersion with utility in high resilience foam applications, the amine group is generally catalytic to the isocyanate-water reaction, resulting in a narrow processing lattitude. As such, the system is sensitive to small catalyst quantity variations. Very slight deviations from these limits can cause overly fast reaction with insufficient resilience occurring in the foam product.
When high resilience polyurethane foams are prepared it is important to ensure that the foam has a sufficient quantity of open cells to prevent shrinkage on cooling. The preparation of high resilience polyurethane foam is nearly always accompanied by the formation of some closed cells. The presence of closed cells substantially reduces the dimensional stability and flexibility of the foam while increasing its rigidity and brittleness. The closed cell content of a foam can be reduced by mechanical means such as crushing or flexing of the foam during its curing process causing the closed cells to be ruptured and opened. Alternatively, the extent of formation of closed cells can be minimized in part by careful selection of cell opening agents and their levels for the preparation of the foams.
A common problem with nearly all conventional cell openers is that they cause deterioration in the mechanical properties of the foams, especially compressive strengths. Since they do not contribute to the overall properties of the foam, except to open cells, it is desirable to reduce the quantity of cell opener required or modify it in such a way that it may contribute to the properties of the foam.
Accordingly, the present invention provides a cell-opening agent, which can assist in cell opening and maintain the mechanical properties of high resilience flexible polyurethane foam.

Polyurethane foam-forming compositions containing polysilsesquioxane cell opening agents


A voltage-level shift apparatus includes a first level shift unit, a second level shift unit, a charging unit, and a discharging unit. The first level shift unit receives a reference voltage and a power voltage to output a level-shifting voltage. The second level shift unit is connected to the first level shift unit and receives the level-shifting voltage. The charging unit receives a control voltage to provide an output voltage. The discharging unit is connected to the charging unit and receives the control voltage and the reference voltage. When the control voltage turns on the charging unit and turns off the discharging unit, the charging unit is charged by the level-shifting voltage. When the control voltage turns off the charging unit and turns on the discharging unit, the discharging unit is discharged from the output voltage.

1. Technical Field
The present disclosure relates generally to a voltage-level shift apparatus and a method of operating the same, and more particularly to a voltage-level shift apparatus which is applied to a motor driver circuit and a method of operating the same.
2. Description of Related Art
The high-speed switching products currently on the market, such as the upper-bridge drive circuit of the brushless DC motor (BLDC), the energy control circuit of the LEDs, need the high-voltage drive circuit. Also, the voltage level of the drive voltage is usually higher than the input voltage of the system.
For the existing technology, it is easy to design the charge pump IC to provide a higher voltage level so that the charge pump IC is widely used in the industry. However, the charge pump IC needs higher costs. In addition, the lowest operation voltage and the charging and discharging efficiency are limited for the charge pump IC.
Accordingly, it is desirable to provide a voltage-level shift apparatus and a method of operating the same which is designed according to the application requirements by the research and development personnel to provide the voltage-level shift apparatus having customizing operation voltage and charging and discharging efficiency, thus avoid the over design condition.

Voltage-level shift apparatus and method of operating the same


A receiving device in which the shielding performance is improved to solve a pulling problem in a receiving device of a direct conversion system is provided.

As an example of electronic equipment having a receiving device that receives a high frequency input signal, a television receiver can be mentioned. The television receiver includes a receiving device that receives a high frequency input signal through an antenna.
In a conventional receiving device, a so-called heterodyne system is employed as shown in FIG. 11.
In the heterodyne system as shown in FIG. 11, a high frequency input signal f is input to an antenna 1000. The high frequency input signal f is mixed with a mixing frequency f1 to be selected, so that the intermediate frequency (f−f1) is obtained. Further, after passing through a filter or the like, the intermediate frequency (f−f1) is mixed with a constant frequency f2, and a base band signal ((f−f1)−f2) is obtained. This base band frequency has a range of DC (direct current) to several ten MHz.
Note that in this case the relation between f, f1 and f2 is f=f1+f2.
However, the heterodyne system mentioned above requires a large number of components and frequency conversion of many times, which results in a high cost.
Then, as shown in FIG. 12, a direct conversion system having a small number of components and a simple structure is beginning to be used. In the direct conversion system, when a high frequency input signal f is input to an antenna 1010, the mixing frequency f1 which is the same as the selection frequency is mixed with the high frequency input signal, and the differential signal is taken out to obtain (f−f1) as a base band signal.
Note that, in this case, the relationship between f and f1 is f=f1.
In such a receiving device, as shown in FIG. 13, an amplifier 1020, a filter 1024, a direct conversion unit 1026 and a digital demodulator 1028 are formed on a substrate 1016. A shield case 1030 and a shield cover 1040 are detachably loaded onto the substrate 1016, and the shield case 1030 and shield cover 1040 shield each elements on the substrate 1016 from high frequency waves.
The shield cover 1040 is engaged with ribs 1061 in the shield case 1030, using a plurality of claws 1060 on the peripheral portion thereof to be hooked, and the shield cover 1040 and shield case 1030 are contacted and fixed to each other.
The shield case 1030 has a frame 1055, and an inner partition plate 1056 is disposed in the center of the frame 1055. The frame 1055 has a plurality of claws 1050, and when the claws 1050 are fixed into concave portions 1017 in the substrate 1016, the shield case 1030 is fixed to the substrate 1016.
With the above structure, the amplifier 1020, the filter 1024, the direct conversion unit 1026 and the digital demodulator 1028, each of which is a functional block of the substrate 1016, are surrounded and shielded.
The inner partition plate 1056 of the shield case 1030 is, for example, disposed to shield between the filter 1024 and the direct conversion unit 1026, where the partition plate 1056 is soldered to the ground of the substrate 1016 to function as a shield plate.

Receiving device and television receiver

Abstract: The receiving device includes: a substrate on which an amplifier 30 that amplifies high frequency input signals, a filter 34 that passes only intended signals and removes unintended signals by tuning the amplified high frequency input signals and a direct conversion unit 36 that converts and detects directly the high frequency input signal from the filter; a first high-frequency shielding portion 90 fixed to a substrate 20 and which stands at the boundary between the filter and the other units for preventing radiation of the high frequency electro-magnetic wave that is induced from the filter to the space; and a second high-frequency shielding portion 60 provided facing and close to the filter surrounded by the first high-frequency shielding portion 90 and which prevents radiation of high frequency electro-magnetic waves induced from the filter to the space, together with the first high-frequency shielding portion 90.


A passive ultrasonic tag is provided and an ultrasonic reading system is constructed more simply and records and/or reads information more reliably by using ultrasonic waves for transmission/reception. A passive ultrasonic tag according to a first embodiment of this invention includes a tag body. The tag body has two or more holes disposed extensively on a surface of the tag body. The holes have bottoms at predetermined depths from the surface of the tag body. The depths of at least two of the two or more holes are set to different values. As a result, when a three-dimensional range including surfaces and bottoms of the two holes is scanned using ultrasonic waves, the ultrasonic waves are reflected in different manners on the basis of the depths of the two holes. This allows information to be recorded and read.

Recently, the need for management of product-specific information, management of tracking information, and the like has been increased and there has been a growing trend toward introduction of contactless tags. Among others, applications of a radio frequency identification (RFID) system using a tag and a reader have actively been studied. Such applications include one in which by conducting wireless communications in which a query signal is broadcast to a product to which a tag is attached, an object to which a tag is attached, or a human body to which a tag is attached and then after obtaining a response from such a tag, stock control of the product, observation of the moving object, or observation of behavior of the human is conducted.
Typical RFID systems use electromagnetic waves. On the other hand, there have also been demands to apply an RFID system to environments in which RFID systems cannot operate, such as an environment in which electromagnetic radiation is present, a situation in which the tag is embedded in water or metal, or an environment in which the tag is affected by electromagnetic shielding caused by metal. Moreover, there is a report that some types of electromagnetic waves may negatively affect the health of human bodies, so concerns about safety of electromagnetic waves have not completely been dispelled.
For a tag using electromagnetic waves, power to drive the tag, such as absorbing energy of a query signal to activate a chip inside the tag must be supplied by electromagnetic induction or via microwaves from the reader. Therefore, disposition of an internal circuit for power supply must be considered, thereby requiring a minimum of one complex system. Thus, under a harsh environment in which the tag is subjected to physical or chemical stress, such as that caused by staining of the surface, peeling, corrosion, or wear, there is no guarantee that reliability of operation of the tag will be maintained.
Ultrasonic tags, which use ultrasonic waves instead of electromagnetic waves, have been considered. These tags are active tags, a type of tag in which an ultrasonic transmitter is disposed for transmitting ultrasonic waves in the vicinity of the ultrasonic tag. In these ultrasonic tags, the communication distance between the tag and reader can be made longer to a degree that ultrasonic waves transmitted from the tag can reach the reader. These tags have been applied to technologies, such as one that calculates the distances from one tag to a plurality of readers by using the differences in the time taken for ultrasonic waves transmitted from the tag to reach the respective readers, and by identifying the three-dimensional location of the tag by three-point measurement based on these distances.
However, with regard to active tags, the use of a complex system, such as an energy supply system, is unavoidable due to the need to transmit ultrasonic waves near the active tags. Such a complex system will be costly in terms of battery replacement or charging.
On the other hand, passive tags have a relative advantage in that while they make some compromise in terms of communication distance, they require no battery and can easily be downsized. However, as for passive RFID tags using electromagnetic waves, complexity is unavoidable, such as including an IC chip and antenna.

Passive ultrasonic tag and method and system for reading recorded information

International Business Machines Corporation


A printing system including printing equipment in which, even if the equipment are interconnected through an interface pursuant to the IEEE 1394 standard, the printing image may be set to effect printing. There is provided a CPU 23 for generating the printing control information containing the text printing image information indicating the picture processing contents for the text at the time of printing and the picture printing image information indicating the processing contents for a picture at the time of printing. There is also provided a data conversion unit 13 which manages control so that picture data and the printing control information will be contained in a packet consistent with the IEEE 1394 standard and sent as output to a printer device 5, and so that the picture data contained in the packet sent as output to the printer device 5 will be printed in accordance with the printing control information. When packets are transmitted/received between the equipment interconnected through the IEEE 1394 interface to print the picture data, the picture processing consistent with the text printing image information and the picture printing image information is performed on the picture data on the side printer device 5 to print the text or the picture.

1. Field of the Invention
This invention relates to a printing system for printing an image by a printing device to which the system is connected over an interface pursuant to IEEE 1394 standard. More particularly, it relates to a printing controlling method and a printing controlling device, a printer device, a printing method and a printing system, in which it is possible to set the quality in printing a text or an image consistent with a user's request.
2. Description of Related Art
The IEEE (The Institute of Electrical and Electronics Engineers) 1394 standard defines physical and electrical standards of connectors provided in respective interconnected equipment. The respective equipment, having an interface pursuant to the IEEE 1394 standard, may be physically interconnected to realize e.g., hot plug and play which automatically sets the high-speed transmission/reception of digital data and interconnection of equipment. So, the IEEE 1394 standard is in widespread use as a standard serial interface reference in the related technical field.
This IEEE 1394 interface is also in widespread use not only in the field of computers but as an interface interconnecting plural AV equipment. Specifically, when a set top box (STB) for receiving satellite broadcast for display on a television device and a printer device for printing an image are interconnected over the IEEE 1394 interface, the STB controls the printer device using a function control protocol (FCP) and an AV/C protocol. The STB and the printer device mount the FCP and the AV/C protocol and are in operation in accordance with an FCP command and an AV/C command.
However, in the printer device having the above-mentioned IEEE 1394 interface or in the STB controlling the printer device, in which there are prescriptions concerning the method for transmitting data representing an image for printing, there are no prescriptions on the printing image quality, such that there lacks a technique for performing the printing with an image desired by the user.

Method and device for controlling the printing, printer device, printing method, printing system and printing method


An optical receiving apparatus includes a signal brancher for branching an optical input signal received from an optical transmission line into a first signal component and a second signal component, a clock extractor for extracting a clock having an amplitude from the second signal component, and a discriminator for discriminating the first signal component. The apparatus also includes a threshold controller for generating a discrimination threshold for the discriminator according to a relationship between the extracted clock amplitude and a bit error rate to which the extracted clock amplitude corresponds.

In an optical transmission system, transmission characteristics of the transmission system are measured at the time of installation and a discrimination threshold of a received signal light at a receiving terminal is determined according to the obtained result. Thereafter, a signal value of the received signal light is discriminated with the discrimination threshold.
As mentioned above, in conventional systems, the discrimination thresholds are fixed. However, it has been understood that the transmission characteristics of the optical transmission line fluctuate with time and, consequently, the optimum discrimination threshold of the received signal light varies as well. FIG. 18 shows a measured result of a time variation of an optimum discrimination threshold. The vertical line and horizontal line show the optimum discrimination threshold and elapsed time respectively.
If the discrimination threshold of the received signal light is remained at the fixed value in spite of such variation, a bit error rate (Q value) becomes deteriorated.


A dual drum winding machine is provided for winding a web of material, e.g., textile material, around a central core. The winding machine is operable on a continuous basis and has a leading winding drum and a succeeding winding drum. The succeeding winding drum is positioned lower than the leading winding drum such that the succeeding winding drum supports a greater proportion of the weight of a forming web roll when the roll is in a winding position supported by both the leading and succeeding winding drums. A method of forming a web roll using the winding machine is also provided.

1. Field of the Invention
The invention relates to a winding machine for winding a web of paper or other raw material or textile stocks, e.g. polymeric films, into large rolls. More particularly, it relates to a dual-drum winding machine capable of producing uniformly tightly wound rolls of such web material across the entire radius of the roll.
2. Description of the Related Art
In conventional dual-drum winding machines, a web of material, e.g. paper, polymeric sheet or film, textile material, etc., is continuously wound on a central core from a source of the web material that is fed continuously from outside the winding machine. As more of the web material becomes wound around the central core, the diameter of the resulting roll increases commensurately, with the increasing diameter roll being supported in a position substantially centered between two adjacent and level support rolls or drums.
U.S. Pat. No. 5,593,106 discloses a typical conventional dual-drum winder characteristic of the prior art, and is incorporated herein by reference. FIG. 1 of the '106 patent shows the web roll of increasing diameter supported in a rolling position B between two adjacent and level winding drums 36 and 38. As the drums 36 and 38 are rotated clockwise, the web roll is thereby caused to rotate counterclockwise and thus to wind additional web material thereon from the web material source shown at W in FIG. 1 of '106. Once the web roll has achieved its final diameter D, the piston-driven cutter 48 extends upward to cut the web source from the now complete web roll, and the finished roll is urged out of the machine via an ejection mechanism comprising a sweep arm 42 and associated piston 44 as shown in the figure.
From FIG. 1 of '106 and the foregoing description, it will be evident to those skilled in the art that existing winding machines such as that disclosed in '106 rely on the web source, which supplies the web material to the winding machine, to also supply the necessary web tension to provide a tightly wound finished web roll. This arrangement results in poorly tensioned web rolls causing the finished rolls to have nonuniform radial or layer density (density of web material on the finished roll measured in layers of web material per radial inch).
In addition, as the source web material is severed from the finished web roll, a long and loose untensioned flap portion of source web material results. This loose flap portion is pressed against a newly supplied central core to begin forming the next successive web roll. The loose flap portion is not tensioned by the web source because the web is severed downstream of the leading drum roller (e.g. roller 32 in FIG. 1 of '106). Hence, the loose flap portion of the web material typically includes myriad folds, creases, lines, wrinkles and other random undesirable gatherings of web material characteristic of untensioned webs. As this loose flap portion is laid against the spinning newly supplied central core, additional layers of web material are wound thereover as the web roll grows. As these additional layers are wound on the creased, untensioned underlying layers, they too become creased and folded, exhibiting undesirable gathering characteristic of web material that has not been properly tensioned. The fact that the web is conventionally severed some distance (e.g. 12 inches, or up to 2 or 4 feet or more) from the newly supplied central core contributes significantly to this problem because the resulting loose flap is very long; sometimes many times the circumference of the central core. The overall result is that a significant portion of the finished web roll within a certain radial distance from the central core is unusable in subsequent processing operations for which tightly and uniformly tensioned material webs are required. In fact, the folds and creases in the rolled web material can lead or contribute to exactly the edge profile defects of finished web rolls with which the '106 patent was principally concerned.
Accordingly, there is a need in the art for a dual-drum winding machine that overcomes the aforementioned deficiencies characteristic of the prior art. Preferably, such an improved dual-drum winding machine will not rely solely on the web source to supply web tension to the forming web roll. Also preferably, such an improved machine will significantly minimize or substantially eliminate the loose flap portion supplied to fresh central cores which has been characteristic of and problematic in the prior art.


A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate,
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, the present invention provides a non-volatile synchronous flash memory that is compatible with existing SDRAM package pin assignments. It will be apparent from reading the detailed description that system designers with knowledge in SDRAM applications could easily implement the present invention to improve system operation. In one embodiment, a synchronous memory device comprises an array of memory cells arranged in rows and columns, a clock connection to receive an externally provided clock signal, and control circuitry to perform a first read operation of a first row of the array in response to a first externally provided active command, and perform a second read operation on a second row of the array in response to a second externally provided active command. The control circuitry does not require a precharge time period during a time period between the first and second externally provided active commands.
In another embodiment, a synchronous memory device comprises an array of memory cells arranged in rows and columns, a clock connection to receive an externally provided clock signal, and control circuitry to perform a first read operation on a first row of the array to output data from the first row on an external connection during a clock signal transition. The control circuitry is adapted to receive a read active command on the clock signal transition to initiate a read operation of a second row of the array.
A method of operating a synchronous flash memory device is also provided. The method comprises receiving a first active read command and a memory array first row address on a first clock signal transition, initiating a first memory read operation in response to the first active read command, and receiving a read command and a memory array column address on a second clock transition that is a first predetermined number of clock transitions following the first clock signal transition. The method further comprises providing data on a data connection that was read from the memory array at the first row address. The data is provided on a third clock transition that is a second predetermined number of clock transitions following the second clock signal transition. A second active read command and a memory array second row address are received on the third clock signal transition, and a second memory read is initiated in response to the second active read command.

Elimination of precharge operation in synchronous flash memory


A porous refractory product includes a matrix of sintered silicon carbide having a porosity of about 45% to about 65%. The matrix is formed by heating in a noble gas atmosphere a cast preform including a mixture of alpha-silicon carbide and boron carbide each having a particle size of less than about 1 micron. The heating causes the formation of gaseous SiO within the silicon carbide matrix, which, in turn, forms pores having an average size of less than about 1 micron. The porous refractory products herein are suitable for use in a variety of applications including for use in high temperature particulate filtering applications.

1. Field of Invention
This invention relates to porous ceramic or refractory products suitable for a variety of applications wherein a porous product is desired. More particularly, the invention concerns a porous ceramic product made of silicon carbide and a method of making the same. The product of the present invention is especially well suited for use in the production of diesel particulate filters.
2. Description of Related Art
Porous ceramic materials are known in the prior art, including porous silicon carbide. Such porous silicon carbide is discussed for example in Shobu et al. U.S. Pat. No. 5,585,313, Atwell et al. U.S. Pat. No. 5,358,910, Gadkaree et al. U.S. Pat. No. 6,555,031 and Way et al. U.S. Pat. No. 6,214,078. Various methods are used to produce porous silicon carbide, but generally, such methods employ a select grade of silicon carbide and elevated firing temperatures that exceed 2300° C.
Porous ceramic materials are used in a variety of applications including high temperature filters as discussed in Way et al.; diffusers as discussed in Veeder et al. U.S. Pat. No. 5,863,031; diesel particulate filters as discussed in Nagi et al. U.S. Pat. No. 5,863,311; Ban et al. U.S. Pat. Nos. 5,961,931 and 6,024,927 and Cheng U.S. Pat. No. 6,835,224; and in armor applications as discussed in Tarpinian U.S. Pat. No. 5,469,773, McCormick et al. U.S. Pat. No. 6,609,452 and Aghajanian et al. U.S. Pat. No. 7,104,177. All twelve of the aforementioned patent documents are incorporated herein by reference
The present invention provides a porous silicon carbide and a method of making the same that offers several distinct advantages over porous products of the prior art. For example, the present invention provides a product that displays uniform porosity and it does not require the use of a special distribution of silicon carbide particles as taught by Way et al. Additionally, the process of the present invention does not require the elevated firing temperatures as taught by Way et al., Shobu et al., Atwell et al. and Gadkaree et al. Further, the porous product of the present invention may be produced without the use of expensive thermoplastic binders as taught by Atwell et al. and Gadkaree et al.


Techniques for automatically maintaining continuity in animation across discrete animation changes. Smooth animation is achieved without forcing the animator to manually calculate compensation values or introducing extra controls to the models that are animated. Continuity or smoothness of the animation is maintained as varying aspects of the animation change under continued authoring.

The present invention relates to the field of computer-generated imagery (CGI) and animation, and more particularly to techniques for maintaining continuity of animation across discrete animation changes.
Animation tools generally provide animators different sets of tools that enable animators to perform animation. The animator may use the tools to animate various models. A model is generally a collection of geometric primitives, mathematical representations, and other information that is used to describe the shape and behavior of an object. Each model may comprise controls (or articulated variables or "avars") for which values may be specified that pose the model, i.e., position and orient its collection of geometric primitives. An animation is simply providing, for each avar in the model, a value at each instant in time over which the animation is to occur. The set of values for the avars may be stored, e.g., in a database, and is sometimes referred to as the "cue" or "animation cue".
An animator may select a particular set of controls for the animation based upon the model to be animated, the type of animation to be performed, etc. Accordingly, animators frequently need to switch between different sets of controls "on the fly" in the course of an animation. For example, the animator may switch from using a set of controls that enable the animator to specify animation using forward kinematics to a set of controls that enable the animator to specify animation using inverse kinematics, and vice versa. A switch from one set of controls to another introduces a discontinuity in the animation that may cause irregularities in the resultant animation (e.g., cause an object being animated to "jump" in the animation). Such discontinuities (or jumps) in an object's motion are generally unacceptable in film-quality animation.
As part of the animation, animators also have to frequently enable and disable constraints between two or more objects (represented by models) being animated. Each time a constraint is changed, the interpretation of a model's controls (avars) may change; thus resulting in the same continuity problem as described above for switching control sets.
The following scenarios illustrate the manner in which a discontinuity is introduced when two objects (represented by models) are constrained together during the animation. Assume that a scene is being animated where a Man and a Bus (both represented by models) are moving to the right (i.e., in the positive X direction) at time t1 and the Man is chasing the Bus. Then, at time t2, the Man catches the Bus and is subsequently constrained (parented) to the Bus. The animation can thus be considered as comprising two parts: before the objects (i.e., the Man and the Bus) are constrained, and after the objects are constrained.
FIG. 1A depicts the positions of the objects being animated as a function of time. PosB represents the world space X position of the Bus and PosM represents the world space X position of the Man. FIG. 1B depicts splines representing the X-direction motions of the objects over time. A spline is generally a mathematical function that computes a value at any point in time by interpolating between a sequence of knots, which represent constraints on the function's value at specific points in time. According to an animation technique, animators specify an animation by creating and editing knots. XB represents the input avar (or control) of the Bus model that specifies the Bus's X position with respect to the Bus's parent's coordinate frame. XM represents the input avar (or control) of the Man model that specifies the Man's X position with respect to the Man's parent's coordinate frame. As shown, a constraint between the two objects is made at time t2. With respect to his own reference frame (i.e., XM), the Man moves until time t2, and then ceases his own motion (XM held constant as shown in FIG. 1B) as he is carried by the Bus thereafter. However, as shown in FIG. 1A, this produces a discontinuity in the Man's world space position (PosM) and causes the Man to "jump off" the Bus at precisely the time that the Man catches the Bus, as the Man's reference frame discontinuously changes from the world reference space to the Bus's reference space. The functions that PosM computes change discontinuously due to a change in the reference frame.
Conventionally, animators attempt to solve the discontinuity problem by manually calculating a compensated value for XM that is required to make the Man "stick" to the Bus, and write that value into the animation cue for XM. Let's assume, without loss of generality, that the manually computed compensation value is zero. FIGS. 2A and 2B represent the effect of the computed compensated value on the animation of the Man and Bus. In this scenario, as depicted in FIGS. 2A and 2B, the Man's motion after time t2 is correct (i.e., it is the same as the Bus's motion). However, the Man's pre-t2 motion of chasing the Bus has been subverted by driving the Man's world space position to zero at t2. As a result, before t2, the Man has a motion of approaching the Bus and then moving away from the Bus, and then magically popping to the Bus at time t2 (after t2, PosM is coincident with PosB).
Other conventional techniques attempt to rectify the above-discussed problems by introducing new animation controls (avars) for each of the models being animated. For example, extra avars are added to each model for each control set switch or constraint addition/deletion. Blending functions also have to be defined that allow an animator to blend motion gradually between otherwise discontinuous states. For example, in the previously described scenario, a new animation control XMB (the X position of the Man relative to the Bus) is defined for the Man and a blending function is defined for a blend interval around the time when the discontinuous change is introduced into the animation cue. The blending function is then used to compute the values of XM and XMB to enable smooth animation. However, this approach also has several problems associated with it. Although it reduces the "jump" in the animation, the object being animated (e.g., the Man) still moves over the blend interval, and it is up to the animator to manually minimize the amount of motion. Thus, the animator still has to manually finesse the animation across the constraint. These manual adjustments are generally quite complex and as a result quite time consuming. Further, this approach requires the addition of new controls (avars) to models being animated. This imposes a debilitating intellectual and managerial burden on animators.

Techniques for automatically maintaining continuity across discrete animation changes


A method for creating a semantically aggregated index in an indexer-agnostic index building system includes: extracting documents from a data source, each document including a data object; distributing the documents to a plurality of processing nodes within the system; for each node: indexing the data objects for each document into fields using semantic rules; and grouping indexed data objects for related fields by: classifying the documents into logical groups based on the semantic rules; and creating a searchable index shard for related logical groups.

Index build technologies are generally optimized for even distribution of data across index shards. While conventional distributed indices are powerful, they also disaggregate the semantics of the data itself under an assumption that the data is homogeneous. Under some circumstances, such as in a general text search problem, the assumption that the data is homogeneous is good. In other circumstances, such as when specific data collections are needed, the assumption is not useful. Providing a search engine for a specific data collection may include either creating collection-specific indices or developing complex aggregation and filtering data joiners along with complex queries, while relying on intrinsically-generated, structured metadata.
Search engines or databases that deal with specific data collections often use a searchable index that includes a compilation of documents or other data for the purposes of the particular search engine. The size and content of the search index depends on the purposes of the search engine. For example, a search engine for patents may search repositories of all issued patents and published patent applications for a particular patent system—for example, for the United States Patent and Trademark Office or for the patent office of another country, or both. In order to create the patent search engine, a searchable index including all issued patents and published applications for the particular system can be built. Building large searchable indexes is a time-consuming process and may require a large amount of computer processing power.

This patent is subject to a terminal disclaimer.

Creating a semantically aggregated index in an indexer-agnostic index building system


In a printing system, intermediate data in a rendering-standby state can be rendered before intermediate data of an entire page is accumulated in a printing apparatus. A printer driver of a host computer sequentially converts a plurality of rendered objects of each page generated by an application to rendering commands of each page which can be interpreted by the printing apparatus. Every time a rendered object that should be rendered last in each of a plurality of bands, which are defined by dividing a page by the printing apparatus, is detected, the printer driver converts the rendered object that should be rendered last to a rendering command and notifies the printing apparatus of end information indicating the end of processing of the corresponding band.

1. Field of the Invention
The present invention relates to a printing system for performing rendering by transmitting rendering data in units of pages from a printer driver of a host computer to a printer and by converting the rendering data to intermediate data in units of bands in the printer.
2. Description of the Related Art
In this type of printing system, a printer driver installed in a storage device of a data processing apparatus converts rendering data generated by an application to rendering data which can be interpreted by a printer and transmits the converted rendering data to the printer upon receiving a print request. In this case, the rendering data transmitted from the printer driver to the printer is called PDL (page description language) data, which is described in units of pages.
The printer converts the rendering data of each page into intermediate data in units of bands. After generating intermediate data of one page, the printer renders the intermediate data in order from the top band so as to generate image data, and compresses and holds the image data. After the data of all bands, that is, the data of one page, has been rendered and compressed, the compressed image data is decompressed in synchronization with a printing process, so that print image data is created.
The main reason of rendering and compressing the data in units of bands is that very large sequential memory is required for holding uncompressed image data of an entire page.
In a printer, three processes executed in a printer controller: a process of generating intermediate data; a process of rendering and compressing the data; and a process of decompressing and printing the data, are generally performed in parallel. Accordingly, data of a plurality of pages is accumulated in respective memory areas for the intermediate data and the compressed image data.
When such a system is applied to a general electrophotographic apparatus, such as a laser beam printer (LBP), copying for making copies of each page or reprinting (recovery) after paper jam is performed by using compressed image data, so that the compressed image data is held until the corresponding page has been printed. However, intermediate data is released in units of bands after being rendered (for example, see Japanese Patent Laid-Open No. 10-147017).
Generally, rendered full-color image data is converted to C, M, Y, and K planes, halftone processing is performed thereon in accordance with the tone of the electrophotographic apparatus, and then the image data is compressed. Accordingly, the compression rate of the image data increases, so that the image data can be efficiently decompressed at printing.
A system of starting printing after rendering all bands of a page is suitable for a full-color electrophotographic apparatus of a tandem system including four developing mechanisms for CMYK and a high-speed monochrome electrophotographic apparatus.
In a medium/low-speed monochrome electrophotographic apparatus or a non-tandem full-color electrophotographic apparatus having only one developing mechanism, a method of performing rendering in synchronization with a printing process has been traditionally used.
Japanese Patent Laid-Open No. 2003-216361 discloses another printing system in which a printer driver installed in a host computer spools rendering commands of one page from an application and sorts the rendering commands in units of bands according to the printing start direction of a printer. Accordingly, rendering data is generated not in units of pages but in units of bands, and the rendering data is transmitted to the printer.
In this system, the printer can render a band of rendering data upon receiving it from the host computer. Further, intermediate data of the band is released after being rendered. Therefore, a memory for intermediate data is less likely to be cluttered up and rendering in the printer can be quickly performed compared to a printing system which generates rendering data in units of pages.
However, the printer driver has to generate rendering data in units of bands based on rendering commands which are output from an application in an arbitrary order (irrelevant to the printing order in the printer). Therefore, the following problems arise: rendering commands must be sorted by considering the printing direction in the printer, which takes time; a rendered object which covers a plurality of bands must be divided into segments, so that processing time for generating the rendered object increases; and, if a rendered object cannot be divided into a plurality of bands, rendering data must be generated for each band, so that the amount of data of a print job increases.
For example, assume that a rendering command output from an application is a JPEG image object. In this case, in order to divide the image object by the printer driver in accordance with a plurality of bands, the image object of a JPEG format must be decompressed. Also, the divided image object must be transmitted to a print job and the image object cannot be re-converted to a JPEG format. Therefore, the data size of the print job increases. In a case of a general figure object, the figure object must be converted to a scan object in order to divide it. Therefore, the data size of the print job increases if header specification is performed to each scan object. Since the data size of a scan object is proportional to resolution, this is not suitable for a printing system of high resolution, such as 1200 DPI or 2400 DPI. Further, in a case of a character object, which cannot be divided, characters must be rendered in each band.
In the above-described printing system according to Japanese Patent Laid-Open No. 10-147017, when printing is started after all bands of a page have been rendered by memory deadlock of the printer, the timing of starting a printing operation is late compared to a band rendering method in which rendering is performed in synchronization with printing (first problem).
The capacity of memory for storing intermediate data (intermediate buffer, which will be described later) is limited, whereas the amount of intermediate data forming a page varies depending on the number, type, and size of rendered objects forming rendering data transmitted from the printer driver of a data processing apparatus and on the rendering position.
For example, when the size of intermediate data forming a page is large, a user may have to wait until the bands of previous pages are rendered and the memory for the intermediate data is released.
Further, when the size of intermediate data forming a page is very large, the available memory space for the intermediate data may be insufficient even if all bands of the previous pages have been rendered. In that case, one or more bands of a page for which intermediate data is being generated must be rendered in order to free enough memory for the intermediate data. At this time, if CMYK conversion or half-tone processing is performed on the rendered image data, the image data may not be adequately rendered depending on the rendering logic of rendering data thereafter.
Therefore, rendered image data should be ideally held in a form of an RGB image. However, the RGB image requires a very large memory and thus the image data is typically compressed according to a JPEG standard or the like. Even in a compressed form, the image data requires a large memory compared to a half-tone processed CMYK image. Further, image quality is degraded due to JPEG compression and processing speed decreases (second problem).
When band sorting is performed in order to generate a print job divided into bands in the printer driver of the host computer so that memory deadlock does not occur in the printer, as in Japanese Patent Laid-Open No. 2003-216361, generation of the print job delays due to increased processing load of the printer driver and first printout delays. Further, the amount of print data may increase by dividing data into bands. Therefore, even if band rendering can be performed in the printer, communication loads of a network increase disadvantageously (third problem).

Data processing apparatus, data processing method, printer driver, print control apparatus, print control method, and printing system


A novel symbollogy derived from the lower-case cursive English alphabet (which is compatible with Latin alphabet derived languages), and a multi-step identification program designed to invoke the strengths of the XY Cartesian coordinate mapping system and a specific multi-step identification criteria designed to work in concert so as to allow absolute identification of each symbol. Each symbol is written onto an electronic tablet capable of identifying and distinguishing each individual symbol from a range of possible stroke patterns and then outputting or storing the symbol's assigned English alphabet counterpart. The combination of this symbollogy and recognition program allows high writing speed with the highest possible recognition potential.

Personal computers in the first decade of the 21st century have become ubiquitous, from highly compact laptops, to personal digital assistants (PDAs), to phones with web surfing and data entry capabilities. Text entry on these devices is accomplished in primarily one of three ways: miniaturized keyboards; virtual-keyboards, where a keyboard is shown on a touch screen, and input is done by tapping on the letters; and letter or word recognition, where symbols are individually written on a touch sensitive screen or equivalent surface and then translated to letters in the currently activated text field by a computerized symbol recognition system. The process of writing or data entry through miniaturized and virtual keyboards can be cumbersome, especially for those with large fingers or poor coordination. Text entry via standard or semi-standard letter recognition has met with mixed results with many users finding it frustrating and inaccurate. Symbol recognition systems that use non-standard characters which have little or no stroke relationship to the target alphabet symbol have proved to be unserviceable. What is needed for the 21st century is a universal writing system designed exclusively for use on computers which includes a new symbollogy consisting of a very specific set of simple and definitive stroke patterns. These patterns when strategically arranged become highly serviceable to those familiar with any Latin derived language. Coupled to that symbollogy must be recognition program specifically designed for that particular symbollogy. This character/program integration produces the highest level of recognition that can be achieved for a symbol recognition program. The result is a comfortable, low error, high speed, stationary writing system. The set of stroke patterns under this invention offer the most simple, intuitive, non-classical system of text input which can be devised for Western style electronic writing. Additionally, combining this technology with a spoken letter output program would be very useful to the visually impaired.
Although numerous systems have been devised that attempt to recognize printed or cursive characters, their recognition accuracy is poor. The more recent systems utilize a nine or twelve point grid system wherein the stylus must pass within a minimum distance of a certain number of select points to establish identification. However, poor, or clumsily written characters still elude proper identification. The combining of low-complexity characters which have been designed for ease of identification with a recognition program aimed at accurate distinction of those specific characters will achieve higher accuracy results and offer greater writing speed than a system designed to use and recognize an existing complex script.
The electronic writing system of the future must be accurate and so intuitively familiar enough to the user that it may be written without hesitation as to allow symbol writing at letter note taking speed. Accuracy requires that each symbol be easily computer distinguishable from one another despite poor penmanship or a pre-biased slant of the user's handwriting. Intuitive familiarity requires that one hundred percent of the symbols match the "feel" of the target alphabet so as to speed up the user's initial learning curve but more importantly, to prevent latent brain/hand conflicts from arising at high writing speed once the system has been mastered.
The following system utilizes a symbollogy designed to abbreviate, yet closely approximate, the essence of the writing strokes used in any Latin derived alphabet. The symbollogy is converted to its alphabetic counterpart based on an extremely accurate, multi-step identification process. In the present invention, the symbology was designed around the recognition system's capabilities and limitations so as to invoke the strengths of the XY Cartesian coordinate mapping system and the specific multi-step identification criteria resulting in enhanced identification accuracy. The majority of the prior art encompasses recognition systems that were designed to identify existing alphabetic characters or alphabets that are slight variations thereof, and as such have less accurate positive identification thresholds.
Henceforth, a simple, accurate handwriting recognition system would fulfill a long felt need in the PDA, cell phone and computer industries. This new invention utilizes and combines known and new technologies in a unique and novel configuration to overcome the aforementioned problems and accomplish this.

Handwriting recognition system and methodology for use with a latin derived alphabet universal computer script


Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

The present invention relates to a process for the selective formation of salicide on active areas of MOS devices.
In the field of semiconductor integrated circuits, it is known to use composite materials comprising silicon and a transition metal e.g., Ti, Co and the like, called sulicides, for forming layers having a relatively small resistivity.
In particular, sulicides are formed on active areas of MOS transistors for reducing the resistance of source and drain diffusion regions, when these regions extend significantly.
A known method for forming a silicide layer on the active areas of MOS transistors provides for forming a gate of the transistor, comprising a gate oxide layer and a polysilicon layer, introducing in the silicon a dopant for the formation of the source and drain diffusion regions of the transistors, and then depositing, over the whole surface of the silicon, a transition metal, such as Ti and Co, and performing a thermal process during which the transition metal reacts with the silicon for creating the silicide.
Since the silicide layer which forms on the active area of the MOS transistor is automatically aligned with the gate, the process is called xe2x80x9cself-aligned-salicidationxe2x80x9d, shortly xe2x80x9csalicidationxe2x80x9d, and the layer thus obtained is correspondingly called xe2x80x9csalicidexe2x80x9d.
A drawback in the formation of salicide is due to the consumption of part of the silicon at the interface during the reaction between silicon and the transition metal.
In addition, during the salicidation process part of the dopant in the underlying silicon is absorbed.
For normal MOS transistors these effects are not particularly harmful, thanks to the substantial depth of the source and drain diffusion regions and their high doping level.
However, in some applications such as those providing for forming, by means of the xe2x80x9cDrain-Extensionxe2x80x9d (DE) technique, N- or P-channel MOS transistors for high voltage (HV), the source and drain diffusion regions of the MOS transistors, respectively, comprise a first region, lightly doped and shallow, and a second region, more heavily doped and of greater thickness, connected to the first region. For the fabrication of such transistors, after the formation of the gate a relatively small dose of dopant is introduced in the silicon, respectively of N type for the N-channel transistors and of P-type for the P-channel ones, so as to form said first lightly doped regions of the source and drain diffusion regions which are automatically aligned with the gate. Successively, a high dose of dopant, of N or P type, is selectively implanted by way of a mask covering the gate and extending over the first lightly doped regions.
In order to form salicide over the source and drain diffusion regions of the transistors, a transition metal is then deposited over the whole silicon surface, and there is performed a thermal process.
The salicide thus forms both over the more heavily doped and deeper regions of the source and drain diffusion regions, where as already mentioned it does not causes particular problems, and over the more lightly doped and shallower regions of the source and drain diffusion regions.
In such lightly doped regions, due to their low doping level and their small thickness, the absorption of dopant by the salicide and the consumption of part of the silicon for the formation of salicide can cause problems, for example, the short-circuit of the salicide with the substrate.
An object of the present invention is that of providing a process of formation of salicide over active areas of MOS transistors, particularly of the type formed by means of the xe2x80x9cdrain-Extensionxe2x80x9d technique, allowing one to overcome the above-mentioned problems, in particular avoiding deterioration of existing lightly doped regions of the source and drain diffusions regions.
In an embodiment of the present invention, there is provided a process for forming salicide on active areas of MOS transistors, each comprising a gate and respective source and drain regions comprising each a first lightly doped sub-region near the gate and a second highly doped sub-region spaced apart from the gate, wherein the salicide is formed selectively only over said second highly doped sub-regions of the source and drain regions of the MOS transistors.
The salicide is formed by depositing over the whole surface of a semiconductor wafer a layer of a transition metal, but protecting (masking) those regions of the wafer where the salicide is not to be formed, in particular the first sub-regions of the source and drain regions of the MOS transistors, in such a way as the transition metal is in contact with the silicon over said second sub-regions but not over the first sub-regions. By submitting the wafer to a thermal process, the layer of transition metal reacts to form the salicide only in the regions where it is deposited directly over the silicon (mono- or poly-crystalline) while remaining unmodified in the other regions from which it can be removed.
Advantageously, for depositing the transition metal over said second sub-regions the same mask is used as that used for the selective introduction of the dopant for the formation of the second sub-regions.
These and other features and advantages of the present invention will be made apparent by the following detailed description of embodiments thereof, illustrated as non-limiting examples in the annexed drawings.

Process for the selective formation of salicide on active areas of MOS devices


A switched-mode power supply includes a first rectifier circuit configured to generate a first rectified voltage from an AC input voltage. An inverter generates a second AC voltage from the first rectified voltage. A transformer includes a primary coil coupled to the second AC voltage and a secondary coil. A second rectifier circuit is connected with the secondary coil and generates a second rectified voltage from a third AC voltage present at the secondary coil. The second rectified voltage is coupled to a node of the switched-mode power supply and represents or correlates to an output voltage thereof. A monitoring circuit shuts off the inverter when the second rectified voltage or the output voltage exceeds a predetermined first threshold, indicating an idle condition in the load and increasing energy efficiency.

Known switched-mode power supplies comprise, e.g., the following functional units: a rectifier for rectifying an input AC voltage, a filter circuit for filtering the rectified input AC voltage, a switching unit with a downstream-connected transformer, a further rectifier circuit with a filter circuit and if necessary a regulator mechanism. The regulator mechanism improves the efficiency of the switched-mode power supply by controlling, e.g., the impulse width of the clock signal and by thus adapting the energy intake to the energy consumption using a power factor corrector (PFC). The switching frequency can be relatively high, e.g., between 25 kHz and 500 kHz, or even higher. As a result, the transformer, which provides not only the transformation but also an electrical isolation, can be relatively small and easily implemented. The switching function itself is implemented with, e.g., transistors, more particularly MOSFETs, or thyristors, e.g., using pulse width modulation.

Switched-mode power supply using ac-dc conversion having inverted control


The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation region. A semi-insulating film is formed to cover the surface of a portion of the semiconductor region, which portion is located between the first and second electrodes and in which portion a depletion layer extends when a reverse bias is applied between the first and second electrodes.

The present invention relates to semiconductor devices, and more particularly, field effect transistors, bipolar transistors, diodes and the like that are required to have a high breakdown voltage.
A MESFET (metal-semiconductor field effect transistor) is one of semiconductor devices in which compound semiconductors such as gallium arsenide (GaAs), indium phosphide (InP), and gallium nitride (GaN) are used. A MESFET has a Schottky junction in which a metal gate electrode is formed directly on a semiconductor layer, and the size of a depletion layer formed in the semiconductor layer due to the Schottky junction is made to change according to a voltage applied to the gate electrode, thereby controlling a current flowing through the channel layer.
One type of MESFET is a HEMT (high electron mobility transistor) in which a heterojunction structure is used. HEMTs, which are capable of operating at high speed, are widely applied, e.g., to low-noise amplifiers for receiving satellite broadcasting, switching devices and power devices for cellular telephones, and the like.
In order to use MESFETs, including HEMTs, as switching devices, power devices or the like, it is necessary to increase the gate-drain breakdown voltage thereof, and therefore it is preferable that in the MESFETs the semiconductor layer on which the gate electrode is formed be made of an undoped semiconductor that has a wider bandgap than the channel layer.
FIG. 9 illustrates a cross-sectional structure of a conventional GaAs-MESFET. As shown in FIG. 9, a channel layer 102 made of an n-type semiconductor is formed on a semi-insulating GaAs substrate 101, and an undoped aluminum gallium arsenide (AlGaAs) layer 103 is formed on the channel layer 102. A gate electrode 108 is formed on the AlGaAs layer 103, and a source electrode 106 and a drain electrode 107 are formed with the gate electrode 108 interposed therebetween. The source electrode 106 and the drain electrode 107 are respectively formed on a source region 104 and a drain region 105, which are high carrier concentration regions formed on the GaAs substrate 101. On the surface of the MESFET thus formed, a protective film 109, which is made of an insulating film such as a silicon oxide film (SiO2), is provided.
The protective film 109 is provided to prevent the creation of dangling bonds and oxidation-induced surface states on the semiconductor layer surface. In recent years, a BCN film made of boron, carbon, and nitrogen has also been used as a protective film to reduce the dielectric constant of the protective film (see Japanese Laid-Open Publication No. 2003-115487, for example.)
However, crystal defects or the like, occurring during a crystal growth step or other fabrication process steps, are present on the surface of the undoped AlGaAs layer 103, causing the resistivity of the surface to be nonuniform. In a case where the surface of the undoped AlGaAs layer 103 has a nonuniform resistivity, if a high-voltage reverse bias is applied between the gate electrode 108 and the drain electrode 107, the electric field is locally concentrated in a region due to the nonuniform resistivity. This results in a problem in that the breakdown voltage of the semiconductor device drops significantly below a design value.
Similar problems arise not only in field effect transistors but also hetero-bipolar transistors (HBTs), Schottky diodes and the like.
Such significant decrease in breakdown voltage is likely to occur in semiconductor devices in which compound semiconductors, such as GaAs, InP, and GaN, are used. Since the semiconductor material of a compound semiconductor contains two or more elements, a deviation from the stoichiometric composition is likely to occur on a semiconductor layer surface, such that the resistivity on that semiconductor layer surface easily becomes nonuniform.

Matsushita Electric Industrial Co., Ltd.