Techniques for managing computational load in real-time communications include receiving usage data on a particular node of a packet-switched network. The usage data indicates an amount of computational resources consumed on that particular node by application layer processes for a first type of data packet. It is determined whether this amount exceeds a threshold amount associated with performance degradation. If it is determined that the amount exceeds the threshold, then a message is sent to a different node on the network. The message includes overload state data that indicates the type of data packets and a reduction request. The reduction request indicates a request to reduce an amount of those type data packets that are sent to the particular node in a particular way. These techniques allow application traffic to be diverted under more specific control than approaches that stop all traffic of all data types to the node.

1. Field of the Invention
The present invention relates to relieving processing load at hosts of server processes that provide services for real time communications in a network; and, in particular, to obtaining differentiated relief from different types or sources of requests for services at an overloaded server host, or both.
2. Description of the Related Art
Networks of general-purpose computer systems and other devices connected by external communication links are well known. The networks often include one or more network devices that facilitate the passage of information between the computer systems and devices. A network node is a network device or computer system connected by the communication links. As used herein, an end node is a network node that is configured to originate or terminate communications over the network. In contrast, an intermediate network node facilitates the passage of data between end nodes.
Information is exchanged between network nodes according to one or more of many well known, new or still developing protocols. In this context, a protocol consists of a set of rules defining how the nodes interact with each other based on information sent over the communication links. The protocols are effective at different layers of operation within each node, from generating and receiving physical signals of various types, to selecting a link for transferring those signals, to the format of information indicated by those signals, to identifying which software application executing on a computer system sends or receives the information. The conceptually different layers of protocols for exchanging information over a network are described in the Open Systems Interconnection (OSI) Reference Model. The OSI Reference Model is generally described in more detail in Section 1.1 of the reference book entitled Interconnections Second Edition, by Radia Perlman, published September 1999, which is hereby incorporated by reference as though fully set forth herein.
Communications between nodes on a packet-switched network are typically effected by exchanging discrete packets of data. Each packet typically comprises 1] header information associated with a particular protocol, and 2] payload information that follows the header information and contains information that may be processed independently of that particular protocol. In some protocols, the packet includes 3] trailer information following the payload and indicating the end of the payload information. The header includes information such as the source of the packet, its destination, the length of the payload, and other properties used by the protocol. Often, the data in the payload for the particular protocol includes a header and payload for a different protocol associated with a different, typically higher layer of the OSI Reference Model. The header for a particular protocol typically indicates a type for the next protocol contained in its payload. The higher layer protocol is said to be encapsulated in the lower layer protocol. The headers included in a packet traversing multiple heterogeneous networks, such as the Internet, typically include a physical (layer 1) header, a data-link (layer 2) header, an internetwork (layer 3) header, and some combination of a transport (layer 4) header, a session (layer 5) header, a presentation (layer 6) header and an application (layer 7) header as defined by the Open Systems Interconnection (OSI) Reference Model. In networking parlance, a tunnel for data is simply a protocol that encapsulates that data.
The popularity and good performance of packet switched networks has led to the expanded use of such networks for real-time communications to support such applications as telephony, multimedia conferencing, gaming, and other real-time shared data applications. Such applications involve the setting up of sessions (often termed "calls" in reference to traditional telephony) between two or more users of end nodes, and terminating those sessions when the communications end. To initiate (or "set up"), maintain and terminate (or "tear down") those sessions, one or more intermediate network nodes send signaling data to end nodes and other intermediate nodes.
The Session Initiation Protocol (SIP) is the Internet Engineering Task Force's (IETF's) standard layer 5 protocol for multimedia conferencing over the Internet Protocol (IP), a widely used layer 3 protocol. SIP is a character-based, application-layer control protocol that can be used to establish, maintain, and terminate calls between two or more end points. IETF publishes an adopted standard for Internet technologies as a Request for Comments (RFC), available on the public Internet at the IETF domain ietf in the class org in the directory named rfc. SIP is described in RFC 3261 in that directory in a file named rfc3261.txt, the entire contents of which are hereby incorporated by references as if fully set forth herein. SIP is designed to address the functions of signaling and session management within a packet switched telephony network. Signaling allows call information to be carried across network boundaries. Session management provides the ability to control the attributes of an end node-to-end node call.
SIP provides the capability to determine the location of the target end point—SIP supports address resolution, name mapping, and call redirection; and SIP provides the capability to determine the media capabilities of the target end point—via Session Description Protocol (SDP). SIP determines the "lowest level" of common services between the end points. Conferences are established using only the media capabilities that can be supported by all end points. SIP provides the capability to determine the availability of the target end point. SIP also supports mid-call changes, such as the addition of another end point to the conference or the changing of a media characteristic or codec. SIP supports the transfer of calls from one end point to another and terminates the session between the transferee and the transferring party. At the end of a call, SIP terminates the sessions between all parties. SIP supports setting up conference calls of two or more users, which can be established using multicast or multiple unicast sessions.
SIP-based networks provide many call services, such as call session control, proxies for call session control, user location, interactive voice response (IVR), authentication, encryption, compression, translation, call forwarding and gateways to other networks, among others. Call services also include International Telecommunication Union-Telecommunications Standardization Sector (ITU-T) defined Integrated Services Digital Network (ISDN) Supplementary Services, such as Call Forwarding (CF) Busy, CF-No Answer, CF-Unconditional, Automatic Call Back, Automatic Recall, Call Waiting (CW), Call Transfer, 3-way calling, and Conference Calling, among others. Many of the call services that SIP supports are provided by servers. The client-server model of computer process interaction is widely known and used in commerce.
According to the client-server model, a client process sends a message including a request to a server process, and the server process responds by providing a service. The server process usually returns a message with a response to the client process. Often the client process and server process execute on different devices, called hosts, and communicate via a network using one or more protocols for network communications. The term "server" is conventionally used to refer to the process that provides the service, or the host computer on which the process operates. Similarly, the term "client" is conventionally used to refer to the process that makes the request, or the host computer on which the process operates. As used herein, the terms "client" and "server" refer to the processes, rather than the host computers, unless otherwise clear from the context. In addition, the process performed by a server can be broken up to run as multiple servers on multiple hosts (sometimes called tiers) for reasons that include reliability, scalability, and redundancy.
In a peer-to peer (P2P) model, the two processes are equals and symmetric, that is, either side may play the client or server. SIP uses the P2P model for the end nodes, at least. The combined client/server is called a User Agent (UA). Thus a UA may either initiate or respond to calls. The primary intermediate node called a proxy also plays both client and server roles and acts as a peer to a UA on an end node.
As the number of calls handled by a network increases, the signaling to initiate, maintain and terminate those calls increases. Requests for call services to support those calls also increase at the nodes that host severs for those services. Such nodes tend to aggregate signaling traffic. At some level of use, one or more of the server hosts become so fully loaded with processing requests for services, that they can not accept additional requests. At the point of responding to no more requests, the host and server fails to provide the service to at least some calls. Some such failures can lead to failure of the network, and result in many dissatisfied and even angry subscribers. For example, as a server host fully exerts it computational resources of central processing unit (CPU) cycles and memory to handle existing requests, the number of call completions is observed to decline. Clients that don't get responses back in timely manner will retransmit the request. A proxy can find itself increasing its computational resources for rejecting requests, while decreasing its computational resources for getting real work done, such as completing call setups. A typical progression evolves from using all expended computational resources on completing calls, to using a percent less than 100% to completing calls and the remainder to process retransmissions and rejecting new calls, to using all its computational resources on processing retransmissions and rejecting new calls, to crashing and performing no call processing.
The goal is to optimize the servicing of call service requests ("goodput") rather than optimizing throughput that includes processing retransmissions and rejections. Commercial devices complete 100% of calls at the design capacity, and complete 95% of design capacity even when overloaded at 150% of designed capacity. For example, if a node can handle 100 calls per second (CPS) at design capacity, then as the load rises to 150 offered CPS, the node completes 95 CPS, and rejects 55 CPS. Five percent of its capacity is devoted to rejecting those 55 CPS.
In one approach, a host for a heavily loaded server (at some percentage over its designed 100% completion capacity) is programmed to reject all service requests. While this is suitable for some purposes, it often does not cure the problem. For example, rejecting SIP INVITE messages from calls in progress causes a client node making the request to retransmit the request. The server still expends host resources in dealing with the retransmissions. Furthermore, this approach can cause the host to fail ("crash") as the server starts to spend more central processing unit (CPU) cycles and memory on detecting and rejecting the additional service requests.
In another approach, a heavily loaded server host is programmed to reject service requests for new calls, but to accept requests for calls in progress. While suitable for some circumstances, this approach suffers some disadvantages. A significant disadvantage is that the heavily loaded host must expend computational resources to examine and distinguish a new call setup message (e.g., a SIP INVITE message) from a mid-call modification message (e.g., also a SIP INVITE message). Furthermore, this approach can cause the host to fail ("crash") as the server starts to spend more computational resources on detecting and distinguishing among types of call requests.
In one approach, multiple nodes are included in the network to host the same server, and a heavily loaded host refuses more call requests in the expectation that the other host can absorb the extra work until the host reduces its load. For example a SIP 503 response message with a RETRY AFTER header (field) is sent to a neighboring network node that sends the offending request. This message is a signal to stop sending all further SIP messages (no matter the type of SIP message) to the host until a time indicated by data following the "RETRY AFTER" characters in the RETRY AFTER field. While delaying the onset of system failure, this approach does suffer some deficiencies. For example, if two equivalent hosts are each at 90% capacity, the refusal of all requests by one server might result in all traffic for that service being directed to the other server host. The new traffic quickly fully loads the other server host, and the other host also refuses new requests. This can generate a cascade of failing server hosts and a failure of the system to provide the call service and the premature termination or refusal of many calls on the network. Again, dissatisfied and even angry subscribers are generated.
Another disadvantage of this approach is that some services are hosted by nodes of the network that are connected to a large number of other nodes, such as a provider edge node that aggregates calls from a large number of SIP phones. When one SIP phone sends a request that causes that host to become heavily loaded, the SIP 503 RETRY AFTER message is sent to the one phone. The host is still inundated with traffic from the many remaining SIP phones that are unaware of the load burdening the edge node. Thus the message is ineffective because of the large fan-out of devices generating the traffic. Another SIP 503 RETRY AFTER message must be sent to each new SIP phone making a call.
Based on the foregoing, there is a clear need for techniques to respond to heavy computational load conditions at a call server host, which do not take as many computational resources on the heavily loaded host as prior art approaches.
There is also a clear need for techniques that do not stop all traffic to a server host, which can lead to cascading failures, but can determine a portion of the traffic to delay or divert.
There is also a clear need for techniques that easily notify all network nodes in a fan-out, which are sending traffic that heavily loads the receiving server host, without adding more work to the heavily loaded server host.

Tailored relief for congestion on application servers for real time communications


An adaptor is for electrically connecting with pins of an electrical connector. The adaptor includes an insulating housing, a pair of crimping connectors, and two connecting members. The insulating housing includes two holes. The crimping connectors are accommodated respectively in the holes. Each crimping connector includes a first crimping portion for electrically connecting to one of the pins and a second crimping portion together formed with the first crimping portion. The connecting members are electrically connected with the crimping connectors respectively. Each connecting member includes a first end, a cable, and a second end. The first end is electrically connected with the second crimping portion. The cable is electrically connected with the first end. The second end is electrically connected with the cable, wherein the second end has a through hole. A testing device for testing the electrical connector is also disclosed.

1. Field of the Invention
The present invention generally relates to an adaptor and a testing device for testing electrical connectors.
2. Description of Related Art
Electrical connectors are widely used in various electronic devices, such as computers, optical disk drives, mobile phones, and so on. An electrical connector is a conductive device for connecting electrical circuits together and for allowing electrical signals to pass between the electrical circuits. Therefore, it is necessary to test the electrical connector, in order to assure reliability of the electrical connector.
Printed circuit boards are used for testing electrical connectors in a testing device. Most electrical connectors include an insulating housing and a plurality of pins accommodated in the insulating housing. One end of each pin is electrically connected to the printed circuit board, and the other end of the pin is exposed to the air.
In addition to the printed circuit board, the testing device includes an oscillograph and a pair of leads. One end of each lead is inserted into the oscillograph, while the other end of the lead is used for electrically contacting with the exposed pins of the electrical connector. Usually the other ends of the pair of leads include two probes or two clips. If probes are used, users need to physically hold the probes against the exposed pin to establish an electrical connection. However, when holding the probes against the pins the probes may slide or skid over the pins resulting in erroneous results. If clips are used, each clip is clipped to a pin to establish an electrical connection. However, when clipping two adjacent pins the distance between the pins maybe so small that the clips may touch each other resulting in erroneous results.
Therefore, an adaptor and a testing device are needed in the industry to address the aforementioned deficiencies and inadequacies.

Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd.


Systems and methods for scoring and visualizing the effects of variants in biological sequences. Variants may include substitutions, insertions and deletions. The method comprises encoding biological sequences as vector sequences and then operating a neural network in the forward-propagation mode and possibly in the back-propagation mode to compute variant scores. Variant scores are determined by normalizing the gradients. Variant scores may be used to select a subset of variants, which are then used to produce modified vector sequences which are analyzed by the neural network operating in forward-propagation mode, to determine improved variant scores. The variant scores may be visualized using black and white, greyscale or colored elements that are arranged in blocks with dimensions corresponding to different possible symbols and the length of the sequence. These blocks are aligned with the biological sequence, which is illustrated by a symbol sequence arranged in a line.

Precision medicine, genetic testing, therapeutic development, patient stratification, patient-patient networking and whole genome, exome and gene panel analysis require systems and method that can accurately score and visualize biological sequence variations that are important functionally, such as in causing or contributing to a disease or disorder.
Biological sequence variants, also called variants, impact function by altering molecular phenotypes, which are aspects of biological molecules that participate in biochemical processes and in the development and maintenance of human cells, tissues, and organs.
Most existing methods for genome or DNA sequence analysis are suited to mutations in exons that either change an amino acid in a protein or prevent the production of the protein; to mutations that directly degrade splice sites very close to exon boundaries; or to mutations that are in conserved sequence regions. Most existing methods for protein sequence analysis are suited to mutations that modify binding domains; or to mutations that are in conserved sequence regions.
Over the past decade, the importance of developing methods that are more generally useful in identifying and visualizing genomic variations has been underscored by several observations: Most existing methods narrowly focus on exons, but evolution is estimated to preserve at least 5.5% of the human genome and only 1% accounts for exons within genes; biological complexity relies on regulatory elements encoded in the genome and cannot be accounted for simply by the gene library (e.g., balsam poplar trees have twice as many genes as humans); differences between organisms rely on differences on regulatory elements encoded in the genome and cannot be accounted for by differences between genes alone (e.g., less than 1% of human genes are distinct from those of mice and dogs); increasingly, disease-causing variants have been found outside of exons, indicating that crucial information is encoded outside of those sequences.
These observations have led to explorations into how biological sequence variations cause changes in what are often referred to as molecular phenotypes. Molecular phenotypes correspond to aspects of physical molecules that play roles, such as in human cells, tissues, organs. Examples include the strength of binding between a protein and a DNA sequence; the strength of interaction between two proteins; the fraction of mRNA transcripts in a particular tissue that contain a particular exon; DNA curvature structure; DNA methylation patterns; RNA folding interactions; and inter-cell signalling. Molecular phenotypes can be quantified in a variety of ways, such as by a vector of one or more real-valued numbers, or by a probability distribution.
The systems and methods described herein can be used to score and visualize biological sequence variations using neural networks that relate biological sequences to molecular phenotypes.

Neural network architectures for scoring and visualizing biological sequence variations using molecular phenotype, and systems and methods therefor


This invention relates to an anti-dementia agent which uses a BEC 1 potassium channel inhibitor as the active ingredient.

Potassium channel is a protein which distributes in the plasma membrane of cells and lets potassium ions selectively pass trough it and is considered to be taking an important role in controlling membrane potential of cells. Particularly, this is contributing to the neurotransmission of central and peripheral nerves, pace-making of the heart, contraction of muscles and the like by regulating frequency, persistency and the like of action potential in nerve and muscle cells.
As the classification based on the opening and closing mechanism of the channel, a voltage-dependent potassium channel, an inwardly rectifying potassium channel, a calcium-dependent potassium channel, a receptor coupling type potassium channel and the like have so far been identified. Among them, the voltage-dependent potassium channel has a property to open it when the membrane potential is depolarized. In general, potassium ions are present in a non-equilibrium state of about 5 mM in the extracellular moiety and about 150 mM in the intracellular moiety. Accordingly, when the voltage-dependent potassium channel is opened due to depolarization, potassium ions flow out from the intracellular part into the extracellular part and cause restoration (re-polarization) of membrane potential as a result. Thus, reduction of excitability of nerve and muscle calls is induced accompanied by the opening of the voltage-dependent channel [Non-patent reference 1].
Compounds capable of modifying opening of the voltage-dependent channel have a possibility to regulate various physiological phenomena by regulating excitability of nerve and muscle cells and therefore to become therapeutic drugs of various diseases.
For example, it is known that 4-aminopyridine which is an inhibitor of the A type voltage-dependent potassium channel found in nerve cells causes epilepsy by increasing excitability of nerves [Non-patent reference 3]. In addition, dofetilide which is an inhibitor of HERG potassium channel expressing in the heart, among voltage-dependent potassium channels, is used as an agent for treating arrhythmia based on its property to control excitability of cardiac muscle cells [Non-patent reference 4].
The potassium channel described as SEQ ID NO:2 in Example 1 of U.S. Pat. No. 6,326,168 (corresponding international patent publication pamphlet WO 99/37677) [Patent reference 1] (to be referred to as BEC 1 or BEC 1 potassium channel hereinafter) is a voltage-dependent potassium channel which shows an expression distribution localized to the brain. Its expression is significant particularly in the hippocampus and cerebral cortex. The hippocampus is a region whose relation to memory and learning are strongly suggested [Non-patent reference 5].
Particularly, granule cells of dentate gyrus and CA 1 and CA 3 pyramidal cells wherein BEC 1 potassium channel expresses form a neural circuit, and input of various memories is transmitted from the granule cells of dentate gyrus to the CA 3 pyramidal cell through the CA 1 pyramidal cell, via an excitatory synapse which uses glutamic acid as the neurotransmitter. It is considered that long-term changes in the long-term potentiation, long-term depression and the like synaptic transmission efficiencies found in respective synapses are deeply concerned in the memory and learning. These long-term changes are regulated by the excitation frequency and excitation strength of nerve cells. In addition, the voltage-dependent potassium channel generally has a possibility of being able to control excitability of nerve cells.
Accordingly, it is considered that BEC 1 is concerned in the formation of memory and learning via the excitability control of nerve cells, but this has not been illustratively proved.
A large number of 2,4,6-triamino-1,3,5-triazine derivatives are currently known, and their uses are disclosed as an anti-HIV agent [Non-patent reference 6], an adenosine A 3 antagonist [Patent reference 2], and antimicrobial agents [Non-patent reference 7], [Non-patent reference 8], [Non-patent reference 9] and [Patent reference 3]. Though many potassium channel inhibitors and 2,4,6-triamino-1,3,5-triazine derivatives have so far been reported [Patent reference 3] and [Non-patent reference 10], there are no reports or suggestions stating that they have BEC 1 potassium channel inhibitory action.
The object of the invention is to provide an anti-dementia agent which uses a substance having BEC 1 potassium channel inhibitory action (to be referred to as BEC 1 potassium channel inhibitor hereinafter) as the active ingredient, preferably an anti-dementia agent wherein the BEC 1 potassium channel inhibitor is a 2,4,6-triamino-1,3,5-triazine derivative or a pharmaceutically acceptable salt thereof, a novel 2,4,6-triamino-1,3,5-triazine derivative having BEC 1 potassium channel inhibitory action or a pharmaceutically acceptable salt thereof, and a medicament comprising said novel derivative or a pharmaceutically acceptable salt thereof.
The present inventors have conducted studies with the aim of achieving the above object and found as a result that a BEC 1 potassium channel inhibitor can become an anti-dementia agent. In addition, it was found unexpectedly that a compound having the 2,4,6-triamino-1,3,5-triazine structure has a BEC 1 potassium channel inhibitory action, thus resulting in the accomplishment of the invention.    [Non-Patent Reference 1]            Hille, B. (ed), Ionic Channels of Excitable Membranes (Sinauer Associates, Sunderland, 1992)            [Non-Patent Reference 2]            Catterall, W. A., Chandy, K. G. & Gutman G. A. (eds), The IUPHAR Compendium of Voltage-gated Ion Channels (IUPHAR Media, Leeds, UK, 2002)            [Non-Patent Reference 3]            Yamaguchi, S. and Rogawski, M. A., Epilepsy Res., 11: 9-16 (1992)            [Non-Patent Reference 4]            Gwilt, M., Arrowsmith, J. E., Blackburn, K. J., Burges, R. A., Cross, P. E., Dalrymple, H. W. and Higgins, A. J., J. Pharmacol. Exp. Ther., 256: 318-324 (1991)            [Non-Patent Reference 5]            Levitan, I. B. and Kaczmarek L. K. (1991), The Neuron: Cell and Molecular Biology, Oxford University Press, New York, N.Y.            [Non-Patent Reference 6]            Bioorg. Med. Chem. Lett., (2001) 11, 2229-2234            [Non-Patent Reference 7]            Acta Cienc. Indica. Chem., (1992) 18(4), 405-406            [Non-Patent Reference 8]            Acta Cienc. Indica. Chem., (1985) 11(1), 66-70            [Non-Patent Reference 9]            J. Indian Chemical Society, (1987) 64(12), 770-771            [Non-Patent Reference 10]            J. Inst. Chem. (India), (1987) 59(4), 183-185            [Patent Reference 1]            U.S. Pat. No. 6,326,168            [Patent Reference 2]            JP-A-11-158073            [Patent Reference 3]            International Publication Pamphlet WO 99/1442

Abstract: It was proved that the BEC 1 potassium channel inhibitor has an action to improve learning disorder and is useful as a preventive or therapeutic agent for diseases, preferably dementia, in which the BEC 1 potassium channel is considered to be concerned.

Abstract: Illustratively, it was confirmed by an in vivo test that the BEC 1 potassium channel inhibitor has an action to improve learning disorder.

Abstract: Also, it was found that a compound having 2,4,6-triamino-1,3,5-triazine has a BEC 1 potassium channel inhibitory action.


A refrigerated display case including a case that defines a product display area adapted to support and display food product to be visible from the front of the case. The case includes a canopy positioned above the product display area with at least one display panel. A refrigeration system supplies refrigerated air to the product display area and is adapted to maintain the food product at a desired temperature. A light source supported by the case projects light along a first path of illumination directed toward the product display area adapted to brighten the food product and projects light along a second path of illumination directed toward the display panel. At least a portion of the light along the second path of illumination passes through the display panel to be visible from the front of the display panel.

The present invention relates to refrigerated display cases and, more particularly, to illuminated canopies for refrigerated display cases.
Refrigerated display cases generally include a case defining a product display area for supporting and displaying food products to be visible and accessible through an opening in the front of the case. Refrigerated display cases are generally used in retail food store applications such as grocery or convenience stores or other locations where food product is displayed in a refrigerated condition.
The case includes a top portion, typically referred to as a canopy, located above the opening to the product display area. Some refrigerated display cases include a night curtain that is mounted within the canopy. The night curtain is a thin sheet of flexible material that is adjustable between retracted and lowered positions. In the retracted position, the curtain is rolled within the canopy onto a roll and hidden from view from the front of the refrigerated display case. In the lowered condition, the curtain is unrolled from the roll away from the canopy and toward the bottom of the opening such that the drawn curtain at least partially covers the opening to the product display area. Generally, the curtain is drawn to the lowered position to better isolate the cooled air of the product display area from the ambient air outside of the refrigerated display case. The curtain improves the efficiency of the refrigerated display case while maintaining the food product at the desired temperature when the retail food store is closed (e.g., during nighttime hours), when convenient access to the food products of the product display area is not required.
Most refrigerated display cases include a dedicated first light source that is located below the canopy to illuminate the food products within the product display area. These refrigerated display cases can also include display panels on the front of the canopy. The display panels can be illuminated from behind by a separate, dedicated light source positioned behind the display panels and within the canopy.

Illuminated canopy for a refrigerated display case


A color sheet having a light-shielding effect comprises at least a reflecting layer and a color layer overcoated on the side of the color sheet where the color sheet is exposed to light from the reflecting layer. The reflecting layer a solar-radiation reflectance of 60% or more in a wavelength range of 780 nm to 1350 nm, and the color layer has a light transmittance of 30% or more in a wavelength range of 780 nm to 1350 nm and a solar-radiation absorbance of 10 to 80% in a wavelength range of 380 nm to 780 nm.

1. Field of the Invention
The present invention relates to a color sheet having a light shielding effect, which is applied, as a film material or the like, to the roofs and exterior walls of buildings such as factories, residences, and the like, the roofs and exterior walls of carrying vehicles such as container cars, refrigeration vehicles, the roofs and exterior walls of ships, plants, storehouses, barns, and the like, and the covers and tents of military use and motorcars, whereby the temperature inside the buildings and so forth can be prevented from rising due to radiation of sunlight, and moreover, the designs and appearances can be improved.
2. Description of the Related Art
The roofs and exterior walls of building and structures are exposed to wind and rain and sunlight, and thus, are ready to be deteriorated. Accordingly, to prevent such deterioration of the roofs and exterior walls and improve the appearance thereof, ordinarily, they are protected by painting with coating materials. In recent years, to enhance the working-efficiency, the technique is carried out, in which color films or sheets suitable for their uses are formed in advance, and are set on the roofs and exterior walls. Thus, effects comparable to those of the above-described painting with coating materials can be simply obtained. In particular, buildings such as residences or the like are exposed to sunlight for a relatively long time. It is preferable to arrange the films or sheets, which effectively suppress from temperature rising inside the buildings especially in summer, onto the roofs and exterior walls of the buildings for improvement of the habitability thereof. Thus, the power consumption of air conditioners used for adjustment of the temperature can be reduced, and thus, the air conditioning cost can be reduced. Moreover, the use of the films or sheets is preferable from the viewpoint of global environments.
Moreover, with the recent distribution container trucks and refrigeration trucks for transporting goods in their low temperature state are generally used. To enhance the refrigerating and cooling effect of the container trucks and the refrigeration trucks, it has been desired to arrange films or sheets having a high heat-shielding property. Recently, it has been more required to give different colors to structures, vehicles, facilities and so forth for more aesthetical appearance, in addition to the high heat-shielding property required as described above.
Furthermore, tents are used outdoors as facilities for refuge and rescue at disaster, and are also used when armies and fire brigades are trained or their practical activities are carried out. However, problematically, on sunny days, the temperature inside the tents is increased, which hinders working or the like inside the tents. As countermeasures against this problem, large-scaled air conditioners are installed. However, it is difficult to decrease the temperature inside the tents, especially inside the large-sized tents and thus, the adjustment of the temperature is troublesome.
Techniques by which films or sheets having a heat shielding property are applied have been carried out for a long time. For example, Japanese Patent Application Laid-open No. Hei 8-81567 discloses a sheet containing an aluminum compound or a diimonium type compound in a specific amount based on a plastic resin so that the sheet has a heat shielding property. Japanese Patent Application Laid-open No. Hei 10-250002 discloses a sheet which is applied so as to be pitched outdoors, in which a layer containing inorganic oxide fine particles doped with a metal is formed on one side of a thermoplastic resin film, and furthermore, a layer containing hydrophilic inorganic colloidal particles is formed so that the heat-shielding property is enhanced. Moreover, Japanese Patent Application Laid-open No. 2002-12679 discloses a color film having heat-shielding property which is produced by mixing at least two type of pigments having a heat-shielding property with a thermoplastic resin film, and forming the mixture into a film.
Such sheets or films as disclosed in Japanese Patent Application Laid-open No. Hei 8-81567 and Japanese Patent Application Laid-open No. Hei 10-250002 are translucent and are suitable to be bonded to window glass sheets. However, the sheets or films are problems in that the heat-shielding properties thereof are not sufficiently high and a wide variety of colors can not be given.
Referring to such a sheet as described in Japanese Patent Application Laid-open No. 2002-12679, any optional color can be given to the sheet. However, since the sheet is composed of a single layer, the types of pigments which satisfy both of required colors and heat-shielding properties have a limitation. Thus, still more expensive pigments must be employed. Generally, for formation of thermoplastic resins, the resins are rolled by means of calendaring or are formed into sheets or films by means of extrusion. However, in the case of resins containing glass beads, problems will occur in that the glass beads are broken, so that the heat-shielding effect is decreased, and moreover, the rolls or the like of extruders are damaged, and so forth. Moreover, the films or sheets formed by calendaring or extrusion are oriented in the machining direction. Thus, the sheets or films tend to be curled due to heat which is applied during their processing. Thus, it is difficult to ensure the heat-shielding effect in many cases.
Moreover, the following light-shielding sheet is known in Japanese Patent Publication No. Hei 9-241979 (U.S. Pat. No. 3091685): the sheet comprises a base-fabric, a light-shielding layer and a surface layer, in which the light-shielding layer is laminated onto the base-fabric and is formed with a high polymer composition containing aluminum power paste and a black-color type colorant, and the surface layer is laminated onto the light-shielding layer and is formed with a high polymer composition. This light-shielding sheet, even if the thickness is smaller than that of a conventional light-shielding layer, can exhibit a higher light-shielding property than the conventional light-shielding layer. Moreover, the amount of the black-color type colorant to be added can be decreased. Thus, the light-shielding layer does not become excessively black, so that influences of the light-shielding layer exerted over the color of the surface layer can be reduced. However, it is very difficult to give a variety of colors to the sheet, since a black-color type colorant is used. To give various coloring, the sheet must be further improved.
Referring to a method for applying coating materials having a heat-shielding effect, the coating materials themselves to which functions of heat-shielding and the like are given are expensive compared to generally-used coating materials. Thus, the coating materials are not preferable from the viewpoint of economy. Thus, inexpensive means is desired. Moreover, in a case of applying coating materials having a heat-shielding effect, multi-layer coating is generally repeated to attain a large thickness. Thus, such coating-work takes much time and labor.

Color sheet having light-shielding property


A level converting circuit has a function of converting an input signal of a first logic level into an output signal of a second logic level. The level converting circuit includes a first transistor responsive to an input signal IN for charging an output node to the ground potential, a second transistor responsive to the input signal IN for lowering the potential of the output node to the negative potential VEE, a third transistor responsive to the potential of the output node for controlling operations of the second transistor, and fourth and fifth transistors responsive to a delay signal with delay to an output of the level converting circuit for controlling the amount of current flowing through the output node. An inverted, amplified signal of the output node is applied to the gate of the fourth transistor, and a non-inverted, amplified signal of the output node is applied to the gate of the fifth transistor. The fourth and the fifth transistors serve to enhance the potential change of the output node by the delay signal (amplified signal). As a result, a level converting circuit carrying out a switching operation at a high speed in response to the input signal IN can be implemented.

1. Field of the Invention
The present invention generally relates to level converting circuits for converting a logic level of an input signal to a logic level of a different type, and more particularly, to a level converting circuit used in an interface portion of a semiconductor integrated circuit fabricated with a BiCMOS technology.
2. Description of the Background Art
In order to obtain a semiconductor integrated circuit operable at a high speed with low current consumption, a composite integration technology for integrating a bipolar transistor operating at a high speed and a MOSFET (an insulating gate type field effect transistor) having low current consumption on the same semiconductor chip has been conventionally developed. The composite integration technology is referred to as a BiCMOS technology.
When manufacturing a semiconductor integrated circuit having an ECL (Emitter Coupled Logic) interface by using the BiCMOS technology, a bipolar circuit (a circuit having a bipolar transistor as its component) is used as an input/output circuit for external interfacing, and a CMOS circuit (a circuit having a p channel MOS transistor and an n channel MOS transistor as its components) is used as an internal circuit for carrying out desired function When a semiconductor integrated circuit to be manufactured is a memory device, for example, it includes a circuit such as an address buffer and the like as an input/output circuit, and memory cells and a peripheral circuit such as a decoder and the like as an internal circuit.
An ECL level has its high level and low level normally set to -0.9 V and -1.7 V (or -2.1 V), respectively. A signal at the ECL level can be transmitted at a high speed because the small logic amplitude. Therefore, in a system which requires a high speed operation, the signal at the ECL level is used as a signal transmitted between devices.
A CMOS level has a high level substantially equal to one power supply potential VCC and a low level substantially equal to the other power supply potential VEE. The large logic amplitude therebetween makes it possible to reduce power consumption by reliably setting MOSFET to be non-conductive and cutting off a path through which a current flows. Normally, VCC is set to 0 V, and VEE is set to -4.9 V or -5.2 V. The ECL level and the CMOS level are different in the potential level and the logic amplitude. In order to achieve matching of an external signal and an internal signal, level converting function for converting a signal of one logic level into a signal of the other logic level is required in a semiconductor integrated circuit having the ECL interface.
FIG. 9 is a diagram showing a configuration of a conventional cross coupled type level converting circuit for converting an input signal of the ECL level into a signal of the CMOS level. Referring to FIG. 9, a level converting circuit 204 includes a p channel MOS transistor 202 having the gate for receiving an input signal IN of the ECL level applied to an input node N0, the source connected to a first power supply line 9 for transmitting one power supply potential VCC, and a drain connected to an output node N1, a p channel MOS transistor 200 having the gate for receiving a reference voltage (a reference potential), and the source connected to the input node N0, and cross-coupled n channel MOS transistors 201 and 203 for latching a signal potential appearing at the output node N1.
The n channel MOS transistor 201 has its gate connected to the output node N1, the drain connected to the drain of the transistor 200, and its source connected to a second power supply line 10 for transmitting the other power supply potential VEE. The n channel MOS transistor 203 has its gate connected to the drain of the transistor 201, its drain connected to the output node N1, and its source connected to the other power supply line 10.
A reference voltage REF provides a reference for determining high and low levels of the input signal IN, which is normally set to a potential of -2 V to -3 V.
The sizes of the transistors 201 and 203 are made to be slightly smaller than those of the transistors 200, 202. The transistors 201 and 203 may have appropriate current driving capability so as to change the latch state thereof in response to the potential of the input signal IN. Output load driving capability of the level converting circuit 204 is made to be small. This is because it is necessary to make load capacitance associated with the input node N0 small, thereby changing the input signal IN at a high speed. A driver circuit 205 is connected to the output node N1 of the level converting circuit 204. The driver circuit 205 buffers (or inverts and amplifies) an output signal of an MOS level (or the CMOS level) appearing at the output node N1, generates an output signal OUT, and drives a large load at the next stage. Operations will now be described.
An operation when the input signal IN makes transition from the ECL low level (-1.7 or -2.1 V) to the ECL high level (-0.9 V) will be first described. When the input signal IN is at the ECL low level, the transistor 202 is conductive, and charges the output node N1 to one power supply potential VCC. A CMOS (or MOS) high level signal of the output node N1 is latched by a latch circuit configured by the transistors 201 and 203. At this time, the transistor 201 is conductive, while the transistor 203 is non-conductive. The transistor 200 is brought to be conductive when the difference between the gate potential (reference potential) and the source potential (the input signal IN) becomes smaller than a threshold voltage Vtp. Therefore, in this state, the transistor 200 is brought to be substantially non-conductive. The transistor 201 is conductive since it receives a signal of the CMOS level at its gate, and the potential of the drain of the transistor 201 is brought to be the other power supply potential VEE level.
When the input signal IN rises to the ECL high level in this state, the transistor 202 makes transition to the non-conductive state. The transistor 200 makes transition to the conductive state with rise of the source potential, causing the drain potential of the transistor 200 to rise. As a result, the transistor 203 initiates transition to the conductive state, causing the potential of the output node N1 to drop. Responsively, the transistor 201 initiates transition to a non-conductive state. With the transition to the conductive state of the transistor 203 and the transition to the non-conductive state of the transistor 201, the latch state of the latch circuit configured of the transistors 201 and 203 is inverted, and the potential of the output node N1 attains the other power supply potential VEE level of the CMOS low level.
An operation when the input signal IN falls to the ECL low level will now be described. In this case, the transistor 202 makes transition to the conductive state, and initiates charging of the output node N1. With the potential rise of the output node N1, the transistor 201 initiates transition to the conductive state, and the transistor 200 is substantially non-conductive, and therefore the drain potential of transistor 200 begins to drop by the transistor 201, and then transistor 203 makes transition to the non-conductive state. With respective changes in states of the transistors 201 and 203, the latch state of the latch circuit configured of the transistors 201 and 203 changes. As a result, the potential of the output node N1 attains the CMOS high level of one power supply potential VCC level.
The signal appearing at the output node N1 is buffered by the driver circuit 205 to produce an output signal OUT of the CMOS level, driving a load of the next stage.
FIG. 10 is a diagram showing a configuration of a conventional current mirror type level converting circuit for converting the ECL level into the CMOS level. Referring to FIG. 10, a level converting circuit 214 includes a p channel MOS transistor 212 responsive to the input signal IN applied to the input node N0 for charging the output node N1 to one power supply potential (hereinafter referred to simply as a ground potential) VCC level applied to the first power supply line 9, a p channel MOS transistor 210 receiving the reference voltage REF at its gate for detecting the level of the input signal IN applied to the input node N0, an n channel MOS transistor 211 connected between the drain of the transistor 210 and the second power supply line 10, and an n channel MOS transistor 213 provided between the output node N1 and the second power supply line 10. The transistor 211 has its drain connected to each gate of the transistors 211 and 213.
The transistors 211 and 213 configure a current mirror circuit. Operations will now be described.
Description will first be given of an operation when the input signal IN rises from the ECL low level to the ECL high level. When the input signal IN is at the ECL low level, the transistor 212 is conductive, while the transistor 210 is substantially non-conductive. Since little current flows through the transistors 211 and 213 in this state, the output node N1 is at the CMOS high level of the ground potential VCC. The potential of the output node N1 is transmitted to a circuit of the next stage as the output signal OUT through a driver circuit 215. As a result, a large load of the next stage is driven at a high speed.
When the input signal IN rises from the ECL low level to the ECL high level, the transistor 212 makes transition to the non-conductive state, while the transistor 210 makes transition to the conductive state. As a result, a current flows through the transistor 211, and a mirror current is produced also in the transistor 213 accordingly. The potential of the output node N1 is discharged to a negative potential VEE (the other power supply potential is referred to as a negative potential hereinafter) at a high speed, causing the potential of the output node N1 to attain the CMOS low level.
When the input signal IN falls from the ECL high level to the ECL low level, the transistor 212 begins to be conductive, while the transistor 210 begins to be non-conductive. Since the mirror current by the transistor 213 is not produced, the output node N1 attains the CMOS high level through the transistor 212.
FIG. 11 is a diagram showing a configuration of a conventional complementary data input/output current mirror type level converting circuit for converting the ECL level into the CMOS level. A level converting circuit 300 shown in FIG. 11 includes a level converting circuit 31 responsive to ECL level input signals a, /a complementary to each other for providing a complementary output signal /b of the CMOS level, and a level converting circuit 302 responsive to the input signals a, /a for providing an output signal b of the CMOS level. The output signal /b and the output signal b are signals of the CMOS level complementary to each other.
The level converting circuit 301 includes a p channel MOS transistor 220 responsive to the input signal /a applied to an input node N10 for supplying a current from a ground line 9 to a node N15, a p channel MOS transistor 222 responsive to the input signal a applied to an input node N11 for supplying a current from the ground line 9 to an output node N12, an n channel MOS transistor 221 provided between the node N15 and a negative potential line 10, and an n channel MOS transistor 223 provided between the node N12 and the negative potential line 10.
The transistors 221 and 223 configure a current mirror circuit, and amount of supply current flow thereof is determined by the potential of the node N15.
The level converting circuit 302 having the same configuration as that of the level converting circuit 301 includes a p channel MOS transistor 224 for receiving the signal a applied to the input node N11 at its gate, a p channel MOS transistor 226 for receiving the input signal /a applied to the node N10 at its gate, and n channel MOS transistors 225 and 227 configuring a current mirror circuit. The transistor 224 charges a node N16 from the ground line 9 in response to the input signal a applied to the input node N11, and the transistor 226 charges an output node N13 from the ground line 9 in response to the input signal /a applied to the input node N10.
The complementary output signal /b and the output signal b are provided from the output node N12 and the output node N13, respectively. Operations of the level converting circuits 301 and 302 are similar to that of the level converting circuit 214 shown in FIG. 10, and therefore, operations of only one level converting circuit 301 will be described briefly.
When the input signal a changes to the ECL high level, and the input signal /a changes to the ECL low level, the transistor 222 makes transition to the nonconductive state, and the transistor 220 makes transition to the conductive state. As a result, the node N15 is supplied from the ground line 9 with a current, which in turn flows to the negative potential line 10 through the transistor 221. A current of the same amount as that in the transistor 221 flows through the transistor 223. Since the node N12 is not supplied with a current from the ground line 9, the signal /b provided from the output node N12 attains the CMOS low level of the negative potential VEE level.
When the input signal /a is at the ECL high level, and the input signal a is at the ECL low level, the transistor 220 becomes non-conductive and the transistor 222 becomes conductive. Since a current does not flow through the transistor 221 at this time, the transistor 223 becomes substantially non-conductive, causing no mirror current. As a result, the output node N12 is charged through the transistor 222, and the output signal /b attains the CMOS high level of the ground potential VCC level.
FIG. 12 is a diagram showing a configuration of a conventional complementary data input/output cross coupled type level converting circuit for converting the ECL level into the CMOS level. Referring to FIG. 12, a level converting circuit 310 includes a p channel MOS transistor 230 responsive to the input signal /a of the ECL level applied to an input node N21 for charging an output node N23 to the ground potential VCC, a p channel MOS transistor 233 responsive to the input signal a of the ECL level applied to an input node N22 for charging an output node N24 to the ground potential VCC level, and n channel MOS transistors 231, 232, 234 and 235 activated in response to the input signals /a and a applied to the input nodes N21 and N22 for configuring a cross coupled type latch circuit for latching the potentials of the output nodes N23 and N24.
The n channel MOS transistor 231 has its gate connected to the input node N21, its drain connected to the output node N23 and its source connected to a node N26. The transistor 232 has its gate connected to the output node N24, its drain connected to the node N26, and its source connected to the negative potential line 10. The transistor 234 has its gate connected to the input node N22, its drain connected to the output node N24, and its source connected to a node N25. The transistor 235 has its gate connected to the output node N23, its drain connected to the node N25, and its source connected to the negative potential line 10. Operations will now be described.
Description will be given first of an operation when the input signal a rises from the ECL low level to the ECL high level. When the input signal a is at the ECL low level, the output signals b and /b are at the CMOS low level and the CMOS high level, respectively. In this state, the transistor 235 is non-conductive, and the transistor 232 is conductive, while the transistor 231 is conductive, and the transistor 234 is non-conductive.
When the input signal a rises from the ECL low level to the ECL high level, the transistor 233 makes transition to the non-conductive state, while the transistor 230 makes transition to the conductive state. As a result, the node N23 is charged to the ground line 9 through the transistor 230, causing the potential to increase. The transistor 235 begins to make transition to the conductive state, and the transistor 234 is rendered conductive by the input signal a, causing the potential of the node N24 to decrease. The transistor 231 is non-conductive, and accordingly, the transistor 232 initiates transition to the non-conductive state. As a result, a latch circuit configured of the transistors 231, 232, 234 and 235 carries out a latch operation, causing the potentials of the nodes N23 and N24 to change, and the output signals b and /b attain the CMOS high level and the CMOS low level, respectively.
When the input signal a changes from the ECL high level to the ECL low level, the transistors 233 and 230 are rendered conductive and non-conductive, respectively, while the transistors 231 and 234 make transition to the conductive state and the non-conductive state, respectively. As a result, the potentials of the nodes N23 and N24 begin to change in accordance with transition of the input signal a from the high level to the low level, the change is latched by the latch circuit configured of the transistors 231, 232, 234 and 235, and the output signals b and /b attain the CMOS low level and the CMOS high level, respectively.
As described above, the conventional level converting circuits both of a cross coupled type and a current mirror type carry out charging and discharging of the output nodes at the CMOS level in accordance with input signals of the ECL level, thereby carrying out conversion of a signal of the ECL level into a signal of the CMOS level.
The level converting circuits shown in FIGS. 11 and 12 may be provided at the succeeding stage with a driver circuit or a buffer circuit, which in turn is configured to buffer the complementary output signals b and /b to drive a load of the succeeding stage.
The conventional level converting circuits shown in FIGS. 9 and 10 use the reference voltage (reference potential) for determining the potential level of the input signal. The reference voltage is internally generated or externally applied. The transistor for receiving the reference voltage at its gate is rendered conductive or non-conductive in accordance with the difference between the potential level of the input signal and the reference voltage. Therefore, when the reference voltage varies, the latch circuit (in the case of the cross coupled type level converting circuit) and the current mirror circuit (in the case of the current mirror type level converting circuit) are not able to carry out operations in accordance with the potential level of the input signal, so that output signals corresponding to the input signals cannot be provided.
In the cross coupled type level converting circuit, when the sizes of the transistors configuring the latch circuit become inappropriate in value because of variation of manufacturing process parameters (processing temperature, misalignment of mask and the like), the latch state of the latch circuit does not change in response to the input signal, so that output signals corresponding to the input signals cannot be provided.
When the sizes of the transistors of the latch circuit become somewhat inappropriate in value, even although the latch state can be inverted, the switching speed of the latch state may become slower, hindering a level converting circuit from operating at a high speed.
When the size of the transistor receiving the reference voltage and that of the transistors configuring the latch circuit become inappropriate in value, even if the transistor receiving the reference voltage is rendered conductive/non-conductive in accordance with input signals, the latch state of the latch circuit does not change, hindering implementation of precise level converting function. This goes for a transistor for charging an output node which receives an input signal.
In the case of the current mirror type level converting circuit, although the transistor receiving the reference voltage (reference potential) at its gate is rendered conductive/non-conductive in response to the potential level of the input signal, the transistor is not rendered non-conductive completely even if the input signal is at the ECL low level. In other words, even if the input signal is at the ECL low level, the potential difference between the gate and the source of the transistor is in the vicinity of the threshold voltage. Since one of the transistors configuring the current mirror circuit has the gate and the drain connected to each other and operates as a diode, a current path is formed so that current may flow through the current mirror circuit. Therefore, a problem is caused that the power consumption in the level converting circuit becomes larger.

Level converter with delay circuitry used to increase switching speed


A method identifying a set of transponders situated in the interrogation field of analysis apparatus, with each transponder storing a different identity code. The analysis apparatus first transmits data, and each unidentified transponder compares this data with a portion of its own identity code, which portion is selected by the analysis apparatus, and then transmits in a time window, selected at least as a function of the result of the comparison. The analysis apparatus, then receives the data transmitted by the transponders, determines whether data enables any of the transponders identity codes. The analysis apparatus then emits modified data so that after a finite number of iterations the data causes each of the transponders to transmit data enabling the individual transponder""s identity code to be determined.

The present invention relates to a method enabling a plurality of transponders present simultaneously in the field of analysis apparatus to be identified, and also to analysis apparatus and to a set of transponders for implementing such a method.
Numerous analysis apparatuses are known that enable a transponder to be identified for example to control access to a building.
Most such analysis apparatuses are adapted to identify only a small number of transponders at a time, which is not a problem when controlling access to a building since the number of people, and thus the number of transponders, capable of arriving simultaneously in the field of the analysis apparatus is no more than about ten.
By way of example, mention can be made of European patent application EP 0 285 419 which describes analysis apparatus for requiring a successive interrogations to determine an n-bit identity code.
Such analysis apparatus is unsuitable for the case where the identity code of each transponder is encoded on a large number of bits, e.g. 32 bits, and where a large number of transponders, e.g. more than 50, are present simultaneously in the field of the analysis apparatus.
Unfortunately this situation arises when transponders are used for remote identification of articles present in a container and for providing information concerning their origins, for example.
A particular object of the present invention is to enable a plurality of transponders to be identified in a relatively short length of time, for example to be able to determine how many of them there are, and to be able to address each of them separately to interrogate them.
The invention achieves this by a novel method of identifying a set of transponders situated in the field of analysis apparatus, each transponder having a different identity code in memory, the method being characterized by the fact that it comprises the steps consisting in:
a) causing the analysis apparatus to transmit data for comparison with a portion of the identity code as selected by the analysis apparatus;
b) causing each as-yet unidentified transponder to compare the received data and the portion of its identity code as selected by the analysis apparatus;
c) causing each as-yet unidentified transponder to transmit in at least one time window selected from a set of time windows common to the set of transponders as a function of the result of said comparison; and
d) causing the analysis apparatus to analyze the data transmitted by the transponders in said set of time windows, and when the data transmitted by the transponders does not enable a transponder identity code to be determined at least in part, causing the apparatus to start again with data that has been modified in such a manner that, within a finite number of iterations, the transponders are caused to transmit data enabling the identity code of at least one of the transponders to be determined, at least in part.
In a preferred implementation of the method, each transponder includes a comparison register in which the data for comparison is stored.
This comparison register is preferably organized to store a plurality of binary words, and the identity code is likewise made up of binary words.
In a preferred implementation of the invention, the analysis apparatus modifies, one at a time, a binary word of given significance in the comparison register, and each as-yet unidentified transponder compares the most-recently modified word with the binary word of corresponding significance of the identity code.
The portion of the identity code that is to be subjected to comparison is selected by selecting the significance of each new binary word that is to be stored in the comparison register.
Preferably, the method of the invention further comprises the step consisting in:
causing the analysis apparatus, whenever the data previously received thereby makes this possible to determine at least a portion of the identity code of one or more transponders to send an order causing said transponder(s) to transmit its/their identity code(s); and
analyzing said identity code(s) as received to determine whether only one identity code was transmitted or whether there has been interference associated with a plurality of different codes being transmitted simultaneously, and in the event of only one identity code being received, storing said code.
Results that are particularly satisfying in terms of the time required to identify all of the transponders have been obtained when the identification method comprises the steps consisting in;
a) using the analysis apparatus to transmit data to be compared with a portion of the identity code selected by the analysis apparatus;
b) within each unidentified transponder, comparing the received data and a corresponding portion of the transponder""s identity code;
c) causing each unidentified transponder to transmit in at least one time window selected from a set of time windows common to the set of transponders;
d) using the analysis apparatus to analyze the data transmitted by the transponders in said set of time windows, and when the data transmitted by the transponders does not enable at least part of the identity code of at least one of the transponders to be identified, beginning again with data modified in such a manner that, after a finite number of iterations, the transponders transmit data making it possible to determine at least a part of the identity code of at least one of the transponders:
e) causing the analysis apparatus, when the data previously received thereby makes it possible to determine at least a portion of the identity code of one or more transponders, to transmit an order causing every such transponder to transmit its own identity code; and
f) analyzing reception of the identity code to determine whether a single identity code has been transmitted or whether interference has occurred associated with simultaneous transmission of a plurality of different codes, and when only one identity code is received, storing said code.
Preferably, when a plurality of transponders transmit a plurality of different identity codes simultaneously and they interfere with one another, the method of the invention further includes the step consisting in sending new data to be compared with a new portion of the identity code in said transponders, other than the portion already determined by the analysis apparatus, optionally in modifying said new data until said new identity code portion has been determined, and thereafter in causing the transponder(s) for which the new identity code portion has been determined to transmit its/their identity code(s), and in the event of interference restarting the process for determining the identity code again by causing the comparison to be performed on an as-yet undetermined portion of the identity code, until only one identity code is received from the transponders.
In a preferred implementation of the method of the invention, each identified transponder is put into a standby mode in which it ceases to transmit the result of comparing its own identity code with the data transmitted by the analysis apparatus.
Preferably, each transponder that has been identified is put into said standby mode by using the analysis apparatus to transmit its identity code. The identity code is advantageously transmitted by loading said identity code into the comparison register, with the transponder whose comparison register matches its identity code then putting itself into a standby mode.
The invention also provides a transponder of the type comprising an identification code such as a serial number stored in a memory and means for remote communication with analysis apparatus, the transponder being characterized by the fact that it includes a comparison register in which data from the analysis apparatus can be stored, calculation means for comparing at least a portion of the identity code with at least a portion of the comparison register, and means for transmitting the result of the comparison in at least one time window selected from a set of time windows, the particular time window depending on the result of the comparison.
The invention also provides analysis apparatus for a plurality of transponders having different identity codes, the apparatus being characterized by the fact that it includes processor means organized to determine the identity codes of a plurality of transponders placed in the field of the analysis apparatus, said analysis apparatus being suitable for:
transmitting a write order associated with identity data, said order causing said identity data to be stored in the transponders at a particular address selected by the analysis apparatus;
analyzing the response from as-yet unidentified transponders in a set of time windows after said identity data has been transmitted;
transmitting a read order to cause the transponders whose identity codes have been determined in part to send their identity codes in full;
transmitting a new write order associated with new identity data in the event of interference between the data transmitted by the transponders, so as to end up by causing only one transponder at a time to send its identity code and storing said code; and
repeating the above steps so as to identity all of the transponders in turn.
The invention also provides analysis apparatus and a set of transponders for implementing a method as defined above.
By means of the invention, it is possible to identify a large number of transponders in a relatively short length of time, and to do so even if the identity code of each transponder is encoded on a large number of bits, e.g. 32 bits.

Method of identifying a plurality of transponders, analysis apparatus and a transponder for implementing such a method


A composition of matter comprising at least 15% by weight of the compound: 8-C-.beta.-D-[2'-.omicron.-(E)-cinnamoyl]glycopyranosyl-2-[(S)-2-hydroxyl] propyl-7-methoxy-5-methylchromone. This compound, found in very small amounts in leaves of the Aloe Barbadensis plant, when concentrated to the desired level, exhibits anti-inflammatory activity.

The present invention describes a compound having biological activity which has been isolated from the Aloe barbadensis plant. This heretofore-unreported compound, systematically named 8-C-.beta.-D-[2'-.omicron.-(E)-cinnamoyl]glycopyranosyl-2-[(S)-2-hydroxy]p ropyl-7-methoxy-5-methylchromone; has a molecular weight of 541 Da, and the following chemical structure: ##STR1## This compound exhibits potent anti-inflammatory activity as measured in vivo assays. The compound has also been shown to inhibit EGF-induced DNA synthesis in in vitro testing in epithelial cell lines.
Exudates from aloe plants have been employed for centuries as folk remedies for the treatment of burns, sores and other wounds. In recent years, a great deal of research has been concentrated on identifying aloe components which have clinical activity. Two factors which prompt this interest are aloe's propensity to lose at lease some of its therapeutic properties shortly after harvesting, and the desire to eliminate components which may be harmful--e.g., certain anthraquinones. See, e.g., McAnalley, U.S. Pat. No. 4,966,892. The results of these research efforts suggest that the aloe plant contains several components which have wound-healing properties.
The literature contains a report of a 5-methylchromone C-glucoside which has been identified in Cape Aloe, viz., 2-acetonyl-7-.omicron.-.beta.-D-glucopyranosyl-8-C-.beta.-D-[2'-.omicron.- (E)-p-coumaroyl]glucopyranosyl-5-methyl-chrome. Giovanna Speranza, P. Gramatica, G. Dada, P. Manitto, "Aloeresin C, A Bitter C,.omicron.-Diglucoside from Cape Aloe", Phytochemistry, 1985, 24(7):1571-1573. This prior art compound has a molecular weight of 556.5 Da, the glucosylation group is coumaric acid, not cinnamic acid, and no biological activity is ascribed to the compound.
Other reports of chromones in aloe are found in the literature. "Aloe Revisited--The Structure of Aloeresin A", P. Gramatica, D. Monti, G. Speranza, P. Manitto, Tetrahedron Letters, 1982, 23(23):2423-2424; "Chromones in Aloe Species Part 1. Aloesin--a C-glucosyl-7-hydroxy-chromone", D. K. Holdsworth, PM, 19(4):322-325; "Structure Determination of Polysaccharides in Aloe arborescens var. natalensis", Akira Yagi, H. Nishimura, T. Shida, I. Nishioka, Planta Medica, 1986, 213-218; "Chromones in Aloe Species Part II--Aloesone", D. K. Holdsworth, PM, 22(1):54-58; and "A C-Glucosylated 5-Methylchromone from Kenya Aloe", Giovanna Speranza, G. Dada, L. Lunazzi, P. Gramatica, P. Manitto, Phytochemistry, 1986, 25(9):2219-2222.

Cinnamoyl-C-glycoside chromone isolated from aloe barbadensis


An event stream processing (ESP) model is read that describes computational processes. (A) An event block object is received. (B) A new measurement value, a timestamp value, and a sensor identifier are extracted. (C) An in-memory data store is updated with the new measurement value, the timestamp value, and the sensor identifier. (A) through (C) are repeated until an output update time is reached. When the output update time is reached, data stored in the in-memory data store is processed and updated using data enrichment windows to define enriched data values that are output. The data enrichment windows include a gate window before each window that uses values computed by more than one window. The gate window sends a trigger to a next window when each value of the more than one window has been computed. The enrichment windows are included in the ESP model.

An increasing number of distributed applications process continuously flowing data from geographically distributed sources, perform analytics on the streamed data, and provide analysis results to entities that may also be geographically distributed. The continuously flowing data may be generated from sensor measurements that capture real-time data describing current operating characteristics of a remote device. The sensor measurements may derive from multiple different types of sensors installed at various locations (e.g., brakes, engine, steering mechanism, cooling system, passenger ventilation, power source, etc.) on a currently-moving vehicle, aircraft or watercraft, for example.
Event stream processing (ESP) can be used to analyze and understand millions of events per second, while detecting patterns of interest as they occur in real time. While processing with sub-millisecond response times for high-volume throughput, data streams can be assessed with ESP to derive insights and take appropriate actions.
ESP models are developed to perform the streaming analytics on real-time data streams, for example, as part of the Internet of Things (IoT). The ESP models may clean, transform, aggregate, calculate new variable values from, analyze, predict new variable values from, output, generate an alert on, etc. the received streamed data. Existing ESP analytics platforms provide the architecture to support ESP model generation to solve various analytics problems. Analysts and software developers design and develop the source code to implement the ESP model to solve each analytic problem, which requires significant development and testing time before implementation of the ESP model to solve real-world problems.

Automated streaming data model generation with parallel processing capability


An apparatus including a rechargeable battery pack installed in an electric vehicle, the rechargeable battery pack coupled to a power supply, the power supply operable to provide a charge voltage to perform charging operations on the battery pack, a heating element to heat a fluid to be circulated through the rechargeable battery pack, a comparator circuit to compare a battery voltage of the rechargeable battery pack to a line source voltage, the comparator circuit operable to compare the battery voltage to the line source voltage and to provide an output signal when the battery voltage is less than a line voltage offset value, and a control circuit coupled to receive the output signal of the comparator, and to couple the line source voltage to the power supply, an to bypass the heating element if the comparator is not providing the output signal.

Electric vehicles generally include vehicles that have some device, usually a battery, that stores energy, and that is operable to provide electrical power to one or more systems used, to at least in part, propel or to accelerate the electrical vehicle, or to provide the energy required for some motions of the vehicle. As the stored energy is consumed through either use in the electric vehicle or through some other form of energy dissipation, the source of the stored energy needs to be re-charged in order to replenish the level of stored energy.

Systems, methods, and apparatus for battery charging


The invention relates to an improved process for preparing aminocrotonylamino-substituted quinazoline derivatives of general formula (I)

Quinazoline derivatives of general formula (I) are known from WO 02/50043 and WO 04/074263, which describe compounds with valuable pharmacological properties, including in particular an inhibitory effect on signal transduction mediated by tyrosinekinases and an inhibitory effect on signal transduction mediated by Epidermal Growth Factor-Receptor (EGF-R). Therefore, compounds of this type are suitable for the treatment of diseases, particularly for the treatment of tumoral diseases, diseases of the lungs and airways and diseases of the gastro-intestinal tract and the bile ducts and gall bladder.
WO 2002/50043 discloses a method of production in which aminocrotonylamino-substituted quinazolines (I) are prepared in a one-pot reaction from the corresponding aniline component (II), bromocrotonic acid, oxalyl chloride and a secondary amine (see Diagram 1).
Diagram 1:

The process is not well suited to technical use on an industrial scale, as the yields obtained are at most 50% and as a rule laborious purification by column chromatography is needed. Moreover the educt bromocrotonic acid is not commercially available in large amounts and the corresponding methyl bromocrotonate is only available with a purity of about 80%.
WO 2005/037824 describes an alternative process for preparing aminocrotonylamino-substituted quinazoline derivatives of general formula (I) by Wittig-Horner-Emmons reaction of dialkyl-phosphonoacetamido-substituted quinazolines (III) with a 2-aminoacetaldehyde (IV) (Diagram 2), while instead of the aldehyde (IV) it is possible to use the corresponding hydrate or an acetal (e.g. the diethylacetal corresponding to (IV)), from which the aldehyde is liberated (beforehand or in situ).
Diagram 2:

The educts of formula III may be obtained according to WO 2005/037824 as follows:
Diagram 3:

Both in the prior art described above and within the scope of the invention described hereinafter, the groups Ra, Rb, Rc, Rd, R1 and R2 have the following meanings:
Ra denotes a benzyl, 1-phenylethyl or 3-chloro-4-fluorophenyl group,
Rb denotes a methyl, ethyl, isopropyl, cyclopropyl, 2-methoxyethyl, tetrahydrofuran-3-yl, tetrahydrofuran-2-yl-methyl, tetrahydrofuran-3-yl-methyl, tetrahydropyran-4-yl or tetrahydropyran-4-yl-methyl group,
Rc denotes a methyl, ethyl or 2-methoxyethyl group or
Rb and Rc together with the nitrogen atom to which these groups are bound denote a morpholino or homomorpholino group optionally substituted by one or two C1-3-alkyl groups,
Rd denotes a cyclopropylmethyl, cyclobutyl, cyclopentyl, tetrahydrofuran-3-yl, tetrahydrofuran-2-yl-methyl, tetrahydrofuran-3-yl-methyl, tetrahydropyran-4-yl or tetrahydropyran-4-yl-methyl group, and
R1 and R2 each independently of one another denote a C1-4-alkyl group, for example each denote an ethyl group.
By a homomorpholino group is meant the next highest ring-homologue of the morpholino group, namely the group of formula

Starting from commercially obtainable 4-chloro-anthranilic acid (V), reacting with formamidine acetate (step a) produces the quinazolinone (VI), which is then nitrated using sulphuric acid and concentrated nitric acid (step b). The desired regioisomer (VII) is then chlorinated using thionyl chloride in acetonitrile (step c) and the chlorination product (IX) is reacted in situ with the corresponding amine Ra—NH2 (step d). The compound of formula (X) thus obtained is reacted by base-catalysed nucleophilic substitution with Rd—OH to form the compound (XI) (step e), which is in turn converted by hydrogenation into the corresponding aminoquinazoline (XII) (step f). The aminoquinazoline (XII) is then converted by reaction with a di-(C1-4-alkyl)-phosphonoacetic acid, e.g. with diethylphosphonoacetic acid, in suitable solvents such as tetrahydrofuran (THF), dimethylformamide (DMF) or ethyl acetate, after corresponding activation, for example with 1,1-carbonyldiimidazole, 1,1-carbonylditriazole or propanephosphonic anhydride, into the dialkyl-phosphonoacetamido-substituted quinazoline (III) needed for the Wittig-Horner-Emmons reaction.
The process described in WO 2005/037824 also has a number of serious disadvantages for technical use. For example, the use of thionyl chloride in Step (c) is problematic for safety reasons. The cyclic or heterocyclic alcohols needed to introduce the group Rd in an excess of about 2 equivalents (eq) are starting materials which are difficult to obtain or expensive, and phase transfer catalysis, for example using 18-crown-6, is also needed to react them according to step (e) in Diagram 3 on an industrial scale. The reaction product has to be purified by recrystallisation to eliminate the phase transfer catalyst. The hydrogenation of step (f) is carried out with the addition of acetic acid, if the educt contains a chlorine atom, so as to prevent the formation of dechlorinated by-products which are difficult to strip out. The addition of acetic acid causes traces of the nickel needed as catalyst to be dissolved, and this is then entrained into the final step and gives rise to a heavy metal problem which is unacceptable for pharmaceutical use. Moreover, the throughput of individual partial reactions is in need of improvement; for example the throughput in step (e) according to Diagram 3 is only 1/60 (1 kg of starting material require a reactor volume of 60 l).
In the light of the disadvantages of the known production method as described above, the problem of the present invention is to provide an improved method, suitable for synthesis on an industrial scale, which permits the safe preparation of aminocrotonylamino-substituted quinazoline derivatives (I) using easily obtainable starting materials of high purity and at a lower technical cost.

Process for preparing aminocrotonylamino-substituted quinazoline derivatives

Abstract: wherein the groups Ra, Rb, Rc and Rd have the meanings given in the claims, as well as sulphonyl derivatives of formula

Abstract: and the use thereof as synthesis components for preparing quinazolines of formula (I). The quinazoline derivatives of formula (I) are inhibitors of signal transduction mediated by tyrosinekinases and by the Epidermal Growth Factor-Receptor (EGF-R) and are therefore particularly suitable for the treatment of tumoral diseases.


An artificial neuromuscular unit (ANMU) network comprising: a plurality of ANMUs, wherein each ANMU comprises an electroactive polymer (EAP) actuator layer and a uniquely addressable EAP logic layer coupled to the actuator layer; a plurality of inert, non-ion-conducting and non-charge-conducting interfaces mechanically coupled between the ANMUs such that the actuator layer of each ANMU is insulated from the actuator layers and logic layers of the other ANMUs; an EAP common conductor layer coupled to the logic layer of each ANMU such that the logic layer of each ANMU is interposed between the common conductor layer and the corresponding actuator layer; and wherein the logic layer of each ANMU is configured to control the transfer of energy to and from the common conductor layer and the corresponding actuator layer.

This electroactive polymer-based artificial neuromuscular unit relates generally to the field of structures comprising a plurality of electroactive polymer (EAP) elements. Electrical energy is customarily distributed to individual polymer strands of a given EAP element by electrical conductors. While masses of polymer strands have been bundled together and activated in concert, no adequate method has existed for the coordination and individual control of sequences of polymer strands in structures comprising multiple EAP elements.

Networked structure of electroactive polymer-based artificial neuromuscular units

The United States of America as represented by the Secretary of the Navy


Articles that have an antimicrobial coating containing cyanoethylated hydroxyal-kylcellulose are provided, and their use in fields where preventing microbial contamination is important, such as in the medical field, where it is critical to minimize the spread of microbes that cause infection.

1. Field of the Invention
The present invention relates to articles that have an antimicrobial coating.
2. Description of the Related Art
The ability of bacteria to colonize the surface of plastics, ceramics and metals is a serious problem in modern medicine. Articles implanted in patients, such as drainage tubes, stents, vascular prostheses, dental prostheses, cardiac valves, limb prostheses, contact lenses, artificial lenses and surgical suture materials, are prone to colonization by bacteria. Catheters, in particular, are preferred sites of colonization for bacteria (e.g. D A Goldmann and G B Pier, Clin. Microbiol. Rev. 6, 176192, 1993). When these articles act as a culture medium for antibiotic resistant bacteria, they put a patient at risk for developing an uncontrollable infection. Increasing numbers of antibiotic resistant bacteria have created an urgent need for articles nearly free of bacterial contamination (A G Gristina et al., Biomaterials, 8, 423426, 1987).
Several approaches have already been tried to prevent bacteria from colonizing on the surfaces of medical articles. Silver compounds (e.g. silver nitrate, silver zeolite and silver sulfadiazine) have been used as antibacterial agents in plastic catheters (EP 328 421, JA 03244663, J. Infectious Diseases 167, 920-924, 1992).
There have also been attempts to treat articles with high concentrations of antibiotics in order to prevent bacteria from colonizing on their surfaces. Antibiotics such as gentamycin, rifamycin, and ciprofloxacin have been used (J M Schierholz, Hospitalis 65, 403-407, 1995), as well as antiseptics such as biguanidines, iodine and/or chlorohexidine (G Golomb and A Shpigelman, J. Biomed. Mat. Res., 25, 937-952, 1991). For these compounds to be effective in preventing bacteria growth, they must be present at concentrations of 0.1 to 2% around the article surface. At these concentrations, the antibiotics and antiseptics will damage human tissues and cells. Moreover, when these articles come in contact with bodily fluids, the concentrations of antibiotics and antiseptics around the article surface will quickly drop below the level necessary for preventing bacterial growth. None of these approaches have shown promise in suppressing bacterial colonization on medical devices.
In addition to being susceptible to bacterial contamination, medical devices used as implants can cause dangerous blood clots. The clots are started when blood cells and other blood particles, such as thrombocytes, adhere to the surface of the implanted device. While certain disinfectants (e.g. benzalkonium chloride/heparin) have been shown to reduce the incidence of clotting, they have poor adherence to plastic, ceramic, and metal, and quickly dissolve off the surface of the implanted device.
Tissues can also adhere to an implant device, causing dangerous medical problems. For example, surgical procedures for inserting an intravascular catheter into a patient's blood vessel are complicated by the tendency of the vessel wall to grip the catheter surface. The resulting friction can cause a tear in the delicate inner lining of the vessel wall, and lead to the formation of a potentially deadly thrombus. Accordingly, the development of coatings that adhere to the surfaces of implantable medical devices, but not to blood cells and tissues, is an important goal for making safe implants.
Articles that can remain free from bacterial contamination would be useful in many applications in addition to medical devices. Pharmaceutical research with genetically engineered microbes, for example, requires large amounts of laboratory equipment to be exposed to experimental microbes. Savings in decontamination costs, as well as increased safety, would be realized if the equipment used in this research (e.g. containers, pipelines, bottles, pipettes, etc.) does not promote the growth of the contaminating microbes.
Cost could also be reduced by providing water treatment plants that resist bacterial growth. Presently, it is common for unchecked bacterial growth to clog and corrode waste water treatment plants. Plants that are built with equipment that can resist bacterial growth would last longer and require less maintenance. This equipment includes pipes, pumps, screens, and waste storage containers.
Sanitary conditions could also be enhanced by providing articles resistant to bacterial growth that are used to handle food and beverages. Also, the spreading of communicable disease would be reduced by providing bacterial resistant articles (e.g. seats, telephones, and toilets, doorknobs, handles, latches, etc.) in public places like airports, schools and hospitals.

by Hella Luise Hill, Henning Hinrich Hill, legal representative

Hill, legal representative; by Friedrich Frank

Hill, legal representative; by Regina Luise


An electrical machine may include a comprise a rotor, a stator, a coolant distributor chamber and a coolant collector chamber. The rotor may be rotated about an axis of rotation that defines an axial direction of the electrical machine. The stator may comprise a plurality of stator windings. The coolant collector chamber may be axially arranged at a distance from the coolant distributor chamber. The coolant distributor chamber may communicate fluidically with the coolant collector chamber by way of least one cooling channel through which a coolant can flow. The at least one cooling channel and the at least one stator winding may be embedded in a plastic mass consisting of an electrically insulating plastic for thermal coupling to the coolant.

A machine of the type in question is known, for example, from U.S. Pat. No. 5,214,325. It comprises a housing which surrounds an interior space and which has a casing encircling in a circumferential direction of the housing and radially bounding the interior space, a rear side wall axially bounding the interior space axially on one side and a front side wall axially bounding the interior space axially on the other side. A stator of the machine is fixedly connected to the casing. A rotor of the machine is arranged in the stator, with a rotor shaft of the rotor being mounted rotatably on the front side wall via a front shaft bearing.
The stator of a conventional electrical machine typically comprises stator windings which are electrically energized during the operation of the machine. In the process, heat arises which has to be dissipated in order to avoid overheating and associated damage or even destruction of the stator. For this purpose, it is known from conventional electrical machines to equip said machines with a cooling device for cooling the stator—in particular said stator windings. Such a cooling device comprises one or more cooling channels through which a coolant flows and which are arranged in the vicinity of the stator windings in the stator. Heat can be dissipated from the stator by transmission of heat from the stator windings to the coolant.
It has proven disadvantageous here that efficient transfer of heat from the stator to the coolant flowing through the respective cooling channel is associated only with a considerable structural outlay. However, this has a disadvantageous effect on the production costs of the electrical machine.
It is therefore an object of the present invention to provide an improved embodiment for an electrical machine, in which said disadvantage is substantially or even completely eliminated. In particular, the intention is to provide an improved embodiment for an electrical machine that is distinguished by improved cooling of the stator windings of the stator.