A multilayer optical disk having an information storage layer which can as well as be reproduced by a general purpose reproducing apparatus, for example, a compact disk player, and from which information can be read from other information storage layers by using an exclusive reproducing apparatus. The multilayer disk has a first substrate on which is formed a first information storage layer which is relatively highly reflective with respect to a light beam having a wavelength of 770-830 nm; and a second substrate on which is formed a second information layer which is relatively transparent with respect to a light beam having a first substrate on which is formed a wavelength of 770 mn to 830 nm but which is sufficiently reflective with respect to a light beam having a wavelength of 615-655 nm.

The present invention relates to a multilayer optical disk having a multilayer structure consisting of a plurality of layers for storing information.
In recent years, the popularity of so-called multimedia results in a necessity of handling large-capacity information such as a digital movie data. Therefore, a necessity arises in that large-capacity information of the foregoing type must be stored and randomly accessed so as to be reproduced, if need arises.
An optical disk is a storage medium permitting random access, exhibiting a large capacity and capable of being ejected (i.e., being removable) from a playback or reproducing apparatus. Therefore, optical disks have been used in a variety of fields and large quantities. In order to enlarge the capacity as described above, one side of the optical disk must be capable of handling large-capacity information.
Under the foregoing circumstance, the capacity of the optical disk has been enlarged by providing for a multiplicity of layers for storing information that are laminated in the direction of the thickness of the optical disk.
In such a multilayer optical disk, a multilayer structure is formed on one side thereof and consists of information layers for storing information, wherein the focal points are made so as to be different from one another among the multiple layers so that information is read while maintaining a random access characteristic and, therefore, large-capacity information is handled by a large capacity.
Reported and representative multilayer optical disks will now be described.
1. A concept for reproducing the optical disk by making the positions of the focal points to be different from one another is reported, for example, U.S. Pat. No. 3,946,367.
2. A method using a multilayer disk having an information layer formed by laminating a plurality of layers on one side of the disk so that information is read by means of transmitted light or reflected light is reported, for example, U.S. Pat. No. 4,219,704.
3. A system for reproducing information from a multilayer optical disk, the system comprising an optical system having an aberration correction function (refer to U.S. Pat. No. 5,202,875).
In order to reproduce data in a conventional multilayer optical disk of the foregoing type, an exclusive apparatus for reproducing the data in the optical disk is required. For example, there arises a requirement for a reproducing optical system capable of independently reproducing a reproduction signal from the first information storage layer or the second information storage layer without mixing of data. As an alternative to this, a signal processing system is required which is capable of distinguishing reproduction signals from the first information storage layer and the second information storage layer from each other so as to extract information without confusion.
Therefore, a reproducing apparatus, such as a compact disk player for reproducing a so-called compact disk (CD) which has been used widely as a read-only optical disk, cannot be used as it is.


The present invention is a metered liquid dispenser. A liquid dispenser has a liquid volume metering element located on a base attached to the top of the neck of a liquid dispenser. Using a lift fill mechanism, the metering element is vertically slid relative to the base to dispense a measured liquid volume. One-way valves located in the base and the top of the metering element alternately act to displace air from the element, and then provide suction to draw a measured liquid volume from the liquid dispenser through a dip tube into the element. The liquid is dispensed by inverting the metered liquid dispenser. The metering element has liquid level markings to indicate the liquid volume being entered to the element for dispensing, and is preferable partly transparent to visually display the liquid in the metering element.

1. Field of the Invention
This invention is a metered liquid dispenser. With a liquid volume metering element attached to the top of a liquid dispenser, a lift fill mechanism is used to dispense a measured volume of liquid as indicated by liquid volume markings on the metering element.
2. Information Disclosure Statement
U.S. Pat. No. 2,593,591 to Benjamin David Menkin et al. describes a fluid dispenser which comprises a container, cylinder means removably mounted upon said container and depending thereinto, piston means mounted for reciprocation within and normally projecting yieldably upwardly beyond said cylinder means and including axially spaced abutments, said cylinder and piston means defining a continuous communicating fluid passage therethrough, valve means in said cylinder means and said piston means, the latter means being effective to pump a fluid upwardly from said container through said passage, and an axially ported cup disposed at the upper end of said piston means in a position to receive a flow from said passage: a wall of the cylinder being formed with radial holes in axially spaced relationship, a spring clamp clampable around the cylinder and including an end adapted to be carried in any selected hole for engagement with said abutments to adjust the extent of relative reciprocating movement of the piston means within the cylinder means.
U.S. Pat. No. 2,774,517 to James E. Teegardin et al. describes a fluid dispensing device which comprises a cylinder, an internal projection means in the wall of the cylinder, a resilient piston operatively mounted in the cylinder, a resilient external projection means associated with the piston for limiting its stroke in the cylinder, the resiliency of the piston and the external projection means being adapted for snapping them past the internal projection means into the cylinder, a valve mounted in the wall of the cylinder for valving fluid thereinto, a second valve for valving fluid out of the cylinder, and a spring means for urging the piston through a return stroke.
U.S. Pat. No. 4,757,922 to David J. Landecker describes a dispenser for liquid acrylic resin and powder, the dispenser having a dish, a raised inlet above the dish, and a shield for the inlet. A bottle or the like is mounted in coaxial relation therewith for dispensing fresh quantities of liquid from the reservoir bottle to the dispenser dish. The outlet in the dispenser dish is above the level of the liquid contained in the dish to prevent return of the liquid and has an umbrella-like shield over the inlet to prevent the backflow to prevent contaminated resin from returning to the bottle.
U.S. Pat. No. 4,875,603 to Jack Weinstein describes a metered dispensing cap system for containers such as tubes and the like. The system has a base element which is attachable to the neck of a squeezable container and which has a sidewall portion and a top. The base element has an opening in the top for outflow of a material from a squeezeable container into a meter element. This base element may be removably attachable, e.g. by being screwed on, or may be permanently attached, e.g. by being integrally molded with the container. A one way valve is located in the opening of the base element to permit the flow of material from a container through the opening while preventing backflow. The system also includes a meter element which acts like an inverted trap and which has a sidewall portion and a top with an opening in the top for dispensing of the material therefrom. The sidewall portion of the meter element is slightly larger than and has the same across section shape as the sidewall portion of the base element and this sidewall portion of the meter element is higher than and located about and encompasses the sidewall portion of the base element. Further, the meter element is vertically slidable along the sidewall portion of the base element with an upward position for receiving a volume of material in a predetermined amount when the squeezeable container is squeezed and downward position whereby the opening in the top of the meter element allows for dispensing of the desired amount of fluid when the meter element is pushed down.
U.S. Pat. No. 4,941,598 to Lawrence E. Lambelet, Jr. et al. describes an apparatus for dispensing predetermined amounts of viscous product. The apparatus has a conduit which is telescopically received with a cap. The cap and conduit define an expandable dosing chamber which expands to a predetermined maximum volume when product is introduced into the chamber through the conduit. A check valve prevents back flow of product through the conduit. Collapsing the chamber from its maximum volume to a minimum volume dispenses the product from the dosing chamber.
U.S. Pat. No. 5,014,881 to Raimund Andris describes how in order to create a metering and spray pump of high functional reliability, consisting of as few individual parts as possible and able to be produced with as low production costs, in particular assembly costs, as possible, in which the pumping member consists of an elastically-flexible bellows, which is arranged connectively between mutually movable, dimensionally stable housing parts, the bellows has at its one end, as axial extension, a radially flexible, sleeve-like annular wall section, which encloses in sealing manner like a valve the circumferential surface of a socket, in the form of a ring or pot, integrally molded onto the housing part executing the pumping strokes. The other end of the bellows is provided with an end wall section which has at least one passage opening and covers like a valve one or more outlet openings of a housing end wall of the second housing part or forms the valve seat for a valve closing member which is molded onto a displacement body arranged in the bellows.
U.S. Pat. No. 5,127,553 to Jack Weinstein describes a present invention which is a liquid metered dispensing container of the squeezable type. The squeezable container has an opening for dispensing liquid therefrom at one end and a bottom at the other end. A non-flexible trap chamber is connected to the opening and extends outwardly therefrom. The trap chamber has a lower end inserted into the container opening and has an inlet orifice extending from the lower end into the container. The inlet orifice is adapted to receive a dip tube which is attached thereto and extends close to or at the bottom of the container. The trap chamber has an upper end with a dispensing orifice. This is small enough to prevent dripping of liquid therefrom by gravity when the bottle is inverted but is large enough to dispense liquid therefrom when the bottle itself is squeezed. A one way valve is connected to the lower end of the trap chamber which permits liquid to flow from the container to the trap chamber but not vice versa. The trap chamber may have indicia so that exact dosage levels of different amounts may be squeezed into the chamber, or the chamber itself may have a single, predetermined volume.
U.S. Pat. No. 5,330,081 to Robert A. Davenport describes a portion measuring device of the type having a first, flexible reservoir having an inlet, and a second, portion measuring, reservoir in fluid communication with said first reservoir. The first, flexible, reservoir is of a larger volume than that heretofore known, and may have a handle to aid in holding. The second, portion measuring, reservoir has a rotatable closure with a pouring spout or opening therein. A configured periphery is provided on the closure to aid in turning the same.
Notwithstanding the prior art, the present invention is neither taught nor rendered obvious thereby.

Metered liquid dispenser with lift fill mechanism


A video recording system for vehicles including a video recorder having an electronic record control input port and a video signal input port; a four-to-one video multiplexer having four multiplexer video signal input ports and one multiplexer video signal output port, the multiplexer video signal output port being in transmitting connection with the video signal input port of the video recorder; an activation switch in electrical connection with the electronic record control input port of the video recorder; and a rear view mirror/camera assembly having four video cameras each with a wide angle fish-eye lens and a camera video signal output port in transmitting connection with one of the four multiplexer video signal input ports, one fish-eye lens being aimed toward the front of the vehicle, one fish-eye lens being aimed at the rear of the vehicle, one fish-eye lens being aimed at the driver seat portion of the passenger compartment, and one fish-eye lens being aimed at the front passenger seat portion of the passenger compartment, the four-to-one video multiplexer switching the camera video signals received at its four multiplexer video signal input ports sequentially to the multiplexer video signal output port in response to an activation signal from the activation switch to the video recorder control input port.

Each year incidents occur in and around vehicles, such as accidents and traffic stops, that could be advantageously recorded for later viewing and analyzation. In addition, when a vehicle is broken into, it would be a great benefit to law enforcement personnel to have a video recording of the perpetrator breaking into the vehicle and stealing items from within the passenger compartment. It would be a benefit, therefore, to have a video recording system for recording events in and around a vehicle. Because it could be undesirable to have the video recording system on continuously, it would be a further benefit to have such a video recording system that could be a manually activated when desired by a user within the passenger compartment of the vehicle. Because the vehicle must often be left unattended, it would be further desirable to have such a video recording system that included an activation mechanism in a connection with an alarm output relay of an existing car alarm that would activate the recording system whenever the vehicle alarm system went off. Because one camera cannot adequately view all of the areas in and around the vehicle, it would also be an advantage to have such a video recording system that included multiple cameras.

Multi-camera video recording system for vehicles


The stack type package module includes a plurality of stacked tape carrier packages. Each package has an elongated lead having an extension end connected to the first lateral end connected to a central portion connected to a second lateral end. The second lateral end is connected to the respective chip via a bump. The packages made as such are then stacked on top of each other on a printed circuit board. The plurality of the stacked first lateral ends are then cut and soldered the printed circuit board. The predetermined portions of the packages including the cut first lateral ends are sealed for protection.

1. Field of the invention
The present invention relates generally to a stack type package module and a method for manufacturing the same. More particularly, the present invention relates to a stack type package module using a tape carrier and a method for manufacturing the same.
2. Description of the Prior Art
Recently, there exist various demands for further improving the semiconductor technologies, such as in the areas of lightness, compactness, multi-functions, high-performance, and low fabrication costs. In order to satisfy the above demands, semiconductor package technologies have been suggested. Among many semiconductor package technologies, a ball grid array (BGA) package technology capable of fabricating a BGA package in a size similar to the size of a semiconductor chip is currently being spotlighted.
According to the conventional BGA package, as shown in FIG. 1, a chip 20 is mounted on an upper surface of an array substrate 10, and mold resin 30 is molded thereon. In addition, solder balls 40 are aligned at the bottom surface of the array substrate 10 in such a manner that the array substrate 10 can be connected to a printed circuit board 50 through the solder balls 40.
However, in the solder joints, which are one of the most important elements for determining reliability of the BGA package, of the conventional BGA package described above, a crack may appear in the solder balls 40 interposed between the package 10, 20, 30 and the printed circuit board 50 for the majority of the temperature cycle (TC).
There are various reasons for the solder balls cracking. One reason is a differential heat expansion coefficient between mutually different materials. That is, fatigue accumulates in the solder balls due to the differential heat expansion coefficient between the package 10, 20, 30 and the printed circuit board 50, resulting in the cracking of the solder balls 40.
The crack created in the solder balls may degrade the reliability of the semiconductor package.

Stack type package module and method for manufacturing the same


An aligner device includes a robot hand, a lifting mechanism, sensors, a misalignment calculating unit, an x-y misalignment correcting unit, and a θ misalignment correcting unit. The robot hand includes vertically aligned hand members each configured to hold a planar workpiece. The lifting mechanism moves planar workpieces transported by the robot hand up from and down to the hand members, respectively. Each of the sensors, vertically spaced apart from each other, has a downward sensor surface to capture the outline of a planar workpiece brought close to the sensor surface by the workpiece lifting mechanism. The misalignment calculating unit calculates, by using the images of the captured outline shapes of the planar workpieces, an amount of positional misalignment of each planar workpiece with a reference position in X, Y and θ directions. The X-Y misalignment correcting unit corrects the misalignment of each planar workpiece in the X and Y directions based on the amount of X-Y direction misalignment calculated by the misalignment calculating unit. The θ misalignment correcting unit corrects the misalignment of each planar workpiece in the θ direction based on the amount of θ misalignment of the planar workpiece.

In one example, in a semiconductor process, a semiconductor wafer (hereinafter, may be referred to simply as "wafer") is carried into a load lock chamber. The wafer is then transferred by a transfer robot from the load lock chamber to a processing chamber. Depending on the process to be conducted in the processing chamber, the wafer needs to be carried precisely to a reference position in the processing chamber. Conventional solution is to use an aligner device, such as one disclosed in Patent Document 1, before a workpiece is carried into a processing chamber. The aligner device determines an amount of misalignment of a wafer in a planar direction (X-Y direction) and a rotational direction (θ direction). With information about the determine amount of misalignment, a transfer robot can correct the position of the wafer and transfer the wafer to the reference position in the processing chamber.
In an attempt to reduce the time taken to transfer target objects ("transfer takt time") in a semiconductor process, a transfer robot having multiple hands (a multi-hand transfer robot) as disclosed in Patent Document 2 has been proposed. The transfer robot is capable of transferring a plurality of wafers simultaneously, so that the transfer takt time can be reduced. In order to utilize such a multi-hand transfer robot, the load lock chamber and the processing chamber are designed to hold a plurality of wafers at predetermined intervals in the vertical direction.
However, conventional transfer systems using multi-hand transfer robots still have room for improvement. For example, the conventional transfer system described above is not capable of placing wafers precisely at their reference positions although such precise alignment may be required by a process to be conducted in the processing chamber. In addition, the conventional aligner device disclosed in Patent Document 1 is only capable of determining positional misalignment of a single wager. Therefore, combining the aligner of Patent Document 1 with the multi-hand transfer robot of Patent Document 2 will not render it possible to reduce the transfer takt time.
Patent Document 1: JP-A-2015-195328
Patent Document 2: JP-A-2013-135099

Aligner device and method for correcting positional misalignment of workpiece


A synchronizing device includes a pair of longitudinal guiding units each having a rack member and a movement damper connected to the rack member, and a rotating mechanism including a pair of pinion gears to be meshed respectively with the guiding units. When the pinion gears move respectively from the rack members for rotation respectively on the movement dampers, an increased pressure is produced between the guiding units and the rotating mechanism, thereby slowing down and damping the rotation of the rotating mechanism.

1. Field of the Invention
The invention relates to a synchronizing device, and more particularly to a synchronizing device for synchronizing a pair of drawer slide mechanisms.
2. Description of the Related Art
Generally, a pair of slide mechanisms with balls are respectively installed on two sides of a drawer or on a bottom of the drawer. Such slide mechanisms include a pair of inner rails respectively covered by and connected to outer rails for slidingly moving back and forth relative to each other.
Since gaps exist between the inner and outer rails of the slide mechanisms, when the inner rails move relative to the outer rails, the inner rails may be affected by an uneven force acting thereon and may not synchronously move in or out of a cabinet. Therefore, when being loaded, the drawer may wobble and may produce undesired rebound effect.
For improvement, as shown in FIGS. 26 and 27, a synchronizing device 9, as disclosed in Austrian Patent No. 006674U2, is provided for a pair of slide mechanisms 83 disposed between a caddy 81 and a drawer 82, so that the drawer 82 is able to move stably and smoothly back and forth relative to the caddy 81 (the figures illustrate only one of the slide mechanisms). Each of the slide mechanisms 83 has a longitudinal slide rail 831 disposed inside the caddy 81. The synchronizing device 9 includes two guiding racks 91 respectively disposed under the slide rails 831 (only one is shown as an example), two connecting devices 92 (only one is shown) disposed on the drawer 82, and a rotating mechanism 93 rotatably disposed between the two connecting devices 92 and movable along the two guiding racks 91. Since the synchronizing device 9 has symmetrical left and right parts, the figures illustrate only one symmetrical part of the synchronizing device 9 for the sake of brevity.
Each guiding rack 91 includes rack teeth 911 disposed on the corresponding slide rail 831, and a longitudinal ledge bar 912 extending parallel to the rack teeth 911 in proximity to the drawer 82. Each connecting device 92 includes a mounting plate 921 disposed on a rear side of the drawer 82, a bearing seat 922 disposed on the mounting plate 921 and movable upward and downward, and an abutting plate 923 extending from the bearing seat 922 and projecting toward the ledge bar 912 for abutting against a bottom of the ledge bar 912. The rotating mechanism 93 includes two shafts 931 respectively and rotatably disposed in the corresponding bearing seats 922, a tubular spindle 932 interconnecting and synchronizing the two shafts 931, and two pinion gears 933 respectively fixed to the shafts 931 and movably meshed with the rack teeth 911 of the guiding racks 91.
When the drawer 82 is pulled, the rotating mechanism 93 is driven for concomitantly moving along with the drawer 82. Each pinion gear 933 is meshed with and moves on the corresponding rack teeth 911. The abutting plate 923 is movable upward and downward together with the bearing seat 922, and supports a bottom of the ledge bar 912 to prevent the pinion gear 933 from disengaging from the rack teeth 911 when the drawer 82 swerves due to an external force. The pinion gear 933 is able to move on the guiding rack 91. If the slide mechanism 83 is obliquely assembled with respect to the guiding rack 91, the pinion gear 933 can still move on the rack teeth 911 without affecting the movement of the drawer 82 because of the use of a particular design of the bearing seat 922 for moving upward and downward relative to the mounting plate 921.
However, the conventional synchronizing device 9 is not able to decelerate the movement of the drawer 82 in either fully open or close states. Since the synchronizing device 9 does not have any damping structure for slowing down the speed of the drawer 82 relative to the caddy 1, such deficiency may result in collision of storage items in the drawer 82 during the final process of the fully open/close operation of the drawer 82. Besides, when the shaft 931 is forced to reduce speed and stop, abrasion wear and abrupt movement of the shaft 931 may occur, or undesirable continuous impact noise may be produced due to the rotation of the non-circular configuration of the shaft 931.

Synchronizing device for a drawer slide mechanism


This disclosure relates to the surprising and unexpected finding that the well-known cancer protein, Myeloid Cell Leukemia-1 (MCL-1), binds to and modulates the enzymatic activity of Very Long Chain Acyl CoA Dehydrogenase (VLCAD), thereby regulating fatty acid β-oxidation. This finding is employed in compositions and methods of treating cancer, metabolic diseases, or other conditions characterized by excessive fatty acid β-oxidation by blocking or reducing the energy production of cells (e.g., cancer) through inhibiting the MCL-1/VLCAD interaction and/or directly inhibiting VLCAD enzymatic activity. In addition, the disclosure features methods for identifying such agents that inhibit the interaction between MCL-1 and VLCAD or that inhibit VLCAD enzymatic activity.

Mitochondrial apoptosis is essential to normal development and tissue homeostasis. BCL-2 family proteins regulate this process through heterodimeric and homo-oligomeric protein interactions, which ultimately dictate whether a cell will live or die. Engagement of multidomain pro-apoptotic members BAX and BAK by select BH3-only proteins, such as BID, BIM, and PUMA, conformationally activates BAX and BAK, transforming them from monomeric proteins into oligomeric pores that pierce the mitochondrial outer membrane, resulting in apoptosis induction (see, e.g., Walensky and Gavathiotis, Trends Biochem Sci., 36(12):642-52 (2011)). Anti-apoptotic proteins, such as BCL-XL and MCL-1, bind and block BH3-only and multidomain pro-apoptotic members to prevent mitochondrial apoptosis.
Cancer cells overexpress BCL-2 family anti-apoptotic proteins to exploit this mechanism and enforce cellular immortality. Myeloid Cell Leukemia-1 (MCL-1), an anti-apoptotic BCL-2 family survival protein, has been implicated in the development, maintenance, and chemoresistance of a broad range of cancers and is one of the top ten most widely expressed pathologic factors in human cancers (see, e.g., Beroukhim, Nature, 463(7283):899-905 (2010)). Highly overexpressed in human cancers, MCL-1 mounts formidable apoptotic resistance by binding and sequestering the essential BH3 domain helices of pro-apoptotic BCL-2 family members. Underscoring the physiologic importance of MCL-1, mouse models of MCL-1 deletion have revealed severe consequences, including embryonic lethality, hematopoietic stem cell loss, cardiomyopathy, mitochondrial dysfunction, and more (see, e.g., Rinkenberger, Genes Dev., 14(1):23-27 (2000), Malone, Mol Cell Neurosci., 49(4):439-47 (2012), Opferman, Science, 307(5712):1101-4 (2005), Opferman, Nature, 426(6967):671-6 (2003), Wang, Genes Dev. 2013). Ironically, the MCL-1 BH3 domain is itself the most potent and selective natural inhibitor of MCL-1's anti-apoptotic function (see, e.g., Stewart, Nat Chem Biol., 6(6):595-601(2010)).
Fatty acid metabolism is a distinct process that, like mitochondrial apoptosis, is also essential to normal development and tissue homeostasis. To support the energetic needs of tissues, both normal and oncologic fatty acids that enter the cell undergo mitochondrial (3-oxidation (FIG. 35). Fatty acids are first charged by acyl-CoA synthetase long-chain family member 1 (ACSL1) to generate the corresponding acyl-CoA species. Because long chain acyl-CoAs cannot reach the mitochondrial matrix by passive diffusion, they are first converted to acylcarnitines and then transported via the carnitine-acylcarnitine translocase (CACT). Once in the mitochondrial matrix, acylcarnitines are converted back to acyl-CoAs by carnitine palmitoyltransferase 2 (CPT2), enabling entry into the β-oxidation pathway. The critically important enzyme Very Long Chain Acyl CoA Dehydrogenase (VLCAD) catalyzes the first of four steps in a process that mobilizes fatty acids to produce cellular fuel/energy by reducing the length of long-chain acyl-CoAs by two carbons, sequentially releasing acetyl-CoA. VLCAD deficiency in humans can cause an early-onset severe condition characterized by life-threatening cardiomyopathy and a later-onset disease that manifests as repeated episodes of hypoglycemia.

Compositions, assays, and methods for direct modulation of fatty acid metabolism


A system and method is described which provides for electrical signal transmission and a secure mechanical attachment in a flexible circuit assembly. The inventive mechanism combines the electrical features of discrete wiring with the mechanical features of etched pads connected to plated vias on flex circuits in order to achieve robustness in both the mechanical and electrical properties. A discrete wire is preferably securely bonded to a conductive pad which pad is then securely attached to a plated via. In this manner, the sequence of connections is made mechanically secure by either ultrasonically bonding or welding the discrete wire to the pad and employing the traditionally robust connection between the pad and the via. The arrangement achieves high quality electrical signal transmission by employing discrete wiring for signal transmission along any path of significant length.

This invention relates in general to electrical systems and in particular to reliable multiple path flexible circuit connections.
In many industrial systems, such as computer and telecommunications systems, there is a need for making a large number of electrical interconnections between a plurality of points of interest. It is generally desirable to achieve reliable connections (i.e. with low connection failure rates), with good electrical properties, and to be able to dispose such connections within a small area to address space limitations. Various prior art approaches have been attempted which experience limitations in one or more of the above-mentioned characteristics.
One prior art approach is that of Printed Wire Board (PWB) flex circuits. PWB flex circuits are generally easy to manufacture if they have wide lines and traces. However, such circuits are generally difficult to manufacture in volume when fine lines, high density, and/or tight impedance controls are required. Moreover, if tight impedance controls are required, yield losses are generally high in volume production due primarily to variations in the etch processes.
FIG. 1 is a section view of a strip line flex circuit 100 for high speed high density applications according to a prior art solution. Conductive traces 102 are shown with a dashed line. Ground planes 101 and 103 are shown running parallel to traces 102.
FIG. 2 is a top view of a center line cross section of the strip line flex circuit depicted in FIG. 1. A number 200 of parallel traces 201 may be seen in the top view of FIG. 2. Generally, the width of and spacing between traces 201 may be important features in determining electrical properties of the structure such as characteristic impedance, resistance, skin effect losses, and crosstalk between the traces.
FIG. 3 depicts sectional views 300 of four possible conductive trace geometries. The three columns separated by ideal spaces 306 are generally equivalent. Accordingly, the four trace geometries depicted in the rightmost column 301 will be discussed herein. Trace 302 generally represents an ideal trace geometry, which although highly desirable, is very difficult to achieve in a typical etch process. Trace 303 generally represents a desirable trace geometry which may be achieved with careful process control and with some yield loss. Trace 304 depicts a trace from which an excessive amount of conductive material, such as copper, has been removed. Trace 304 will generally experience excessive direct current (d.c.) resistance, increased skin effect losses, and undesirably high characteristic impedance. Element 305 depicts an under-etched trace. Such an under-etched trace will generally have excessive crosstalk and lower than ideal characteristic impedance.
High speed data cables have been employed to provide interconnection having superior electrical signal characteristics. However, the use of such cabling is generally more expensive to implement for transmission of a given set of signals than is printed wire board flex circuit. Moreover, connectors used to connect such data cables to a board generally provide lower signal density than do flex circuits. Furthermore, such cable connectors are commonly the cause of impedance mismatches, crosstalk, and skew.
In certain cases, multiple rigid PCBs (printed circuit boards) are used to establish electrical connections to system or subsystem units which are not on the same plane. As a result, multiple connectors may be introduced into the signal path, the addition of which generally degrades the quality of signal transmission. In addition, implementing a plurality of rigid PCBs generally adds to system cost, and takes up additional space.
FIG. 4A is a section view 400 of a via connected to a wire according to a prior art multiwire connection arrangement. Employing this arrangement, via 401 is generally formed onto the end of wire 402. Wire 402 may be coated with TEFLON(copyright) (polytetrafluoroethylene) for insulation purposes. In a connection employing the arrangement depicted in FIG. 4A, the available area for establishing a connection between wire 402 and via 401 is generally limited to the cross-sectional area of wire 402. Some additional contact area may become available where the polytetrafluoroethylene coating is etched back for a finite distance along wire 402 from the outside diameter of via 401. FIG. 4B is a top view of the same connection.
Although the embodiment depicted in FIGS. 4A and 4B generally provides the superior electrical properties of discrete wiring, the attachment of wire 402 to via 401 provides a weak mechanical connection between wire 402 and via 401 which is subject to failure if wire 402 is pulled or moved in any direction.
FIG. 5A is a section view 500 of a via 501 connected to a trace 502 in a printed circuit board arrangement. Employing this arrangement, a hole is drilled in a conductive pad connected to trace 502, and plating material added to create via 501. FIG. 5B is a top view of the connection depicted in FIG. 5A. This connection generally provides for a 360 degree connection between plating on via 501 and the copper of trace 502. This trace-via connection offers a more robust mechanical connection than the connection between the discrete wire and via depicted in FIG. 4. However, the trace-via connection of FIG. 5 is subject to the inconsistency in dimensional tolerance and electrical properties discussed in connection with FIG. 3.
FIG. 6 is a section view of a rigid circuit employing discrete wiring 602 between stripline shield layers 601 according to a prior art embodiment. FIG. 7 is a top view 700 of a center line cross section of wires 602 depicted in FIG. 6. Returning to FIG. 6, generally, the cross sectional area between stripline shield layers 601 is filled with rigid dielectric material 603, such as FR4 or G-Tec. The rigid circuit embodiment of FIG. 6 benefits from the advantageous electrical performance properties of discrete wiring. However, the embodiment employs the mechanically vulnerable wire to via connection discussed in connection with FIG. 4A.
Accordingly, it is a problem in the art that PWB flex circuits are difficult to manufacture in high volume and experience and high yield losses due to etch variations.
It is a further problem in the art that it is difficult to generate consistent trace geometries, resulting in inconsistent electrical properties for conductive traces.
It is a still further problem in the art that cables are generally more expensive to implement than flex circuits for the same number of signals.
It is a still further problem in the art that connectors used to attach cables to boards offer lower signal density than PWB flex circuits, and commonly cause impedance mismatches, crosstalk, and skew.
It is a still further problem in the art that the deployment of multiple PCBs cause added cost, take up additional space, and cause degraded performance because of the implementation of multiple connectors along individual signal paths.
It is a still further problem in the art that the connection of discrete wires to plated vias generally mechanically weak and subject to failure when the wire is pulled or moved.
The present invention is directed to a system and method which provides consistently high quality electrical performance characteristics in combination with robust mechanical attachment between conductors and electrical junctions. Preferably, discrete wires are connected to conductive pads employing either laser welded or ultrasonically bonded wire joints between the wires and pads. A plurality of layers having conductive pads may be combined to form a multiple layer flex circuit. Holes may then be drilled through the conductive pads in the traditional manner and then plated to create vias.
Preferably, electrically reliable discrete wires may be employed and still benefit from the mechanically robust connection created by the attachment of the pad to the via. Therefore, there is a generally a two stage connection which includes a connection between a wire, or other high performance conductor, to a conductive pad, and then a robust connection between the conductive pad and the via. A robust connection between the high quality conductor and the conductive pad may be formed by a number of mechanisms including but not limited to: laser welding and ultrasonic bonding. In this manner, a mechanically flexible circuit is provided which enjoys the high quality electrical performance of discrete wiring conduction and robust mechanical attachments between the wire, pad, and via, thereby enabling the circuit to be flexed at will without causing electrical connection failure.
In a preferred embodiment, a wire may be placed in contact with a conductive pad and then be ultrasonically bonded or welded thereto. Thereafter, a hole may be drilled in the conductive pad, and optionally, through a plurality of other layers in a flex circuit. The drilled hole may then be plated, thereby enabling the plating material to form a solid conductive and mechanical connection to the conductive pad. In this manner, the resulting connections are mechanically robust and benefit from the superior electrical properties of discrete wiring.
In a preferred embodiment, the system and method described above allow the creation of a high speed flexible circuit that combines high speed signal handling ability with robust mechanical connections. Since the bulk of the distance traveled by the signals is covered by a high quality conductor, such as, for instance, drawn wire, rather than etched trace, the conductor surface is preferably smooth, thereby enabling low loss skin effect parameters to be realized.
In a preferred embodiment, the wires may be individually formed, thereby enabling such wires to avoid the electrical performance problems associated with under-etch and over-etch to be avoided. Preferably, the wire to pad connection, which may be accomplished by welding or ultrasonic bonding, allows robust signal vias to be created employing standard drill and plating processes. Preferably, tighter impedance, resistance, and skin effect loss parameters may be realized employing a process which allows consistent manufacturing of a large number of circuits.
Therefore, it is an advantage of a preferred embodiment of the present invention that electrical performance characteristics of high quality conductors such as discrete wiring may be combined with robust mechanical characteristics in a flex circuit.
It is a further advantage of a preferred embodiment of the present invention that a flex circuit connection with robust mechanical and electrical characteristics may be reliably and consistently manufactured.
It is a still further advantage of a preferred embodiment of the present invention that impedance mismatch and other electrical performance problems associated with introduction of connectors into the signal path may be minimized.
It is a still further advantage of a preferred embodiment of the present invention that high quality conductors may be employed which do not suffer the yield losses associated with fine line etching of conductive traces.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.


A full adder includes a static logic block for generating an inverted carry with respect to multiple inputs through an inverted carry output node; a first dynamic inverter logic block for inverting the inverted carry produced from the static logic block via the inverted carry output node according to a clock, to thereby generate a carry through a carry output node; a dynamic logic block for generating an inverted sum with respect to the multiple inputs according to an inverted clock via an inverted sum output node; and a second dynamic inverter logic block for inverting the inverted sum generated from the dynamic logic block via the inverted sum output node according to a clock, to thereby generate a sum through a sum output node.

1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a full adder for implementing a carry logic block and a sum logic block with static and dynamic logics, respectively, using an NMOS transistor.
2. Discussion of Related Art
Generally speaking, a full adder is an adder that receives input signals and outputs two outputs, SUM and CARRY. In case of three-bit full adder, the sum and carry for input signals A, B and C can be expressed as the following logic functions.
SUM=A'B'C'+A'BC'+AB'C'+ABC PA1 CARRY=AB+AC+BC PA1 SUM'=CARRY'(A+B+C)+ABC PA1 CARRY'={AB+C(A+B)}'
FIG. 1 shows a conventional full adder using a CMOS transistor. This adder using CMOS transistor runs in negative logic so that the logic functions of SUM and CARRY should be implemented in the negative logic.
In FIG. 1 the conventional full adder is made up with first. to fourth logic blocks 11-14. The first logic block 11 receives three inputs A, B and C and implements inverted carry CARRY'={AB+C(A+B)}'. The second logic block 12 inverts the inverted carry CARRY' outputted from the first logic block 11 to thereby output carry CARRY. The third logic block 13 receives the inverted carry output CARRY' outputted from the first logic block 11, and three inputs A, B and C, to thereby implement inverted sum SUM'=CARRY'(A+B+C)+ABC. The fourth logic block 14 inverts the inverted sum SUM' outputted from the third logic block 13 to thereby output sum SUM.
The logic circuit of the full adder using CMOS transistor is expected to reduce the power consumption, but reduces the processing speed and increases the area of chip because it requires three-stage CMOS logic circuit in order to implement the full adder logic block.
Referring to FIG. 2, a full adder using complementary pass transistor logic (CPL) produces sum SUM and carry CARRY according to the exclusive-ORed signal of two inputs A and B and other input signal C.
If the first and second input signals A and B have different levels, the exclusive-ORed signal A.sym.B becomes HIGH so that transmission gates 23 and 25 are turned on and transmission gates 22 and 24 are turned off. As the sum SUM, third input signal C is output after being inverted, and as the carry CARRY, the third. input signal C is output as it as.
If the first and second input signals A and B have the same level, exclusive-ORed signal A.sym.B becomes LOW so that transmission gates 23 and 25 are turned off and transmission gates 22 and 24 are turned on. As the sum SUM, third input signal C is outputted as it is, and as the carry CARRY, the second input signal B is outputted as it is. The operation of the full adder using CPL is shown in table 1.
TABLE 1 ______________________________________ A B C B' A.sym.B 22 23 24 25 SUM CARRY ______________________________________ 0 0 0 1 0(B) ON OFF ON OFF 0(C) 0(B) 0 0 1 1 0(B) ON OFF ON OFF 1(C) 0(B) 0 1 0 0 1(B) OFF ON OFF ON 1(C') 0(C) 0 1 1 0 1(B) OFF ON OFF ON 0(C') 1(C) 1 0 0 1 1(B) OFF ON OFF ON 1(C') 0(C) 1 0 1 1 1(B) OFF ON OFF ON 0(C') 1(C) 1 1 0 0 0(B) ON OFF ON OFF 0(C) 1(B) 1 1 1 0 0(B) ON OFF ON OFF 1(C) 1(B) ______________________________________
Here, "1" represents the HIGH level signal, and "0" does the LOW level signal.
The full adder using CPL performs the full adding through the transmission gates results in a fast performance speed but there are drawbacks the overall power consumption and the area of chip are increased.
Referring to FIG. 3, like the full adder using CMOS transistor shown in FIG. 1, a full adder using pseudo-NMOS transistor includes first to fourth logic blocks 31-34 for outputting sum SUM and carry CARRY, having the same operation. The difference is that gate-grounded PMOS transistors MP31-MP34 as load are connected between the power terminal VDD and the output stages of the logic blocks. The full adder using pseudo-NMOS transistor can decrease the area of chip but also reduces the processing speed and increases the power consumption.
Referring to FIG. 4, like the full adder using CMOS transistor shown in FIG. 1, a full adder using quasi-domino logic has four logic blocks 41-44 for outputting sum SUM and carry CARRY. The third logic block 43 for outputting sum SUM is made with a dynamic logic circuit, the first logic block for outputting carry CARRY being with a quasi-dynamic logic circuit.
The first logic block 41 of the full adder using quasi-domino logic is designed to output inverted carry CARRY' at the output node NODE1, having a discharging portion with NMOS transistors MN11 and MN12 that perform discharging according to inverted clock CLKB. For instance, if the inverted clock CLKB is HIGH, NMOS transistor MN11 is turned on so that a current path is formed between output node NODE1 and ground VSS. In this state the first logic block 21 performs discharging, and node NODE1 becomes LOW.
Meanwhile, if inverted clock CLKB is LOW, NMOS transistor MN11 is turned off so that the inverted carry CARRY' at node NODE1 is determined according to three input signals A, B and C. Here, inverted carry CARRY' at node NODE1 is shown in table 2.
TABLE 2 ______________________________________ A B C MP13 MP12 MP11 MP14 MP15 NODE1 ______________________________________ 0 0 0 ON ON ON ON ON 1 0 0 1 OFF ON ON ON ON 1 0 1 0 ON OFF ON ON OFF 1 0 1 1 OFF OFF ON ON OFF 0 1 0 0 ON ON OFF OFF ON 1 1 0 1 OFF ON OFF OFF ON 0 1 1 0 ON OFF OFF OFF OFF 0 1 1 1 OFF OFF OFF OFF OFF 0 ______________________________________
In table 2, if two input signals A and B, A and C, or B and C are LOW at the same time, and only if three inputs A, B and C are LOW at the same time, the inverted carry CARRY' at node NODE1 becomes HIGH. Therefore, it is noted that the first logic block 41 performs CARRY'={AB+C(A+B)}'.
The inverted carry CARRY' of first logic block 41 is applied to the second logic block 42, a dynamic inverter logic logic circuit. The second logic block 42 inverts the inverted carry CARRY' outputted from first logic block 41 according to clock CLK that is HIGH, to thereby output carry CARRY.
The third logic block 43 is a quasi-dynamic logic circuit that performs SUM'={CARRY'(A+B+C)+ABC}'. As the precharging portion for precharging node NODE2, third logic block 43 comprises PMOS transistor MP31. In other words, if clock CLK is LOW, PMOS transistor MP31 is turned on so that node NODE2 is precharged in the HIGH state. If clock CLK is HIGH, PMOS transistor MP31 is turned off so that the inverted sum SUM' at node NODE2 is determined according to inputs A, B and C as shown in table 3.
TABLE 3 __________________________________________________________________________ A B C NODE1 MN35 MN33 MN31 MN32 MN34 MN36 MN37 NODE2 __________________________________________________________________________ 0 0 0 1 OFF OFF OFF OFF OFF OFF ON 1 0 0 1 1 ON OFF OFF OFF OFF ON ON 0 0 1 0 1 OFF ON OFF OFF ON OFF ON 0 0 1 1 0 ON ON OFF OFF ON ON OFF 1 1 0 0 1 OFF OFF ON ON OFF OFF ON 0 1 0 1 0 ON OFF ON ON OFF ON OFF 1 1 1 0 0 OFF ON ON ON ON OFF OFF 1 1 1 1 0 ON ON ON ON ON ON OFF 0 __________________________________________________________________________
In table 3, if inverted carry CARRY' at node NODEl is HIGH, input A, B or C is HIGH, and three inputs A, B and C are HIGH at the same time, node NODE2 becomes LOW. Therefore, third logic block 43 outputs inverted sum SUM' at node NODE2 according to clock CLK that is HIGH.
Like the second logic block 42, the fourth logic block 44 is a dynamic inverter logic circuit that inverts the inverted sum SUM' output from third logic block 43 according to HIGH clock CLK to thereby output sum SUM.
The quasi-domino full adder logic circuit increases the overall area of chip because the first logic block 41 outputting inverted carry CARRY' is implanted with a PMOS transistor. In addition, the width of voltage swing at nodes NODEI and NODE2 increases to reduces the processing speed in turn because the pull-up transistor is made with PMOS transistor.

Hyundai Electronics Industries Co., Ltd.


A therapeutic bandage provides a removable bandage article that can be readily wrapped and fastened around an injured joint. The bandage includes an internal air bladder that can be selectively inflated to provide compression to the injury, and an internal coolant bladder that can be selectively chilled to provide cooling therapy to the injury.

1. Field of the Invention
This invention relates generally to first aid methods and associated medical rehabilitative materials, and more specifically to an improved therapeutic bandage device for efficient treatment of minor injury or discomfort to a user's joints.
2. Description of the Prior Art
Bandages such as those used to support and treat joint injuries are well known. Typically, such bandages consist of a length of elastic material that is wrapped around the joint and secured in place with pins or clamps, thereby temporarily supporting or otherwise immobilizing the joint. However, such known bandages are difficult to adjust in their degree of compression to the injury, and may be awkward to properly apply. In addition, such bandages do not readily enable cooling or chilling of the injured area, which can be important in therapeutic treatment.


The present invention relates to an image processing apparatus, and more particularly, to a device and method capable of binarizing pixels by removing an isolated point. The pixel binarization method contemplates the steps of: establishing a local window of pixels including a central pixel and a plurality of neighboring pixels; analyzing the neighboring pixels within the local window and detecting a minimum brightness value and a maximum brightness value exhibited by the neighboring pixels; comparing a brightness value exhibited by the central pixel with the minimum brightness value; and determining the central pixel to be an isolated point and outputting the central pixel as a white pixel when the brightness value exhibited by the central pixel is less than the minimum brightness value.

The present invention relates to an image processing apparatus, and more particularly, to a device and method for binarizing pixels by removing isolated points.
Generally, an image processing system, such as a facsimile machine, compares a mean brightness value of local pixels with a brightness value of a central pixel to determine the logic state in which a pixel is binarized. A binarization method of this type is disclosed in Korean Patent No. 93-3484, assigned to the same assignee as the present invention. This type of method is used in a facsimile machine for improving character readability by emphasizing edge regions in consideration of a brightness characteristic of local pixels. Such a method, however, applies uniform threshold values without consideration of the quality of the document being processed. Therefore, when documents of normal quality are processed, character readability can be improved. When documents of poor quality are processed, however, isolated black dots (i.e., isolated points) are generated on the white background of the document. In particular, when there is only a slight difference in brightness between the edges of the image and the white background of the document, in order for these edges to be cleanly displayed as black lines, the threshold value must be reduced. For example, when pixels exhibit 16 different levels of brightness, wherein level 16 represents a brightest level and level 1 represents a darkest level, the threshold value should be set to represent either level 1 or level 2. Doing this, however, creates a problem in that the possibility of generating undesired isolated points increases. The present invention is directed towards solving this problem.

Pixel binarization device and method for image processing system


A synthetic, nuclear-encoded ND4 gene was linked to a mitochondrial targeting sequence and a FLAG epitope tag. This fusion construct was inserted into a rAAV vector. The ND4 fusion protein was expressed and imported into the mitochondria of cells harboring a mitochondrial DNA mutation (G11778A), where it restored cellular respiration.

A G to A transition at nucleotide 11778 in mitochondrial DNA (mtDNA) in the gene specifying the ND4 subunit of complex I results in an arginine to histidine substitution at amino acid 340. This mtDNA point mutation was linked to Leber Hereditary Optic Neuropathy (LHON), a maternally-inherited human disease that leads to blindness in patients during their 2nd and 3rd decades of life. Since this discovery (Wallace et al., Science 242:1427-1430, 1988), more than 30 other pathogenic point mutations in human polypeptide-coding mtDNA genes have been described. While mtDNA encodes 13 mitochondrial proteins involved in oxidative phosphorylation, the remainder of these proteins are encoded by nuclear DNA, synthesized on cytoplasmic ribosomes, and imported into the mitochondria (usually directed by an N-terminal mitochondrial targeting presequence) (Hartl et al., Science 247:930-938, 1990). Thus, mutations in either mtDNA or nuclear DNA may impair mitochondrial function and thereby result in human disease (Schon EA, Trends Biochem Sci. 25:555-560, 2000).
LHON is the most common of all mitochondrial diseases. Three mtDNA mutations (G3460A, G11778A and T14484C) account for 95% of LHON cases, with the G11778A mutation being the most common, accounting for 50% of LHON cases (Chinnery et al., Ann Neurol. 48:188-193, 2000 and Carelli et al., Ann Neurol. 45:320-328, 1999). Each of the foregoing LHON mutations affects a different subunit of the nicotinamide adenine dinucleotide::ubiquinone oxidoreductase complex (complex I) in the oxidative phosphorylation pathway, where electrons first enter the electron transport chain (Wallace DC, Science, 283:1482-1488, 1999). This large enzyme consists of 7 subunits (ND1, 2, 3, 4, 4L, 5, and 6) encoded by mtDNA, while the remaining 35 subunits are nuclear-encoded (Sazanov et al., Biochemistry 39:7229-7235, 2000). Mitochondrial oxidative phosphorylation deficiency due to mutations in complex I subunit genes is believed to play a pivotal role in development of LHON, although the precise pathophysiologic events precipitating acute visual failure and cellular injury remain incompletely understood. Each LHON mutation alters mtDNA-encoded intrinsic complex I membrane proteins, but surprisingly, results from standard spectrophotometric assays of complex I activity in LHON cells containing the G11778A mutation in the ND4 subunit gene are reduced only slightly (Vergani et al., Biochem Biophys Res Commun. 210:880-888, 1995; Majander et al., FEBS Lett. 292:289-292, 1991; and Larsson NG et al., Ann Neurol. 30:701-708, 1991). Only the G3460A mutation in the ND1 subunit gene reduces complex I activity markedly (Brown et al., J Biol. Chem., 275:39831-39836, 2000 and Cock et al., J Neurol Sci. 165:10-17, 1999). However, clear evidence of complex I deficiency with all three pathogenic mutations comes from polarographic investigations showing impairment of cellular respiration when driven by complex I linked substrates (Majander et al., FEBS Lett. 292:289-292, 1991 and Larsson N G et al., Ann Neurol. 30:701-708, 1991). How these different degrees of changes in complex I function result in the same clinical picture of almost simultaneous bilateral apoplectic visual failure during early adult life is unclear, but reductions in oxidative phosphorylation and cellular injury induced by reactive oxygen species are suspect (Esposito et al., Proc Natl Acad Sci USA 96:4820-4825, 1999 and Brown MD, J Neurol Sci. 165:1-5, 1999).
Unlike most other mitochondrial mutations that impair neurologic and myocardial function and are often fatal, patients with LHON, though blind, have a normal life expectancy. Unfortunately, there is little propensity for spontaneous visual recovery in the G11778A LHON patients, and there is no effective therapy. One of many potential avenues for treatment is to utilize gene therapy to introduce a "normal" gene encoding the defective complex I subunit into the optic nerves of LHON patients. While exogenous genes have been successfully imported into the nuclear genome to protect the optic nerve, (Guy et al., Arch Ophthalmol. 117:929-937, 1999 and Guy J, Proc Natl Acad Sci USA 95:13847-13852, 1998) these methods cannot be applied directly to similarly introduce genes into the mammalian mitochondrial genome.

Reducing cellular dysfunction caused by mitochondrial gene mutations

University of Florida Research Foundation, Inc.


A sensor system and method of operating such a sensor system for measuring an angle of rotation with an arrangement of at least four magnetic sensors (10, 11, 12, 13), at least four signal modulators (30, 31, 32, 33), each one connected to one of the magnetic sensors (10, 11, 12, 13) and having at least two control states, whereby, in a first state (+), a signal received from a sensor (10, 11, 12, 13) is output by the signal modulators (30, 31, 32, 33) and, in a second state (−), the inverse of the signal received from the sensor (10, 11, 12, 13) is output by the signal modulators (30, 31, 32, 33), a means (90) for adding the signals output by the signal modulators (30, 31, 32, 33) and a diametrically magnetized magnetic source (9). The sensor system further comprises a data output (82) and a control circuit (80) with at least one control input (81), allowing to switch the control circuit (80) into at least two different modes. In a normal mode of operation, the signal modulators (30, 31, 32, 33) are configured in such a way that a signal corresponding to the angular position of the diametrically magnetized magnetic source (9) is output to the data output. In an alignment mode of operation, the signal modulators (30, 31, 32, 33) are configured in such a way that a signal corresponding to the average magnetic field strength detected by the sensors (10, 11, 12, 13) is output to the data output (82).

From the document U.S. Pat. No. 7,095,228 a sensor system and a method for operating the sensor system are known, which allow for the analysis of two- and three-dimensional magnetic field distributions. The sensor system comprises an arrangement of sensors wherein each sensor is connected to a signal modulator. By issuing appropriate control signals, the signal modulators either forward the original sensor signal or its inverse to a signal adder, which combines all signals output by the modulators to a single system signal. The content of U.S. Pat. No. 7,095,228 is hereby incorporated by reference.
Several sensors arranged in a plane can be configured in such a way as to first measure a first component of a magnetic field in a first direction of said plane and then be configured to measure a second component of the magnetic field in a second direction of that plane, preferably orthogonal to the first direction. By performing predetermined arithmetic operations on the first and second measurements the rotational angle of the magnet with respect to the location of the sensors can be computed.
FIG. 1A shows a magnet 9, which is axially symmetric with respect to the z-axis. Its magnetic axis, i.e. the axis through its North (N) and South (S) pole is aligned with the x-axis of the coordinate-system.
FIG. 1B shows a side view of the magnet 9 along the x-axis. In addition to the magnet 9 itself, its magnetic field pattern is shown using flux lines, starting at the magnet's North (N) pole and ending at its South (S) pole.
FIG. 1C shows the amplitude B of the tangential magnetic field of the magnet 9 shown in FIG. 1A. The magnetic field amplitude is zero at the center of the magnet, i.e. the z-axis, and increases linearly to the edge of the magnet. Further away from the magnet 9 the strength of magnetic field decreases rapidly with the distance from its center and approaches zero for big distances. At a particular distance x1 from the center of the magnet, the magnetic field has a value of B0.
FIG. 2 shows the magnet 9 placed in a plane with a sensor arrangement comprising four sensors 10, 11, 12 and 13, which are placed on a circle with radius x1 around the center of the magnet 9. The angle between the symmetry axis of the magnet 9, i.e. the y-axis, and a ray through the sensor 10 is denoted with α1, which equals 45° in the presented example. In general, the rotation of the magnet 9 with respect to the sensor arrangement is denoted with the symbol α.
FIG. 3 shows a circuit comprising a magnetic sensor 10 and an associated signal modulator 30 according to the prior art. A magnetic sensor 10, for example a Hall sensor, measures the magnetic field by outputting a voltage proportional to the strength of the magnetic field on the two outputs 21 and 22. The measured voltage provided to the outputs 21 and 22 is converted into a current and amplified, if necessary, by a transconductance amplifier 70. The amplified output signal is provided to inputs 41 and 42 of the signal modulator 30. In order to keep FIG. 3 simple, no supply lines to the sensor 10, the transconductance amplifier 70 or the signal modulator 30 are shown.
The signal modulator 30 is used to forward the signal received from the inputs 41 and 42 to the modulator outputs 51 and 52, either unmodified or inverted. In order to invert the signal received from the inputs 41 and 42, the signal modulator 30 receives control signals from a control unit 60 which can either connect the output 41 with the output 51 and the output 42 with the output 52 or, inversely, connect the output 41 with the output 52 and the output 42 with the output 51.
For this purpose the signal modulator 30 comprises four electronic switches, e.g. transistors, which are controlled by three control signals en, p and m, which are provided by the control unit 60. The control signal en enables the signal modulator 30. If, together with the enable signal en, a signal p is provided to the control unit 60 the output signal from the inputs 21 and 22 is passed through to the outputs 51 and 52 unmodified. If however, a control signal m is provided in combination with a control signal en, then the inverted signal provided at the inputs 21 and 22 is forwarded to the outputs 51 and 52.
The sensor arrangement according to the prior art is constructed in such a way that always two sensors are arranged as a pair, canceling out errors resulting from a minor misalignment of the diametrically magnetized magnetic source.
However, in order to achieve optimal performance of the sensor arrangement it is important to align the magnetic source correctly in the middle of the sensor arrangement, i.e. it should be placed exactly in its center, with its magnetic axis parallel to the sensor plane and its rotary axis orthogonal to this plane and in the center of the magnet.

Magnetic rotary encoder and method for iteratively aligning magnet relative to magnetic sensors


After a device having a particular function is detected from among devices connected to a network and if a transmission medium to the detected device is not a transmission medium compatible with a predetermined transmission system, an alarm message is displayed. A user can therefore be notified of that the detected device is not connected through a transmission medium suitable for data communications.

1. Field of the Invention
The present invention relates to a communication apparatus connectable to a network via a digital interface.
2. Related Background Art
There are many digital device having a digital interface for communications with external devices and the like. Such digital devices are interconnected through digital interfaces so that a network system can be configured. Conventionally, one network system has been configured by using only one type of digital interfaces, and it is difficult to configure the network system using different types of digital interfaces.
As one method of solving this problem, UPnP (Universal Plug and Player) has been proposed (Reference Document 1: Universal Plug and Play Device Architecture, Version 1.0, 08 Jun. 2000). UPnP performs communications among different interfaces by using the IP (Internet Protocol). UPnP can therefore configure a network system using different types of interfaces, independently from transmission media compatible with interfaces.
FIG. 9 shows an example of a network system in conformity with UPnP (hereinafter called a UPnP network system). Referring to FIG. 9, a DTV 103 as a control point can detect and control a DVCR 104 as a device. However, DTV 103 and DVCR 104 are not directly connected through a transmission medium capable of data communications in conformity with the IEEE1394 Standard (Reference Document 2: IEEE Std 1394-1995, IEEE Standard for a High Performance Serial Bus, Institute of Electrical and Electronics Engineers, Inc.), and DTV 103 cannot receive moving image data from DVCR 104 using the IEC61883 protocol (Reference Document 3: IEC 61883-1, Consumer audio/video equipment—Digital interface—Part 1: General). Therefore, in the UPnP network such as shown in FIG. 9, even if a user operates a panel for controlling DVCR 104 displayed on the display screen of DTV 103, a reproduced image will not be displayed on the screen. Even if each device connected to the UPnP network operates normally, a user may judge that the device is out of order.

Detecting whether a connection between apparatuses includes a predetermined transmission medium


A system and method are disclosed for transmitting signals from a digital MAC interface to a bus and for transmitting signals from a bus to a digital MAC interface. A first bus data line is modulated by holding the first bus data line at a potential when the transmit data line is in a first state and allowing the first bus data line to float when the transmit data line is in a second state when data transmission from the digital MAC interface is enabled. A second bus data line is modulated by holding the second bus data line at a potential when the transmit data line is in the second state and by allowing the second bus data line to float when the transmit data line is in the first state. One of the bus data lines are connected to a receive data line on the digital MAC interface. The state of the first data line is compared to the state of the second data line the collision line is set to a fist preselected state when the state of the first data line and the state of the second data line are both a second preselected state.

1. Field of the Invention
The present invention relates generally to methods and apparatuses for implementing an Ethernet physical media using a digital bus that includes three wires.
2. Description of the Related Art
The growth of local-area networks (LANs) has been driven by the introduction of Ethernet Technology as well as the availability of powerful, affordable personal computers and workstations.
Ethernet
Ethernet is a Media Access Control (MAC) layer network communications protocol specified by the Institute of Electrical and Electronics Engineers (IEEE) in IEEE specification 802.3 (the xe2x80x9c802.3 specificationxe2x80x9d). When the Ethernet protocol is used, network devices each listen on a network bus and transmit only when no other network device is transmitting. Occasionally, two nodes do transmit nearly simultaneously and a collision occurs. A network that that includes detection of such collisions is referred to as a Carrier Sense Multiple Access Collision Detection (CSMA/CD) network.
Early Ethernet applications used a coaxial cable that carried an analog signal for the bus. Collisions were detected by analyzing the analog signal on the line to determine when two network devices were transmitting. In one implementation, collisions were detected by measuring the energy on the bus. Later, Ethernet was implemented on a set of digital communication lines that included separate transmit and receive lines. In such systems, collisions are detected by each network device by noting when data appears on the receive line while the network device is transmitting. The separate transmit and receive digital lines for each device make it necessary to have a hub to connect each of the transmit lines of the network devices to all of the receive lines of other network devices. Ethernet hubs are also referred to as repeaters. An Ethernet repeater serves as a central station for connecting network devices included in an Ethernet network, hence the term xe2x80x9chub.xe2x80x9d An Ethernet repeater receives messages from the transmission lines of network devices that are plugged into it and broadcasts (or xe2x80x9crepeatsxe2x80x9d) the message to all of the devices on the network on their receive lines.
As the Ethernet standard has evolved, the basic CSMA/CD scheme has remained for the most part the same. In July 1993, a group of networking companies joined to form the Fast Ethernet Alliance. The charter of the group was to draft the 802.3u 100BaseT specification (xe2x80x9c802.3u specificationxe2x80x9d) of the Institute of Electrical and Electronics Engineers (IEEE) and to accelerate market acceptance of Fast Ethernet technology. The final IEEE 802.3 specification was approved in June 1995. Among the other goals of the Fast Ethernet Alliance are: to maintain the Ethernet transmission protocol (CSMA/CD); to support popular cabling schemes; and to ensure that Fast Ethernet technology will not require changes to the upper-layer protocols and software that run on LAN workstations. For example, no changes are necessary to Simple Network Management Protocol (SNMP) management software or Management Information Bases (MIBs) in order to implement Fast Ethernet.
CSMA/CD
Carrier sense-collision detection is widely used in LANs. Many vendors use this technique with Ethernet and the IEEE 802.3 specification. A carrier sense LAN considers all stations as peers; the stations contend for the use of the channel on an equal basis. Before transmitting, the stations monitor the channel to determine if the channel is active (that is, if another station is sending data on the channel). If the channel is idle, any station with data to transmit can send its traffic onto the channel. If the channel is occupied, the stations must defer to the station using the channel.
FIG. 1A depicts a carrier sense-collision detection LAN. Network devices 102, 104, 106, and 108 are attached to a network bus 110. Only one network device at a time is allowed to broadcast over the bus. If more than one device were to broadcast at the same time, the combination of signals on the bus would likely not be intelligible. For example, assume network devices 102 and 104 want to transmit traffic. Network device 108, however, is currently using the channel, so network devices 102 and 104 must xe2x80x9clistenxe2x80x9d and defer to the signal from network device 108, which is occupying the bus. When the bus goes idle, network devices 102 and 104 can then attempt to acquire the bus to broadcast their messages.
Because network device 108""s transmission requires time to propagate to other network devices, the other network devices might be unaware that network device 102""s signal is on the channel. In this situation, network device 102 or 104 could transmit its traffic even if network device 108 had already seized the channel after detecting that the channel was idle.
Each network device is capable of transmitting and listening to the channel simultaneously. When an analog communication line is used and two network device signals collide, they create voltage irregularities on the channel, which are sensed by the colliding network devices. The network devices then turn off their transmission and, through an individually randomized wait period, attempt to seize the channel again. Randomized waiting decreases the chances of another collision because it is unlikely that the competing network devices generate the same wait time. When digital lines are used, the network devices detect collisions by detecting data on the receive line at the same time as they are transmitting.
FIG. 1B is a block diagram illustrating a topology used in a conventional analog Ethernet network. An analog bus line 100 connects network devices 112, 114, and 116. Additional network devices may be added to the network by simply tapping into analog bus line 100. Since each network device transmits and receives on the same line, there is no need to include a device to connect the transmit lines of one network device to the receive lines of another network device. Each network device listens on analog bus line 100 before transmitting to make sure that no other network device is already using the bus. When two network devices simultaneously or nearly simultaneously begin transmitting, a collision occurs. The collision is sensed by the network devices by analyzing the analog signal on line 100.
FIG. 1C is a block diagram illustrating a digital implementation of a digital Ethernet network that includes network devices 122, 124, and 126 and 128. The digital Ethernet network does not include a common bus line as shown in FIG. 1B for the analog Ethernet network. That is because each network device includes both a transmit data line and a receive data line. Each network device therefore, must be connected to a Repeater 120. Repeater 120 receives the data transmitted on each of the data transmit lines belonging to the different network devices and repeats the transmitted data onto a each of the data receive lines of the network devices. Repeater 120 is also referred to as a hub. The interface between each network device and the repeater includes 7 wires that carry a set of signals according to the Ethernet network standard.
It would be useful if a digital Ethernet network could be implemented without requiring the use of a hub. Furthermore, it would be useful if the number of wires required to provide connections to each of the network devices in such a network could be minimized.
Accordingly, a digital Ethernet network is disclosed that allows transmission of data by multiple stations on a shared bus and does not require a hub or repeater. In one embodiment, the network uses only two wires to transmit and receive data, and a third wire for a common clock. The two data wires are logical complements of each other while data is being transmitted. Collisions are detected based on the signals transmitted on the two wires before corrupted data is transferred.
It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, a system and method are disclosed for transmitting signals from a digital MAC interface to a bus and for transmitting signals from a bus to a digital MAC interface. A first bus data line is modulated by holding the first bus data line at a potential when the transmit data line is in a first state and allowing the first bus data line to float when the transmit data line is in a second state when data transmission from the digital MAC interface is enabled. A second bus data line is modulated by holding the second bus data line at a potential when the transmit data line is in the second state and by allowing the second bus data line to float when the transmit data line is in the first state. One of the bus data lines is connected to a receive data line on the digital MAC interface. The state of the first data line is compared to the state of the second data line the collision line is set to a fist preselected state when the state of the first data line and the state of the second data line are both a second preselected state.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.

Method and apparatus for implementing an ethernet protocol using three wires


In a system having a multiplexed address/data bus, initiator and target devices on the bus use special three mode drivers to achieve fast back-to-back read operations without intervening turnaround cycles. These drivers have voltage, current and Hi-Z modes characterized by low output impedance, high output impedence and very high output impedance, respectively. During a first clock cycle, an initiator device places an address on the bus using voltage mode during the first phase of the clock cycle and current mode during second phase. During a second clock cycle, a target device places data on the bus using voltage mode during the first phase of the clock cycle and current mode during second phase. Because a high impedance current mode precedes a low impedance voltage mode, electrical contention problems are eliminated, even if two devices momentarily drive the bus to opposite logical states. Fast back-to-back write operations are also described.

This invention pertains to computer systems and other information handling systems and, more particularly, to a computer system employing a multiplexed address/data bus in which xe2x80x9cturnaround cyclesxe2x80x9d or xe2x80x9cwait cyclesxe2x80x9d are eliminated.
In the design of computer buses, the reduction in the total number of signal lines is frequently an important criterion. From a mechanical design standpoint, reducing the total number of lines also reduces the total number of pins for any connector that is coupled to the bus. One way to reduce the total number of lines is to xe2x80x9ctime multiplexxe2x80x9d the address and data signals such that there is only one set of xe2x80x9caddress/dataxe2x80x9d lines that carry both address and data information, but at different times. In other words, during certain intervals of time address information is transmitted over the address/data lines, while data is transmitted over these same lines during other intervals of time.
One such industry standard bus is the Peripheral Component Interconnect bus or PCI bus. On the PCI bus, 32 bits of address information and 32 bits of data are transmitted over the same 32 address/data lines. If the PCI bus did not use time multiplexing, a total of 64 lines would be needed just to carry the address and data information. Consequently, for PCI, the use of time multiplexing for the address and data signals reduces the total number of signal lines by 32, which also reduces the bus connector xe2x80x9cpin countxe2x80x9d by the same amount. Consequently, when compared to other competing buses that do not multiplex the address and data signals, the PCI bus has about half the total number of signal lines.
Since two or more devices can drive the bus, electrical contention problems can result. These contention problems are caused by the first device""s failure to relinquish the bus before the second device takes over. Consequently, for a brief interval of time, two bus driver circuits coupled to the same line on the bus may be simultaneously attempting to drive that line to two different logic levels. These contention problems become more acute with increased bus speeds.
To alleviate this electrical contention problem, it is common in the industry to have xe2x80x9cturnaround cyclesxe2x80x9d or xe2x80x9cwait cyclesxe2x80x9d allocated between the time when one device is driving the bus and the time when another device takes over. The disadvantage to the insertion of turnaround cycles, however, is that they decrease data throughput. For example, on the PCI bus, turnaround cycles reduce the data throughput by 50% for all non-burst mode read cycles, and for non-burst mode write cycles involving either a change of initiator or target device the throughput is reduced by 33%.
The term xe2x80x9cback-to-back writexe2x80x9d or xe2x80x9cback-to-back readxe2x80x9d refers to two or more consecutive data transfer operations (i.e., read or write operations) in non-burst mode between the same initiator device and the same target device, with or without turnaround cycles. For non-burst mode data transfers, address information is transmitted over the bus at the beginning of each individual data transfer operation. For burst mode data transfers, however, consecutive data transfer operations are read from or written to consecutive address locations so that the base address information is only transmitted once at the beginning of each burst of data. The term xe2x80x9cconventional back-to-back transferxe2x80x9d refers to a back-to-back transfer that includes turnaround cycles, while the term xe2x80x9cfast back-to-back transferxe2x80x9d refers to a back-to-back transfer in which turnaround cycles have been eliminated.
One method for the elimination of turnaround cycles for back-to-back write operations is described in U.S. Pat. No. 5,448, 703. According to this patent, a PCI initiator uses address range checking hardware to detect that two consecutive write cycles are to the same physical target device, and then eliminates turnaround cycles for this type of write operation. This technique for eliminating turnaround cycles for back-to-back writes has been incorporated into version 2.0 of the PCI specification. The""703 patent, however, also explicitly excludes read cycles as candidates for fast back-to-back transfers.
The industry solution to the turnaround cycle problem has another drawback; specifically, write throughput is different from read throughput. Since certain software applications require symmetrical read and write rates, it is necessary to slow the write rate down to equal that of the slower read rate. However, the calculation of the different read and write rates in software is not a trivial problem. Thus, it is desirable for the read throughput and the write throughput to be the same.
Contention is particularly problematic on a multiplexed address/data bus when an initiator device performs a read operation on a register in a target device. Since the initiator device places the address information on the address/data lines first, followed by the target device driving the register data onto the same address/data lines, a turnaround or wait cycle is inserted between the address cycle and the data cycle to prevent contention between the driver circuits in the initiator and the driver circuits in the target. Furthermore, for conventional back-to-back read operations, a turnaround cycle must also be inserted after the target device places data on the address/data lines to separate the previous data cycle from the next address cycle.
Accordingly, the invention described below eliminates turnaround cycles not only for back-to-back writes, but also for back-to-back reads. The elimination of turnaround cycles not only doubles the data throughput for back-to-back read operations, but also makes the data throughput for fast back-to-back read operations equal to the data throughput for fast back-to-back write operations.
To accomplish these advantages, the current invention utilizes a three mode (5state) bus driver circuit, which is described in a related patent application Ser. No. 09/162,618 (now U.S. Pat. No. 6,088,756) and which was filed on the same date as this application. This co-pending application, which is incorporated into this application by reference, is entitled xe2x80x9cFive State Bus Driver Having Both Voltage And Current Source Modes Of Operationxe2x80x9d.
Briefly, the invention is a method and apparatus for performing data read operations between an initiator device and a target device that are coupled to a bus. A clock signal on one line of the bus includes a plurality of clock cycles wherein each clock cycle includes a first and a second phase. Each of the initiator and target devices includes a three mode bus driver having three selectable modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is a Hi-Z mode having high output impedance. During a first clock cycle, the third mode of operation is selected for the driver of the target device. The initiator device drives a first address onto the bus during the first clock cycle. For the driver of the initiator device, the first mode of operation is selected during the first phase of the first clock cycle and the second mode of operation is selected during the second phase of the first clock cycle. During a second clock cycle, the third mode of operation is selected for the driver of the initiator device, and the target device drives first data onto the bus. For the driver of the target device, the first mode of operation is selected during the first phase of the second clock cycle, and the second mode of operation is selected during the second phase of the second clock cycle.
In another embodiment, the invention is a method and apparatus for performing a data write operation from an initiator device to a first target device that are coupled to a bus. A clock signal on one line of the bus includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase. Each of the initiator and target devices includes a three mode bus driver having three selectable modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is Hi-Z mode having very high output impedance. During a first and a second clock cycle, the third mode of operation is selected for the driver of the first target device. The initiator device drives a first address onto the bus during the first clock cycle. For the driver of the initiator device, the first mode of operation is selected during the first phase of the first clock cycle. During the second clock cycle, the initiator device drives first data onto the bus. For the driver of the initiator device, the first mode of operation is selected during the first phase of the second clock cycle, and the second mode of operation is selected during the second phase of the second clock cycle.
In still another embodiment, the invention is a method and apparatus for performing a data write operation from an initiator device to a first target device. A clock signal on one line of the bus includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase. A control signal on a control line of the bus has active and inactive states, wherein the active state is asserted when the target device is ready to accept data from the initiator device. The first target device includes a three mode bus driver having three selectable output modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is Hi-Z mode having very high output impedance. The three mode bus driver of the first target device is coupled to the control line of the bus. The initiator device places a first address on the bus during a first clock cycle. The target device drives the control line active during the second clock cycle. During the first phase of the second clock cycle, the first mode of operation is selected for the driver of the first target device, while the second mode of operation is selected during the second phase of the second clock cycle. During the second clock cycle, the initiator device places first data on the bus.

Elimination of turnaround cycles on multiplexed address/data buses

International Business Machines Corporation


Disclosed is a tape cartridge which contributes to shorten the time for sensing an RFID tag in the tape cartridge itself, and which makes it possible to sense the condition of the RFID tag. The tape cartridge includes a tape-shaped recording medium, an RFID tag for storing management information about the tape-shaped recording medium, a cartridge case containing the tape-shaped recording medium and the RFID tag, and an RFID tag sensing means making it possible to sense present of the RFID tag, the RFID tag sensing means being set in the cartridge case. In addition, the RFID tag sensing means includes two light-transmitting components for passing light therethrough, which are placed on a top surface of an upper half case of the cartridge case and on a bottom surface of a lower half case of the cartridge case, respectively, in alignment with the RFID tag.

1. Field of the Invention
An apparatus consistent with the present invention relates to a tape cartridge and, especially to a magnetic tape cartridge containing a tape-shaped recording medium. More specifically, an apparatus consistent with the present invention relates to a magnetic tape cartridge which makes it possible to sense the presence of an RFID tag within.
2. Description of the Related Art
Magnetic tape cartridges have been widely used as mass storage media. Such magnetic tape cartridges, however, have a structure that a single magnetic tape contains data, and their access time inevitably ends up being long. To overcome this disadvantage, a non-contact type of IC tag that functions as an automatic identifying means using radio waves or magnetic coupling has been produced, and a magnetic tape cartridge equipped with this IC tag has become popular. Hereinafter, an IC tag is referred to as "RFID (radio frequency identification) tag". Such an RFID tag is a medium on/from which information about the location of the data on the magnetic tape, production management of the magnetic tape cartridge, etc. can be written or read, and allows the access time for the magnetic tape cartridge to be short.
Concretely, an RFID tag includes within an IC chip that stores management information about the data recorded on the magnetic tape, and an antenna or a coil. Further, the RFID tag can communicate with an RFID reader/writer by means of radio waves or magnetic coupling in a non-contact manner (see a reference numeral 9 in FIG. 1). Furthermore, when certain data needs to be read from a magnetic tape cartridge, the management information about this data can be read from the RFID tag, so that the location of the data can instantly be pinpointed. Consequently, it is possible to access a magnetic tape cartridge efficiently.
As for the procedures of reading data from the magnetic tape cartridge with an RFID tag, the RFID reader/writer is first activated, then refers to the management information recorded on the RFID tag, and the data is finally read from the magnetic tape, based on the information. In addition, when new data is written on the magnetic tape, the RFID reader/writer writes, on the RFID tag, the management information about the new data. Furthermore, an RFID reader/writer senses the presence of an RFID tag. Concretely, an RFID reader/writer sends a command to an RFID tag, and then waits for a response from the RFID tag. The RFID reader/writer determines whether the RFID tag is present, based on the presence or absence of the response.
An RFID tag has conventionally been integrated into a cartridge, but recently, for the purpose of facilitating the exchange of RFID tags, a magnetic tape cartridge from which an RFID tag can be detached was disclosed (see Japanese Unexamined Patent Application No. 2003-297040). In this structure, an RFID tag is fixed to a block body separate from a cartridge, and this block body is inserted into an aperture in the cartridge. Moreover, a label type of RFID tag which can be affixed on the back of a cartridge was also proposed. This RFID tag can be attached/detached to or from a cartridge as appropriate.
However, in an RFID tag as in the examples above, problems may occur, such as the positional relationship between an RFID tag and an RFID reader/writer is not optimum, or the performances of them are quite different from each other. In these cases, the RFID reader/writer may fail to identify the RFID tag, or may spend a long time to search for the RFID tag. These disadvantages may also appear when the specifications between the RFID tag and the RFID reader/writer are mismatched.
An RFID tag of this type may be damaged when being attached/detached to or from the magnetic tape cartridge. In this case, the disadvantages above may also occur.
The present invention has been conceived, taking the disadvantages above into account. An object of the present invention is to provide a magnetic tape cartridge with an arrangement which makes it possible to sense the presence of an RFID tag, with or without an RFID reader/writer, thereby shortening the time to search for the RFID tag.
An additional object of the present invention is to provide a means for sensing, by working with an RFID reader/writer, the presence, condition, etc. of an RFID tag having various specifications.