A friction material matrix 2 consisting of a mixture of a fibrous base material, a binder, and various fillers is introduced into a molding die 3. Rod members 5 are inserted into the molding die 3 from above. The rod members 5 are vertically actuated while a stroke of the actuation of the rod members 5 is gradually reduced. The friction material matrix 2 is compressed until its volume becomes 50 to 60 vol. % of the initially introduced friction material matrix 2. Then, a bottom plate 4 is raised to compress the friction base matrix 2, so that the friction base matrix 2 is preformed.

1. Field of the Invention
The present invention relates to a method of preforming a friction material used as, for example, a disk brake friction pad for use in an automobile.
2. Related Art
For example, a disk brake friction pad for use in an automobile is manufactured by the steps of introducing a friction material matrix which consists of a mixture of a fibrous base material made from, e.g., metallic, inorganic, or organic fibers, a binder made from a thermosetting resin powder, and various fillers, e.g., a friction adjustor and a lubricant, into a molding die; stamping the friction material matrix at room temperature; preforming the stamped friction material matrix; transferring the thus formed preform to a thermoforming die having a back plate set thereto; and heating the thermoforming die under pressure (hereinafter referred to as thermoforming).
In the above described manufacturing processes, the friction material matrix introduced into the molding die is leveled before being preformed. For example, Japanese Patent Publn. No. Hei-2(1990)-51719 discloses a method of forming a two-layer disk brake friction pad. Specifically, the disk brake friction pad comprises a brake lining layer made from semi-metallic material, and a heat insulating layer which is made from material with plenty of heat insulating properties and has a projecting boss to be jointed into a dovetailed hole formed in a back plate. The method is characterized by comprising the steps of introducing material for use as the heat insulating layer into a molding die, forming the boss by stamping the heat insulating layer by lowering a boss-stamping rod, leveling the top of the heat insulating layer, introducing a powder and granular material, such as, a semi-metallic material on the flat top of the heat insulating layer, further leveling top of the semi-metallic material, and ramming the semi-metallic material and the heat-insulating layer by lowering a pressing ram into the molding die. Further, Japanese Patent Publn. No. Hei-3(1991)-6878 discloses a flattening apparatus preferably for use in the above described flattening operation.
As a result of the surface of the friction material matrix being leveled through the flattening operation, the thickness of the friction material matrix in the molding die becomes even. The distribution of pressure of the pressing ram also becomes even, which improves the moldability of the friction material matrix.
The friction material matrix consists of a mixture of a fibrous base material, a binder, and various fillers, and these materials are solid. When the friction material matrix is introduced into the molding die, a plenty of air is mixedly trapped in the friction material matrix. Some of the air escapes through voids between the interior wall of the molding die and the friction material matrix associated with a compressing operation. However, much of the air still remains in the preform. If the preform containing the residual air is thermally formed, the residual air expands, so that holes are formed in a resultant molding. Eventually, cracks or bulges are produced in the molding, that is, a disk brake friction pad.
The previously described flattening operation is only intended to level the upper surface of the friction material matrix. By means of this flatting operation, the adhesion between the two materials contained in the two-layer disk brake friction pad, as disclosed in Japanese Patent Publn. No. Hei-2(1990)-51719, and the adhesion of a contact surface between the friction material matrix and the pressing ram are improved. However, it is impossible to eliminate the air still remaining in the friction material matrix by the flattening operation.
In view of the friction effect and mechanical strength of the disk brake friction pad, it is desirable that the fibrous base material, the binder, and the various fillers should become united to each other, specifically, fibers should become closely interlocked together, and they should become integrally united together while the fillers run deep into the fibrous base material, in addition to the even distribution of the fibrous base material, the binder, and the fillers within the molding. The friction material matrix is prepared by formulating predetermined amounts of solid materials, that is, the fibrous base material, the binder, and the fillers, and by simply kneading them with each other. As a result, the materials become locally uneven and less united together.
However, it is impossible to make the materials united together as well as to make the friction material matrix homogenous to a much greater extent by use of the previously described flattening operation.


A method is described for selectively etching photoresist on a semiconductor substrate having one or more layers of a spin on glass, including an edge bead that was formed when the glass was originally applied. First the wafer is coated with a layer of unexposed, undeveloped negative photoresist. Then, while spinning the wafer, a vertical jet of photoresist EBR solvent is directed to a point just inside the edge so that photoresist gets removed from an annular area extending inwards from the perimeter. The edge bead is then removed using a liquid etchant and integrated circuit processing can now proceed, making use of the unexposed, undeveloped layer of photoresist in the usual way; that is, exposing it through a mask and then developing and baking it before using it as an etch mask. The method is general and may be used in other situations where selective removal of photoresist along the periphery is required and where the remaining resist is to be used for other purposes.

(1) FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits, more particularly to the improved use of spin on glass.
(2) DESCRIPTION OF THE PRIOR ART
It is common practice to apply, to the surface of an integrated circuit, a layer of a spin on glass (SOG). As the name implies, a spin on glass is applied to the surface of the integrated circuit in liquid form, most commonly by spin coating. After drying, this coating is heated in an oxidizing atmosphere as a result of which it is converted into a glassy layer. Since it was originally applied as a liquid, this layer will have a planar upper surface; that is, the integrated circuit will be planarized. Additional steps in the manufacture of the integrated circuit, such as etching, can now proceed.
One problem associated with this method of planarization is that, during the application of the SOG, a thickened region, or edge bead, tends to form near the periphery of the wafer. This is a consequence of the fact that the SOG is applied in droplet form at the axis of the spinning wafer and then spreads out because of centrifugal force. A "SOG hump" is induced as a result of the top and edge rinse (in isopropyl alcohol or similar solvent) that is applied during the SOG coating process.
The above-mentioned SOG edge bead is undesirable for several reasons: During subsequent processing steps, such as plasma etching where the wafer is held in place by a set of tight fitting claws, the edge bead tends to act as a source of dust. The edge bead introduces stress into the SOG layer which, in turn, leads to the propagation of defects into the semiconductor layers immediately beneath it. Last, but not least, the presence of the bead defeats one of the main purposes of SOG application, namely planarization.
For all of these reasons it is common practice to remove the edge bead as part of the total process. A straightforward, but relatively expensive, way of achieving this is to provide a photoresist mask that protects the center of the wafer and to then remove the edge bead by etching in the normal way, following which the resist mask is removed and processing proceeds as normal. In order to avoid this extra masking and etching step a number of novel schemes for the direct removal of edge beads have been described in the prior art. For example, Koze et al. (U.S. Pat. No. 5,425,846 June 1995) stack multiple wafers, each of which has a similar edge bead, one on top of another and then subject the stack to a plasma etch. Etching proceeds from the wafers' edges inward and is terminated once the etch front has passed the edge beads.
Cuthbert et al. (U.S. Pat. No. 4,510,176 April 1985) direct a jet of SOG solvent at the wafer's periphery while the wafer is spinning. Care is taken to ensure that debris resulting from the SOG removal does not contaminate the wafer.
The approach of Brewer (U.S. Pat. No. 4,732,785 March 1988) is similar to that of Cuthbert et al. but is modified in that multiple treatments (of solvent) are given to the edge bead while at the same time the speed of rotation is gradually reduced.
Tanigawa et al. (U.S. Pat. No. 5,328,871 July 1994) remove the edge bead after the SOG has been applied to the wafer but before it has been processed into a glass. Under these conditions it is easier to remove. This is done using a jet of solvent directed at the spinning wafer at a point just inside the wafer's periphery.

Process for wafer peripheral edge defect reduction

Taiwan Semiconductor Manufacturing Company Ltd.


A heel support for elevating the heel and bony prominences of a patient's lower limbs in multiple patient orientations. The heel support includes a plurality of apertures for floating the ankles and bony prominences when the patient is positioned on her side. The heel support additionally includes one or more edge contours for floating the heel and boney prominences of the foot when the patient is positioned on her back. The heel support has a size and shape which makes it comfortable to the patient whether the patient is on her back or side. The heel support is portable and convenient to manipulate for hospital staff. A washable or disposable cover may be provided.

A common problem facing bedbound people is decubitus ulcers otherwise known as pressure sores. A pressure sore can occur whenever a bony prominence of a person is subjected to unrelieved pressure. This pressure causes reduced circulation and eventual skin breakdown. An ulcer can occur in as little as a few hours if conditions are right. The sore(s) will start with what appears to be a simple bruise, but if pressure is unrelieved, it can lead to a sore that can go deep into the soft tissue, and if not adequately addressed, the pressure will cause the sore to open all the way to the bone.
Persons who are bed bound or chair bound, have compromised skin integrity due to poor health, and/or is desensitized from anesthesia, pain medication or neurological impairment, are prone to pressure ulcers. It is a common occurrence in the hospital setting, especially for those in long term care and those who are subject to long operations in where they are not moving naturally. Hospital management has a strong incentive to prevent such sores and the infections that may arise there from, as they can be costly for all involved.
The most common spots for pressure sores are the heel of the feet and the sacral/coccyx area of the lower back, because these spots are difficult to support without pressure and there is only a thin layer of skin over these bony prominences. To minimize the pressure to the lower back, the care giver must shift the patient frequently by "turning" them from side to side so that they do not stay on any one pressure point for an extended time. As for the feet, the standard of care is to "float" the heels off the surface of the bed by tucking pillows under the persons lower legs so that the heels do not touch anything.
Standard pillows and foam wedges have been used to "float" the heels off the surface of the bed. However the use of standard pillows and known foam wedges to float the heels suffer from a number of problems.
Standard pillows, although soft and malleable making it easy for a care giver to "shape" the pillows so that they can accomplish "floating", are inadequate for the long term because the soft pillows cannot hold the shape the care giver fashioned. Additionally, the pillows tend to slip out of place or "bottom out" under the weight and natural shifting of the patients' movements. Frequently one will find direct pressure from the pillow itself only a few minutes after it had been "shaped" to do the opposite. Thus a standard pillow is not an effective tool to prevent pressure sores of the heel.
Another approach is to use a specially shaped foam wedge to support the lower legs. Foam wedges have an advantage over a soft pillow because the foam material maintains a specific shape, and it will not easily move out of place with shifting of the patient. A number of heel supporting wedges are available and most have a square shape, with a thickness high enough to elevate the heel well above the bed. Some of the foam wedges are shaped with a sloping angle so as to provide support under the knees and thighs.
Although these wedges serve to elevate the feet, often well above the heart, they have a number of shortcomings.
First, these types of wedges are too thick. Although the heel floating wedges available now can accomplish an elevation of the entire lower limb, they are well over 12″ thick. The wedges are so high that the wedge must be removed when the patient is turned to their side, which should occur at least every 2 hours. If the patient were to have a wedge this large under her body when on her side, her lower back/hips would be so twisted as to cause injury.
Another problem with the known foam wedges is the existence of long square edges. There are many patients who are not able to extend their legs to a full straight position due to musculoskeletal malformations, and thus cannot get a thick wedge all the way under their legs. Because of the solid shape of the wedge, if one limb is shorter than the other, only one heel can be floated. Square edges tend to be effective only when the patients' foot is angled at 90 degrees from the edge, which is not always a natural or comfortable position.
Another problem with the known foam wedges is that they address only floating the heels. Even if the patient could tolerate the wedge under the legs while on the side, the bony prominence of the ankles, the lateral and proximal malleolus, and of the feet, the medial and lateral sides of the phalanges, which are also common sites for pressure sores, are subject to pressure unless the entire foot was suspended off the wedge. Floating the entire foot causes a transfer of weight uncomfortable to the ankle joint, putting undue stress on the ankle and subsequent injury.
Another problem with the known foam wedges is that they are too big. Wedges tend to be bulky and cumbersome, making them awkward for a care giver to position, and for a hospital to store when not in use. Many are designed to support the entire lower limb up to the patient's buttocks. They can impede with the care of the patient during cleaning and are susceptible to soiling. Contrary to hospital pillows, they cannot be covered easily with a standard pillow case, so when soiled, they cannot simply remove the pillowcase and throw it in the laundry then wipe it down as they do with pillows. Indeed, a large wedge is difficult and inconvenient to rinse off under a running faucet. These factors are enough to discourage a rushed caregiver to use the known foam wedges.
There have been attempts to address some of the above shortcomings. An example of a foam cushion which addresses some of the above described shortcomings is disclosed in U.S. Pat. No. 6,634,045 to DuDonis and shown in FIG. 1.
However, despite the availability of some of the known pillows and foam wedges, a heel support for floating the heels from the bed in multiple patient orientations and without the above identified problems is still desired.

Heel support for multiple patient orientations


A memory has coding units that are used for allocating any one of redundant lines at a time to any one of first lines on an address basis. Each coding unit has a programmable activation unit. In a first programming state of the activation unit, the associated coding unit, when programmed, allocates a complete redundant line to a complete first line on an address basis. In a second programming state of the activation unit, the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on an address basis.

The invention relates to an integrated memory having a redundancy function.
In addition to the regular word lines and bit lines, integrated memories often have so-called redundant word lines and/or redundant bit lines. If there is a fault on one of the regular word lines or bit lines, this word line or bit line is replaced by the appropriate redundant line on an address basis. Therefore, such a memory can operate without faults.
Published, European Patent Application EP 0 612 074 A1 describes an integrated memory which has redundant columns. In order to allocate one of the redundant columns to a corresponding regular column, which has a plurality of bit lines, on an address basis, the memory has coding units. These can be used independently of block, with the result that, by programming a block address and a column address, each coding unit can be allocated to a redundant column in any memory block. In this way, fewer coding units are required for repairing faults than if each coding unit were allocated to only one particular memory block.
U.S. Pat. No. 4,051,354 describes a memory in which redundant word or bit lines are each subdivided into subregions which, independently of one another, can be allocated to corresponding subregions of the regular bit lines or word lines and replace these on an address basis. In this way, a plurality of faults on different regular bit lines can be repaired using only one redundant bit line, for example.
In U.S. Pat. No. 4,051,356 each subregion of the redundant line has associated coding elements allowing allocation to a regular subregion which is to be replaced. Hence, there is exactly the same number of groups of coding elements as subregions of all the redundant lines.
It is accordingly an object of the invention to provide an integrated memory having a redundancy function that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which the number of coding units necessary for allocation to regular lines on an address basis can be reduced without significantly reducing the reparability of the memory. With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
addressable first lines having subregions;
addressable second lines intersecting said first lines;
memory cells disposed at intersections of the first lines and the second lines;
redundant lines each subdivided into subregions on an address basis for replacing the first lines and intersecting the second lines;
redundant memory cells connected to the redundant lines; and
coding units for allocating any one of the redundant lines at a time to any one of the first lines on the address basis, each of the coding units having a programmable activation unit whose programming state determines if an associated coding unit, when programmed, allocates a complete redundant line to a complete first line on the address basis, and if the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on the address basis.
In the integrated memory according to the invention, each coding unit has an associated programmable activation unit whose programming state affects the operation of the coding unit. In a first programming state of the activation unit, the associated coding unit, when programmed, allocates a complete redundant line to a complete first line on an address basis. In a second programming state of the activation unit, the associated coding unit, when programmed, allocates only one of the subregions of one of the redundant lines to a corresponding subregion of one of the first lines on an address basis.
Thus, the activation unit of each coding unit determines whether, as a result of the programming of the coding unit, either a complete first line is replaced by a complete redundant line or only a subregion of a first line is replaced by a corresponding subregion of one of the redundant lines. Since each coding unit can be allocated to any one of the redundant lines, the invention makes it possible for the coding units to be allocated to the redundant lines or to their subregions in such a way that the existing redundant lines and the existing coding elements are utilized in optimum fashion.
In accordance with an added feature of the invention, the first lines are bit lines and the second lines are word lines. Alternatively, the first lines can be word lines and the second lines are bit lines.
If a plurality of faulty subregions are disposed on a common first line, it may be beneficial for the relevant first line to be replaced completely by a redundant line, for which purpose, according to the invention, only one of the coding units is necessary. In practice, for example, faults on a complete line are relatively frequent. The invention makes it possible to repair such faults by using only one of the coding units. At the same time, the memory according to the invention affords the advantage that subregions, too, of the redundant lines can be used on an individual basis to repair corresponding subregions of the regular first lines by allocating one of the coding units at a time. This permits faulty subregions of a plurality of the first lines to be repaired using a plurality of subregions of only one of the redundant lines. Therefore, in the first instance, the number of redundant lines in the memory according to the invention can be kept small in comparison with memories in which only complete lines can be replaced. In the second instance, the number of coding units can also be kept relatively small in comparison with a memory in which each subregion of the redundant lines has a respective coding unit permanently associated with it, as is the case, for example, in U.S. Pat. No. 4,051,354, mentioned in the introduction. Since fewer redundant lines and/or coding units need to be provided for repairing faults in the memory according to the invention than in known memories, the memory according to the invention has a lower space requirement than known memories. This is because each additionally required redundant line and each additionally required coding unit increases the area required for producing the memory.
By way of example, the first lines can be bit lines and the redundant lines can be redundant bit lines. However, the first lines can also be word lines and the redundant lines can be redundant word lines. In other illustrative embodiments of the invention, each coding unit can also be used, by way of example, to allocate an appropriate redundant column to a regular column containing a plurality of bit lines.
In accordance with one development of the invention, the coding units of the integrated memory have, among other things, third subunits, which, when programmed, allocate the associated coding unit to a particular subregion of the redundant line associated with it via a first subunit and of the first line associated with it via a second subunit. The programming state of the third subunits is evaluated only if the activation unit associated with the respective coding unit has an appropriate programming state. This distinguishes whether the respective coding unit is allocating the associated redundant line to the associated first line completely or whether this is the case only for a subregion.
In accordance with one development of the invention, the subregions of the redundant lines and first lines are distinguished using a subaddress derived from second addresses, in which case the second addresses are used to address second lines intersecting the first lines. The memory cells of the memory are disposed at the intersections. If the respective coding unit is allocated to a complete redundant line, the subaddresses derived from the second addresses are not taken into account. However, if the coding unit is allocated to only a subregion of one of the redundant lines, this subregion is identified using the subaddresses derived from the second addresses.
In accordance with an additional feature of the invention, the coding units each have a first, a second and a third programmable subunit. The first programmable subunit when programmed allocates the associated coding unit to a particular one of the redundant lines. The second programmable subunit when programmed allocates the associated coding unit to a particular one of the first lines which is to be replaced on the address basis by a redundant line associated with the associated coding unit via the first programmable subunit. The third programmable subunit when programmed allocates the associated coding unit to a particular subregion of the redundant line associated with it via the first programmable subunit and of a first line associated with it via the second programmable subunit. And a programming state of the third programmable subunit is evaluated only if the programmable activation unit associated with the associated coding unit has an appropriate programming state.
In accordance with another feature of the invention, the first lines are addressed using first addresses and the second lines are addressed using second addresses. The coding units each have a first and a second comparison unit. The first comparison unit is supplied with the first addresses and with an address stored by the second programmable subunit and outputs a first result signal. The second comparison unit is supplied with subaddresses derived from the second addresses and with an address stored by the third programmable subunit and outputs a second result signal. The programmable activation unit has a first programming state in which the redundant line associated with the associated coding unit is activated on a basis of the first result signal output from the first comparison unit, but not from the second comparison unit. The programmable activation unit further has a second programming state in which the redundant line associated with the associated coding unit is activated on a basis of the first result signal and the second result signal from the first comparison unit and the second comparison unit, respectively.
In accordance with a concomitant feature of the invention, the number of the coding units is smaller than the number of the subregions of all of the redundant lines.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a redundancy function, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

Integrated memory having a redundancy function


A semiconductor system for voltage limitation includes a first cover electrode, a highly p-doped semiconductor layer that is connected to the first cover electrode, a slightly n-doped semiconductor layer that is connected to the highly p-doped semiconductor layer and a second cover electrode. At least one p-doped semiconductor layer and two highly n-doped semiconductor layers are provided next to one another in an alternating sequence between the slightly n-doped semiconductor layer and the second cover electrode.

The use of semiconductor diodes for voltage limitation is conventional. Such a conventional semiconductor diode is shown in FIG. 1. This semiconductor diode is a pn diode, a p-doped layer 2 having been diffused into a homogeneously n-doped region 1. In order to reduce the bulk resistance and to improve the ohmic connection of the n-type semiconductor to the metal plating, n-doped region 1is highly n-doped from the back of the wafer as an n+ doping (region 3). Reference numerals 4 and 5 denote metal layers. If a reverse voltage US is applied to such a diode, the current increases strongly as soon as breakdown voltage UZ is exceeded. The cause of the current increase and accordingly of the voltage limitation is based on the onset of the avalanche effect. When a reverse voltage is applied, a space charge region forms at the pn boundary surface. From a specific electrical field strength Ecrit of approximately 2·105 through 4·105 V/cm, charge carriers in the space charge region are accelerated so strongly that when they strike the crystal lattice, they break open bonds of the semiconductor and thus produce additional electrons and holes, which for their part are accelerated and are able to break open additional bonds. As a result, the current increases steeply.
A disadvantage of such diodes is that the breakdown voltage increases as the temperature rises. It possesses a positive temperature coefficient TK. If such a diode is briefly operated at high currents in breakdown, the power occurring as heat, the product of breakdown current IZ and breakdown voltage UZ may be very high. In diodes used in motor vehicle generators for rectification, powers in the range of several kilowatts occur during load-dump operation. As a consequence, the diode heats up and breakdown voltage UZ rises strongly. This is disadvantageous for many applications. For example, the maximum acceptable voltage in future 42-V electrical systems is only 58 V. Because the generator voltage in such systems may rise to 48 V, the temperature coefficient of the breakdown voltage must be negligibly small. In this connection, it should be noted that in addition to the influence of temperature on the breakdown voltage, it is also necessary to consider the bulk resistance and manufacturing tolerances.

Semiconductor system for voltage limitation


A frequency calibration method applicable in a Universal Serial Bus device includes: plugging the Universal Serial Bus device to a Universal Serial Bus host; using the Universal Serial Bus device to receive a polling low frequency periodic signal generated from the Universal Serial Bus host; determining a host type of the Universal Serial Bus host according to the polling low frequency periodic signal; and calibrating a programmable oscillator of the USB device according to a specific clock period corresponding to the host type, to make the programmable oscillator generate a target oscillating signal having a predetermined frequency.

1. Field of the Invention
The present invention relates to a frequency calibration method applicable in a Universal Serial Bus (USB) device and the related USB device, and more particularly, to a method of utilizing a polling low frequency periodic signal to calibrate an oscillator of a USB device and a related USB device thereof.
2. Description of the Prior Art
With the development in the technical field of the Universal Serial Bus (USB), the latest data transmission interface has been updated to USB 3.0. The maximum data transmission speed of the USB 3.0 reaches 5 Giga bits per second (Gbps). In other words, the operation clock of USB 3.0 device is at least 2.5 GHz. In a traditional design, a precise inductor capacitor oscillator (LC oscillator) is built in a USB 3.0 device, and the LC oscillator oscillates a reference clock having a precise frequency. Next, a signal synthesizer may be utilized to synthesize a 2.5 GHz operation clock. However, an LC oscillator usually occupies a very large chip area, resulting in an increased production cost of the USB 3.0 device. Hence, how to generate a reference clock having a precise frequency with a lower cost has become an important issue to be solved.

Frequency calibration method applicable in universal serial bus device and related universal serial bus device


A wireless communications apparatus includes a wake-up receiver adapted to receive a wake-up signal and an initially powered-off, sleeping wireless communications transceiver. When the wake-up receiver receives the wake-up signal, it can in turn power on the wireless communications transceiver. In another aspect, the invention includes an apparatus for sending a wake-up signal to the wake-up receiver. The wake-up transmitter and the wake-up receiver can communicate via a variety of wireless communications protocols, including the BLUETOOTH™ standard.

Wireless networks may be used to transmit signals from devices that are only activated rarely. For example, a sensor detecting glass-breakage in a security alarm system may only rarely be activated. In such a design, the system may continuously power the sensor and processor to monitor for glass breakage while the associated wireless transceiver may be powered-down to save battery power. Upon detecting glass breakage, the sensor/processor module can power up the associated wireless transceiver and use it to transmit signals associated with the detected event to a central control panel. This works to "wake up" the transceiver from within the device. But how could the control panel query the status of the glass breakage detector since its transmitter is normally in the off state—that is, "wake up" the transceiver from outside the device?
Such a dilemma increases in importance in the case of implanted devices. Consider for example an implanted medical device such as a combination heart monitor/defibrillator that is implanted in a person's body. In like manner to the previous example, the heart monitor could "wake up" a powered-down associated transceiver upon detecting a dangerous heart condition or a heart attack. But how could a medical professional access the heart monitor when the transceiver is in the powered-down state?
In the art are known systems to manage the power condition of the transceiver and yet make it available to receive external requests. For example, the transceiver may power up on a schedule and check for messages. The schedule may be synchronized with the associated network or it may be intrinsic only to the transceiver itself. This scheduling approach allows the transceiver to be shut down most of the time and so conserve precious battery power. There are at least two problems with this method. First, the transceiver is still being powered-up; using what is often critical battery power. Indeed, in some transceiver systems, the receiving component draws more power than the transmitting component. Second, some wireless networks require acquisition time for the network to synchronize, handshake, verify security protocols, etc. This can be a time consuming and by correlation, a power consuming process. For many devices that may be associated with wireless networks, this is an unacceptable solution because the power draw cannot be supported.
U.S. Pat. Nos. 5,115,236, 5,553,058, and 5,973,611 show the use of signals to remotely wake up a receiver. U.S. Pat. Nos. 3,145,380 and 4,963,887 show the use of transmitted radio frequency energy to provide energy to a responder system.
What is needed in the art is a system to activate a transceiver, such system requiring little or no power draw of its own. In addition, it is preferable that the activation signal be transmitted on a network (i.e., frequency or data communications protocol) distinct from the primary network used by the receiver to be activated.


The disclosure discloses a GOA circuit and a liquid crystal display. The GOA circuit comprises a plurality of GOA units, each sequentially charging the Nth-staged horizontal scanning lines and the (N+1)th-staged horizontal scanning lines in the display region. The GOA unit comprises N-staged pull-up control circuits, (N+1)-staged pull-up control circuits, N-staged pull-up circuits, (N+1)-staged pull-up circuits, N-staged pull-down circuits, (N+1)-staged pull-down circuits, and a pull-down holding circuit. The pull-down holding circuit holds the voltage level of the Nth-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the Nth-staged horizontal scanning line is charged, and holds the voltage level of the (N+1)th-staged gate signal point and the Nth-staged horizontal scanning line to the low level after the (N+1)th-staged horizontal scanning line is charged. By way of such configuration, the two-staged GOA units share a common pull-down holding circuit to further reduce the power consumption.

Technical Field
The disclosure is related to the technology field for the liquid crystal display, and more particular to a GOA circuit and a liquid crystal display.
Related Art
Gate Driver on Array, referred as GOA, is a technology that uses the current array manufacture process for the thin film transistor liquid crystal display to fabricate the gate scanning driving signal circuit on the array substrate to achieve the driving approach on the gate by way of scanning line by line.
The current GOA circuit is composed of a pull-up part, a pull-up control part, a transfer part, a pull-down part, a pull-down holding part and a boost part for boosting the voltage. The pull-up part outputs the inputted clock signal to the gate terminal as a driving signal for the display device. The pull-up control part controls turning-on of the pull-up part. The control of the turning-on is usually performed by the signal transmitted from the upper stage GPA circuit. The pull-down circuit pulls down the gate to the low voltage level upon the completion of the output by the gate, i.e. closing the gate signal. The pull-down holding circuit usually holds the gate output signal and the gate signal (usually referred as Q point) of the pull-up part at the turn-off state (that is the set negative voltage level). There are usually two pull-down parts functioning alternatively. The boost part boosts the voltage level of the Q point again. This ensures the normal output for G(N) of the pull-up part.
However, each stage has a pull-down holding part in such design, and there are two parts functioning alternatively. The power consuming is large and is not good for environment protection.

Shenzhen China Star Optoelectronics Technology Co., Ltd


A hammer for a Charpy pendulum, comprising a body including a head and an arm, wherein the arm is equipped with a portion for attachment to an end opposite to that of the head and wherein the head has a general C-shape, with a concave part in which an area of impact is situated. The arm and the head of said body are obtained in a monolithic form by perimetral cutting of a plane plate.

1. Field of the Invention
The present invention relates in general to equipment for impact tests on plastic materials. More precisely, the invention relates to a hammer for a Charpy pendulum. As is known, the Charpy pendulum is a measuring instrument that is basically made up of a supporting structure having a rotating shaft with horizontal axis, fixed to which is a hammer that has the purpose of striking a specimen with a preset energy. The hammer must be designed and built so as to approximate as accurately as possible the behaviour of an ideal pendulum having an equivalent mass concentrated in the point of impact with the specimen.
2. Description of the Related Art
In traditional solutions, the hammer comprises a metal block fixed to the end of a rod that constitutes the arm of the hammer. The traditional solutions derive from the need to position the centre of gravity of the hammer at the point of impact of the head. Traditionally, the arm of the hammer is formed by a relatively thin rod with a weight as small as possible with respect to the weight of the head.
The known solutions involve difficulties from the production standpoint, in particular since they require three different components (the head, the rod, and a device for fixing the rod to the shaft of the pendulum) that must be fixed to one another with high precision.


A cuckoo clock having a scissored extension arm is disclosed. The clock, using the arm, provides an attractive visual display with minimum displacement and shift of center of gravity.

Cuckoo clocks can have a variety of displays and movement mechanisms. Such displays and mechanisms can enhance the ornamental value of the clock. However, adapting a cuckoo clock to have a scissoring extension arm has proven difficult, as operating the arm incurs a substantial reduction in the stored energy of the clock, unwanted shifts in the center of gravity of the clock as a whole, and a mechanical complexity which has proven difficult to solve. Consequently, an improved scissoring extension and actuating mechanisms for cuckoo clocks is desired.

Cuckoo clock having scissoring extension ARM and actuating mechanisms


A distributed code development environment includes baseline code that is logically divided into a plurality of labels, each including a plurality of transactions authored by respective developers. A computer-implemented method for identifying intermittent errors in the baseline and determining whether errors generated by a test of transactions are intermittent or consistent may include steps of providing the baseline code and providing the plurality of transactions, each of the plurality of transactions including code authored by a developer. A selected test may be carried out on a selected one of the plurality of transactions, the selected test generating an error that represents an unsuccessful completion of the selected test. The generated error may then be compared against errors generated by the selected test on other transactions or labels. The generated error may be identified as intermittent with respect to the transaction and spurious in the baseline if a selected number of errors generated by the selected test on the other transactions or labels are identical or similar to the generated error, according to a selected metric.

1. Field of the Invention
Embodiments of the present invention relate to the field of source code management. More particularly, embodiments of the present invention relate to methods and systems for identifying intermittent errors in a distributed source code development environment and related mechanisms to improve developers' efficiency and product quality.
2. Description of the Prior Art and Related Information
It is now common for a number of developers to work on a single set of code. Typically, developers make a copy of all or a portion of the baseline code, shown at 102 in FIG. 1. Changes are made to the copy of the baseline code, which is now termed a transaction, as shown at 106. All transactions (transactions 1-3 being shown in FIG. 1) may be merged into the baseline code 102 when completed. This is typically the manner in which large coding projects incrementally update the baseline code. The baseline code 102, updated by the transactions merged therein over a given interval (e.g., a day) may be called a label. Labels L4 through Ln are shown in FIG. 1. A label may be thought of as a snapshot in time of the baseline code. These labels are in turn the incarnations of the baseline code used to start transactions as explained above. To minimize errors being introduced, developers run tests 108 on their individual transactions before merging the transactions into the baseline code 102. The baseline code 102, in turn, is also tested regularly. Both transactions and labels are tested using many test suites, each of which may include hundreds or thousands of individual tests. Such tests are called regression tests and it is not uncommon for a label to be tested nightly by using more than 100,000 regression tests running on over 1,000 servers. For large and complex code development projects, such testing may be carried out by a farm of hundreds or thousands of computers. The testing may also be carried out using the developers' individual computing power to harness the power of grid computing. This allows many tests to be run simultaneously on many machines.
In a typical scenario, tests are run nightly on both the transactions and the labels (if such labels have been defined, which is not necessary) and when the developers return to the office the next morning, they review the results of the tests that they ran the previous night. The results provide a basis for quality comparison between a transaction shown at 202 and the label used to begin it. The desired goal is to not have transactions adversely affect the quality of the baseline code when they are merged. A success (commonly referred to as a 'suc') returned by a given test means that the code is behaving as expected and has successfully passed the test. An error or a difference (commonly referred to as a 'dif') means that something is broken in the code and that there is a difference between the actual and expected outcome of the test. Difs may be identified by the size of the error text file output by the regression test. Difs may also be identified in many other ways, such as hashes, text string comparisons, for example. The file size is but one of many possible metrics.
There are two scenarios of interest. The first scenario occurs when a developer is working with a single set of code; and the second scenario occurs when a developer is working with two sets of code where one is based on the other. Within the first scenario, the following nomenclature applies: a 'dif' is an error; a 'suc' is a success, a 'consistent dif' is a dif that is consistently reproduced within the code upon testing and an 'intermittent dif'is a dif that sometimes occurs within the code and sometimes does not. Within the second scenario, the relevant information relates to the differences between the two sets of code (e.g., A and B, or the new and the old) and the following nomenclature may be established: a 'new dif' is a dif that occurred when running a test T on B but not on A (or occurred differently on A); a 'spurious dif' is a new dif that is not caused by the code differences between B and A (instead, the dif may have occurred because the error is intermittent in A and therefore in B, or caused by the environment differences, etc), and a 'real dif' is a new dif that is caused by the code differences between B and A. So, if B is a transaction built on top of A, a 'real dif' would be a dif introduced by the transaction.
Intermittent problems are significant problem: they are the hardest to solve, and so tend to account for many of the errors in the baseline. Intermittent difs encountered in testing a transaction may be caused by errors in the transaction code or in the baseline code. Further, intermittent difs may also be caused by factors that are external to and independent of the code. Such factors generally relate to the prevailing conditions within the environment (e.g. server, server farm, grid computing network) when the regression tests are run. These prevailing conditions may include noise, disk full conditions, timeouts caused by a lack of sufficient CPU cycles, to name only a few examples. Not only are intermittent difs difficult to solve, but they are also difficult to identify. For example, a developer may run a test on a transaction over and over again, to determine whether a dif re-occurs each time the test is run or whether it re-occurs not at all or only a limited number of times. There are, however, several problems associated with this code development scheme. For example, the time required to run the large numbers of test suites on a transaction is often longer than the time necessary to make the code changes. When a new dif is identified, as shown at step S11, the cause may be faulty code within the transaction, an intermittent problem with the transaction or label, an intermittent problem with the test, or a problem with the difference between the baseline run and a transaction run, as they may not be treated identically by the testing mechanism—for example, a transaction may include debugging data in the code, which the baseline lacks. The developer may examine each such error (which takes a large amount of time), or, more likely, rerun the failing tests as shown at S12 in the hope that the failed test will now succeed (match the results of the baseline label run). Re-running the test can be wasteful of both time and computing resources and may cause delays not only in the merging the transaction into the baseline code if there are no problems found, but also will cause delays in the resolution of real difs (errors introduced by the transaction) due to the delay of identifying them as real. If the dif is not re-observed upon repeating the test or if the dif is only re-observed a small number of times as shown at S13, the dif may be characterized as being intermittent in nature, and thus classified as spurious. Alternatively, it may be determined that the dif is consistent and the developer should review and debug his or her code, as indicated at S16. If, after running the regression test multiple times, it is determined that the dif is spurious in nature as shown at S14, the transaction with the spurious dif may be merged into the baseline code as shown at S15, with the expectation that the transaction's code changes are not faulty, but rather that either the baseline code or the environment is the cause of the dif. However, running these transaction and/or label tests over and over again is wasteful in both time and computing resources, as the underlying transaction could have been merged into the baseline code much earlier. In turn, the developer could have pushed ahead with code development, instead of wasting valuable time and computing resources determining whether the difs are real or spurious. Further, this approach will cause the developer to ignore an intermittent dif introduced by his or her transaction, thereby introducing an error into the baseline code. Alternatively, instead of running the regression tests over and over again, the developer may choose to examine the transaction code manually in an attempt to determine whether the difs are related to the code changes or instead are related to factors external to the transaction code. This, however, can waste a great deal of developer time, as there are commonly dozens or hundreds of difs to be examined.
The baseline code, moreover, has its own errors that must be resolved. The mechanism for finding such errors is generally based on a single run of every test for each new label of the baseline. This does not address intermittent errors, which are frequently discovered long after the error was introduced, when a run happens to encounter the problem. At that point, finding the cause and assigning the error is difficult.
Conventionally, there is no well defined way of dealing with intermittent difs when they are encountered in a label of the baseline code. Because such errors are not encountered in every label, it is normally impossible to tell which transaction introduced the error, and a judgment call must be made as to which developer to task with the resolution of the dif. This makes resolution of the problem extremely difficult for the developers, as there is no way to tell which code changes are related to the error. Because of the time it takes to find, assign, and resolve such issues, intermittent difs may persist in the baseline for months at a time. The baseline code is tested a limited number of times and such limited testing may overlook intermittent difs for a long time, and subsequently the errors take a long time to fix.
From the foregoing, it may be appreciated that there is a need for improved methods and systems for identifying intermittent difs so as to be able to ignore spurious difs encountered in transaction testing and resolve intermittent errors in the baseline code. Preferably, such methods and systems should make this determination in a manner that is economical in terms of both time and computing resources, and that allow developers to spend more of their time developing code and less of it testing and characterizing difs generated by testing suites.

Methods and systems for identifying intermittent errors in a distributed code development environment


Provided is a wireless communication apparatus wherein when a wireless communication having high directivity is performed together with another wireless communication apparatus, the user can clearly recognize a communicatable range of the wireless communication. In this apparatus, a periphery image capturing unit (110) captures a periphery image through the optical system in such a manner that the line-of-sight of wireless communication for establishing a wireless communication having high directivity is coincident with the optical axis of the optical system. A preview display unit (120) displays, in a preview window, another wireless communication apparatus image-captured as a periphery image. A communication establishing unit (130) establishes the wireless communication with the other wireless communication apparatus displayed in the preview window.

For example, radio communication apparatuses capable of performing transmission and reception of content data such as moving images and still images with other radio communication apparatuses using radio communication have been widespread. This enables services such as content transfer using Digital Living Network Alliance (DLNA) and video streaming using Wi-Fi display.
With the spread of services described above, a technology has been developed which allows for a radio communication apparatus to select another radio communication apparatus as a communication counterpart.
Patent Literature (hereinafter, abbreviated as "PTL") 1 discloses an example of the above technology. In the technology of PTL 1, a user flicks his or her finger on a touch panel of a radio communication apparatus with his or her finger in a direction of another radio communication apparatus with which the user hopes to communicate as a communication counterpart. This allows the radio communication apparatus operated by the user to establish radio communication with the other radio communication apparatus present in the direction in which the user flicked the finger on the touch panel. In other words, according to the technology of PTL 1, the user can select another radio communication apparatus as a communication counterpart by performing an intuitive operation, namely, flicking a finger.

Wireless communication apparatus, wireless communication method, and wireless communication control program

PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.


A flat display panel and a flat display device are realized in which sealing layers can sufficiently alleviate and absorb strain stress between two substrates which is caused by internal stress of the substrates during sealing process and after cooling process, and which can cancel out disadvantages of an amorphous glass paste and a crystallized glass paste, and a flat display panel manufacturing method is realized which can prevent application of excessive or insufficient pressure to the sealing layers. In a flat display panel formed with at least two substrates (1A) and (1B) sealed together, sealing layers (21a) are formed as a stacked structure containing a plurality of layers or formed in a region containing a plurality of stripes, so as to obtain a stable seal. The sealing layers (21a) are formed of a crystallized glass paste (2A) and an amorphous glass paste (2B). A pressing force applied in the sealing process is positioned near the sealing layers and inside the position of the sealing layers.

1. Field of the Invention
The present invention relates to a flat display panel constructed as a hermetically sealed case, such as a plasma display panel, to a flat display device having the flat display panel, and to a method for forming the flat display panel.
2. Description of the Background Art
FIG. 15 shows the structure of an AC-type plasma display device as an example of a flat display device.
In FIG. 15, the AC-type plasma display device 201 has a plasma display panel 111, a plasma display panel driving circuit 202, address electrodes 204, X electrodes 205, and Y electrodes 206. The address electrodes 204, X electrodes 205 and Y electrodes 206 are all plural in number. The electrodes are arranged so that the address electrodes 204 perpendicularly intersect the X and Y electrodes 205 and 206 in a plurality of discharge cells 203 arranged to form a grid in the image display portion 111a of the plasma display panel 111.
The address electrodes 204, X electrodes 205 and Y electrodes 206 are all connected to the plasma display panel driving circuit 202 and supplied with driving voltage from the plasma display panel driving circuit 202.
To obtain a desired image in this AC-type plasma display device 201, first, the plasma display panel driving circuit 202 performs addressing operation. More specifically, for the addressing operation, write voltage is applied between the address electrodes 204 and the Y electrodes 206, for example. This causes write discharge between these electrodes to set discharge cells 203 involved in the display operation. As is well known, this operation is write operation in which wall charge is stored in the dielectric in the plasma display panel of the AC-type plasma display device.
Subsequently, the plasma display panel driving circuit 202 performs discharge sustain operation (display operation). More specifically, for the discharge sustain operation, the discharge cells 203 set by the addressing operation are caused to discharge to present a display. For this purpose, sustain voltage is alternately applied between the X electrodes 205 and the Y electrodes 206. This discharge sustain operation causes discharge between the X electrodes 205 and the Y electrodes 206 in the discharge cells 203, displaying an image in the image display portion 111a.
When given discharge sustain operation ends, the plasma display panel driving circuit 202 performs erasing operation to change the image displayed in the image display portion 111a (operation for eliminating the wall charge). More specifically, erase voltage is applied between the X electrodes 205 and the Y electrodes 206 to eliminate the wall charge.
FIG. 16 shows the structure of a conventional flat display panel 11, e.g. the plasma display panel 111. FIG. 16 is a top view of the flat display panel 11. FIG. 17 is the sectional view taken along the line Bxe2x80x94B of FIG. 16. FIG. 18 is a sectional view of the flat display panel 11 in a stage where it has not yet been heated and processed into the condition shown in FIG. 17.
The flat display panel 11 has two substrates 1A and 1B made of glass etc. and a sealing layer 12 for bonding the substrates 1A and 1B together. In the case of a plasma display panel, for example, the substrates 1A and 1B are a display surface glass substrate and a back glass substrate opposing each other. The sealing layer 12 is arranged near and along the peripheries of the substrates 1A and 1B to keep the image display portion 11a in a hermetic state.
FIG. 16 shows the substrate 1B with a broken line so that the sealing layer 12 can be seen. FIG. 17 shows barrier ribs 13 sectioning individual discharge cells in the plasma display panel as an example of components in the image display portion 11a.
A glass paste is generally used as the material of the sealing layer 12; for example, a thermally soluble material, in which powder of a low-melting-point glass (frit glass) such as PbOxe2x80x94B2O3xe2x80x94SiO2 type glass or PbOxe2x80x94B2O3xe2x80x94ZnO type glass, is mixed into a solvent together with a binder of nitrocellulose or acrylic resin, a filler of ceramics powder for adjusting the thermal expansion coefficient to those of the substrates 1A and 1B, and so forth. In this specification, xe2x80x9cfrit glassxe2x80x9d stands for glass materials having lower melting points than ordinary glass; e.g. a glass material having a melting point around 400xc2x0 C. In a broader sense, it stands for glass materials which melt at lower temperatures than the substrates 1A and 1B.
A common sealing procedure is now described referring to the plasma display panel as an example. (1) First, the sealing layer 12 is formed on the display surface glass substrate or on the back glass substrate (on the substrate 1B in the example of FIG. 18) where internal components like the barrier ribs 13 have been previously formed. (2) Pre-firing is applied to cause desorption of the binder component in the sealing layer 12. (3) Next, positioning is achieved with the display surface glass substrate and the back glass substrate facing each other. (4) The two glass substrates are fixed with a jig like a clip and appropriate pressure is applied to the sealing layer 12. (5) The entire panel is heated. (6) The panel is cooled and the jig or clip is removed. (7) When the sealing is completed, the entire panel is evacuated, while being heated, through an exhaust tube previously attached to the panel, so as to remove impurity gas adsorbed in the panel. (8) A gas for discharge is entrapped (a mixture gas containing Ne, Xe, etc.) when the panel has reached a given temperature. (9) The exhaust tube is sealed.
Generally, the sealing layer 12 is required to satisfy the following conditions: (a) to have such fluidity that it will easily deform and fuse upon application of external pressure at the sealing temperature, (b) to have such rigidity that it will not deform by atmospheric pressure at the evacuating temperature, (c) to have thermal expansion coefficient at the same level as those of the display surface glass substrate and the back glass substrate so that the substrates will not crack during the sealing process and after the cooling process.
To satisfy the conditions above, the sealing layer 12 has generally been formed by using an amorphous glass paste which contains amorphous frit glass or using a crystallized glass paste which contains crystallized frit glass. The amorphous glass paste has superior fluidity and is not very susceptible to temperature condition. The crystallized glass paste, on the other hand, is poor in fluidity, but provides excellent thermal resisting stability after it is sealed.
Whichever glass paste is used, however, the sealing layer cannot sufficiently alleviate and absorb strain stress between the two substrates which is caused by the internal stress of the two substrates while they are being sealed and after they have been cooled. It is therefore difficult to obtain a large quantity of flat display panels with sufficiently ensured hermetic seal; for example, the hermetic seal of the flat display panel may be broken if the flat display device undergoes external force, such as vibrations and impacts, during its assembly or transportation after cooling, which results in lower yield.
Furthermore, the amorphous glass paste has lower softening point than the crystallized glass paste. Therefore, during the exhausting process following the sealing process, it requires that the temperature be set lower than when the crystallized glass paste is used, which may result in insufficient removal of the impurity gas. The temperature must be set lower because the bonded sealing part will otherwise be re-softened with heat during the exhaust and then the dynamic bonding strength will be reduced or the hermetic seal will be broken to cause leakage of the discharge gas.
On the other hand, the crystallized glass paste, having higher softening point than the amorphous glass paste, has to be heated for a longer time period than the amorphous glass paste to cause crystallization. Moreover, when the temperature distribution largely varies during the heating process, parts where the temperature increases slower will melt while being affected by stress (strain) generated in parts which have hardened earlier, because of the characteristic of the material itself that the melting and the hardening by crystallization are completed where the temperature has increased earlier. It is therefore difficult to uniformly bond the entire panel together.
Furthermore, the bonding part is required to maximize the area of the image display portion while minimizing the width of the sealing layer (the area it occupies on the substrates). When the width of the sealing layer is large, the area of the image display portion will be reduced, or the sealing layer may come in contact with the barrier ribs etc. in the image display portion, and then the path of gas cannot be ensured during the exhaust process. Therefore it is also necessary that the sealing layer provide as uniform width as possible after it is heated.
However, when the crystallized glass paste having poor fluidity is used, it is very difficult to set conditions for the application of external force, so that the sealing layer may provide uneven thickness (uneven flattening) after it has been heated.
Moreover, it has not been clearly known where the jig should be located on the two glass substrates in the step (4) in the above-described sealing process, i.e. in the process step where appropriate pressure is applied to the sealing layer 12 with the two glass substrates fixed with a jig.
FIGS. 19 and 20 show examples of the relation between the position where the pressure is applied and the position where the sealing layer 12 forms; the two substrates 1A and 1B are put into a heating furnace while being pressed by external pressure PS.
In FIG. 19, the distance xe2x80x9caxe2x80x9d from the end of the substrate 1A to the position where the pressure PS is applied and the distance xe2x80x9cbxe2x80x9d from the end of the substrate 1A to the center of the formation width of the sealing layer 12 are set in the ratio of a=b. When the distances are set as a=b, unnecessarily large pressure is applied to the sealing layer 12 and the edges of the glass substrates 1A and 1B will be deformed after they are heated. As a result, the sealing layer 12 is formed in a larger width and hence at a smaller distance from the barrier ribs etc. in the image display portion, in which case it is difficult to ensure the path of gas during the exhaust process.
In FIG. 20, the distance xe2x80x9caxe2x80x9d from the end of the substrate 1A to the position of application of the pressure PS and the distance xe2x80x9cbxe2x80x9d from the end of the substrate 1A to the center of the formation width of the sealing layer 12 are set in the ratio of a greater than  greater than b. When the distances are set as a greater than  greater than b, insufficient pressure is applied to the sealing layer 12 and then conditions for bonding the substrates 1A and 1B together cannot be satisfied. If the worst happens, a gap GP may be formed to cause leakage of the discharge gas.
A first aspect of the present invention is directed to a flat display panel comprising: first and second substrates; and a plurality of sealing layers which adjoin each other, wherein the first and second substrates are sealed together with the plurality of sealing layers and the plurality of sealing layers have different thermal expansion coefficients from each other.
Preferably, according to a second aspect, in the flat display panel, the plurality of sealing layers form a stacked structure between the first and second substrates.
Preferably, according to a third aspect, in the flat display panel, the plurality of sealing layers are arranged side by side between the first and second substrates.
Preferably, according to a fourth aspect, in the flat display panel, the plurality of sealing layers are arranged in a line between the first and second substrates.
Preferably, according to a fifth aspect, in the flat display panel, the plurality of sealing layers comprise a first sealing layer comprising a crystallized glass paste and a second sealing layer comprising an amorphous glass paste.
Preferably, according to a sixth aspect, in the flat display panel, the plurality of sealing layers comprise a first sealing layer having a first thermal expansion coefficient, a second sealing layer having a second thermal expansion coefficient which is lower than the first thermal expansion coefficient, and a third sealing layer provided between the first sealing layer and the second sealing layer and having a third thermal expansion coefficient which is lower than the first thermal expansion coefficient and higher than the second thermal expansion coefficient.
Preferably, according to a seventh aspect, in the flat display panel, the plurality of sealing layers comprise a first sealing layer having a first softening point and a second sealing layer having a second softening point which is lower than the first softening point.
Preferably, according to an eighth aspect, in the flat display panel, the plurality of sealing layers further comprise a third sealing layer provided between the first sealing layer and the second sealing layer, the third sealing layer having a third softening point which is lower than the first softening point and higher than the second softening point.
Preferably, according to a ninth aspect, in the flat display panel, irregularities exist at an interface between the plurality of sealing layers.
A tenth aspect of the present invention is directed to a flat display device comprising: the flat display panel of the first aspect and a flat display panel driving circuit for controlling driving of the flat display panel.
An eleventh aspect of the present invention is directed to a flat display panel manufacturing method comprising a process of providing a sealing layer between first and second substrates and sealing the first and second substrates together by externally applying a pressing force to the first and second substrates to press the first and second substrates together, wherein the pressing force applied in the sealing process is positioned near the sealing layer and inside the position of the sealing layer.
According to the first aspect of the present invention, the plurality of sealing layers adjoining each other have different thermal expansion coefficients from each other. The thermal expansion coefficients of the plurality of sealing layers are set approximately equal respectively to those of the first and second substrates, to the extent that the seal between the first and second substrates will not be broken, and the plurality of sealing layers are appropriately arranged between the first and second substrates. Thus the plurality of sealing layers can gradually alleviate and absorb the strain stress between the two substrates which is caused by the internal stress of the first substrate and the internal stress of the second substrate. This provides a flat display panel with a stabler hermetic seal as compared with a flat display panel having only one sealing layer. The flat display panel can thus be kept hermetically sealed even if the flat display device is subjected to external forces, such as vibrations and shocks, during its assembly process or transportation after cooling, for example.
According to the second aspect, the plurality of sealing layers form a stacked structure between the first and second substrates, which can gradually alleviate and absorb the strain stress between the two substrates which is caused especially by internal stress of the first and second substrates directed in their thickness direction.
According to the third aspect, the plurality of sealing layers are arranged side by side between the first and second substrates, which can gradually alleviate and absorb the strain stress between the two substrates which, especially, is caused by internal stress traversing the sealing layers in the surfaces of the first and second substrates.
According to the fourth aspect, the plurality of sealing layers are arranged in a line between the first and second substrates, which can gradually alleviate and absorb the strain stress between the two substrates which, especially, is caused by internal stress directed in the direction of the line in which the sealing layers are disposed on the surfaces of the first and second substrates.
According to the fifth aspect, the plurality of sealing layers include a first sealing layer containing a crystallized glass paste and a second sealing layer containing an amorphous glass paste. It is therefore possible to make full use of advantages of the two pastes while canceling out their disadvantages.
According to the sixth aspect, a third sealing layer having a third thermal expansion coefficient lower than the first thermal expansion coefficient and higher than the second thermal expansion coefficient is provided between the first sealing layer and the second sealing layer. It is therefore possible to more gradually alleviate and absorb the strain stress between the two substrates which is caused by the internal stress of the first substrate and the internal stress of the second substrate. This provides a flat display panel with a stabler hermetic seal.
According to the seventh aspect, the plurality of sealing layers include a first sealing layer having a first softening point and a second sealing layer having a second softening point lower than the first softening point. Therefore, in the cooling process performed during formation of the plurality of sealing layers, the first sealing layer solidifies first and the second sealing layer solidifies later. Accordingly, in the case of the flat display panel of the second aspect, the second sealing layer can alleviate and absorb strain stress between the substrates which the first sealing layer cannot completely alleviate and absorb. Further, in the case of the flat display panel of the third aspect, the first sealing layer will not be re-softened while being heated in the exhausting process, even though the second sealing layer may be re-softened, which enables stable heating exhaust.
According to the eighth aspect, a third sealing layer having a third softening point lower than the first softening point and higher than the second softening point is provided between the first sealing layer and the second sealing layer. Accordingly, in the case of the flat display panel of the second aspect, the third sealing layer can alleviate and absorb strain stress between the two substrates which the first sealing layer cannot completely alleviate and absorb, and the second sealing layer can alleviate and absorb strain stress between the two substrate which the third sealing layer cannot completely alleviate and absorb. Further, in the case of the flat display panel of the third aspect, the first and third sealing layers will not be re-softened while heated in the exhausting process even though the second sealing layer may be re-softened, which enables stable heating exhaust.
According to the ninth aspect, an interface between the plurality of sealing layers have irregularities and therefore stresses of the sealing layers cancel each other at the interface, which suppresses separation between the sealing layers. This provides a flat display panel with a stabler hermetic seal.
The tenth aspect provides a flat display device having the effects of the flat display panel of the first aspect.
According to the eleventh aspect, the position of application of the pressing force applied during the sealing process is set near the sealing layer and inside the position of the sealing layer. This prevents application of excessive pressure to the sealing layer and thereby prevents the width of the sealing layer from being unnecessarily enlarged. It is therefore easy to ensure the passage of the gas exhausted from the cavity between the first and second substrates. This also suppresses application of insufficient pressure to the sealing layer. Therefore gaps are less apt to form between the first and second substrates. Furthermore, the sealing layer can be formed in almost uniform width along the entire periphery, which prevents nonuniform occurrence of the internal stresses. Moreover, the sealing layer occupies smaller area while maximizing the display area, and also provides uniform sealing width after sealed, as is required for bonding. Deformation of the substrate edges and leakage of the discharge gas are least likely to occur when the ratio between the distance from the substrate edge to the pressing force application position and the distance from the substrate edge to the center of the sealing layer formation width is approximately in the range of 2:1 to 10:1.
The present invention has been made to solve the problems explained earlier, and objects of the present invention are to provide a flat display panel and a flat display device in which the sealing layer can sufficiently alleviate and absorb the strain stress between two substrates which is caused by the internal stresses of the substrates during sealing process and after cooling process, and which can cancel out disadvantages of an amorphous glass paste and a crystallized glass paste, and to provide a flat display panel manufacturing method which prevents application of excessive or insufficient force to the sealing layer.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

Flat display panel, flat display device and flat display panel manufacturing method


A new and improved humidifier wick and its method of manufacture are disclosed. The humidifier wick is made from a cellulose foam material that is compressed to a predetermined thickness in a dry condition. A series of air flow openings are formed in such material. As a result, the wick is capable of being expanded to a substantially increased thickness when wet in order to allow air to be drawn through the air flow openings for conveying moisturized air by a power driven fan blade from a humidifier into the atmosphere of a room. The air-flow openings are pre-configured in the humidifier wick, when in its dry condition, in order to allow air to pass into and beyond the air flow openings of the wick when it is wet and expanded. The wick may be used by itself or together with a number of similarly constructed wick elements. The method of forming air flow openings in an endless web of cellulose foam material when in a compressed and dried condition; and cutting the endless web of cellulose foam material into discrete individual humidifier wick segments.

The present invention relates to humidifier wicks, and more particularly, to a dry compressed and wet expandable humidifier wick.
Humidifier wicks are currently constructed from pleated or webbed fibrous material, i.e., a paper-like material, which draws water by capillary attraction into the wick from a water reservoir in a humidifier. When wet, the wick enables moisturized air to be drawn through the wick by a motor driven fan blade in order to discharge the moisturized or humidified air from the humidifier into the atmosphere of a room containing the humidifier. Examples of such fibrous humidifier wicks are shown in U.S. Pat. Nos. 4,822,533; 5,034,162 and 5,110,511.
While the aforementioned fibrous humidifier wicks have readily proven to be a suitable absorbent capillary wicking material, they must be packaged in protective cartons due to their considerable size and also to avoid the possibility of damage since such fibrous material constructed wicks are relatively fragile. As will be appreciated, the protective cartons containing such fibrous material wicks require considerable shipping space as well as retail outlet shelf space.
The present invention relates to a humidifier wick that is made from a material, i.e. cellulose foam material, that can be compressed to a predetermined thickness when in a dry condition, but is capable of expanding to a substantially increased thickness when wet. While a material of this type is known per se, having been used in products such as sponges and the like, they have not been usefully constructed for use as a humidifier wick. In the discussion that follows, it will be seen that the humidifier wick of the present invention provides many advantages not currently available with fibrous material wicks, including reducing the shipping volume and shelf storage space, while also providing an improved and economical process for the manufacturer of such improved humidifier wicks.

Compressible/expandable humidifier wick and method for manufacture


A face conveyor includes a continuous conveyor formed by a conveyor chain with entrainment plates that are connected to chain links and which, when conveying, circulates in an outward run and a return run, each of which are guided in trough portions by trough elements, which are arranged in a row. Guides provided on each trough element include a first guide on a working face side and a second guide at a spacing from a goaf side. The first guide on the working face side is secured on the trough element between the outward run and the return run. The outward run and the return run extend in a laterally offset manner with respect to each other, and the trough portion guiding the entrainment plates in the outward run is open on the working face side.

Face conveyors with entrainment means attached to conveyor chains have been used for decades in underground mining in order to remove material that has been extracted at a working face by means of an extracting machine, for example a shearer loader or an extracting plough, away from the extracting face and then discard it onto a so-called entry conveyor, which can consist, in particular, of a belt conveyor with circulating rubber belts.
A scraper chain conveyor is used as face conveyor for numerous applications in this connection, said scraper chain conveyor being provided with trough portions which are located one above another and in which the conveyor chains with the connected scraper webs as entrainment means circulate. The upper trough portion is then called the upper run and forms the outward run, whilst the lower run forms the return run. In the majority of cases the scrapers are guided with their scraper ends on profiled side profiles of the trough element. A disadvantage of this development is that the broken material has to be conveyed from the extracting machine into the upper outward run, for which purpose attaching a loading ramp to the side cheek of the trough element on the working face side has been proposed, for example in WO 03/091 541 A1, said side cheek being provided with an angular portion over its height.
Scraper chain conveyors are suitable in particular as face conveyors for extraction plants at longwall faces where face lengths of between 100 and in excess of 400 meters predominate and a migratory support system consisting of numerous shield-type support frames is used. The support shields are located side by side in order to keep the excavation area behind a face front open for the extraction machine, and by advancing the support shields in groups or in turn, the support system is displaced as the face front is excavated further with each operating cycle of the machine.
For special applications such as shortwall extracting, which is used, for example, to advance the machine prop unit (cf. DE 1 583 039), or when material is to be conveyed using both runs (DE 914 478), using the two runs not one above the other but essentially side by side is known.

Face conveyor for extraction plants and trough element for said face conveyor


A method of forming a layer of alpha-tantalum on a substrate including the steps of depositing a layer of titanium nitride on a substrate; and depositing a layer of alpha-tantalum on the layer of titanium nitride, wherein the deposition of the alpha-tantalum is carried out at temperatures below about 300° C.

Tantalum (Ta) is a refractory metal having a high melting point, a low electrical resistivity, and which is generally inert at temperatures below about 150° C. Alpha-tantalum (α-Ta) is the bulk equilibrium or stable-phase of tantalum. α-Ta has numerous applications in magnetic thin films devices including magnetic disk hard drives, and as diffusion barriers in integrated circuits fabrication where copper interconnect technology is used. Because of its numerous uses, there remains a need for methods of forming α-Ta.

Methods of forming layers of alpha-tantalum


Described herein are systems, methods and devices for implementing a temperature-aware, multi-antenna scheduler that cools mmWave devices by preventing heat buildup via switching or distributing a data stream to other redundant antennas, allowing for dissipation of heat as well as providing reliable connectivity.

The explosive demand for mobile broadband globally has created significant stress on the existing wireless infrastructure. Millimeter-wave (mmWave) has emerged as the core, new technology for the next-generation wireless LAN and cellular standards: IEEE 802.11ad; IEEE 802.11ay; and 5G NR. MmWave systems are the key enabler for applications that demand multiple Gbps throughput and ultra-low latency connectivity including immersive virtual and mixed reality, tactile internet, telesurgery, control for smart infrastructures, and autonomous vehicle safety. MmWave systems achieve these capabilities by operating at a very high frequency and ultra-wide bandwidth, on the order of multiple GHz.
Such a high operational regime, however, brings unique challenges: Compared to the micro-wave devices, like Wi-Fi, the mmWave devices consume more energy, dissipate more power, and, subsequently, heat up faster. Increase in device temperature not only affects the hardware, but also is disconcerting to the users, especially when devices are small, hand-held, body-worn, and near the face and brain. Device overheating is a common concern of many users, and mmWave would exacerbate the problem further. Thus, investigating ways to mitigate thermal inefficiencies in mmWave devices is of vital importance.
The current disclosure's research shows that preliminary measurements reveal that after only 10 s. of data transfer at 1.9 Gbps bit-rate, the mmWave antenna temperature reaches 68° C.; it reduces the link throughput by 21%, increases the standard deviation of throughput by 6×, and takes 130 s. to dissipate the heat completely.
While existing research and products have characterized and solved challenges in mmWave channel, link, network, and applications, none have looked at minimizing the system-level temperature of active mmWave antennas. Accordingly, it is an object of the present disclosure to provide devices, systems and methods for mitigating thermal inefficiencies in mmWave devices.
Citation or identification of any document in this application is not an admission that such a document is available as prior art to the present disclosure.

Heat dissipation for millimeter-wave devices with antenna switching


The present invention relates to a battery reverse voltage prevention system, and more particularly, to a battery reverse voltage prevention system, which prevents current of a battery from flowing to a resistor by connecting an additional P-type channel MOSFET to a P-type channel MOSFET gate terminal in the related art in order to prevent opening/closing of a P-type channel MOSFET from being delayed due to a resistor installed to limit capacitance and dark current generated by the P-type channel MOSFET in a battery reverse voltage prevention system in the related art, which includes the P-type channel MOSFET, thereby reducing an opening/closing delay time of the P-type channel MOSFET in the related art.

A fuse which is a device that serves to protect a circuit or a system by cutting off overcurrent is widely used to prevent secondary damage such as circuit protection or fire in most circuits. While an environmental problem has been recently issued due to a concern about an environment, an interest in and a demand for environmentally friendly new renewable energy that can replace fossil fuels, which have a great impact on environmental issues increase. As a result, the need for environmentally friendly new renewable energy sources is increasing.
A secondary battery is one of energy sources that can replace the fossil fuels. The secondary battery is a battery which is semi-permanently used in a manner of charging electricity generated while current supplied from an external power source causes oxidation/reduction reactions of an anode and a cathode.
The secondary battery has a primary advantage that the secondary battery can drastically reduce the use of the fossil fuels and an advantage that no by-product is generated due to the use of energy. Further, unlike a primary battery which is used and wasted once, the secondary battery has an advantage that the secondary battery can be charged several times. Due to the advantages, the secondary battery is used in wide ranges including an electric vehicle (EV), a hybrid vehicle (HV), an energy storage system (ESS) or an uninterruptible power supply (UPS) system using a medium/large battery used for a house or an industry, and the like.
The secondary battery may not be applied when the secondary battery is used in a battery of a portable terminal, or the like requiring a low capacity, but in an environment requiring a high capacity such as the electric vehicle, the energy storage system, and the uninterruptible power supply, a plurality of unit secondary battery cells may be bonded and used.
When the plurality of secondary battery cells is bonded and used in the form of the battery, an abnormal operation such as overcurrent and overvoltage may cause the battery to overheat, resulting in a problem that the unit cell is swollen and damaged. To solve such a problem, it is necessary to measure and monitor various state information such as voltage, current, and temperature of each individual cell and prevent overcharging or overdischarging of the unit cell whenever the plurality of battery cells is bonded and used. In addition, a load needs to be prevented from being damaged by reverse voltage that may occur when an internal circuit of a battery pack is disconnected or damaged due to external environment or abnormal conditions.
In the related art, a diode or a MOSFET is used to protect the load from the reverse voltage of the battery. When the reverse voltage preventing system is constructed using the diode, a voltage drop of the voltage applied to an actual circuit occurs due to forward voltage of the diode occurs, which makes it difficult to operate in a circuit using low voltage. In addition, when the reverse voltage of the battery is prevented by using the MOSFET, the problem of the voltage drop is improved compared to the diode. However, in a case where the reverse voltage is momentarily applied in a normal situation, there is a problem in that the opening/closing of the MOSFET is delayed due to the resistor connected to prevent the capacitance and the dark current generated in the MOSFET, and as a result, the reverse voltage cannot be instantaneously blocked.
Therefore, it is necessary to protect the load from the reverse voltage of the battery more safely by blocking the reverse voltage which is instantaneously generated without delaying the opening/closing of the MOSFET in the reverse voltage preventing system using the MOSFET.

Battery reverse voltage prevention system and method


In an ultrasound system and method, a transducer connects to an estimator for obtaining first and second blood flow parameters associated with first and second scan line directions, respectively, in a first scan plane. One beam substantially covering a cross-sectional area of a tubular structure (uniform insonification) or a plurality of beams may be used. A first area associated with the cross-section of the tubular structure is also estimated from the blood flow parameters. The process is repeated for a plurality of scan planes. A processor determines the cross-sectional area of the tubular structure perpendicular to its axis (a second area), the average velocity of flow parallel to the axis, and the volume flow as a function of the first area and the first and second blood flow parameters of all the scan planes. For real-time volume flow, the orientation of the tubular structure is determined using the second area and the first and second blood flow parameters. As measurements are made, the orientation information is used to derive the real-time volume flow.

This invention relates in general to ultrasound systems, and in particular to an ultrasound system for measuring fluid flow.
Volume flow measurements may be important for various medical diagnosis. Volume flow indicates blockage in blood vessels and the performance of diseased or transplanted organs. For example, changes in the blood flow out of a kidney over time may be determined. Other examples of clinical application of volume flow measurements include: blood flow through shunts, blood flow to or from transplanted or diseased organs, umbilical cord and uterine artery flow, flow through various arteries and vessels, the blood flow in the brachial artery before and after artificially induced ischemia, flow through mitral aortic tricuspid and pulmonic valves, and others.
Ultrasound systems have been used to estimate volume flow. For example, a mean velocity estimate for a small sample volume inside a vessel is obtained from spectral Doppler information. An angle of flow is estimated by user input. The user also manually outlines the vessel's cross section to obtain an estimate of area. The mean velocity, area and the appropriate trigonometric function of the Doppler angle are multiplied to obtain a flow estimate. However, the various manual tracings and estimations are laborious and prone to inaccuracies due to human error. Furthermore, obtaining the mean velocity from one sample volume may not accurately represent the true mean velocity across the entire vessel.
In another ultrasound technique for measuring volume flow, a high spatial resolution image is used to measure the flow profile across a vessel. The individual estimates of flow from each volume cell within a vessel are summed together to obtain the total volume flow. However, due to non-ideal ultrasound beam profiles, the information from one volume cell may duplicate, in part, another volume cell. Furthermore, this technique assumes that flow is parallel to the vessel or requires user estimation of the flow angle.
In yet another ultrasound technique to obtain volume flow, the velocity profile across a vessel is assumed to correspond to a particular function, such as a parabolic or plug profile. A single velocity estimate is obtained at the center of the vessel and used to estimate volume flow. The area of the vessel is calculated either manually or assumed to be circular. However, the area measurement is prone to human or estimation errors, and the actual flow profiles of fluids within a vessel may not match the parabolic or plug functions. Furthermore, as discussed above, the flow angle is manually entered, making the volume flow calculation laborious and error prone.
In yet another ultrasound technique for measuring volume flow, a cross section of a vessel located within a sample volume is insonified using a C-scan. Thus, ultrasound information is obtained from a plane parallel to the face of the transducer. In order to obtain the C-scans information, a fixed two-element transducer or a two-dimensional array transducer is used. The first moment of the C-scan information is calculated, eliminating the need to measure the area of the vessel. Measuring data in a plane parallel to the face of the transducer also eliminates the need to measure the flow direction. However, this technique does not accurately estimate volume flow in vessels that run parallel to the face of the transducer. Additionally, specialized transducers are required.

Ultrasonic system and method for measurement of fluid flow