A center machine for producing corrugated fins for heat exchangers has servomotor driven pullout rolls for stretching a compressed corrugated strip to desired fin density and normally driven in phase with corrugation forming rolls. A cutoff knife severs parts from the strip and a sensor measures the length of each part. A control determines part length error, calculates servomotor speed adjustment needed to nearly correct the error and causes such a speed adjustment for a short period to alter the phase of the pullout rolls relative to the forming rolls.

Automotive radiators and other heat exchangers have a series of parallel flat tubes carrying a hot fluid, such as engine coolant, for transfer of heat to a cooler medium, such as air, which flows around the tubes. To improve heat transfer rate, sinuous or corrugated metal strips called fins or air centers are inserted in the spaces between the flat tubes and soldered or brazed at the junction of the peaks of the air centers and the tubes to assure good heat conductivity from the tubes to the fins. The tubes are assembled in the radiator at fixed spacings and the air centers then must be manufactured to fit in the spacing. Different products may have different heat transfer requirements and thus require centers with different fin spacings or lengths. It is desirable to reliably provide an accurate part length having a preset number of convolutions per part.
It is known to make corrugated fins from sheet stock in a machine with forming rolls for producing a set number of corrugations peaks or convolutions per unit length of strip stock, stuffing rolls to stuff or pack the fins such that the convolutions are touching, then feeding the fins by metering rolls and stretching out the fins by pullout rolls until the desired pitch is obtained. The number of teeth in the pullout rolls and the tooth form determines the nominal fin spacing or density. The corrugated material is stretched between the metering rolls and the pullout rolls during machine set up to achieve substantially the correct fin pitch or density, and to operate the rolls in phase so that the pitch remains the same. The fin is cut into pieces having equal numbers of corrugations so that the part length is then determined by the pitch. It is also known to drive the pullout rolls by a servomotor and to make adjustment of the phase of the pullout rolls through servomotor control to change fin pitch during operation for correction of part length. This is accomplished by detecting whether a cut part is too long or too short and adjusting the phase by a preset increment to make a gross change in the size of the next part without consideration of the amount of deviation of the part length from a target value.

Method of controlling the length of corrugated fins


A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

The present invention relates to a semiconductor memory device including a number of data input/output terminals, and more particularly, to a data input/output sensing circuit for controlling a data input/output line functioning as a data bus line within a memory chip.
Generally, semiconductor memory devices include a number of data input/output lines (hereinafter referred to as DIO lines) as internal data bus lines inputting and outputting data to/from the exterior of the memory chip device. There are two types of DIO lines. One is DIO lines used in pairs and the other is the use of single DIO lines.
When using DIO lines in pairs, logic circuits as shown in FIG. 1 through FIG. 4 are used. In this case, the number of the DIO lines is twice the number of data input/output terminals (hereinafter referred to as a DQ terminal) and usually the DIO lines have been precharged to a logic "high" state.
FIG. 1 is a circuit diagram illustrating the structure of a reading driving circuit which connects data read out from a memory cell array and provided on the input/output lines IO and IOB of the memory cell to the DIO lines DIO and DIOB. FIG. 2 is a circuit diagram illustrating the structure of an output driving circuit which outputs data provided to the DIO lines DIO and DIOB through the DQ terminal DQ. The input/output line IOB is complementary to the input/output line IO, and similarly the DIO line DIOB is complementary to the data input/output line DIO.
In FIG. 1, the DIO lines DIO and DIOB are precharged with a precharge signal PRECH of the logic "low" state. Assuming that data read out from the memory cell transmitted along the input/output line IO at the logic "high" state and to the input/output line IOB at the logic "low" state, it is then input to an I/O sense-amplifier 102. If an input/output sensing enable signal IOSE is enabled to the logic "high" state, MOS field effect transistors MOSFETs 114 and 122 are turned ON and MOSFETs 116 and 120 are turned OFF, thereby continuously maintaining the line DIO at the logic "high" state and changing the line DIOB, previously precharged to the logic "high" state, to the logic "low" state. Signals on the DIO lines DIO and DIOB are respectively applied to the lines in FIG. 2, and accordingly, the line DIO of FIG. 2 goes to the logic "high" state and the line DIOB goes to the logic "low" state. Then, if a read data transmitting pulse RDTP is enabled to the logic "high" state, a MOSFET 208 is turned ON and a MOSFET 210 is turned OFF according to the logic state of the DIO lines DIO and DIOB. Consequently, data output buffer 212 outputs data of the logic "high" state through the DQ terminal to the exterior of the memory device.
FIG. 3 is a circuit diagram illustrating the structure of an input driving circuit which connects data input through the DQ terminal DQ from the exterior of the memory device to the DIO lines DIO and DIOB. FIG. 4 is a circuit diagram illustrating the structure of a writing driving circuit which applies data provided in the DIO lines DIO and DIOB to the I/O lines IO and IOB to thereby write data in the memory cell. Assuming that DQ terminal is logic "high" state, in FIG. 3, if a writing data transmitting pulse WDTP is enabled to the logic "high" state, MOSFETs 308 and 316 are turned ON and MOSFETs 310 and 341 are turned OFF, so that the line DIO goes to the logic "high" state and DIOB to the logic "low" state. Signals of the DIO lines DIO and DIOB are respectively applied to the lines in FIG. 4, and accordingly, the line DIO goes to a logic "high" state and the line DIOB goes to the logic "low" state. Thereafter, if the data transmission control pulse DTCP is enabled to the logic "high" state, the MOSFETs 408 and 416 are turned ON and MOSFETs 410 and 414 are turned OFF according to the logic state of the DIO lines DIO and DIOB. Consequently, the I/O line IO goes to the logic "high" state and the I/O line IOB thereof goes to the logic "low" state, to thus write data having a "high" state in the memory cell.
When using single DIO lines, logic circuits as shown in FIG. 5 to FIG. 8 are used. In this case, the number of DQ terminals is equal to the number of DIO lines.
FIG. 5 is a circuit diagram illustrating the structure of a reading driving circuit which connects data provided in the IO lines IO and IOB of the memory cell to the line DIO. FIG. 6 is a circuit diagram illustrating the structure of an output driving circuit which outputs data provided to the line DIO through the DQ terminal DQ. Assume that data read out from the memory cell is input to the I/O line IO at the logic "high" state and to the I/O line IOB at the logic "low" state. In FIG. 5, if the input/output sensing enable signal IOSE is enabled to the logic "high" state, MOSFET 512 is turned ON and MOSFET 514 is turned OFF, and therefore the line DIO goes to the logic "high" state. Referring to FIG. 6, after the line DIO goes to the logic "high" state, if the read data transmitting pulse RDTP is enabled to the logic "high" state, MOSFET 610 is turned ON and MOSFET 612 is turned OFF. Consequently, data output buffer 614 outputs data of the logic "high" state through the DQ terminal DQ to the exterior of the memory device.
FIG. 7 is a circuit diagram illustrating the structure of the input driving circuit which connects data input through the DQ terminal DQ from the exterior of the memory device to the DIO line DIO. FIG. 8 is a circuit diagram illustrating the structure of the writing driving circuit which applies data provided in the DIO line DIO to the I/O lines IO and IOB to thereby write data in the memory cell. Assuming that the DQ terminal DQ is at the logic "high" state, in FIG. 7, if the writing data transmitting pulse WDTP is enabled to the logic "high" state, MOSFET 710 is turned ON and MOSFET 712 is turned OFF, and therefore the line DIO goes to the logic "high" state. Referring to FIG. 8, after the DIO line DIO goes to the logic "high" state, if the data transmission control pulse DTCP is enabled to the logic "high" state MOSFETs 812 and 818 are turned ON and MOSFETs 814 and 816 are turned OFF. Consequently, the I/O line IO goes to the logic "high" state and the I/O line IOB goes to the logic "low" state to thereby write data at the logic "high" state in the memory cell.
When using DIO lines in pairs, as described above, the number of the DIO line is twice the number of DQ terminals and the DIO lines have to be precharged to the logic "high" state. However, when using a single DIO line, because the DIO line is fully swung, a sense amplifier 502 and a driving FET 512 of FIG. 5 and a driving FET 710 of FIG. 7 have to have a size larger than sense amplifier 102, driving FETs 114 and 120 of FIG. 1 and driving FETs 308 and 314 of FIG. 3, which are used when the pairs of DIO lines are precharged.
However, in the conventional circuits as described above, timing of the DIO line data transmission, a read data transmitting pulse and a data transmission controlling pulse is critical in order to prevent non-effective data from being applied to the I/O lines or DQ terminal and can result in problems. More particularly, when using a single DIO line, since the DIO line is always in the logic "high" state or the logic "low" state, when compared with the case of using the DIO lines in pairs, the read data transmitting pulse RDTP or the data transmission control pulse DTCP has to be enabled after sensing whether or not data of the DIO line is an effective value. If the read data transmitting pulse RDTP or the data transmission control pulse DTCP is enabled prior to the DIO line, non-effective data is provided to the DQ terminal upon reading and to the I/O lines upon writing. This results in generation of speed loss to ensure that effective data is obtained.
However, using pairs of DIO lines also has disadvantages. As the number of the I/O terminals increases, the number of the DIO lines within the chip is increased in proportion to the number of the I/O terminals, thereby causing the layout of the semiconductor memory device to be bulky. Therefore, when using DIO lines in pairs, this results in design problems due to spare occupied on the layout by the pairs of DIO lines.

Data input/output sensing circuit of semiconductor memory device


The invention provides a method of treating a patient infected with hepatitis C virus (HCV) comprising raising the core temperature of the patient and then returning the core temperature of the patient to normal at least one time, wherein the core temperature is raised to a temperature range and a duration sufficient to reduce or eliminate the patient's viral load of HCV.

Injected drug users are the largest group of people with hepatitis C infection. People who received a blood transfusion or kidney transplant before a diagnostic test became available form another large group of those infected.
Since human immunodeficiency virus (HIV) is also common among injected drug users and is transmitted sexually, about forty percent of HIV infected patients are co-infected with HCV. Various types of HIV such as HIV-1 and HIV-2 exist. Hepatitis C virus occurs in six known genotypes and more than fifty subtypes. The hepatitis C virus is harbored in the liver and most people infected with HCV eventually will develop cirrhosis or liver carcinoma. HCV can cause an acute or chronic infection. In chronic infection, the infected person can exhibit signs of chronic hepatitis or be a chronic asymptomatic carrier.
Current treatments for hepatitis C include interferons and other pharmaceuticals. However, because these treatments are not effective for all patients, improved methods for treating hepatitis C are being sought.

This patent is subject to a terminal disclaimer.

Treatment of hepatitis C using hyperthermia


A phase-locked loop (PLL) having a digitally controlled oscillator (DCO), where the DCO receives a digital control signal generated by the PLL and an externally generated oscillator clock signal and generates an output signal having a frequency greater than that of the oscillator clock signal. In one embodiment, the DCO is an analog PLL, such as a fractional-N frequency synthesizer, that receives a two-part digital control signal corresponding to the integer and fractional portions of a desired multiplier. The feedback path within the DCO has a dual-modulus divider that is controlled by a modulus controller to apply, over time, an effective divisor value that achieves the desired degree of multiplication. PLLs of the present invention are especially applicable to low-bandwidth, low-noise applications, such as high-multiplication frequency synthesizers and clock filtering, that are integrated into digital ASICs.

1. Field of the Invention
The present invention relates to electronics, and, in particular, to phase-locked loops.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump: PLL, which is described in Floyd M. Gardner, xe2x80x9cCharge-Pump Phase-Lock Loopsxe2x80x9d IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference.
FIG. 1 shows a block diagram of a conventional charge-pump phase-locked loop 100. Phase detector (PD) 102 compares the phase xcex8IN of the input signal FIN to the phase xcex8OUT of the feedback signal FOUT and generates an error signal: either an UP signal U(when xcex8IN leads xcex8OUT) or a DOWN signal D (when xcex8OUT leads xcex8IN), where the width of the error signal pulse indicates the magnitude of the difference between xcex8IN and xcex8OUT.
Charge pump 104 generates an amount of charge equivalent to the error signal (either U or D) from PD 102. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitors in loop filter 106. For purposes of this explanation, loop filter 106 has a relatively simple design, consisting of a capacitor CS in parallel with the series combination of a resistor R and a relatively large capacitor CL. As such, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage VLF is applied to voltage-controlled oscillator (VCO) 108. A voltage-controlled oscillator is a device that generates a periodic output signal (FOUT in FIG. 1), whose frequency is a function of the VCO input voltage (VLF in FIG. 1). In addition to being the output signal from PLL 100, the VCO output signal FOUT is used as the feedback signal for the closed-loop PLL circuit.
Optional input and feedback dividers 110 and 112 may be are placed in the input and feedback paths, respectively, if the frequency of the output signal FOUT is to be either a fraction or a multiple of the frequency of the input signal FIN. If not, the input and feedback dividers can both be considered to apply factors of 1 to the input and feedback signals, respectively.
Charge-pump PLL 100 of FIG. 1 is an example of an analog PLL, in which VCO 108 is controlled by an analog input signal VLF generated by charge pump 104 and loop filter 106. Digital phase-locked loops are also known.
FIG. 2 shows a block diagram of a conventional digital phase-locked loop 200. PLL 200 is similar to PLF 100 of FIG. 1, except that charge pump 104 and loop filter 106 are replaced by a digital accumulator and filter 204 and voltage-controlled oscillator 108 is replaced by a digitally controlled oscillator (DCO) 208, which receives an externally generated, high-speed clock signal having frequency FHSCK.
In operation, input divider 210, phase detector 202, and feedback divider 212 of PLL 200 operate analogously to input divider 110, phase detector 102, and feedback divider 112 of PLL 100, respectively. Instead of generating an analog voltage control signal, digital accumulator and filter 204 accumulates and filters the UP and DOWN signals generated by PD 202 to generate a digital control signal M, which has a positive integer value. DCO 208 uses the digital control signal M to convert the high-speed clock signal FHSCK into the PLL output signal FOUT according to Equation (1) as follows:
FOUT=FHSCK/M.xe2x80x83xe2x80x83(1)
Since Equation (1) represents a division operation, in a conventional digital PLL, DCO 208 is implemented as a simple digital divider.
One application for PLLs is in frequency synthesizers with high multiplication ratios. For example, it may be desirable to implement a PLL having a multiplication ratio as high as 77,750 in order to convert an input signal FIN having a frequency of 8 kHz into a phase-locked output signal FOUT having a frequency of 622 MHz. In order for the feedback loop of a charge-pump PLL to remain stable, the frequency of the inputs to the phase detector must exceed the PLL closed-loop bandwidth. A typical ratio is 10. This means that, in order to use a charge-pump PLL for the previous example of a high-multiplication frequency synthesizer, the PLL closed-loop bandwidth should be on the order of 0.8 Hz.
Another application for PLLs is in clock filtering. Some clock filtering applications, such as SONET clock filtering, require PLL closed-loop bandwidths as low as 0.1 Hz.
One problem with using charge-pump PLLs in applications such as high-multiplication frequency synthesizers and clock filtering that have low closed-loop bandwidths, relates to noise. Charge-pump PLLs do not provide a large amount of cancellation of intrinsic noise generated within the feedback loop. As a result, for low-noise applications, PLL closed-loop bandwidth is usually maximized.
In light of these competing goals, charge-pump PLLs are often not suitable for applications requiring both a high degree of stability and a low amount of noise.
In general, it would be desirable to implement PLLs for applications such as high-multiplication frequency synthesizers and clock filtering, as part of digital ASICs (application-specific integrated circuits). One known way to integrate analog PLLs into digital ASICs is to base the VCO on a ring oscillator. A ring oscillator is a set of delay cells connected head to tail, whose output frequency is controlled by a voltage control signal applied to all of the delay cells. As mentioned before, in order to have low noise, a charge-pump PLL must have a relatively high loop bandwidth in order to allow the PLL feedback loop to cancel (or at least significantly reduce) internally generated noise. This in turn requires that the frequency at the phase detector (i.e., the PD update rate) also be large in order for the PLL to remain stable. However, since PLL applications, such as high-multiplication frequency synthesizers and clock filtering, require relatively low PLL loop bandwidths and the large multiplication value implies a relatively low input frequency for a fixed output frequency, it is impractical to integrate conventional ring-oscillator-based analog PLLs, such as charge-pump PLL 100 of FIG. 1, into digital ASICs for such applications.
It is also impractical to use conventional digital PLLs, such as PLL 200 of FIG. 2, in applications such as high-multiplication frequency synthesizers. Because the digitally controlled oscillator 208 simply divides down the input clock signal FHSCK, in order to accurately generate a PLL output signal FOUT having a frequency as high as 622 MHz, FHSCK must have a frequency much higher than 622 MHz. This may be impractical in many applications. This is even more true for applications that require PLL output signals having frequencies greater than 622 MHz (e.g., as high as 1 GHz or even higher).
The present invention is directed to a PLL design that addresses limitations in the prior art. In particular, PLLs of the present invention can be used in applications such as high-multiplication frequency synthesizers and low-bandwidth clock filtering that are integrated into digital ASICs without having to sacrifice low-noise performance.
In one embodiment, the present invention is an integrated circuit (IC) having a phase-locked loop (PLL), the PLL comprising (a) a phase detector (PD), configured to receive a PLL input signal and a PLL feedback signal and to generate PLL PD signals based on differences in phase between the PLL input and PLL feedback signals; (b) an accumulator/filter, configured to receive the PLL PD signals from the phase detector and to generate a digital control signal; and (c) a digitally controlled oscillator (DCO), configured to:
(1) receive (i) the digital control signal from the accumulator/filter and (ii) an oscillator clock signal; and
(2) to generate an output signal whose frequency is (i) based on the digital control signal and (ii) greater than the frequency of the oscillator clock signal, wherein the PLL feedback signal is generated from the output signal.

Phase-locked loop with digitally controlled, frequency-multiplying oscillator


A cooking utensil is provided which can be stood invertedly upright and stored temporarily in a hygienic manner, without taking up space. The cooking utensil includes a shank portion, a head portion, a supporting member, and a liquid receiving member. The supporting member is formed at an end section of the shank portion and supports the cooking utensil in an inverted upright state with the head portion in an upward position. And the liquid receiving member is formed on the shank portion and/or head portion for receiving liquid adhering to the head portion when the cooking utensil is invertably stood.

The present invention relates to a cooking utensil which can be held in an inverted upright state.
When a cooking utensil, such as a ladle, rice paddle, turner, or the like, is not being used temporarily during cooking, a problem arises in terms of where to place the utensil. For example, if soup in a saucepan is stirred using a ladle and is then to be heated further, the ladle is either left in the pan or it is placed on a worktop, or the like, in the kitchen. However, if the ladle is left inside the pan, then the grip portion of the ladle may become hot due to the heat from the heat source of the burner, or the like, which is transmitted upwards along the outer sides of the pan, and it may become impossible to touch the grip portion of the ladle, or the grip portion may even be melted by the heat. Moreover, if the ladle is left on a worktop in the kitchen, it takes up free space and is liable to roll over due to poor positional seating, and therefore it may interfere with other tasks. Furthermore, since liquid adhering to the bowl portion of the ladle may spill on to the worktop, the worktop is liable to become soiled.
In order to resolve these problems, a ladle has been proposed which comprises a flat portion formed in the base of the bowl portion thereof, in such a manner that the ladle can be stood upright with the bowl portion being in a downward position. This allows the ladle to stand in an upright state in the center of a pan, or to stand in an upright state on top of a worktop, for example. However, standing the ladle in the center of the pan is not suitable in cases where, for example, a lid must be placed on the pan, and furthermore, if the ladle is stood on top of a worktop, then the bowl portion which comes into direct contact with food will touch the surface of the worktop and hence problems of hygiene arise. In order to resolve such problems, it has been proposed that the ladle is used in combination with a ladle receiving dish, whereby the ladle is held upright in the receiving dish, but this increases the number of components and the complexity of the device.
Similar problems also apply to a turner, and the like, although in the case of a utensil having a plate-shaped head portion, such as a turner, or the like, it is not possible to stand the utensil in an upright position as described above.
The present invention was devised with the foregoing problems in view, and aims to provide an invertably standable cooking utensil which occupies reduced space when stood temporarily, and which resolves problems of hygiene by preventing dispersal of liquid adhering to the head portion of the utensil when the utensil is stood in an inverted state with the head portion in an upward position and the grip portion in a downward position.
According to one embodiment of the present invention, an invertably standable cooking utensil is provided which comprises a shank portion, a head portion, a supporting member formed at an end section of the shank portion for holding the cooking utensil in an inverted upright state with the head portion in an upward position, and a liquid receiving member formed on the shank portion.


A scheme for carrying out modular calculations which is capable of carrying out modular calculations using redundant binary calculation even when a number of bits of the mantissa (dividend) is larger than a number of bits of the modulus (divisor). In this scheme, the divisor c in the divisor register is left shifted by (i-j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, and the modular reduction a mod c is calculated up to (i-j)-th decimal place using the dividend a and the left shifted divisor c. Alternatively, the divisor c given in h-ary notation in the divisor register is left shifted by (i-j) digits when a number of digits j of the divisor c is less than a number of digits i that can be stored in the divisor register, while the dividend a given in h-ary notation in the dividend register is left shifted by (k-l) digits when a number of digits l of the dividend a is less than a number of digits k that can be stored in the dividend register, where k.gtoreq.i. Then, the modular reduction a mod c is calculated up to a digit of [(k-l)-(i-j)]-th power of h using the left shifted dividend a and the left shifted divisor c to obtain a remainder, and this remainder is right shifted by (k-l) digits.

1. Field of the Invention
The present invention relates to a scheme for carrying out modular calculations, especially modular exponentiation calculations, which are necessary for basic operations and key generation in public key cryptosystems such as RSA cryptosystem.
2. Description of the Background Art
Basic operations and key generation in public key cryptosystems such as RSA cryptosystem require modular calculations such as modular exponentiation a.sup.b mod c, modular multiplication a.times.b mod c, and modular reduction a mod c. In addition, application protocols utilizing public key cryptosystems often utilize these modular calculations in combination. Consequently one frequently encounters cases where some modular calculation result is to be used in next calculation. In view of this fact, there has been a proposition of a calculation scheme using redundant binary calculation, as disclosed in A. Vandemeulebroecke, et al.: "A New Carry-Free Division Algorithm and its Application to a Single-Chip 1024-b RSA Processor", IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, pp. 748-756, June 1990.
However, this conventional scheme has been associated with the problem that modular exponentiation a.sup.b mod c and modular reduction a mod c cannot be calculated when .vertline.a.vertline.>.vertline.c.vertline.. In the following description, .vertline.k.vertline. will be referred to as a number of bits of k, and a, b and c appearing in modular exponentiation a.sup.b mod c will be referred to as mantissa (dividend), exponent, and modulus (divisor), respectively.
In principle, the redundant binary calculation requires the most significant bit of a divisor in binary expression to be "1" in a case of division, so that there has been a limitation that a number of bits of a divisor of a designed division circuit must coincide with a number of bits of a divisor to be used in calculation.
In this regard, there has been a proposition disclosed in Japanese Patent Application Laid Open No. 8-147266 (1996) for removing this limitation on a number of bits of a modulus by the following provisions.
(1) An entire divisor (modulus) is left shifted until the most significant bit of a divisor (modulus) becomes "1".
(2) An entire dividend (mantissa) is also left shifted as much as a shifting made in (1).
(3) A calculation is carried out by the conventional redundant binary calculation.
(4) A calculation result is right shifted as much as a shifting made in (1) in order to correct the calculation result.
However, since the mantissa is to be right shifted for the same number of bits as the modulus in (2), there has been a problem that an accurate calculation becomes impossible when a number of bits of the mantissa is larger than a number of bits of the modulus because of the overflow.
Under such condition, when an application of this proposition to LSI is considered, there is no problem when the mantissa is set to be smaller than the modulus in advance, but it is rather inconvenient for applications to various application programs. For example, in a case of modular multiplication a.times.b mod c, one usually has a<c and b<c but a product a.times.b becomes larger than c in general so that this calculation cannot be carried out by this proposition.
Now, the modular exponentiation is frequently utilized as basic operations in public key cryptosystems. For example, in RSA cryptosystem, modular exponentiation using a secret exponent is to be carried out in the decryption operation and the signing operation.
Conventionally, almost all public key cryptosystems utilize modular exponentiation, which can be expressed as a.sup.b mod c. In the signing operation or the decryption operation, at least one of the three parameters involved in modular exponentiation is to be kept secret.
However, when three parameters are exactly the same, an identical result will be obtained obviously. On the other hand, in a case of carrying out modular exponentiation using a dedicated processor, an identical calculation result is always obtained when an environment such as operation frequency is constant. Then, there is a report which points out that a secret key can be obtained by utilizing these features, as disclosed in P. C. Kocher: "Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems", Advances in Cryptology--CRYPTO'96, Lecture Notes in Computer Science 1109, pp. 104-113, Springer-Verlag.
This method (called timing attack) is somewhat time consuming and not very easy, but still far easier than a method for deriving a secret key by utilizing mathematical features or a method for carrying out the extensive search of a secret key. This method becomes more dangerous in an environment in which the time can be measured more accurately. Moreover, this method becomes more dangerous when a number of parallel jobs is fewer.
Thus, the secret key calculation utilizing modular exponentiation and the like has the same amount of calculations for exactly the same parameters, and there are cases where this feature can be maliciously utilized to obtain a secret key.

Scheme for carrying out modular calculations based on redundant binary calculation

Nippon Telegraph and Telephone Corporation


Apparatus for continuously producing semiconductor films on substrates in a vacuum chamber. A plurality of reaction chambers are provided within the vacuum chamber, substrates are supported by a top plate and transferred to each reaction chamber, which are filled with a certain reactant gas mixture while the substrates are heated from above the reaction chamber. Continuous treatment of the substrates is provided with an increase in reactant gas utilization efficiency. Disturbance of reactant gas flow by thermal convection is prevented and semiconductor layers having smooth surfaces are formed.

In recent years, the demand for compound semiconductors, especially Group III-V compounds (e.g. GaAs), has been growing because of their superior performance characteristics compared to the conventional silicon semiconductors. For the production of such compound semiconductors, there are known, among others, (a) the so-called molecular beam epitaxy (MBE) process which comprises causing atoms, required for a compound to be epitaxially grown, to evaporate from a solid material using a heat gun and causing them to collide, in the molecular beam form, against a substrate in an ultrahigh vacuum to thereby cause growth of a film of said material on said substrate, and (b) the so-called metal organic chemical vapor deposition (MOCVD) process which comprises introducing the vapor of a methyl-metal or ethyl-metal compound into a reaction chamber at atmospheric pressure or under reduced pressure by means of a carrier gas such as H.sub.2, allowing said vapor to mix with a Group V metal hydride and allowing the reaction therebetween to take place on a heated substrate for crystal growth.
However, the MBE process has a problem in that it is not suited for large-scale production, hence can hardly meet the needs of the market. The MOCVD process also has a problem in that the reactant gases are expensive and because of the growth mechanism, the efficiency of utilization of reactant gases is low, although the process is higher in production capacity than the above-mentioned MBE process. It is therefore difficult to use the MOCVD process for the production of semiconductors for use in fields other than some special fields where high costs do not matter. Furthermore, since a large quantity of unreacted gas, which is toxic, is produced because the efficiency of reactant gas utilization is low, as mentioned above, and since a carrier gas is used for gasifying and carrying the Group III compound, which has a low vapor pressure, and this constitutes an additional waste gas portion, a toxic waste gas is discharged in large quantities, and this fact leads to waste gas disposal problems. An apparatus so far in use for such a MOCVD process can be schematically illustrated by FIG. 11. Thus, a substrate 3 is mounted on a heater 2 disposed in a vacuum chamber 1, and a gaseous compound mixture for semiconductor deposition is fed toward the substrate 3, in the direction indicated by the arrows A, from a nozzle 4 disposed in the upper part of the vacuum chamber 1. In such an apparatus, the vacuum chamber 1, which has a large capacity, is filled with a gaseous compound (reactant gas) mixture for each treatment run and after treatment, the gaseous compound mixture is discharged as a waste gas. The waste gas contains unreacted gases, which have not been involved in semiconductor deposition, in large quantities and, accordingly, the reactant gas utilization efficiency is low. In the above-mentioned apparatus, the substrate 3 is placed on the heater 2 and heated from the under surface. Thermal convection thus takes place over the substrate, as shown by the arrows B, and heat is dissipated from the substrate 3 heated by the heater 2 to the vicinity of the upper surface of the substrate 3, as shown by the arrows C. As a result, the flow of the gaseous compound mixture fed from the nozzle 4 is disturbed by the forcing-up effect of the above-mentioned thermal convection current (arrows B) and heat dissipated (arrows C), so that uniform film growth on the upper surface of the substrate 3 cannot take place any longer. Therefore, it is a serious disadvantage of the apparatus mentioned above that the semiconductor films produced (semiconductor layers) do not have a smoothly finished surface. This disadvantage is further aggravated by the fact that GaAs particle flags formed by contact and reaction, in the gaseous atmosphere, of the reactants that have failed to arrive at the surface of the substrate 3 due to the abovementioned thermal convection (arrows B) float in the gaseous atmosphere and deposit on the semiconductor film at random. Furthermore, in the above-mentioned apparatus, any change in the type of feed gas is effected by operation of a plurality of valves 5, 6 and 7 for respective gas feeding pipes connected to the above-mentioned nozzle 4. For formation of a plurality of different types semiconductor layers, frequent change-over operation of the valves 5, 6 and 7 is required. This disadvantageously means a low operation efficiency. It is a further problem that the compound or compounds used in the previous series of runs remain in the nozzle 4 and behave as impurities which make it difficult to obtain semiconductors of good quality.
U.S. patent application Ser. No. 941,005 discloses an apparatus for producing semiconductors in a vacuum chemical epitaxy to solve the above-mentioned problems. A substrate is placed in a vacuum chamber. The substrate is heated from its topside. Mixing chambers are disposed in a multistage manner below the substrate. A plurality of reactant gases are supplied toward the substrate from the mixing chambers. However, the above-mentioned apparatus is basically for a batch system production process and unsuitable for a continuous operation. In a specification of the U.S. patent application, it is said that continuous operation is possible but an exact structure for the continuous operation is not disclosed at all.
Accordingly, it is an object of the invention to provide an apparatus for producing good-quality semiconductors having a smooth semiconductor layer surface efficiently by combining the advantages of the MBE process and those of the MOCVD.


The drive system from the engine (1) to the drive wheels (7) of a vehicle is equipped with a torque converter (2), which has a lock-up clutch (3), and a variator (4). Said engined car is provided with a lock-up control means for controlling the engagement/disengagement of the lock-up clutch (3) and a gear change mode switch-controlling means (FIG. 8) for performing control to switch between a “continuously variable gear change mode” and a “DSTEP gear change mode.” While traveling, the gear change mode switch-controlling means (FIG. 8) prohibits gear change by the “DSTEP gear change mode” when the detected oil temperature is at or below a lock-up engagement-permitting threshold for permitting engagement of the lock-up clutch (3) and allows gear change by the “DSTEP gear change mode” when the detected oil temperature is higher than the lock-up engagement-permitting threshold.

Conventionally known is a control device in a continuously variable transmission for a vehicle including a torque converter, wherein the control device employs a simulated step shift mode, wherein the simulated step shift mode is configured to set a target input rotational speed so as to repeat gradual increase and rapid decrease of a transmission input rotational speed during acceleration of the vehicle, and thereby vary a transmission ratio in a stepwise manner (see a patent document 1, for example).
However, if the simulated step shift mode is performed at low oil temperature in the conventional vehicular continuously variable transmission control device, the transmission input rotational speed becomes unstable, for example, because an engine rotational speed does not fall but remains high even when an upshift is performed. This causes a problem that a driver may feel uncomfortable when the simulated step shift mode is employed for shifting at low oil temperature.

Control device for continuously variable transmission of vehicle


A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout. When the following readout of the digital information out of the memory is performed, a new control sum is calculated in the same way, taking into consideration the currently read bit positions corresponding to the first set of bits and a fourth set of bits corresponding to the address position currently selected for readout, to form a fifth set of bits. The read digital information is accepted as correct when a comparison is performed and agreement is found between the second set of bits and the fifth set of bits.

This invention relates to a method of controlling information stored at an address that is pointed out in a memory so that the information is correctly readable before that information is used to control various functions. This invention also relates to a device that can coact with a memory and ensure that digital information, written into and stored within the memory, is correctly readable.
The method and the device or control circuit according to the invention are more specifically intended to ensure that information is correct, where the information is readable from a control memory, or more specifically out of a location in the control memory pointed out by an address, and where the information is coordinated into a data packet.
In a more specific application in a telecommunication system, the invention is intended to ensure that information stored within a control memory is correctly readable before that information is used to control functions within a switching unit.
Within such a communication system and switching unit, required exchange of signals is performed with information-carrying digital signals that are structured and coordinated into data packets, with one address-related field, or field pointing towards an address, and one information-content-related field, or information-carrying field, or set of bits.
Communication systems that use data packets for required exchange of signals are previously known. One such system, to which a specifically preferred embodiment of the present invention is related, uses a number of digital bit positions coordinated into structured sets of bits. The sets of bits are structured and coordinated into data packets, for required exchange of signals.
Such structured data packets arc called "data cells" in known asynchronous-transfer-mode (ATM) systems. Nevertheless, in the following, the expression "data packet" will be used in a simplifying and more general way, keeping in mind that the invention, with great advantage, can be used even in an ATM system where the data packets are called "data cells".
Data packets (data cells) of the kind relevant here are characterized by certain bit positions that are coordinated into a set of bits representing an address-related field or a field pointing towards an address (called a "header"). This field comprises, among other things a virtual address, also called a channel number. Other bit positions are coordinated into a set of bits representing a user-related information-carrying field or an information-content-related field (called a "payload"), comprising the data information from the user.
Through this separation into structured fields, or sets of bits, some of the bit positions of the address-related field can be structured to indicate and point out a specific destination address while the information-carrying bit positions are structured Into sets of bits within the information-carrying field, and are used to transfer desired information to the chosen receiver at the destination address.
The specific destination address can indicate the use of a chosen channel number. Such channel numbers are virtual and are usually valuable over a single physical link. It has thereby been proven advantageous to change the channel number whenever a data packet is to be directed from one link to another.
Data packets having the same address-related bit positions or fields and the same or different information-carrying bit positions or fields will in the following be said to be data packets of the same category, and there may be a first category, a second category, and so forth.
Such changes of channel numbers (data packets are thereby allotted to different categories) are therefore often performed on both incoming ad outgoing sides of a switching unit within a telecommunication system that uses digital information.
It is further known to add data packets that arc used solely for internal use by the switching unit to optimize certain functions hardware-wise within the switching unit. Such data packets use more bit positions than the amount of bit positions or sets of bits used in a standardized data packet. These switching-unit-internal data packets can be structured as a label, a label field, or label-related bit positions or sets of bits that can be added to incoming data packets to direct such data packets to the correct outgoing link based on the digital value of the bit positions of tile added label.
The label field added to each respective data packet comprises a set of extra bit positions corresponding to the amount of bit positions in the address field, which are removed at the outgoing side of the switching unit. Thus, the label field only exists as a supplement to the standardized data packet as internal data packets within the selector switching unit.
It is further known that with telecommunication systems of this kind the use of a traffic arranging computer, belonging to the switching unit, is required to establish a connection through the switching unit. The traffic arranging computer or traffic computer is a very complicated unit that will not be described in detail in this application. Only the less complex part that is required to realize and understand the present invention will be described.
It is known that when a caller is making a call and wishes to establish contact, such as a voice contact, with a called subscriber, data packets are activated for transmission according to a standardized signalling protocol. The data packets can here be supposed to belong to a specific category in that the address-related bit positions or sets of bits call for a direct connection with the control computer as soon as they arrive at one of the free receiver circuits in the switching unit.
The address-related field thus comprises a specific channel number that calls for the direct engagement of the traffic computer, while the information-carrying field can hold information of a desired connection to a pointed out called subscriber.
The channel number is, in a previously known manner, read out of the address-related field whenever a data packet of this kind arrives at one of the free receiver circuits of the switching unit, and, when the channel number is interpreted as a calling channel number, the whole data packet is transmitted to the traffic computer for evaluation and processing.
At this point the information carrying field is evaluated and under guidance of this, and taking the momentary situation within the switching unit under consideration, the traffic computer selects an available connecting path through the switching unit via earlier known functions, and gives the call a new channel number which is notified to the caller. From this point the caller transmits its data packets with the new channel number. In this way, the data packets have been given a new category.
At every call and following setup of connections it is also earlier known to let the traffic computer write into a control memory what address-related fields and/or labels are to be given to every thereafter-incoming data packet with the given new channel and what switch-internal chosen channel number these are to be given. Of course this is done in case a change of channel numbers is to be performed.
The control memory will therefore, in the normal case, comprise bit positions coordinated into a set of bits structured into a specific label, and coordinated bit positions structured into a specific address-related field, the latter representing the switch-internal channel number. This is done for every channel number given by the computer unit that will be used by the caller.
The control memory also needs to be configured in a way so that every above-mentioned bit position or set of bits will be assigned an addressing or addressable position in the memory.
The normal case will thus be that a control memory of this kind will comprise a large number of bit positions and a large number of bit positions that are coordinated into sets of bits within various address positions, representing a large number of established connections.
Every selected address position or address within the control memory will determine what label and what switch-internal channel number that is to be given to a certain received data packet.
Whenever a data packet having a channel number given by the control computer arrives at one of the available receiver units of the switching unit, it is determined, from its given channel number, which switch-internal connection it belongs to. Based on the channel number of the arriving data packet, a correct address position within the control memory can be pointed out where the label and switch-internal channel number are stored.
The label and the address-related field is at this point added to the data packet at hand by changing its incoming channel number to the switch-internal channel number, whereafter the data packet, with its changed channel number, is transmitted further through the switching unit.
It is also known to change channel numbers in the same way if a change of channel numbers is required on the outgoing side of the switching unit.
The invention is intended to control whether the information read out of the control memory is correct.
In view of the known prior art as described above, it must be regarded as a technical problem to be able to realize what measures and means are to be coordinated to be able to create a method and a control circuit or device that is to provide the technical advantages attached to the invention at hand, which are the possibilities to be able to control that an information read from a memory is correct before the information is used to control various functions and where the control consists of letting, amongst other things, the address of the memory position be a part of a control sum.
It will further be considered as a technical problem to, with simple means, be able to create such conditions that a first control sum can be calculated and stored separately at the entry of the switch-internal-related information intended to be stored; that another control sum can be calculated at the reading of the information; and that these control sums will be controlled and verified to be identical before the thus read information is to be used.
It must also be considered as a technical problem to be able to realize the advantages that reside in entering not only address-related bit positions but also control-sum-related bit positions into the memory, where the latter not only originate from the former but also from the bit positions that represent the address positions in the memory where the address-related bit positions or set of bits are stored.
It is a further technical problem, based on known prior art as described above and for a telecommunication system based upon data packets of bit positions and sets of bits such as an ATM system, to be able to realize that to achieve the technical advantages that reside in the invention a control and an activation of a traffic computer is required so that the traffic computer can calculate a control sum, such as parity bits, a check sum or likewise, valid for the address-related information that is to be stored in the control memory and a set of bits corresponding to a selected address in the memory, and that the traffic computer has to be controlled and activated to write the bit positions corresponding to a label and/or the bit positions corresponding to an address field and further the bit positions corresponding to the thus calculated control sum.
It must also be considered as a technical problem to be able to realize the importance of being able to use a known receiver unit, belonging to a switching unit, to receive each and every one of the arriving data packets to be able, in every data packet and depending on the bit positions coordinated within the channel number given by the control computer and represented by the address-related field, to read the corresponding information, stored in the control memory and pointed out by the channel number, where the information is to be added to respective data packets, for the purpose of switch-internal collecting functions, as a switch-internal address-related field, or switch-internal usable field or bit positions, instead of the channel number that has been given by the control computer to the data packets transmitted from the caller.
It is also a technical problem to be able to realize the necessity of and simplicity in calculating the relevant control sum with the same chosen algorithm or likewise, and to store it as parity bits or a check sum.
It is also a technical problem to be able to realize the importance of calculating the parity bits or check sums independent of each other using different calculating circuits or look up tables and thereby realize the high probability that is offered of a correct reproduction of read information and that a verified agreement between the check sums or parity bits can be made so that it can be known that no bit error has occurred in the information that has been stored in and read out of the control memory and that therefore the data packet at hand, with label and/or switch-internal address-related fields, can pass on through the switching unit.
There is also a technical problem in being able to realize the importance of letting the switch-internal address-related field also comprise a label field adapted to specific functions.
There is also a technical problem in being able to realize the advantages of letting the control computer perform parity calculations of the channel numbers within the information-related fields of respective incoming data packets.


A planning system for quickly forming the optimum plan for a given planning problem, includes a setting unit for accepting the given planning problem; an optimization unit for creating an objective function which expresses an item intended to be minimized or maximized in the planning problem, and for executing a process which minimizes or maximizes a value of the created objective function; a storage unit for storing therein, at least, constant values which are required for the optimizing process; and a display unit for displaying a processed result of the optimization unit. The optimization unit performs a first function of calculating a difference value between the values of the objective function assumed in a last formed plan and a newly formed plan, and performs a second function of comparing the difference value of the objective function with the constant value set in the storage unit, and then substituting the last formed plan by the newly formed plan and setting the latter as a candidate for an optimum plan, on condition that the difference value of the objective function is smaller than the constant value.

1. Field of the Invention
The present invention relates to technology for offering the optimum plans of multifarious planning problems in various fields. More particularly, it relates to a planning method of and a planning system for solving a problem which involves an enormous number of combinations or permutations and as to which a plan being the optimum solution exists without fail, with a simple construction and at a very high speed.
2. Description of the Related Art
In a variety of fields (for example, the design of the pattern to-be-printed of an electronic circuit board, a manufactural process, the design of piping in sewerage, and a materials handling system), various techniques have been proposed in order to find the optimum solutions within realistically allowable time periods in the planning of problems of multifarious purposes, wherein the optimum solutions are plans each of which maximize or minimize predetermined items.
By way of example, as stated in a report "Epoch-making Solution for `Traveling Salesman Problem`--Marvelously excellent results obtained by utilizing chaos" in a magazine "Kagaku Asahi (1993-Feb.)" or the official gazette of Japanese Patent Application Laid-open No. 304587/1990 entitled "System for Calculating Shortest Distance, Shortest Time or Lowest Traffic Cost", a mutual coupling type neural network, a chaotic technique, etc. are applied with the intention of realizing an expedient in which the plans of planning problems in various fields are optimized within actually allowable time periods.
In contrast to a so-called "enumeration method", wherein the combinations of all thinkable plans are studied on a given planning problem, recent optimization expedients which include the aforementioned example of the applications of the mutual coupling type neural network, the chaotic technique, etc. have a common idea as stated below. First, a certain plan is formed. Thenceforth, while the content of the plan is being efficiently altered little by little, the value of an objective function which expresses an item desired to be finally maximized or minimized in the planning problem is evaluated on and on (that is, plans are not formed at random, but the optimum solution is intended to be obtained in a small number of times of planning). Herein, a superior plan (for example, a plan which decreases the objective function value) is adopted as the succeeding candidate for the optimum plan, namely, the plan which maximizes or minimizes the objective function. Thus, it is intended to eventually obtain the optimum solution in a short time period.
Any of the prior-art techniques, however, have the following drawbacks:
(1) Each time a new plan is formed it requires at least n.sup.2 to n.sup.3 operation processes to be executed, in order to configure the new plan, where letter n denotes the number of the constituent elements (the objects to-be-dealt-with) of the particular plan. Herein, the constituent elements act as the parameter of the planning operation for optimizing the objective function. PA1 (2) There is not the theoretical support that the optimum solution can be reached, and the optimality is empirically evaluated. Accordingly, a long processing time period is expended in attaining to the optimum solution or a quasi-optimum solution. Moreover, the optimum solution is attained to at a very low probability. PA1 setting means for accepting, at least, a given planning problem, and values of a variable required for solving the problem; optimization means for creating an objective function which expresses an item intended for either of minimization and maximization in the planning problem, and for forming a plan which affords either of minimum and maximum values of the created objective function; and storage means for storing therein, at least, a variable required for forming the plan; PA1 the optimization means including calculation means for calculating a difference value between-values of the objective function assumed in a plan formed last and a plan formed anew; and replanning means for comparing the difference value of the objective function with a value of the variable previously set in the storage means, and for substituting the last formed plan by the plan formed this time and setting the latter as a candidate for the optimum plan, on condition that the difference value of the objective function is smaller than the value of the preset variable. PA1 altering part of an element arrayal of a permutation in a case where the plan is a permutation problem, and at least one element to-be-selected in a case where the plan is a combination problem; and PA1 calculating a difference between values of the objective function assumed before and after the alteration, and setting the new plan after the alteration as a candidate for an optimum plan on condition that the difference is smaller than a value which is uniformly distributed within a range of values decreasing gradually each time the plan is altered.
By way of example, in a system explained in the above report of the magazine, the settlement of the so-called "traveling salesman problem" for determining the shortest one of routes in each of which 30 places are respectively visited only once requires a long time period of 20 [seconds] even when a recent computer (for example, a work station having a capability of 10 to 100 [MIPS (million instructions per second)] is used. Besides, the optimum solution is erroneously found at a probability of 3 [%].


The universal clipping retainer for engaging a bundle of tubular elements to a frame rail flange of a vehicle comprises first and second sections. The first section comprises structure to which a tubular bundle is engaged by means of a cable tie strap member, the strap member extending through openings in the section, extending around the bundle and engaging to itself. The second section is a clip engaged to one end of the first section, the clip comprising a plurality of fingers biased toward a centerline of the clip for engaging a frame rail flange therebetween, each of the fingers having barbs on a flange engaging surface thereof, with the barbs pointing away from free ends of the fingers.

The present invention relates to a universal clipping retainer which is particularly adapted to engage a frame rail flange of a vehicle such as a truck, the flange being slightly wedge shaped and the retainer being engageable thereto by merely pushing it onto the flange. The retainer being able to withstand three gravities of force load to prevent disengagement when the vehicle travels over rough, bumpy terrain. More specifically, the retainer includes resilient flange grasping fingers which are provided with angled barbs thereon for resisting displacement of the retainer on the flange.

Navistar International Transportation Corp.


A door frame and a method for constructing a door frame assembly for use in prefabricated housing. The door frame assembly has a header frame and two side frames fixedly attached and constructed out of metal. The door frame assembly is slidable into position in a prefabricated housing unit. The individual frame members are preferably manufactured from galvanized steel.

The various components in a prefabricated housing unit are often assembled in various locations and then shipped to the prefabricated housing manufacturer for installation into the housing unit. The housing manufacturer generally assembles these components in assembly line fashion. As with any product manufactured on an assembly line, time and ease of construction are paramount considerations.
The installed components in the construction of a prefabricated housing unit include the doors and the door frames. The door or frame manufacturer generally will construct the frame, hang the doors on the frame, and then the ship the door frame assembly to the prefabricated housing manufacturer for installation therein.
An example of current door frame assembly design is shown in FIG. 1. In essence, the construction of this prefabricated door frame assembly 10 starts with the assembly of a wooden frame 20. An exterior aluminum frame 30 with one or more hinges 35 and a door stop 37 is attached to the wooden frame 20 and an aluminum screen door 40 is then attached to the hinges 35. One or more entry door hinges 50 and an entry door stop 55 are attached to the opposite side of the wooden frame 20. A steel entry door 60 is then attached to the entry door hinges 50. Weather stripping 65 is also applied. The unit 10 is then shipped to a housing manufacturer. The manufacturer slides and fastens the door frame assembly 10 into place in the prefabricated unit.
Although this method provides a door and door frame that can be easily installed into a prefabricated housing unit, there are drawbacks in terms of strength, security, and costs. The housing unit is only as strong and secure as the wooden frame upon which the doors are hung. Further, the method of construction for the frame manufacturer is expensive and time consuming given the number of parts involved. Several laborers are required to construct this type of door frame assembly.
Although it is known in the art of residential and commercial construction to use steel door frames for increased strength and security, such frames have not been used in the prefabricated housing industry because of difficulties in installation. These frames generally comprise several discrete components that are assembled at the construction site. For example, the assignee of the present application manufactures and sells a steel frame under the trademark "Rediframe" brand wall system. This product envelopes and is attached to the surrounding wall. As is shown in FIG. 2, the door frame assembly 70 comprises a header frame 75 and two side frames 80. Each frame member 75, 80 of the door frame assembly 70 surrounds the wall 86 and is held in place by a plurality of fasteners 90 which penetrate wall board 85 and engage the wall framing such as steel stud 95. The door frame assembly 70 is thus secured to the wall framing, such as steel stud 95, positioned behind the wall board 85. The doors are then hung after the frame unit 70 is in place in the wall 86.
Although a steel door frame would provide additional security, this type of construction is not suited for the prefabricated housing industry because of the time involved in attaching each of the respective frame members to the wall and then mounting the doors. In other words, this type of door frame is not appropriate for the prefabricated housing industry because known steel door frames cannot be adapted for installation in assembly line fashion. The industry demands that the door frame assembly be able to slide quickly into place in the housing unit with both doors pre-hung.
What is needed therefore, is a door frame assembly of simple manufacture for use in the prefabricated housing industry. The door frame assembly should provide superior strength and security while being easy to assemble with reasonable costs. It is essential that the door frame assembly be able to slide into place into a prefabricated housing unit as the unit is progressing on the assembly line.


In a nozzle plate of the present invention, a part of fuel flowing out from a fuel injection port of a fuel injection device is atomized by colliding with an interference body, is rapidly bent in a flowing direction, and collides with the fuel that is flowing straight through a nozzle hole and an orifice to make the fuel that flows straight through the nozzle hole and the orifice turbulent. The orifice includes a corner portion which is defined by an outer edge portion of the interference body and has a pointed shape without roundness at a part of an opening edge. The corner portion makes an end portion of a liquid film of the fuel passing through the orifice into a pointed shape for ease of atomization by friction with air.

Internal combustion engines (hereinafter, referred to as an "engine") of automotive vehicles and the like are configured to mix fuel injected from a fuel injection device with air introduced via an inlet pipe to generate a combustible gas mixture, and burn the combustible gas mixture within a cylinder. The engines of this type are known to have a configuration in which a state of mixture between the fuel injected from the fuel injection device and the air has significant influence on engine performances, and specifically, atomization of the fuel injected from the fuel injection device is an important factor which affects the engine performances.
FIG. 39 illustrates a nozzle plate 1002 mounted at a fuel injection port 1001 of a fuel injection device 1000. The nozzle plate 1002 is provided with nozzle holes 1003 having a square shape in plan view and formed so as to increase in size from one end side to the other end side in a plate thickness direction, and is mounted at the fuel injection port 1001 of the fuel injection device 1000 so that the one end side thereof in the plate thickness direction faces a side where the fuel injection port 1001 of the fuel injection device 1000 resides. The nozzle plate 1002 is provided with interference bodies 1005 formed at nozzle hole opening edges 1004 on the other end side in the plate thickness direction, and the interference bodies 1005 are configured to partly occlude the nozzle holes 1003.
The fuel injection device 1000 provided with the nozzle plate 1002 described above is configured in such a manner that when fuel flows out from the fuel injection port 1001, misty fuel F2 that has collided with the interference bodies 1005 and flowing along surfaces 1008 of the interference bodies 1005 collides with fuel F1 flowing along inner wall surfaces 1006 of the nozzle holes 1003, so that the fuels F1 and F2 are atomized and are injected from the nozzle holes 1003 into the inlet pipe (see JP-A-10-122097).


An abrasion resistant bearing system for use in the agitation assembly of a mineral dissolution machine. The agitation assembly is part of the mixing tank where abrasive materials such as gypsum, nitrogen, potassium, sulphur and the like are kept in a mixed condition for ultimate discharge into an agricultural irrigation system.

The present invention relates to bearings, and in particular to an abrasion resistant bearing for use in mixing machines for abrasive minerals.
In agriculture, it is desirable to enhance soils with certain minerals and nutrients such as gypsum, sulphur, potassium and nitrogen. Many growers have installed drip or sprinkler irrigation systems for their crops. These irrigation systems provide an efficient method for applying such minerals and nutrients to the soil. There are a number of well known mixing machines in use which provide different ways of mixing these minerals and nutrients with water for injection into irrigation systems. Among these are U.S. Pat. Nos. 4,812,045; 4,820,053; and 5,417,491. The dissolution machines described in these patents include a large mixing tank with an agitation apparatus inside where the mineral or nutrient is mixed with water. Large amounts of these materials are mixed with water in order to keep the material in suspension.
Unfortunately, these materials are very abrasive. Moreover, minerals such as gypsum will settle out very rapidly when agitation is stopped making it very difficult to then bring them back into suspension. As a result, it is often necessary to keep such materials actively agitated for long periods of time. The abrasive quality of these materials causes much wear on the bearings of the agitation assembly.
Existing agitation systems have been constructed using parts made out of cast iron and brass. The abrasive quality of materials such as gypsum causes significant wear on parts made of these materials resulting in continuous maintenance in the form of repair and replacement.
In 1982, Spraying Devices, Inc. of Visalia, Calif. developed a material made of glass filled nylon for use in the bearings of agitation systems. While this proved a great improvement over the cast iron and brass, the glass filled nylon still wore out too quickly.


A chain-shaped foldable cellphone capable of expanding functions and changing shape during usage comprises a mainframe module, a display module, more than one dual-spindle connecting block and an expansible module or an extensive module, wherein the extensive module is a complementary connector of the expansible module, and the neighboring ends of the two modules can be connected mutually while the distant ends thereof can be connected to one of the spindles of one dual-spindle connecting block respectively; by using the pivotal connection of the dual-spindle connecting block, the mainframe module is pivotally connected to the display module, and a plurality of extensive module and expansible module of various functions can be further pivotally connected to construct a chain-shaped foldable cellphone.

1. Field of the Invention
The invention relates to a chain-shaped foldable cellphone, and more particularly, to a chain-shaped foldable cellphone capable of extending functions and changing shape during usage.
2. Description of the Related Art
In the prior art, a foldable cellphone generally has a display module and a mainframe module, and the display module is pivotally connected with the mainframe module by a single spindle. Therefore, the foldable cellphone has advantages of being small in size and portable because the display module can lift 180 degree upwardly relatively to the mainframe module or cover the mainframe module.
Another conventional foldable cellphone also has a display module and a mainframe module; nevertheless, the display module and the mainframe module are respectively pivotally connected to each of the spindles of a dual-spindle connecting block. The display module of such foldable cellphone has an angle of usage adjustable from 0 to 360 degree, and more particularly, uses and functions of the foldable cellphone can be expanded and improved by folding reversely 360 degree of the display module to the back of the mainframe module.
Nevertheless, above-mentioned conventional cellphones are not capable of folding obversely or reversely to change the shape during usage.


The invention features a dry platelet composition and methods of making and using the freeze-dried platelet composition.

Platelets are useful in the treatment of various pathologic conditions such as, for example, wounds, platelet deficiencies (e.g., thrombocytopenia), various genetic or acquired abnormalities, and severe blood loss. However, despite their high demand, the availability of platelets has been limited, at least in part, by their short shelf-life and the inability of current methods to preserve normal platelet function after storage for relatively long periods of time. There is a need therefore to develop platelet compositions that have increased shelf-life.


The method for producing silicon metal and porous carbon from rice hulls is provided. The method comprises a first step S1 of producing a rice hull charcoal M2 containing SiO2 and C by heat treatment of rice hulls M1; a second step S4 of exposing the rice hull charcoal M4 to at least any one of heated first inert gas G2 or reducing gas to produce SiC; a third step S5 of exposing SiC to a heating atmosphere containing Cl2 gas to produce SiCl4 and porous carbon P1; a fourth step S7 of reacting SiCl4 and Zn to produce silicon metal P2 and ZnCl2; and a fifth step S9 of electrolyzing ZnCl2 to produce Zn and Cl2 gas. The Cl2 gas in the fifth step S9 is used in the third step S5, and Zn in the fifth step S9 is used in the fourth step S7.

Methods for producing silicon carbide, amorphous silica, or silicon metal from rice hulls or carbide of rice hulls are conventionally known.
In Patent Literature 1, a method for continuously producing silicon carbide and silicon nitride from carbide of rice hulls is described. In the method, the carbide of rice hulls is heated while being transported in a heating zone under presence of an inert gas nonreactive with carbon.
In Patent Literature 2, a method for producing a molded product of porous silicon carbide including composite structure of silicon carbide whiskers and silicon carbide fine particles made from carbide of rice hulls is described. In the method, the surface of pulverized carbide of rice hulls is treated and the carbide is molded after surface treatment. The molded product is then heat treated for removal of carbonized components.
In Patent Literature 3, a method for producing silicon metal made from silicicolous plants such as rice hulls is described. In the method, silica ash obtained by firing silicicolous plants is reacted with a metal such as aluminum by heating in an inert gas atmosphere.
In Patent Literature 4, a method for producing a silica raw material from rice hulls is described. In the method, rice hull powder is treated with pressurized hot water to adjust the ratio of silica components to organic components in the rice hull powder.
In Patent Literature 5, a method for producing high purity amorphous silica from rice hulls is described. In the method, rice hulls are treated with acetic acid-containing solution to separate alkaline components from the rice hulls. After separation of alkaline components, the rice hulls are washed and dried. The dried rice hulls are carbonized to form rice hull charcoal. The rice hull charcoal is fired to produce high-purity silica.
In Patent Literature 6, a method for producing active carbon is investigated focusing on carbon components of rice hulls. A hydrogen absorption method is described, including the steps of: carbonizing carbon material; subjecting the carbonized carbon material obtained in the previous step to alkali activation, accommodating the porous carbon made in the alkali activation step in a vessel, and introducing hydrogen into the interior of the vessel so as to have a pressure of 0.5 to 6 MPa in equilibrium state, while keeping the temperature in the interior of the vessel in the range of 77 to 150 K. The process has a problem that silica components are melted with an alkali salt and discarded.

Method for producing silicon metal and porous carbon