A control system for the use of the main engine of a vehicle as a heat source in maintaining the temperature of an operator compartment. The system is manually enabled subject to multiple criteria, the temperature in the operator compartment is monitored, and signals for the desired operator compartment temperature within an about plus or minus 10 degrees control range are produced. The main engine of the vehicle is enabled to start and run by all standard safety features and with a fuel flow controlled idle power output. Cycling through the starting and stopping of the engine is accomplished in response only to the temperature monitor signals. Disconnect of the operator compartment temperature control is accomplished manually by the operator, usually by actuating the operator controls. The invention provides the added safety feature of focused operator attention at enablement; the added control feature of system hysteresis through the use of a temperature range to prevent over regulation and any added idling is only that needed for operator compartment temperature maintenance.

In the operation of vehicles that are in service for long periods, such as trucks, tradeoffs are encountered in the considerations involved in the controls provided when the main engine that provides the power for the movement of the vehicle is also to be used for the source of energy for the heating or cooling of the operator compartment. The limitations imposed by the environmental conditions of operation, the duration of the operation and the performance expected of the operator are at times difficult to accommodate together.
An example of the various considerations involved in the interrupting and restarting of a main vehicle engine is illustrated in U.S. Pat. No. 5,186,015. Adding to the types of considerations illustrated in U.S. Pat. No. 5,186,015 further considerations are encountered in providing for the control of the main engine where it is also to serve as an energy source for maintenance of the temperature of the operator compartment so that an operator is able to sleep in it for a normal period. Under such circumstances, additional safety considerations become involved due to the relatively prolonged period without operator attention.
In U.S. Pat. No. 5,072,703 a system is described that provides an operator compartment temperature monitoring function that is independent of operator involvement and participation. In the system of U.S. Pat. No. 5,072,703 there is a "pre start up" engine starting, running and stopping operation that is used to establish that there is a non-moving condition of the vehicle, in other words that the vehicle is parked, and some of the sub systems are enabled by this "pre start up" operation. The "pre start up" operation is then followed by an "actual" engine starting, running and stopping cycling operation during which the operator compartment temperature is one of many conditions that enable engine cycling.
In the operation of vehicles there may be many environmental and operational considerations that would limit the use of a complete automatic starting, running and stopping system for the control of the main engine for temperature control of the operator compartment. There is a need in the art for an ability to retain operator participation while controlling operator compartment temperature during sleeping periods.

Vehicle engine control for operator compartment temperature maintenance


A method of restoring a used golf ball in which a small portion of the old cover is removed and a new layer of material added, which new layer includes dimples. The new layer may be transparent with an indicia on its outer surface or on the outer surface of the remaining old cover.

Constructions of golf balls have included cores and multiple layers on the cores including a layer for carrying indicia (U.S. Pat. No. 4,998,734). Such multiple layers have also included covers applied in layers (U.S. Pat. No. 4,337,946, U.S. Pat. No. 4,431,193 and U.S. Pat. No. 4,919,434).
It has also been proposed to place indicia on the core visible through a clear cover stock and clear final coat (U.S. Pat. No. 4,798,386).


A reference voltage generator for improving setup voltage characteristics without an increase in a standby current and a method of controlling the same, in which the reference voltage generator includes: a reference voltage generation unit including a resistor connected between a power supply voltage and an output node, for dividing the power voltage, and generating a reference voltage fed to the output node thereof; a voltage detector receiving a feedback of the reference voltage and detecting a level of the reference voltage; and a bypass circuit connected in parallel to the resistor of the reference voltage generation unit and bypassing the resistor in response to an output signal of the voltage detector.

1. Technical Field
The present disclosure relates to a semiconductor integrated circuit and, more particularly, to a reference voltage generator for improving setup voltage characteristics without an increase in a standby current.
2. Discussion of Related Art
A reference voltage is generally used to determine a logic level of data. More specifically, data lower than the reference voltage is determined as a logic low level, and data higher than the reference voltage is determined as a logic high level. Thus, if a reference voltage level varies, a data logic level may be erroneously determined. In addition, the reference voltage can be used to generate an internal power voltage in a memory device, such as DRAM.
The reference voltage should always have a constant value even in the face of variations of a process, a temperature, and a power supply voltage. A circuit for generating the reference voltage must have good setup voltage characteristics. A variety of types of circuits are used to generate the reference voltage, and one example of a reference voltage generator is disclosed in U.S. Pat. No. 5,309,083 A.
FIG. 1 is a circuit diagram of a conventional reference voltage generator. FIG. 2 is a plot of voltages illustrating characteristics of the conventional reference voltage generator.
Referring to FIG. 1, the conventional reference voltage generator includes a voltage divider 11 that divides a power supply voltage VDD and outputs a reference voltage VREF to an output device, and a reference voltage controller 13 that controls the level of the reference voltage VREF in response to the control voltage VCON generated from the voltage divider 11.
The voltage divider 11 includes two resistors RS and R and two NMOS transistors N1 and N2. The reference voltage controller 13 includes a PMOS transistor P1.
The conventional reference voltage generator, however, determines a setup voltage VSET of the reference voltage VREF according to the resistor RS. In more detail, the smaller the value of the resistor RS becomes, the lower the setup voltage VSET becomes, resulting in the improvement of the setup voltage characteristics but causing an increase in a standby current.

Reference voltage generator having improved setup voltage characteristics and method of controlling the same


A method for determining an amount of consumed energy includes acquiring deformation information of a mat surface of an elastic mat used by a user during one deformation process, determining an amount of energy consumed by the user during the deformation process according to the deformation information, and recording the amount of energy.

People have begun to pay attention to health problems with the continuous improvement of living standards, and most people like to keep fit by means of exercises. Generally, people can calculate an amount of energy consumed in an exercise to determine an amount of exercise.
In conventional technologies, when determining the amount of exercise, people generally record the name and a corresponding duration of a single exercise and then inquire an amount of energy that can be consumed in the exercise within a unit of time. For example, one minute of sit-up would consume 10 calories. Thus, the amount of energy consumed by the exercise can be calculated according to an exercise duration, and the amount of exercise can be determined accordingly.
However, with the conventional technologies described above, only the duration of the exercise is tracked for calculating the amount of consumed energy without considering the difference in energy consumption caused by different exercise amplitudes and exercise frequencies within the same period of time. Thus, the accuracy in calculating the amount of consumed energy is not accurate.

Method and device for determining value of consumed energy


A power fault testing apparatus for testing telecommunications equipment interfaces to Telcordia""s 2nd Level AC power fault standards. The apparatus is powered by a three-phase 480 VAC, 600 A power service. A plurality of transformers, including a variable autotransformer and a fixed transformer, and load resistor banks are coupled to the power source in a network organized as a plurality of selectable and switchable power paths for interfacing with an Equipment Under Test (EUT) operable to be disposed in a test chamber. Power output of the fixed transformer is referenced to a single point ground positioned at a relay bank. The power to the EUT is referenced to building ground that is tied to the single point ground of the fixed transformer. The fixed transformer thereby operates as an isolation transformer, which allows for testing the EUT while operating under power.

The present invention relates to testing equipment for telecommunications equipment. More particularly, and not by way of any limitation, the present invention is directed to an AC power fault machine capable of testing telecommunications (telecom) line cards and broadband coaxial cable interfaces to known power fault immunity criteria.
Telecommunications (telecom) equipment deployed in today""s networks is required to comply with various governmental and industry standards not only to ensure seamless interoperability which reduces the risk of service interruption resulting from third-party product failures, but also to address various product safety issues. Accordingly, equipment manufacturers test their products to telecom industry standards commonly known as Telcordia specifications (formerly known as the BellCore specifications) which define an extensive list of electromagnetic compliance (EMC), product safety, and environmental requirements.
The Telcordia specifications comprise two sets of testing standards, GR-1089-CORE and GR-63-CORE. The tests in GR-1089-CORE deal primarily with electrical phenomena, whereas the tests in GR-63-CORE are predominantly environmental in nature. While each set of standards is quite extensive, typically only a subset of the tests are required based on the type of equipment and its intended operating environment. Together, these two sets of standards specify the electrical and environmental requirements that networking hardware must meet in order to be located in a telco building, e.g., the telco""s central office (CO).
Besides the testing requirements, which are determined by product type, Telcordia has defined additional testing levels generally referred to in the telecom industry as Network Equipment Building Systems (NEBS) levels. The appropriate NEBS level for particular equipment is determined, again, by its intended operating environment and specific requirements of the Regional Bell Operating Companies (RBOCs). Generally, a higher NEBS level indicates a more stringent testing specification. NEBS testing verifies that telecom equipment can operate successfully under certain electrical and physical environmental stresses and not pose a safety hazard to personnel and users. These stresses and hazards include earthquakes, airborne contaminants, fire and smoke, electromagnetic interference (EMI), electrical safety, and grounding.
Requirements under the three NEBS levels may be summarized as follows: Level 1 includes: electrical safety; lighting and AC power fault (2nd level); bonding and grounding; emissions; and fire resistance; Level 2 includes: all of Level 1 in addition toxe2x80x94Electrostatic Discharge (ESD) under normal operation; emissions and immunity; lighting and AC power fault (1st level); ambient temperature and humidity (operating); earthquake Zone 2 and office vibration; and airborne contaminants (indoor level); Level 3 includes: all of Level 1 and Level 2 in addition toxe2x80x94ESD (installation and repair); open door emissions and immunity; ambient temperature and humidity (short-term); earthquake Zone 4; airborne contaminants (outdoor level); and transportation and handling. Each test within these three Levels is defined in either the GR-1089-CORE or GR-63-CORE documentation.
Testing of telecom interfaces, i.e., tip-and-ring (T and R or T/R) interfaces of the line cards utilized in telecom equipment and broadband coaxial cable interfaces, for lightning and AC power fault immunity in accordance with the above-referenced standards is necessary for several reasons. Power companies, Local Exchange Carriers (LECs) and broadband access providers often serve the same customers, and frequently employ joint-use facilities such as supporting structures or a common trench for their respective outside plant. Metallic conductors, such as cable or wire pairs serving telecom equipment may be exposed to electrical surges resulting from lightning and commercial power system disturbances. Despite the presence of protective devices in the telecommunications network that limit the effect of lightning and power surges, a portion of these disturbances can be impressed on the network equipment. Accordingly, under abnormal conditions, for instance, the power and telecommunications lines (including coax cables) may come into electrical contact. If the contact occurs to a primary power line, faults may be cleared quickly by the power system (5 seconds or less), and protectors (e.g., carbon blocks) can limit 60 Hz voltages appearing on the T and R conductors to maximum of approximately 600 VRMS with respect to ground. If the contact occurs to a secondary power line, the full secondary voltage with respect to ground (up to about 275 VRMS in some cases) may appear on the T and R conductors, which may persist indefinitely as the secondary fault may not be cleared by the power system.
Moreover, because electric power lines and telecom lines often occupy parallel routes as a result of a common right-of-way, the magnetic field produced by currents in a nearby power line, especially under abnormal conditions such as a phase-to-ground fault, may result in large voltages being induced into the telecom lines through electromagnetic coupling. The induced voltages appear longitudinally in the T and R conductors and may approach several hundred volts. Lower levels of induction may result from a high-impedance power fault such as a phase conductor falling to the earth. If the resulting unbalanced current is within the normal operating range of the power system, or if power system breakers or fuses do not operate, the fault may persist for an extended period of time.
Under the Telcordia""s GR-1089-CORE standard, the lightning surge and AC power fault immunity criteria include compliance with various tests such as short-circuit tests (tip to ring, tip to ground with ring open-circuited, ring to ground with tip open-circuited, tip and ring to ground simultaneously, et cetera) and several AC power fault tests. As set forth hereinabove, these criteria are separated into 1st level and 2nd level criteria. To comply with the 1st level criteria, it is required that the telecom Equipment Under Test (i.e., EUT) be undamaged and continue to operate properly after power stress is removed. To comply with the 2nd level criteria, primary protectors are typically removed and high open-circuit voltages and high short-circuit currents are often applied for variable durations, ranging up to 15 to 30 minutes or so in some instances. The EUT may sustain damage, but it is required that the equipment not become a fire, fragmentation (that is, forceful ejection of fragments), or an electrical safety hazard.
While several lightning machines are available for conducting the lightning compliance tests required under the BellCore standards alluded to hereinabove, there is a paucity of appropriate AC power fault (PF) machines capable of sourcing power to telecom units under test for adequately conducting the AC power fault compliance tests, including the 2nd Level tests. Further, the relatively few solutions extant today are beset with various shortcomings and drawbacks. First, the existing AC power fault machines are typically custom-designed to a large extent and, accordingly, incapable of accommodating various telecom equipment types and form factors. Additionally, these machines are quite expensive to manufacture owing at least in part to their custom design. In spite of the custom design, however, the existing PF machines are not capable of providing appropriate levels of test power safely to the EUT to conduct the whole range of 2nd Level power failure tests as required under the relevant Sections of the GR-1089-CORE standard. Furthermore, although the conventional PF machines are fairly capacious because of the large size of the transformers typically required to provide adequate levels of test power, they are incapable of sourcing power to both two-wire T/R interfaces as well as broadband coax cable interfaces in the same physical plant. In addition, it would be desirable to support testing the EUT interfaces while the EUT is operating under power.
Accordingly, the present invention advantageously provides a safe, versatile and single-platform power fault (PF) testing apparatus that is capable of performing both voltage mode and current mode testing on line card T/R interfaces (two-wire interfaces) as well as broadband coaxial cable interfaces to Telcordia""s 2nd Level AC power fault standards. The power fault testing apparatus for testing telecommunications equipment interfaces includes a variable autotransformer unit coupled to a three-phase power source through a power relay. The variable autotransformer unit operates to provide a selectably switchable power output. A fixed transformer is selectably coupled to the power output of the variable autotransformer unit in order to provide selectably switchable power output to an interface of an Equipment Under Test (EUT) that is operable to be disposed in a test chamber. The power output of the fixed transformer is referenced to a single point ground, which may be building ground. The single point ground may be positioned at a relay bank. The power fault testing apparatus of the present invention further comprises a return path for the power output of the fixed transformer from the EUT to the single point ground of the fixed transformer. The return path, thereby referencing the EUT to the building ground, allows for testing the EUT interfaces while equipment is operating under power.
In one embodiment, the power fault testing apparatus of the present invention comprises a load resistor bank disposed between the fixed transformer and the EUT""s tip-and-ring interface. The load resistor bank comprises a plurality of binary-coded resistors selectable by a series of relays coupled thereto. At least one relay operating under computer-based timer relay control may be disposed between the fixed transformer and the load resistor bank. Another relay operating under interface electronics control may be disposed between the variable autotransformer and the fixed transformer. A step transformer may be positioned between the variable autotransformer and the fixed transformer. The step transformer may be a 4:1 step down transformer. The variable autotransformer may be a 1:1.17 voltage boost transformer. The fixed transformer may be an isolation transformer.
In another embodiment of the present invention, at least one load resistor bank comprising individual (fixed) power resistors is disposed between the fixed transformer and the EUT""s coaxial cable interface. A boost transformer is disposed between the variable transformer and the fixed transformer. At least one relay operating under interface electronics control is disposed between the variable autotransformer and the boost transformer.
Alternatively, a step down transformer is disposed between the variable transformer and the fixed transformer in a voltage bucking configuration. At least one relay operating under interface electronics control is disposed between the variable autotransformer and the step down transformer. In another embodiment, the output leads of the fixed transformer are applied directly to the test chamber.
In another aspect of the present invention, the power fault apparatus for testing telecommunications equipment interfaces includes a three phase 480 Vac, 600 A power service for sourcing power to the power fault testing apparatus. A plurality of transformers and load resistor banks are selectively and switchably coupled to the power service in a network organized as a plurality of power paths for interfacing to one of a tip-and-ring interface and a broadband coaxial cable interface of an equipment under test (EUT). A portion of the plurality of transformers are referenced to a single point ground that is also referenced to the EUT. A plurality of power relays interconnect the transformers and load resistor banks disposed in the network. A plurality of output relays are positioned for effectuating duration control output power applied to the tip-and-ring and broadband coaxial cable interfaces. The relays are referenced to a ground bar positioned at a Remote Control Station (RCS) to prevent voltage drops, through a common return, from adversely affecting unpowered relays.
Preferably, the EUT is placed in a testing chamber comprising a clear Plexiglas enclosure. Additionally, preferably, the testing chamber is provided with a safety interlocking mechanism. In a presently preferred embodiment, a RCS is associated with the test chamber.

2nd level power fault testing apparatus for testing telecommunications equipment


An image sensor having different bias voltages is provided. The image sensor may include a plurality of pixels configured to output pixel signals based on a received optical signal, and logic circuits configured to output the pixels signals as image data. The pixels may be formed on a first region of a semiconductor substrate, the first region being substrate biased to a first voltage. The logic circuits may be formed on a second region of the semiconductor substrate different from the first region, the second region being substrate biased to a second voltage different from the first voltage. A full-well capacitance (FWC) of the photodiode may be increased by applying the first voltage, which is a negative (−) voltage, to a photodiode of a pixel to reduce (or, alternatively prevent) a blooming effect.

Example embodiments of the inventive concepts relate to an image sensor. For example, at least some example embodiments relate to an image sensor having different substrate bias voltages to reduce (or, alternatively to prevent) a blooming effect.
Image sensors are semiconductor devices configured to convert optical images into electrical image data. Among semiconductor-based image sensors, complementary metal oxide semiconductor (CMOS) image sensor is characterized by increasing a degree of integration and a resolution of a pixel, thereby providing a display screen with improved image quality. CMOS image sensor converts an optical signal into an electrical signal by using a photoelectric device, such as a photodiode, and outputs the electrical signal. The photodiode is a device that generates photocharges in proportion to the amount of light applied thereto. When light that is too strong is applied to the photodiode, photocharges exceeding a storage capacity of the photodiode may be generated. The excessive photocharges may flow over not only a corresponding pixel but also adjacent pixels, which may lead to a generation of a screen that is white overall or is not precisely recognizable. When CMOS image sensor is used, a blooming effect causing such a screen distortion may occur.

Image sensor having different substrate bias voltages


A sheet transport device comprises a sheet feeding path through which a sheet is transported, first and second elements which are located face to face with a particular point in the sheet feeding path and have first and second surfaces, respectively, constituting part of the sheet feeding path and arranged therealong, an interposed element disposed insertably into and withdrawably from a space formed between the first and second elements, and a discharge arrester disposed in first and second surfaces for providing protection against a discharge of static electricity from the sheet, the discharge arrester having a projecting part extending in a direction intersecting the sheet feeding path.

1. Field of the Invention
The present invention relates to a sheet transport device and an image forming apparatus.
2. Description of the Related Art
Typically, an image forming apparatus is provided with a sheet transport device for transporting sheets. The sheet transport device having a sensor for detecting whether each sheet has passed a particular point in a paper path. This sensor is a photointerrupter (hereinafter referred to as a PI sensor) including a light-emitting element and a light-sensitive element. The light-emitting element has a light-emitting surface from which light is emitted while the light-sensitive element has a light-receiving surface for sensing the light emitted from the light-emitting surface. The sensor further includes an interposed element which can be inserted into and withdrawn from a space formed between the light-emitting element and the light-sensitive element.
When a sheet passes the point in the paper path where the PI sensor is mounted, the sheet goes into contact with the interposed element, forcing the interposed element from within the space between the light-emitting element and the light-sensitive element to the outside of the space. More specifically, when forced by the sheet, the interposed element swings by a specific angle and moves from within the space between the light-emitting element and the light-sensitive element to the outside thereof. When moved to the outside of this space, the interposed element does not interrupt the light emitted from the light-emitting surface, whereby the PI sensor detects that the sheet has passed the particular point in the paper path.
If no sheet passes the point in the paper path where the PI sensor is mounted, the interposed element does not swing and thus remains in the space formed between the light-emitting element and the light-sensitive element. In this case, the interposed element interrupts the light emitted from the light-emitting surface, whereby the PI sensor detects that no sheet has passed the particular point in the paper path.
Since the sheet is transported along the paper path in sliding contact with various elements provided therearound, such as a transport roller or a transport guide plate, a static charge is accumulated in the sheet as a result of friction. If a discharge of the accumulated static charge occurs directly at the PI sensor, then a breakdown of a control board of the PI sensor, for example, may potentially occur.
One approach to the solution of this problem is shown in Japanese Unexamined Patent Publication No. 2005-162342, which proposes the provision of a grounding plate attached to a PI sensor for protecting the sensor from a discharge of static electricity. Specifically, the grounding plate described in this conventional approach is a flat-shaped plate fitted to a paper path close to a light-emitting element and a light-sensitive element of the PI sensor, the grounding plate being arranged to cover the entirety of surfaces of the light-emitting element and the light-sensitive element facing the paper path. With this arrangement, the static electricity is discharged to the grounding plate so that the PI sensor is protected from the discharge of the static electricity.
However, the aforementioned grounding plate is flat-shaped so that the grounding plate must have a larger surface area than a total area of the surfaces of the light-emitting element and the light-sensitive element facing the paper path in order to protect the PI sensor from the discharge of the static electricity. Considering, in particular, a mechanical error which occurs when the grounding plate is mounted to the PI sensor, it is necessary that the grounding plate have a large surface area.
In addition, since the grounding plate is flat-shaped, a discharge of static electricity which occurs from a sheet may not directly reach the grounding plate but the PI sensor, if the surface area of the grounding plate generally equals the total area of the surfaces of the light-emitting element and the light-sensitive element facing the paper path. This is another reason why the grounding plate must have a large surface area to ensure that the discharge of static electricity would easily reach the grounding plate.
If, however, the surface area of the grounding plate is so increased, the space between the light-emitting element and the light-sensitive element will be reduced. This would make it difficult to smoothly insert and withdraw the interposed element into and out of the space between the light-emitting element and the light-sensitive element and, as a consequence, it will be difficult that the PI sensor properly detects whether the sheet has passed the particular point in a paper path.

Sheet transport device and image forming apparatus employing the same


Provided is a muscle stem cell in vitro culture method. A muscle stem cell is cultivated in vitro by using a cell culture medium of a cell factor added with a blood cell or a conditioned medium of the blood cell. Also provided is a culture medium used in the muscle stem cell in vitro culture method and an application thereof.

Muscle stem cells are responsible for the postnatal muscle mass gain and muscle regeneration. Muscle stem cells are non-tumorigenic in vivo. The application of muscle stem cells have no ethical problems faced by embryonic stem cells. They therefore display wide application prospects to treat various muscle degenerative diseases such as muscle wasting and dystrophy etc. One of the major obstacles preventing the application of muscle stem cells in clinic is the lack of method to support long term muscle stem cell culturing in vitro. Similar to the majority of adult stem cells, muscle stem cells can only divide for 2-4 times in the in vitro culturing system and can hardly be serially expanded.
The current protocols to culture muscle stem cells (satellite cells) are largely all based on the method established by Dr. Bischoff in 1986. The method was further optimized by Dr. Beauchamp et al. and it cultures muscle stem cells in F10 basal culture medium supplemented with 10 ng/ml FGF. Under this culture condition, muscle stem cells can divide 3-5 times. When muscle stem cells are continuously expanded, they will go through a major crisis. During the major crisis, most of the cells die. The survived cells differentiate to progenitor cells losing the stemness. Therefore, after culturing in vitro for 1-3 passages (3-12 days), all the isolated muscle stem cells differentiate to progenitor cells losing the stemness. And the molecular markers of muscle stem cell cannot be detected in these progenitor cells. These progenitor cells show very low efficiency to repair muscle injury in vivo. They are unable to form functional stem cells in vivo after injury reparation and fail to repair secondary injury after transplantation. (Bischoff P. A satellite cell mitogen from crushed adult muscle. Dev Biol., 1986. 115(1): 140-147. Beauchamp, J R, et al., Expression of CD34 and Myf5 defines the majority of quiescent adult skeletal muscle satellite cells. J Cell Biol. 2000. 1546): p. 1221-34.) That is, the muscle stem cells will go through a crisis phase if the current in vitro culturing system of muscle stem cells is applied. After the crisis, the majority of the cells with the ability to proliferate have become muscle progenitor cells and lose the ability to repair muscle injury in vivo. Due to the presence of the said problem, the genetic correction in muscle stem cells to treat muscle degenerative diseases is difficult to be applied in clinic.

Muscle stem cell in vitro culture method and application

Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences


In a method and magnetic resonance apparatus to determine a B0 field map describing the local deviation from a nominal Larmor frequency of the magnetic resonance apparatus, magnetic resonance data are acquired at at least two different dephasing times after an excitation, in measurements implemented at two different echo times whose difference forms a dephasing time, and a phase change used to determine the B0 field map is determined from a difference of phases measured at different echo times. The phase changes of different dephasing times are evaluated to at least partially reduce an ambiguity due to Nyquist phase wrapping. The measurements for different dephasing times are implemented at least in part with excitations that generate different excitation fields.

Field of the Invention
The present invention concerns a method to determine a B0 field map that describes the local deviation from a nominal Larmor frequency of a magnetic resonance device, wherein magnetic resonance data are acquired in measurements implemented at two different echo times whose difference forms a dephasing time, after an excitation at at least two different dephasing times; and a phase change to be used to determine the B0 field map is determined from a difference of phases measured at different echo times; wherein the phase changes of different dephasing times are evaluated for at least partially reducing an ambiguity due to Nyquist phase wrapping.
Description of the Prior Art
Magnetic resonance imaging and its basic operation are widely known in the prior art. A subject to be examined is introduced into a basic magnetic field with a relatively high field strength (known as the B0 field). In order to be able to acquire magnetic resonance data, for example in a slice of a subject, the nuclear spins of this slice are excited and the decay of this excitation is detected as a signal, for example. Gradient fields can be generated by a gradient coil arrangement while radio-frequency excitation pulses (which are frequently designated as radio-frequency pulses) are emitted via a radio-frequency coil arrangement. The entirety of the radio-frequency pulses (excitation) generates a radio-frequency field that is typically designated as a B1 field, and the spins of resonantly excited nuclei are deflected (with a spatial resolution due to the gradients) by an angle known as a flip angle relative to the magnetic field lines of the basic magnetic field. The excited spins of the nuclei then radiate radio-frequency signals that can be acquired and processed further by suitable reception antennas (such as by the radio-frequency coil arrangement itself) in order to thus be able to reconstruct magnetic resonance image data therefrom.
Conventional radio-frequency coil arrangements are operated in a mode known as the "homogeneous mode", for example in a CP mode (circularly polarized mode), wherein a single radio-frequency pulse is emitted with a defined, fixed phase and amplitude to all components of the transmission coil, for example all transmission rods of a birdcage antenna. To increase flexibility and to achieve new degrees of freedom to improve the imaging, it has been proposed to also enable a mode known as a parallel transmission (pTX), in which multiple transmission channels of a radio-frequency coil arrangement are individually charged with individual pulses that can deviate from one another. This entirety of the individual pulses (which, for example, can be described via the parameters of phase and amplitude) is then defined as a whole in a control sequence (protocol) that is described by a corresponding parameter set. Such a multichannel pulse (excitation) that is composed of individual pulses for the different transmission channels is often designated as a "pTX pulse" (for "parallel transmission"). In addition to the generation of spatially selective excitations, field inhomogeneities can also be compensated (for example within the scope of "RF shimming").
In order to determine control parameter sets of a control sequence, it is necessary to know the background (thus the B0 field), as well as the effects of the individual transmission channels in the imaging region (in particular the homogeneity volume).
For measurement of the basic magnetic field (B0 field)—designated as a B0 mapping—first magnetic resonance data are typically acquired (preferably by gradient echo imaging) at two different echo times. The phase difference (phase change) of the magnetic resonance data acquired at different echo times (which can be determined by subtraction of the phases of two magnetic resonance images of the first magnetic resonance data that are acquired at different echo times) is proportional to a deviation of the local B0 field from the nominal basic magnetic field strength and to the dephasing time (thus the difference of the two echo times). The field deviation is thereby specifically described by a deviation of the Larmor frequency from a nominal Larmor frequency of the magnetic resonance apparatus (a value describing this deviation is designated as a Larmor frequency value in the following).
The phase generated by deviations in the homogeneity of the B0 field thus develops over time. The effect of the Nyquist phase wrapping must be taken into account because the proportionality of the phase difference of magnetic resonance data acquired at different times to the deviation from the nominal Larmor frequency, and to the difference of the echo times, applies only as long as the phase difference (limited to 2π) corresponds to the actual phase evolution. However, the phases can be further developed by multiples of 2π depending on the dynamic range of the B0 distribution. This leads to ambiguities and errors in the calculation of the B0 maps. Incorrect associations in the phase evolution show themselves in non-physical spatial discontinuities due to the 2π jumps in the phase difference images. This means that an extremely fast development of the B0 phase also occurs if the deviation of the local Larmor frequency from the nominal Larmor frequency is high, such that the phase will go beyond 2π when the echo time (here the difference of the two echo times) is not short enough, such that the described ambiguity occurs.
The selection of extremely short dephasing times is frequently not possible due to the sequences that are used, and so smaller deviations from the nominal Larmor frequency can no longer be measured with sufficient precision given an extremely short echo time difference.
A few approaches are known in the prior art to solve the ambiguity problem in the association of the measured phase change. It is thus possible to choose the dephasing time (thus the difference of the echo times) to be so short that the phases do not develop by more than 2π at any location during them. However, since the dynamic range of the B0 field distribution is not known before the measurement, the dephasing time must be chosen to be so short that the sensitivity of the acquisition method is not sufficient, and this procedure is consequently not used (as has already been explained).
Therefore, it was proposed to detect and correct phase jumps in the B0 maps in a post-processing, under the assumption that the B0 field is spatially continuous. Algorithms that have this effect are designated as phase unwrapping algorithms. However, the reliability of such algorithms is often questionable. The primary difficulty exists in that the entire volume can be comprised of non-contiguous partial regions, such that individual partial regions of the B0 maps are separated by voxels that only include noise and are very low in signal. The phase in these voxels can thus not be determined, or can only be determined unreliably.
It has also been proposed to iteratively acquire first magnetic resonance data with increasing dephasing time, consequently increasing difference between the echo times. The shortest dephasing time is thereby selected so that no spatial phase jumps occur. Whether a phase jump will occur given longer dephasing time is estimated from the acquisitions with shorter dephasing times. If this is the case, this is taken into account in the evaluation (reconstruction) of the first magnetic resonance data with longer dephasing time. The phase ambiguity is therefore dispelled, and long dephasing times are enabled for a high sensitivity.
A further alternative procedure is to minimize the phase gradients between adjacent voxels in the B0 maps. Given this solution, the B0 maps do not necessarily need to be corrected for phase jumps. However, the risk exists that a calculated B0 shim is optimized for false B0 offsets in different spatial areas. Moreover, no frequency (zeroth order shim) can be calculated from differential method.
Corresponding mapping processes are also known for B1 fields and are designated as "B1 mapping". Generally speaking, B1 field maps are acquired for each transmission channel, which means that the B1 field maps show how strong the B1 field is at a specific location in the imaging region given a specific excitation (for example a uniform excitation and/or given a defined transmitter voltage). This means that a complex B1 value (consequently a B1 amplitude and a B1 phase, which can also be differentiated in a B1 amplitude map and a B1 phase map) is associated with each voxel (image point). Typically, measurements for a number of excitation modes are conducted, wherein an excitation mode does not necessarily need to correspond to the operation of only one channel; rather, combinations are also conceivable from which the individual transmission channels can then be concluded.
In order to determine the amplitude of the B1 field, for example, it is known to measure the flip angle that a radio-frequency pulse causes, wherein reference is made to DE 10 2005 049 229 B3 as an example. An excitation mode thereby results in a constant phase shift (consequently a constant B1 field), wherein the B0 phase continuously varying over time (as it has been described) is, however, naturally also acquired as well in the phase measurement. Therefore, for B1 mapping it is known to use basically the same echo time for the different excitation modes, such that the effect of the B0 field on the phases is kept constant, such that a raw phase map obtained from the magnetic resonance data of one excitation mode can be used as a correction so that the stable effect of the B0 field on the phase cancels out, and consequently the phases of the excitation mode used for correction serve as a reference phase map. This means that all other B1 phase maps are defined relative to the B1 phase map used as a correction, which is, however, not problematic since it ultimately depends anyway only on the relative phases of the different transmission channels.

This patent is subject to a terminal disclaimer.

Method and magnetic resonance apparatus to determine a B0 field map


The invention is related to the foundry practice. According to this invention, the method for making castings by directed solidification from a selected point of the melt toward the periphery of the casting comprises forming a casting in a mold having thermodynamic characteristics that allow uniform volume cooling of the melt to be effected to a temperature at which natural solidification processes are completed. To improve the structural isotropy of the casting formed, the cooling is effected at a rate not exceeding 0.5° C./sec. The casting is formed in a nonuniform field of force. The nonuniform field of force is set up by ultrasonic waves focused on a selected point of the melt to form therein a localized elevated pressure zone and to direct the solidification front from the zone toward the periphery of the casting. The nonuniform field of force is sustained in the mold until the cooling casting reaches a temperature at which the natural melt solidification processes are completed as the melt cools. Before the melt is poured into the mold, it is overheated to a level that, together with the thermodynamic characteristics of the mold allowing the melt therein to be cooled at a rate not exceeding 0.5 K/sec, sustains the liquid phase of the melt for a time sufficient for directed melt solidification to be effected from the selected point of the melt toward the periphery of the casting before the commencement of natural melt solidification processes as the melt cools. Subsequently, as the temperature at which natural solidification processes are completed is reached, the nonuniform field of force is removed, and casting cooling may continue at any reasonable rate.

The need to effectively control solidification of a metal melt in a mold to make castings with acceptable practical service properties forces researchers and engineers to look constantly for new approaches in order to radically improve the quality of castings because castings acquire their basic service properties at the crystalline structure solidification stage.
Until recently, all methods for controlling processes developing during solidification of metal melts have been confined to influencing the thermal processes within the melt and at the heat exchange boundary. In this environment, the two-phase solidification front zone forming at the casting periphery obstructs removal of latent heat as it moves toward the center at a slowing rate, causing variation in the grain size and raising pressure within the melt as the contracting solid phase grows, and in this way provoking the release of dissolved gases into the melt. This organization of the solidification process is ineffective, to an extent, and results, no matter what option is used, in the casting grain size developing a gradient and hence anisotropy of properties. Moreover, when solidification is effected by heat removal, defects such as micro- and macro-voids and various forms of liquation cannot be avoided. Attempts are made to offset the structural defects of castings made by an existing method in which the melt is solidified from the periphery to the center thereof. A good example of this is a method in which a fine structure is produced by activating the melt with various impurities, mostly those having a higher melting point, the particles thereof serving as solidification centers. It is appropriate to interpret the mechanism in which solidification centers are formed as operation of "micro-refrigerators." More refractory inclusions have a stable crystalline structure at solidification temperatures of the host metal, and their atoms are able to "take away" some of the energy from the melt components in localized zones of the melt. This "take-away" energy creates conditions favorable enough to begin solidification in these zones.
A similar solidification mechanism develops when various alloys are used to "multiply" their structure within the melt, a process now known as "heredity." Whatever the method used to produce alloys, they have a structure fragmented considerably and have a slightly higher melting point than the host metal because of large contact surface areas of their components. Accordingly, dissolution of a partially molten alloy in the host metal, if slightly overheated, results in more solidification centers developing as in the example described above. Use of alloys, as also addition of a modifier to complete volume solidification to produce a fragmented structure gives rise to several problems. Production of a desired structure is influenced significantly by various parameters such as temperature, dissolution quality, distribution of alloy components over the melt volume, and a few other factors. Many research projects are centered on these problems. Also, excessive pressure is produced within the melt, for example, in a thermostatic gas chamber. In this example, interatomic distances are reduced, and interaction energy rises. Since, however, excessive pressure is built in all examples within the entire volume of the melt, and heat is removed, as it has been before, from the surface, the solidification front is directed from the periphery to the center, causing all possible casting defects typical of prior art methods. The only advantage to be gained from this method is possibly improved mold filling and an insignificant improvement in casting structure uniformity.
An analysis of defects developing during solidification suggests a conclusion that they ultimately result from the method in which solidification is conducted by removing heat from the casting surface.
Indeed, the solid peripheral phase, like the solidification front as well, shuts off the accompanying gas phase inside, contributing to blistering, cracking, liquation, and so on.
A method is, however, known in the art to be used for making castings by directed solidification of the melt (U.S. Pat. No. 1,424,952), wherein a casting is formed in a nonuniform field of force of a rotating mold as the melt volume is cooled in its entirety (rather than in a selected direction). The mold rotation speed is chosen in this case so as to expose the melt to a pressure required to overcool the melt to the extent equal to the interval of its metastability. In these conditions, undirected cooling of the melt causes solidification thereof to be directed from the periphery toward the rotation axis of the mold. This effect is achieved by the solidification temperature rising under the influence of pressure built up in the peripheral zones of the melt, being higher than pressure in zones closer to the rotation axis of the mold.
To put this method into practice, however, a high pressure is to be built up with the possibility of the casting mold containing the melt being broken.
Moreover, the constant rotation speed of the mold to produce the desired pressure results in anisotropy of the casting structure and strength characteristics because the solidification front shifts as overcooling decreases continuously toward the rotation axis of the mold.
Accordingly, the conclusion that can be drawn from the above is that a localized elevated pressure zone produced in the casting volume could allow solidification to be controlled effectively from that zone toward the casting periphery. A solidification front moving from that zone toward the periphery could allow gas pockets and unbound intermetallic compounds to be pushed out to the casting surface, prevent development of shrinkage cracks, blisters, and so on.

Method for making castings by directed solidification from a selected point of melt toward casting periphery


An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.

1. Field of the Invention
This invention relates to integrated circuit manufacture and more particular to a capacitor with enhanced area and dielectric formed by implantation of conductive and insulative layers within a polysilicon material.
2. Background of the Relevant Art
A capacitor is an electronic component capable of storing electrical energy. A capacitor consists of two conductive plates insulated from each other by a dielectric. The capacitance value is determined by the following formula: EQU C=kA/t
where, C=Coulombs/Volt (Farad), k=dielectric constant of the insulator, A=area of overlay of the plates, and t=thickness of the dielectric
Capacitors can be configured in many ways. The plates and adjacent dielectrics can take on a planar shape, a trenched shape, a stacked shape or a fin shape. A planar capacitor entails a dielectric placed between a pair of planar conductors, wherein the conductors can be polysilicon and/or silicon. The polysilicon and silicon are generally formed on or near the substrate topography. Each side of the plate is electrically connected to other active devices formed upon the substrate to complete the connection. In high density applications, capacitors are sometimes laid out in a trench such that the insulative and conductive regions extend into the substrate instead of across the substrate. A trench capacitor thereby occupies a substrate area roughly equal to the thickness of the dielectric and adjoining plates rather than the area of the plates. Another way in which to conserve substrate area is to stack the capacitor on top of the transistors to which they are connected. Stacking of capacitors was favorably introduced in DRAM applications where conservation of area is crucial. It is understood that "capacitor" set forth herein below comprises electrically conductive plates spaced from each other by an insulative material, wherein the plates and insulative material are arranged in a planar, trenched or stacked configuration.
An examination of capacitance value C indicates that in order to increase the capacitance, dielectric constant k and/or area A must be increased or, conversely, thickness t must be decreased. A majority of plated capacitors utilize silicon nitride as a preferred dielectric material. Silicon nitride is generally deposited from a chemical vapor deposition (CVD) chamber onto the lower conductive plate. The CVD reaction used for preparing high-temperature silicon nitride is as follows: 3SiH.sub.4 +NH.sub.3 .fwdarw.Si.sub.3 N.sub.4 +12H.sub.2. Silicon nitride is relatively impermeable to oxygen (as well as phosphorous and boron) and provides an efficient barrier against diffusion between the plates. More importantly, silicon nitride has a dielectric constant K much higher than, for example, silicon dioxide. While silicon nitride is the preferred dielectric, silicon nitride often exhibits numerous pinholes which may or may not extend through the nitride. Regardless of the CVD techniques used, silicon nitride remains more prone to pinholes that other dielectrics. Pinholes, resulting from deposition, must be avoided in order to ensure the conductive plates do not short to one another.
If the designer wishes to increase capacitance by decreasing dielectric thickness t, then he or she must address the problem of pinholes. As the deposited layer of silicon nitride becomes thinner, the propensity for catastrophic pinholes increases. Thus, a trade-off exists between dielectric enhancement (thickness minimization) and the presence of pinholes. Existing silicon nitride layers require a dielectric thickness placed upon the lower plate of generally more than 100 Angstroms in order to prevent substantial occurrence of pinholes. After the silicon nitride is deposited, a wet oxidation step is used to fill the pinholes. Thereafter, a second conductive plate of, for example, polysilicon is deposited over the silicon nitride dielectric to complete the plated capacitor configuration. Accordingly, conventional capacitors utilize four deposition steps: a first conductive deposition step, followed by an insulative deposition step, followed by a wet oxide step, followed by a second conductive deposition step. All four steps require two separate masking and photolithography steps thereby adding to the complexity of the manufacturing process. Moreover, the plated structure results in a relatively thick combination of conductive and insulative layers which, if placed on an even substrate surface, substantially adds to the unevenness of the circuit topography. Subsequent planarization steps involving selective removal of overlaying oxide and/or application of spin-on glass (SOG) are needed to re-planarize the upper surface.
In addition to increasing dielectric constant K and/or decreasing thickness t, capacitance C can be increased by increasing area A. Recent work has been performed in the area of texturization, in which additional area is provided at the juncture between the insulative layer and one of the adjacent conductive layers. Specifically, the conductive layer can be texturized after it has been deposited by growing a sacrificial oxide upon the upper surface of the conductive (generally polysilicon) layer. Doping of the underlying polysilicon prior to oxide growth enhances oxide growth rate and, when performed at a specific temperature, leads to a roughness or texture in the areas at which oxide is grown. Oxide grown upon the exposed surface of the deposited polysilicon is then removed leaving a roughened or textured upper surface on which silicon nitride is subsequently placed. The method of polysilicon texturization to enhance capacitor surface area is well studied and set forth in U.S. Pat. Nos. 5,043,780 to Fazan, et al.; 5,082,797 to Ghan, et al.; 5,102,832 to Tuttle; 5,138,411 to Sandhu; 5,191,509 to Wen; and 5,208,176 to Ahmad, et al. All of the above teach the importance of texturization, but in the context of depositing a polysilicon layer to be textured followed by deposition of a dielectric and another polysilicon thereover. For reasons stated above, deposition of separate layers not only is time consuming, costly and burdensome, but also increases the chances of pinholes existing in the dielectric as well as gross contamination occurring on the textured polysilicon before silicon nitride deposition. Any pinholes or contamination (which can lead to pinholes) existing within the dielectric will deleteriously effect capacitor performance regardless of any advantages of texturization. Accordingly, it would be advantageous to provide a processing methodology in which a capacitor is formed absent deposition of each layer (conductive and insulative layers). It would be further desirable to obtain the benefits of silicon nitride, as the dielectric at textured junctures, without having to undergo the disadvantages of pinholes, contamination, and added processing steps associated with layer-by-layer deposition.

Method of fabricating a capacitor with a textured polysilicon interface and an enhanced dielectric


A dish type antenna includes a board fixed to the back surface of a dish, a frame having a lower portion fixed to a base and an upper portion pivotally coupled to the board at a pivot axle, and a cylinder pivotally coupled between the base and the board so as to rotate the dish about the pivot axle. The antenna includes a simplified configuration and can be easily disengaged and removed.

1. Field of the Invention
The present invention relates to an antenna, and more particularly to a dish type antenna.
2. Description of the Prior Art
Two typical dish type antennas are disclosed in U.S. Pat. No. 4,652,890 to Crean, filed Jul. 24, 1984, and U.S. Pat. No. 4,804,971 to Bruns et al., filed Apr. 16, 1986. Both of the antennas include a post mounted within ground by being embedded in a poured concrete base or support, such that the antennas can not be easily removed when required, for example, when hurricane comes. In addition, both of the antennas include a complicated configuration, which is adverse for both manufacturing and assembling purposes.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages of the conventional dish type antenna.


Mucoadhesive buccal films comprising a statin-hydroxypropyl-beta-cyclodextrin inclusion complex and a statin-loaded mixed micelle composition, wherein the ratio of the mixed micelle composition to the inclusion complex is from 2:0.5 to 2:1.5 are provided. Methods of improving permeation of a statin across mucosal tissue by administering the film to a subject are also provided.

Statins are indispensable for lowering blood cholesterol levels and are increasingly being used to manage cardiovascular disorders, a major cause of death and morbidity around the world [1]. However, many statins suffer from poor solubility and thus low bioavailability.
Different strategies have been reported to improve drug solubility and dissolution in order to achieve a suitable systemic drug concentration and a desired pharmacological effect. These strategies can be classified into physical, chemical and other miscellaneous modifications techniques [6]. Reduction in a drug's particle size by micronization and nanosuspension formation, crystalline change by polymorph and amorphous/crystallin modifications, drug dispersion in hydrophilic carriers (solid dispersions), solid solutions and cryogenic methods are examples of physical modifications [7-11]. Derivatization, salt formation and complexation are common types of chemical modifications [12,13]. Cosolvency, hydrotropes, addition of surfactants and solubilizers, and supercritical fluid technology are good examples of other modifications [14-16].
Mucoadhesive buccal films are pharmaceutical dosage forms that utilize a water-dissolving polymer that allows the prepared films to quickly hydrate, adhere and dissolve when placed in the buccal, palatal, gingival, lingual, sublingual or cheek mucosa of the buccal cavity [20,21]. They are promising drug delivery systems that release their drug content directly toward the buccal mucosa with subsequent drug absorption through the venous blood system that drains from the cheek. Accordingly, development of these films has the advantage of avoiding the hepatic first pass effect [22].
Due to the bioavailability problems with oral delivery of statins, alternative and effective drug delivery systems are needed.

Mucoadhesive buccal film having a dual release carrier system


The object of a process and an arrangement for producing dose profiles for the fabrication of structured surfaces with a beam which is used for exposure and is directed on the surface consists in arranging the surface irradiation in such a way that the processing times and material outlay required for fabrication of micro-lenses and micro-lens arrays can be substantially reduced. According to the invention, the beam has at least one shaped region in cross section, which shaped region is movable relative to the surface and whose extent in the movement direction of the relative movement, in combination with the velocity of the relative movement, determines the dose. Effective lithographic fabrication of lens structures, in particular micro-lenses and micro-lens arrays, can be realized with the invention.

a) Field of the Invention
The invention is directed to a process and an arrangement for producing dose profiles for the fabrication of structured surfaces with a beam which is used for exposure and is directed on the surface.
b) Description of the Related Art
Devices and processes employing the technique of variable dose writing to fabricate surface profiles for electron-beam lithography and photolithography are known (T. Fujita, H. Nishihara, J. Kayama, "Blazed grating and Fresnel lenses fabricated by electron-beam lithography", Opt. Lett. 7 (1982) 12, p. 578; M. Haruna, M. Takahishi, K. Wakahayhashi, H. Nishihara, "Laser beam lithographed Micro-Fresnel lenses", Applied Optics/Vol. 29, No. 34/1 December 1990).
The fact that the dissolve rate of a radiation-sensitive resist in the developer bath can be predetermined by the radiation dose introduced in the resist is made use of. Accordingly, it is possible to design the lateral radiation dose distribution in such a way that the desired surface profile is obtained after a certain period of time following development. FIG. 14 illustrates this procedure schematically.
However, the high cost of the facilities for producing the dose profiles required for this process poses problems, since the systems which have been used up to now, such as electron-beam writing devices or laser pattern generators, are physically large and very expensive. Further, very long processing times are necessary for extended surface profiles. The fabrication of micro-lenses and micro-lens arrays especially is highly time-consuming. Further, the amounts of data needed to write the required dose profiles are sometimes enormous, requiring a corresponding expenditure on computer technology.

Process and arrangement for producing dose profiles for the fabrication of structured surfaces


A method and system for providing energy assisted magnetic recording (EAMR) heads including EAMR transducers are described. The method and system include aligning a laser bar to the EAMR heads on a substrate. The laser bar includes lasers in locations corresponding to a portion of the EAMR transducers. The method and system also include bonding the laser bar to the substrate and removing a portion of the laser bar to separate the plurality of lasers. The substrate is separated into the EAMR heads.

FIG. 1 depicts a side view of portion of a conventional energy assisted magnetic recording (EAMR) disk drive 10. The conventional EAMR disk drive 10 includes a recording media 12, a conventional slider 20, and a conventional laser diode 30 that are typically attached to a suspension (not shown). The conventional slider 20 has a leading edge 22, a trailing edge 26, and a back side 24. Other components that may be part of the conventional EAMR disk drive 10 are not shown. The conventional slider 20 is typically attached to the suspension at its back side 24. A conventional EAMR transducer 28 is coupled with the slider 20.
The laser diode 30 is coupled in proximity to the EAMR transducer 22 on the trailing edge 26 of the slider 20. Light from the conventional laser diode 30 is provided substantially along the optic axis 32 of the conventional laser diode 30 to the trailing edge 26 of the slider 20. More specifically, light from the laser diode 30 is provided to a grating (not shown) of conventional EAMR transducer 22. The light from the laser diode 30 coupled into the grating is then provided to a waveguide (not shown). The waveguide directs the light toward the conventional media 12, heating a small region of the conventional media 12. The conventional EAMR transducer 22 magnetically writes to the conventional media 12 in the region the conventional media 12 is heated.
FIG. 2 depicts a conventional method 50 for fabricating a portion of the conventional EAMR disk drive 10. For simplicity, only a portion of the method 50 is described. The conventional EAMR transducer 28 is fabricated on a conventional substrate, such as an AITiC substrate, via step 52. Typically, a reader for the conventional disk drive 10 has already been fabricated. Thus, the conventional EAMR transducer 28 is built on other structures. Typically, multiple transducers are fabricated in parallel on the same substrate.
Once fabrication of the conventional EAMR transducer 28 is completed, the laser diode 30 may be mounted in proximity to the conventional EAMR transducer 28, via step 54. More specifically, the laser diode 30 is mounted in proximity to the trailing surface 26 of the slider 20. The EAMR heads may then be separated, via step 56. For example, the substrate holding the EAMR transducers 28 may be cleaved or otherwise cut into individual sliders 20. The front side of the substrate, on which the EAMR transducer 28 is fabricated, becomes the trailing edge 26 of the slider 20. In other conventional methods, the EAMR heads are separated prior to the laser diode 30 being mounted. However, in both cases, the laser diode is mounted in proximity to the EAMR transducer 28. The fabrication of the conventional drive 10 may then be completed. For example, the conventional EAMR head including the conventional slider 20 and conventional EAMR transducer 28 may be mounted on a flexure and then in a disk drive.
Although the conventional EAMR disk drive 10 and method 50 may function, improvements are desired. More specifically, aligning the laser 30 to the desired position with respect to the conventional transducer 28 is time consuming and prone to error. Further, the throughput and yield of a manufacturing for fabricating the conventional EAMR disk drive 10 may be adversely affected. Other conventional methods have proposed using a coupling mechanism, such as an optical fiber (not shown) to transmit light from the laser 30 to the conventional transducer 28. However, such methods have analogous drawbacks.
Accordingly, what is needed are improved methods and systems for fabricating EAMR disk drives.

Method and system for mounting lasers on energy assisted magnetic recording heads


A method and an apparatus for processing food into a tubular shape is provided in which a die for processing the food includes a guide plate having a material outlet and a cylindrical feed pin having a water outlet at its center co-axially housed in the material outlet. The guide plate and feed pin cooperatively define a ring-like opening. Food material is extruded out of the ring-like opening in a tubular shape. Simultaneously, hot water is expelled out of the water outlet of the feed pin, flows into and fills a hollow inside the tubular food material. The hot water in the hollow prevents the wall of the tubular food material from collapsing and also accelerates coagulation of the food material. Food material is thus continuously processed into a tubular shape. An extruding die for performing the described method is also provided.

There are presently known a wide variety of processed foods in a tubular shape, such as macaroni made of flour and the Japanese processed food known as "chikuwa" which is made mainly of fish. In addition, in the Japanese Utility Model Application No. 6-4815 the inventor of the present invention proposed a "konnyaku" in a tubular shape similar to the shape of macaroni and chikuwa. "Konnyaku" is a jelly-like Japanese processed food which conventionally takes the shape of a bar of soap or noodle. Specifically, konnyaku is made from "Konnyaku potatoes" including glucomannan. When the glucomannan absorbs water, its expands and becomes an extremely larger volume colloid having high viscosity. When this colloid is added to lime water and other substances and heated, it coagulates as a translucent and elastic lump.
The above mentioned tubular foods are shaped in various manners. For instance, chikuwa is made by applying fish paste to the periphery of a rolling pin and baking or steaming it. Macaroni is shaped by extruding a kneaded mixture of flour and water out of a ring-like opening.
Tubular konnyaku, on the other hand, has not been commercially produced because of technical difficulties. For instance, the method for producing chikuwa is not appropriate for konnyaku. Specifically, the rolling pin around which the konnyaku material would be applied must be removed after the material has coagulated. When the material is konnyaku, it is tremendously difficult to pull away the rolling pin without destroying the desired tubular shape. Therefore, it is not feasible to produce tubular konnyaku, especially with small diameters, through the same method used to produce tubular chikuwa. Even if the tubular konnyaku to be formed is of a relatively larger diameter, the productivity would be too limited to realize commercial production.
The method for producing macaroni is also inappropriate for processing konnyaku since the wall of konnyaku material defining the hollow tubular shape tends to collapse because of its higher flowability, and spoil the desired hollow tubular shape of the final product before it coagulates.

Apparatus for processing food into tubular shape


The invention concenrs giant ring compounds containing about 20 to about 160 atoms in the backbone of the ring and methods for preparing the giant ring compounds.

The present invention relates to the composition of giant ring compounds and methods for preparing the giant ring compounds.
Phospholipids, a major constituent of biological membranes, typically possess two chains of 14-18 carbons each of which are linked to the glycerol backbone by means of ester functionalities. Such compounds are stable at ambient temperature and neutral pH, but readily decompose at: elevated temperatures; in highly acidic media; and/or in enzymatic reactions catalyzed by esterases. Furthermore, since the hydrophobic chains are connected only at one end, they have a certain amount of freedom within the membrane bilayer to wiggle, bend, and interdigitate.
It has been observed that thermophilic archaebacteria are fully functional at temperatures up to 90.degree. C. and some at external pH values as low as 0.5. The ability of these bacteria to thrive under such adverse conditions is believed to be due in part to the unique lipids present in the plasma membrane. Two of the unique features of lipids of the plasma membrane being that they are macrocyclic and have a complete absence of ester linkages. The lack of ester linkages results in enhanced stability of such lipids to enzymatic hydrolysis by esterases, in addition to the temperature and pH stability. The cyclic nature of the lipids from archaebacteria is characterized as long isoprenoid chains bound through ether linkages to two polar heads; the two polar heads being either two glycerols or one glycerol and one nonitol. See, for example, Rosa et al., J.C.S. Chem. Comm. 514-515 (1977); Yamauchi et al., Biochim. Biophy. Acta 1003, 151-160 (1989); Yamauchi et al., J. Am. Chem. Soc. 112, 3188-3191 (1990).
Due to the unique properties of the lipids from archaebacteria, there is interest in using such lipids to form thermal, enzymatic, and pH stable membranes as liposomes for drug and pesticide delivery, for use in cleaning products, and for use in high performance fluids such as high temperature lubricants. However, it is difficult to obtain the bacterial lipids from natural sources and chemical synthesis is not an easy task.
Synthetic procedures for making macrocyclic rings having 12 to 20 atoms in the backbone of the ring include a method for preparing ether-linked phospholipids based on regiospecific opening of glycidyl derivatives mediated by boron trifluoride as described by Guivisdalsky et al. J. Org. Chem. 54, 4637-4642 (1989).
Yamauchi et al. J. Am. Chem. Soc. 112, 3188-3191 (1990) describe the synthesis of 1,1'-(1,32-dotriacontamethylene)-bis-(2-phytanyl-sn-glycero-3-phosphocholi ne) as a model to study the macrocyclic lipids.
McMurry et al. J. Am. Chem. Soc. 112, 6942-6949 (1990) describe a process for forming macrocyclic diols having a 14-membered carbocyclic ring. None of the procedures currently used have been effective in preparing macrocyclic lipids having greater than 12 to 20 atoms in the ring in significant yields.
It would therefore be advantageous to synthetically produce macrocycles having greater than 20 atoms in the backbone of the ring whereby the hydrophobic chains are linked to a polar backbone. It would also be advantageous to have macrocycles of greater than 20 atoms where the hydrophobic chains are linked to a glycerol backbone by means of ether functionalities. Such macrocycles have enhanced thermal stability, chemical stability, photolytic stability and enzymatic stability compared to previously synthesized cyclic stuctures which contain ester linkages.


A method of producing single-crystal silicon is disclosed. Polycrystalline silicon rod is formed from polycrystalline silicon granules, lumps or a mixture thereof by continuous casting through electromagnetic induction. Then, silicon single cyrstal is grown from the polycrystalline silicon rod by the FZ method.

1. Field of the Invention
The present invention relates to a method for producing silicon single crystal, which can be used as a material for semiconductor devices, solar cells and the like.
2. Background of the Invention
Single-crystal material, in particular single-crystal silicon in large volume, is an essential material for the development of highly effective solar batteries (solar cells). There are primarily two processes for forming single-crystal silicon. A single-crystal silicon rod obtained by the Float Zone (FZ) method, is recognized to have the highest quality among current methods. The Czochralski (CZ) method, an alternative to the FZ method for providing single-crystal silicon, cannot eliminate the defects caused by dissolved oxygen due to the use of a silica (quartz) crucible. FIG. 2 shows a manufacturing method for a single-crystal silicon rod according to the FZ method.
The conventional manufacturing method for a single-crystal silicon rod in accordance with the FZ method uses as a starting material, a polycrystalline silicon rod manufactured by the Siemens process. The Siemens process is described in Ger. Offen 1,102,117. A polycrystalline silicon rod (50) is partially melted by inserting the material into an induction coil (40a) to form a single-crystal silicon rod (51) which is further inserted into a second induction coil (40b) to provide the product of a single-crystal silicon rod (52). Two FZ melting steps are required to fully exhaust gas contained in the material (50) as instructed in manufacturing manuals published by the developers of the FZ method.
The conventional method provides a single-crystal silicon rod of a long lifetime, high specific resistance and the like, each essential for the solar cells, but at a high cost and price. The economics of production by the conventional method hinders provision of single-crystal silicon in a large volume for solar cells.
The reasons for the high cost to produce the single-crystal silicon by the FZ method are mainly as follows:
(1) There is a high cost to produce the starting material polycrystalline silicon rod by the Siemens process.
(2) There is high loss of the polycrystalline silicon rod manufactured by the Siemens process in preparing the rod for FZ melting. Due to irregularities in the outer diameter of the rod manufactured by the Siemens process, the outer surface of the rod must be shaped in order to fit between the induction coils for FZ melting. This introduces waste of polycrystalline silicon.
(3) Two FZ melting process steps must be performed to obtain high quality single-crystal silicon rods. A single FZ melting is insufficient to obtain high quality single-crystal silicon.
The reasons for the high cost associated with producing polycrystalline silicon by the Siemens process is as follows. This process is conducted basically in batch production and is thereby low in production efficiency. The Siemens process has the additional drawback in that the surface area for deposition of silicon is smaller with respect to the furnace capacity. Further, the furnace surface dissipates heat rapidly, thereby leading to a high cost of production.
In recent years, the fluidized-bed granulation process, as an alternative to the Siemens process has been given attention as a manufacturing method for polycrystalline silicon. The applicant has developed this process (Japanese Patent Applications Nos. 324010/1988, 100929/1989, 100930/1990).
The fluidized-bed granulation process continuously grows polycrystalline silicon granules in a fluidized-bed reactor (FBR) and extracts them therefrom, so that the process is substantially high in production efficiency in comparison with the Siemens process of batch production. Further, the ratio of the surface area for deposition of silicon with respect to the capacity of a FBR is especially larger, thereby providing definite advantages in productivity, efficiency of power consumption and the like, and a notably lower cost to produce polycrystalline silicon in comparison with the Siemens process. While fluidized-bed granulation efficiently produces polycrystalline silicon granules, the granules are inappropriate for direct crystallization by the FZ method due to low quality as well as small size.
Despite the existing methods, no one has provided an economical process for producing polycrystalline silicon rods of high quality from the cheap granules.

Method for producing silicon single crystal from polycrystalline rod formed by continous casting


Embodiments of the invention include a fracture ring sensor and a method of using the same to detect out of tolerance forces. Aspects of the invention include a product having a defined an out of tolerance force, a fracture ring sensor, and a mounting assembly coupling the fracture ring sensor to the product. The fracture ring sensor is patterned with a conductive trace and is manufactured to break when subjected to a predetermined amount of force. The predetermined amount of force is substantially equal to a percentage of the out of tolerance force of the product.

The present invention generally relates to stress monitoring systems, and more specifically, to a fracture ring sensor and a method of using the same to detect out of tolerance forces.
Deflection, torque, and insertion forces are important characteristics of various components in many products for which there are specific critical tolerances. Detecting cases where these deflection, torque, or force tolerances have been exceeded can be important to maintaining a product and to prevent unsafe operating conditions. A printed Circuit Board Assembly (PCBA), for example, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks, or signal traces etched from copper sheets laminated onto a non-conductive substrate. The electronic components can include circuit elements such as capacitors, resistors, or active devices. Damaging the PCB during manufacture, installation, or handling can cause these electronic components or the PCB itself to fail.
One type of failure in the printed circuit board assembly is a strain-induced failure. Strain-induced failures can be caused by subjecting the PCB to sufficiently large deflection, torque, insertion, or shock forces (also known as out of tolerance forces). These strain-induced failures can result, for example, in cracked BGA (ball grid array) solder joints, intermittent opens of conductive traces and joints, cracked printed circuit boards (PCB) and cracked capacitors. Inadvertently operating a damaged PCB or component often exacerbates the problem as powering damaged circuitry can cause further damage to the equipment as well as to electrically coupled components. Damage associated with strain-induced failures reduces overall device yields and profitability.
To ensure product quality and reliability, PCB and component manufacturing and handling standards provide product specific critical tolerances that should not be exceeded. Monitoring for, and detecting, cases where deflection, torque, or other force tolerances have been exceeded is challenging but is necessary to maintain a profitable product line and to prevent unsafe operating conditions.

INTERNATIONAL BUSINESS MACHINES CORPORATION


An encoding/decoding processor includes a coprocessor that is dedicated to encoding and decoding processes, where the coprocessor comprises: a parameter register that stores externally given operation modes and the settings of generation polynomials; and a calculation circuit that operates on the basis of the operation modes and the generation polynomials and that performs calculations, which are required for the encoding and decoding processes, by a plurality of bits per cycle in a parallel manner, and the coprocessor further comprises memory controllers, which include: address generator circuits for outputting the addresses of the storage devices; FIFO circuits for temporarily storing data; and data packing circuits for making up predetermined numbers of bits of data for output.

In a wireless communication system transmitting and receiving digital data, it is generally required to perform encoding/decoding processing of transmission/reception data signals. More specifically, on the transmission side, encoding processing such as adding CRC code to transmission data signals, scrambling processing, convolution encoding, and interleave (data rearrangement) processing is required. On the reception side, decoding processing such as de-interleave (inverse of interleave) processing on reception data signals, Viterbi decoding, de-scrambling processing, and CRC judgment processing is required.
In such encoding/decoding processing, calculations are performed with a bit unit or a byte unit. Thus, such processing may be referred to as bit/byte processing in some cases. Conventionally, such encoding/decoding processing has been achieved through mounting exclusive hardware circuits for each of the corresponding processing in order to deal with the encoding/decoding processing of a single wireless communication system at a high speed and with low power consumption.
Further, recently, there is an increasing expectation on a software wireless technique which makes it possible to deal with a plurality of wireless systems with a single device. Among the various kinds of normalized or standardized wireless systems, the contents of the encoding/decoding processing are similar to each other. However, the processing data unit, a part of processing parameters in calculations, the calculation order, and the like thereof are different.
However, to deal with the encoding/decoding processing of the plurality of wireless systems with the method of mounting the exclusive hardware circuit for each of the wireless communication systems, the corresponding numbers of exclusive hardware circuits are required for the number of the wireless systems to be dealt with. This causes an issue that the area of the circuits to be required and the cost thereof are increased. Further, it is also an issue that the flexibility for changes and expansions of the processing is low.
As a technique that can overcome such issue, depicted in Patent Document 10 to be described later is a technique which makes it possible to achieve both the high-speed characteristic and the power efficiency by dealing with a plurality of wireless systems through making the exclusive hardware circuit as the structure that can be set by various parameters. This is designed to deal with a plurality of wireless systems flexibly by constituting an exclusive processing engine to be resettable so as to be able to deal with a plurality of kinds of base band processing.
Further, as a technique similar to that, Patent Document 1 discloses a technique with which the exclusive hardware circuit is structured to be capable of setting operation modes and it is controlled from a central overall control processor to flexibly deal with system changes and the like.
Further, Patent Document 7 discloses a technique which performs processing on the encoding/decoding processing corresponding to a plurality of wireless systems with software by using a processor such as an exclusive signal processor (DSP) or the like. This is a technique which flexibly corresponds to various kinds of communication systems by achieving communication processing through using a typical signal processor and a DMA controller for increasing the speed of access to the memory in order to secure the flexibility.
Further, as a technique similar to that, Patent Document 2 discloses a technique which reduces memory access latency of a processor through providing an exclusive memory controller on the outside of a signal processing processor.
As other related techniques, Patent Document 3 discloses an image-processing signal processor capable of having a built-in magnification variable function while suppressing increase in the circuit scale by using a single memory port. Patent Document 4 discloses a logic integrated circuit capable of saving the space of the operation logic through structuring it to be capable of executing adding processing and multiplication processing in parallel.
Furthermore, Patent Document 5 discloses a communication system which sets a parameter regarding communications by a forward pilot tone and a reverse pilot tone. Patent Document 6 discloses a multiprocessor system which improves the efficiency of data transfer among a plurality of processors through compressing data locally before transferring it to a shared memory.
Patent Document 8 discloses a processor design tool and the like including an address generating unit which calculates an address every time according to a command. Patent Document 9 discloses a communication system that uses a processor that includes a register file used for calculation provided inside thereof.    Patent Document 1: Japanese Unexamined Patent Publication 2000-295309    Patent Document 2: Japanese Unexamined Patent Publication 2001-034573    Patent Document 3: Japanese Unexamined Patent Publication 2006-155637    Patent Document 4: Japanese Unexamined Patent Publication 2007-295128    Patent Document 5: Japanese Unexamined Patent Publication 2008-187722    Patent Document 6: Japanese Unexamined Patent Publication 2010-092499    Patent Document 7: Japanese Patent Application Publication 2002-541693    Patent Document 8: Japanese Patent Application Publication 2003-518280    Patent Document 9: Japanese Patent Application Publication 2005-516432    Patent Document 10: Japanese Patent Application Publication 2009-505608
The first issue is that it is not possible to flexibly deal with various kinds of encoding/decoding processing of a plurality of wireless communication systems in the encoding/decoding processing (bit/byte calculation processing) of a wireless communication apparatus.
The reason is as follows. Regarding the content of encoding/decoding processing in general, each processing among the plurality of wireless communication systems is similar in many cases. However, a part of processing parameters and calculation orders largely depend on the specifications of each of the wireless systems and the required calculation amount is relatively large. Therefore, conventionally, exclusive hardware circuits are mounted for each of the wireless systems.
However, in accordance with improvements in the processing capacity achieved due to the increases in the scale, the speed, and the like of recent system LSI, it is desired to achieve a wireless communication apparatus called a multimode wireless device or a software wireless device (SDR: Software Defined Ratio) capable of dealing with a plurality of wireless systems with a same encoding/decoding processing circuit. Further, it is also required to be the type capable of flexibly dealing with future specification changes and functional expansions.
The second issue is as follows. In a case where encoding/decoding processing (bit/byte calculation processing) is achieved by software processing by using a processor while placing a great importance on the flexibility in a wireless communication system, it is not possible to perform processing such as simultaneous calculations of a plurality of bits (bytes) at a high speed including memory access latency.
The reason is as follows. In order to process a single bit with the encoding/decoding processing in the wireless communication, information of a plurality of bits before and after that bit is required. Thus, it is not particularly an issue when executing the processing thereof in parallel with exclusive hardware circuits. However, in a case where it is to be achieved by software processing by using a processor while placing the importance on the flexibility and the expandability, it is difficult with a typical processor to simultaneously perform calculations of the encoding/decoding processing of a plurality of bits/bytes.
Further, in the case of the software processing by using the processor, the processor generally accesses to the memory, so that specific latency (the cycle number or delay time) is required. Therefore, the operability of the calculator is decreased for that and the processing time is increased, so that the processing cannot be performed at a high speed.
Note here that the processing amount of the encoding/decoding processing in the wireless communication generally depends on the required data transfer rate. The required data transfer rate is increased in the recent wireless systems, and the still lower power consumption is desired. Therefore, it is important to be able to perform high-speed communication with the still lower power consumption.
The technique capable of overcoming the issues described above is not depicted in each of the above-described Patent Documents. While it is possible with the technique depicted in Patent Document 10 to deal with changes in a part of the processing parameters of a calculation formula relatively easily by executing resetting, it is not possible to easily deal with changes in the processing data unit, the repeating number, the detailed calculation order, the processing order among each of the processing engines (exclusive hardware circuits), and the like.
In order to constitute it to be able to change the processing order and the like as well, the connection structure between each of the exclusive hardware circuits becomes extremely complicated so that the area of the device and the required cost are increased further. Also, it is still not possible to flexibly deal with future expected expansion of specifications such as changes in the calculation order and the like within processing engines.
Further, it is not possible with the technique depicted in Patent Document 1 to easily deal with changes in the detailed processing order, and the processing order and the like between each of the processing (exclusive hardware circuits) because of the same reasons.
In the meantime, with the technique depicted in Patent Document 7, the encoding/decoding processing of the wireless communication becomes special bit processing with the bit unit or the byte unit. Thus, the number of processing cycles is increased greatly with a typical signal processor compared to the case of the exclusive hardware structure that is capable of executing calculations of a plurality of bits in parallel. Further, while the flexibility for the changes in the processing is extremely high, the access latency from the processor to the memory, for example, comes to be in a state of performance overhead. Therefore, it is also difficult to increase the speed.
Even if a DMA controller is used for making an access to the memory, different cycles are required for a memory load/storing command and a calculation processing command in the case of the software processing executed by using the processor. Thus, the speed becomes slower compared to the case of the exclusive hardware processing, and the performance overhead of the bit shift processing and the like is required when the data unit to be processed by the processing and the data unit to be stored on the memory are different. For increasing the speed further in such case, it is necessary to increase the speed of the clock frequency. This results in increasing the power consumption and the heating value.
Further, with the technique depicted in Patent Document 2, the throughput at the time of data writing where the address and the data are transferred together while simply incrementing the address for an external memory is improved. However, the transfer cycles of the data corresponding to the addresses are different (2 cycles or more are required for reading out), so that the throughput at the time of reading out the data cannot be improved. Further, the addresses are for performing simple increment, so that it is not possible to deal with the special address order that is not the simple increment such as interleave/de-interleave processing in the coding/decoding processing of the wireless communication.
None of the other techniques depicted in Patent Documents 3 to 6 and Patent Documents 8 to 9 is designed to achieve encoding/decoding processing that can deal with a plurality of wireless communication systems at a high speed and with a simple circuit structure. Further, none of those is provided with the structure for that, so that such issues cannot be overcome naturally.
The object of the present invention is to provide the encoding/decoding processor and the wireless communication apparatus capable of achieving various kinds of encoding/decoding processing in a plurality of wireless communication systems at a high speed and with a simple circuit structure.

Encoding/decoding processor and wireless communication apparatus