A multi-stage centrifugal pump assembly includes at least two impellers (2, 6) and two impeller groups (4, 8) which are consecutive in a flow direction and each with at least one impeller (2, 6). A backflow channel (24) connects an exit side of the first impeller group (4) to an entry side thereof is located in a first impeller group (4) of the two impeller groups (4, 8).

The present invention relates generally to a multi-stage centrifugal pump assembly with at least two impellers, for example an at least two-stage centrifugal pump.
With such multi-stage centrifugal pump assemblies, several impellers are arranged one after the other in the delivery direction, so that a further pressure increase takes place from stage to stage. A problem with these centrifugal pump assemblies is that they firstly need to be bled and filled with fluid on starting operation. The centrifugal pump assemblies are not self-priming. This is disadvantageous with certain case of application, for example in fire extinguishing devices, with which a constant filling with fluid, in particular water cannot be ensured. It is important for the applied pumps to be self-priming in such devices.


A tunable filter having an electronically tunable center frequency and dynamic bandwidth control over a large tuning range. High-Q continuously tunable evanescent-mode cavity resonators and filters using reliable RF MEMS actuators. One embodiment is a 3.4-6.2 GHz (1.8:1 tuning ratio) continuously tunable electrostatic MEMS resonator with quality factor of 460-530, with a volume of 18×30×4 mm including the actuation scheme and biasing lines. A tunable resonators is also disclosed with a 2.8:1 (5.0-1.9 GHz) tuning ratio, and Q of 300-650.

This invention relates to electronic filters, and more particularly to tunable filters of the type used in radio-frequency (RF) systems such as RF communications and test equipment, for example, in RF front-end sections of receivers and transmitters.
The continuous rapid development of wireless communication technologies has led to significant growth of RF and microwave devices and systems for both civilian and military applications. This is particularly true for mobile applications with increased demands for high efficiency, small volume, low weight and low cost. Furthermore, there is a defining trend to combine multiple wireless communication functionalities into a single frequency-agile platform for multi-band and multi-standard operation with a lower overall system cost. While digital technologies and the associated signal processing have enabled the implementation of frequency agility at base-band, the design and implementation of the RF front-end components remain a significant challenge for mobile systems. Tunable filters suitable for band selection and image rejection constitute typical examples.
Most of today's practical tunable filters are based on the ferromagnetic tunability Yttrium-Iron-Garnet (YIG) resonators. YIG based tunable filters exhibit very wide tuning range over multiple octaves and very high quality factors (Q) of 10,000 at 10 GHz. Nevertheless, the large volume and high power consumption (0.75-3 W) of YIG based tunable filters hinder their integration into mobile communication systems. Many alternative approaches have been proposed to make miniaturized tunable RF/Microwave filters. These approaches are predominantly based on planar transmission line resonators loaded with solid-state varactors, ferroelectric-tuned varactors and MEMS varactors, switches and switched capacitors, as described, for example, in the following papers:    A. R. Brown et al., "A Varactor-Tuned RF Filter," IEEE Trans. Microwave Theory & Tech., Vol. 48, No. 7, pp. 1157-1160, July 2000;    F. A. G. Miranda et al., "Design And Development Of Ferroelectric Tunable Microwave Components For Ku- and K-Band Satellite Communication Systems," IEEE Trans. Microwave Theory & Tech., Vol. 48, No. 7, pp. 1181-1189, July 2000;    A. Tombak et al., "Voltage-Controlled RF Filters Employing Thin-Film Bariumstrontium-Titanate Tunable Capacitors," IEEE Trans. Microwave Theory & Tech., Vol. 51, No. 2, pp. 462-467, February 2003;    J. Nath et al., "An Electronically Tunable Microstrip Bandpass Filter Using Thin-Film Barium-Strontium-Titanate (BST) Varactors," IEEE Trans. Microwave Theory & Tech., Vol. 53, No. 9, pp. 2707-2712, September 2005;    D. Peroulis et al., "MEMS Devices For High Isolation Switching And Tunable Filtering," 2000 IEEE MTT-S Int. Microwave Symp. Dig., Vol. 2, No., pp. 1217-1220 vol. 2, 2000;    A. Abbaspour-Tamijani et al., "Miniature And Tunable Filters Using MEMS Capacitors," IEEE Trans. Microwave Theory & Tech., Vol. 51, No. 7, pp. 1878-1885, July 2003; and    A. Pothier et al., "Low-Loss 2-Bit Tunable Bandpass Filters Using MEMS DC Contact Switches," IEEE Trans. Microwave Theory & Tech., Vol. 53, No. 1, pp. 354-360, January 2005.
While achieving significant progresses in terms of miniaturization and tuning, planar resonator based tunable filters have relatively low quality factor (Q) of less than 400-500. This is due to either the low-Q lumped elements, as in the case of solid-state varactors, and/or the low-Q of the resonator itself. Inherently high-Q resonators loaded with tuners that result in a graceful Q degradation while tuning are need for high-Q tunable filters. Several approaches have attempted to accomplish this by employing dielectric resonators, cavity resonators and high temperature superconductivity (HTS) resonators. However, their limited tuning range and the requirement for cryogenic cooling (in the case of HTS tunable resonators) makes them unsuitable for mobile systems in the near future.
Evanescent-mode waveguide filters have recently attracted interest for realizing low-loss, highly-selective tunable filters for reconfigurable RF front-ends. Reference is had to the following papers:    T. A. Schwarz et al., "A Micromachined Evanescent Mode Resonator," 1999 European Microwave Conference Dig., Vol. 2, pp. 403-406, October 1999;    L. P. B. Katehi, "Tunable Evanescent Mode Filters," DARPA Project Report, December 2000; and    X. Gong et al., "Precision Fabrication Techniques and Analysis on High-Q Evanescent-Mode Resonators and Filters of Different Geometries," IEEE Trans. Microwave Theory & Tech., Vol. 52, No. 11, pp. 2557-2566, November 2004.
Compared to half-wave cavity resonators, evanescent mode resonators offer several advantages including substantially smaller volume and weight, larger spurious-free region and feasibility for monolithic integration while maintaining a very high-Q. It is well known that waveguides below cut off can be used to create microwave filters by introducing obstacles inside the guide, as described by G. F. Craven et al. in "The Design of Evanescent Mode Waveguide Bandpass Filters for a Prescribed Insertion Loss Characteristic," IEEE Trans. Microwave Theory & Tech., Vol. 19, No. 3, pp. 295-308, March 1971, and by R. V. Snyder in "New Application of Evanescent Mode Wave-Guide to Filter Design," IEEE Trans. Microwave Theory & Tech., Vol. 25, No. 12, pp. 1013-1021, December 1977. This concept finds wide applications in the form of evanescent mode filters, ridge waveguide filters and combline filters. See, e.g., R. Levy et al., "Transitional Combline/Evanescent-Mode Microwave Filters," IEEE Trans. Microwave Theory & Tech., Vol. 45, No. 12, pp. 2094-2099, December 1997; A. Kirilenko et al., "Evanescent-Mode Ridged Waveguide Bandpass Filters With Improved Performance," IEEE Trans. Microwave Theory & Tech., Vol. 50, No. 5, pp. 1324-1327, May 2002; and R. V. Snyder et al., "Bandstop Filters Using Dielectric Loaded Evanescent Mode Resonators," 2006 IEEE MTT-S Int. Microwave Symp. Dig., Vol. 2, No., pp. 599-602 Vol. 2, 6-11 Jun. 2004.
The simplest and most practical type of waveguide obstacle is a conductive re-entrant post, which represents an effective shunt capacitance and is usually realized by a tuning screw. By changing this capacitance, i.e., the gap between the post and waveguide wall (FIG. 1), the center frequency of the filter can be changed. It has been proposed to create tunable evanescent-mode filters using metal thin films as waveguide walls and externally attached piezoelectric actuators for frequency tuning, as described by S. M. Hou et al. in "A High-Q Widely Tunable Gigahertz Electromagnetic Cavity Resonator," J. Microelectromech. Syst., Vol. 15, No. 6, pp. 1540-1545, December 2006, and by H. Joshi et al. in "Highly Loaded Evanescent Cavities for Widely Tunable High-Q Filters," 2007 IEEE MTT-S Int. Microwave Symp. Dig., pp. 2133-2136, June 2007. These techniques offer excellent RF performance but suffer from issues such as large overall volume, hysteresis, instability, and/or high power consumption. One alternative is electrostatic actuation, offering advantages as discussed herein, but there remains a need for improvements in actuation techniques for tunable evanescent-mode filters.
Another shortcoming of current filters in front-end receivers is that they have very limited tuning. Generally multiple filters are needed in a multi-band environment. Also, the filter bandwidth tends to vary linearly with frequency in evanescent-mode filters due to the coupling iris, which can be quite significant over tuning ranges of more than an octave.


In one embodiment, a computer-implemented method includes receiving training data including a plurality of records, each record having a plurality of attributes. The training data is horizontally parallelized across two or more processing elements. This horizontal parallelizing includes dividing the training data into two or more subsets of records; assigning each subset of records to a corresponding processing element of the two or more processing elements; transmitting each subset of records to its assigned processing element; and sorting, at the two or more processing elements, the two or more subsets of records to two or more candidate leaves of a decision tree. The output from horizontally parallelizing is converted into input for vertically parallelizing the training data. The training data is vertically parallelized across the two or more processing elements. The decision tree is grown based at least in part on the horizontally parallelizing, the converting, and the vertically parallelizing.

Various embodiments of this disclosure relate to decision trees and, more particularly, to scalable streaming decision tree learning.
Many applications require the processing of Big data, which may be at rest or in motion. Big data is a broad term for data sets so large or complex that traditional data processing applications are inadequate. Challenges include analysis, capture, data curation, search, sharing, storage, transfer, visualization, and information privacy. When the data is in motion, processing it may need to take place in real time. One mechanism for processing data is through the use of decision trees.
When a decision tree is used, data can be classified by stepping through the nodes of the tree based on known attributes of the data. At each node, a child node is selected based on the value of an attribute of the data, and this selection process may continue until a leaf of the tree is selected. The leaf may be associated with a value to be assigned as a classification value for the data.
Decision tree learning is a form of classification learning, used to determine how to classify data. In decision tree learning, a system generates a decision tree that will be used to classify data based on observed attributes. Through the generation of the decision tree, which is an iterative generation, each interior node is split into subsets, with a child node at the root of each subset, based on the value of an attribute associated with that interior node. Each edge leading from the interior node to a child node corresponds to a particular value of the attribute. If no more attributes are available, a node then becomes a leaf node in the final decision tree, corresponding to a classification or prediction of a final value for the data.
In some systems, parallelism is used to speed up decision tree learning where a large amount of training data is being used as input into generating the decision tree. Specifically, either horizontal of vertical parallelism is used. The data generally includes multiple records, with each record containing multiple attributes, or columns. With vertical parallelism, the set of attributes are divided among available processing elements. In other words, each processing element receives data from multiple records, but the data received by each processing element includes only a subset of the existing attributes. With horizontal parallelism, the set of records are divided among available processing elements. In this case, each processing element receives data from one or more records, including every attribute for the subset of records assigned to that processing element.
Each processing element operates on the data assigned to it. The results of these operations are then aggregated together to complete generation of the decision tree.

This patent is subject to a terminal disclaimer.

Scalable streaming decision tree learning

INTERNATIONAL BUSINESS MACHINES CORPORATION


An error detection circuit for an airbag deployment control system includes a delay circuit receiving an analog acceleration signal, a difference circuit producing a difference signal based on a time difference between the original and delayed acceleration signals, and a first comparator circuit comparing the difference signal to first and second threshold signals. If the difference signal falls within an error region defined between the first and second threshold values, a decision circuit inhibits an otherwise pending airbag deployment event. If, on the other hand, the difference signal falls outside of the error region, the decision circuit allows airbag deployment with minimal delay. The error detection circuit further includes a second comparator circuit comparing the acceleration signal to near-supply and near-ground threshold values, wherein the decision circuit also inhibits airbag deployment if the acceleration signal magnitude exceeds the near-supply threshold value or falls below the near-ground threshold value.

The present invention relates generally to circuitry for controlling automotive airbag or Supplemental Inflatable Restraint Systems, and more particularly, to circuitry for detecting non-deployment conditions in seemingly deployable circumstances and inhibiting deployment of the airbag based on detection of such conditions.
Airbags are commonplace in automotive vehicles as a result of the need to improve occupant safety in collisions. In fact, airbags are standard equipment in many, if not most, late model automotive vehicles. These airbags are typically located in strategic places, such as the steering wheel of a vehicle, and are intended to help reduce occupant injury in the event of a crash. In general, airbag management requires specialized systems for detecting collisions, deploying airbags when appropriate, and also inhibiting airbag deployment when the crash is not sufficiently severe to warrant airbag deployment.
Airbag management systems typically include at least one acceleration sensor, commonly referred to as an accelerometer, to sense acceleration/deceleration along a specific axis. Deployment of the airbag generally occurs only when the accelerometer senses at least a minimum acceleration along an appropriate axis. Typically, an airbag management system includes a number of accelerometers for sensing acceleration along a corresponding number of axes.
In the operation of typical airbag management systems, an accelerometer senses acceleration and produces an acceleration signal, wherein the acceleration signal is processed via a decision circuit to determine whether airbag deployment is warranted. Generally, however, great care must be exercised in designing such systems to avoid inadvertent airbag deployment. Inadvertent airbag deployment is not only costly, as the result of having to repair and replace the deployed airbag, but it can also create a potentially dangerous situation for the occupants. For example, inadvertent deployment may force the driver out of position or otherwise impair the driver""s ability to safely operate the vehicle. To reduce the possibility of inadvertent airbag deployment, some airbag management systems include a redundant xe2x80x9carmingxe2x80x9d sensor (e.g., accelerometer) operable to alert the system of a potential deployment condition only if the crash is above a crash severity threshold.
Referring to FIG. 1, one known airbag management system 100 is shown including such a redundant arming sensor 110. System 100 also includes at least one accelerometer 120 suitably positioned for controlling a corresponding airbag. The accelerometer 120 senses and transduces an acceleration 130 into an analog acceleration signal proportional to the amount of acceleration sensed, typically measured in multiples of gravitation force units denoted by the symbol G.
The accelerometer 120 provides the analog acceleration signal to an analog to digital (A/D) converter 140 via signal path 122 which converts the signal to a digital acceleration signal and provides this digital signal to a microprocessor 150 via signal path 142. The microprocessor 150 is electrically connected to a deployment circuit 160 via signal path 154 which is itself electrically connected to an inhibit deployment circuit 170 electrically connected to arming sensor 110 via signal path 112. An output of the inhibit deployment circuit 170 is connected to an actuator (not shown) of an airbag 174 via signal path 172.
The microprocessor 150 typically includes a deployment control algorithm 152 for determining whether the digital acceleration signal on signal path 142 is of sufficient magnitude to deploy airbag 174, and provides a signal corresponding thereto to the deployment circuit 160. The arming sensor 110 is also operable to sense acceleration and provide a corresponding acceleration signal to the inhibit deployment circuit 170. Typically, the arming sensor 110 is configured to provide greater resolution in the lower G ranges, and the inhibit deployment circuit 170 is operable to process this signal to determine whether the crash event is sufficiently severe to allow deployment of the airbag 174. If, for example, the inhibit deployment circuit 170 determines that the acceleration signal produced by arming sensor 110 is below a predefined G threshold, circuit 170 is operable to inhibit any deployment signal produced by deployment circuit 160 on signal path 162 so that the airbag 174 is not deployed. If, on the other hand, the inhibit deployment circuit 170 determines that the acceleration signal produced by arming sensor 110 is above the predefined G threshold, circuit 170 is operable to pass any deployment signal produced by deployment circuit 160 to airbag 174 via signal path 172 to thereby deploy the airbag 174.
The airbag management system 100 just described includes a multitude of components including the arming sensor 110. These components increase the cost and complexity of system 100. Further, as the number of accelerometers 120 increase, the number of arming sensors 110 increases linearly. Therefore, for every accelerometer 120 located in the vehicle to sense along a certain axis, an arming sensor 110 must be located along the same axis, and preferably in close proximity to the accelerometer. Not only is this cost restrictive, physically locating these devices in close proximity is oftentimes impractical and sometimes impossible. Moreover, physical and electronic constraints of standard microprocessors limit the number of accelerometers that the system can manage. As more accelerometers are added, processing time becomes a constraint and thus unacceptable delays in the deployment of the airbag ensue, thereby compromising the safety of the occupants of the vehicle.
Referring now to FIG. 2, another known airbag management system 180 is shown that eliminates the need for arming sensor 110 but that incorporates and implements the arming sensor""s functions into a microprocessor 190. System 180 includes many of the same components as system 100 of FIG. 1, and like components are therefore identified with like reference numbers. For example, an accelerometer 120 is responsive to an acceleration 130 to produce an analog acceleration signal on signal path 122. An A/D converter 140 is operable to convert the analog acceleration signal on signal path 122 to a digital acceleration signal and provide this digital acceleration signal on signal path 142. Microprocessor 190 is responsive to the digital acceleration signal on signal path 142 to produce a deployment control signal on signal path 194 if a crash of sufficient severity is detected, in accordance with deployment control algorithm 152 as described hereinabove. A deployment circuit 170 is, in turn, responsive to the deployment control signal on signal path 194 to produce a corresponding drive signal on signal path 172 to thereby deploy air bag 174.
In addition to algorithm 152, the microprocessor 190 is also programmed to assume the function of the arming sensor 110 of FIG. 1 by including a software algorithm 192 operable to determine the magnitude of the digital acceleration signal on signal path 142 and assess whether this magnitude is sufficiently large along the proper axis to cause the deployment control algorithm (e.g., algorithm 152) to produce an active deployment control signal for deploying the air bag 174.
Referring to FIG. 3, a flowchart illustrating one known embodiment of a software algorithm 200, resident within microprocessor 190 of FIG. 2, is shown, wherein algorithm 200 is operable to process the digital acceleration signal and determining whether to deploy, or inhibit deployment of, the airbag 174. The algorithm 200 thus incorporates therein both the deployment control algorithm 152 program and algorithm 192 described with respect to FIG. 2. At step 202, the digital acceleration signal is received, and at step 204, the algorithm processes the digital acceleration signal in an known manner to determine whether to deploy the airbag 174. Step 204 thus corresponds to the execution of the deployment control algorithm 152. Thereafter at step 206, if the microprocessor 190 determines that airbag deployment is not warranted, algorithm execution advances to step 214 to inhibit airbag deployment. If, however, microprocessor 190 determines at step 206 that airbag deployment is warranted, algorithm execution advances to step 208 where microprocessor 190 is operable to calculate a time rate of change of the digital acceleration signal, preferably by comparing the absolute value of the digital acceleration signal with the absolute value of the previous digital acceleration signal, and compute a so-called xe2x80x9cdelta-jerkxe2x80x9d value corresponding thereto. The delta-jerk value is compared thereafter at step 210 with a Max value. If delta-jerk is less than Max value, algorithm execution advances to step 214 to inhibit airbag deployment. If, on the other hand, the delta-jerk value is greater than or equal to the Max value at step 210, algorithm execution advances to step 212 where the delta-jerk value is compared to a Min value. If the delta-jerk value is less than or equal to the Min value, algorithm execution advances to step 214 to inhibit airbag deployment. If, however, the delta-jerk value is greater than the Min value at step 212, algorithm execution advances to step 216 where microprocessor 190 is operable to determine whether the digital acceleration signal is stuck to rail or ground by comparing the digital acceleration signal with upper and lower boundary values. Thereafter at steps 218 and 220, algorithm 200 is operable to advance to step 214 to inhibit airbag deployment if the digital acceleration signal is outside the upper or lower boundary values, and otherwise advances to step 222 to deploy the airbag 174.
The airbag calculation/deployment algorithm 200 of FIG. 3 is operable to process the digital acceleration signal to determine whether airbag deployment is warranted, and if so to monitor the time rate of change of the digital acceleration signal to determine whether to inhibit airbag deployment. The steps of algorithm 200 monitoring the time rate of change of the digital acceleration signal and comparing this value to maximum and minimum threshold values accomplish in software the function of the arming sensor 110 of the system 100 of FIG. 1. Step 210 inhibits airbag deployment in cases where the absolute value of the digital acceleration signal minus the previous digital signal is greater than the Max threshold, wherein such conditions are typically indicative of an output fault since true crash signal levels generally do not move fast enough to produce such large differences between signal values. Step 212 similarly inhibits airbag deployment in cases where the absolute value of the digital acceleration signal minus the previous digital signal is less than the Min threshold, wherein such conditions are typically indicative of an output fault since true crash data shows at least some minimum movement in the magnitude of the acceleration signals over time.
One drawback associated with the use of a software algorithm, such as algorithm 200, to detect deployment inhibit conditions is that such algorithms typically require a microprocessor to perform sophisticated calculations associated with at least the determination of the difference values. Requiring a microprocessor, in turn, increases the cost and complexity of airbag deployment discrimination systems. Generally, a microprocessor is not needed to accomplish the stuck-to-rail and stuck-to-ground comparisons of steps 216-220 since such steps are easily implemented in hardware with comparators. Likewise, a microprocessor is not needed to execute the deployment control algorithm 152 since supplemental inflatable restraint control systems are known that do not include a microprocessor but instead includes analog circuitry operable to execute in hardware an analog version of algorithm 152. One such control system is described in U.S. Pat. No. 5,801,619 which is assigned to the assignee of the present invention, and the contents of which are incorporated herein by reference.
The delta-jerk calculation of step 208, on the other hand, is not so easily realizable in hardware circuitry. On possible solution to this dilemma is to provide one or more microprocessors for executing at least the error detection functions (e.g., inhibit features of algorithm 192), but this would generally be cost prohibitive. An ideal solution to the foregoing problem would be to conduct the error detection functions; i.e., the airbag deployment inhibit features of steps 208-220 of algorithm 200, without microprocessor involvement, and then do away with the microprocessor altogether by implementing a supplemental inflatable restraint control system of the type described in U.S. Pat. No. 5,801,619. What is therefore needed is an error detection circuit for accomplishing at least the error detection features performed heretofore by either an arming accelerometer or a microprocessor executable control algorithm. Ideally, such a circuit should not delay airbag deployment under valid crash conditions of sufficient severity to warrant airbag deployment, and should generally be operable to inhibit airbag deployment for a number of different error conditions as well as other invalid crash events.
The foregoing shortcomings of the prior art are addressed by the present invention. In accordance with one aspect of the present invention, an error detection circuit for an airbag deployment control system comprises a delay circuit receiving an analog acceleration signal and producing a delay signal corresponding to the analog acceleration signal delayed in time, a differential circuit subtracting the delay signal from the analog acceleration signal and producing a difference signal corresponding thereto, and a first comparison circuit responsive to the difference signal to produce a first inhibit signal for inhibiting deployment of an airbag if the difference signal falls within a first predefined signal range.
In accordance with another aspect of the present invention, a method of inhibiting airbag deployment in an airbag deployment control system comprises the steps of receiving an analog acceleration signal over time, delaying the acceleration signal for a predefined time period and producing a delay signal corresponding thereto, subtracting the delay signal from the analog acceleration signal and producing a difference signal corresponding thereto, comparing the difference signal with a first signal window, and inhibiting deployment of an airbag if the difference signal falls within the first signal window.
One object of the present invention is to provide an error detection circuit for processing an analog acceleration signal and inhibiting airbag deployment under conditions wherein pending airbag deployment is the result of one or more error conditions and not the result of an actual crash event of sufficient severity to warrant airbag deployment.
Another object of the present invention is to provide such an error detection circuit for use with airbag deployment control systems that may or may not include a microprocessor-based airbag deployment control algorithm.
Yet another object of the present invention is to provide such an error detection circuit that does not delay airbag deployment under valid crash conditions of sufficient severity to warrant airbag deployment.
These and other objects of the present invention will become more apparent from the following description of the preferred embodiments.

Error detection circuit for an airbag deployment control system


An air filtration system and a helmet for use in the air filtration system are disclosed and utilized to filter air between a head and body of a user and an external environment. The air filtration system and helmet include inner and outer shells that define an air flow channel for channeling air about the user. A fan module is mounted between the inner and outer shells and a scroll housing is mounted adjacent the fan module. The scroll housing includes an air inlet for drawing air into the air filtration system and helmet, and at least one air outlet to distribute air flow to the air flow channel. The helmet includes air exits at front and rear sections that are in fluid communication with the air flow channel and the air outlet or outlets. The air filtration system includes a gown operating as a filter for filtering the air.

1) Technical Field
The subject invention generally relates to an air filtration system for filtering air between a head and body of a user and an environment external to the user. The air filtration system is utilized in the medical profession during surgical procedures. The subject invention more specifically relates to a helmet assembly and gown for use in the air filtration system.
2) Description of the Prior Art
Air filtration systems and helmet assemblies utilized in the air filtration systems are known in the art. As indicated above, air filtration systems and helmet assemblies are worn by users throughout the medical profession, such as surgeons, during surgical procedures for filtering air between a head and body of the surgeon and an external environment, such as a clean room.
Conventional air filtration systems and helmet assemblies are deficient for one reason or another. For example, U.S. Pat. No. 5,592,936 to Thomas, Jr. et al. discloses an air filtration system and helmet assembly that draws air through a filter medium into the helmet assembly and through an intake grid where the air is then channeled through an air flow channel over a face of the user. The air filtration system and helmet assembly of this patent are deficient in that air is not distributed completely about the head of the user. That is, air is not distributed to a back of the head, toward a neck, of the user. Further, the intake grid is deficient in that the grid does not extend between a front and rear section of the helmet assembly to maximize an effective intake area for the filter medium.
A further example of a conventional air filtration system and helmet assembly is disclosed in U.S. Pat. No. 5,054,480 to Bare et al. This patent discloses an air filtration system and helmet assembly that draws air into the helmet assembly via an intake fan, and exhausts air from the air filtration system and helmet assembly via an exhaust fan disposed at the rear section of the helmet assembly spaced away from the neck of the user. The air filtration system and helmet assembly of this patent is deficient in that they are overly heavy due to the additional fan required to exhaust air. Furthermore, the exhaust fan creates excessive strain, and therefore fatigue, in the neck of the user because the exhaust fan is spaced away from the neck of the user.
The conventional air filtration system and helmet assembly disclosed in U.S. Pat. No. 5,711,033 to Green et al. is also deficient. This patent discloses an air filtration system and helmet assembly that draws air into the helmet assembly through an intake fan and scroll housing disposed at a rear section of the helmet assembly. The air filtration and helmet assembly of this patent is deficient because the intake fan and scroll housing are spaced away from the neck of the user. Further, the scroll housing in this patent includes only one air outlet to distribute air about the head of the user resulting in less balanced air flow throughout the helmet assembly. Additional drawbacks of such an air filtration system and helmet assembly including only one air outlet from the scroll housing are excessive fog build-up and poorer heat dissipation in the helmet assembly.
Other conventional air filtration systems and helmet assemblies are also deficient for the following reasons. First, these conventional air filtration systems and helmet assemblies do not assist a single user in self-gowning as the surgeon maintains sterility. That is, these air filtration systems and helmet assemblies do not include a positioning and supporting system that automatically centers a face shield over the helmet assembly and that supports an entire weight of the gown and face shield. Instead, the conventional air filtration systems and helmet assemblies merely utilize hook-and-loop fasteners randomly places around the helmet assembly to connect the face shield to the helmet assembly in any orientation. Furthermore, randomly-placed hook-and-loop fasteners do not automatically center the face shield and do not support the entire weight of the gown and the face shield as the surgeon self-gowns. Instead, as the user self-gowns, he or she must repeatedly adjust the face shield in order to center the face shield. This is time consuming and burdensome.
Secondly, it is generally understood that the amount of air flowing into the helmet assembly is critical for anti-fogging and heat control purposes. However, the air filtration systems and helmet assemblies of the prior art do not assist the surgeon in recognizing the amount, or volume, of air flowing into the helmet assembly. That is, these air filtration systems and helmet assemblies do not provide audible indication to the surgeon of the volume of air flowing into the helmet assembly during any particular surgical procedure.
Thirdly, as discussed above, it is ideal to position and maintain any fans in the air filtration system and helmet assembly as directly over, and not spaced from, the neck of the user as possible in order to minimize strain and fatigue. The prior art air filtration systems and helmet assemblies do not incorporate a strap flexibly connected to the front section of the helmet assembly such that the strap is pulled from the front section of the helmet assembly and the weight of any fans is maintained over the user's neck when the helmet assembly is adjusted to fit various sized heads.
Due to the inefficiencies identified in such conventional air filtration systems and helmet assemblies, it is desirable to implement a novel air filtration system and helmet assembly that utilizes a single fan to distribute air toward both the face and the neck of the user and that includes a scroll housing that includes at least two air outlets for complete balancing of the air flow about the head of the user. It is also desirable to dispose the fan in the helmet assembly such that it is not spaced away from the neck of the user to minimize strain, and to include an intake grid that extends between front and rear sections of the helmet assembly to maximize the effective intake area for filtering the air. Finally, it is desirable to implement an air filtration system and helmet assembly that includes a positioning and supporting system to assist the user in self-gowning, that includes audible indication to the user of the volume of air flowing into the helmet, and that includes a strap that can be adjusted to fit different sizes of heads while maintaining the weight of the helmet assembly over the neck of the user.

Air filtration system including a helmet assembly


A blood collection tube includes a bottom and an open end that is hermetically sealed by a plug. A supporting film having an anticoagulant coated thereon is positioned within the tube. The anticoagulant-coated surface of the supporting member is provided with a large number of fine convexes.

1. Field of the Invention
The invention relates to a blood collection tube in which an anticoagulant is enclosed.
2. Description of Related Art
Such a blood collection tube as described in the official gazette of Japanese Patent Laid-Open No. 38,536/1983 has been hitherto proposed. This blood collection tube comprises a bottomed tube whose open end is hermetically sealed by a plug and a porous support having an anticoagulant such as heparin sodium carried thereon, accommodated in said bottomed tube.
In the conventional blood collection tube mentioned above, however, an anticoagulant is carried by impregnation on a porous support such as nonwoven fabric, and it is therefore difficult to control the quantity of such anticoagulant impregnated therein. Moreover, such a blood collection tube in which the quantity of an anticoagulant carried on a porous support is too much or too less than a standard value is not proper because its use may compromise the reliability of the clinical inspection results of the blood collected by that blood collection tube.


A method for controlling a back-to-back three-phase three-level converter having a grid-side AC/DC converter and a machine-side DC/AC converter connected by a split DC link which defines a DC link midpoint. The method includes controlling the grid-side converter to convert AC power from a grid into DC power of the DC link, controlling the machine-side converter to convert DC power from the DC link to AC power to feed a low frequency machine, and concurrently performing common mode voltage injection for the machine-side converter so as to at least partially compensate midpoint voltage ripple caused by the machine-side converter. The method further includes performing common mode voltage injection for the grid-side converter so as to at least partly further compensate the portion of the midpoint voltage ripple which remains uncompensated by controlling the machine-side converter. A control system implementing the control method and a power conversion system utilizing same.

Three- or multi-level NPC and NPP power converters are widely used in many different power conversion applications such as, but not limited to wind and solar converters, power supplies, and variable speed drives, including high power medium voltage low speed machines and Doubly Fed Induction Machines (DFIM). An NPC converter typically includes three phase legs and a DC bus capacitor bank comprising at least two series connected DC bus capacitors. Each phase leg is composed of four series connected switches and each switch has an antiparallel freewheeling diode. Two additional diodes, so-called clamping diodes, are connected between the leg and a DC bus midpoint. The NPP converter topology is substantially similar to the NPC topology, but the output converter phases are connected to the DC bus midpoint by an internal bi-directional switch instead of the clamping diodes. Three-level NPC or NPP converters have many advantages, including good utilization of the semiconductor switches and low distortion of the output voltage.
In the 3-Level NPC and NPP converter topologies the splitting of the DC bus capacitor bank into two capacitor sub-banks provides an intermediate voltage step (midpoint or neutral point) for the 3 step modulation of the output phase voltages, i.e. via switching between the positive or negative DC bus rails and the capacitor midpoint. An inherent property of the NPC and NPP topologies, however, is that the resultant capacitor midpoint current, which ideally has a zero average, in addition to high switching ripples, contains a significant low frequency content or ripples. This low frequency midpoint current drives differences between voltages of the upper and lower DC bus capacitors causing capacitor midpoint voltage variations which may affect operation of the converter.
The capacitor midpoint current has a variable peak or rms value and waveform shape depending on the converter current and its phase shift with respect to phase voltage, i.e. the power factor. It is dominated by its fundamental frequency found at 3 times the converter output frequency and is thus often also called "3rd harmonic midpoint current injection". In addition to the 3rd harmonic current injection, due to various system asymmetries, the capacitor midpoint current may have some small non-zero average DC value which is source of a drift of average value of the capacitor midpoint voltage.
In practical applications, two 3-level NPC or NPP converters are often connected in so called back-to-back topology to allow indirect AC/AC (grid frequency input/variable frequency output) conversion with intermediate DC link stage, i.e. an AC/DC/AC conversion. In this topology one of the converters is connected to the power grid-side and forms grid-side AC/DC conversion stage which is operated at constant frequency of typically 50 Hz/60 Hz to control the grid currents and exchange power between the grid and DC link. The other converter is connected to a load, such as a three-phase machine and forms the load- or machine-side DC/AC conversion stage to control the machine currents and exchange power between the DC bus and machine. To allow power transfer via the DC link, the grid-side and machine-side stages must be interconnected (back to back) via the positive and negative dc bus rails with or without interconnection of the capacitor midpoints. It may be more advantageous to interconnect the capacitor midpoints of the grid and machine-side converter stages to stiffen up the capacitor midpoint potential.
The midpoint current and associated dynamic voltage ripple and static drift of the midpoint voltage are source of several significant effects which have to be considered in the NPC converter design. These effects include an increased voltage and current stress of the DC bus capacitors, increased losses in the capacitors, and reduced capacitor life time. Excessive midpoint voltage variations may increase stress of semiconductor switching devices and may cause activation of DC brake choppers or protective overvoltage converter trips.
The capacitor midpoint voltage ripple is an extremely important issue in applications of the 3L NPC/NPP converters for stator current control of high power medium voltage low speed machines or rotor currents in Doubly Fed Induction Machines (DFIM). In these applications the machine/rotor side converter can be operated at nearly full modulation depths at very low nominal frequencies, e.g. 3 Hz-5 Hz. In such operational conditions the midpoint current produced by the machine-side converter, which is dominated by the 3rd harmonic component, has a relatively low frequency, e.g. 9 Hz-15 Hz. Therefore, the capacitor midpoint voltage ripple created by the machine-side converter can be an order of magnitude higher than that created by the grid-side converter operated at 50 Hz/60 Hz nominal frequency, i.e. a midpoint current injection at 150 Hz/160 Hz. In order to keep the capacitor midpoint voltage ripple or oscillations within a tolerable level in all operational conditions, there are two basic options: passive means by using large DC bus capacitors and/or active means based on direct or indirect midpoint current control.
In low frequency machine applications the passive control of the DC midpoint voltage ripple requires a substantial increase of the DC bus capacitance which has strong cost and space implications. In the back-to-back converter topologies the capacitor midpoint voltage ripple in the machine-side converter can be partially passively reduced if the capacitor midpoints of the grid- and machine-side converters are interconnected. But in critical low speed applications the residual midpoint voltage ripple may still be excessive and further increase of DC bus capacitance is normally required.
To reduce the size of the DC bus capacitors in low frequency applications it is extremely advantageous to maximize utilization of the active means to reduce the capacitor midpoint voltage ripple. For example, it is well known that it is possible to eliminate or reduce the capacitor midpoint current injection in 3-level NPC/NPP converters in an active way via injection of common mode voltage into converter voltage references. Such active compensation algorithms are typically designed to control common mode voltage inserted into the converter voltage references with the goal to stabilize static drift of the average value of the midpoint capacitor voltage and to reduce its ripple which is associated with the converter own midpoint current injection. The static midpoint voltage drift and the converter midpoint current ripple can be fully compensated in this way only in the operational points where the power factor is high and when a sufficient modulation margin is available. Unfortunately in the most critical operational points of the machine-side converter the modulation margin may be relatively low so that the midpoint current injected by the machine-side converter may only be marginally compensated.
The most direct way to control the DC bus capacitor midpoint potential is to connect the capacitor midpoint to the supply neutral point, e.g. via a direct connection, as disclosed in U.S. Pat. No. 7,528,505 B2, for example. The advantage of this solutions is that a very effective capacitor mid-point voltage control can be achieved in practically all operational points. However, this solution relies on passive mechanisms and is effective mainly in prevention of drifts of average value of the capacitor midpoint voltage. Moreover, as the neutral current path is lightly damped, this can potentially lead to instabilities. A disadvantage of this solution is also that the converter input inductor must not be a three-phase magnetically coupled inductor. The input inductor must be composed of three independent single-phase inductors.
Alternatively, if a three-phase magnetically coupled inductor is used an additional inductor has to be inserted between the grid and converter neutral points. An example of such solution is presented in US 2013/0163292 A1, where the DC bus midpoint is connected to a grid transformer neutral via an inductor and an additional active control of the neutral point current is used to actively control the capacitor midpoint voltage. But regardless of effectiveness of both solutions, major disadvantages are that additional passive components and access to the grid transformer neutral point are required.
The midpoint voltage can also be controlled in an active way using the converter Pulse Width Modulation (PWM). The basic advantage of this solution is that there is no need for additional passive components. A common approach is to utilize controlled injection of the common mode voltage into the converter voltage references. In this way it is possible to alter the midpoint current injected by the converter without affecting the converter line-line voltages and introducing unwanted distortion into the converter phase currents. From U.S. Pat. No. 8,441,820 B2, for example, it is known that it is possible to find bilateral functional relationships between the converter midpoint current and the injected common mode voltage. This allows to shape the common mode voltage injection to control instantaneous value of the midpoint current injection for capacitor midpoint voltage control.
In the state of the art solutions, injection of the common mode voltage is performed with the goal to compensate either average drift and/or ripple in the midpoint voltage produced by the converter itself. U.S. Pat. No. 9,071,084 B2 discloses a back-to-back 3-level NPC converter with interconnected capacitor midpoint, where control of average midpoint voltage drift is shared between the grid- and machine-side converters depending on available modulation margins of the converters. Compensation of low frequency ripples caused by the machine-side converter is not achieved and not intended.
It is an object of embodiments of the invention to improve performance of the capacitor midpoint variation compensation in back-to-back 3-level converter topologies with interconnected capacitor midpoints in low frequency applications. In particular, it is an object of embodiments of the present invention to provide a control method and system for such converter topologies, which greatly facilitate compensation of capacitor midpoint variations, including the dominating 3rd harmonic ripples caused by the machine-side converter. Another object of embodiments of the invention is to provide a power conversion system based on back-to-back 3-level converter topologies with interconnected capacitor midpoints and having capabilities for efficient compensation of capacitor midpoint drifts and low frequency ripples.
To solve this object, embodiments of the present invention provide the control method having the features of independent claim 1, the control system of claim 11 and the power conversion system of claim 15. Embodiments of the present invention are subject-matter of the dependent claims.

System and method for controlling a back-to-back three-level converter with voltage ripple compensation

GE ENERGY POWER CONVERSION TECHNOLOGY LIMITED


A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.

A content addressable memory (CAM), also known as an associative memory, is a data storage device in which a location is identified by its informational content rather than by the names, addresses, or relative positions, and from which the data may be retrieved. For applications requiring content addressable processing, existing solutions make use of content addressable memories having a memory plane formed by an array of CMOS static memory cells.
U.S. Pat. No. 5,452,243 to Ansel et al. discloses a fully static CAM cell with low write power (minimum power supply current surges), but it has a total of seventeen transistors in the disclosed embodiment. It would be desirable to have a smaller memory cell that uses fewer transistors. U.S. Pat. No. 5,475,633 to Mehalel discloses a four-transistor cache memory cell. However, the cell disclosed is pseudo-static and still requires refresh operations to be performed. It would be desirable to have a static memory cell that does not require refresh operations.
U.S. Pat. No. 5,386,379 to Ali-Yahia et al. discloses a static CAM cell using eight transistors. The transistors are divided into two arrays, the first array having a data storage function and the second array having a comparison function between the stored data item and a data item being applied to the input of the cell, the comparison result being obtained on a selection line. In the first embodiment, the first array comprises four transistors for storage purposes and two access transistors connected to two bit lines and a word line, the second array comprises two transistors, the two access transistors of the first array being associated with these two transistors of the second array in order to ensure the comparison function, the data item to be compared being applied to the bit lines connected to the two access transistors of the cell. The selection line is preloaded during reading-writing operations and during comparison operations. A second ten-transistor cell embodiment in the patent eliminates the need to preload the selection line; however two additional transistors need to be added to the cell.
The eight-transistor memory cell of Ali-Yahia et al. operates well in isolation. However, there is a problem that occurs when more than one memory cell is on the same selection line. Referring to FIG. 2, which shows the memory cell described in Ali-Yahia et al., the selection line 29 is always preloaded to a "1" logic state. Nodes 91 and 92 are storage cells for data written into the memory cell. When bit line 28 is loaded to "1" and bit line 27 is loaded with a "0", there is a match and current flows from ground to Vdd through transistors 31 and 32, and node 91 of the cell will be pulled towards ground. However, if bit line 28 is loaded with a "0" and bit line 27 is loaded with a "1", there is not a match, and current flows from Vdd to ground through transistors 34 and 33 and node 92 is pulled towards Vdd. Therefore, if a matching cell and a non-matching cell are on the same selection line 29, there will be a mismatch on the selection line as the matching cell will be pulled towards ground and the non-matching cell will be pulled towards Vdd. This could cause the state of one of the cells to change to the opposite state, thus compromising the stability of the memory cell. This problem can be obviated by making node 91 large, such that it can source a greater amount of current than the current that flows through transistors 34, 33 and 37 to ground. Thus, it would be necessary to make the saturated drain current at node 91 much larger than the saturated drain current of transistor 36. However, it would be desirable not to have to be concerned with having to increase the size of node 91 to avoid compromising the stability of the memory cell.
Another problem that could occur would be in the case where there are more than two memory cells--for example N cells, where N is typically 24-32 bits wide. Then, if all but one cell match, then there will be (N-1) cells having transistors of the size of node 91 pulling the selection line 29 up and only one cell having one transistor 31 or 33 pulling the match line 29 through transistors 36 or 37. Since there is only one cell driving the line low and (N-1) cells driving the line high, the voltage on the selection line 29 will stay high and the mismatch will not be detected.
Additionally, even if the circuit of Ali-Yahia et al. could be made to work with multiple cells, it is not a low power solution. In the first embodiment of Ali-Yahia et al., it is necessary to precharge the selection line 29 in order to avoid the transistors of the comparison logic 36 and 37 forming an unloading path from the match line into the storage cells 91 and 92, which could also compromise the stability of the memory cell. In CAMs, only one line matches at a time, so if there are M words in the memory, then every (M-1) signals will have to be precharged and discharged for every cycle. This precharging and discharging consumes power equal to (C.times.Vdd.sup.2 .times.F), where C is the capacitance of the signal and F is the operating frequency. It would be desirable not to have to precharge the match line.
In a multiprocessor system, there is a need to keep the caches coherent, as the introduction of caches can cause a coherence problem for multiprocessors if the view of memory through the cache of one processor is different from the view of memory obtained through the cache of another processor. To keep the caches coherent involves two entities, the processor and the bus, looking at the look up mechanism simultaneously. However, using common methods known in the art, such as dual look up mechanisms or inclusion methods, problems occur when updating one of the look up mechanisms by one entity while the other is accessing the look up mechanism. To eliminate these problems, it would be desirable to provide a content addressable memory with more than one access port to allow two simultaneous read operations or to allow simultaneous read and write operations.
It is an object of the present invention to provide a static content addressable memory that is fast, uses a minimal amount of transistors and operates when multiple memory cells are provided in a manner that does not compromise the stability of the memory cells.
It is a further object of the invention to provide a static CAM that does not require precharging, and thus requires less power.
It is another object of the invention to provide a dual port cam which allows two simultaneous read operations or simultaneous read and write operations in order to keep the memory caches coherent.

Low power, static content addressable memory


A Venetian blind including a head rail, a tilting device, two or more tilt cords, a bottom rail, a predetermined number of draw cords, a cord pulley retainer, and a plurality of slats fastened to the tilt cords such that the slats are spaced equidistantly and parallel to one another and that the slats can be adjusted at any angle to regulate the light by the tilting device. Each of the slats is provided with two or more through holes located on the same side of a center line of the slat. The through holes of one slat are therefore obscured by the lower edge of another slat located thereover at the time when the slats are in an upright position to keep out the light.

Referring to FIGS. 1-4, a typical Venetian blind 10 of the prior art is shown to comprise a head rail 11, a tilting device 13, three tilt cords 14, a bottom rail, a plurality of slats 16, two draw cords 17, and a cord pulley retainer 18.
The head rail 11 is fastened securely to a wall or a window frame. The tilting device 13 is mounted pivotally in the head rail 11. Each of the three tilt cords 14 has one end fastened to the tilting device 13 and another end that is suspended. Each tilt cord 14 is composed of two slings 141 parallel to each other. Located between the two slings 141 are a plurality of connection lines 142 which are equidistantly spaced. The bottom rail 15 is disposed at the bottom ends of the tilt cords 14 and is parallel to the head rail 11. The slats 16 are disposed respectively between the two slings 141 of the tilt cord 14 and are supported by the connection lines 142 such that the slats 16 are suspended equidistantly. Each of the slats 16 is provided with two through holes 161 corresponding in location to the tilt cords 14. The through holes 161 of the adjacent slats 16 are corresponding in location to one another. The tilting device 13 is used to cause the slings 141 to move upwards or downwards so as to regulate the position of the slats 16 in order to keep out the light. Each of the two draw cords 17 has one end that is fastened to the bottom rail 15 and another end that passes through the through holes 161 of the slats 16 before emerging via the head rail 11. The draw cords 17 are used to raise or lower the bottom rail 15 so as to draw up or lower the slats 16. The cord pulley retainer 18 is disposed in one side of the head rail 11 for retaining and locating the draw cords 17.
The through holes 161 of the slats 16 are oval in shape and situated on a center line 162 of the slats 16, as shown in FIG. 4. As a result, the slats 16 are not interfered by the draw cords 17 at the time when the slats 16 are set together at an angle to regulate the light. However, when the slats 16 are adjusted to be in an upright position to keep out the light, as shown in FIG. 3, the through holes 161 of the Venetian blind 19 are so exposed that they allow the light to pass therethrough and that they can be improperly used as peep holes.


The present invention relates to the isolation of a cDNA clone encoding the calcium sensor in human placenta and subsequent Northern blots confirming the mRNA expression also in human parathyroid and kidney tubule cells. Close sequence similarity is demonstrated with the rat Heymann nephritis antigen, a glycoprotein of the kidney tubule brush border with calcium binding ability. Immunohistochemistry substantiates a tissue distribution of the calcium sensor protein similar to that previously described for the Heymann antigen. It is proposed that the identified calcium sensor protein constitutes a universal sensor for recognition of variation in extracellular calcium, and that it plays a key role for calcium regulation via different organ systems. The calcium sensor protein belongs to the LDL-superfamily of glycoproteins, claimed to function primarily as protein receptors, but with functionally important calcium binding capacity.

The present invention relates to a cDNA clone encoding a human calcium sensor protein of parathyroid, placental, and kidney tubule cells.
In WO 88/03271 there is described monoclonal antiparathyroid antibodies identifying a parathyroid cell membrane-bound calcium receptor or sensor, crucially involved in calcium regulation of the parathyroid hormone (PTH) release (1,2). The receptor function is essential for maintenance of normal plasma calcium concentrations, and reduced receptor expression within proliferating parathyroid cells of patients with hyperparathyroidism (HPT) results in calcium insensitivity of the PTH secretion and variably severe hypercalcemia (3-6). Reactivity with the antiparathyroid antibodies was also demonstrated for proximal kidney tubule cells and cytotrophoblast cells of the human placenta, and the cytotrophoblasts were demonstrated to exhibit an almost parathyroid-identical regulation of cytoplasmic calcium [Ca.sup.2+ i] (7,8). The antibody-reactive structure was found to exert calcium sensing function also in the cytotrophoblasts, and as these cells constitute part of the syncytium, the calcium sensor was suggested to be actively involved in the calcium homeostasis of the fetus (7,8). It was proposed that the antibody-reactive structure of the proximal kidney tubule cells exerts a similar calcium sensing function, and that the calcium sensor, thus, plays a more universal role in calcium regulation via different organ systems (1,7,9,10).
On HPT patients with hypercalcemia, surgery is performed to remove one or more of the parathyroid glands. It would be greatly desirable to have alternatives to this surgical procedure as HPT has proven to be a very common disorder and surgery is a relatively costly procedure and sometimes even entails some risks for the patients.
The calcium sensor/receptor has been revealed as a 500 kDa single chain glycoprotein (7). However, the amino acid sequence as well as the corresponding DNA sequences thereof are hitherto unknown.

Methods using human calcium sensor protein, fragments thereof and DNA encoding same

Rhone-Poulenc Rorer Pharmaceuticals Inc.


A semiconductor device includes a plurality of pillar structures on a semiconductor substrate, and a support pattern in contact with at least a part of each of the pillar structures, the support pattern connecting the pillar structures with one another, wherein the support pattern includes support holes exposing side surfaces of the pillar structures, the support holes including at least a first support hole and a second support hole that are spaced apart from each other, the first and second support holes having different shapes from each other.

1. Field
The present disclosure relates to a semiconductor device including a support pattern.
2. Description of the Related Art
Semiconductor devices are considered to be an important factor in electronic industry because of their small size, multi-function, and/or low fabrication cost. The semiconductor devices are being highly integrated with the development of the electronic industry, e.g., line widths of patterns of the semiconductor devices are reduced for high integration of the semiconductor devices. However, new exposure techniques and/or expensive exposure techniques are required to reduce line widths of the patterns to facilitate high integration of the semiconductor devices. Thus, research has been conducted for new integration techniques, e.g., to bury word lines inside a semiconductor substrate in dynamic random-access memory (DRAM) memory devices.

Semiconductor devices including support patterns


A photovoltaic cell including a first substrate having on its surface a first electrode layer having on its surface a semiconductor film on which a photosensitizer is adsorbed, and a second substrate having on its surface a second electrode layer. The first and second substrates are arranged so that the first electrode layer overlaid with the semiconductor film and the second layer are opposite each other with an electrolyte layer disposed therebetween. The electrolyte layer includes an electrolyte and a liquid crystal and at least one of the electrode-layer-having substrates is transparent.

The present invention relates to a photovoltaic cell which is excellent in photovoltaic transduction efficiency (photovoltaic transfer efficiency).
More particularly, the present invention relates to a photovoltaic cell which realizes high electron moving velocity, ensures prolonged stability of electrolyte layer and exhibits high photovoltaic transduction efficiency. Still more particularly, the present invention relates to a thin photovoltaic cell for solar cell, or thin flexible photovoltaic cell for solar cell, exhibiting high energy transduction efficiency.
Photovoltaic transducers are a material from which light energy is continuously taken out as electric energy and a material which converts light energy to electric energy by the utilization of an electrochemical reaction between electrodes. When a photovoltaic transducer material is irradiated with light, electrons are generated from one electrode. The electrons move to a counter electrode, and the electrons having reached the counter electrode return by migrating as ions through an electrolyte to the one electrode. This energy conversion is continuously carried out, so that it is utilized in, for example, a solar cell.
The common solar cell is produced by first forming an electrode on a support such as a glass plate coated with a transparent conductive film, subsequently forming a semiconductor film having a photosensitizer adsorbed thereon on a surface of the electrode, thereafter providing a counter electrode comprising a support such as a glass plate coated with another transparent conductive film, sealing an electrolyte between the counter electrode and the semiconductor film, and finally sealing the side faces with a resin or the like.
When the above semiconductor film is irradiated with sunlight, the photosensitizer adsorbed on the semiconductor absorbs visible-region rays to thereby excite itself. Electrons generated by this excitation move to the semiconductor, next to the transparent conductive glass electrode, and further to the counter electrode across a lead connecting the two electrodes to each other. The electrons having reached the counter electrode reduce the oxidation-reduction system in the electrolyte. On the other hand, the photosensitizer having caused electrons to move to the semiconductor is in oxidized form. This oxidized form is reduced by the oxidation-reduction system of the electrolyte to thereby return to the original form. In this manner, electrons continuously flow. Therefore, functioning as the solar cell can be realized.
The electrolyte to be sealed between the electrodes is dissolved in a solvent, selected according to the type of the electrolyte, to thereby obtain an electrolytic solution. The electrolytic solution is sealed in a cavity created by sealing the sides of the photovoltaic cell with, for example, a resin.
The above solvent can be selected from among, for example, water, alcohols, oligoesters, carbonates such as propione carbonate, phosphoric acid esters, dimethylformamide, dimethyl sulfoxide, N-methylpyrrolidone, N-vinylpyrrolidone, sulfur compounds such as sulfolane 66, ethylene carbonate and acetonitrile.
However, when the electrolyte is used in the form of such an electrolytic solution, the solar cell may suffer from, during a long-term service, alteration of solvent molecules, decomposition of solvent molecules, vaporization of low-boiling-point solvent, leakage of electrolytic solution (solvent and/or electrolyte) from sealed parts, etc. with the result that the performance, such as photovoltaic transduction efficiency, thereof is deteriorated. That is, the use of the electrolyte in the form of an electrolytic solution has a drawback in that the long-term stability is poor.
Moreover, depending on the type of electrolyte used in the electrolytic solution, hygroscopicity is exhibited to thereby absorb water, and it may occur that the water causes the electrolyte and the photosensitizer to decompose to result in performance deterioration.
The photovoltaic transduction efficiency of the current solar cell is not always satisfactory, and there are limitations in the application thereof. Therefore, there is a demand for further enhancement of light utilization ratio.
It is an object of the present invention to provide a photovoltaic cell which is excellent in long-term stability, ensures high light utilization ratio and exhibits high photovoltaic transduction efficiency.
The first photovoltaic cell of the present invention comprises:
a first substrate (base) having on its surface an electrode layer (1), the electrode layer (1) having on its surface a semiconductor film (2) on which a photosensitizer is adsorbed, and
a second substrate having on its surface an electrode layer (3),
the first substrate and the second substrate arranged so that the electrode layer (1) overlaid with the semiconductor film (2) and the electrode layer (3) are opposite to each other with an electrolyte layer (4) interposed therebetween,
wherein the electrolyte layer (4) comprises an electrolyte and a liquid crystal, and
wherein at least one of the electrode-layer-having substrates is transparent.
The first photovoltaic cell of the present invention contains a liquid crystal in the electrolyte layer thereof, so that, even if the angle of light incidence is large, the quantity of light received is not much decreased by virtue of the light scattering depending on the existence of the liquid crystal with the result that light energy can be stably transduced to electrical energy and taken out.
The second photovoltaic cell of the present invention comprises:
a first substrate having on its surface an electrode layer (21), the electrode layer (21) having on its surface a semiconductor film (22) on which a photosensitizer is adsorbed, and a second substrate having on its surface an electrode layer (23),
the first substrate and the second substrate arranged so that the electrode layer (21) overlaid with the semiconductor film (22) and the electrode layer (23) are opposite to each other with an electrolyte sealed between the semiconductor film (22) and the electrode layer (23),
wherein spacer particles are interposed between the semiconductor film (22) and the electrode layer (23), and wherein at least one of the electrode-layer-having substrates is transparent.
In the second photovoltaic cell of the present invention, spacer particles are interposed between the semiconductor film and the electrode layer opposite thereto, so that not only can the inter-electrode gap be decreased and uniformized but also the energy loss of charges (electrons) moving through the electrolyte layer can be reduced. Moreover, the whole cell can exhibit uniform optical and electrical characteristics. Therefore, the photovoltaic transduction efficiency can be enhanced, and the amount of electrolyte can be reduced.
The third photovoltaic cell of the present invention comprises:
a first substrate having on its surface an electrode layer (31), the electrode layer (31) having on its surface a semiconductor film (32) on which a photosensitizer is adsorbed, and
a second substrate having on its surface an electrode layer (33),
the first substrate and the second substrate arranged so that the electrode layer (31) overlaid with the semiconductor film (32) and the electrode layer (33) are opposite to each other with an electrolyte sealed between the semiconductor film (32) and the electrode layer (33),
wherein spacer particles are sunk in the semiconductor film (32) in such a manner that at least portions of the spacer particles are exposed from the semiconductor film (32) so as to contact the electrode layer (33).
In the third photovoltaic cell of the present invention, the semiconductor film in which spacer particles are partly sunk is disposed opposite to the electrode layer with spacer particles interposed therebetween, so that not only can the inter-electrode gap be decreased and uniformized but also the energy loss of charges (electrons) moving through the electrolyte layer can be reduced. Moreover, the whole cell can exhibit uniform optical and electrical characteristics to thereby enable improving apparent curve factor (FF) and configuration factor. Therefore, high photovoltaic transduction efficiency can be exhibited. Furthermore, by virtue of the interposition of spacer particles, contacting of the semiconductor film with the electrode layer opposite thereto can be avoided even when pressure is applied to the cell. Still further, the electrolyte layer can be made uniform and extremely thin, so that the light absorption by the electrolyte can be reduced. Still further, electromotive force is also effectively produced by incident light from the side of electrode opposite to the semiconductor film. Therefore, the photovoltaic cell can appropriately be used as a thin, or thin flexible, film solar cell.
In the above second and third photovoltaic cells, it is preferred that the spacer particles be spherical particles having an average diameter (D) of 1 to 100 xcexcm.
Further, it is preferred that a surface of the semiconductor film (22), (32) that is brought into contact with the spacer particles have a roughness (RS) of 5 xcexcm or less, and also a surface of the electrode layer (23), (33) that is brought into contact with the spacer particles have a roughness (RE) of 5 xcexcm or less, and that the ratio of surface roughness (RS) to average diameter of spacer particles (D), RS/D, and the ratio of surface roughness (RE) to average diameter of spacer particles (D), RE/D, be both 0.2 or less.
The above semiconductor film (2), (22), (32) is preferably a metal oxide semiconductor film.
The spacer particles are preferably particles having a hydrophobic (water repellent) surface, and a dispersion medium thereof is preferably a solvent which is miscible with water. The component for semiconductor film formation preferably comprises particles of crystalline titanium oxide.
The fourth photovoltaic cell of the present invention comprises:
a first substrate having on its surface an electrode layer (41), the electrode layer (41) having on its surface a metal oxide semiconductor film (42) on which a photosensitizer is adsorbed, and
a second substrate having on its surface an electrode layer (43),
the first substrate and the second substrate arranged so that the metal oxide semiconductor film (42) and the electrode layer (43) are opposite to each other with an electrolyte layer interposed therebetween,
wherein:
(i) the metal oxide semiconductor film (42) comprises metal oxide particles having an average diameter of 5 to 600 nm,
(ii) the metal oxide particles each have a core/shell structure comprising a core particle part and, disposed on a surface thereof, a shell part,
(iii) the core particle parts have an average diameter of 2 to 500 nm, and the shell parts have a thickness ranging from 1 to 150 nm, and
(iv) the metal oxide constituting the core particle parts and the metal oxide constituting the shell parts have intrinsic volume resistivity values (Ec) and (Es), respectively, which satisfy the relationship:
Ec less than Es.
In the fourth photovoltaic cell, it is preferred that the metal oxide constituting the shell parts be crystalline titanium oxide. The crystalline titanium oxide is preferably one obtained by heating/aging of peroxotitanic acid. Further, it is preferred that the metal oxide semiconductor film comprise metal oxide particles and a titanium oxide binder.
The coating liquid for forming a semiconductor film for use in a photovoltaic cell according to the present invention comprises a component for semiconductor film formation and spacer particles both dispersed in a dispersion medium. Peroxotitanic acid is preferably contained as the binder component. The average diameter of spacer particles is preferably in the range of 1 to 100 xcexcm.

Catalysts and Chemicals Industries Co., Ltd.


A method and an apparatus for implementing device sharing, which are applied to a local system in a heterogeneous system that includes the local system and a peer system, where the peer system have a peripheral device. The method executed by the local system includes: acquiring identifier information of a peripheral device of the peer system; generating according to the acquired identifier information and according to a message format that can be locally identified, an operation request against the peripheral device managed by the peer system; and parsing out from the operation request, a request message including a parameter necessary to generate the operation request, and notifying the peer system of the request message. According to the method, the local system can access a peripheral device of the peer system, thereby implementing peripheral device sharing in the heterogeneous system.

As cloud computing technologies develop, a big data era requiring massive data processing has come. In order to meet parallelization and diversification trends of applications and an urgent desire of corresponding industries for reducing energy consumption, a heterogeneous system becomes a new research hotspot.
The heterogeneous system refers to a system obtained by interconnecting, in various manners, two systems including different processors. For example, one system includes an X86 processor, and the other system includes an ARM processor. Each system in the heterogeneous system not only includes a processor, but also includes a memory and a peripheral device that are independent from each other. Because the heterogeneous system has features of a high computing capability, a rich hardware resource, and close coupling, when the heterogeneous system is used to execute applications with different characteristics, a hardware advantage of the heterogeneous system can be brought into full play. Therefore, energy consumption of the heterogeneous system can be effectively reduced and a performance ratio can be improved. For example, there are two computing tasks, and the two computing tasks interact with each other relatively frequently, where one computing task is relatively complex (which needs to be run on an X86 processor), and the other computing task is relatively simple (which may be run on an X86 processor or on an ARM processor). If there is no heterogeneous system, two X86 processors are required to complete the two computing tasks. If there is a heterogeneous system, the heterogeneous system with X86+ARM processors may be used to complete the two computing tasks, where the complex computing task is run on the X86 processor, and the simple task is run on the ARM processor. Power consumption of the ARM processor is much lower than that of the X86 processor, and therefore, using the heterogeneous system reduces the energy consumption of the heterogeneous system effectively and improves the performance ratio.
As PCI Express technologies develop continuously, people begin to use a non-transparent bridge (NTB) in a PCIe-switch to interconnect two systems in a heterogeneous system. In a process of implementing the present disclosure, the inventor finds that: in the prior art, only memory sharing in a heterogeneous system can be implemented, where the so-called "memory sharing" refers to that two systems in the heterogeneous system not only can access a memory of a local system, but also can access a memory of a peer system. However, currently, sharing peripheral device cannot be implemented in the heterogeneous system in the prior art, in other words, the two systems in the heterogeneous system can access only a peripheral device of the local system, but cannot access a peripheral device of the peer system.

Method and apparatus for implementing device sharing


A laboratory instrument comprising a single base plate is presented. The single base plate comprises at least one embedded consumable compartment, an embedded sample processing compartment, an embedded waste compartment, an embedded activation device compartment, an embedded rack receiving compartment, or a combination thereof. A laboratory system and a method adjusting the positioning of at least one pipetting device or handling device of a laboratory instrument or laboratory system are also disclosed.

In diagnostic laboratories, automated pre-analytical, analytical, and post-analytical laboratory instruments are used for various sample processing steps to produce accurate and reliable test results which represent pivotal information for physicians. Typically, such laboratory instruments are equipped with consumables, sample processing devices, waste containers, sample racks, and reagent racks which are accommodated in dedicated units assembled on a working surface within the laboratory instrument. Thus, the interior and the working surface of a laboratory instrument are built with a plurality of units and construction components which must be precisely adapted to one another for being assembled.
For a reliable and safe operation, such laboratory instruments have to be well maintained. The different components and the working surface of the laboratory instrument have to be cleaned on a regular basis to avoid cross contaminations which can lead to erroneous test results. The thorough cleaning of the interior of the laboratory instrument also ensures the safety of the operator and extends the laboratory instrument lifetime. As the downtime of the laboratory instrument should be kept as short as possible, the cleaning of the laboratory instrument should
be as efficient as possible. However, as conventional laboratory instruments comprise multiple assembled units and construction components, the working surface of the laboratory instrument may possess small gaps and splits which complicate the thorough cleaning of the interior of the laboratory instrument. Particularly, in laboratory instruments in the area of nucleic acid analytics where a highly sensitive analytical technology is used, smallest impurities may have severe consequences on test results and subsequent diagnosis.
Some sample processing steps include pipetting operations like the aspiration and/or dispensation of liquid samples and reagents out of and/or into vessels using a pipetting device. For those pipetting operations an accurate positioning of the pipette device relative to the sample vessels or reagent vessels positioned on the working surface is important as a physical contact between the pipette tip of the pipetting device and the sample vessels or reagent vessels can cause sample cross-contamination, reagent cross-contamination, and/or damage of the vessels or pipetting device of the laboratory instrument. Therefore, the positioning of the pipetting device has to be adjusted or calibrated on a regular basis.
U.S. Patent Publication Nos. US 2014/0263879 A1 and US 2009/0090198 A1 disclose laboratory apparatuses providing base plates or working surfaces for mounting or positioning other elements of the apparatuses.
There is a need to maintain diagnostic laboratory instruments in a simple and efficient way. It is an object of the present invention to improve conventional instrument working surfaces, particularly to better serve the needs of automated in vitro diagnostic sample processing.


An adjustable depth cover plate assembly includes a top plate and an adjustable sleeve to compensate for different spacing between the outer surface of a wall and the front side of an electrical box. The adjustable cover plate is positioned on the electrical box with the end of the sleeve abutting the electrical box. Mounting screws of an electrical wiring device pass through an opening in the top plate of the cover plate into the electrical box whereby the cover plate is captured between the wiring device and the electrical box. The length of the sleeve of the cover plate is adjustable by providing frangible score lines or telescoping members.

Electrical boxes are generally attached to a wall stud or other support structure for supporting an electrical device and enclosing electrical wiring. The electrical boxes are mounted in a variety of positions, orientations, and locations in the wall or ceiling by the use of nails, screws, or other fasteners. In new construction, the electrical box is attached to the wall stud or other support structure with the open front face of the electrical box facing outward. Generally, the open front face of the electrical box is positioned outwardly from the wall stud a distance corresponding to the thickness of the wall material or membrane so that the front edge of the electrical box is flush with the outer surface of the wall. In some forms of construction, the stud or other support structure does not allow a proper orientation of the electrical box so that the open end of the electrical box is recessed within the wall when the wall material is attached to the wall stud. This makes it difficult to mount the electrical wiring device to the electrical box while being properly oriented with respect to the front face of the wall. The electrical wiring device must be securely attached to the electrical box which often results in the wiring device being recessed with respect to the outer surface of the wall.
Renovating old construction can also create difficulties in positioning the electrical box with respect to the outer surface of the wall. The new wall board or paneling can be applied over the existing wall so that the original electrical box is recessed within the wall and spaced from the front surface of the wall. It is generally very difficult to move an electrical box within an existing wall and to reposition the electrical box without damaging the existing wall so that the front face of the electrical box is flush with the outer surface of the wall. The recessed electrical box often results in the electrical device being recessed with respect to the front surface of the wall.
Various devices have been produced that include an adjustable assembly for connecting to an outlet box that can accommodate different thicknesses of wall structures. These devices typically provide a mechanism for positioning the electrical device in a desired location with respect to the outer surface of the wall structure. These prior devices generally require a series of movable and adjustable components that are attached directly to the electrical box prior to installing the wall. After the wall is attached to the wall stud, the device is adjusted to position the electrical device in the desired location with respect to the outer surface of the wall.
An example of such a device is disclosed in U.S. Pat. No. 4,634,015 to Taylor. This device includes a plate and an open collar on the mounting plate and circling a central opening. A box frame slides within the collar to contact the side walls of the collar. The box frame is adjusted outwardly with respect to the collar by adjustment screws mounted in the box frame and connected to a frame on the collar or on the mounting plate.
Another example of an adjustable mud ring is disclosed in U.S. Pat. No. 5,931,325 to Filipov. The adjustable mud ring for the electrical box has a plate that can be attached to a conventional electrical box. The adjustable mud ring has a collar extending outwardly from the plate and a movable sleeve surrounds the collar. The sleeve is attached to the collar by screws that adjust the position of the sleeve with respect to the collar.
A further example is disclosed in U.S. Pat. No. 7,301,099 to Korcz. This device includes a base plate having a central opening and a collar encircling the central opening. A sleeve slides through the collar and is adjusted by adjustment screws extending between the sleeve and inwardly extending legs on the base plate.
Other examples of electrical box extension devices are disclosed in U.S. Pat. No. 6,820,760 and U.S. Patent Application Publication No. 2005/0051354 and 2005/0082079 to Wegner et al. The adjustable assemblies disclosed in these patents and published applications include an electrical box extension having an extending member for a switch or electrical receptacle. The extension member includes fastener brackets and a fastener base bracket. The fasteners extend through the fastener brackets of the base bracket to adjust the position of the extending member with respect to the base. Another form of adjustable extension members for electrical boxes include a base attached to the electrical box and a sleeve extending outwardly from the base plate. The sleeve can include frangible or breakable lines so that the length of the sleeve can be shortened to position the end of the sleeve in a desired location with respect to the outer surface of the wall. Examples of this type of device are disclosed in U.S. Pat. No. 2,989,206 to McAfee, U.S. Pat. No. 3,525,450 to Payson and U.S. Pat. No. 3,651,245 to Moll.
The prior devices have been generally suitable for the intended purpose. However, there is a continuing need in the industry for an improved adjustable device for mounting an electrical component to an electrical box.

Add-a-depth ring and cover plate assembly


A method and an apparatus for nondestructively detecting the orientation of anisotropic molecules in thin films and in molecular layers in general. The present invention is based on a single measurement of the non-polarized photoluminescence spectrum, in order to determine whether the molecules are orientated at right angles or parallel to the surface of the molecular layer, fabricated with any technique. The method is fast and noninvasive and can also allow to observe noninterferingly in real time during growth the orientation of the molecules in the film. The result of this real-time observation can be used to optimize the growth conditions of the film in order to achieve the intended molecular orientation.

The present invention relates to a nondestructive apparatus and method for determining the molecular orientation and the orientation of the unit cell of organic systems which are anisotropic or have anisotropic behavior, and particularly in thin films.
Over the past ten years, interest in organic materials (or organic molecules) has increased enormously in view of the prospect of developing a new generation of electronic and photonic devices based on said materials.
Examples of organic-based devices which are currently of great interest are thin-film transistors [1] and light-emitting diodes [2], but the application potential is extremely broad.
With respect to the conventional technology of inorganic semiconductors, such as silicon and gallium arsenide, organic molecular materials offer the fundamental advantage that they can be easily processed as thin films and therefore can be compatible with large area flexible substrates. Their thermal and mechanical stability is another characteristic that makes them excellent candidates for applications in optoelectronic devices.
It has been demonstrated that high control of molecular order in films is absolutely necessary in order to control the basic physical phenomena that determine the operation of optoelectronic devices. Furthermore, control of the orientation of highly anisotropic systems is important, since the optical and transport properties are significantly anisotropic along the various crystalline directions.
Various growth techniques (such as for example Langmuir-Blodgett, vacuum sublimation, supersonic beams, et cetera) have been proved to be suitable for growing monomolecular layers of an organic compound. In said ultrathin films, thickness is controlled on the magnitude order of one unit of molecular length.
Molecular orientation on the substrate depends not only on the intrinsic molecular properties and on intermolecular interactions but also on the nature of the molecule-substrate interaction and on the growth kinetics. Said kinetics is controlled by a series of experimental parameters, such as the growth rate, the temperature of the substrate, and the thickness of the film.
The absolutely critical dependence of structural order and molecular orientation on the growth conditions makes it indispensable, in order to obtain highly orientated organic thin films, to be able to simply and rapidly measure the orientation of the molecules in the film.
Furthermore, since the film may be subsequently manipulated in order to vary the molecular orientation and therefore the optoelectronic properties, the real-time noninterfering evaluation of said manipulation is useful both for quality and for process control.
Known methods for evaluating molecular orientation comprise anisotropy of ultrasonic speed, X-ray diffraction, optical double refraction, optical dichroism, small-angle light scattering [U.S. Pat. No. 4,264,207], polarized reflectance [U.S. Pat. 5,365,067], photoluminescence anisotropy, and polarized photoluminescence.
These techniques usually require complicated measurements and highly critical modeling. Specific technical skill and a long time for making the measurements are also necessary.
Photoluminescence anisotropy and polarized photoluminescence have been used in order to measure molecular orientation in thin films of polymers and in films of organic molecules [3, 4, 5].
Furthermore, measurement of photoluminescence intensity as excitation polarization varies is used to monitor molecular orientation in [U.S. Pat. No. 4,521,111].
However, prior to the present invention it was not known how to determine the molecular orientation in a film from a single non-polarized luminescence measurement.
The aim of the present invention is to overcome the drawbacks of currently known methods for determining molecular orientation in thin films, by providing a method and an apparatus for detecting the orientation of organic molecules in thin films by means of a simple and rapid measurement of nonpolarized luminescence and without critical modeling.
Another object of the present invention is to provide a method and an apparatus which allow to detect whether the molecules are orientated in a thin film parallel to the substrate or at right angles thereto without performing polarized photoluminescence or photoluminescence anisotropy measurements.
Another object of the present invention is to provide a method and an apparatus for monitoring in real time, during the growth or manipulation of the film, the molecular orientation in said film with respect to the substrate or surface of the film.
Another object of the present invention is to provide a method and an apparatus for monitoring molecular orientation in the film noninvasively and noninterferingly.
Another object of the present invention is to provide a method and an apparatus which allow to optimize in real time the growth conditions of the film, in order to obtain specific structural characteristics.
This aim and these and other objects which will become better apparent from the description that follows are achieved, according to the present invention, by means of a method which comprises the steps of a) stimulation of the luminescence of the molecular layer; b) measurement of the consequent nonpolarized luminescence spectrum; c) spectral and vibrational analysis of said luminescence spectrum in order to determine the orientation of the molecules.
Luminescence can be obtained with any method, particularly with photoluminescence excitation or with an electroluminescence excitation. For the sake of simplicity, but without intending to limit the invention, reference is made in the remainder of the description exclusively to photoluminescence.
The invention furthermore provides an apparatus for detecting noninvasively and noninterferingly and, if necessary, in real time during dynamic growth or manipulation phenomena, the orientation of the molecules according to the above method. Said apparatus comprises the following elements: a) an exciter source suitable to induce photoluminescence of the specimen; b) an optical system for collecting the photoluminescence generated by the specimen; c) an analyzer of photoluminescence spectra with appropriate optical and spectral characteristics; d) an interface with the user, suitable to indicate the orientation of the molecules, optionally providing the relative weights of the various orientations detected with respect to the dominant orientation. Conveniently, the apparatus according to the present invention furthermore comprises e) a system for varying in real time the growth or manipulation conditions, suitable to act according to the result of the determination of the molecular orientation and achieve specific structural characteristics.
The inventors of the present invention have in fact found that the orientation of the molecules on the substrate is revealed by measuring a nonpolarized photoluminescence spectrum and observing the active vibronic transitions.

Nondestructive apparatus and method for detecting molecular orientation in thin films