In a gear train where there is backlash, the backlash is prevented by a gear drive which includes an anti-backlash driven pinion which is mounted on, or is otherwise connected to, a torsion spring shaft that is adjustable for twisting, and thereby, loading the anti-backlash driven gear.

This invention relates to an anti-backlash gear drive and, more particularly, to such a gear drive that is adapted for use in controlling backlash effects in a servo driven gear train, as will be shown, described and explained later herein.
In such a gear train, such as is in use in an elevation actuator assembly in a tracking system, the output pinion tends to hunt or rattle during periods of low tracking rates, thereby causing the problems of excessive noise and of needless wear on the gear train.
Where space is not a limiting factor, the prior art provides a solution by the use of split spring-loaded gears, where one gear is staked to the common hub and the other gear is free to rotate but is loaded by springs in one direction, and where the spring force can be varied by winding the split gear to vary the amount of scissors action on the mating gear. However, where space is a limiting factor (e.g., where space limitations do not permit the use of the gear face width that is required), this prior art means for preventing backlash cannot be used.
My invention eliminates these problems (i.e., excessive noise and needless wear on the gear train) even where space is a limiting factor; and, thereby, my invention significantly advances the state-of-the-art.

The United States of America as represented by the Secretary of the Air Force


A planetary multi-stage transmission for a vehicle is provided. A drive (An) is connectable by a zeroth shift element (K0) to a first shaft (1). A first element of a first planetary gear set (RS1) is connected to a housing (9). A first shaft (1) is permanently connected to a second element of the first planetary gear set (RS1). A rotor (10) of an electric motor (EM) is connected to a third element of the first planetary gear set (RS1), and the third element of the first planetary gear set (RS1) is connectable by one or more of a plurality of additional shift elements to at least one element of one or more of a second and third planetary gear sets (RS2, RS3).

Hybrid transmissions are known from automotive engineering. With such hybrid transmissions, a purely electric start-up, driving by purely electric means, starting the internal combustion engine from a purely electric driving mode and a so-called drag start are all possible. Furthermore, hybrid driving with a load point displacement is conceivable. In addition, it is known that the electric motor is connected to the transmission input shaft by an additional preceding gear ratio. As a result, the electric motor can be designed with less torque.
For example, the publication DE 10 2009 046 367 A1 discloses such a hybrid multi-stage transmission in planetary design with an additional preceding gear ratio for the electric motor. However, it has been found that connecting the electric motor by an additional preceding gear ratio requires a significant amount of installation space, which in turn increases not only the production costs, but also consumption.


The disclosed computer-implemented method for load balancing backup data may include (1) receiving a request to backup files in a multi-node computing cluster, (2) identifying a backup distribution of the files among multiple backup clients, (3) reading an initial data block of a current file from a data node in the cluster, (4) reading a copy of the initial data block of an additional file from another data node in the cluster, (5) reading a subsequent data block of the current file from the data node in the cluster, and (6) balancing backup of the current and additional files among the data node and the another data node by reading a copy of a subsequent backup data block of the additional file from the another data node in the multi-node computing cluster. Various other methods, systems, and computer-readable media are also disclosed.

In an era of constant connectivity, an inability to efficiently backup and recover large sets of data can be a severe liability. Traditional systems may utilize a scale-out backup architecture that divides and distributes large backup workloads across multiple proxy clients of computing cluster nodes. However, the workload distribution of backup workloads in traditional systems may result in the proxy clients fetching backup data blocks from the computing cluster nodes in an uneven manner, thereby overutilizing (e.g., overloading) some nodes while underutilizing others during backup input/output operations. The instant disclosure, therefore, identifies and addresses a need for systems and methods for load balancing backup data.

Systems and methods for load balancing backup data


Optimizations are provided for reconstructing geometric surfaces for an environment that includes moving objects. Multiple depth maps for the environment are created, where some of the depth maps correspond to different perspectives of the environment. A motion state identifier is assigned to at least some pixels in at least some of the depth maps corresponding to moving objects in the environment. A composite 3D mesh is built using at least some of the multiple depth maps, by incorporating pixel information from the depth maps, while omitting pixel information identified by the motion state identifiers as being associated with moving objects.

Mixed-reality systems, including virtual-reality (VR) and augmented-reality (AR) systems, have received significant attention because of their ability to create truly unique experiences for their users. For reference, conventional VR systems create a completely immersive experience by restricting their users' views to only a virtual environment. This is often achieved through the use of a head-mounted device (HMD) that completely blocks any view of the real world. As a result, a user is entirely immersed within the virtual environment. In contrast, conventional AR systems create an augmented-reality experience by visually presenting virtual objects that are placed in or that interact with the real world.
As used herein, VR and AR systems are described and referenced interchangeably. Unless stated otherwise, the descriptions herein apply equally to all types of mixed-reality systems, which (as detailed above) include AR systems, VR systems, and/or any other similar system capable of displaying virtual objects.
Some of the disclosed mixed-reality systems use one or more on-body devices (e.g., the HMD, a handheld device, etc.). The HMD provides a display that enables a user to view overlapping and/or integrated visual information in whatever environment the user is in, be it a VR environment, an AR environment, or any other type of environment. Continued advances in hardware capabilities and rendering technologies have greatly improved how mixed-reality systems render objects. However, the process of immersing a user into a mixed-reality environment creates many challenges, difficulties, and costs, particularly with regard to accurately perceiving the surrounding environment and then sharing the perceived information with the user.
For instance, traditional techniques for reconstructing geometric surfaces include obtaining multiple images of an environment and then building depth maps using those images. The information in the depth maps is then fused together to generate a coherent three-dimensional (3D) depth mesh (or simply "depth mesh" or "3D mesh") that represents at least some of the geometric surfaces included within the environment.
While the above techniques work well for static environments, significant problems arise when objects are moving while the images are being formed. As an example, consider a scenario where a person is moving in a room. Because of the movements, each image will show the person at a different position and/or location in the room. Consequently, the depth maps will portray varying or non-uniform depths for the person. Because the overall 3D mesh is built by fusing together these depth maps, the 3D mesh will unfortunately include blurring effects (e.g., ghosting) for the person. That said, some techniques have been developed in an effort to resolve these problems. For instance, there is a technique referred to as a "clean up later" approach in which the processes described above are followed, thereby resulting in ghosting effects for any moving objects. As the name suggests, however, the clean up later approach causes different "post-processing" operations to be performed in an attempt to clean up or erase the ghosting effects from the 3D mesh.
While some techniques (e.g., the clean up later approach) have been developed in an effort to improve the quality of the 3D mesh, these techniques are (1) inefficient, (2) deficient, and (3) based on a false assumption. To illustrate, traditional techniques are (1) inefficient because post-processing operations are very resource intensive, (2) deficient because erasing content from the 3D mesh almost always lead to inaccuracies, and (3) based on a false assumption because they assume that perfectly accurate depth images are available. In real practice, however, perfectly accurate depth images are rarely, if ever, obtained. Accordingly, there is a significant need to improve how geometric surfaces are reconstructed.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is provided to illustrate only one exemplary technology area where some embodiments described herein may be practiced.

Surface reconstruction for environments with moving objects


A first shaft which is, for example, the output shaft of a clutch, is coupled to a second shaft which, for example, is the input shaft of a transmission, by a splined coupling. The splined coupling includes a first sleeve having internal splines for splining with the first shaft and external splines for splining with the internal splines of a second sleeve which internal splines also spline with the external splines of the second shaft. A first spring extending between the first sleeve and first shaft biases the first sleeve toward the second shaft, while a second spring extending between the first sleeve and second sleeve biases the second sleeve toward the second shaft. In order to decouple the first shaft from the second shaft so that, for example, a clutch may be removed from a drive train without removing a transmission, the first and second sleeves are pushed to a retracted position, collapsing the first and second springs. The sleeves are then held in the retracted position by a screw which extends through the sleeves and is tightened against the first shaft. Upon replacing or repairing the clutch, the clutch is reinstalled and a retaining screw released in order to reproject the sleeves and effect positive engagement between the output shaft of the clutch and input shaft of the transmission.

1. Field of the Invention
This invention relates to a coupling for connecting shafts. More particularly, this invention is directed to a coupling for connecting the output shaft of a clutch to the input shaft of a transmission.
2. Background
In drive trains for vehicles which include a transmission and clutch, clutches may require relatively frequent replacement or repair. This requires removing the clutch from the drive train. In many drive trains, it is necessary to remove the transmission before removing the clutch. Having to remove the transmission as well as the clutch involves additional time, labor and expense.
The problem has been addressed in the prior art. The prior art includes the concept of providing splines on both the output shaft of the clutch and the input shaft of the transmission and then coupling the clutch to the transmission with a coupling splined to both shafts. These prior art arrangements require considerable understanding and manipulation by the person removing the clutch and therefore may result in improper installation upon reconnecting the clutch to the transmission.


A method for signaling a driver of a motor vehicle that the motor vehicle is operating in a stoichiometric air/fuel mode or a non-stoichiometric air/fuel mode. The method includes providing an air/fuel sensor, the air/fuel sensor providing a signal that is representative of a stoichiometric air/fuel ratio mixture or a non-stoichiometric air/fuel ratio mixture being supplied to or burned by the motor vehicle. The method also includes providing a powertrain control module that is operable to receive the signal from the air/fuel sensor and to energize a light source when a non-stoichiometric air/fuel ratio mixture signal is received.

FIG. 1 illustrates an engine control module at reference numeral 10, where a plurality of inputs 12 can be received by a powertrain control module 14, and the powertrain control module 14 can provide a plurality of outputs 16. As shown in the figure, the plurality of inputs can include inputs from and/or in the form of a switch, variable resistor, alternating current (AC), direct current (DC), variable voltage and the like. In addition, the powertrain control module can process, monitor, analyze, etc. the inputs and provide a plurality of outputs to the engine from and/or in the form of a solenoid, light source, relay, motor, transistor and the like. It can be desirable that the plurality of inputs 12 are processed, monitored, analyzed, etc. for the purpose of providing one or more outputs 16 that optimize one of more functions of the engine. One such function can be the consumption of engine fuel.
The consumption of gasoline by motor vehicles continues to be a significant area for possible increased fuel efficiency. For example, in the year 2005 alone, over 136 million passenger vehicles burned over 73 billion gallons of gasoline based on U.S. Department of Transportation, Bureau of Transportation Statistics. Thus, various government organizations encourage drivers to use driving techniques that increase fuel economy. For example, the term "hypermilers" is recognized within the United States as drivers who exceed the Environmental Protection Agency's estimated mileage on their vehicles by modifying their driving habits.
Techniques that are used to maximize the fuel economy include upkeep of vehicle maintenance, minimizing mass of the vehicle during driving, slow acceleration during takeoff, and built-in trip computers that display real-time miles per gallon when a driver is operating the vehicle. Regarding the built-in trip computer, typically only a limited number of cars include this feature which provides the driver with a real-time indicator on how driving techniques affect their gas mileage. The complexity and cost of such a built-in trip computer prohibit their installation in most vehicles. Therefore, an indicator that would provide a driver with information on fuel economy as a function of their driving habits would be desirable.

Toyota Motor Engineering & Manufacturing North America, Inc.


A model simulating cochlear spectrum analysis is disclosed which includes a pair of matched all pole lattices interconnected by a plurality of tip couplers providing non-linear distributed bilateral signal processing. One of the lattices along with the tip couplers corresponds to the organ of Corti found in the cochlea and the second lattice corresponds to the basilar membrane also found in the cochlea such that the model provides a striking resemblance in structure to the physical properties of the cochlea itself. With the cochlea model disclosed, distortion products and otoacoustic emissions are simulated. An intermediate model is also disclosed which provides bilateral signal processing but lacks distributed amplification.

Many researchers, including the inventor herein, have spent many years trying to understand the biophysical mechanisms of the human ear to understand how the human ear works and also to help in developing a module, which may be physically constructed, which duplicates or simulates the operation of the ear. Many theories and models have been developed over the years which have progressed this development. The inventor herein has previously developed a biophysical model (Goldstein, J. L. "Modeling rapid waveform compression on the basilar membrane as multiple-bandpass-nonlinearity filtering", Hearing Research 49, 39-60) which sought to explain the biophysical mechanisms of the ear in terms of a multiple band pass non-linear input/output model for simulating the non-linear basilar membrane response. The approach in this prior model was to account for non-linear cochlear phenomena directly in terms of a mathematical model of I/O behavior rather than treating them as non-linear perturbations from a physically based linear theory. This basic model, and later models, incorporate two non-linearly interacting filter systems that simulate the two distinct non-linear regimes observed in all non-linear phenomena at low-to-moderate and moderate-to-high stimulus sound levels. While this prior model and theory represented a dramatic departure from the prior art in itself, and helped to advance the work on understanding the ear as it provided new direction, this model was not a complete answer in that it did not explain observed phenomena such as distortion products and otoacoustic emissions, or otherwise provide any understanding of the operation of the organ of Corti. Furthermore, the model did not fully address the function of the basilar membrane as the model structure does not reflect the known biophysical properties of the cochlea.
With the present invention (See Goldstein, J. L., Changing Roles in the Cochlea: Bandpass Filtering by the organ of Corti and Additive Amplification of the Basilar Membrane, paper 4aPP3 at 124th Meeting of the Acoustical Society of America, November 1992), the inventor has improved on his earlier model to bring it further in congruence with the known biophysical mechanisms of the ear, including most particularly the organ of Corti and basilar membrane, and has in the process achieved simulation of the heretofore unexplained distortion product and otoacoustic emissions. In an intermediate step, the inventor has added bilateral signal processing to his prior model to more completely simulate the two signaling channels responsible for the "tips" and "tails" of Cochlear tuning curves. This bilateral processing potentiates extension of the model to other phenomena, including combination tones (distortion products) and otoacoustic emissions. This intermediate step takes advantage of non-linear feedback while the full invention adds distributed amplification. This distributed amplification provides for the non-linear addition of many signals from tip sources which are believed to function similarly to the organ of Corti. These organ of Corti filters, or tip sources, are connected at different locations along a filter-bank spectrum analyzer (a corollary to the outer hair cells and adjoining structures) and are non-linearly added through a propagating medium (a corollary to the basilar membrane) to provide distributed amplification. This model thus helps explain the non-linear input/output characteristic as observed by others in the basilar membrane mechanical response in the human ear.
There are several additional features of the present invention, including a "zoom" capability, a sensitivity adjustment, and efferent neural control simulation. As explained in greater detail below, the present invention includes a pair of matched all pole lattices with a plurality of tip couplers tapped into each lattice and interconnecting them at chosen "center frequencies". A scaling factor, or alpha, may be induced at any frequency to alter the response at that frequency and thereby match the model's output to any particular human ear output. Additionally, an efferent bias control, which is ordinarily set to zero, may also be used to scale the throughput of any one or more tip couplers to simulate the brain's ability in humans to "tune out" undesirable sounds or simulate "listening without hearing" as experienced in humans. Choosing the number of tip couplers (and hence the length of the matched lattices), and the "center frequencies" of each of the tip couplers permits the model builder to focus on any one or more range of frequencies for measurement with the model. Additionally, the model accommodates the use of 12,000 tip modules which corresponds to the full complement of outer hair cells believed to be contained and operative in the organ of Corti, to thereby provide a full representation and simulation of the frequency range of the human ear. As this may be cumbersome or undesirable, a fewer number of tip couplers may be used and may be focused over a chosen portion of the frequency range of hearing to thereby minimize cost and complexity of the model while still simulating with great accuracy the desired response frequencies.
While the principal advantages and features of the present invention have been described above, a more complete and thorough understanding of the invention may be attained by referring to the drawings and description of the preferred embodiment which follow.

Electronic simulator of non-linear and active cochlear spectrum analysis


A patient monitoring system is provided which includes a monitor and a transmitter which can optically communicate with each other. The monitor receives analog physiological data from a patient and converts the analog data to a digital optical signal which is sent to the transmitter optically. The transmitter includes a memory for storing the digital signal thereby allowing separation of the monitor from the transmitter prior to subsequent transmission. Additionally, the transmitter is capable of converting the digital signal to a modulated tone for transmission via standard phone lines. In this manner, the transmitter is able to send the converted signal to a central processing system via phone lines. This converted signal can then be monitored at the central processing system or it can be further communicated to one or more remote receiving stations.

It is well known that various galvanometric devices can be used to detect and record the minute differences in potential between different parts of the body caused by muscle action. Perhaps the most well known such device is the electrocardiograph which measures these differences for the heart muscle. In any event, and regardless of the particular muscle action being measured, it is frequently necessary or desirable to monitor the muscle's activity over an extended period of time. This is particularly so where the heart muscle is involved.
For the particular case involving the heart muscle, it is known that some heart anomalies can be identified early and properly diagnosed by studying a history of the patient's electrocardiogram (ECG). Further, it is known that some heart anomalies can even be effectively predicted by observing trends which are disclosed in the ECG history. In order to observe these trends, however, it is necessary that the heart be continuously monitored. This, of course, requires that the patient remain "hooked up" to an electrocardiograph for an extended period of time. Additionally, in order to be useful and effective, it is necessary that the ECG history be periodically reviewed by a physician. Consequently, the problem is essentially twofold. First, there is the need to detect and record the ECG history. Second, there is the need to safely, effectively and reliably transmit this ECG history to the proper medical authorities.
Fortunately, much of the world is serviced by a vast and extensive telecommunications network which is commercially available for the transmission of data and information between remote locations. Indeed, this existing network is accessible by various types of devices, to include telephones, facsimile machines, and central processing units. The present invention recognizes that the flexibility, reliability and conveniences of this network can, and should, be effectively used for the transmission of physiological data, such as an ECG history, from a patient to proper medical personnel. Where, however, it is necessary that the device remain connected to the patient while collecting this data (e.g. an electrocardiograph compiling an ECG history) it is essential that the patient be electrically isolated from the telecommunications network.
Accordingly, it is an object of the present invention to provide a device for relaying physiological data along a communications path from a patient to an electronic data processing system which electrically isolates the patient from the telecommunications network used by the electronic data processing system. Another object of the present invention is to provide a device for establishing a communications link between a patient and a data processing system which permits the relatively rapid unloading and transmission of data from the patient into the system. Yet another object of the present invention is to provide a device for transmitting collected physiological data which is safe to use with a commercial telecommunications network. Still another object of the present invention is to provide a device for collecting and transmitting physiological data from a patient which has minimal power requirements. Another object of the present invention is to provide a device for relaying physiological data along a communications path from a patient to an electronic data processing system which is easy to use, relatively simple to manufacture and comparatively cost effective.


The present invention relates to a structural object coated with a superhydrophobic nanostructure composite, the structural object being obtained by densely coating a surface of a solid substrate having a desired shape with a nanostructure obtained by combining a polymer having a polyethyleneimine skeleton with silica on the nanometer order, and bonding a hydrophobic group to the surface of the nanostructure, and a process for producing the structural object. The present invention also relates to a structural object coated with a superhydrophobic nanostructure composite, the structural object being obtained by removing the polymer having the polyethyleneimine skeleton from the nanostructure and bonding a hydrophobic group to the surface of the residual nanostructure containing silica as a main constituent component, and a process for producing the structural object. Furthermore, the present invention provides a method of using the structural object as a container for transferring an aqueous solution.

When a water droplet contacts a solid surface, a contact angle range of 70° to 150° where the water droplet contacts the surface is defined as hydrophobicity, and a contact angle range of 150° or more where the water droplet contacts the surface is defined as superhydrophobicity. In particular, on a solid surface having a water contact angle of 170° or more, water droplets roll off the surface and a clean state is maintained for a long time without leaving a trace of contact with water. In other words, it is expected that even after an aqueous solution is allowed to flow into a container or the like having a superhydrophobic surface, a completely clean state can be maintained without leaving even droplets of the solution on the inner wall of the container, and the container can be repeatedly used without washing. However, it is difficult to exhibit superhydrophobicity using only a molecule residue having a low surface tension.
On the other hand, many living matters of the natural world exhibit superhydrophobicity. For example, lotus leaves, rice plant leaves, cabbage leaves, and the like have superhydrophobicity in which water droplets are completely repelled. For example, it is known that the superhydrophobicity of a lotus leaf is deeply related to the surface structure of the leaf. Specifically, nanofibers extend throughout the entire surface to form a surface layer, micron-sized projections similar to aggregates of nanofibers make up an outermost layer on the surface layer at certain intervals, and hydrophobic wax is present on the surfaces of these nanofibers. As a result, water cannot adhere to the surface and rolls off the surface of the lotus leaf, and surface contaminations and the like are removed by the force of rolling, thus exhibiting a so-called self-cleaning function. This suggests that, in order to exhibit superhydrophobicity, it is most important to control the surface roughness, that is, the surface structural object and shape in the nano-dimension.
The structural principle for exhibiting superhydrophobicity, which is also called "lotus effect", has been used as a guideline for developing many methods for designing an artificial lotus-like structure. With the advancement of nanomaterials, in recent years, various techniques for providing a flat solid surface that exhibits superhydrophobicity have been developed. For example, it has been reported that the contact angle is increased to 170° or more by regularly arranging carbon nanotubes on a surface of a substrate (refer to NPL 1). Is has also been reported that the surface contact angle is controlled to be 170° or more by growing polypyrrole nanofibers on a silicon surface coated with platinum by an electrochemical process (refer to NPL 2). Furthermore, superhydrophobicity is exhibited by forming a nanocrystal seeds layer composed of zinc oxide on a surface of a glass substrate at a temperature of 400° C. or higher, and then growing a large number of rod-like zinc oxide nanofibers thereon (refer to NPL 3).
As for a simple process, for example, it has been reported that a network structure composed of polypropylene nanoparticles is formed by adding a certain poor solvent to a solution of polypropylene, casting the resultant mixture onto a surface of a substrate, and then adjusting the temperature, whereby the contact angle is increased to 160° (refer to NPL 4). Alternatively, superhydrophobicity can be exhibited by providing glass made of oxides of silicon, boron, and sodium with a phase separation structure, and etching the glass by a chemical treatment to induce an irregular structure on the surface, and lastly allowing a fluorine compound to react on the surface (refer to PTL 1). Furthermore, it is also known that a superhydrophobic surface is constructed by preparing a stacked film of a polyarylamine and polyacrylic acid, and then treating a surface of the film by a chemical method to induce a surface porous structure, immobilizing silica nanoparticles thereon, and then lastly hydrophobing with a silane coupling agent having a fluorine alkyl residue (refer to PTL 2).
Among the processes proposed above, in the cases of a superhydrophobic surface based on an inorganic material, the step of obtaining a surface roughness provided with a nanostructure is complex, and the cost is also high. In the cases of a superhydrophobic surface based on an organic polymer, although the cost is low, the solvent resistance and corrosion resistance of the resultant superhydrophobic surface are low, and furthermore, the step of obtaining a surface roughness provided with a nanostructure is also complex. Thus, there is a problem in terms of practical use. Furthermore, the processes proposed above are characterized in that the superhydrophobic surface is formed on a planar solid surface. However, no example has been reported in which a limited space, specifically, an inner wall of tubular substrate is coated with an inorganic material-based superhydrophobic surface.
A prerequisite for exhibiting superhydrophobicity is to construct a nanostructure composite surface in which micro-sized domains are scattered over the entire surface of a substrate while fibrous nanostructures densely cover the surface of the substrate. However, many studies are still necessary to ascertain which materials and which processes are beneficial for constructing such a nanostructure composite. In particular, even when only the contact angle is temporarily high and superhydrophobicity is exhibited, the superhydrophobicity often disappears after a prolonged immersion in water. Considering that exhibition of superhydrophobicity for only a short period of time does not have practical utility, developing a material that exhibits semi-permanent or permanent superhydrophobicity (super-water repellency) even while being immersed in water, and providing a simple process for producing such a material are important objectives.

Structural object coated with superhydrophobic nanostructure composite and process for producing the same


The mode of attachment of a wearable device to an earphone component enables a durable connection between the two. The earphone component includes an earphone cable, a motherboard, and a support shelf, and the earphone cable is fastened to the motherboard by the support shelf.

Wearable devices, such as smart watches, smart glasses are popular because users can use them to listen to music, watch videos, or make calls. An earphone usually includes jack earphone or wireless earphone. However, the large size of the jack earphone affects appearance of a wearable device to which it is connected, and sound qualities of the wireless earphone can be poor.

Wearable device and earphone component thereof

HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD.


Systems and methods for calculating gas densities within a fluid enclosure are disclosed. In an example embodiment, a system includes a temperature probe for measuring an enclosure temperature in a fluid enclosure filled at least in part with a fill gas, an atmospheric pressure sensor for measuring the atmospheric pressure outside the fluid enclosure, a gas sensor for measuring an enclosure pressure within the fluid enclosure, and a controller for calculating a fill gas density within the fluid enclosure based at least in part on the enclosure temperature, the atmospheric pressure, the enclosure pressure, and a gas coefficient of the fill gas.

Various techniques exist for measuring gases (as well as liquids and other material) and for determining the concentration or pressure of such in a given space. Different techniques among these can work with varying reliability or accuracy based on the location of sensors and their ability to accurately reflect the systemic variables as opposed to a point-value. Further, while sensors may provide instantaneous data relating to the measured gases, such data does not provide insight into past trends or future values.


A boom assembly is provided for a material handling machine. The boom assembly includes a boom pivotally coupled to a frame of the machine. The boom has a pair of side plates, a top plate and a bottom plate that are rigidly interconnected. The top plates have a pair of slots which extend therethrough. An arm is pivotally coupled to an end of the boom. A mounting unit extends between a center portion of the side plates. A pair of hydraulic boom cylinders are coupled between the frame and the mounting unit. A pair of spaced apart arm cylinder mounting plates are rigidly mounted to the mounting unit. Each mounting plate extends through a corresponding one of the slots. An arm cylinder is connected between the mounting plates and an arm.

Industrial loaders used in the construction and mining industries have a frame which carries a loader boom. The loader boom is conventionally raised and lowered by means of a pair of hydraulic cylinders having one end connected to the loader frame section and their piston rod ends connected to transversely spaced boom arms. The boom arms are normally rigidly interconnected by one or more transverse members. The boom lift cylinders transmit large forces to the boom arms.
One way of attaching the cylinder rods to the loader arms has been to provide a yoke on the end of the cylinder rod with a transverse pin extending through the yoke and a portion of the boom arm. In such a case, the cylinder is disposed in the same vertical plane as the loader arm, and a relatively large yoke is required to transmit the forces involved. Also, the single thickness of the boom arm absorbs the entire load.
If the cylinders are connected to the boom arm mounting plates, then the mounting plates have to be relatively large and the welds extensive to accommodate the forces involved. This results in an expensive and heavy boom. If a boom weighs too much, the hydraulic cylinder can have difficulty controlling the boom during operation.
U.S. Pat. No. 4,798,512 shows a loader boom that is controlled by a pair of hydraulic cylinders acting between the main frame of the loader and a pair of parallel, transversely spaced boom arms that are interconnected by a transverse tube. A pair of tabs are respectively welded to the tube a short distance from the opposite ends of the tube, and the piston ends of the cylinders are respectively connected to the boom arms by a transverse pin extending through aligned bores in the tabs, eye members attached to the ends of the hydraulic cylinder piston rods, and the boom arms. However, in this design the boom is coupled directly to a bucket and both the boom and bucket cylinders are coupled to a vehicle frame part.


Methods and liquid compositions for stabilizing an oxidizing biocide in a water system. The liquid composition comprises a hydantoin, and a surfactant, a ratio of a concentration of the hydantoin to the surfactant in the liquid composition is in a range of 1:1 to 99:1 by volume. The method comprises mixing a hydantoin, a surfactant and an oxidizing biocide with water to form a liquid treatment composition, and then adding the liquid treatment composition to a water stream in the water system, the liquid treatment composition improving the efficacy of the oxidizing biocide in the water stream.

Biofouling is a detrimental type of fouling experienced in industrial water treatment applications. Regardless of industry, water treatment experts spend a considerable amount of their time focused on preventing biofouling of heat exchangers and cooling towers. When biofouled, poorly performing heat exchangers and cooling towers can lead to millions of dollars in lost revenues.
The use of oxidizing and non-oxidizing biocides for microbiological control in industrial applications is known. However, the known chemistries have significant drawbacks when it comes to overall efficacy, safety, and delivery.
Methods for combining stabilizers with oxidizing biocides vary, but include: (i) direct injection of the stabilizer into a biocide such as hypochlorite, which is then injected into an aqueous system, (ii) injection of the stabilizing component and biocide such as hypochlorite into the aqueous system separately but in close proximity, and (iii) creating a solid form of a stabilized product, which is then dissolved into an aqueous system.
Whether stabilized or not, oxidizing biocides have difficulty penetrating biofilms once they have been established. While it is possible to feed an exorbitant amount of oxidizing biocide to essentially "burn" the system, the high levels of free oxidant increase corrosion rates throughout the water system. To help improve the oxidizing biocide's ability to penetrate these films and make contact with the microorganisms, biosurfactants have been implemented.
Biosurfactants, sometimes referred to as biodispersants, significantly improve the efficacy of both oxidizing and non-oxidizing biocides. There are subtle differences between biosurfactants and biodispersants, but they have the same function—minimize the growth and adherence of biofilms. Biosurfactants work by actually removing the biofilm in a scrubbing type action, while biodispersants disperse bio matter so that it cannot agglomerate.
Research has shown that biofilms are typically 30 to 40% organic matter, with the rest being inorganic material such as silt, metals, and other particulate matter. Other dispersants, such as sulfonated polymers and copolymers, are sometimes used in conjunction with biodispersants and biosurfactants to help disperse these inorganic materials. While this approach can be effective, it involves a comprehensive and cumbersome water chemistry program.
Conventional efforts have attempted to address these issues by combining stabilizer, surfactant, and a halide ion in a solid form. However, practical application of the solid form in water systems requires special feed systems such as pot feeders and requires manual handling of the chemicals. Other programs have been developed that generate stabilized oxidizing biocides. For example, researchers have combined a stabilizer and a bromine source into a single chemistry, as well as combined a bromine and surfactant into a single chemistry. But these programs require expensive generators, and may pose significant hazards if the systems fail.

Compositions and methods for treating water by stabilizing an oxidizing biocide


A page of content includes instructions that, when executed by a client device presenting the page, obtain a visibility state of the page describing presentation of the page of content to a user and a time when the visibility state was obtained. Execution of the instructions also generates an identifier with which the visibility state and the time are associated. The instructions also obtained updated visibility states, obtains times when the updated visibility states are obtained, and associates the updated visibility states and their corresponding times with the identifier. The client device communicates the obtained visibility state, updated visibility states, and corresponding times to an online system in association with the identifier. Based on the times corresponding to the visibility state and the updated visibility states, the online system determines a duration the page was presented.

This disclosure relates generally to presenting content to users of an online system, and more specifically to determining a duration that the content was presented to the users of the online system.
Online systems, such as social networking systems, allow users to connect to and to communicate with other users of the online system. Users may create profiles on an online system that are tied to their identities and include information about the users, such as interests and demographic information. The users may be individuals or entities such as corporations or charities. Online systems allow users to easily communicate and to share content with other online system users by providing content to an online system for presentation to other users. Content provided to an online system by a user may be declarative information provided by a user, status updates, check-ins to locations, images, photographs, videos, text data, or any other information a user wishes to share with additional users of the online system. An online system may also generate content for presentation to a user, such as content describing actions taken by other users on the online system.
Third party systems and online systems also provide content to users. For example, a third party system provides pages of content to users. Similarly, an online system provides pages of content to users. To increase exposure to and interaction with pages of content provided by third party systems or by the online system, the online system may provide its users with content items identifying pages of content. If a user accesses a content item identifying a page of content via a client device, the client device may retrieve and present the page of content to the user.
When providing content items for presentation to the online system identifying pages of content provided by a third party system, the third party system has an interest in the effectiveness of the content items in causing online system users to view or to access the pages of content. Similarly, the online system may seek to analyze effectiveness of content items provided by the online system in causing users to interact with pages of content provided by the online system. Conventionally, tracking mechanisms may be included in pages of content that are executed when the page of content is loaded by a client device and communicate an indication that the page of content was loaded to a third party system or to an online system associated with the page of content. However, these conventional tracking mechanisms provided limited information about interaction with the page of content as they simply identify that the page of content has been loaded by a client device. This limited information about interaction with the page of content provides limited information for an online system or a third party system to evaluate effectiveness of content items identifying the page of content in inciting users to engage with the page of content.

Determining a duration content is visible to a user of an online system


The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.

Field of the Invention
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits.
Description of Related Art
The new millennium brings with it a demand for connectivity that is expanding at an extremely rapid pace. By the end of year 2015, the number of global network connections will exceed two times the world population and it is estimated that in 2020 more than 30 billion devices will be wirelessly connected to the cloud forming the Internet of Things (or "IoT"). Enabling this new era are the revolutionary developments in mobile computing and wireless communication that have arisen over the last two decades. Following Moore's Law, development of highly-integrated and cost-effective silicon complementary metal oxide semiconductor (CMOS) devices allowed incorporation of digital and analog system elements, such as bulky Analog-to-Digital converters or transceivers, into a more cost effective single chip solution.
In the last few years, however, while digital circuits have largely followed the predicted path and benefited from the scaling of CMOS technology into ultra-deep submicron (sub-μm), analog circuits have not been enabled to follow the same trend, and may never be enabled without a paradigm shift in analog design. Analog and radio frequency (or "RF") designers still struggle to discover how to make high-performance integrated circuits (or "ICs") for ultra-deep sub-μm feature sizes without losing the benefits of shrinking size; including reduced power, compact footprint, and higher operational frequencies. Truly a paradigm shift is needed to break through the established science of analog design to meet the system on chip (SoC) demands of the new millennium.
Prior Art
The core building block of analog circuits is the amplifier. Discrete component amplifiers are free to use resistors, capacitors, inductors, transformers, and non-linear elements as well as various types of transistors. Unwanted parasitics between various components are normally negligible. However, in order to build amplifiers within an integrated circuit, the normal analog circuit components are not readily available, and often take special IC process extensions to obtain these circuit elements if at all. The parasitics on integrated circuit amplifiers are severe due to their close proximity and being coupled together through the silicon wafer they are integrated into. Moore's law IC process advancements are focused on digital, microprocessor, and memory process development. It takes a generation (˜18 months) or two to extend the IC process to incorporate analog components, thus analog functionality is generally not included on the latest process single chip systems. These "mixed-mode" IC processes are less available, vender dependent, and more expensive as well as being highly subject to parametric variation. It takes substantial engineering to include sparse analog functionality on any IC which becomes specific to its IC vender and process node. Because analog circuitry is carefully and specifically designed or arranged for each process node, such analog circuitry is highly non-portable. Eliminating this limitation, analog circuit design engineers are becoming scarce and are slowly retiring without adequate replacements.
Operational Amplifiers (or OpAmps) are the fundamental IC analog gain block necessary to process analog information. OpAmps make use of a very highly matched pair of transistors to form a differential pair of transistors at the voltage inputs. Matching is a parameter that is readily available on an integrated circuit, but to approach the required level of matching, many considerations are used: like centroid layout, multiple large devices, well isolation, and physical layout techniques among many other considerations. Large area matched sets of transistors are also used for current mirrors and load devices. OpAmps require current sources for biasing. OpAmps further require resistor and capacitor (or RC) compensation poles to prevent oscillation. Resistors are essential for the "R" and the value of the RC time constant is relatively precise. Too big value for a resistor would make the amplifier too slow and too small results in oscillation. Constant "bias" currents add to the power consumed. In general, these bias currents want to be larger than the peak currents required during full signal operation.
As IC processes are shrunk, the threshold voltages remain somewhat constant. This is because the metal-oxide-semiconductor (or MOS) threshold cutoff curve does not change with shrinking of the IC processes and the total chip OFF leakage current must be kept small enough to not impact the full-chip power supply leakage. The threshold and saturation voltage tends to take up the entire power supply voltage, not leaving enough room for analog voltage swings. To accommodate this lack of signal swing voltage, OpAmps were given multiple sets of current mirrors, further complicating their design, while consuming more power and using additional physical layout area. This patent introduces amplifier designs that operate even better as power supply voltages are shrunk far below 1 volt.
Prior art CMOS integrated circuit amplifiers are based on several analog or mixed-mode IC process extensions which are not available on all-digital IC processes. Primarily matched pairs of transistors are used as a differential inputs and current mirrors. These analog FET transistors must be long, as depicted in FIG. 1q, to provide the necessary high output resistance, and also must be wide in order to support the necessary current that is mirrored between them. For example, conduction channel 13q which is operable by the gate terminal 17q must have a sufficient length or distance between the source terminal 14q and the drain terminal 19q on the body/substrate 16q. Bias currents, which are normally larger than the peak analog signal currents, must be generated and maintained. Resistors and large area capacitors are normally required to create references and stabilize the amplifiers. Because of parametric sensitivity, these designs are not very portable between IC processes or venders. They are redesigned for each IC process node and are very specifically tailored to their various applications. Due to their bulkiness amplifiers are normally the limiting speed element of an IC system. What is needed is a scalable design that uses logic-only IC processes components, is process parameter tolerant, consumes a small area, uses relatively low power, and operates at voltages significantly below 1 volt. This is the subject of the present invention.
The conventional MOS amplifier gain formation is an input voltage driving a trans-conductance (gm) which converts the input voltage into an output current. This output current then drives an output load which is normally the output of a current source for the purpose of establishing a high load resistance. This high resistance load converts the output current back into an output voltage. The resulting amplifier voltage gain is gm*Rload. The equivalent output load resistance is actually the parallel combination of the load current source transistor and the amplifier output transistors. In order to keep this equivalent load resistance high, and the voltage gain high, these parallel transistors must be very long, but to drive enough current, these transistors must be very wide to carry sufficient current also, thus very large transistors are necessary. It also might be noted that the load resistance the amplifier output drives is also an additional parallel resistance that reduces the voltage gain. It should also be noted that a load capacitance interacts with the amplifiers output resistance, modifying the AC performance characteristics. What is actually needed is exactly the opposite of the present analog amplifier operating principles of very small voltage-input to high-impedance current-output (gm); which the present invention is about: very small current-input to low-impedance voltage-output (rm). FIG. 1a is a transistor level schematic diagram of a high-quality MOS IC OpAmp as a baseline reference (Gray, Paul R. et al., "Analysis and Design of Analog Integrated Circuits," 5th edition, John Wiley & Son Ltd, at pg. 484) which is used for comparison in the description of the amplifiers illustrated herein.
The baseline comparisons are (all made in a 180 nm IC process) in the form of performance plots as in: a Bode Gain-Phase plot FIG. 1b, when Vdd=1.8 Volts and Rcmp=700 ohms. Wherever possible all the axis scales for each of these three comparison plots are kept the same. A 180 nm process was selected for comparison of all the comparative examples in this specification because conventional prior art amplifiers work best and have had the most usage to mature the analog mixed-mode IC process extensions offered as required for conventional analog. Also as the IC process is shrunk and the power supply voltage is decreased, this is where the implementations of the present invention become highly beneficial.
Normally MOS amplifiers operate within a square-law form due to the strong-inversion MOS transistor square-law characteristics; these are not very well defined or predictably stable to the degree that analog circuits need. Exponential-law operation, like bipolar transistors operation is higher gain, stable, and well defined. At very weak operating conditions, MOS transistors convert to exponential operation, but they are too slow to be of very much use. Furthermore, the "moderate-inversion" transition between these two operating mode provide non-linarites that lower the quality of analog MOS circuits. At the threshold voltage, where MOS transistors operate around, is where 50% of the current is square-law and the other 50% is exponential. This is the definition of threshold voltage in the latest MOS simulation equations. Full exponential MOS operation at high speed would provide higher gain that is predictable, stable, and well defined. This patent is about fast amplifiers that operate in the exponential mode but not in weak-inversion; instead a super-saturated mode is introduced.
To understand the prior art, let's begin with a discussion of weak vs. strong-inversion (Enz, Christian C. et al., "Charge-based MOS Transistor Modeling—The EKV model for low-power and RF IC Design, John Wiley & Son Ltd., 2006). Referring to FIGS. 1e and 1f, weak-inversion is the range where most designers would consider the transistor to be OFF:                Weak conduction channel inversion 13e occurs when the Gate 17e on the body/substrate 16e is operated below its threshold voltage Vthreshold 17f in FIG. 1f with channel ionization 13e characterized by a thin surface layer;        Source 14e to Drain 19e voltage 19f is small (typically less than 100 mV);        For weak-inversion, the gate G 17e is typically operated by gate voltage supply 12e at a low potential (˜300 mV);        This creates a channel surface conduction layer 13e, of uniform depth from source S 14e to drain D 19e;         Since there is essentially zero voltage gradient along the channel 13e (˜no electric field), any current between drain D 19e and source S 14e is primarily supported by diffusion;        Increased gate voltag Vgs 12e at the gate G 17e increases the thickness of the conduction layer 13e below the gate 17e, thus allowing more charge to diffuse along the channel 13e;         The conductivity of this surface layer is exponentially related to the gate voltage Vgs 12e at the gate G 17e;         This exponential relationship holds over as many as 6 decades of dynamic analog signal range for the drain channel current;        The channel appears as a moderately high value resistor for its channel current (many 100+s of K-Ohms);        The resulting uniform conduction channel depth promotes higher exponential gain but at a severe speed penalty due to low current density; and        This weak-inversion conduction is reflected in a near zero operating point 13f in FIG. 1f.
Strong conduction channel inversion occurs when the gate voltage Vgs 12g at the Gate 17g on the body/substrate 16g is operated above its threshold voltage 17h (referring to FIGS. 1g and 1h) with channel ionization characterized by a graduated conduction channel, deeper near the Source 14g and shallow near at the Drain 19g:                 Strong conduction channel inversion 15g and 15h occurs when the Drain 19g to Source 14g voltage 19h is larger than the threshold Vthreshold17h in FIG. 1h (typically in excess of 400 mV);        The Gate 17g is operated above its threshold voltage Vthreshold 17h in FIG. 1h;         In strong-inversion 18g, the Drain 19g voltage is typically operated above the Gate 17g voltage which results in a pinched-off conduction channel 15g near the Drain 19g;         This pinched-off channel at 15g gives rise to high output impedance at the Drain 19g and can be observed as the thick flat part 18h of the operating characteristic plot FIG. 1h;         As the Drain 19g voltage Vd is changed, the pinched-off region 15g changes length, but its thin conduction layer is retained, keeping the output impedance high;        Due to the Gate 17g to channel 15g voltage and the electric field along the conduction channel path (Drain 19g to Source 14g), the conduction channel 15g is forced deeper at the Source 14g and tapers to near pinch-off at the Drain 19g;         The resulting conduction layer behaves with a Square-law response to the gate voltage at the Gate 17g;         In strong-inversion, dynamic range of channel current is limited to about 2 or 3 decades; the channel must drop into weak-inversion for additional dynamic range; p1 This strong-inversion conduction channel 15g appears as an adjustable current source (high value resistor); and        The wedge shape of the conduction channel 15g provides high speed from high current density, but requires the carriers to transit the channel and velocity saturation is reached limiting the speed or cutoff frequency of the transistor; and        This is reflected as the operating point 15h in FIG. 1h which is along its bolded line 18h.
FIG. 1e, shows the channel development under weak-inversion conditions. The conduction channel has a relatively even distribution of carriers over its entire length and width. Note that the conduction 13e depth of the entire channel is the same as the pinch-off area 15g on the right channel side (or near the drain 19g) of FIG. 1g. The output drain voltage Vd loaded on the drain D 19e by bias current, Ibias Ld19e. This thin conduction layer 13e contributes a significant amount of noise because the channel current travels along the surface where defect traps are concentrated. The Gate 17e to channel voltage Vg in FIG. 1e has a strong (exponential) effect on the density of carriers in this conduction layer 13e.
FIG. 1f shows a plot which has an exponential relationship of drain current Id to drain voltage Vds using a fixed gate voltage Vg. It is to be noted that the drain voltage Vds must be limited to a small value (on the order of 100 mV) in order to stay in weak-inversion.
FIG. 1g shows channel 15g ionization under strong-inversion conditions. In strong-inversion, there is an output drain voltage Vd loaded on the Drain 19g by an output load: Ibias Ld19g. This load presents a lower potential difference between Gate 17g and Drain 19g end of the conduction channel 15g than the potential difference between the Gate 17g and Source 14g end of the conduction channel, resulting in a tapered conduction channel 15g. The conduction channel thins down to a minimum as it approaches the drain provide a high output resistance. This output resistance is primarily defined by the thin channel cross-sectional area. As the drain voltage is varied, this thin pinched-off length of the channel changes, but not so much its cross-sectional area. This leads to a high output resistance, in that Drain 19g output resistance variation with drain voltage is relatively small, yielding a high output resistance. This high resistance is required in conventional gm analog MOS circuit design. In this pinched-off channel region, the carriers approach their velocity saturation, thus limiting their transit time along the channel. This is called "channel length modulation" (the flat part of the channel 15g), resulting in pinch-off near the drain diffusion where the channel reaches a thin layer at 15g. The pinch-off region, where the carriers are forced to the top of the channel, imparts significant noise by means of surface defect carrier traps. The higher the drain voltage Vd, the longer the pinch-off region and thus the higher the contributed noise (Rahul, Sarpeshkar, "Ultra Low Power Bioelectronics-Fundamentals, Biomedical Applications, and Bio Inspired Systems", ISBN9780521857277, and Lee, Thomas "The Design of CMOS Radio-Frequency Integrated Circuits", 2nd Ed, Cambridge ISBN-13 978-0521835398), thus is desired to keep this voltage low for low noise contribution to the channel current. Other effects such as velocity saturation and hot electron jumping over to the gate oxide are noted around this thin saturated region, thus it would be highly desirable to minimize this region by lower voltage and semiconductor doping profiles.
FIG. 1h shows a characteristic plot which approaches a "constant current" relationship between drain current Id and drain voltage Vds with a fixed Gate voltage Vg on the gate G. It is to be noted that the drain voltage Vds spans a much larger range of nearly the power supply voltage Vdd, while maintaining the same current.
A two-finger CMOS inverter is illustrated in FIGS. 1i, 1j, 1k, 1m, and 1n. A logic inverter possesses several desirable properties:                They exist in all logic IC processes        are the most common and fundamental building block        highly scalable        process parameter drift tolerant        small        high speed        high output drive for varying capacitive loads        arguably the highest gain of a complementary pair of MOS transistors        low power        easily used
A basic two finger inverter schematic of the prior art is depicted in FIG. 1i. For example, Vin 10i of the basis two finger inverter 100 is connected to the gate terminals of NFET 101 and PFET 102. The source terminal of NFET 101 is connected to negative power voltage, and the source terminal of PFET 102 is connected to positive power voltage. The drains of NFET 101 and PFET 102 are connected together to form an output 19i. A generic physical layout is illustrated in FIG. 1k in parallel with another inverter schematic diagram in FIG. 1j which has been stretched out and aligned alongside the physical layout to correlate the inverter schematic FIG. 1j to the physical layout structure FIG. 1k. Artistic liberty was used to clearly relate these two figures. Actual physical layout would be in accordance of the design rules and practices of the IC process it is designed for. FIG. 1m is a 3-D sketch of the physical layout. FIG. 1n shows a cross-section view of the physical layout as indicated Section AA in FIG. 1m. The two finger inverter 100 includes a common gate terminal 10j/10k/10m/10n, and output 19j/19k/19m/19n connected to drain terminal D− 11j/11k/11m/11n and D+ 12j/12k/12m/12n. As can be seen in FIGS. 1k to 1n, the drain D− 11k/11m/11n is displaced between the source terminals, S− s13k/s13m/s13n and s15k/s15m/s15n, while the drain D+ 12k/12m/12n is displaced between the source terminals, S+ s16k/s16m/s16n and s14k/s14m/s14n. The pull down transistor channel 13k/13m/13n is in parallel with 15k/15m/15n, while the other pull down transistor channel 14k/14m/14n is in parallel with 16k/16m/16n. The poly transistor control gate 17k/17m/17n is in communication with the gate terminal 10k/10m/10n. Drain diffusions 12n are shown in FIG. 1n. The charge distribution in the drain channels 13n, 15n, 14n, and 16n are shown in FIG. 1n. This charge distribution is illustrated for the voltage where the logic is in the middle or most active part of its state change. This charge distribution is an extension of the charge distribution in FIG. 1g. These inverter figures are closely related to the present invention as the basis for making minor alterations that do not require any IC process modification as will be developed below.
FIG. 1p illustrates a prior art MOS structure that turns out to actually emulate a combination of both modes of operation; strong-inversion FIGS. 1g, 1h with enhanced weak-inversion-like properties of FIGS. 1e, 1f. This structure is inherent in a 2-finger inverter as shown twice in the FIG. 1k physical layout abstraction. For reasons that will be developed, this structure will be named an iFET (MOSFET with a current input terminal=i) where the MOS structure is employed for the present invention.
Although similar MOS structures appear in prior art, no significant exploitation of many of its unique properties are known or published. In addition, proper biasing remains as a problem(s) for its operation(s). A deeper understanding of the internal mechanisms resulted in discovery of many desirable applications (enabling superior operation at deep-sub-micron scale), including an approach to proper biasing that takes advantage of natural equilibrium. This natural equilibrium is the result of a "PTAT"/"CTAT" (proportional to absolute temperature/complement to absolute temperature) known as a "Band-Gap" voltage reference mechanism, again functional at deep-sub-micron scale.
Some references show a MOS field effect device includes a body/substrate 16p, the source terminal 14p and drain terminal 19p on the body 16p. The gate terminal 17p is placed between the source terminal 14p and the drain terminal 19p for controlling conductivity therebetween. The device further includes two identical regions 13p and 15p of like "conductivity type" separated by a diffusion region 11p (designated as Z for Low Impedance in the prior art) as shown in FIG. 1p. Non-patent literature, Pain, Bedabrata et al., "Low-power low-noise analog circuits for on-focal-plane signal processing of infrared sensors", the Jet Propulsion Laboratory, California Institute of Technology, and the Defense Advanced Research Projects Agency and the National Aeronautics and Space Administration; and Baker, Jacob et al., "High Speed Op-amp Design: Compensation and Topologies for Two and Three Stage Design", Boise State University, for example, shows such a structure. However, these references do not exploit any opportunities as shown in this present invention, especially when complementary devices like this are combined into a single composite device structure as will be explained in this invention. Such configurations have been called self-cascading or split-length devices. The two conduction regions of such a configuration are arranged between source and a drain diffusions and have both a high impedance common gate connection and a low impedance Z connection to the mid channel region. This low impedance mid channel control input/output Z, when exploited as outlined in this document, enables an entirely new set of analog design methods and capabilities.
Although a cascode amplifier can be found in prior art, the prior art does not contain a complementary pair of cascode transistors connected as a totem-pole. With this simple compound device structure, feedback from the output to the input can be used to self-bias the resulting inverter into its linear mode. As mentioned above in association with FIG. 1a, the biasing of an amplifier by means of current mirrors has always been problematic; however, the novel and inventive self-biasing structure of the present invention addresses such an issue. Advantages of the configuration of the present invention (referred to as a complementary iFET or CiFET) are many, including, but not limited to:                Gain of the single stage is maximum when the output is at the midpoint (self-bias point);        The gain of a single CiFET stage is high (typically approaching 100), therefore, while the final output may swing close to the rails, its input remains near the midpoint where the gain is high.        When used in a series chain of CiFET devices, all earlier stages operate with their inputs and outputs near the mid-point ("sweet-spot") where the gain is maximized;        Slew rate and symmetry are maximized where the channel current is highest (near the mid-point);        Noise is minimized where the channel current is highest (near the mid-point); and        Parasitic effects are negligible where the voltage swing is small.
When the gate input signal moves in one direction, the output moves in the inverse direction. For example; a positive input yields a negative output, not so much because the N-channel device is turned on harder, but rather because the P-channel device is being turned off. A Thevenin/Norton analysis perspective shows that the current through the P and N devices must be exactly the same, because there is nowhere else for drain current in one transistor to go except through the drain of the complementary transistor; however the voltage drop across those devices does not have to be equal, but must sum to the power supply voltage. Due to the super-saturated source channel, these voltages are tied together exponentially. This is even more evident at low power supply voltages where the voltage gain peaks due to the conduction channels being forced into a diffusion mode of operation similar to weak-inversion. This means that the gate-to-source voltage is precisely defined by the same and only drain current going through both transistors. Exponentials have the unique transparent physical property like as with a time constant, or "half-life;" It does not matter where a value is at a given point of time, a time constant later the value will be a fixed percentage closer to the final value. This is a "minds-eye" illustration of the primary contributor to output movement in response to input change. This same current balance of gate-to-source operating voltages also indicates why the "sweet-spot" in the self-biased amplifier is so repeatable. In effect it is used as a differential pair-like reference point to the amplifier input signal.
Briefly stated, the operation of the conventional CMOS amplifier of FIG. 1a is as follows:
In operation, differential analog input voltages are applied to Input+10a and Input−11a of a precisely matched pair of transistors Q1a and Q2a respectively. Any mismatch in these two transistors appears as a DC voltage added to the differential input. If there is 1 millivolt of mismatch, which is very hard to meet in CMOS, and the amplifier has a gain of 1000, the output voltage error will be 1 volt. In newer IC process nodes, power supplies are already limited to less than a volt. Exotic double centroid physical layout with multiple identical transistors arranged in diametrical opposition and everything else possible symmetrically possible are needed in the physical layout of the differential pair to minimize the offset voltage.
These amplifiers function by steering and mirroring bias currents from a current source 12a between their transistors. All the bias currents have to be larger than the peak signal deviations and these currents always flow. These currents also have to be large enough to drive the internal capacitive load of the amplifier's internal transistors plus interconnect, not to mention the output drive current which comprises the capacitive load at the maximum bandwidth frequency or slew rate.
The first bias current mirror input transistor is a transistor Q8a which is "diode connected" in that its gate and drain are tied together and bias at a threshold voltage below the top power supply rail. This bias voltage is applied to the gates of two transistors Q5a, Q7a additional positive rail based current mirrors that have to be matched to a lesser degree. In order to progressively increase the mirrored currents from the bias current mirror input transistor Q8a to the differential current feed transistor Q5a to the output pull-up current transistor Q7a, the transistors Q5a and Q7a are actually multiple instances connected in parallel. A double for the transistor Q5a and an eight (8) times for the transistor Q7a are typical choices for these multiples.
The differential pair of the transistors Q1a, Q2a is used to split the bias current to the transistor Q5a equally at the zero differential voltage input where the amplifier strives for. To achieve a voltage gain in analog designs, a positive drive current is balanced against a negative drive current. The differential pair of transistors Q1a, Q2a achieves this by mirroring transistor Q3a of the outputs back to the other leg of transistor Q4a, making current opposition with the transistor Q2a. Voltage gain is gm*RL where RL is the parallel combination of the output impedance of the transistors Q4a and Q2a. For analog MOSFET transistors to present a high impedance on their output, they need to be very long because the depilation width due to drain voltage modifies the conduction channel length near the drain terminal. This is called "channel length modulation" which is similar to the bipolar "Early voltage" named by Jim Early of Fairchild Semiconductor during the early bipolar days. For this high output impedance requirement, the transistor Q4a must be long, and it also must be equally wide to preserve its gain setting the basic transistor sizing of the amplifier. This size must be set equal for the transistors Q3a and Q6a, except the transistor Q6a must also include the multiple used for the transistors Q5a to Q7a along with a factor of two to make up for the split of current by the differential pair. In equilibrium, the gate voltage on the transistor Q6a wants to be the same as the gate voltage on the transistors Q3a, Q4a looking like a pseudo-current mirror arrangement at the bottom power supply rail.
There are still many other linear amplifier circuit design considerations beyond these basic principles like stability considerations by compensation resistance or Rcomp 15a and compensation capacitance or Ccomp 16a and power supply noise rejection. As can easily be envisioned, the design of analog circuits in an IC is quite involved, process parameter dependent, and not very portable between IC processes.
The resulting linearity of these amplifiers are also limited due to different non-linear characteristics between the gain device and the load device (pull-up and pull-down) which cannot cancel each other out. The CiFET device structure, which is the present invention to be explained later in this specification, loads itself with the same device structure, except that the combination obtains its complementary nature through the use of opposite semiconductor diffusion types which inherently and precisely mimic any non-linear characteristics with the opposite sign to cancel each other's linearity deviations out. CMOS inverters get their opposing drive through the opposite semiconductor diffusion type, thus are a good foundation to base linearity on. This is because the same current is carried through one transistor is also passed through the complementary device. Inversion is obtained through opposite diffusions.
It is to be noted that during the transition from vacuum tubes to bipolar transistors the industry underwent a major paradigm shift, learning to think in terms of current rather than voltage. With the advent of FETs & MOSFETs the pendulum swing is back toward thinking in terms of voltage, but much knowledge has been lost or forgotten. Herein is contained the rediscovery of some old ideas as well as some new ones, all applied to the up-coming "current" state of the art. It is believed that the inherent simplicity of the present invention speaks to their applicability and completeness.
A first issue may be that there is always a need for a little analog functionality, yet nearly all analog performance metrics of a MOS transistor are remarkably poor as compared to that of a Bipolar transistor. The industry has made MOS devices serve by employing extensive "work-arounds." Conventional analog design is constrained by one or more of the followings:                Power supply voltages sufficient to bias the stacked thresholds, and transistors large enough to supply the necessary low output impedance, or high output impedance for gain and linearity.        Process extensions (unavailable at deep sub-μm scale) to function at all, let alone with the enhanced performance, demonstrated herein.        Resistors, inductors, and large capacitors are mostly non-existent for analog designs in newer IC processes.
In contrast, bipolar transistors can be made to have high gain (β), wider bandwidth, wider dynamic range (many decades, from near the rails down to the noise floor), better matching (required in differential pairs), and band-gap references. Junction FETs, which operate with sub-surface channel conduction below the surface defects, have lower noise than bipolar transistors. Likewise the iFET super-saturated source channel operates primarily below the defects at the channel surface underneath the gate oxide.
MOS designs are poorer in the above areas but have their own extreme advantages, including, but not limited to:                MOS devices are small        highly scalable        high speed        low power        ultra-dense/high functionality systems on a chip, where Bipolar designs cannot go (deep sub-μm scale).
Accordingly, building analog circuits on an IC has always been problematic. Engineering around poorly performing analog components has been the overriding objective for analog IC designers since analog circuits have been integrated. This drove the need for digital signal processing with algorithm development yielding digital magic.
Today the real-world of analog circuit design signals still needs to be converted, on both the front and back end of signal processing systems. This need has become a road-block at deep sub-μm scale.
Another problem may be that solid-state amplifiers have been notoriously non-linear since their inception. To make them linear, increased open loop gain (with levels significantly higher than is ultimately needed) is traded for control over actual circuit gain and linearity through the use of a closed loop (feedback). A closed loop amplifier requires negative feedback. Most amplifier stages are inverting, providing the necessary negative feedback. A single stage, with a closed loop, is stable (does not oscillate). Increased loop gain requires that stages be added such that there are always an odd number of stages (sign is negative), to provide the necessary negative feedback. While a single stage amplifier is inherently stable, three stages and most definitely five stages are unstable (they always oscillate).
The problem then is how to properly compensate a multi-stage closed loop amplifier while maintaining a reasonable gain-bandwidth product. This is particularly difficult at deep-sub-micron scale where circuit stages must be simple in their design. The severely limited power supply voltages preclude the use of conventional analog design approaches. Additionally, it is desirable to avoid reliance upon analog extensions but rather to accomplish the necessary analog functions using all digital parts, to improve yields and decrease costs. Using all digital parts allows analog functions at process nodes that do not yet have analog extensions, and may never have them.
There is a long felt needs for low-cost/high-performance systems on a single chip to realize, affordable high-volume devices such as the Internet of things, smart-sensors, and other ubiquitous devices.

Complementary current field-effect transistor devices and amplifiers


Disclosed herein is a structure for preventing current from leaking out of devices such as a valve, an intermediate reservoir, etc., which are employed in an electrostatic spray coating apparatus for applying a desired voltage to electrically conductive paint so as to electrostatically spray-coat a workpiece therewith. The current-leakage prevention structure basically comprises any one of the devices each made of an electrically-conductive material, a container made of an insulating material, which accommodates the device therein and has a paint passage defined therein capable of communicating with the device, and a cover for externally covering the container. A creepage distance defined by the container and the cover is set to reach a desired creepage length or more capable of preventing current leakage. It is therefore possible to reliably prevent current from leaking even when a high voltage is applied to the devices.

1. Field of the Invention
The present invention relates to a structure for preventing current from leaking out of devices such as a valve, an intermediate reservoir, etc., which are employed in an electrostatic spray coating apparatus for applying a desired voltage to electrically conductive paint so as to electrostatically spray-coat a workpiece therewith.
2. Description of the Related Art
As an electrostatic spray coating or painting apparatus for applying a high voltage to electrically conductive paint so as to electrostatically spray-coat an object such as a car body to be coated therewith, there has heretofore been known a paint color-changeover system disclosed in Japanese Patent Application Laid-Open No. 2-2885, for example.
According to the disclosure, the paint is first introduced into an intermediate reservoir electrically insulated from ground potential. Thereafter, the paint is supplied via a paint passage from the intermediate reservoir to a spray gun subjected to a high potential. Thus, a process for electrostatically spray-coating the object to be coated with the paint is carried out.
In the above disclosure, even the intermediate reservoir has been subjected to a considerable high voltage. It is therefore necessary to make devices such as the intermediate reservoir, various valves of insulating materials. However, the devices made of the insulating materials has problems in accuracy and strength, and the manufacturing cost is raised.
Further, a line is coupled to the devices through a joint. Thus, current tends to leak from the joint. When an electric conductor such as a human body approaches one of the devices, an electric discharge takes place due to insulation breakdown.
Therefore, there has been made the following approach. For example, a block valve mechanism disposed between a paint feed source and an intermediate reservoir, the intermediate reservoir, and a flow control valve for controlling the delivery rate of electrically conductive paint supplied to a spray gun from the intermediate reservoir are spaced away from one another by a distance required to reliably provide insulation against a high voltage applied to the paint. Under this condition, they are disposed on the same plane.
In the disclosure referred to above, however, the devices such as the block valve mechanism, the intermediate reservoir and the flow control valve are spaced away from one another by the distance referred to above. Therefore, spaces for disposing the devices are greatly increased. Further, since the devices are exposed to the outside, there is much risk of an electrical short when a robot arm approaches the devices, for example.
As a result, the devices cannot be disposed within a spray booth or near an electric conductor. In addition, the length of the line extending up to the spray gun increases. Therefore, paint is wasted in quantity when a color changeover process is performed. Further, much cleaning time is required and the quantity of cleaning liquid to be used is increased.

Structure for preventing current from leaking out of devices for electrostatic spray coating


A calculation system (1) for manufacturing an ophthalmic lens. A set of calculation modules (M1, M2, M3, M4) is associated to partial calculation in relation with manufacturing process of said ophthalmic lens. A managing unit (MU) is configured to: receive input data, and calculate output data through one or several iteration(s) of: determining one or several calculation module(s) to be activated, determining an order of activation of the one or several calculation module(s), and activating the determined one or several calculation module(s), in accordance with the determined order of activation. The managing unit transmits an indication that the output data have been calculated.

The discussion of the background of the invention herein is included to explain the context of the invention. This is not to be taken as an admission that any of the material referred to was published, known or part of the common general knowledge at the priority date of any of the claims.
Ophthalmic lens is commonly used for correcting many different types of vision deficiencies of a wearer of the ophthalmic lens. These include defects such as near-sightedness (myopia) and far-sightedness (hypermetropia), astigmatism, and defects in near-range vision usually associated with aging (presbyopia).
An ophthalmic lens is typically made of plastic or mineral material and generally has two opposing surfaces which co-operate with one another to provide a required refractive property, generally corresponding to the wearer's prescription.
Currently, for providing an ophthalmic lens, an eye care practitioner orders the ophthalmic lens at an ophthalmic lab by sending an order request to the ophthalmic lab. The order request comprises wearer data, for example the wearer's prescription, and optionally other wearer's parameters, such as a head/eye movement coordination parameter and/or an eye rotation center. The order request further comprises spectacle frame data, for example the type of spectacle frame the wearer has selected, and lens data, for example the type of ophthalmic lens the wearer has selected.
The ophthalmic lab receives the order request and sends it to an ophthalmic lens designer. The lens designer uses the data comprised in the order request to calculate an ophthalmic lens design, by using an ophthalmic lens calculator. The ophthalmic lens design comprises optical data of the ophthalmic lens to be provided to the wearer, and manufacturing process data related to the manufacturing process of the ophthalmic lens.
The ophthalmic design determined by the lens designer is sent to the ophthalmic lab and the ophthalmic lens is manufactured based on the calculated design. The manufacturing process may for instance comprise a blocking step, a surfacing step, a polishing step and a marking step.
The current ophthalmic lens manufacturing process presents some drawbacks.
Firstly, each ophthalmic lab has its own management entity, and its own apparatus and tools. Consequently, each lens designer has to be adapted to calculate manufacturing process data for the different ophthalmic labs.
This may be achieved by using, in the ophthalmic lens calculator, a database containing ophthalmic labs data related to the different labs. However, some labs data may not be obtained or updated, and this may result in performing a manufacturing process based on incorrect calculated manufacturing process data.
In a similar way, each ophthalmic lab has to be adapted to perform a manufacturing process based on manufacturing process data calculated by different lens designers. In particular, some lens designer calculators are configured to compute all the necessary information (optical information and manufacturing information) to manufacture an ophthalmic lens in a single calculation, while other lens designer calculators are mainly focused on optical calculations, and not as much on how to manufacture the design.
Secondly, the manufacturing process data are calculated prior to the beginning of the manufacturing process, and it is not possible to recalculate some of the manufacturing process data during the manufacturing process, for example to update the manufacturing process data based on measured process data. This may result in a lack of precision.

Calculation system for manufacturing an ophthalmic lens


Methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning. A mandrel line including an upper layer and a lower layer is formed over a hardmask. A non-mandrel cut block is formed over a portion of a non-mandrel line, after which the upper layer of the mandrel line is removed. An etch mask is formed over a first section of the lower layer of the mandrel line defining a mandrel cut block over a first portion of the hardmask. The first section of the lower layer is arranged between adjacent second sections of the lower layer. The second sections of the lower layer of the mandrel line are removed to expose respective second portions of the hardmask, and the second portions of the hardmask are removed to form a trench. The mandrel cut block masks the first portion of the hardmask during the etching process.

The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of self-aligned double patterning and interconnect structures formed by self-aligned double patterning.
A back-end-of-line (BEOL) interconnect structure may be used to connect device structures, which have been fabricated on a substrate during front-end-of-line (FEOL) processing, with each other and with the environment external to the chip. Self-aligned patterning processes used to form a BEOL interconnect structure involve linear mandrels acting as sacrificial features that establish a feature pitch. Non-mandrel lines are arranged as linear spaces between sidewall spacers that are formed adjacent to the sidewalls of the mandrels. After the mandrels are pulled to define mandrel lines, the sidewall spacers are used as an etch mask to etch a pattern predicated on the mandrel lines and the non-mandrel lines into an underlying hardmask. The pattern is subsequently transferred from the hardmask to an interlayer dielectric layer to define trenches in which the wires of the BEOL interconnect structure are formed.
Mandrel cuts may be formed in the mandrels in order to section the mandrels and define discontinuities between the sections. Non-mandrel cuts may also be formed along non-mandrel lines and may include portions of the spacer material used to form the sidewall spacers. The mandrel cuts and non-mandrel cuts are included in the pattern that is transferred to the hardmask and subsequently transferred from the hardmask to form the trenches in the interlayer dielectric layer. The mandrel cuts and non-mandrel cuts appear in the BEOL interconnect structure as adjacent wires that are spaced apart at their tips with a tip-to-tip spacing related to the dimension of the discontinuity.
The tip-to-tip spacing for a cut mandrel is limited to a distance equal to twice the thickness of the sidewall spacers. If the tip-to-tip spacing is greater than this distance, the sidewall spacers do not merge within the mandrel cut between the sections of the mandrel, which results in incomplete filling of the mandrel cut. Transverse to the length of the cut mandrel, the mandrel cut is arranged in the pattern between non-mandrel lines that flank the cut mandrel line. The result of the incomplete filling can be a short between wires in the BEOL interconnect structure formed using the non-mandrel lines at the location of the mandrel cut. In addition, the wrapping of the sidewall spacers about the tips of the sections of the cut mandrel may introduce notches or indents at the side edges of the merged sidewall spacers. These notches or indents may form metal asperities that project from the side edges of wires formed using the adjacent non-mandrel lines into the mandrel cut. The proximity of these metal asperities may also result in shorting of wires in the BEOL interconnect structure formed using the non-mandrel lines.
Improved methods of self-aligned double patterning and improved interconnect structures formed by self-aligned double patterning are thus needed.

Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks