Apparatus for aligning a refining disc is a refiner is disclosed, the apparatus including a first wedge slidable along a support for the axle package of the refining disc, a second wedge disposed between the first wedge and a bearing housing in which the rotatable axle of the axle package is journalled, the second wedge being slidable transversely to the slidable movement of the first wedge, a controller for controlling displacement of the first wedge including an actuator at one end of the support and a control axle extending from the actuator to the first wedge, the control axle being rotatable and rotatably secured to the first wedge whereby operation of the actuator causes rotation of the control axle, which in turn causes displacement of the first wedge which causes transverse displacement of the second wedge.

For highly concentrated refining, CTMP, TMP, fluffing and highly concentrated grinding of sack paper and other lignocellulose-containing material, refining apparatus or disc refiners are used. Examples of refining apparatus are described in U.S. Pat. No. 6,957,758 and EP Patent No. 386;031. Refining apparatus usually comprise two opposite refining discs rotatable in relation to each other, where usually one refining disc is rotatable, a so called rotor, and one refining disc is non-rotatable, a so called stator, but in some refining apparatus both refining discs are rotatably arranged. The refining discs in this type of refining apparatus are provided with replaceable refining segments which form the refining surfaces of the refining apparatus. The refining segments comprise bars and intermediate grooves. Refining occurs between the two refining surfaces which are held at a certain distance from each other, whereby a space, known as a refining gap, is provided between the refining surfaces.
If the refining surfaces were to come in contact with each other during operation, this will result in a risk of a breakdown or at least result in wear of the refining surfaces, and thus a shortened operating performance. Furthermore, the degree of alignment between the refining surfaces has a crucial importance for the quality of the ground material. When the degree of alignment between the refining surfaces decreases, the quality of the refined material is deteriorated. A correct alignment between the refining surfaces is therefore of great importance.
To obtain a correct alignment between the refining surfaces of the refining discs it is a prerequisite that the rotation axle, to which the rotor is attached, obtains correct alignment. To angle the axle in relation to the horizontal plane and the vertical plane, two alignment devices are used, which align the whole axle package, to which the axle and the rotor belongs. Such an alignment device according to known technology is described in more detail in the detailed description in connection with FIGS. 1 to 6. The alignment of the axle package, and thus of the axle and the rotor, is performed with approximately one-month intervals for a refining apparatus in operation. The adjustment of the axle along its own longitudinal axis is performed by means of another adjustment device which displaces the whole axle package in relation to the support in the direction of the longitudinal axis of the axle. This lengthwise adjustment of the axle package, and thus of the size of the refining gap, is performed several times per second, as the refining gap often must be reduced or increased because of the constant change in the quality of the material intended for refining, such as the amount of material per time unit. To obtain correct alignment between the refining surfaces of the refining discs, an alignment of the refining surfaces themselves in relation to the refining discs also takes place. An example of alignment of the refining surfaces themselves is given in British Patent No. 1,468,649.
Certain problems exist, however, with the present alignment devices for aligning the refining disc of a refining apparatus, of which an example is described in detail in FIGS. 4 to 6.
The requirement that the contact surface of the upper wedge-shaped member against the bearing housing must form different angles with the horizontal plane so that, at different settings of the axle package, they fully bear against the exterior surface of the bearing housing, results in the requirement that the upper wedge-shaped member must rotate in relation to the horizontal plane. This "tilting" of the upper wedge-shaped member results in a relatively large sideway play between the upper wedge-shaped member and the space in the support in which the upper wedge-shaped member is provided. This play results, however, in the upper wedge-shaped member easily jamming in its installation space in the support. Furthermore, the flat contact surface of the upper wedge-shaped member against the bearing housing and the flat contact surface of the bearing housing against the upper wedge-shaped member have a very even surface as these repeatedly slide in relation to each other, which poses high requirements on the machining of these flat surfaces.
The requirement that the actuator of the alignment device must be placed on the side of the support which is facing away from the refining housing, so that the operator is able to control same, has led to a complicated construction of the alignment device, where the alignment by means of the alignment device includes many steps. This also results in a long distance between the securing point of the alignment device in the support and the lower wedge-shaped member, which leads to rendering the respective alignment device sensitive to temperature influence, and in addition the construction is not unresilient enough.
The above-mentioned problems will appear more clearly from the detailed description, where the prior art is described in more detail.
One of the objects of the present invention is thus to provide an alignment of the refining disc of a refining apparatus, which is reliable in service and straightforward to perform.

Device for aligning the refining disc of a refining apparatus


A lower tool frame is used in manufacturing a plurality of convertible roofs. Structural roof parts are disposed in the lower tool frame upside down with respect to their use position. Forward connection parts are provided for selectively connecting the forward end of the convertible roof to a windshield frame and rearward connection parts are provided for attaching the rearward end of the convertible roof to a vehicle body. A single upper tool frame is lowerable onto the lower tool and is used to position the forward and rearward connection parts with respect to the structural roof parts. The single upper tool frame is used to assemble all of the convertible roofs for a series of vehicles.

It is necessary in the mass production of convertible roofs to maintain high dimensional precision to allow assembly of the roof to the vehicle body in as time saving a manner as possible and with as little adjustment effort as possible and to be able to ensure high dimensional accuracy and qualitative equivalence.
It is known to assemble a series of convertible roofs on parallel production stands which simulate in their position and alignment the relationships of vehicle bodies onto which the finished roofs are to be placed. A plurality of production steps must be carried out manually using templates and in an unfavorable work position with the respective assembly person looking up and working from below.
In addition problems may arise due to dimensional differences or complaints that must be traced to the production stand and the person(s) associated with a particular roof. This tracing is, however, very important for the quality assurance and, optionally, the remedying of errors.
The spacing between the front crossmember of a production stand, which simulates the windshield frame, and the rear lateral support consoles, which simulate body side mounts for lateral main support units of the roof, is set in an optimized manner. This must take into account not only the tolerances for the assembly of the parts of the roof, but also the tolerances in the design of the production stand, which makes it more difficult to provide uniformity of roofs.
Within a series of vehicles, the relative spacing between the rear consoles, where the convertible top connects, and the front windshield frame is typically constant. To compensate for possible production tolerances of the roof, the position of at least one axis of rotation within the mechanism moving the roof may be adjusted. Typically, the axis of rotation between the roof linkage and a lateral roof frame is adjusted. This variability can be achieved, for example, using lateral elongate holes. However, this results in kinematics of the roof movement which are slightly modified in dependence on the tolerance so that said roof movement takes place with non-optimized torques and with jerks under certain circumstances.

Method of manufacturing a plurality of convertible roofs for vehicle bodies


An MEMS element (A1) includes a substrate (1), and a first electrode (2) formed on the substrate (1). The MEMS element (A1) further includes a second electrode (3) including a movable portion (31) spaced from the first electrode (2) and facing the first electrode. The movable portion (31) is formed with a plurality of through-holes (31a). Each of the through-holes (31a) may have a rectangular cross section.

Conventional MEMS elements are disclosed in e.g. Patent Documents 1 and 2 listed below. The MEMS element disclosed in Patent Document 1 will be described below with reference to FIGS. 18 and 19 of the present application, and the MEMS element disclosed in Patent Document 2 will be described below with reference to FIGS. 20 and 21.
Patent Document 1: JP-A-2004-12327
Patent Document 2: JP-A-2005-40885
The conventional MEMS device X shown in FIG. 18, structured as a capacitance type acceleration sensor, includes a substrate 91 on which an MEMS element Y and controllers 95a and 95b are mounted. The substrate 91, the MEMS element Y and the controllers 95a and 95b are covered by a resin package 96. A plurality of external terminals 97 for mounting project from the resin package 96.
FIG. 19 is an exploded perspective view of the MEMS element Y. As shown in the figure, the MEMS element Y includes a pair of glass substrates 92a and 92c, and an Si substrate 92b which are laminated. A movable electrode 94 comprising a movable portion 94a and a support portion 94b is incorporated in the Si substrate 92b. The MEMS element Y including such an Si substrate is generally called an MEMS element by bulk micromachining.
The paired glass plates 92a and 92c are formed with fixed electrodes 93a and 93b, respectively. The movable portion 94a and the fixed electrode 93a face each other, thereby forming a variable capacitor. Similarly, another capacitor is formed between the movable portion 94a and the fixed electrode 93b. When acceleration occurs in the vertical direction in FIG. 19, the movable electrode 94 is relatively moved up or down, whereby the capacitances of the two capacitors will vary. Based on the variation of the capacitances, the MEMS device X determines the magnitude of the acceleration.
The MEMS device X may be mounted to a cellular phone provided with a HDD as the recording medium. With such an arrangement, when the cellular phone is overaccelerated, the MEMS device X detects the acceleration. For instance, when the user drops the cellular phone onto the floor, the MEMS device X can detect the fall. Thus, it is possible to arrange that, based on such detection, the rotation of the HDD may be stopped, or the data read/write head may be moved away from the HDD.
To utilize the MEMS device X in the above-described manner, the MEMS device X needs to have a small thickness to be able to be mounted to the cellular phone. However, the MEMS device X is relatively thick because of the employment of the MEMS element Y processed by the bulk micromachining. Specifically, the Si substrate 92b of the MEMS element Y incorporates the movable electrode 94 by chipping a relatively thick Si material. Thus, the MEMS element Y comprising the lamination of the Si substrate 92b and the glass substrates 92a, 92c has a relatively large thickness. Since the MEMS device X further includes a resin package 96 for sealing the MEMS element, the thickness of the MEMS device X further increases. Thus, the MEMS device X cannot meet the demand for thickness reduction.
As shown in FIG. 20, the MEMS element disclosed in Patent Document 2 includes a substrate 91′, and a lower electrode 92′ and a wiring 95′ formed on the substrate. An upper electrode 93′ is connected to the wiring 95′. The upper electrode 93′ includes a movable portion 93a′ spaced from the lower electrode 92′ in the vertical direction in the figure and facing the lower electrode.
When the MEMS element is used for an acceleration sensor, the magnitude of the acceleration in the vertical direction in FIG. 20 is measured based on the variation of the capacitance between the lower electrode 92′ and the upper electrode 93′. Specifically, the capacitance between the lower electrode 92′ and the upper electrode 93′ depends on the size of the gap between the lower electrode 92′ and the movable portion 93a′ of the upper electrode 93′. When acceleration in the vertical direction is produced, the movable portion 93a′ is relatively moved in accordance with the acceleration, causing the size of the gap to vary. As a result, the capacitance varies. By electrically measuring the variation of the capacitance, the magnitude of the acceleration can be determined.
FIG. 21 shows a step in the process of manufacturing the MEMS element of FIG. 20. In this manufacturing process, a sacrifice layer 94′ is formed to cover the lower electrode 92′, and a movable portion 93a′ is formed on the sacrifice layer 94′. Then, by removing the sacrifice layer 94′, a gap of a predetermined dimension is defined between the lower electrode 92′ and the movable portion 93a′. The removal of the sacrifice layer 94′ may be performed by wet etching using an etchant which dissolves only the sacrifice layer 94′.
To enhance the measurement accuracy of the acceleration sensor utilizing an MEMS element, it is preferable that the capacitance of the MEMS element is large. To increase the capacitance of an MEMS element, the size of the lower electrode 92′ and movable portion 93a′ needs to be increased, and the gap between the lower electrode 92′ and the movable portion 93a′ needs to be reduced. However, to increase the size of the lower electrode 92′ and movable portion 93a′, the size of the sacrifice layer 94′ also needs to be increased. As a result, the time required for removing the sacrifice layer 94′ increases, which deteriorates the manufacturing efficiency of the MEMS element. Further, when the gap between the lower electrode 92′ and the movable portion 93a′ is reduced, the possibility that the movable portion 93a′ adheres to the lower electrode 92′ due to the surface tension of the etchant increases. In this way, when the measurement accuracy of an acceleration sensor is intended to be enhanced, various problems are caused in the process of manufacturing the MEMS element.
The above-described problems occur also in the process of manufacturing an actuator using the MEMS element shown in FIG. 20. Specifically, in an actuator utilizing the MEMS element, the movable portion 93a′ is driven by applying a voltage between the lower electrode 92′ and the upper electrode 93′. To enhance the operation accuracy of the movable portion 93a′, the size of the lower electrode 92′ and movable portion 93a′ needs to be increased, and the gap between the lower electrode 92′ and the movable portion 93a′ needs to be reduced. However, when the size of the lower electrode 92′ and movable portion 93a′ is increased, the manufacturing efficiency of the MEMS element is deteriorated. Further, when the gap between the lower electrode 92′ and the movable portion 93a′ is reduced, these parts may adhere to each other.

MEMS element, MEMS device and MEMS element manufacturing method


Peripherals and data processing systems are disclosed which can be configured to interact based upon sensor data. In at least certain embodiments, a method for sensing motion and orientation information for a device includes receiving a motion event from at least one sensor located in a device. The method further includes determining an orientation for a display of the device. The method further includes determining whether the device is currently moving. The method further includes determining whether the device moves within an angle with respect to a ground reference for a first time period. The method further includes switching the orientation of the display of the device if the device moves in excess of the angle.

Electronic devices, such as computer systems or wireless cellular telephones or other data processing systems, may often be used with peripheral devices. A peripheral device, such as a wired or wireless headset or a wireless or wired keyboard or a wired or wireless cursor control device, is coupled to the electronic device which may be referred to as a host system. The peripheral typically provides input and/or output capabilities to the electronic device.
The peripheral may also be configured to operate with only one particular electronic device or host. For example, a wireless headset peripheral may be paired with a designated wireless cellular telephone so that it communicates with that designated wireless cellular telephone rather than other wireless cellular telephones which are within radio range of the wireless headset. This allows a user to operate the wireless headset with its designated wireless cellular telephone even though it may be surrounded by other wireless cellular telephones which are within the radio range of the wireless headset. Thus, the wireless headset in this case includes some intelligence or data which allows it to selectively operate with a designated host system, but there is no further processing or sensing capability in the wireless headset. A Bluetooth pairing or partnership is an example of a relationship created between a peripheral and a host. It is created by the user in order to exchange information in a secure manner. Creating a Bluetooth partnership between two devices involves entering the same personal identification number (PIN) or passkey on both devices; creating such a partnership is a one-time process. Once a partnership is created, the devices can recognize the partnership and exchange information without entering a PIN again.
Certain electronic devices described previously include sensors for various purposes. However, these sensors (e.g., an accelerometer sensor, a proximity sensor and an ambient light sensor) can not properly detect and distinguish whether an intentional or unintentional user action causes the occurrence of motion and/or orientation information for the device. For example, unintentional movements of a device can trigger improper configurations for the device. An unintentional movement may include a device moving with a user who is jogging or if a user quickly places a device on a surface causing the device to move for a short time period. The sensors are also not able to determine interactions between an associated peripheral and the device.

Methods and systems for providing sensory information to devices and peripherals


A digital crossbar switch designed to facilitate easy and flexible interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the ports is controlled by 32 stored control memory locations associated with each port. The controlling memory locations can be changed dynamically without interfering with data flow. Additional program flexibility can be achieved by providing each port with a 16 word first-in first-out data buffer. The capability to bit reverse the data on any of the ports is also provided to simplify the interconnection of busses from different architectures. The device is fully expandable to wider busses, has extensive test capability and a master reset is provided for system initialization.

I. Field of the Invention
The present invention relates generally to digital crossbar switches for loading and transferring data from multiple sources to multiple destinations. More particularly, the invention relates to a multiple-port digital crossbar switch that can be dynamically programmed and reprogrammed to load each port.
II. Background of the Invention
Digital crossbar switches require high speed data loading and transmission in order to allow their host computer to solve complex programs such as integrated circuit simulation, global weather predictions, Monte Carlo simulations in solid state particle physics or fault simulation of a nuclear reactor, to name just a few examples. The speed of digital crossbar switches can be related to the manner and method in which the data is received by the individual crossbar ports, stored within the ports, the number of ports and how read from the ports. Most often these and other system parameters are determined by hardwired connections which are physically inadequate for complex computations or lack program flexibility to allow adjustment for dynamically changing problematic conditions. It should thus be apparent that it is desirable to have a digital crossbar switch which is physically hardwired to achieve multiple permutations of data loading and unloading and which also is dynamically reprogrammable to allow changing of routing functions without interrupting data flow.

Programmable configurable digital crossbar switch


A new apparatus, system and method for fall prevention training is provided that delivers, studies and analyzes the biomechanics of a disturbance event, such as a slip or trip incident, so that an appropriate response can be executed by the person to reduce or eliminate the number of falls experienced. The apparatus includes a platform that delivers a disturbance event in less than about 500 ms and preferably in the range of about 100 ms to about 200 ms. The method includes a unique protocol for fall prevention training using the apparatus.

The present invention generally relates to the medical rehabilitation field. More specifically, the present invention relates to a method for fall prevention training using a dynamic perturbation platform to improve the study and research of the biomechanics of trip, slip, and laterally-directed postural disturbances by a person and the step recovery thereof.
It is well known in the medical field that a slip or trip during walking or standing can lead to a fall and be a serious cause of injury. This is particularly problematic for elderly people where such injuries are a leading cause of mortality. It is well known that many of these injuries can be prevented or their severity lessened if the person uses an effective strategy and technique for responding to a fall situation. Therapeutic Interventions can reduce the likelihood of a fall from a disturbance event, such as a trip or slip incident. Exercise and physical training can be used to develop strength, balance and coordination. Also, the person's environment can be changed to remove obstacles and other hazards that can cause a slip or trip. Bars and hand rails can be provided to assist walking and standing. Padded garments can be worn by the person to reduce the injury caused by the slip or fall.
An alternative approach is to study why a person falls and train them to better recover from a slip or trip to avoid a fall by taking a corrective step response. Therefore, the biomechanics of a slip or fall can be studied to better understand clinically effective ways to prevent such falls due to a slip or trip. As part of the study and analysis of disturbance events, including slip and trip incidents, it is highly desirable to be able to monitor a slip or fall incident in a controlled environment to produce data that is usable for effective training to help persons adapt their strategy for responding to a slip or trip incident.
In view of the foregoing, there is a need for a system that can accurately simulate a slip or tripping incident. There is a need for a system that can measure the biomechanics of a slip or tripping incident to further assist a person to better respond to the incident to avoid a fall. There is a further need for an apparatus that is well-suited to measure such biomechanics. There is a need for an apparatus that can simulate various trip and slip scenarios that could lead to a fall so an appropriate response can be developed. There is a need for an apparatus and system that can better train a person to avoid a fall following a trip or slip incident. Moreover, there is a need for a method for fall prevention training to better prepare a person for a disturbance event, including, a slip, trip or fall, to avoid injury or death.

Fall prevention training system and method using a dynamic perturbation platform


A linear motor in which the shape of magnetic pole surfaces of pole teeth located at both ends of a plurality of pole teeth can be easily formed to be suitable for reducing cogging force. Each of magnetic pole surfaces 19a of pole teeth 15A located at both ends of a plurality of pole teeth 15 is constituted by an arc-shaped curved surface that is curved so that a gap from a stator 1 increases with increasing distance from other adjacent pole tooth 15B. Through holes 23A and 23B that extend in the laminating direction of electromagnetic steel plates 10 are formed in the vicinity of the magnetic pole surfaces 19a of the pole teeth 15A. Inside the through holes 23A and 23B, magnetic pieces, which are shorter than the thickness of the electromagnetic steel plates in their laminating direction, are arranged so as to leave spaces at both ends of the through holes 23A and 23B.

The present invention relates to a linear motor.
As an example of a linear motor in which a movable element reciprocates linearly relative to a stator, the linear motor has an armature and at least one row of magnetic poles formed by juxtaposedly arranging a plurality of permanent magnets. The armature has a core which is constituted by laminating a plurality of electromagnetic steel plates and exciting windings. The core has a yoke that extends linearly in a direction orthogonal to the direction in which the electromagnetic steel plates are laminated, and a plurality of pole teeth that protrude from the yoke toward the magnetic pole row side and have magnetic pole surfaces opposed to the row of magnetic poles or magnetic pole row at their ends. A plurality of the exciting windings excite the pole teeth. In the linear motor of this type, however, large cogging force is generated. Thus, in order to solve this problem, there has been proposed a linear motor in which a processed metal plate was mounted so as to cover the core, as shown in FIG. 7 of U.S. Pat. No. 4,638,192. This processed metal plate has portions that protrude from both ends of the core in the reciprocating direction of the movable element. Each of these protruding portions has an arc-like curved surface so that a gap between the row of magnetic poles or magnetic pole row increases with increasing distance from the respective adjacent pole tooth.
However, in this linear motor, the metal plate is processed to form the arc-like curved surfaces. Thus, it was difficult to form the optimum arc shape for reducing the cogging force. Further, since the processed metal plate is employed, eddy current loss increases. Still further, the curved surfaces tend to deform due to an external force. For these reasons, variations in the quality of the linear motor were apt to occur.


A method for producing fine patterns is disclosed, comprising spin-coating a photosensitive resin solution as an upper layer, which comprises a diazonium salt as a photobleachable agent, water and/or an organic solvent, and a polymer, on a photoresist layer as a lower layer and then light-exposing both the upper layer and the lower layer, wherein the polymer in the upper layer has a structural unit shown by formula (I): ##STR1## wherein R.sub.1, R.sub.2, and R.sub.3 each represents a hydrogen atom, an alkyl group having from 1 to 4 carbon atoms, a halogen atom, or a nitrile group; R.sub.4 represents a hydrogen atom, an alkyl group having from 1 to 4 carbon atoms, a halogen atom, a hydroxyl group, or a carboxyl group; and X represents a hydrogen atom, an alkali metal, an alkaline earth metal, or an ammonium group.. According to another embodiment of this invention, a method for producing fine patterns is disclosed, comprising spin-coating a photosensitive resin solution as an upper layer, which comprises a diazonium salt as a photobleachable agent, water and/or an organic solvent, and a polymer, on a photoresist layer as a lower layer, wherein a counter anion of the diazonium salt is a functional group of the polymer in the photosensitive resin.. According to this invention, a light of low contrast can be increased to one of high contrast without requiring complicated steps, and patterns of less than 1 .mu.m can be produced with good precision.

With the increase of integration scale of integrated circuits, the feature sizes of patterns tend to shrink more and more and, recently, a high-precise pattern profile of less than about 1 .mu.m in line width has been demanded. For meeting this demand, various methods have been proposed.
For example, from the aspect of apparatus, at the following two points:
(1) use of a light source of shorter wavelengths; and
(2) use of lens having a large numerical aperture have been proposed for increasing the resolution from optical theory, and test machines are marketed. However, when a light source having shorter wavelengths is used, the percent transmission of a lens is reduced and, thus, a sufficient amount of the light is not obtained. Also, when a lens having a large numerical aperture is used, there occurs a problem that the resolution becomes worse on the wafer with topography because the depth of focus becomes shallow.
On the other hand, from the aspect of the resist, the development of a resist having high contrast (hereinafter referred to as "high-gamma resist") has been attempted. A high-gamma resist surely improves the resolution to some extent. Also, the high-gamma resist can be produced by controlling the molecular weight and dispersion degree of a polymer in the resist. However, in the case of using such a high-gamma resist, there is a restriction on the material to be used, and the resolution is not improved to a great extent.
Also, from the aspect of lithography, there are proposed the following methods:
(1) a method of using a multilayer resist; and
(2) a method of spin-coating a photosensitive resin on a resist film.
The method of using a multilayer resist can provide patterns having a high resolution of less than about 1 .mu.m, but there are yet problems as an industrial technique in the method because the process is complicated, the production of devices requires a too long period of time, and the yield for the production of devices is low.
In the method of spin-coating a photosensitive resin on a resist film, the resolution is improved as follows. That is, light directly after passing through a mask has high contrast, but the contrast of the light is reduced after the light passes through space and a lens. In this regard, according to the improved method, the reduced contrast of the light is increased again by passing through the photosensitive resin to thereby improve the resolution.
As a photobleachable material contained in the photosensitive resin, there are proposed nitron compounds as described, for example, in Japanese Patent Application (OPI) No. 104642/84 or diazonium salts as described, for example, in Japanese Patent Application (OPI) No. 238829/85 (the term "OPI" as used herein means an "unexamined published patent application").
The method of using a nitron compound may certainly improve the resolution, but since in the method an interlayer is required between a resist layer as the lower layer and a photosensitive layer as an upper layer, there are problems that the process becomes complicated and the yield for the production of semiconductors is not so improved.
In the method of using a diazonium salt, the improvement effect for resolution is not yet satisfactory, and the diazonium salt to be used has problems in terms of storage stability.
The inventors have investigated on the method of using a diazonium salt as a photobleachable agent in the aforesaid methods of forming a photosensitive layer which is bleached by light based on the considerations that a method capable of simultaneously developing a photosensitive layer with the developer of the lower layer can simplify the process, and a great improvement of resolution can be expected in this case.
As the result of investigations using a method reported as an evaluation method for the mechanism of positive photoresist. (F. H. Drill et al, Characterization of Positive Photoresist, IEEE Transactions on Electron Devices, Vol. ED-22, No. 7, July 1975 by IBM Corp., U.S.A.), the inventors have discovered that the resolution can be greatly improved by increasing an A value as defined below.
The A value is generally shown by the following equation: ##EQU1## T(0): Initial Transmittance T(.infin.): Final Transmittance
d: Film Thickness
For increasing the A value, it can be considered to reduce the film thickness (d), give a high transmittance to the photosensitive layer (upper layer) after bleaching (that is, the value of T(.infin.) is near 100% as close as possible), and also reduce the initial transmittance T(0) as low as possible. In order to reduce the value of T(0), the concentration of a diazonium salt as a photobleachable agent in the photosensitive layer may be increased, but if the concentration thereof is increased, crystals of the photobleachable agent deposit after coating, which results in rather reducing the resolution.
Also, a method of adding an additive such as a sulfonic acid derivative or a salt thereof for increasing the solubility as disclosed in Japanese Patent Application (OPI) No. 238829/85 cannot increase the effect owing to the limitation on the addition amount thereof because if the amount is large, the coating properties of the photosensitive layer are reduced.
Furthermore, there is also a problem that the diazonium salt as a photobleachable agent is poor in heat stability.
Diazonium salts capable of absorbing a light of longer wavelength are generally poorer in stability. However, as described above, the lithography using light having a short wavelength has a problem that the light transmittance is lowered. Furthermore, manufacturers for semiconductor integrated circuits have a desire of elongating the life of a light-exposure apparatus (mainly using a light of 436 nm at present) in order to avoid an increase in investment for equipment and, hence, an improvement in stability of diazonium salts is an important factor in this field of technique.
Thus, when the stability of a diazonium salt was investigated by adding thereto a stabilizer such as phosphoric acid, organophosphoric acid, citric acid, tartaric acid, etc., an improvement effect was confirmed to some extent and, hence, when a large amount of the aforesaid additive was added for further improving the stability of the salt, it was further confirmed that the coating properties were reduced to thereby lower the resolution.
For solving the above-described problems, the inventors have made various investigations on polymers used for photosensitive resins, and as the result thereof, it has been discovered that by using a polymer containing a benzenesulfonic group, the solubility of the diazonium salt in a solvent is increased, the deposition of crystals of the diazonium salt at spin-coating is prevented, and further the stability of the diazonium salt can be improved.
Also, it has been found that by utilizing a functional group of the polymer in a photosensitive resin as a counter anion of the diazonium salt, a large amount of the diazonium salt can be dissolved without reducing the coating properties and, at the same time, the stability of the diazonium salt can be improved. As the result thereof, fine patterns can be produced with high precision, and based on these discoveries, the present invention has been attained.

Method for producing fine patterns utilizing specific polymeric diazonium salt, or diazonium salt/sulfone group containing polymer, as photobleachable agent


An rf pulse compressor has a single high Q cavity resonator fed by a four port hybrid coupler which is connected to the resonator at coupling ports located at the intersection of two of the resonator's orthogonal axes with the resonator cavity walls. The hybrid coupler divides pulse power from an rf pulse power source and excites two space and phase orthogonal modes in the single cavity, the stored energy of which aids in producing compressed pulses at the output of the hybrid. On-axis perturbations in the cavity walls can be used to lock the orthogonal orientation of the modes excited in the cavity.

The present invention generally relates to techniques for rf pulse compression and more particularly to high power pulse compressors using cavity resonators to store and release pulse power in the aid of pulse compression.
High Q cavity resonators are used in pulse compressors to store a significant part of the energy from an amplified pulse received from an rf pulse power source. During a "fill time," the pulse power incident on an aperture in the cavity resonator has part of this power reflected and the remaining part coupled to the cavity. Some of the power coupled to the cavity is dissipated in the cavity walls, while the balance builds energy in the cavity resonator. By abruptly reversing the phase of the rf power source, the energy stored in the resonator cavity is released and effectively combined with the power from the rf source to yield an increase in peak power output at a reduced pulse length.
The high Q cavity resonators such as used in high power pulse compressor systems have typically been cylindrical cavities for supporting modes of the TE01n family. These modes have electric fields that do not terminate on the cavity walls. Hence, electron emission and multipactor effects are significantly reduced as compared to many other modes.
An example of the use of high power rf pulse compressors is the SLED (Stanford Linear Energy Doubler) system used by the Stanford Linear Accelerator (SLAC) to increase the energy in the beam used for particle acceleration. SLED uses pulse compressors comprised of two cylindrical cavity resonators operating in a single mode, and a four port 3 db sidewall hybrid having ports conventionally denoted ports 1, 2, 3, 4. In this type of system, pulse power fed into port 1 of the sidewall hybrid is divided equally into ports 2 and 3 with a phase difference of 90° between Ports 2 and 3. The output from port 2 couples to one of the cylindrical cavity resonators, while the output from port 3 is coupled to the other of the cylindrical cavity resonators. The transmission line lengths used to feed the two resonator cavities of the SLED system are equivalent to maintain the 90° phase differential at and within the cavities.
In the SLED system, each cavity reflects essentially all of the incident power at the start of the filling pulse. The reflection travels back to the hybrid and combines to exit the hybrid at the hybrid's port number 4. As the cavity starts to fill, less power is reflected and more power is coupled. All this is a function of time, frequency, cavity Q, and coupling coefficient in a predictable manner. After an appropriate fill time interval, the phase of the rf power to hybrid port 1 is reversed. (This is usually accomplished by reversing the phase of the drive to the rf power source, such as a klystron amplifier.) Immediately after phase reversal, the following occurs at the cavities: (1) the incident power is completely reflected, and (2) power is emitted from the cavity's stored energy. The phase of the reflected power and the emitted power are equal at a given cavity, so that the voltages add. Consequently, the power traveling from a cavity to the hybrid increases as the square of this voltage. The hybrid serves to combine the reflected power and power released from energy stored in the cavities, and to deliver this power to port 4 of the hybrid.
In another type of pulse compression system a single resonator cavity is fed by a 3 port circulator instead of a 4 port hybrid. In this case, power from the rf source is fed into port 1 of the circulator and emerges out of port 2. Port 2 is connected to a transmission line that is, in turn, coupled to the cavity resonator to build energy in the single cavity during the pulse fill time. Upon reversal of polarity of the input pulse power at port 1 of the circulator, the stored energy released from the single cavity resonator is released to aid in the production of a compressed output pulse, which is conveyed out of port 3 of the circulator to a load.
The advantage of a single cavity/circulator system is that it eliminates the need for the two cavity resonators used in the SLED system. A disadvantage is that circulators are more complex and costly as compared to four port hybrids. Also, because all of the energy is stored in a single mode in one cavity, the peak electric field within the cavity of the circulator fed single cavity system is increased by the square root of 2 over the two cavity/hybrid pulse compressor. The power level in the feed line connected to port 2 of the circulator is also increased.
The present invention provides the benefits of both of the above described pulse compression systems into a single system. That is, the invention involves a single cavity resonator that is hybrid fed. Thus, the maximum electric fields in the cavity resonator and the feed arms to the resonator are equivalent to the two cavity/hybrid system. A hybrid can be used instead of the more costly circulator, and a single cavity resonator is required instead of two.

Dual mode single cavity pulse compressor


A surgical instrument is provided having a tubular body including a distal portion, a proximal portion and a mid portion. A cutting member having a cutting edge is longitudinally received within the tubular body for guided reciprocal movement therein between a cutting position wherein the cutting edge extends from the distal portion and a non-cutting position wherein the cutting edge is retracted within the tubular body. A urging mechanism is also provided within the mid portion of the tubular body for urging the cutting member to the cutting position. A vacuum source is coupled to the cutting member at a proximal end thereof and provides a vacuum directed to the distal portion to hold tissue to be cut. A method of cutting the tissue is also provided.

1. Field of the Invention
This invention relates to an instrument for cutting tissue and, more particularly, to an instrument for creating a hole or flap in the lens capsule of the eye.
2. Description of Related Art
Many surgical procedures require incision of membranes and the like for insertion of instruments. For example, when incising the lens capsule, straight cuts are typically made with cutting instruments having extremely sharp blades and instruments are thereafter inserted to carry out the desired surgical procedure. However, stress concentration occurs at edges of the straight cut when instruments are manipulated in the incision, which may result in tearing of the incision. To eliminate the problems of stress concentration, circular cuts have been proposed. However, the physical nature of tissue being cut often precludes a clean incision, since the tissue may collapse or distort when initial penetration is made with the cutting instrument. Thus, conventional instruments do not facilitate a clean cut since the tissue cannot be properly held during the cutting operation. Further, precise circular cuts cannot be made with conventional instruments due to their slow cutting speeds.
In other surgical procedures, clean cuts are also required to retrieve biopsy specimens or to remove a precise segment of tissue for transplants. For example, in keratoplasty utilizing corneal transplantation, a precise piece of the cornea must be removed.

Capsule suction punch instrument and method of use


An interconnection interface for transmitting digital data between a sending module and a receiving module connected to one another through point-to-point serial links, forming a global data link. Each of the modules are provided, firstly, with a multiplexing unit associated with each of the serial links disposed in the module""s physical layer, so as to distribute data transmitted through the global link at a speed determined by the sending module to a given number of parallel links, with each of these parallel links conveying a part of the transmitted data at a speed higher than the sending module data speed; and secondly, with a demultiplexing unit associated to the parallel links conveying received data parts, so as to synchronously and integrally reconstitute these received data parts at a speed accepted by the receiving module.

1. Field of the Invention
The present invention relates to the field of high-speed networks, and more particularly to interconnected networks constituted by high-speed serial links connecting nodes of data processing systems or data communication systems, hereinafter called modules.
Hereinafter, and in general, the connection of two modules that are remote from one another is called a linkage or link.
The invention is described below based on the protocol SDH, the abbreviation for Synchronous Digital Hierarchy, defined by the ITU, the abbreviation for xe2x80x9cInternational Telecommunication Union,xe2x80x9d in its G.708, G.709 and G.783 guidelines.
However, the invention is not limited to the utilization of this protocol, which is given as an example to provide a good understanding of the invention.
2. Description of Related Art
The increase in the demand for multimedia services, particularly the transmission of digitized images, and the specialized interconnections of local area networks comprising an increasing number of processors interconnected with one another, require higher and higher speeds under strict limitations in terms of cost, transmission time, space and the integrity of the transmitted information.
The high-speed serial links of the prior art, particularly the serial links of the SDH type that use a link constituted by two opposite one-way point-to-point links, are no longer able to meet the demand for speeds that can exceed several tens of GB/s, typically exceeding or equalling 50 GB/s. Such speeds are reached especially when a large number of processors are communicating with one another in a data processing machine or a network connecting several machines to one another.
The limitation due to the maximum allowable speed affects the latency of a data processing machine, which is an important parameter to consider in the efficiency of a multi-module machine, especially when the distance between the modules is large and/or when the number of processors communicating with one another is large.
One solution for solving this problem consists of parallelizing several point-to-point links.
One particular solution of this type is known from the document entitled xe2x80x9cHigh Performance Parallel Interface-Mechanical, Electrical and Signalling Protocol Specification (HPPI-PH),xe2x80x9d published in xe2x80x9cX3T11 Maintenance Copy of American National Standard X3.1833333331991.xe2x80x9d This document describes a parallel point-to-point interface for transmitting digital data at speeds of 800 or 1600 Mb/s between data processing machines, which data is conveyed through twisted pairs of copper wires over distances of more than 25 m.
However, this solution runs into the major problem of the deviation of the propagation times in the parallel links, also known as xe2x80x9cskew,xe2x80x9d which makes it necessary to solve the problem of resynchronizing the data conveyed through each line on reception.
This problem is even more difficult to solve when the operating frequency of the modules is high.
In fact, at frequencies higher than 200 MHz, for which the skews become greater than the bit period, the static deviations are substantial, and in complex configurations the sum of the contributions of the skews for a 10-meter link can reach 10 ns. For a 10-meter link, there is typically a maximum of 4 ns in the cables and two times 3 ns in the transceivers.
If the information contained in the messages to be transmitted through a given number of links is distributed at a rate of 1 bit per link, the deviations cause the information to arrive at the ends of the links at different instants. The problem is that for a frequency of 200 MHz, or 5 ns after the departure of the information, the bits arrive in the wrong order, and is no longer known which message the bits received at the end of the link belong to.
The object of the invention is specifically to eliminate these drawbacks.
Another object of the present invention is to offer a physical interface structure capable of supporting speeds of several GB/s, typically greater than or equal to 5 GB/s, through 16 channels, or 2.5 Gb/s per channel, in cables having a skew on the order of xc2x14 ns.
Hereinafter, the term xe2x80x9cchannelxe2x80x9d will be used to define the level of parallelization of a link and the term xe2x80x9ccablexe2x80x9d will be used to define the physical medium of the links.
Likewise, the unit GB/s means gigabytes per second and the unit Gb/s means gigabits per second: a byte corresponds to an octet, or 8 bits.
The skew of xc2x14 ns, which corresponds to a length of several meters, should be compared to a bit period, typically on the order of 0.4 ns, and a frame header, on the order of 50 ns.
The bit period therefore has a lower order of magnitude than the skew, while the duration of the header has a higher order of magnitude than the skew. It is known to increase the bit period by increasing the number of parallelized channels, but the number of physical connection points must remain compatible with the dimensions of a mass-produced card.
For this reason, the first subject of the invention is a process for interconnection between data processing or data communication modules by means of high-speed point-to-point serial links conveying multiplexed information, organized into frames and comprising a start-of-frame recognition pattern, of the type consisting of parallelizing several high-speed channels, making it possible to increase the flow of information exchanged between the modules.
The process according to the invention is characterized in that it consists, on transmission and on reception, of performing an analog synchronization of the basic clocks of each module to a reference clock generated by a module designated among the modules as a reference module, called the master module, the other modules being called slave modules, and of digitally synchronizing the start-of-frame of each slave module to the start-of frame sent by the master module.
According to one characteristic, for the analog synchronization on transmission, the process consists of:
extracting the basic clock signals of each slave module from the signals conveyed through each of the respective links connecting the master module to the slave modules;
frequency-locking and phase-locking each slave module to the data of one channel, chosen as the master channel, coming from the master module; and
from the basic clock signals, generating in each slave module a new clock signal with a given frequency higher than its own clock frequency, conveyed by the link connecting the slave module to the master module, and with a cycle imposed by the clock of the master module.
According to another characteristic, for the digital synchronization on transmission, it consists of:
detecting the start-of-frame conveyed through each link;
digitally aligning the start-of-frame of each channel with the start-of-frame pattern sent by the master module.
According to another characteristic, for the analog synchronization on reception, it consists of:
designating a master channel among all of the channels forming the link connecting each slave module to the master module;
from the data conveyed through the master channel, extracting the clock signal sent by the module connected to the link; and
generating a clock signal with a frequency higher than the frequency of the extracted clock signal, to be used as a sampling frequency for the respective data signals extracted from the other links.
According to another characteristic, for the digital synchronization on reception, it consists of digitally aligning, to the nearest bit, all of the starts-of-frame of the links with the starts-of frame of the master link, at a given frequency corresponding to the throughput of the data conveyed through each of the links.
According to another characteristic, there is an overlap of all the headers related to each link.
Another subject of the present invention is an interconnection interface for implementing the above process.
The interface is characterized in that it comprises, in each module:
multiplexing means associated with each serial link, disposed in the physical layer of the module, making it possible to distribute the data transmitted through the global link at a speed determined by the sending module to a given number of parallel links, each parallel link conveying part of the data at a speed higher than the speed of the data blocks sent by the sending module; and
means for demultiplexing the given number of parallel links respectively conveying the data parts received, in order to reconstitute the data that has passed through the interconnection interface, synchronously and with integrity, at a speed corresponding to the speed allowable by the receiving module.
According to another characteristic, the multiplexing/demultiplexing means comprise a sending block and a receiving block, the sending block comprising a plurality of clock generating blocks and the receiving block comprising a plurality of clock retrieving blocks, each generating block using the sending logic for a given link to which it is connected, the sending block synchronizing the plurality of generating blocks, and each retrieving block using receiving means for a given link, the receiving block defining the clock domain related to the reception of the given number of links connected to the same module.
According to another characteristic, each clock retrieving block comprises:
a logical circuit that senses the leading edges of the data signal conveyed through the link to which it is connected, making it possible to extract a pure and substantially fixed clock frequency from the data transmitted through the link; and
a phase-locked oscillator that receives the clock frequency output by the logical circuit.
According to another characteristic, the receiving blocks include a device for correcting the deviation of the propagation times in the parallel links, also called the skew.
According to another characteristic, the skew correcting device comprises:
means for generating a local receiving clock from the signal received from the master link;
means for phase-shifting the signals received from the slave links;
means for sampling the phase-shifted signals at a rate imposed by the local receiving clock;
means for phase-shifting the sampled signals in the signal received from the slave link, the logical contents of the phase-shifted signals corresponding to a bit shift defined by a given whole number of periods STM-N, where N corresponds to the level of interleaving; and
means defining a window for operating the phase-shifting means specific to each slave link, the phase-shifting means being active in the phase preceding the detection of the start bit and inactive during the transfer of the rest of the frame.
The digital synchronization of the frames is achieved through a digital alignment of the recognition patterns, hereinafter called xe2x80x9cstart bits,xe2x80x9d contained in the starts-of-frame provided according to the SDH data transport protocol.
The present invention uses the detection of each start-of-frame and the periodicity of these frames to perform a precise logical synchronization of the information transported by the frames.
One advantage of the present invention is that it specifically separates the logical transport layers from the physical layers for access to the media.

Interconnection process and interface using parallelized high-speed serial links


A method for altering the operation of a printer driver. A printer driver initially creates a database file. During operation of the printer driver, it accesses the database file and searches for the application that called the printer driver. If the application name is located under a heading in the database file, the printer driver modifies its operation in accordance with the heading.

1. Field of the Invention
This invention relates to printer drivers, more particularly to methods of modifying printer drivers based upon applications.
2. Background of the Invention
The increased availability of high-quality printers and software applications for printing applications has caused an explosion in desktop printing and publishing. Users have more options than every before, from printers to software applications. Print systems have become more robust in order to handle more and more printing applications.
Print systems usually include the printer and software printer drivers. The printer drivers actually control the printer in whatever manner is required by the application that calls them. With the increase in the number of applications that can call the drivers, however, little customization of the print drivers is possible for the users. Yet, some customization would be desirable.
For example, some applications only allow one page of print to be printed per print job. Others might use fonts that the printer needs for true rendering of the image. Most drivers do not handle these types of special situations, they just continue to process the print jobs as they process all print jobs. However, if the print driver could adapt to the unique requirements of applications, it would eliminate print time overhead and make the printing system more efficient.
One aspect of the invention is a method for altering a printer driver. The printer driver is created such that it will search for a database file, and if it does not locate the file, it will create one. The database file can be altered by the users of the print system that has that driver, even if it has pre-loaded information. When the printer driver is called by an application, the printer driver references the database file. If the application name is listed under any of the headings, the printer driver alters its operation in accordance with the information in the headings.
Another aspect of the invention is a printer driver with the necessary structure to search for the database file and create it if it does not locate one.

Method of modifying printer driver output

Sharp Laboratories of America, Incorporated


Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state. Selected ones of the subcircuits in each of the plurality of subsets share a same dynamic voltage state, where memory storage for the same dynamic voltage state is shared by the subcircuits in each of the selected ones of the plurality of subsets. Once generated, the hierarchical representation may be used during simulation of the circuit to reduce the number of computations required.

1. Field of the Invention
The present invention relates to computer-aided design tools. More particularly, the present invention relates to the simulation of circuits using a hierarchical data structure and applying isomorphism matching to skip computations on duplicate subcircuit behavior.
2. Description of the Related Art
Device-level circuit simulation is an important step in microelectronic circuit design. Through such simulation, the functionality of a circuit may be validated and performance of the circuit may be predicted before the circuit is physically fabricated. The application of existing simulation tools such as SPICE, however, is limited to the simulation of small subcircuit blocks, typically less than 100,000 transistors, due to their memory capacity and performance limitations.
The capacity of existing simulators is primarily determined by the size of the circuit being simulated. Although circuits are hierarchically structured, the circuit hierarchy is typically flattened to the device level during simulation. As a result, the device connectivity and device parameters are stored during simulation for each device. This is particularly important since there is a fixed memory overhead measured in bytes per device. It follows that memory usage during circuit simulation is approximately proportional to the circuit size measured in number of devices in the circuit. In existing simulators, the memory usage per device is in the order of hundreds of bytes. This means that approximately 1 G bytes (one billion bytes) of memory are required in order to simulate a circuit containing 10 million devices, assuming 100 bytes of memory are required per device. The excessive memory usage therefore makes it impractical to use existing circuit simulators to perform full-chip circuit simulation on today""s VLSI circuits. For example, a 256 M DRAM chip contains more than 256 million transistors and no existing circuit simulator can perform the full-chip simulation on the 256 M DRAM circuit. This memory limitation therefore forces microelectronic circuit designers to partition the full-chip design into blocks of smaller subcircuits which can be simulated by existing circuit simulators. Thus, the circuit is partitioned into subcircuits and the separate simulation results for the partitioned subcircuits are relied upon to predict the full-chip circuit behavior. However, the circuit partitioning is a tedious and error-prone task and thus reduces the designer""s productivity. Moreover, the simulated subcircuit behavior obtained by local subcircuit simulation may be different from that obtained if the subcircuit is simulated together with all other subcircuits. Accordingly, it would be desirable if large microelectronic circuits could be simulated without such partitioning.
As described above, the size of the circuit that may be simulated using currently available circuit simulators is limited. However, even those circuits that can be simulated using currently available circuit simulators require a substantial amount of simulation time as well as memory. This becomes evident from the fact that the behavior of a circuit, as well as the behavior of each subcircuit, is formulated into a set of mathematical equations which are solved during simulation. Typically, the circuit hierarchy is flattened to the device level and numerical analysis is applied to the mathematical equations that are formulated from the flattened data. Since the mathematical equations are formulated at the device level, the computations required increase with the number of devices in the circuit. However, as described above, a large circuit may contain millions of devices and therefore the electrical behavior of the circuit may be expressed by millions of equations. As a result, the circuit can be time-consuming to simulate. Accordingly, the cost of testing such a circuit is non-trivial.
Although simulators having reduced simulation time have been developed, such improvements have generally been achieved through relaxing the accuracy of the simulation results. In addition, some simulators such as PowerMill available from Synopsys Inc., located in Mountain View, Calif. have achieved an increase in circuit simulation speed by taking advantage of circuit latency found in digital CMOS circuits. Thus, these simulators skip computations for idle subcircuits. However, the applicability of such simulators is limited to digital CMOS circuits. In addition, the assumption of circuit latency is getting invalidated by analog behavior arising in today""s deep submicron technology. For example, due to noise from crosstalk capacitances, each device could be physically active all the time even though it is functionally idle most of the time. Therefore, although SPICE and other faster circuit simulators continue to play a critical role in microelectronic circuit simulation, the demand for more efficient circuit simulation is increasing.
To meet the challenge of simulating very large circuits containing millions of transistors, a simulation technology known as macromodeling has been implemented. Through the use of macromodeling, the electrical behavior of a subcircuit is characterized and the subcircuit is replaced by its behavioral model. Since this approach skips the details of a subcircuit and replaces it with an abstract model, the macromodeling approach consumes a minimal amount of memory. In addition, the simulation speed is much faster since it operates on a simpler behavioral description instead of massive numerical data. Theoretically, this approach can therefore be used to simulate a circuit of unlimited size. However, such approximate characterization of subcircuit behavior cannot accurately simulate the behavior of the entire circuit. Moreover, this approach requires a nontrivial effort to build the model since the modeling process is circuit dependent. Model characterization is tedious and time-consuming since it needs to include different combinations of input patterns and output load conditions. In addition, the subcircuit must be recharacterized whenever the subcircuit topology and circuit parameters change. Due to the difficulty in building the behavioral model, this macro-modeling approach is limited to applications where the subcircuit size is small or the subcircuit behavior is less sensitive to the surrounding environment. It would therefore be desirable if circuit simulation could be performed without such characterization.
In view of the above, it would be desirable if the simulation time and memory consumed during circuit simulation could be reduced. Moreover, a new technology is needed to allow a circuit simulator to perform full-chip simulation on circuits containing hundreds of million transistors, whether such circuits exist today or will emerge in the next decade.
The present invention implements methods and apparatus for validating the functionality and performance of microelectronic circuits prior to fabrication. More particularly, the present invention may be advantageously used to accurately simulate the electrical behavior of very large microelectronic circuits. This is accomplished, in part, through exploiting the hierarchical architecture in microelectronic circuit design.
Currently available circuit simulators have not used the hierarchical architecture of microelectronic circuits to benefit the simulation process. Rather, even when a hierarchical data structure is produced from a netlist representing the circuit being simulated, the hierarchical data structure is typically flattened during the simulation process. In other words, the memory required during simulation is proportional to the number of devices in the circuit being simulated. Similarly, the number of computations performed during the simulation process increases with the number of devices in the circuit. In order to reduce the simulation time and memory required during simulation, the circuit is often partitioned. However, such partitioning can introduce errors into the simulation process and therefore reduces the accuracy of the resulting simulation.
In order to utilize the hierarchical architecture to simulate the electrical behavior of a circuit, the present invention uses a hierarchical data structure throughout the simulation process. More particularly, a netlist describing the circuit may be parsed to permit the information in the netlist to be stored in a hierarchical data structure. However, it is particularly important that the hierarchical data structure be constructed in a manner that facilitates the simulation process. As will be described below, through the use of such a hierarchical data structure, memory requirements as well as the number of computations performed during simulation may be dramatically reduced.
According to the present invention, the hierarchical data structure is designed to maximize the benefits that may be obtained from the hierarchical architecture of microelectronic circuits. In many circuits, identical subcircuits are often used multiple times within the same circuit. By way of example, an inverter may be used repeatedly within a circuit. As yet another example, in memory arrays, numerous memory cells may be used within a single memory circuit. As a result, these identical subcircuits may share a common circuit structure or subcircuit definition. By way of example, a subcircuit definition may describe the topology of the subcircuit as well as the device parameters of the subcircuit (e.g., resistance, capacitance, and transistor size). Alternatively, the device parameters may be specified in corresponding element definitions provided in leaf nodes that are linked to the subcircuit definition. According to one embodiment, the topology of the subcircuit is represented by a block matrix. Since multiple child subcircuits may be associated with a single subcircuit definition, it is desirable to combine such subcircuits or xe2x80x9cinstancesxe2x80x9d in memory. Thus, multiple subcircuits may share a single static circuit storage area in which the subcircuit definition is stored. In this manner, memory consumed during the simulation process may be minimized.
While multiple circuits may share such static circuit storage, the circuits may have different node voltages at a specified time and therefore different xe2x80x9cdynamic voltage statesxe2x80x9d. Thus, a set of voltage states may be associated with each subcircuit definition. However, where node voltages are determined to be identical for more than one subcircuit during simulation, the subcircuits may also share a common dynamic voltage state. As a result, the voltage state associated with multiple nodes (e.g., child subcircuits) in the hierarchical data structure may be linked to a single voltage state. In this manner, memory use during simulation may be further reduced. It is important to note that through the use of the above-described hierarchical data structure, the memory storage required by the present invention is proportional to the number of different subcircuit types rather than the number of devices. In typical microelectronic circuits, the number of different subcircuit types is much less than the number of devices. By way of example, a standard 256 M DRAM circuit may contain 284 million devices and only 500 subcircuit types. Accordingly, the capacity limit faced by existing simulators is eliminated and the size of the circuit that may be simulated is therefore dramatically increased.
Where two subcircuits share a dynamic voltage state as well as a subcircuit definition, isomorphism may be applied to skip computations for these duplicate circuit blocks throughout the simulation process. According to one embodiment, the voltage state is updated for each subcircuit identified in the hierarchical data structure. As described above, each subcircuit is linked to a corresponding subcircuit definition and associated set of voltage states. As a result, the voltage state associated with a subcircuit need not be updated if the state has previously been updated for another subcircuit linked to the same subcircuit definition and voltage state. In other words, at a specific point in time during the simulation process, each one of the voltage states associated with a particular subcircuit definition need be updated only once, regardless of the number of subcircuits linked to the subcircuit definition and set of voltage states.
Once the voltage states have been updated, the device model is calculated for primitive elements in the circuit using the updated voltage states. As described above, where subcircuits share the same subcircuit definition and voltage state, the device model may be calculated a single time for the multiple subcircuits. Thus, the time required to calculate device models as well as total simulation time is dramatically reduced. Moreover, since the number of device model calculations during the simulation process is reduced, the memory required to store the reduced number of device model calculation results is similarly minimized.
Upon completion of the device model calculations, the behavior of the subcircuit may be simulated using the device model values and information associated with the subcircuit definition. More particularly, as described above, the behavior of each subcircuit may be represented by a set of equations in the form of a matrix. The matrix may then be loaded and solved using the device model calculations and the subcircuit definitions that are linked to the hierarchical data structure. According to one embodiment, a hierarchical block matrix is used to identify child subcircuits associated with each node in the hierarchical data structure. Once loaded with the appropriate values, the block matrices may be hierarchically solved. More particularly, the present invention may recursively simulate the behavior of each child subcircuit instance. Since most subcircuit instances not only share the same subcircuit definition but also exhibit the same behavior either throughout the simulation period or in sub-intervals of the simulation period, duplicate computations may be eliminated. By way of example, most sense amplifiers and core memory cells in memory circuits are observed to exhibit the same behavior during simulation. Thus, as indicated above, through the use of a hierarchical data structure, a circuit may be hierarchically simulated to skip the duplicate processing typically performed while simulating subcircuits with identical behavior. In this manner, the hierarchical nature of microelectronic circuits may be advantageously used to simulate the electrical behavior of a circuit while minimizing the simulation time and memory required. Accordingly, the present invention is superior to simulation tools that flatten the circuit hierarchy, particularly for circuits with a regular array structure such as memory circuits.
According to another aspect of the invention, the hierarchical netlist may be restructured to facilitate the simulation process. Where coupling between nodes in the circuit being simulated is equal to zero, the simulation process may be greatly simplified. This may become evident from examining a standard matrix. Where entries in the matrix are zero, the number of computations required is reduced. Thus, where coupling between the nodes in the circuit is represented by one or more entries in the matrix, it becomes evident that the number of computations may be greatly reduced where the coupling is zero. Through the use of equivalent impedance partitioning, it may be determined whether the coupling between nodes in the circuit may be approximated to zero and therefore effectively ignored during the simulation process. Thus, through examination of circuit parameters such as the equivalent resistance and frequency of operation of the circuit, it may be determined whether the coupling parameters may be approximated to zero.
Once it is determined whether the coupling parameters can be approximated to zero through the use of a method such as equivalent impedance partitioning, the hierarchical data structure may be modified through the use of a process such as hierarchical injection. Moreover, such restructuring may be limited to circuits that are large in size since restructuring may be unnecessary where the circuit and corresponding matrices are relatively easy to solve. According to one embodiment, such restructuring may be accomplished through the application of an algorithm such as the Min-Cut algorithm where a minimum number of nodes are selected and moved outside a subcircuit in order to partition the subcircuit. In this manner, subcircuits having an identical topology are created. Thus, it is likely that these newly created subcircuits may share both a subcircuit definition and a voltage state. Accordingly, memory requirements and simulation time may be minimized through preprocessing performed prior to transient simulation.
According to yet another aspect of the invention, simulation of the circuit is achieved without flattening the hierarchical data structure. In existing simulation technology, the circuit hierarchy is flattened to the device level and numerical analysis is applied to the mathematical equations formulated from the flattened data. As a result, memory requirements and computations are proportional to the number of devices in the circuit. However, as described above, the hierarchical data structure may be processed hierarchically such as through a recursive process in order to eliminate such unnecessary calculations and memory requirements.
The present invention provides methods and apparatus for simulating the electrical behavior of a circuit without flattening the circuit hierarchy. More particularly, simulation is performed through the use of a hierarchical data structure to advantageously exploit the hierarchical nature of electronic circuits. In this manner, the memory consumed as well as the computations performed during the simulation process are minimized. Thus, the present invention enables microelectronic circuit designers to perform full-chip circuit simulation in a reduced simulation time. Accordingly, through the use of the present invention, circuits with more than 100 million transistors can be simulated, whereas existing circuit simulators can typically simulate a circuit having up to one million transistors.

Transistor level circuit simulator using hierarchical data


For the evacuation of a low-vacuum chamber (4) and of a high-vacuum chamber (5), two pump trains (6, 7) are provided, each consisting of a vacuum pump unit (8, 9) and a forepump unit (10, 11). The forepump unit (11) of the pump train (7) of the high-vacuum chamber (5) can draw selectively from the vacuum pump unit (9) of the high-vacuum chamber (5) or from a high-vacuum pump unit (12) connected likewise to the high-vacuum chamber (5). The vacuum pump unit (9) can aspirate either from the highvacuum chamber (5) or from the low-vacuum chamber (4) and discharge to the forepump unit (10) of pump train (6) or to the forepump unit (11) of pump train (7).

The invention relates to a method for evacuating a low-vacuum chamber and a high-vacuum chamber of a high-vacuum apparatus, in which first the low-vacuum chamber and the high-vacuum chamber are evacuated together by means of pump trains each containing a vacuum pump unit and a vacuum forepump unit. The pump train of the high-vacuum chamber is used as a forepump for a high-vacuum pump unit of the high-vacuum chamber when the vacuum falls below a preset level. Furthermore, the invention relates to a high-vacuum apparatus for the practice of such a method.
In vacuum technology it is often necessary to evacuate two or more chambers in a vacuum apparatus to different working pressures. In vacuum depositing apparatus for coating substrates in band form, a pressure of less than 5.times.10.sup.-4 mbar must prevail, for example, in the chamber in which the vapor depositing process takes place, while in the winding chamber in which the substrate is wound and unwound a pressure of 5.times.10.sup.-2 mbar suffices.
To produce the necessary vacuums in such an apparatus, it has up to now been the practice to associate one pump train with the low-vacuum chamber configured as the winding chamber and another with the one serving as the coating chamber. When the changeover pressure is reached, the pump train of the high-vacuum chamber is cut off from the latter by means of a valve and used as the forepump for a high-vacuum pump unit then to be connected to the high-vacuum chamber. To assure a rapid draw-down and reliable operation of the high-vacuum pump unit, it is necessary to select the lowest possible changeover pressure. Especially in the case of dirty production apparatus this requires the pump train of the high-vacuum chamber to have a very great suction capacity in the pressure range between 1000 to 1 mbar. As soon as the pump train, however, is operating only as a forepump for the high-vacuum unit, and since then a preliminary vacuum pressure of 1.times.10.sup.-1 to 3.times.10.sup.-1 mbar is sufficient, all that is needed is only about one-tenth of the previously needed suction capacity. Therefore the pump train of the high-vacuum chamber is oversized for a far greater proportion of the time involved in the pumping cycle.

Method for the evacuation of a low-vacuum chamber and of a HGH-vacuum chamber, as well as a high-vacuum apparatus for the practice thereof


A method for concurrent reading of mixed radix DFT/IDFT data, a method for concurrent calculation of mixed radix DFT/IDFT method, an apparatus for concurrent reading of mixed radix DFT/IDFT data, and an apparatus for concurrent calculation of mixed radix DFT/IDFT. The method for concurrent reading includes: configuring dual circulation parameters according to the number of points corresponding to the number of series to be computed and the number of points corresponding to the number of series accomplished; then, determining the value size between the maximum number of concurrently read data and the product of the number of points corresponding to the number of series accomplished; and based on the result of determination, calculating the dual circulation parameters corresponding thereto according to the result of determination, and concurrently reading data based on the calculated dual circulation parameters.

In a digital processing system, especially for a sequence with finite length, a DFT (Discrete Fourier Transform) is a vitally essential mathematic transform. In nature, it is a discrete sampling of finite points of the Fourier transform of a sequence with finite length. It enables the digital signal processing to be accomplished by employing a digital computation method in the frequency domain, enhancing the flexibility of digital signal processing. The DFT has been broadly applied in the field of digital communication, image processing, power spectrum estimation, etc. Wherein, a computation of DFT with a point number of powers of 2 may be accomplished by employing an algorithm of radix 2 FFT. In the case of other point numbers, namely, the computation could not be accomplished by employing a FFT algorithm, it is referred to as a general number DFT.
Presently, a general number DFT generally employs a mixed radix algorithm on the theoretical basis of Cooley-Tukey algorithm. A radix 2 FFT algorithm is derived by modifying on this basis. Its basic idea is: converting a DFT of larger point number to a plurality of DFTs of smaller point number, wherein each round of computation is referred to as one level, each level of computation is executed sequentially to accomplish the entire process of DFT. Typically, the smaller point number is set to a prime number, i.e. 3, 5, . . . , while in computation, it is proceeded in a nested way sequentially in accordance with radix 3, radix 5, . . . . The radix N operation of each level is executed a number of times, but the data which is specific to varies.X(k)=A+WN/3k×B+WN/32k×B+WN/32k×C X(k+3/N)=A+WNN/3×WN/3k×B+WN2N/3×WN/32k×C X(k+2N/3)=A+WN2N/3×WN/3k×B+WN4N/3×WN/32k×C   (1)
Eq (1) is an expression of a radix 3 algorithm, wherein WN/3k, WN/32k are input twiddle factors, which are relevant to k; and WNN/3, WN2N/3, WN4N/3 are output twiddle factors, which are irrelevant to k;
Since the process of a general number DFT is not an integer multiple of 2, when it is processed by a general processor, the data of an integer group may not be read in or wrote out at once, so that the degree of concurrency is reduced. Moreover, the process of a general DFT processing is first proceeded with a multiplication and an addition computation between the data and the input twiddle factors, and then is proceeded with a multiplication and an addition computation between the data and the output twiddle factors, resulting in a comparably larger relevance between data. Moreover, the process of a general number DFT performs the multiplication computation and the addition computation alternatively, which brings in the relevance of calculation again. This leads to a longer waiting cycle of the arithmetic unit caused by the relevance among data, a lower pipeline usage, and so that the processing speed of the entire computation of DFT is reduced.
To this end, the present application is presented hereby.

Method and apparatus for concurrent reading and calculation of mixed radix DFT/IDFT

Institute of Automation, Chinese Academy of Sciences


A cover fabric for a V belt having increased flex and wear-life, and a method of making the cover fabric. A fabric is bias cut into a continuous strip of fabric. The individual fibers in the continuous strip are impregnated with an elastomeric polymeric material effective to increase the flex and wear-life of the fabric when used as a cover fabric for V belts. This impregnation is accomplished by immersing the strip in a fluid mix having a viscosity of about 2000 cps or less, the mix including a fluid carrier, an elastomeric polymer (e.g. a polychloroprene compound) and a dark pigment. A coating of an elastomeric polymer (e.g. another polychloroprene compound) is applied to the strip, the strip is stretched in its width direction to increase the angular relation of the threads of the fabric relative to its longitudinal axis, and the thus coated strip is dried. The continuous strip is ultimately slit longitudinally of itself into a plurality of tapes, and the tapes are used to cover a V belt.

This invention relates to improvements in the production of industrial fabrics intended for use in covering power transmission belts, commonly referred to as V belts, and the like. Conventional belt cover fabrics, such as in U.S. Pat. Nos. 3,784,427 and 4,062,989 (the disclosures of which are incorporated by reference herein) have been generally suitable for performing their intended function for normal V belt life.
In such power transmission belt cover fabric constructions, the end of normal wear life is typically indicated when the cover fabric becomes abraded enough to show the undyed white filaments or fibers making up the yarns of the cover fabric. While this has been a safe practice, V belt manufacturers are presently applying dye to the tubular or square woven cover fabrics before coating to improve the cosmetic effect of the raw cut fabric edge along the belt. It is felt by some producers that transmission belt life is extended by dyeing the white fiber components of the cover fabric to a darker shade. This "cosmetic" treatment has the effect of extending the usage of the transmission belt--sometimes dangerously. This is because such cosmetic effects do not extend the wear life of the V belt, but tend to unduly prolong replacement because of the longer time needed to detect abraded fibers.
According to the present invention there is provided an improved method for making cover fabrics for V belts and the like. The cover fabric so produced exhibits greatly improved wear-life compared to prior art cover fabrics. The present invention also overcomes the possibly dangerous cosmetic effect associated with present cover fabrics, without adversely affecting the improved wear life properties of cover fabrics according to the present invention.
This increase in cover fabric wear-life is accomplished by impregnating the fiber bundle of the yarns making up the fabrics employed (typically bias cut woven tubular fabric, although knitted or non-woven fabrics may also be suitable), so as to coat or encapsulate the individual fibers thereof, for example by passing a continuous strip of bias cut woven fabric into a fluid mixture of an elastomeric polymeric material. The polymeric material is preferably dissolved or emulsified in a fluid mix having a relatively low viscosity in order to accomplish complete impregnation of the fiber bundle. The desired viscosity is about 2000 cps or less, and is preferably 1500 cps.+-.250 cps. Where pressurized or evacuated systems are available, or where exceptionally long paths in dip tanks are provided, complete impregnation can be achieved utilizing fluid mixes having viscosities somewhat higher than 2000 cps, and may be as high as 40,000 cps.
According to the present invention, the impregnating fluid mix also preferably includes a dark pigment, such as conductive black. One purpose of the pigment is to improve sales appeal by coloring the fibers to eliminate the objectionable whiteness of the raw cut edges of the fabric. However, this pigmenting effect is to be distinguished from dyeing. If dyeing is practiced, it is difficult to determine when abrasion of the fabric fibers has occurred, necessitating belt replacement.
According to the present invention, the impregnating and encapsulating polymeric materials holds the pigment on the fabric and fiber components until the pigment is abraded off with the coating. When such abrasion occurs, white fibers begin to show, signalling the time for belt replacement. Greater flex life and greater wear life is nevertheless achieved, because of the polymeric encapsulation of the individual fibers in the yarn bundle of the cover fabric, which protects such fibers from premature abrasion. Nevertheless, when there is serious abrasion the white fibers begin to appear, signalling that the belt is worn and should be replaced.
The fiber bundle impregnation according to the present invention is practiced by passing the continuous strip of bias cut fabric into a dip tank, and removing excess fluid mix by utilizing a pair of textile pad rolls. After impregnation the cover fabric is treated by following the conventional steps of U.S. Pat. Nos. 3,784,427 and 4,062,989. That is, an elastomeric coating is applied to the fabric strip, the strip is stretched in its width direction to increase the angular relation of the yarns or threads of the fabric relative to its longitudinal axis, and the thus coated strip is dried. There is usually no drying between impregnation and coating, although in some circumstances that may be feasible. After coating and drying, the continuous strip is longitudinally slit into a plurality of tapes, and the tapes are used for covering a V belt or the like.
It is therefore the primary object of the present invention to provide an improved cover fabric for V belts or the like, and a method of production thereof. This and other objects of the invention will become clear from the detailed description of the invention, and from the appended claims.

Production of cover fabrics for V belts which function as wear indicators due to different layer characteristics


A contact sensing head, for example for a measuring device, comprises a sensor having a free end which is vibrated at low amplitude by a motor at the resonant frequency of the sensor. A transducer senses the vibrations and feeds a signal to an electronic detection system. When the sensor contacts an object, the frequency and amplitude of its oscillation changes. This is picked up by the electronic detection system, which signals that contact has been made.

The present invention relates to a contact sensing head and is particularly, but not exclusively, related to a sensing head for a measuring device operable to detect the position of the points in space with regard to which mechanical contact takes place between a sensor of the sensing head and an object to be measured.
Such measuring devices may be operated by securing the object on a mobile workpiece-carrying table and by moving the points to be measured into the region of the sensing head, which is capable of locating them with a desired degree of precision relative to a reference origin. When the positions of the sensing head itself and of the table have been determined by the measuring system of the machine relative to a common reference origin and according to selected coordinate axes, it is an easy matter to deduce therefrom, by calculation, the positions of the aforementioned points measured relative to the said origin.
There are measuring heads which supply an "all or nothing" electrical signal as soon as mechanical contact is established, at the point to be measured, between the sensor and the object. In this case, in order to ascertain the position of the point of contact, the procedure is to utilise the said electrical signal for "recording in flight" or "fixing" the coordinates indicated by the measuring system of the machine at the instant of contact, and to add to the said coordinates the constants due to the geometrical form of the sensor.
In known embodiments of such measuring heads, generation of the electrical signal takes place by employing the following processes:
The mechanical contact establishes an electrical current between the sensor and the object;
Electrical contact or contacts establishing the signal are actuated by the sensor; they are frequently mounted on guides having a zero degree of freedom and maintained by springs (see German Patent Specification No. 25 51 361 and British patent specification No. 1,447,613);
The sensor actuates an element the position of which is detected by magnetic, capacitive or photoelectrical means producing an analog voltage approximately proportional to the displacement of the said element (German Patent Specification No. 26 11 781);
The useful signal of the "all or nothing" type is produced by a voltage comparator during passage to zero of the said analog voltage;
A strain gauge system of the resistance wire or semiconductor type is fixed on the sensor itself or on a support thereof, constituted for example by flexible blades; it converts the deformation of the sensor or of its support on contact with the object to a proportional analog voltage (French Patent Specification No. 73 23 193, publication No. 2 235 351); as in the preceding case, the passage to zero of the said voltage is located by a voltage comparator which produces an all or nothing signal; these systems generally have the following defects:
1. Non-constant quality of electrical contact
2. Vibration of the electrical contact
3. Lack of rigidity, fragility
4. Precision of measurement which is a function of the length of the sensor.
British patent specification No. 932069 relates to a sensor constituted by a piezoelectrical crystal vibrating at its resonant frequency and maintained at this frequency by an oscillating circuit. Application of the said sensor is limited to that of signalling the advance of the cutting tool of a lathe. The said sensor reveals the instant of passage of the tool, coming always from the same direction. Such an embodiment cannot be envisaged for universal application as in a measuring head, in which case the direction in which measurement is effected is optional but precision of measurement must remain non-variable. Furthermore, in the British patent specification No. 932069, the sensor itself is constituted by the piezoelectric crystal and this construction makes it extremely fragile and vulnerable to untimely shocks.