A member with a first body having a through hole along a longitudinal axis thereof along which a beverage is fed from a percolation chamber. A first cup-shaped body is axially aligned under the first body, and a ball, which stops the flow of the beverage under the bias of a spring, is between the hole and the inside of the first cup-shaped body until the beverage reaches a given pressure. A second cup-shaped body houses the lower part of the first body and the first cup-shaped body and internally defines a chamber. A first through window is defined in the first cup-shaped body under the stopping zone of the flow in the hole; and a second through window is defined in the second cup-shaped body, through which contact between the beverage and air is made and is suited to feed the beverage from the chamber outwards.

As known, hot beverage producing machines comprise a water tank, a pump which channels the water taken from the tank into a heat exchanger, which takes the water to a predetermined temperature, and a percolation chamber, in which a quantity of infusion product (in powder form, in a pod, in a capsule) is housed. The water from the heat exchanger reaches the percolation chamber and is mixed with the infusion product herein. The beverage thus formed is then fed from the percolation chamber outside the machine.
For given beverages, such as coffee, for example, users prefer a creamy beverage, and in this case some manufacturers of such machines have adopted systems for mixing the beverage exiting from the percolation chamber with pressurized air. However, such systems are complex because they are made directly in the percolation chamber. It is worth noting that the further channels required to make such systems must be periodically subjected to in-depth cleaning to remove scaling which has formed and which could obstruct the channels themselves. Now, it is apparent that either descaling liquids must be used or the percolation chamber must be removed from the machine to then clean it for such cleaning operations. In addition, in the first case, water must be subsequently made to flow at a given pressure in the channels of the aforesaid systems so as to make any residues of the liquids used to remove the scaling flow out. In the second case, either the machine is taken to a maintenance center with consequent costs or there is the risk of breaking some parts of the machine if the users remove the percolation chamber themselves.

Member to increase the thickness and the creaminess of a beverage in a beverage producing machine


A switched power converter includes a switchable power stage for generating an output voltage according to a switching signal and an input voltage via a switching element. The switching signal is generated by a multi-mode controller. The multi-mode controller controls a digital control path for generating a pulse width modulation switching signal and a constant-on-time control path for generating a constant-on-time switching signal. The switching signal for controlling the switching element is generated in the digital control path when the multi-mode controller is run in a high load mode. The switching signal is generated in the constant-on-time control path when the multi-mode controller is run in a light load mode.

Switched DC-DC converters comprise a switchable power stage, wherein an output voltage is generated according to a switching signal and an input voltage. The switching signal is generated in a digital control circuit that adjusts the output voltage to a reference voltage. The switched power stage comprises a dual switch consisting of a high-side field effect transistor (FET) and a low-side FET, an inductance and a capacitor. During a charge phase, the high-side FET is turned on and the low-side FET is turned off by the switching signal to charge the capacitor. During a discharge phase the high-side FET is turned off and the low-side FET is turned on to match the average inductor current to the load current. The switching signal is generated as digital pulse width modulation signal with a duty cycle determined by a control law. The control law may be implemented by a PID compensator.
A digital control circuit for DC-DC converters is very well suited for high performance applications that require a good load transient behavior. Nonetheless, if the powered application runs in light load the digital control circuit has the disadvantage of consuming too much current and therefore the efficiency of the DCDC converter is negatively influenced. This results in poor light load efficiency. Because many applications run most of their time in light load conditions, this negatively affects the overall energy consumption. Therefore it is highly desirable to have better efficiency under light load conditions.


A video projection display system (10) of this invention employs histograms to detect an active video region (2) of a video frame (1). A microcontroller (16) loads registers (27) in an ASIC (26) to accumulate histograms of low pixel values occurring within columns (70-74) of video data. The microcontroller scans the histograms to, identify the left-most column in which a set (80) of black pixel values is clustered, which column marks the left edge of the active video region. The right edge of the active video region is detected in a similar manner. The video signal may also include overshoot and noise. When an ADC (24) digitizes the video signal, the overshoot and noise causes many bright pixels to be converted to below their maximum digital values. Therefore, the microcontroller programs the ASIC such that a histogram (90) of the highest pixel values is collected from within the active video region. The microcontroller then scans the histogram to locate a rapid decrease in the number of pixels having values greater than some large value. Pixels having even greater values fall within the overshoot and noise range. The microcontroller remaps the upper range of data to the maximum digital values, thereby enhancing image brightness at the high end of the pixel value range.

Not Applicable
Not Applicable
This invention relates to analog-to-digital conversion of video image frames, and more particularly to employing image luminance histograms to detect the presence of and correct luminance values of a video signal.
Presentations using multimedia projection display systems have become popular for conducting sales demonstrations, business meetings, and classroom instruction. In a common mode of operation, multimedia projection display systems receive analog video signals from a personal computer (xe2x80x9cPCxe2x80x9d). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control digitally-driven display devices, such as a transmissive or reflective liquid crystal displays or digital micro-mirror devices (hereafter xe2x80x9clight valvesxe2x80x9d), to form the display images for projection onto a display screen. A wide variety of such display systems are available from In Focus Systems, Inc., the assignee of this application.
A necessary feature of multimedia display systems is compatibility with the various analog video signal modes and levels generated by PCs and other video sources. The modes typically range from 640xc3x97480 to 1600xc3x971200 resolutions provided at image refresh rates ranging from 60 Hz to 100 Hz. The resolution expresses the number of controllable horizontal and vertical pixel elements that can be turned on and off. Given the variety of display modes, multimedia display systems include an interface that attempts to convert the various analog video signal levels and modes to digital video signals suitable for controlling the light valves.
Analog video signals typically include image information (signal levels) for each of the red, green and blue colors, and timing signals, which may include a horizontal synchronizing pulse (xe2x80x9cHSYNCxe2x80x9d) and a vertical synchronizing pulse (xe2x80x9cVSYNCxe2x80x9d), or a composite image and sync signal. The color image information is stored in the PC memory as digital color data and is converted to the analog video signals by digital-to-analog converters. When composite sync is employed, a conventional sync separator is used to extract the HSYNC and VSYNC timing pulses.
The timing signals synchronize the scanning of the analog video signals across a raster-scanned display device. The HSYNC pulse controls the horizontal scanning timing, and the VSYNC pulse controls the vertical scanning or video frame refresh timing.
FIG. 1 shows that each video frame 1 typically includes a central active video region 2 surrounded by an inactive or blanked margin 3. The resolution of a raster-scanned display refers to the number of displayable image information points (xe2x80x9cpixelsxe2x80x9d) in active video region 2.
Because the light valves employed by multimedia display systems require digital video signals, either the light valve or the display system normally includes an analog-to-digital converter (xe2x80x9cADCxe2x80x9d) for converting the PC-generated analog video signals into a digital format suitable for driving the light valve. The ADC is typically digitizes samples of the analog video signal under control of a voltage-controlled oscillator (xe2x80x9cVCOxe2x80x9d), which is in turn controlled by a phase-locked loop (xe2x80x9cPLLxe2x80x9d) that locks to a predetermined multiple xe2x80x9cnxe2x80x9d of the HSYNC pulses.
FIG. 2 shows an exemplary analog signal waveform 4, with plateau regions (pixel data components) 5 that correspond to the color levels of individual pixels in the image display. Consecutive pixel data components 5 are connected by signal transition regions 6.
FIG. 2 further shows a typical pixel clock waveform 7, which is generated by the VCO. The number n of pixel clock pulses 8 per HSYNC pulse is typically set to match the resolution mode established by the PC or other analog video source. To determine the resolution mode, certain characteristics of the analog video signal, such as the number of HSYNC pulses per VSYNC pulse, may be used to refer to a mode lookup table. The resulting number n is set to equal the number of pixel data components in each horizontal line of the analog video signal, including those in active video region 2 and blanked margins 3 (FIG. 1). For example, for a 640xc3x97480 screen resolution, n may be set to about 800 to include pixels in blanked regions 3 on either side of the 640 pixel-wide active video region 2. Thus, pixel clock pulses 8 would cause the ADC to sample analog signal waveform 4 about 800 times along each horizontal scan line of video frame 1. Unfortunately, n is usually an approximation because it is often difficult to determine the exact proportion of active video region 2 to blanked margin regions 3 (FIG. 1).
FIG. 2 also shows the desired timing relationship between analog signal waveform 4 and pixel clock waveform 7. Ideally, the number n of pixel clock pulses 8 is set to establish a one-to-one relationship between pixel clock pulses 8 and pixel data components 5 of analog signal waveform 4. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video signal frequency. Under this relationship, each pixel data component 5 is sampled by a single pixel clock pulse 8, such that the ADC properly digitizes the instantaneous voltage value of each pixel data component 5. Because pixel clock pulses 8 have xe2x80x9cjitterxe2x80x9d zones 9 at their leading and trailing edges, pixel clock pulses 8 should be centered on pixel data components 5, so that the ADC sampling is not randomly shifted by jitter zones 9 into signal transition regions 6 of analog signal waveform 4.
The stream of digitized signal values from the ADC form the digital video data signal is conveyed to the light valve to activate or deactivate its pixels in a pattern corresponding to the image defined by analog signal waveform 4. Unfortunately, such ADC conversion is often imperfect because of sample timing errors caused by pixel clock pulses 8. Such sample timing errors are typically caused by pixel clock frequency deviations (xe2x80x9ctrackingxe2x80x9d errors) and xe2x80x9cphasexe2x80x9d errors, both of which may degrade the quality of images generated by the light valve or valves.
FIG. 3 shows a typical tracking error resulting from improperly setting the number n of pixel clocks along the entirety of pixel clock waveform 7xe2x80x2. As described above, the number n of pixel clock pulses 8xe2x80x2 should be equal to the number of pixel data components 5 of each horizontal line of analog signal waveform 4. An improper setting of n results in pixel data components 5 being sampled at inconsistent points. For example, n is set too large in pixel clock waveform 7xe2x80x2 (i.e. the frequency is too high). The resultant crowding of the pixel clock pulses 8xe2x80x2 causes an additive leftward drift of pixel clock pulses 8xe2x80x2 relative to pixel data components 5. Such drift causes sampling in signal transition regions 6 as shown by positional bracket A in which leading edges 9xe2x80x2 of the third through sixth of pixel clock pulses 8xe2x80x2 sample in transition regions 6 of analog signal waveform 4. Accordingly, the transition region data will be erroneous and the image information from adjacent non-sampled pixel data components 5 will be missing from the digitized video signal. If n is erroneously set large enough, pixel clock pulses 8xe2x80x2 may be so crowded that individual analog pixel data components 5 may be double-sampled. On the other hand, if n is set too small (i.e. the frequency is too low), the resulting dispersion of pixel clock pulses 8xe2x80x2 results in a rightward drift in which sampling may also occur in signal transition regions 6.
To minimize tracking and phase errors, some prior workers have provided some multimedia projection systems with manual controls that permit an operator to adjust the number n and the phase of pixel clocks pulses 8. The controls are adjusted until the projected image appears satisfactory to the eye of the operator. While manual controls are usually effective in achieving an acceptable image quality, adjusting such manual controls is time-consuming and inhibits the user-friendliness of the multimedia projection system.
Accordingly, other prior workers have developed automated pixel clock adjusting techniques. For example, U.S. Pat. No. 5,657,089 for VIDEO SIGNAL PROCESSING DEVICE FOR SAMPLING TV SIGNALS TO PRODUCE DIGITAL DATA WITH INTERVAL CONTROL describes an active video interval detector that generates data indicative of a difference between the detected active video interval and a required reference video interval. A video signal supply interval controller receives the difference data and provides frequency-dividing ratio control data to a programmable frequency divider that is part of the PLL controlling the pixel clock frequency. Over a number of video frames, the difference data is iterated toward zero to achieve accurate pixel clock tracking.
Unfortunately, some PCs generate video signals with an indefinite xe2x80x9cblackxe2x80x9d video level, which makes the transitions between blanked margin regions 3 and a black active video region 2 difficult to determine. Detecting this transition is particularly troublesome when running DOS, graphics, or other programs that generate images having black backgrounds. The problem is made worse by computer display driver systems that cut costs by eliminating the xe2x80x9cblacker than blackxe2x80x9d blanking level offset that is typically found in a standardized video signal format.
Another problem occurs when the analog video signal undergoes a large signal level transition, such as when active video region 2 has a white background color. Because of the fast rise time of such transitions, the analog video signal may include, and/or have overshoot and noise induced into it somewhere along its video processing chain. Moreover, the amount of overshoot on the initial transition in each line may be greater than the amounts of overshoot on subsequent transitions in the same line. The combination of overshoot differences and noise causes video signal value inaccuracies across each scan line so affected. This is particularly troublesome in multimedia projection display systems because projected image brightness is an important performance factor. The ADC and associated signal processing typically assigns a xe2x80x9cfull scalexe2x80x9d signal value to the largest amount of overshoot and noise affected portions of the analog video signal, which causes the real full scale signal values to be less than their overshoot and noise affected values. This problem diminishes the full brightness potential of the projected image.
What is needed, therefore, is an improved technique for detecting the active video region and for correcting erroneous video signal values, thereby increasing projected image clarity and brightness.
An object of this invention is, therefore, to provide an apparatus and a method for reliably detecting the active video region of an analog video signal.
Another object of this invention is to provide an apparatus and a method for correcting erroneous video signal values.
A further object of this invention is to provide a video image projection system having increased image clarity and brightness.
A histogram is a list of occurrences of a predetermined parameter that falls within a predetermined range of parameter values over a specified collection period. In a preferred embodiment of this invention, a microcontroller and an Application Specific Integrated Circuit (xe2x80x9cASICxe2x80x9d) coact to provide at least one, and preferably several, continuously updating histograms for examining and counting real time video data that fall within programmable value ranges and rectangular regions of a video frame. The ASIC includes multiple histogram registers that count the numbers of video data values generated by an ADC that fall within the programmable ranges and regions during each frame of video data.
Video data include difficult to detect transitions between the inactive margins and the active video region of a frame. The transition may include a small step increase in pixel values between the inactive margins and the left and right edges of the active video region, and represents the difference between the blanking pulse and black video levels. Conventional active video region detectors often miss the blanking-to-black transition.
In a first embodiment of this invention, an active video region detector employs histograms to reliably detect the blanking-to-black transitions in a video frame. The microcontroller loads registers in the ASIC to accumulate histograms of low pixel values occurring within rectangular regions corresponding to columns of video data. Histograms collected for columns including the inactive margins reveal that pixel values are clustered in first sets of very low values representing blanking and/or noise levels. Histograms collected for columns including the transition in the active video region reveal that pixel values are further clustered in second sets of low values representing black pixel values. The microcontroller scans the histogram registers to identify the left-most column in which the second set of pixel values is clustered, which column marks the left edge of the active video region. The right edge of the active video region is detected in a similar manner by collecting histograms of the right most columns. However, to identify the right edge, the microcontroller scans the histogram registers to identify the right-most column in which the black pixel values is located. The microcontroller or ASIC then generates an active video signal corresponding to the interval between detection of the left and right edges of the active video region.
As described in the background of this invention, the analog video signal may include, and/or have overshoot and noise induced into it somewhere along its video processing chain. Moreover, the amount of overshoot on the initial transition in each line may be greater than the amounts of overshoot on subsequent transitions in the same line. The combination of overshoot differences and noise causes video signal value inaccuracies across each scan line so affected. Accordingly, when the ADC digitizes the analog video signal, the highest value (brightest) pixels for each color are not always converted to a maximum digital value as intended in the original video signal.
Therefore, in a second embodiment of this invention, histograms are employed to detect the extent of the overshoot and noise condition and cause remapping of the upper range of pixel values to the maximum digital value. The microcontroller programs control registers in the ASIC such that a histogram of the highest pixel values is collected over a rectangular region corresponding to a majority of the active video region. The microcontroller then scans the histogram to locate pixel values having significantly fewer occurrences than most remaining pixel values. For example, the histogram may reveal a rapid decrease in the number of pixels having values greater than some large value. Accordingly, pixels having even greater values fall within the overshoot and noise range. The microcontroller employs this information to remap the upper range of data to the maximum digital values, thereby enhancing image brightness at the high end of the pixel value range.

Image luminance detection and correction employing histograms


A touch detection chip, a touch panel and a touch detecting method are disclosed. The touch detecting method includes: detecting a signal amount of each of a plurality of touch units; determining candidate touch units according to the signal amount of each of the plurality of touch units; and determining a target touch unit from the candidate touch units according to signal amounts of adjacent touch units of each of the candidate touch units.

A touch panel of a touch display device can adopt a single-layer self-capacitance structure. The single-layer self-capacitance touch panel has only one layer of ITO (Indium Tin Oxides), and each ITO touch unit is connected with a touch detection chip through a touch electrode line, so each ITO touch unit can be detected independently, and the function of single-touch or multi-touch can be implemented.

Touch detection chip, touch panel and touch detecting method

BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.


An image catheter is introduced into the venous system and is maneuvered through the venous system to points adjacent to sections of arteries to be imaged. The arterial segments are then imaged from those adjacent points in the venous system. Ideally an ultrasound imaging catheter with a diameter of 7-10 French (2.3 mm-3.3. mm) operating at a frequency between 15 and 20 MHz is used.

This invention relates to methods and apparatuses for imaging arterial structures and more particularly for ultrasonically imaging epicardial arterial structures.
A conventional way of obtaining ultrasonic images indicating the condition of blood vessels, particularly arteries in the vicinity of the heart, involves insertion of an ultrasound imaging catheter directly into the artery of interest. This type of catheter, referred to as an intraarterial catheter, typically is inserted into the femoral artery and is then guided, such as with the aid of fluoroscopy, to the artery to be imaged. When in place, the catheter is activated to generate a scanning ultrasound signal which is reflected from the inner wall of the surrounding artery. The reflection signal is received by a suitable transducer and an image indicative of the cross-section of the artery is developed with the aid of electronic circuitry.
There are a number of drawbacks to this method. Since the catheter must pass through the artery, it can only image arterial sections whose interior diameters are sufficient to enable the catheter to pass through. Often arterial diseases produce blockages which can narrow an artery to the extent that the area with the blockage is too narrow for the catheter to enter. Thus the section of an artery of most interest to a physician frequently cannot be imaged with an intraarterial catheter.
Another disadvantage associated with the use of intraarterial catheters is that they can cause serious complications in patients. The introduction of a catheter into the relatively high-pressure arterial system presents a serious risk of arterial injuries such as arterial perforation, arterial thrombosis, myocardial ischemia and infarction. Due to these dangers, physicians are often reluctant to utilize intraarterial ultrasound imaging. This further impairs the usefulness of the technique.
It is the object of this invention to provide methods and apparatuses for developing images of arteries which do not suffer from the aforementioned disadvantages of the prior art.

Coronary intravascular ultrasound imaging method and apparatus


An optical sensor effective for (i) exciting an analyte-sensitive fluorophore, exposed to an unknown concentration of the analyte for which the fluorophore is sensitive, with radiant energy from an excitation source, (ii) measuring the extent to which luminescence of the excited fluorophore is quenched by presence of the analyte, (iii) ascertaining the concentration of analyte to which the fluorophore is exposed from such measurement, and (iv) reporting the ascertained concentration. The sensor is preferably an epi-fluroescence confocal optical detector, and preferably performs step (ii) by employing a summing amplifier.

Optical sensors are a widely employed method of measuring analyte concentration, typically oxygen, within a package or container. Briefly, analyte concentration within a package or container can be measured by placing an analyte sensitive fluorophore within the package or container, allowing the fluorophore to equilibrate within the package or container, exciting the fluorophore with radiant energy, and measuring the intensity and/or rate of decay in the intensity of luminescence emitted by the excited fluorophore. Such optical sensors are available from a number of suppliers, including Presens Precision Sensing, GmbH of Regensburg, Germany.
Optical sensors typically employ fiber optics to both guide the excitation light generated by the sensor from the sensor to the analyte sensitive fluorophore, and also guide emitted light from the fluorophore to a photo multiplier in the optical sensor for detection and measurement.
While effective for accurately measuring analyte concentration, such optical sensors are very expensive.
Accordingly, a substantial need exists for a low cost optical sensor capable of accurately and reliably measuring analyte concentration within a package or container.

Epi-fluoresence confocal optical analyte sensor


A compensation polarizing plate which is superior in polarization characteristic to a polarizing filter layer of a composite layer sample is arranged on the polarization filter layer side of the composite layer sample whose polarizing filter layer has an insufficient degree of polarization, and polarization transmission axes of the polarizing filter layer and the compensation polarizing plate are kept in parallel with each other to compensate the polarization characteristics of the polarization filter layer. Measurement for obtaining the retardation value and the optical principal axis direction of the sample is carried out in the state of the compensated sample.

1.Field of the Invention
The present invention relates to a method of and an apparatus for measuring retardation of a composite layer sample such as a composite sheet prepared by stacking a polarizing film and a phase difference film (retardation film) with each other to be applied to a liquid crystal display panel, for example.
2.Description of the Background Art
As liquid display elements are increasingly employed, requirements for large areas of liquid crystal display panels and enlargement of ranges of visual directions are also increased. Thus, awaited is development of a technique which can readily measure characteristics of a film type polarizing filter (polarizing film) and a phase difference film in steps of producing such films.
In general, the display panel of a liquid crystal display unit has a polarizing filter which is provided on one surface of a liquid crystal cell sealing a liquid crystal material therein as an optical element and a phase difference film, a polarizing filter and a protective film which are successively stacked on another surface (observed side). The phase difference film, which is adapted to compensate polarization characteristics of the liquid crystal cell, consists of a birefringent material. It is necessary to examine the states of a composite sheet, also called an elliptic polarizing plate, which is obtained by stacking and bonding the polarizing filter and the phase difference film with each other, such as the polarization transmission axis direction of the polarizing filter, the optical principal axis direction of the phase difference film and the retardation value thereof. We refer to these characteristic (i.e., retardation value etc.) as "optical characteristic" hereafter.
In the display panel of the liquid crystal display unit, the optical characteristic as viewed from a direction other than that perpendicular to the surface, i.e., the optical characteristic obtained with changing the incident angle of measuring beam, is also an important characteristic. In order to evaluate the angle of visibility, it is necessary to measure the retardation value in the case of changing the angle of incidence of a measuring beam in the state of the composite sheet. At present, however, white light is introduced into the composite sheet to make evaluation by the spectrum of the transmitted light.

Method of and apparatus for measuring retardation of composite layer


Disclosed is a LED lighting apparatus comprising: a LED module including a substrate 10 having a front surface 12 and a rear surface 13, and a plurality of LEDs 11 mounted on the front surface 12 of the substrate 10 and driven by direct input of AC voltage; a heat sink 50 for dissipating heat from the LEDs 11 on the substrate 10; a plurality of capacitors 20 to eliminate flickering of the LEDs 11; a flame barrier plate 30 being made of flame-retardant material and covering the front surface 12 of the substrate 10 so as to insulate the LED module from fire flame; and a plurality of capacitor housings 31 made of flame-retardant material, each of the capacitor housings 31 including an opening 32 formed at a front side and accommodating each capacitor 20 so as to insulate the capacitor 20 therein from fire flame; a flame barrier film 40 made of flame-retardant material and covering the opening 32 of the capacitor housing 31; and lens 60 detachably coupled to the rim of the heat sink by hook 62.

Recently, there are rapidly increasing demands for a LED lighting apparatus of a high power and high efficiency. According to the demands, a direct input AC powered LED lighting continues to be developed and released.
Generally, in a direct input AC powered LED lighting, a flickering of LEDs occurs due to characteristics of AC drive circuit. To reduce or eliminate the flickering of LEDs, capacitors were connected to the LED drive circuit. U.S. Pat. No. 9,532,412 discloses an example of such a direct input AC powered LED lighting system.
According to disclosure of the US patent, capacitors as anti-flickers protrude from a front surface of the substrate of LED module as the capacitors are mounted on the substrate. The protrusion of capacitors from the front surface obstructs physical contact between the rear surface of the substrate and a heat-sink, and thus it results in diminishing the efficiency of heat dissipation at the heat sink. In addition, the protrusion of capacitors from the front surface of the substrate blocks light of LEDs and thus forms a dead zone or a shading zone behind the capacitors.
Recently, it requires that a lighting device on a ceiling should comply with 'UL 5VA flammability Standard'. However, even though there were many trials to upgrade material of components, they fail to provide with substantially effective results.

LED lighting apparatus having flame barriers


An antenna, a read/write unit, an radio frequency identification (RFID) arrangement and a method, wherein the antenna is configured to connect to an external antenna connection of the read/write unit via an antenna line, wherein the antenna includes a data memory having type information and/or having property information, the content of the data memory being readable by the read/write unit, and includes a measuring device for determining a value of the field strength or power of a radio frequency signal fed into the antenna by the read/write unit, and includes a device for informing the read/write unit about the value being reached or exceeded.

1. Field of the Invention
The invention relates to an antenna for a read/write unit for Radio Frequency Identification (RFID) arrangements, a read/write unit for RFID arrangements, a system comprising a read/write unit for RFID arrangements and an external antenna, and a method for matching the read/write unit for RFID arrangements to an external antenna.
2. Description of the Related Art
Read/write units for Radio Frequency Identification (RFID) arrangements, such as in the Ultra High Frequency (UHF) band, are frequently operated with external antennas, particularly in the case of arrangements in which an internal antenna alone is not sufficient for covering a required radio area. For example, it is possible to equip a loading door in logistics with four antennas for the purpose of better radio coverage, all four antennas being connected to a single read/write unit ("Reader"), where alternate operation of the various antennas is implemented in the read/write unit via a changeover matrix, for example.
At least when the RFID arrangement, i.e., the read/write unit and the antennas, is installed for the first time, a user needs to carefully parameterize the antenna lines and antennas used in the read/write unit when configuring the read/write unit. For example, it is necessary to reduce the maximum transmission power as the antenna gain rises, in order to comply with legal requirements. On the other hand, in the case of antenna lines or in the case of connections between the radio-frequency circuit of the read/write unit and the radiation element of the antenna, losses may arise, depending on the damping and depending on the adjustment (e.g., reflection factor), which can or are permitted to be compensated for by a higher transmission power for the read/write unit. Only exact configuration of the read/write unit in respect of the type or properties of the antenna used and the properties of the antenna line (cable) used results in the desired or permitted radiation power and, on the other hand, a misconfiguration, such as cable damping which is set too high, may possibly result in the permissible radiation power being exceeded.
To configure a read/write unit with respect to "antenna configuration", it is necessary to manually input, for each "antenna port" used, i.e., for each antenna connection, what line parameters (e.g., cable damping) and what antenna (type or antenna gain) are used. Firstly, this is complicated for a user, because he may need to look up what values need to be set in manuals, tables or the like, and secondly legal requirements may be infringed or else malfunctions may occur as a result of incorrect inputs. In addition, there is the danger of the configuration not being adjusted when the operating frequency is changed, when an antenna is replaced or when an antenna line is replaced, as a result of which faults or impermissible operating states can likewise occur.

Antenna for a read/write unit for radio frequency identification (RFID) arrangements, and read/write unit for operation with an external antenna


An ultrasonic signal drive/sense circuitry is provided, which circuitry is adaptable to a variety of automated or manual fastener tightening operations. This circuitry operates for measuring tension in a fastener as a function of change in time of flight of an ultrasonic wave. A microcontroller directs the operation of circuit components to generate high amplitude, high repetition rate, drive pulses with these amplitude and repetition rate factors being electronically adjustable to compensate for fastening tool and fastener acoustical properties and tightening rates. Software driven timing circuitry calculates, calibrates and adjusts pulse echo detection window width and center location and also optimum echo detection threshold. This timing circuitry is implemented by digital techniques to measure pulse time of flight and incorporates analog interpolation of data between digital counts. Sampling rates of the echo pulses are adjusted to tool speed. An auto-calibration technique is implemented prior to each fastener tightening operation to overcome circuit errors and set detection window position and to optimize pulse voltage and echo threshold detection levels. Time of flight data is selectably calculable from the initial ultrasonic pulse to the primary echo or successive reflections thereof.

This invention relates to electronic circuitry for generating ultrasonic signals and for sensing reflected ultrasonic echo signals; and more specifically to such electronic circuitry for use as ultrasonic tension control in manual or automated fastener tightening.
Ultrasonic signal processing has been used in the past to detect flaws in metal objects, such as fasteners, and to measure the elongation of a fastener during or after tightening. The procedure adopted has been to transmit electronically generated ultrasonic pulses down the length of a fastener and then to measure the time from pulse to echo, i.e. the reflected ultrasonic signal. This is the "time of flight" of the echo. The time of flight of the echo measures the distance to a fault, an inclusion or a fracture in a faulty fastener, and the length of a good fastener. However, the length of the fastener changes as tension is applied to the fastener. Therefore, a change in time of flight occurs as a function of axial tension.
Meisterling, U.S. Pat. No. 4,760,740, shows an extensometer unit coupled to an ultrasonic transducer which in turn is mounted to the head of a fastener. The Meisterling extensometer unit contains signal generating, signal receiving and signal processing circuitry of a general nature. An example of an extensometer circuit is shown by McFaul et al., U.S. Pat. No. 3,759,090.
Jones, U.S. Pat. No. 4,413,518, shows a bolt elongation measurement apparatus and a method of measuring bolts. The circuitry utilizes a microprocessor-based digital system including a binary counter which counts pulses generated by a high frequency oscillator during the time interval between the entry into the bolt of a first pulse and exit from the bolt of a second pulse derived from the reflection return of ultrasonic energy from the opposite end of the bolt. The count is applied to a computer for calculation of bolt length or of bolt stretch due to mechanical stress. The calculation also incorporates data input thereinto and corresponding to material velocity, stress correction factor, measurement temperature, and thermal correction factor. A digital filtering algorithm ensures an accurate and stable measurement. The receiver of the apparatus overcomes the problem of spurious ultrasonic reflection characteristics of threaded bolts by means of a dual characteristic echo sensing circuit to deal with stress-induced pulse distortion and a gain contour circuit to deal with spurious echo pulses that are characteristic of threaded bolts.
Couchman, U.S. Pat. No. 4,295,377, shows ultrasonic signal generation and detection circuitry which includes logic and timing circuits for generating an echo signal detection "window" This circuitry and detection technique of Couchman is also shown in his U.S. Pat. No. 4,294,122. The detection window establishes a time period when any signal received is taken as the desired echo pulse The time lapse between detection windows is adjustable and a function of the repetition rate of the primary ultrasonic pulses which Couchman provides at 100 to 2000 pulses per second.
Moore, U.S. Pat. No. 4,014,208, shows an ultrasonic device for measuring dimensional changes in a structural member. The device includes circuitry to double pulse a transducer to transmit an acoustic pulse into the member at one end for reflection from its other end with a period between paired pulses selected to cause the second echo received of the first pulse to coincide with the first echo of the second pulse. A voltage controlled oscillator is employed with a digital counter to time the period between paired pulses, the interval between successive paired pulses, and the time of a predetermined number of pulse pairs. The latter timing is used to alternatively shift the frequency of the voltage controlled oscillator to cause the first echo of the second pulse to be offset in phase from the coincidence position it might have at the central frequency. Phase detection and integration of the echo pulse coincidence during alternately high and low frequency offsets produces a phase-sensitive feedback signal to the voltage controlled oscillator to drive its central frequency toward precise coincidence.
Kibblewhite, U.S. Pat. No. 4,846,001, shows a fastener with an ultrasonic transducer affixed thereto. Electronic source pulses are applied to the transducer and electrical echoes produced by reflected ultrasonic waves are sensed. Kibblewhite measures a change in mechanical stress in the fastener by measuring a change in bolt stretch as a function of change in time of flight of echo measurement. Three time of flight measurement schemes are discussed. These are (1) a direct timing technique, (2) an indirect timing technique, and (3) a double pulsing technique.
A direct timing technique involves the measurement of the time interval between a source pulse (drive pulse) and the received echo. An indirect timing technique involves timing from the first echo to the second echo of a particular source pulse. In a double pulsing technique, two source pulses are transmitted, one after another. The time interval between these two pulses is adjusted so that the second echo from the first of the two source pulses coincides with the first echo from the second of the two source pulses.
Kibblewhite also discusses various echo detection techniques which can reduce the delay time of waiting for echoes of the previous pulse to die down. These detection techniques include (a) a fundamental frequency detection technique, (b) an acoustic impedance detection technique, (c) a harmonic resonance frequency detection technique and (d) a phase detection technique.
While the above-cited devices and methods can provide reliable information about a fastener, they have limitations in use. These techniques rely on averaging techniques to achieve their accuracy Therefore, they are capable of either high accuracy or high measurement rate and are generally used for taking measurements before and after tightening.
What is desired is an intelligent drive/sense ultrasonic signal circuit for measuring time of flight of pulse-echo time with greater accuracy.
What is secondly desired is ultrasonic signal drive/sense circuitry which achieves both high accuracy and high measurement rate and hence is useful for the control of ultrasonic measured tension during tightening.
What is further desired is ultrasonic signal drive/sense circuitry which does not require an extended delay time between transmitted pulses.
What is also desired is such drive/sense circuitry which uses a window for detecting an echo pulse and which can automatically select an optimum echo detection threshold for detecting an echo pulse.
What is further desired is such drive/sense circuitry which can automatically adjust the time position window for echo detection.
What is additionally desired is such drive/sense circuitry which automatically adjusts pulse drive voltage to compensate for variations in ultrasonic transducer electrical and acoustic efficiency and in fastener geometry.
What is even further desired is such drive/sense circuitry which can operate in an interleaved pulsing mode where pulse time is chosen so that echoes from the previous pulses fall outside the time acceptance window of the current measurement.
What is additionally desired is such drive/sense circuitry which can be adjusted to measure time of flight from a pulse to its echo, or from a pulse to its successive echo (reflections) or from its echo to a successive echo of that echo.
What is further additionally desired is such drive/sense circuitry which can operate with pulse repetition rates up to 10 KHz.

Ultrasonic drive/sense circuitry for automated fastener tightening


An irrigation system includes a valve that controls the flow of water through a sprinkler head, and a flow sensor that measures the water flow rate through the sprinkler head. In some embodiments, the valve is adjusted until the flow sensor measures a water flow rate that matches a first predetermined water flow rate. This is a first position for the valve. The valve opening is adjusted again by a set amount or until the flow sensor measures a water flow rate that matches a second predetermined water flow rate. This is a second position for the valve. The first and second predetermined water flow rates each correspond to a throw distance the water stream discharged from the sprinkler head will travel. This relationship between the water flow rate and distance is based on empirical data for the sprinkler. A second equation relating the valve opening to water flow rate, for a given pressure, is then used to estimate the water effective pressure. In some embodiments, the first and second valve positions and the first and second water flow rates are used to estimate the effective pressure using the second equation.

Irrigation sprinklers are known for watering circular patterns or arc segments of a circular pattern. Typical irrigation sprinklers discharge a single rotary water stream that is rotated in a circle around a vertical rotational axis. This water stream is thrown by a sprinkler nozzle mounted in the peripheral sidewall of the nozzle head at an upward angle relative to the horizontal to direct the water a radial distance from the nozzle.
Irrigation systems generally comprise multiple sprinklers within multiple watering zones. Each sprinkler is recessed within the ground and is fed water through underground pipes. An irrigation controller activates a zone by opening a valve that controls the flow of water through the pipes of the zone. The irrigation controller activates the zones sequentially for a predetermined period of time based on zone program instructions.
Irrigation sprinklers currently have several drawbacks. The most significant is that they spray water in circles that are overlapped between sprinklers in order to conform to complex landscape shapes. This causes excess water to be deposited in the areas where these sprinklers overlap. In many systems 50% excess water is used.
Another drawback to conventional irrigation sprinklers is that they use only a few nozzles or nozzle openings. One drawback is that some nozzles spray a fine mist close to the sprinkler which results in water evaporation due to the small droplet size. Another drawback is that some of the nozzles must water a large annular ring around the sprinkler which results in watering that is not uniform across the annular ring (i.e., in a radial direction from the nozzle). As a result, these conventional sprinklers waste water and are inflexible to landscape variations.
Irrigation systems have been disclosed that comprise, for example, a computer server with one or more wireless networks, one or more computerized sprinklers with a digitally controlled valve connected by wire to the server, one or more controllers with Wi-Fi plus another wireless network and one or more flow sensors connected by wire to the controller. Exemplary irrigation systems are disclosed in International Patent Application Serial No. PCT/US2011/044337, filed Jul. 18, 2011, and U.S. patent application Ser. No. 13/744,588, filed Jan. 18, 2013. The above referenced patent applications are incorporated herein by reference in their entirety. In these irrigation systems, each sprinkler provides a uniform incremental amount of precipitation to the soil for each revolution and can also adjust the incremental amount for a given arc portion of a revolution. In one embodiment the server and controller are combined and in another embodiment they are separate thereby creating more flexibility.
The systems must be properly calibrated to provide the desired watering pattern including the throw distance the watering stream travels from the sprinkler head over various arc portions of a revolution. Furthermore, it has been determined that a consistent pressure and flow are desirable to maintain efficiency where efficiency is defined by the system using the desired amount of water. Too much pressure causes too much flow resulting in over-watering and a throw distance that is too long, and too little pressure causes too little flow resulting in under-watering and a throw distance that is too short.
An installation contractor may use a pressure gauge to measure static pressure, but that does not account for working pressure loss under flow conditions in pipes and fittings in the field. The contractor can also turn on the sprinkler and measure the distance of the streams which are reflective of the flow conditions under working pressure, but this has proven to be complicated and slows down the installation. There is a need for automatically finding the effective pressure for a particular irrigation sprinkler and setting the sprinkler distance at a particular installation site.


A data processing apparatus for a virtual memory system including a logical address register, a real address register, a paged address translation table and an address translation buffer in which a map of a fraction of the paged address translation table is stored columnwise. Upon checking address translatability of a logical address into a real address, a bit of a translation control word contained in the column of the address translation buffer relevant to that logical address indicates whether or not a succeeding logical address is susceptible to the address translation. Necessity to pretest the address translatability of every logical address is obviated. System overhead is considerably reduced.

The present invention relates to a data processing apparatus for a virtual memory system which is capable of examining at a high speed whether the addresses of operands of instructions to be executed are susceptible to address translation.
In a computer system in which a virtual memory system is employed, data stored in a main memory device of the computer system is designated by logical addresses which are provided separately from the addresses (real addresses) which serve to indicate physical locations of the data. In this connection, the correspondences between the logical addresses and the real addresses are determined with the aid of an address translation table stored in the main memory. The address translation table in turn is supervised by an operating system.
When a given instruction is to be executed in the computer system outlined above, it is examined prior to the execution of the instruction to determine whether or not the logical address of the given instruction or relevant operand is susceptible of address translation, i.e., whether the logical address in concern is validly resident in the address translation table, whereby the instruction is allowed to be executed when the result of the examination has proven affirmative. This check or examination is referred to as a pretest.
Referring to FIG. 1 which shows in a functional block diagram a typical address translation scheme, reference numeral 1 denotes a logical address register in which a logical address is loaded, numeral 2 denotes a real address register in which a real address resulting from the address translation is loaded, numeral 3 denotes an address translation table stored in a main memory device, and reference numeral 4 denotes an address translation buffer or TLB in which a portion or fragment of the address translation table is copied. As is known, the address translation is usually carried out on the basis of a space paged as a unit size, which space is commonly referred to as a page. Upon address translation, the significant or upper-order bits representing the page address of the logical address register 1 are translated to the page address of the real address register 2 through the address translation buffer 4 directly or with the aid of the address translation table 3, if demanded. On the other hand, the lower-order bits or less significant bits indicating the page displacement of the logical address register 1 are directly used as the page displacement of the real address register 2. The main memory device is accessed with the aid of the address loaded in the real address register 2.
The pretest memtioned hereinbefore is effected in the address translation scheme such as illustrated in FIG. 1.
Now, assuming that operands of variable length are stored in a main memory device and that an instruction is issued for processing operands each having the maximum length which does not exceed the size of a single page, a procedure for executing the pretest of these operands will be elucidated below by referring to FIG. 2.
In FIG. 2, there is illustrated the paged state in which a first operand and a second operand are stored in the main memory device. As can be seen from the figure, the first operand labelled "1 op" is stored extending consecutively from page 1 to next page 2, while the second operand labelled "2 op" is stored over page 3 and page 4 in continuity. The consecutive storage or entry of an operand over two adjacent pages in this manner is referred to as the inter-page consecution of an operand. In this illustrated case, a check of the first operand "1 op" must be made for the two pages 1 and 2, while the check of the second operand "2 op" has to be made over the two pages 3 and 4. Accordingly, the pretest as to whether the address translation is possible (i.e. address translatability) or not must be carried out as many as four times.

Data processing apparatus for virtual memory system