Provided is a system and a method for propagating cells, the system comprising a multi well plate and a plate sealing means for sealing at least one well of a multiwell plate, the plate sealing means comprising at least one solid bulge or at least one bulge comprising a solid base, said at least one bulge consisting of a resilient elastomer to securely seal at least one well of the multiwell plate. Also disclosed is the use of such a system for propagating cells and the corresponding method.

For analyzing biological mechanisms and for testing toxicity of drugs or chemical compounds, the use of cells and microtissues becomes increasingly admired. Usually, mammalian cells are cultivated in form of a two dimensional monolayer of cells adhering to a surface of or within the vessel used of cultivating said cell. However, the natural in situ environment of a cell in a living mammalian organism has a three-dimensional architecture. Thus, cultivating mammalian cells in a three-dimensional architecture leading to the formation of spheroids or microtissues provides test systems which more closely resemble the morphological and functional characteristics of a natural environment than a monolayer of cells.
Generating spheroids or microtissues is cumbersome, resource-demanding and fiddly. For this reason, spheroids and microtissues are usually generated in facilities possessing the know-how of propagating 3D cell cultures. For use, the spheroids or microtissues are shipped from where they are generated to the site of their use, for example, in drug screening assays. Typically, cells in culture are cooled down to about 4° C. or are even frozen for being shipped, regardless of whether the cells are present in a two-dimensional or in a three-dimensional architecture. The cooling or freezing of the cells for and during their shipment reduces their metabolism and increases their survival rate. However, at their site of use, the cells have to be thawed and/or warmed up to the temperature at which the subsequent assay is performed. For example, mammalian cells being propagated at 37° C. will be frozen, shipped in liquid nitrogen or dry ice, and warmed up to 37° C. again in such a procedure.
Regardless of how gentle the cooling/freezing and thawing/warming is performed, the viability of the cells within the spheroid/microtissue is affected as the accuracy and/or reliability of the subsequent assay is. Therefore, there is a need for procedures and means which enable propagation and shipping of cells, in particular in form of spheroids or microtissues, without impairing the cell's viability.
Moreover, it is desired to keep the extent of manipulation of spheroids and microtissues during propagation prior to an assay to be performed as well as during the assay as small as possible. Any transfer of spheroids and microtissues from one culture vessel to another culture vessel might affect their integrity and/or functionality. In addition, manipulating cell cultures always renders the cell cultures prone to contamination with unicellular microorganisms such as bacteria or yeasts when the lid of the culture vessel is opened, for example for changing culture media.
Therefore, there is a need for means for culturing cells, in particular in form of microtissues or spheroids, which prevent contamination to the utmost extent.
Mammalian cells may be cultivated in standard SBS/ANSI format multiwell plates which are extensively used in molecular biology laboratories. Multiwell plates are typically rectangular flat plates comprising an array of wells. The precise dimensions (length×width×height) of a multiwall plate of the ANSI (American National Standard Institute) as recommended by the SBS (Society for Biomolecular Screening) are 127.76 mm×85.48 mm×14.35 mm. Multiwell plates come in a variety of formats within said base area but may have a different height. Typical multiwell plates comprise                6 wells in a 2×3 array, each of the wells including a volume of 2 ml to 5 ml;        12 wells in a 3×4 array, each of the wells including a volume of 2 to 4 ml;        24 wells in a 4×6 array, each of the wells including a volume of 0.5 ml to 3 ml;        48 wells in a 6×8 array, each of the wells including a volume of 0.5 to 1.5 ml;        96 wells in a 8×12 array, each of the wells including a volume of 0.1 to 0.3 ml; or        384 wells in a 16×24 array, each of the wells including a volume of 0.03 to 0.1 ml.
The multiwell plates are available in different well formats having either a flat bottom (F-bottom), a flat bottom with minimal rounded edges to the wall (C-bottom), tapered walls (V-bottom) or a bottom in U-shape (U-bottom). Multiwell plates are typically made of polystyrene or polyvinyl chloride. For cell cultures, the surfaces of these products are modified using an oxygen plasma discharge to make their surfaces more hydrophilic so that it becomes easier for adherent cells to grow on the surface which would otherwise be strongly hydrophobic.
Multiwell plates may comprise wells having a circular cross section or wells having a rectangular cross section, preferably a square cross section.
Multiwell plates may be utilized to generate and propagate spheroids or microtissues. For example, multicellular tumor spheroids (MCTS) may be generated in that equal volumes of a suspension of tumor cells is pipetted into agarose-coated wells of a multiwell plate. At the lowest area of the agarose-coating of each well only one spheroid forms, and all spheroids within the multiwell plate will have approximately the same volume. In another approach, microtissues or spheroids may be generated and propagated in hanging drops, wherein specific multiwell plates are used.
During generating and/or propagating spheroids or microtissues in a multiwell plate, for and during storage of multiwell plates containing spheroids or microtissues, as well as for and during shipping multiwell plates containing spheroids or microtissues, the multiwell plates have to be covered. Said covering prevents the cell culture in each well from contamination and secures integrity of the cell culture. Conventional polystyrene lids for multiwell plates are not suitable for shipping multiwell plates containing spheroids or microtissues at ambient temperature, because these conventional lids can not prevent spilling of the well's content. For avoiding any spill, each of the wells of a multiwell plate bearing cells has to be securely sealed.
For sealing multiwell plates that are used in molecular biological methods such as—for example—Polymerase Chain Reaction (PCR) experiments, a number of ways for sealing the plates are known. For example, a foil or plastic film may be applied across the entire upper surface of the plate. Heat sealable aluminum foils provide an efficient gas and liquid tight seal, but they are tiresome to apply and remove.
Certain adhesive plastic films made of polyethylene plates may provide an alternative for sealing multiwell allowing exchange of oxygen, carbon dioxide and water vapor. However, these films are tiresome to apply and to remove. In addition, these films are neither autoclavable nor reusable. Beyond that, the inventors found that sealing multiwell plates bearing spheroids or microtissues with an adhesive polymer film did not prevent substantial loss of viability when the microtissue-bearing multiwell plates were kept at a temperature of between 20° C. and 37° C. compared to conventional lids for multiwell plates.
Surprisingly, the inventors found that loss of viability of the cells of microtissues kept at a temperature of between 20° C. and 37° C. is significantly reduced, if the multiwell plate containing the microtissues is sealed with a specifically configured plate sealing means made of a resilient elastomer. Moreover, said plate sealing means improves handling of microtissue cultures.


A reconfigurable ring architecture for RF transport over fibers which eliminates the need for multiple pairs of fibers to serve multiple microcells and the need for backup communications lines as a result of system failure due to a fiber break. The ring architecture has a plurality of remote units which are interconnected to a host unit in a serial fashion. The host unit transmits signals to the plurality of remote units and receives signals from the plurality of remote units. Each of the remote units having photodetectors for receiving the transmitted signals and an antenna/transmitter for receiving other signals from another source; a splitter for splitting the transmitted signals into two parts, one part of the signals being output from the remote unit and the other part of the signals being transferred to adjacent remote units and then back to the host unit; and a transmitter for transferring the other signals from the remote unit to adjacent remote units and then back to the host unit. The transmission and reception of signals taking place even in the event of failure of a remote unit or the interconnection between remote units.

The transport of radio frequency (RF) signals over optical fibers has many applications in the cellular and personal communication systems (PCS) industry.
Basically, most voice and data is carried through the public switched telephone network as digital data. For a voice channel, this data is typically 64 kbit/sec. However, this format is incompatible with what a cellular or PCS provider needs to broadcast through the air. In the case of a typical analog cellular voice channel, the 64 kbit/sec channel is first converted to analog, and then to a 30 kHz wide FM signal, and finally this 30 kHz signal is upconverted to near 800 MHz to be broadcast through the air.
For the new generation of digital cellular or PCS even more conversion is required. First, the 64 kbit/sec signal is digitally compressed to a lower bit rate to save spectrum. Thereafter, other signal processing is performed, such as code or time division multiplexing (depending on which digital air interface is used), before the signal is upconverted to its RF frequency. All this conversion requires a substantial amount of electronics, which is located at the cellular base station. Furthermore, presently, in the industry, there is a desire to use smaller cell areas called microcells to provide cost effective coverage of dead spots and to increase capacity. However, the necessity of duplicating all the electronics required for the conversions described above reduces the advantages of this microcell approach.
The concept of transport over optical fibers involves carrying the signal intended for broadcast over the antenna in a form as close as possible to its final one, so that no conversions are required at the microcell site. Such an approach is described in the following publications: W. E. Stevens and T. R. Joseph, "A 1.3 .mu.m Microwave Fiber-Optic Link Using a Directly Modulated Laser Transmitter," IEEE J. Lightwave Tech., Vol. LT-3, No. 2, pp. 308-315 (1985) and D. M. Fye, "Design of Fiber Optic Antenna Remoting Links for Cellular Radio Applications," Proc. 40th IEEE Vehic. Tech. Conf., pp. 622-625, June 1990. In such a case the signals are carried at the RF frequencies which are near 800 MHz for cellular and near 1800 MHz for PCS. These very high frequencies are the reason optical fibers are required. To carry the signals over coaxial cable would require numerous microwave amplifiers which could degrade signal quality.
In the past, systems for RF transport over optical fibers involved the use of a star configuration or architecture, with point-to-point transmission between the base station and each microcell. Such a system involved the use of a separate single pair of fibers to connect a base station with each microcell. If two or more microcells were served from one base station, then separate additional pairs of fibers with associated lasers and photodetectors were required between the base station and each of the additional microcells. This type of arrangement was extremely expensive. Furthermore, in the event of a break in an optical fiber between the base station and the microcell, the RF transport link ceased to function, causing the microcell to fail and operation to end.
It is therefore an object of this invention to provide a reconfigurable ring system for the transport of RF signals to a plurality of remote units such as cell areas or microcells.
It is a further object of this invention to provide a reconfigurable ring system which enables a plurality of microcells to be served by a single pair of optical fibers interconnected between all of the remote units.
It is another object of this invention to provide a reconfigurable ring system for the transport of RF signals which permits all the remote units within the system to remain fully operational even in the event a pair of fibers is cut or damaged.
It is still a further object of this invention to provide a reconfigurable ring system for the transport of RF signals which, even in the event of failure of one of the remote units, permits all the other remote units in the system to remain fully operational.

Reconfigurable ring system for the transport of RF signals over optical fibers


A system and method for coding video in which deblocking artifacts are reduced by using modified filtering that is based, at least in part on pixel intensity associated with a coding unit, such that filtering levels are increased as pixel intensity increases. In some embodiments, an offset value or indicator of an offset value for parameters associated with deblocking filter parameters can be associated with a filtering level that is based at least in part on an intensity value.

The technical improvements in evolving video coding standards illustrate the trend of increasing coding efficiency to enable higher bit-rates, higher resolutions, and better video quality. The Joint Video Exploration Team developed a new video coding scheme referred to as JVET and is developing a newer video coding scheme referred to a Versatile Video Coding (VVC)—the complete contents of the VVC 7th edition of draft 2 of the standard titled Versatile Video Coding (Draft 2) by JVET published Oct. 1, 2018 is hereby incorporated herein by reference. Similar to other video coding schemes like HEVC (High Efficiency Video Coding), both JVET and VVC are block-based hybrid spatial and temporal predictive coding schemes. However, relative to HEVC, JVET and VVC include many modifications to bitstream structure, syntax, constraints, and mapping for the generation of decoded pictures. JVET has been implemented in Joint Exploration Model (JEM) encoders and decoders, but VVC is not anticipated to be implemented until early 2020.
Current video coding schemes implement deblocking and filtering without taking image intensity into account and consequently implement filtering of content in a uniform manner across all content. However, the data reveal that the intensity of the content can impact the degree or level of filtering that is desired or necessary in order to reduce display issues. Accordingly, what is needed is a system and method of deblocking based at least in part on pixel intensity of coding units.

This patent is subject to a terminal disclaimer.

System and method for deblocking HDR content


Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.

The inventive concepts relates to a stacked semiconductor package, and more particularly, to a semiconductor package in which an upper chip is stacked on a lower chip using a through-silicon via.
As electronic devices become more miniaturized, lighter, and provide increased multi-functional capabilities—in line with the rapid development of the electronics industry and user need, a system on chip implementing a variety of functions in a single semiconductor chip, and a stacked semiconductor package including a plurality of stacked semiconductor chips in a single semiconductor package, are being developed. Also, a semiconductor package in which the system on chip and a different semiconductor chip (e.g., a memory semiconductor chip) are vertically stacked is being developed.
However, all characteristics of semiconductor chips have to be considered to implement a stacked semiconductor package where different types of semiconductor chips are stacked. That is, there may be some limitations in designing a lower semiconductor chip depending on the characteristics of an upper semiconductor chip stacked on the lower semiconductor chip.


The invention relates to a phase rotation method for a clock recovery, comprising the steps of: providing a timing estimation value that indicates for each input data symbol at least whether an input data sample has been sampled early or late by a sampling clock signal; generating a phase offset value indicating a phase rotation of the sampling clock signal based on the timing estimation value; modifying the timing function value based on a change of the phase offset value, resulting in the timing estimation value.

The present invention relates generally to the field of clock and data recovery methods and apparatuses in general, and more particularly to measures to handle a latency of a clock recovery loop.
Clock and data recovery are an important technique to be used on the receiving side of electronic units. It is generally applied to a received high-speed serial data stream, which is transmitted without any reference to a clock signal.
High-speed digital inputs/outputs (IOs) for receiving an incoming data stream are usually based on an analog-to-digital converter sampled by a phase-rotated clock signal. The phase-rotated clock signal is obtained by means of a clock and data recovery mechanism. Analog-to-digital converters, as well as commonly applied subsequent feed-back equalizers, introduce a significant portion of a loop latency for a data item propagating through a clock recovery loop of the clock and data recovery mechanism. This loop latency generally affects the jitter tolerance specifications which are, e.g., for PCI express generation 3 and 4 and are difficult to meet. Thus, there is a general need to minimize a loop latency of the clock recovery loop.
Document US 2012/0328063 A1 describes a method and an apparatus for minimizing a loop latency caused by a demultiplexer and a phase error processor in a clock and data recovery system. By at least partially embedding a phase error processor into the demultiplexer, a portion of the total latency of a clock and data recovery architecture caused by the demultiplexer and the phase error processor can be reduced to less than a sum of the individual operation latencies.
Document U.S. Pat. No. 8,194,792 B2 discloses a clock and data recovery circuit in which a look-ahead technique is employed to produce a low-latency timing adjustment.
Document U.S. Pat. No. 6,873,668 B2 discloses a clock recovery circuit having two phase comparators operating in parallel and feeding a single loop filter. A first recovery section for recovering a clock signal from the known digital feedback control and a second clock recovery section including either analog feed-forward components or feedback components causing a much shorter clock delay are provided. A first feedback loop is configured to detect a first phase difference using the output of the digital filter and a second feedback loop is configured to detect a second phase difference using the output of the analog-digital converter. The gain of the second feedback loop is adaptively controlled. The second phase difference derived from the output of the analog-digital converter can be used to reduce the clock delay caused by the analog-digital converter thus contributing to boosting the gain of the clock recovery loop.
Document US 2013/0251084 A1 discloses a low-jitter clock recovery unit having a first phase detector for measuring the phase difference between a first clock signal from a voltage-controlled oscillator and a data signal. A phase shifter responsive to a control signal based on the phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the voltage-controlled oscillator. The phase-locked loop including the voltage-controlled oscillator filters out jitter.

International Business Machines Corporation


A lighting device includes at least a light source for emitting light rays and a guide for guiding light rays on a projection plane. The guide is formed by a lens presenting a cylindrical portion extending along an axis perpendicular to the projection plane, and at least one convex shaped surface extending at an extremity of the cylindrical portion. The convex shaped surface is adapted to direct a portion of the light rays emitted from the light source towards the projection plane. This enables to project the light towards a projection plane quasi parallel to the beam direction without using any guides on the projection plane itself.

Such a lighting device is known from the document EP0242739. Means for guiding the light are constituted of strips and bars provided on the projection plane. Such a solution presents the drawback of being cumbersome because of the presence of a grid of strips and bars. The size of such a lighting device can not be reduced more than the desired size of the display. Applications for such a lighting device are consequently reduced to display applications mainly.

Lighting device having a cylindrical lens


This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.

1. Field of the Invention
The present invention relates to a flip chip packaging structure and method of a semiconductor integrated circuit and, in particular, to a flip chip packaging structure and method of an image sensor.
2. Description of the Related Art
Multilayer packaging is one of the most advanced processes for fabricating semiconductor integrated circuit (IC) products. With the multilayer package, the space between the electrodes of an IC chip having multilayer package electric circuits is increased; the chip is protected from the internal stresses of the package and any external stresses, and an appropriate thermal path for dissipating heat generated by the chip and an electrical interconnection are established. The method for packaging an IC chip is deemed as the system used for the package, dominating the total cost, performance and reliability of the whole package chip.
IC chip packaging generally falls into two categories, that is, hermetic packages and non-hermetic packages. When a chip is packaged by the hermetic package, it is isolated from the external environment by a vacuum seal or a particular kind of gas surrounding the chip. In general, such hermetic packages are the ceramic packaging used for high efficient applications. In other words, when a chip is packaged by the non-hermetic packages, it is not substantially isolated from the external environment. In this light, the hermetic packages have higher fabrication cost than the non-hermetic packages. Even so, the hermetic packages are still needed in some particular applications such as image sensors or pressure detectors. The recently advanced application with the plastic packaging has expanded the scope of usage and the performance of the hermetic packages. Since the traditional method for fabricating products is good for automatic batch processing, the plastic packages are highly cost-effective.
An IC chip packaging recently developed is ball grid array (BGA) packages, which can be used for both the ceramic packaging and the plastic packages. The BGA packages use a plurality of solder balls or bumps to serve as interconnections between the IC chip and other micro electronic devices providing electricity, mechanical support or heat transfer. The solder balls or bumps cause the IC chip to be fixedly mounted on a circuit board, and are electrically connected with the conductive pattern of the circuit board. The BGA techniques are included in the bonding technology defined as the controlled collapse chip connection (C4) or the flip chip technology.
The flip chip technique can be used to bond various circuit boards comprising a ceramic substrate, a printed circuit board, a flexible circuit and a silicon substrate. The solder bumps are generally disposed on a conductive bond pad of an area array of a flip chip, the conductive bond pad being electrically interconnected to an electric circuit trace on the flip chip. Since micro-electric circuits of the flip chip will generally perform various functions, a number of solder bumps will therefore be required. As a rule, each side of the flip chip has a size of about 13 mm, resulting in solder bumps jammed on the perimeter of the flip chip. Thus, the conductive pattern of the flip chip is consisted of various conductors spaced apart appropriately equal to or less than 0.1 mm as a matter of course.
Leadless chip carrier (LCC) packages are generally found in an image sensor such as a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor.
The CCD image sensor is an electronic device capable of converting an optical pattern or image into a charged pattern or an electronic image, comprising a number of photosensitive units capable of modifying, storing and transferring a charge to another photosensitive unit. In designing an image sensor, the material is selected subject to the photosensitivity of silicon. Each photosensitive unit represents a pixel. Semiconductor technologies and design rules dominate the array structure and matrix structure of the pixels. Signal output from the CCD is modified by means of one or more than one amplifier disposed on the edge of the chip. An electronic image is obtained by a series of pulses which sequentially output the charge of one pixel in array after another pulse is output to an output amplifier. Then, the output amplifier converts the charge into a voltage. An external electric circuit transfers an output signal in an appropriate form for detection or pick-up.
The CMOS image sensors operate at a voltage lower than the CCD image sensor so as to reduce power consumption and facilitate the portability. Each CMOS active pixel sensing unit has an amplifier with buffering capability for reading/writing separately. A conventional pixel sensing unit has four transistors and a photosensitive unit. The pixel sensing unit has a transfer gate for separating the photosensitive unit from a floating diffusion having a capacitance, a reset gate interposed between the floating diffusion and a power supply, a source-follower transistor for temporarily storing the capacitance of a read-out line in the floating diffusion, and a row of select gates for connecting the pixel sensing unit to the read-out line. All the pixels connected in column -are connected to a shared sense amplifier.
In comparison with the CCD image sensor, the CMOS image sensor not only reduces power consumption but also has a generally simple scheme due to decoupling and crystallization characteristics. Hence, a miniature CMOS image sensor is easy to design, requiring fewer circuits in support thereof.
FIG. 5 shows a traditional leadless chip carrier package 30 which is generally used for a CCD or CMOS image sensor IC chip. The leadless chip carrier package 30 comprises a transparent cap layer 32 made of glass having a supporting layer 35. An anti-reflection coating 34 is interposed between the glass cap 32 and the supporting layer 35. A multilayer substrate 36 has a castle-shaped structure 42 with an image sensor chip 38 provided thereon. An upper lead 40 extends from the chip 38 to be electrically connected to a lower lead 44 encased on the bottom and the sides of the substrate 36. The transparent glass cap 32 facilitates light transmission to the image sensor chip 38.
The leadless chip carrier package 30 generally has a thickness 46 of about 2 mm. When the leadless chip carrier package 30 is used for the image sensor package 30, a relatively large space is required. In most cases, an over-sized image sensor restricts the utilization of the leadless chip carrier package 30. In this light, there is a dire need to provide the image sensors with a new and improved packaging structure and method.

Packaging structure and method of an image sensor module

Industrial Technology Research Institute


A diffraction element for diffracting a particular wavelength of incident optical beam includes: a base section made from a first resin and provided with a predetermined diffraction pattern; and a cover section made from a second resin and covering the diffraction pattern, wherein a rate of change of refraction index of the first resin is substantially the same as a rate of change of refraction index of the second resin in a temperature range between a first temperature and a second temperature.

1. Field of the Invention
The present invention relates to a diffraction element, objective lens unit, optical pickup and optical disc apparatus, and is preferably applied to an optical disc device, for example.
2. Description of Related Art
There is an optical disc device that supports a plurality of types of optical discs: Compact Disc (CD), Digital Versatile Disc (DVD) and "Blu-ray Disc (Registered Trademark)" (BD). The wavelengths of laser beam vary according to the types of optical discs.
As an optical pickup for the optical disc device, there is one capable of collecting different wavelengths of laser beams by a diffraction element and a subsequent objective lens: Considering different focal distances of the optical discs, the diffraction element only diffracts particular wavelengths of laser beams while laser beams of other wavelengths passes through it without being diffracted.
This kind of diffraction element includes a step-like diffraction pattern made from a resin, and a plane cover layer made from the other resin to cover the diffraction pattern (see Jpn. Pat. Laid-open Publication No. 2005-302270, for example).

Diffraction element, objective lens unit, optical pickup and optical disc apparatus


Structures for 3D sense amplifiers for 3D memories are disclosed. A first embodiment uses one type of vertical transistors in constructing 3D sense amplifiers. A second embodiment uses both n- and p-type transistors for 3D sense amplifiers. Either or both of n- and p-type transistors are vertical transistors. The n- and p-type transistors may reside on different levels, or on the same level above a substrate if both are vertical transistors. In any embodiment, different options are available for gate contact formation. In any embodiments and options or alternatives thereof, one or more sense-enable circuits may be used. Sense amplifiers for several bit lines may be staggered on one or both sides of a memory array. Column multiplexers may be used to couple particular bit lines to data outputs. Bit-line multiplexers may be used to couple certain bit lines to shared 3D sense amplifiers.

One of the driving forces of scaling down semiconductor manufacturing technology is the ever increasing demand for higher density memory devices. Technology scaling has indeed satisfied needs for high density memories of certain applications. However, certain other applications require extremely high density memories which technology scaling alone could not satisfy without resorting to multi-chip solutions. Three-dimensional (3D) memories, particularly those constructed with vertical transistors over an underlying memory control logic, has expanded the memory density that can be integrated on a single chip in efforts to address those certain other applications.
Vertical transistors used in virtually (if not completely) all 3D products are vertically oriented MOSFET's (metal-oxide-semiconductor field-effect transistors). For this reason, throughout the present disclosure, the terms "vertical transistor," "n-type vertical MOSFET," and "p-type vertical MOSFET" are used interchangeably with "vertical MOSFET," "vertical n-MOSFET," and "vertical p-MOSFET," respectively.
3D memory products, whether in the marketplace or under development, have so far employed vertical transistors in their memory cells and planar transistors in their memory control logic including sense amplifiers. Since vertical transistors are built over memory control logic, memory cells and sense amplifiers reside at different levels. In such arrangements, sense amplifiers can be optimally designed to minimize the effects of the manufacturing fluctuations on mismatch and thus to maximize the operating margin of the memory product. Usually mirror imaging of circuit elements used in designing sense amplifiers is avoided because misalignment during photolithography steps of certain critical layers would shift characteristics of mirror-imaged elements in opposite directions, frequently leading to failure of sense amplifiers.
In memory products, particularly in virtually all DRAM or flash products, the signal developed on a bit line by a memory cell during a read operation is a fraction of the voltage powering the memory cell. That signal, called bit-line swing, is often as low as or around 100 mV. That small signal must travel through a long 3D routing from a bit line down to a sense amplifier. Substantial loss of the small signal is inevitable along the path. The signal might even be lost in the middle of the long 3D routing. Mitigation or prevention of such undesirable consequences usually requires very large and complex 3D routing and sense amplifiers for each bit line, compared to those used in conventional memory products constructed only with planar transistors. Sense timing is a critical factor, because the small signal may be lost after a relatively long wait but the small signal may have not arrived before a relatively short wait. Due to a longer time required to travel a long 3D path, the timing window for sensing is much narrower in a memory of vertical transistors than that in a memory of planar transistors. The signal delay associated with the long 3D path, if the bit-line swing must reasonably develop at sense amplifiers before a successful sensing is guaranteed, entails an increase in the complexity of design and in chip size.
An alternative to the complexity and size of memory logic circuit in resolving such issues of signal loss and timing delay may be the design and construction of memory cells for a much larger bit-line swing so that even the arrival of a fraction of a fully developed bit-line swing can successfully excite the sense amplifier. This is particularly true for high performance and/or high throughput products. Such an alternative would, however, require much wider vertical transistors, and may severely undermine the very advantages of 3D memories built with vertical transistors. The logic circuitry on the substrate and the memory cells above the substrate may have to increase in size significantly.


Aqueous liquid dishwashing detergent compositions are prepared that exhibit improved detergency performance and foam stability over a range of water hardness levels. A preferred formulation incorporates a three component mixture: an anionic surfactant, a nonionic surfactant, and an amido amine oxide to provide a detergent having good detergency performance and foam stability over a range of water hardness levels. Another preferred formulation incorporates a three component mixture: an anionic surfactant, a nonionic surfactant, and an alkyl ethoxylated carboxylate to provide a detergent having good detergency performance and foam stability at high hardness levels.

This invention relates to light duty dishwashing detergents, and in particular, to light duty dishwashing detergents that are effective over a wide range of water hardness levels. Light duty liquid detergents, such as are suitable for use in the washing of dishes, are well known and have met with a high degree of consumer acceptance because of their good washing and foaming properties and convenient form for use. Most of the formulations in commercial use at the present time are based on synthetic organic detergents which, together with supplementing materials often used, give them satisfactory detergency and foaming properties. Nevertheless, there is an ongoing effort to make products that clean and foam even better and produce more stable foams.
A particular problem with generally available detergents exists when the water used for washing is soft (i.e., has a hardness level less than 25 ppm as CaCO.sub.3). At these low water hardness levels, the stability of the foam can be inadequate. Consequently, a need exists for a dishwashing detergent that provides good foam stability over a wide range of water hardness levels.
Surprisingly, it has been found that a dishwashing detergent that is effective and provides stable foam over a wide range of water hardness levels can be prepared by combining, in a three component mixture, an amido amine oxide, an anionic surfactant, and a nonionic surfactant. The use of the amido amine oxide provides an unexpected increase in detergency and foam stability over a range of water hardness levels especially when compared to a detergent formulated with the same anionic and nonionic surfactant without the amido amine oxide. Surprisingly, a detergent containing the amido amine oxide shows a marked increase in performance as the water hardness level is increased when compared to detergents containing an alkyl amine oxide combined with an anionic and nonionic surfactant.
Another problem with generally available detergents exists when the water used for washing has a hardness level greater than about 300 ppm (as CaCO.sub.3). At a high hardness level the amount of foam produced and the performance of the detergent is reduced.
Unexpectedly, it has been found that a dishwashing detergent that is effective at high hardness levels can be prepared by combining, in a three component mixture, an alkyl ethoxylated carboxylate, an anionic surfactant, and a nonionic surfactant. A composition containing the alkyl ethoxylated carboxylate shows a surprising increase in detergency when used in hard water (greater than 300 ppm as CaCO.sub.3) as compared to the detergency of a composition without the alkyl ethoxylated carboxylate.
The present invention thus provides a detergent that exhibits good detergency performance and foam stability over a range of water hardness levels and a detergent that exhibits good detergency and foam stability at high hardness levels.


A backing pad 7 is secured on the bottom of a ceramic plate 6. A template 1 is secured on the bottom of the backing pad 7. The thickness of the template 1 successively diminishes from the inner periphery wall 12 of the central accommodation opening for restraining the semiconductor wafer, toward the outer periphery wall 13 of the template 1, so that the bottom of the template 1 is inclined and the cross section of the template 1 is tapered.

1. Field of the Invention
The present invention relates to a method of polishing a semiconductor wafer retained by a template and to templates used in the polishing operation.
2. Description of Prior Art
As shown in FIG. 4, in the operation of polishing a semiconductor wafer 10 which is restrained within a template 8 and is impelled in to contact with an abrasive cloth 5, there exists a clearance 9 between the bottom surface of the template 8 and the upper surface of the abrasive cloth 5 due to the width difference between the template 8 and the semiconductor wafer 10. Therefore, the stresses induced on the upper surface of the abrasive cloth 5 vary abruptly within the region which takes the contact point 81 of the template 8 and the semiconductor wafer 10 as its center. For this reason, deflection 51a appears on the upper surface of the abrasive cloth 5, and this will cause inadequate contact between the outer peripheral portion 10a of the semiconductor wafer 10 and the outer contact surface 51 of the abrasive cloth 5. Accordingly, it is very difficult to polish the outer peripheral portion 10a of the semiconductor wafer 10. As a result, as shown in FIG. 5, the central portion of the polished surface of the semiconductor wafer 10 will become depressed, and the flatness of the semiconductor wafer 10 will be impaired after polishing.

Template used for polishing a semiconductor wafer


A lighting inverter provides voltage and current to a gas discharge lamp in general and a metal halide lamp in particular with a novel power factor controller. The power factor controller. step down converter having the device stresses of a buck converter, continuous current at its input like a CUK' converter, a high power factor, low input current distortion and high efficiency. The inverter consists of two cyclically rotated CUK' switching cells connected in a half bridge configuration and operated alternately. The inverter is further optimized by using integrated magnetics and a shared energy transfer capacitor. The AC voltage output from the inverter is regulated by varying its frequency. A ballast filter is coupled to the regulated output of the inverter. The ballast filter is formed by a series circuit of a ballast capacitor and a ballast inductor. The lamp is preferably connected across the inductor to minimize the acoustic arc resonance. The values of the capacitor and the inductor are chosen so as to satisfy the firing requirements of the HID lamps. A plurality of lamps are connected by connecting the multiple lamps with the ballast filters to the secondary of the inverter transformer. Almost unity power factor is maintained at the line input as well as the lamp output.

1. Field Of Invention
This invention is directed toward developing a high frequency economical electronic ballast having high power factor, low device stresses, high frequency, low switching losses, and sine wave output for lighting nonlinear loads such as HID lamps, more specifically metal halide lamps and also to provide plurality of the lamp connections for the lighting industry in general.
2. Description Of The Prior Art
The contemporary high frequency electronic ballasts used for lighting purposes use either boost converter or a flyback converter in discontinuous mode for controlling the power factor, and to pre-regulate the DC voltage connected to the inverter. Bandel, in his U.S. Pat. No. 5,359,274, uses boost converter for power factor correction. Mortimer et. al. in their U.S. Pat. No. 5,204, 587 uses flyback PWM converter in discontinuous mode to correct the power factor. Also, use Mapham inverter or Shwartz inverter, or their modifications having half bridge or fall bridge configurations. The prior art Mapham inverter is described by Neville Mapham in IEEE Transactions on Industry and General Applications, March/April 1967, IGA-2, No. 2, pages 176-187. Mapham showed an SCR inverter with a good regulation and a sine wave output which provides a frequency dependent output voltage, such as shown in FIG. 1. U.S. Pat. No. 4,220,896 by Derek A. Paice describes a ballast filter which reduces the KVA ratings of the transformer. But in the above mentioned prior art, only the voltage ratings of the transformer are reduced by quality factor times four times the ballast filter. The current ratings of the transformer are increased as it has to take care of the filter capacitor current. Thus, insulation requirements of the transformer are reduced at the cost of increased copper losses in the transformer. From the switch point of view voltage ratings of the switches are reduced, making them economical.
The converters used for power factor correction in the contemporary art had the drawbacks of either forcing high voltage on the inverter switches, or it produced the discontinuous current at the input, thus contributing to EMI/RFI produced. Also the switches used in the prior art inverters have high on losses. This is because the switches have to support the additional current drawn by the capacitor connected in parallel with the transformer primary. For proper operation of the Mapham inverter, a value of the capacitor should be such that it draws at least four times the instantaneous load current.

High frequency electronic ballast for lighting

Allied Energy Services International, Inc.


A control system for a voltage converter includes: a power comparator for comparing a power signal on input terminals of the converter with a commanded power signal and producing a power comparison signal; a power regulator for transforming the power comparison signal to a commanded current signal; a current comparator for comparing the commanded current signal with a measured current signal on output terminals of the converter and producing a current comparison signal; a current regulator for transforming the current comparison signal to a pulse width modulator (PWM) duty cycle command signal; and a PWM for using the PWM duty cycle command signal to control electrical switches of the converter. The control system may further include: a command multiplier for converting a voltage signal across the output terminals of the converter to a gain signal having a value between zero (0) and unity (1), and a power multiplier for multiplying the commanded power signal by the gain signal to provide a limited commanded power signal, wherein power comparator compares the limited commanded power signal with the power signal on the input terminals.

The present invention relates to voltage converter interfaces for regulating power flow.
Switch-mode converters with reversible power flow are described, for example, in Chapter 8 of Ned Mohan et al., Power Electronics--Converters, Applications, and Design, 2.sup.nd ed. (John Wiley & Sons 1989). Auxiliary energy storage devices such as ultra-capacitors and batteries can be used to provide power to or receive power from DC or AC power buses. An example of such an application is the use of a battery power distribution system on an electric or hybrid vehicle. An external system controller is used to control an interface between the storage device and the power bus.
The level of power delivered to a storage device is a function of the direction of power flow. Control of the storage device power is most convenient on the storage device side of the interface. However, in some circumstances the power which actually needs to be controlled is the power flow on the power bus side of the interface. The relation between the storage device and power bus sides of the interface is complicated by interface losses and non-linear characteristics. It is thus difficult to regulate power flow on the power bus side of the interface by controlling the storage device side of the interface.

Bi-directional power control system for voltage converter


A power converter includes a power switch adapted to receive an input power from an external power source and to generate an output power, and an adaptive oscillator adapted to output an adaptive minimum-on signal of the power switch in response to a change in measured magnitude of at least one of the input power and the output power.

1. Field of the Invention
Embodiments relate to switching DC-DC power converters including adaptive-minimum-on-time control and methods of adaptively controlling minimum-on-time for switching DC-DC power converters. More particularly, embodiments relate to switching DC-DC power converters including adaptive-minimum-on-time control and methods of adaptively controlling minimum-on-time of switching DC-DC converters, which may enable a reduction in switching loss by adaptively controlling a duty cycle of a power switch thereof based on, e.g., a magnitude of an input (or output) voltage.
2. Description of the Related Art
Switching DC-DC power converters, e.g., buck converters, may be employed in various electronic devices, e.g., mobile phones, laptop computers, etc., which receive power from a voltage source, e.g., a battery. Such electronic devices may include a plurality of circuits, e.g., an encoder, a decoder, a memory, a processor, etc., each of which may require a different voltage level than a voltage level supplied from a battery of the electronic device, and thus, DC-DC power converters may be employed to generate multiple controlled voltages from the single battery voltage.
A DC-DC converter may accept an input DC voltage Vin and may generate an output DC voltage Vo by, e.g., controllably storing energy in a component(s), e.g., a magnetic component such as an inductor. The amount of energy stored in the component(s) may be controlled by adjusting a duty cycle (ratio of on/off time) of, e.g., a power switch (e.g., two transistors connected in series between a first voltage source and a second voltage source) through which current and/or voltage is supplied. Accordingly, an output voltage Vo of a DC-DC converter is generally based on at least the input DC voltage Vin and the duty cycle of the transistors of the power switch, i.e., an amount of time the respective transistors are on and a number of times of the power switch is switched on and off.
In known devices, a minimum on-time of the power switch is set based on a maximum voltage of the battery of the electronic device. However, characteristics of the input DC voltage Vin supplied from a battery of the electronic device may change, e.g., decrease, over time. Therefore, in such known DC-DC converters efficiency thereof may decrease over time as the input DC voltage Vin supplied thereto decreases.
Further, with regard to the duty cycle of the power switch, some power is generally lost during operation of a switch. Power loss generally corresponds to a sum of conduction loss and switching loss. Conduction loss is generally proportional to a magnitude of output current, while switching loss is generally proportional to a number of switching times of the power switch. More particularly, power switching loss Psw may be represented by Equation 1:Psw=CV2f  (Equation 1)where C is parasitic capacitance of transistor(s) of the power switch, V is the charged voltage of the parasitic capacitance C, and f is the number of switching times for generating a desired output voltage Vo (or current).
Accordingly, it is desirable to provide a DC-DC converter that adaptively controls a minimum-on-time of the power switch in view of a change in the DC input voltage Vin and/or the power switching loss of the power switch.

Switching DC-DC converter with adaptive-minimum-on-time control and method of adaptively controlling minimum-on-time of a switching DC-DC converter


A method of determining fatigue load of at least one operative wind turbine, comprising: providing a transfer function that associates an obtained at least one measurement value of a first sensor to an obtained at least one measurement value of a second sensor the at least one measurement value of the first sensor and the at least one measurement value of the second sensor being obtained by use of a reference wind turbine at which the first sensor and the second sensor are located; obtaining at least one measurement value of a third sensor, wherein the third sensor is located at the at least one operative wind turbine, and wherein the third sensor corresponds in type and position to the first sensor at the reference wind turbine; calculating at least one transfer function value corresponding to the obtained at least one measurement value of the third sensor by use of the provided transfer function; calculating the fatigue load of the at least one operative wind turbine based on the calculated transfer function value.

In order to reduce technical effort in wind turbine manufacturing, it is desired to reduce safety redundancies in the design of wind turbine supporting structures.
Limits for reducing such safety redundancies are usually defined by the mechanical stress that affects the wind turbine. A known approach is thus to design the wind turbine structures so as just to withstand the cumulative fatigue loading on the structure throughout its design life when operating under a given set of environmental conditions.
Wind turbines are often operated under conditions in which the fatigue loads are occasionally of such magnitude that if the loads were to be maintained at that magnitude, the fatigue capacity of the wind turbine structure would be exceeded during its entire design lifetime. To meet such situations, it is known in the state of the art to implement load monitoring sensors and to shut down the wind turbine in case of high loads or even overloading.
However, shutting down a wind turbine in such a manner produces undesired times of unavailability, in which the wind turbine does not produce energy. Further, the shutdown process may by itself add to the overall fatigue damage of the wind turbine.
European patent application publication EP 1 674 724 describes a method wherein the position of components of the wind turbine is determined with respect to a fixed reference location with one or more sensors coupled with the wind turbine component. Here, fatigue load analysis is performed based on output signals from the one or more sensors. However, for this method, a plurality of accelerometers is required, which further need to be located in a specific geometrical pattern, for example a number of three accelerometers that are oriented in an orthogonal manner. Further, the solution proposed therein requires complex mathematical processing of the accelerometer signals by performing a double integration in order to provide an approximate displacement figure.
An alternative solution that may avoid the complex calculations of the solution described above is proposed in U.S. Pat. No. 4,297,076. This patent describes a wind turbine that comprises load measurement means (strain gauges) which are coupled to the wind turbine blades for measuring the bending moment on said blades and for providing an output signal representative thereof. Further, it provides adjustment means which are coupled to said load measurement means for varying the pitch of said tip portions in response to said output signal.
In a similar manner, the system presented in United States patent application publication US 2002/0047275 A1 comprises a rotor hub which is provided with measurement means for the mechanical loading at the hub.
However, the use of strain gauges for directly measuring the mechanical loads acting on the wind turbine suffer from the disadvantage that strain gauges, such as bonded or welded strain gauges, require expertise to install and maintain and moreover have only a comparatively short technical lifespan.
Various alternative approaches are known from the state of the art:
In United States patent application publication US 2004/0151577 A1, a wind turbine is described which comprises one or more sensors connected to directly detect deflection of a main shaft flange of the wind turbine from one or more predetermined positions. Further, a signal is generated that corresponds to the detected deflection, and a control circuit is coupled with the sensors to receive the signals and to mitigate a load causing the deflection of the main shaft flange in response to the signals. However, this method has the disadvantage that shaft deflections may be caused by numerous factors, including internal bearing play and flexibility. Further, the correlation between loading and deflection will generally be suboptimal.
United States patent U.S. Pat. No. 4,339,666 describes a blade pitch angle control for a wind turbine generator that utilizes means providing a turbulence factor signal that is indicative of the degree to which the present instantaneous wind velocity may exceed a present average wind velocity. It further proposes signal processing means for providing a load capacity signal as a function of the turbulence measurement. However, the wind speed measurement is taken at a certain point, such as at hub height, so that the point at which the measurement is taken is not indicative of the wind speed that actually acts at the rotor disk.
The system proposed in the aforementioned patent may be combined with the system of UK patent application GB 2 067 247 A, which describes a method in which the instantaneous wind speed is measured at the blade surfaces and where this measurement is used to reduce loads. These methods however do not take into account accumulated fatigue data and will therefore perform more load regulation over the lifetime of the wind turbine than may be needed when talking into account "unused" fatigue capacity.

Method for determining fatigue load of a wind turbine and for fatigue load control, and wind turbines therefor


A method for optimizing completion building is disclosed. The method involves receiving a work request by a host channel adapter (HCA), caching a portion of the work request in a completion cache in the HCA, wherein the cached portion of the work request includes information for building a completion for the work request, receiving, by the HCA, a response to the work request, querying the completion cache upon receiving the response to the work request to obtain the cached portion of the work request, and building the completion for the work request using the cached portion of the work request, wherein the completion informs a software application of at least a status of the work request as executed by the HCA.

The Infiniband® network includes nodes that communicate through a channel-based switched fabric (Infiniband® is a registered trademark of Infiniband Trade Association, located in Beaverton, Oreg.). For example, the nodes may be a host, an input/output subsystem, or a router which connects to another network. The switched fabric is made up of a collection of switches, routers, and/or links that connect a set of channel adapters. The channel adapters form an interface between the switched fabric and the nodes. The channel adapter of the host is referred to as a host channel adapter. The channel adapter of an I/O subsystem is referred to as a target channel adapter.
In Infiniband®, two processes communicate using a queue pair. A queue pair includes a send queue and a receive queue. Specifically, in order for a process to send a message to another process, the process posts the message to the send queue. The host channel adapter sends the message in the form of packets to the channel adapter having the receive queue. Each packet that is sent may include a packet sequence number. Logic associated with the receive queue ensures that packets are processed in a particular order using the packet sequence number.
Infiniband® supports operations such as remote direct memory access (RDMA) read and write operations and reliable connections. Specifically, a requesting process may send a request in the message for the receiver to store data and/or return data. In response, the remote node's channel adapter includes functionality to store and/or return the requested data to the requesting process.
In network communications, reliable connections (both for remote copying and extended remote copying) are implemented by the requester having an acknowledgement when a packet is successfully transmitted or having a timeout if an acknowledgement is not received within a fixed programmable time after a packet is sent. When an acknowledgement is received by the requestor, the requestor must 'complete' the request by writing required data to a completion queue in main memory. The data for the completion is obtained from the send queue of the corresponding queue pair (QP). A completion is written to the completion queue in order to provide a user with information about the send request. In the event that packet transmission is not successful, after the timeout period has elapsed, the initial transmission is followed by packet retransmission, where duplicated packets are ignored by the responder. Once a timeout for a given request packet is detected, the requester may retry the request.

Method and system for an on-chip completion cache for optimized completion building


A measuring device for measuring a length of a sheet includes a sheet-carrying unit for carrying a sheet, a reading unit having an area sensor and configured to repeatedly read the surface of the sheet from the leading end to the trailing end of the sheet while the sheet is being carried by the sheet-carrying unit, and a measuring unit for measuring the length of the sheet in the carrying direction on the basis of information regarding the sheet surface that is repeatedly read by the reading unit.

1. Field of the Invention
The present invention relates to devices for measuring lengths of sheets while the sheets are carried, and relates to image forming apparatuses such as copying machines and printers including the measuring devices.
2. Description of the Related Art
According to known methods for forming images on both sides of sheets in image forming apparatuses, toner images are first formed and fixed on first surfaces of the sheets. The sheets are then sent to double-sided printing paths so as to be reversed, and toner images are formed and fixed on second surfaces.
However, when the sheets are heated and pressurized during fixing of the toner images on the first surfaces, moisture content in the sheets is vaporized and fibers are extended, resulting in subtle changes in the size of the sheets after the fixation. Therefore, in order to adjust the positions of the images on the back surfaces of the sheets relative to those on the front surfaces, it is necessary for the image forming apparatuses to form images suitable for the image sizes on the second surfaces changed from those on the first surfaces after the passage of the sheets through fixing units.
In order to support the above-described phenomenon, an image forming apparatus that changes image sizes on second surfaces of sheets according to the change in the sheet size caused by the passage of the sheets through a fixing unit is disclosed in Japanese Patent Laid-Open No. 5-008460.
The image forming apparatus disclosed in the Japanese Patent Laid-Open No. 5-008460 defines variations in sheet size as a predetermined value, although the amount of vaporization of the moisture content in the sheets and the amount of elongation of the fibers are practically changed according to types of sheets and fixing conditions. That is, since the variations in sheet size are changed according to various conditions, the image forming apparatus needs to measure the actual sizes of the sheets so as to obtain more accurate variations.
An image forming apparatus measuring actual sizes of sheets is disclosed in Japanese Patent Laid-Open No. 3-172255. The image forming apparatus measures time from start of driving registration rollers to detection of the trailing end of a sheet using a sheet-detecting sensor, and converts the time into a length using carrying speed. Moreover, Japanese Patent Laid-Open No. 4-121345 (corresponding to U.S. Pat. No. 5,291,225) discloses an image forming apparatus that converts the number of clock pulses for driving a feed motor into a length by multiplying the clock pulses by the carrying speed of the sheet, the clock pulses being counted during a period between detection of the leading end and the trailing end of a sheet using a sheet-detecting sensor.
However, the carrying speed of the sheet is not simply determined by only the rotating speeds of the registration rollers or those of carrying rollers driven by the feed motor, and errors may be generated due to eccentricity or abrasion of the rollers. Therefore, when the rollers slip during carrying of a sheet, for example, the sheet size is not accurately detected in the technologies disclosed in Japanese Patent Laid-Open Nos. 3-172255 and 4-121345.

Device for measuring sheet length and image forming apparatus


A battery voltage detecting circuit includes: a first capacitor having one end connected to one input terminal of an operational amplifier; a second capacitor having one end connected to an output terminal of the operational amplifier and the other end connected to the one input terminal of the operational amplifier; a third capacitor having one end connected to the other input terminal of the operational amplifier; a fourth capacitor having one end applied with a reference voltage and the other end connected to the other input terminal of the operational amplifier; and a switching circuit configured to electrically connect the one input terminal of the operational amplifier to the one end of the first capacitor after the transient current has stopped flowing.

1. Field of the Invention
The present invention relates to a battery voltage detecting circuit.
2. Description of the Related Art
In an apparatus such as a notebook-sized personal computer that uses rechargeable batteries, the voltage of each of the batteries needs to be highly precisely detected to manage recharge/discharge of each of the batteries that are connected in series. FIG. 3 depicts a common configuration of a battery voltage detecting circuit (see, for example, Japanese Patent Application Laid-Open Publication No. 2002-243771). A battery voltage detecting circuit 100 is used for detecting the voltages of four batteries BV1 to BV4 that are connected in series, and is configured including an operational amplifier 110, resistors R1 to R4, switches SW0M to SW4M and SW0P to SW3P, and a power source 115 that outputs a reference voltage VREF. In such a battery voltage detecting circuit 100, when a voltage VBV4 of the battery BV4 is to be detected, the switches SW4M and SW3P are turned on and other switches are turned off. Thereby, a voltage VOUT that corresponds to the difference between a voltage V4 of a plus terminal of the battery BV4 and a voltage V3 of a minus terminal thereof is output from the operational amplifier 110 to an AD converter (ADC) 120. The ADC 120 converts the voltage VOUT into a digital value and, thereby, the voltage VBV4 of the battery BV4 can be detected. Similarly, the switches SW3M and SW2P are turned on and other switches are turned off and, thereby, a voltage VBV3 of the battery BV3 can be detected. The switches SW2M and SW1P are turned on and other switches are turned off and, thereby, a voltage VBV2 of the battery BV2 can be detected. Furthermore, the switches SW1M and SW0P are turned on and other switches are turned off and, thereby, a voltage VBV1 of the battery BV1 can be detected.
When lithium ion batteries are used as the batteries BV1 to BV4, each of the voltages VBV1 to VBV4 between both terminals of each of the batteries BV1 to BV4 reaches about 4.5 V when the batteries are fully recharged. Assuming that each of the voltages VBV1 to VBV4 respectively of the batteries BV1 to BV4 is defined as 5 V taking the design allowance into account, the batteries BV1 to BV4 connected in series as a whole generate a voltage of 20 V and, therefore, the battery voltage detecting circuit 100 needs to be of a high-voltage type. On the other hand, a circuit including the ADC 120 in a control system generally uses a power source voltage of about 3 V and the voltage VOUT output from the battery voltage detecting circuit 100 needs to be 3.3 V or lower.
In this case, assuming that the resistance values of the resistors R3 and R4 respectively are R3 and R4, the gain GAMP of the operational amplifier 110 is R4/R3. Therefore, the VOUT output when the voltage VBV4 of the battery BV4 is detected is VOUT=VBV4/GAMP+VREF=(V4−V3)R3/R4+VREF. Assuming that VBV4 is 5 V and VREF is 0.2 V, a condition for the gain GAMP of the operational amplifier 110 to be VOUT≦3.3 V is that GAMP≦(VOUT−VREF)/VBV4=(3.3−0.2)/5≈0.6. Based on this condition, the resistance values respectively of the resistors R3 and R4 are selected such that the gain GAMP of the operational amplifier 110 becomes about 0.6 and, thereby, the voltage VOUT output to the ADC 120 can be made 3.3 V or lower. However, in this case, the operational amplifier 110 needs to be of a high-voltage type and this results in increase of the cost of the battery voltage detecting circuit 100.
To make the operational amplifier 110 need not to be of a high-voltage type, the voltage applied to the operational amplifier 110 needs to be 3.3 V or lower. That is, to make the voltage V+ applied to a + input terminal of the operational amplifier 110 be 3.3 V or lower, that (V3−VREF)R4/(R3+R4)+VREF≦3.3 needs to be satisfied. This leads to R4/(R3+R4)≦(3.3−VREF)/(V3−VREF)=(3.3−0.2)/(15−0.2)=3.1/14.8≈0.21. Therefore, the gain GAMP of the operational amplifier 110 is GAMP=R4/R3≦0.21/(1−0.21)≈0.26. Therefore, by selecting the resistance values respectively of the resistors R3 and R4 such that the gain GAMP of the operational amplifier 110 is about 0.26, the operational amplifier 110 can be made need to not be of a high-voltage type. However, in this case, the voltage VOUT input into the ADC 120 goes low because the gain GAMP of the operational amplifier 110 is small. Therefore, to highly precisely detect the battery voltage, the ADC 120 needs to be of a high-precision type and this results in increase of the cost thereof.
In the battery voltage detecting circuit 100, when the voltages respectively of the batteries BV1 to BV4 are detected, a current flows through the resistors R1 and R3 that are connected to the input terminal of the operational amplifier 110. Therefore, to suppress the discharge of the batteries BV1 to BV4 caused by this current, high resistances such as about several mega ohms each need to be used as the resistances respectively of the resistors R1 and R3. To highly precisely detect the voltages respectively of the batteries BV1 to BV4, the resistors R1 to R4 need to be those that each have a low voltage-dependent resistance value. When an integrated circuit using resistors that each have a high resistance value with low voltage dependency as above is manufactured, special process steps need to be provided and this results in increase of the cost thereof.


A mother board provided in a plural disk unit, which is formed with an interconnection pattern containing high speed control buses such as SCSI buses, is disposed at the central portion of a housing. A plurality of disk units capable of being removably inserted by plugging are directly mounted on the front side of the mother board through bus connectors, while connector units for external connection and having connectors of the control buses, terminal units having terminal circuits of the control buses, power units for supplying power to the disk units, and fan connectors having fans for cooling the interior of the housing are directly mounted on the back side of the mother board through connectors. Interconnections between the units are all contained in the interconnection pattern formed on the mother board. The entire plural disk unit is thus integrated.

1. Field of the Invention
The present invention relates to apparatus employing plural disk units, and particularly to a technology which is effectively applied to a mounting process or the like in a plural disk unit apparatus that includes a plurality of disk units controlled through a bus connection.
2. Description of the Related Art
In rotating external memories such as magnetic disk apparatus used for information processing systems, there is a continuing need for increased storage capacity and reliability, yet at a reduced cost. To meet such demands, a disk array (for example, as described in Pattersonc et al, "A Case for Redundant Arrays of Inexpensive Disks (RAID)", Report No. UCB/CSD 87/391, Computer Science Div., University of California, Berkeley, 1987) having a large capacity and highly reliable external memory has been devised, which is composed of a plurality of small rotating memories which are effectively integrated.
This plural disk unit has a limited disk unit-mounting density due to a load interval (interval between adjacent disk units connected to a small computer system integration (SCSI, or "scuzzy") control bus) problem. More concretely, the SCSI bus most commonly used for a plural disk unit must be designed so that the tap-off length from the bus line is shortened, to ensure a high-speed control bus signal; however, the tap-off length must be somewhat long so that the disk unit is connected to the SCSI bus by a single connector, but when the tap-off length is excessively long, data loss occurs because the pulse of a signal switched to high speed is disturbed by a reflected wave. In particular, the relationship between load interval and tap-off length is important; that is, the load interval must be sufficiently larger than the tap-off length.
There are at least two methods by which to satisfy the relationship between the load interval and tap-off length in high density mounting. One method shortens the tap-off length by providing two control bus connectors on each disk unit and connecting the individual disk units substantially in series to the control bus, and the other increases the load interval by connecting adjacent disk units one after another by means of a flat cable. The former method, however, is disadvantageous in that the provision of two connectors for each disk unit obstructs the high density mounting of the disk units and increases the cost. On the other hand, the latter method is disadvantageous in that connection between disk units one after another does not allow the connectors to be inserted and removed easily; hence, the disk units cannot by easily exchanged by plugging, thus reducing the maintainability of the apparatus.
The entire plural disk unit cannot be adequately miniaturized solely by integrating the disk units; miniaturization must include a general integration of disk units and peripheral units such as power supplies, cooling units, and the like. Furthermore, any attempt at miniaturization requires an effective plan to cool the plural disk unit because heat generation is concentrated for high-density disk units.
Another consideration in the design of a plural disk unit apparatus is the need for uninterruptible operation and high processing speed. To this end, attempts have been made to share a plural disk unit among a plurality of host computers, and to provide uninterruptible operation and uninterruptible maintenance of the plural disk unit itself.

Plural disk unit apparatus providing high-density mounting of disk units and peripheral units

Hitachi, Ltd. and Hitachi Information Technology Co., Ltd.


A multi-position valve assembly including a valve housing, a stator element and a rotor element rotatably mounted about a rotational axis. The valve assembly further includes a pressure adjustment assembly movable between a release position and a stop position, hard stopped relative to the valve housing. The pressure adjustment assembly includes a pressure adjuster device configured to movably cooperate between the rotor element and the valve housing to adjustably generate an axial compression pressure at the rotor-stator interface at a calibrated operating pressure, PC. When the pressure adjustment assembly is oriented in the release position, the axial compression pressure is substantially removed from the rotor-stator interface. In contrast, when the pressure adjustment assembly is oriented in the stop position, the axial compression pressure is substantially reproduced at the calibrated operating pressure, PC.

Current high pressure liquid chromatography shear valve systems typically employ a metallic stator element and a rotor device composed of a polymer material that forms fluid-tight seal at a rotor/stator interface therebetween. Depending upon the internal fluid pressures that these shear valve systems are designed to operate (typically 15 Kpsi or greater), as well as other environmental factors, these valves are typically capable of more than 15K, relatively maintenance free, cycles of use. Certain valve components, however, do wear over time such as the rotor seal and the stator seal. These valve components, fortunately, can be serviced or replaced, significantly extending the lifecycle of the valve.
Many multi-position, shear valve assemblies currently in use, including the next generation valve assembly 20 designs, shown in FIGS. 1-3, are typically rebuilt using the following technique. By simply removing the three socket head cap screws 21 that bolt the stator element 22 to the valve housing 25, the stator element 22 can be removed in order to access the rotor element 23. Using this technique, a service technician and/or end user can then easily replace both the rotor element and/or stator element. In this current valve configuration, loosening of the cap screws 21 is sufficient to simultaneously remove the sealing load (i.e., compression pressure) between the stator element 22 and the rotor element 23, at a rotor-stator interface, which is generated by a combination of a spring assembly 26 and a pressure adjuster nut 27 directly rotatably mounted to the valve housing 25.
Briefly, as shown in FIG. 2, as the pressure adjuster nut 27 is adjusted by rotating its head, relative to the valve housing 25, a distal portion of the pressure adjuster nut is axially advanced or retracted into contact with a proximal portion of the spring assembly 26. As the spring washers 28 of the spring assembly 26 are compressed, the generated compression force biases the rotor element into compressive contact with the stator element. When the valve is properly calibrated, via adjustment of the pressure adjusting nut 27, the rotor element 23 and the stator element 22 are sealed together at the interface in a fluid-tight manner to accommodate a selected fluid pressure flowing through the rotor channels and stator channels.
Accordingly, when the serviceable valve components are replaced, the stator screws 21 are reinserted and retightened. This requires tightening the stator screws 21 while simultaneously battling the compression force generated by the spring assembly 26 when the stator screws contact the stator element 22.
While this rebuild technique and valve design is satisfactory for the most part, several potential problems may be encountered during such field servicing unless the valve is field recalibrated; a procedure that significantly reduces an end users ability to self-rebuild the valve. For one, the pressure adjuster nut 27, at the proximal end of the shear valve assembly 20 could potentially be rotated, altering the factory "set" compression load. Furthermore, the end user may not properly tighten the stator screws 21 to the requisite torque requirements. In addition, since the stator element 22 is tightened against the rotor element 23, via the three stator screws 21, while a compression load is simultaneously generated at the rotor-stator interface via the spring assembly 26 and pressure adjuster nut 27, the stator element 22 may not properly seat flat and/or flush against a distal end edge of the stator ring 30. Due to any one of these variables, let alone in combination, the ability of the valve hold the required fluid pressure, at the interface, can greatly be affected.
Moreover, with the next generation ultra-high pressure, shear valve assemblies recently designed by Rheodyne (i.e., those capable of accommodating fluid pressures of 25 Kpsi or greater, and as shown in FIGS. 1-3), metallic stator elements and metallic rotor elements are applied, thus incorporating metal-on-metal sealing surfaces to improve durability and increase their lifecycle. With these metal-on-metal valves (disclosed in our U.S. Provisional Patent Application Ser. No. 61/225,143, filed Jul. 13, 2009, to Tower; 61/301,516, filed Feb. 4, 2010, to Tower; and 61/328,594, filed April, 2010, to Tower, all of which are entitled "ROTARY SHEAR VALVE ASSEMBLY WITH HARD-ON-HARD SEAL SURFACES", and all of which are incorporated by reference in their entirety), it has been observed that the proper amount of compression force being applied by the pressure adjuster nut is very critical. Another design challenge observed with these metal-on-metal sealing surfaces is that the perpendicularity (or flushness) of the stator element 22 to the rotor element 23 is also very important to maintain a fluid-tight sealing surface under high pressure fluid loads. Even slight surface variations on the order of only 0.005″ can cause the shear valve to hold thousands of PSI less than when new or can cause premature valve failure.
Accordingly, the ability to reproduce the factory set compression pressure, as well as the ability to assure a substantially flat seat of the stator element 22 to the distal end edge of the stator ring 30, during a valve rebuild, is highly desirable.

Rebuildable micro-fluidic valve assembly


A self-watering dish garden includes a lower container section which defines a liquid holding reservoir, an upper container section which fits on the lower container section and has an open top, and a tray which fits into the upper container section. The tray receives plant material in a growing medium and has a depth such that the bottom of the tray is above the top of the lower container section. The tray includes a supporting flange for supporting a partition which includes an outer rim and retaining members. At least one water absorbing member extends from the growing medium through the bottom of the tray into the liquid holding reservoir.

The present invention relates to a self-watering dish garden for plants, and relates more particularly to an inexpensive and efficient dish garden which is readily shippable in boxes.
Typical dish gardens today consist of a container usually made of a heavy ceramic material or perhaps a wicker basket with a thick plastic lining. These containers are relatively expensive and contribute to a large percentage of the cost of the dish garden.
Conventional dish gardens are watered from the top, because the nature of the container material, for example, ceramic or wicker basket lined with plastic, does not lend itself to bottom watering. There are many plants species, for example, African violets, in which bottom watering is greatly preferred. Top watering tends to result in overwatering of the plant, whereas bottom watering, if done properly, tends to provide sufficient moisture to the plant without the adverse effects of overwatering.
Another problem with conventional dish gardens and potted plants in general is the maintenance required. Generally, plants are watered periodically which means that one must be aware of when the plant was last watered and how much water the plant or plants require. Another problem with conventional dish gardens is that they are frequently assembled or arranged on site, and are transportable only with great care, for example, by hand-carrying. Conventionally arranged dish gardens are not adaptable to being shipped in boxes.
As is apparent from the foregoing, the problems of dish gardens relating to cost, bottom watering, ease of watering maintenance, and transportability, prior to the present invention, have not been solved. These problems, in turn, have led and can lead to both grower and customer dissatisfaction with dish gardens heretofore available.


Methods and apparatus for depositing material on a continuous substrate are provided herein. In some embodiments, an apparatus for processing a continuous substrate includes: a first chamber having a first volume; a second chamber having a second volume fluidly coupled to the first volume; and a plurality of process chambers, each having a process volume defining a processing path between the first chamber and the second chamber, wherein the process volume of each process chamber is fluidly coupled to each other, to the first volume, and to the second volume, and wherein the first chamber, the second chamber, and the plurality of process chambers are configured to process a continuous substrate that extends from the first chamber, through the plurality of process chambers, and to the second chamber.

Ceramic matrix composites (CMCs) are comprised of ceramic fibers embedded in a ceramic matrix. CMCs were developed to address limitations with conventional technical ceramics that prohibit use at high-temperatures and in oxidizing environments. Conventional unreinforced technical ceramics, including alumina, silicon carbide, aluminum nitride, silicon nitride, and zirconia, have low crack resistance and therefore fracture easily under mechanical and thermo-mechanical loading. These material limitations can be addressed by integrating multi-strand long ceramic fibers to enable greater elongation to rupture, fracture toughness, thermal shock resistance, and dynamic fatigue resistance.
Non-oxide polycrystalline ceramic fiber, typically silicon carbide (SiC) fiber, is used as continuous-length structural reinforcement in ceramic matrix composites (CMC). SiC-based ceramic fiber for CMC manufacture has small diameter, high thermal conductivity, low surface roughness, and a carbon-free surface. Furthermore, SiC-based ceramic fiber has high tensile strength as-produced, at high temperature, under high mechanical stress, as well as in oxidizing environments.
Chemical vapor infiltration (CVI) is used to produce an environmental barrier in the form of a thin conformal encapsulation layers on ceramic fibers. In general, the coated fiber has mechanical, thermal, and chemical advantages to un-coated fiber. Boron nitride (BN) and carbon-containing crack-deflecting interfacial coatings on SiC-based fiber surfaces improve SiC-based fiber oxidation resistance at high temperatures. Typically, barrier material such as boron nitride (BN) and carbon-containing crack-deflecting interfacial coatings are deposited on ceramic fibers in multiple sequential coating processes (i.e., one coating process for each layer) using individual deposition systems, separated by vacuum breaks for transfer of the ceramic fibers to each deposition system. However, depositing the coating in multiple sequential steps using individual deposition systems is time-consuming, costly, and inefficient.
Accordingly, the inventors have provided improved processing systems for depositing coatings on a continuous substrate, such as a tow material.

Methods and apparatus for depositing materials on a continuous substrate


A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of channel units for controlling the data transfer to and from the central processing unit and a plurality of control units for controlling the data transfer to and from the magnetic disk drive are independently connected to the cache units and the nonvolatile memory units through data buses and access lines.

The present invention relates to an external storage subsystem, and more particularly to a technology effective for an improvement of reliability of an external storage subsystem having a cache function.
For example, in a magnetic disk subsystem used as an external storage in a general purpose computer system, a well-known cache memory comprising a semi-conductor memory is interleaved at a portion of a disk controller to avoid as much as possible the reduction of a data transfer rate due to a mechanical factor such as a rotational delay time or a latency time in a magnetic disk drive.
A cache structure in such a disk controller is discussed in "A Multiport Page-Memory Architecture and A Multiport Disk-Cache System" New Generation Computing 2 (1984) 241-260 OHMSHA, LTD, and Springer-Verlag, in which it is proposed to improve an access performance to the cache by dividing into a plurality of memory banks. Further, a switching network called an interconnection network is proposed as a system for coupling the memory banks and a channel or a disk controller.
The conventional technology above intends to improve the cache performance by providing a plurality of memory banks and the switching network. As to a data bus structure in the disk controller, the switching network system called the interconnection network is proposed. However, the switching network system is imparted with a hardware restriction when a data bus configuration for exchanging data is to be constructed by connecting a plurality of memory banks and a plurality of channel units or a plurality of control units.
It does not refer to the multiplexity of the cache unit comprising the memory banks.