A slide-on multi-level basket useful for storing and transporting baked goods is provided which includes a floor and a pair of upstanding side walls configured for stacking identical baskets at three different levels and presenting structure enabling other, identical baskets to slide thereon into stacked or nested orientations. A multi-level basket hereof includes a slideway or rail extending along each of the side walls, the side walls being divided into inner and outer panels. Each basket includes a thin web and a wide web spaced apart and respectively proximate a front end wall and a rear end wall. The thick and thin webs are complimentarily configured with a relieved portion and a slot in each of the side walls whereby the webs can slide along the rail of a next lower, identical basket enabling the upper basket to drop into either a nested or stacked relationship according to the relative orientation of the two baskets, when superposed over the next lower, identical basket.

1. Field of the Invention
This invention concerns a slide-on multi-level basket especially useful for stacking or nesting at alternate heights for storing baked goods such as cake, buns, and bread loaves therein. The slide-on multi-level basket hereof is advantageously configured to receive a second, complimentarily configured basket thereon; enabling the second basket to slide onto the first basket so that the two can be stacked at a first or second level in superposed relationship.
2. Description of the Prior Art
It is now well-known in the operation of bakeries to provide a rigid supporting container or basket to protect baked goods from damage incident to handling and transport thereof. In most recent years, bakeries have produced a variety of different baked goods, such as loaves, cakes, and hamburger buns. Each of these products is conventionally produced in different product heights, resulting in the need to economically protect those goods while avoiding the necessity for having different baskets for each product.
As a result, there have been developed a number of different multi-level stacking baskets which are advantageously designed to stack or nest at different levels according to the height of the product contained therein. For example, a second basket could be superposed over a first basket at a first, lower level for hamburger buns, and at a second, upper level for loaves of bread. The availability of multi-level baskets has reduced the need for an increased inventory of specialty baskets for each product. Examples of different stacking baskets include those shown in the following: U.S. Pat. No. 3,387,740 to Bockenstette; U.S. Pat. No. 3,420,402 to Frater et al.; U.S. Pat. No. 3,392,875 to Bockenstette; U.S. Pat. No. 4,093,070 to Stahl; U.S. Pat. No. 4,106,623 to Carroll et al.; U.S. Pat. No. 4,106,624 to Thurman; U.S. Pat. No. 4,106,625 to Carroll et al.; U.S. Pat. No. 4,189,052 to Carroll et al.; U.S. Pat. No. 4,211,327 to Stahl et al.; U.S. Pat. No. 4,320,837 to Carroll et al.; U.S. Pat. No. 4,440,302 to Ehrman et al.; U.S. Pat. No. 4,426,001 to Stahl et al.; U.S. Pat. No. 4,520,928 to Wilson; U.S. Pat. No. 4,523,681 to Kreeger; U.S. Pat. No. 4,600,103 to Tabler; U.S. Pat. No. 4,601,393 to Veenman et al.; U.S. Pat. No. 4,619,366 to Kreeger; U.S. Pat. No. 4,643,310 to Deaton et al.; and U.S. Pat. No. 4,759,451 to Apps.
However, a difficulty inherent in those baskets able to nest or stack at alternate levels was their inability to alternately stack or nest without aligning the upper basket directly over the lower basket. Oftentimes, the baskets' configuration required that the user place the second basket immediately over the first basket for them to stack or nest. This presents a huge problem in practice, as stacks of baskets may often reach six to eight feet in height. Stacking or unstacking the baskets has proved difficult, especially for shorter people handling very tall stacks. It is to the solution of this and other problems to which the present invention is directed.


Provided are previously uncharacterised markers of cancers, for example colorectal cancers, and uses of these as diagnostic and prognostic markers of cancers, and in particular colorectal cancers. The markers are SEQ ID NO: 1—hnRNP-K; SEQ ID NO:2—HMG-1; SEQ ID NO:3—proteasome subunit alpha type 1; SEQ ID NO:4—bifunctional purine biosynthesis protein; SEQ ID NO:5—ST11; SEQ ID NO:6—annex in IV; SEQ ID NO:7—60 kDa heat shock protein; SEQ ID NO:8—T complex protein 1 beta subunit; SEQ ID NO:9—T complex protein 1 epsilon subunit; SEQ ID NO: 10—mortalin; and SEQ ID NO: 11—TER-ATPase. The invention further provides related methods and materials for the use of the markers in therapeutic intervention in colorectal and other cancers e.g. to specifically target neoplastic cells without causing significant toxicity in healthy tissues, and to provide methods for the evaluation of the ability of candidate therapeutic compounds to modulate the biological activity of cancerous cells from the colon, rectum and other tissues.

Cancer remains one of the leading causes of death in the Western world. Clinically, the treatment of human cancer currently involves the use of a broad variety of medical approaches, including surgery, radiation therapy and chemotherapeutic drug therapy (see, for example, the Oxford Textbook of Oncology, Souhami R L, Tannock I, Hohenberger P, and Horiot J-C (ed.s), 2nd edition, New York, N.Y., Oxford University Press, 2002).
A diverse group of chemotherapeutic agents are used in the treatment of human cancer, including the taxanes paclitaxel and docetaxel, the topoisomerase inhibitors etoposide, topotecan and irinotecan, the antimetabolites methotrexate, 5-fluorouracil, 5-fluorodeoxyuridine, 6-mercaptopurine, 6-thioguanine, cytosine arabinoside, 5-aza-cytidine and hydroxyurea; the alkylating agents cyclophosphamide, melphalan, busulfan, CCNU, MeCCNU, BCNU, streptozotocin, chlorambucil, bis-diamminedichloroplatinum, azetidinylbenzoquinone; the plant alkaloids vincristine, vinblastine, vindesine, and VM-26; the antibiotics actinomycin-D, doxorubicin, daunorubicin, mithramycin, mitomycin C and bleomycin; and miscellaneous agents such as dacarbazine, mAMSA and mitoxantrone. However, some neoplastic cells develop resistance to specific chemotherapeutic agents or even to multiple chemotherapeutic agents, and some tumours are intrinsically resistant to certain chemotherapeutic agents. Such drug resistance or multiple drug resistance can theoretically arise from expression of genes that confer resistance to the agent, or from lack of expression of genes that make the cells sensitive to a particular anticancer drug.
It is well established that certain pathological conditions, including cancer, are characterized by the abnormal expression of certain molecules, and these molecules thus serve as "markers" for a particular pathological condition.
Apart from their use as diagnostic "targets", i.e. abnormal components that can be identified to diagnose the pathological condition, the molecules serve as reagents which can be used to generate diagnostic and/or therapeutic agents. An example of this, which is not intended to be limiting, is the use of markers of cancer to produce antibodies specific to a particular marker. A further non-limiting example is the use of a peptide which complexes with an MHC molecule, to generate cytolytic T cells against cells expressing the marker.
One particular cancer target of interest is colorectal cancer. Colorectal cancers are the third most common malignancies in the world, and amongst men in the European Union it is the second most common cause of cancer death after lung cancer. Although more than 90% of cases are curable when diagnosed at an early stage in development, the majority of patients with colorectal cancer present clinically when the tumour is at an advanced, metastatic stage. Consequently, the disease kills around 98,500 people every year in the EU (where less than 50% of patients survive 5 years after an initial diagnosis of colorectal cancer) and an estimated 437,000 people per annum worldwide. This problem of late diagnosis is compounded by the resistance of some patients' tumours to currently available chemotherapy; leading to a failure to respond to treatment. Such patients require earlier detection and more successful treatment of their illness, and to this end it is desirable to identify proteins whose expression is associated with cancerous cells, which may serve as diagnostic markers, prognostic indicators and therapeutic targets.
Colorectal cancer is a consequence of pathologic transformation of normal cells of the colonic epithelium to an invasive cancer, and may result from inherited mutation, spontaneous mutation or exposure to carcinogens in the bowel contents. The majority of cancers of the colorectum are adenocarcinomas (Jass & Morson, J. Clin. Pathol. 40: 1016-23, 1987), but questions remain concerning the true origins of colorectal carcinomas. Such carcinomas may arise both from within existing benign neoplasms ("adenomas"), in what has been termed the adenoma to carcinoma sequence (Muto et al, Cancer 30: 2251-70, 1975), but the majority of adenomas do not appear to progress to carcinoma and indeed may even regress (Knoemschild, Surg. Forum XIV: 137-8, 1963). Alternatively carcinomas may arise de novo from areas of generalised dysplasia without an adenomatous stage. Clinical evidence supports the identification of environment, diet, age and sex as risk factors for colorectal cancer, but the lack of confirmed involvement of these factors in all cases suggests an underlying genetic basis for colorectal tumour formation. Several genetic alterations have been implicated in development of colorectal cancer, including mutations in tumour-suppressor genes, proto-oncogenes and DNA repair genes (reviewed by Robbins & Itzkowitz, Med Clin North Am 86:1467-95, 2002; Fearnhead et al, Br Med Bull 64: 27-43, 2002). For example, WO 0077252 identifies the Barx2 gene as a candidate tumour suppressor implicated in ovarian and colorectal cancer.
One of the earliest detectable events, which may be the initiating event in colorectal tumourigenesis, is inactivating mutation of both alleles of the adenomatous polyposis coli (APC) tumour suppressor gene. Other implicated genes include MCC, p53, DCC (deleted in colorectal carcinoma), and genes in the TGF-beta signalling pathway. Tumour specific patterns of expression have also been demonstrated for a number of proteins in colorectal tissues, and these proteins are undergoing evaluation as diagnostic and therapeutic targets. One such protein is carcinoembryonic antigen (CEA), which is detectable in the majority of colorectal cancers but not in normal tissues (reviewed by Hammarstrom, Semin Cancer Biol 9: 67-81, 1999). CEA is immunologically detectable in the serum of colorectal cancer patients, and detection of CEA mRNA by RT-PCR can identify lymph node micrometastases, which are a prognostic indicator of a reduced chance of survival in colorectal cancers (Liefers et al, New England J. of Med. 339: 223-8, 1998). Another promising marker for colorectal cancer is minichromosome maintenance protein 2 (MCM2), which is being developed as a target for diagnosis from stool samples (Davies et al, Lancet 359: 1917-9, 2002).
At the present time, none of the protein markers under investigation are in routine clinical use, and further targets for diagnosis, prognosis and treatment are desirable. The current routine diagnostic test for colorectal cancer is the FOBT (Faecal Occult Blood Test), which is lacking in sensitivity and specificity. Evaluation of the effectiveness of this test indicates that it may fail to detect as many as 76% of suspicious growths (Lieberman et al, N Engl J Med; 345: 555-60, 2001). It also results in a large number of false positives and these patients require to undergo the unpleasant, invasive procedure of colonoscopy. Even when administered together these two procedures have been found to miss 24% of tumours and precancerous polyps. Currently the best candidates for new diagnostic tests are based on DNA analysis, but these have at best a 50% detection rate.
It will be appreciated from the forgoing that the provision of novel specific, reliable markers that are differentially expressed in normal and transformed tissues (such as colorectal tissue) would provide a useful contribution to the art. Such markers could be used inter alia in the diagnosis of cancers such as colorectal cancer, the prediction of the onset of cancers such as colorectal cancer, or the treatment of cancers such as colorectal cancer.

Mitochondrial stress-70 protein markers for colorectal cancer

The University Court of the University of Aberdeen

Grampian Health Board (AKA NHS Grampian)


A storage system accesses a storage device according to the host I/O request and internal I/O request for preventing a time out error of the host I/O due to a stagnation of command processing. The command processing section performs system load management, where the host I/O requests which are not managed by the storage system are managed according to the system load of the storage system, and for the host I/O requests which exceed the system load, the host I/O request is not processed but an error is replied, and the host retries the command to suppress the stagnation of command processing in the system.

1. Field of the Invention
The present invention relates to a storage system which inputs/outputs data using such a storage device as a magnetic disk, and dynamic load management method thereof, and more particularly to a storage system for preventing the stagnation of command processing by managing the processing amount of input/output commands and dynamic load management method thereof.
2. Description of the Related Art
In a storage device using such a storage medium as a magnetic disk, magneto-optical disk and optical disk, the storage medium is actually accessed by the request of a data processing apparatus. When the data processing apparatus uses large capacity data, a storage system comprising a plurality of storage device and a control device is used.
Such a storage system has a DTC (Dynamic Traffic Control) function which dynamically optimizes resource allocation in the system for a large volume of access, so as to implement stable performance for the access from the host device. FIG. 19 is a block diagram of a prior art, and FIG. 20 is a diagram describing the prior art.
As FIG. 19 shows, the storage controller 100 controls access to a plurality of storage devices (magnetic disk devices) 110 according to the host I/O commands. This storage controller 100 has a command processing function 102, DTC function 104, disk driver 106 and device adaptor 108. The command processing function 102 receives the host I/O command and the internal I/O command.
The internal I/O command is a command for I/O control which is executed in the background of the host I/O, and examples are OPC (One Point Copy), which-sequentially copies in the background of the host I/O according to the copy instruction of the continuous block group of the host, rebuilding RAID, and copy back for data backup.
The DTC function 104 controls the number of commands to be issued to the storage device 110 via the driver 106 and the device adaptor 108. As FIG. 20 shows, according to the prior art, the DTC function 104 measures the response time of each command (time from when the command is issued to the storage device 110 to when the response is received from the storage device 110), calculates the average of the response time, and increases the number of issued commands in unit time if this average response time is quicker than a predetermined time, or decreases the number of issued commands in unit time if the average response time is slower than a predetermined time. The commands exceeding the determined number of issued commands are held in a queue.
The command processing function 102 processes the host I/O (random, sequential) with priority, without restrictions in acceptance, and transfers it to the DTC 104. The internal I/O is processed in the background of the host I/O, and is transferred to the DTC 104. The DTC 104 issues the number of commands, which does not exceed a predetermined number of issued commands, to the storage device 110 via the driver 106 and the device adaptor 108.
In this way, the DTC 104 dynamically changes the number of startup (number of commands) according to the response time of the storage device 110, so as to optimize the execution of the I/O commands.
Since all host I/Os are accepted in the prior art, if host I/Os beyond system performance are accepted, the host I/Os cannot be executed within the internal time out time (e.g. 25 seconds), and a time out is replied to the host. Therefore the execution wait time of I/O request for host becomes long, and the host must issue the host I/O again according to the time out.
Also an internal I/O, such as OPC, may wait in the DTC 104 while having an exclusion right (called Extent exclusion) of the internal buffer area in the command processing section 102, and if this happens, the next host I/O command cannot acquire Extent exclusion and sleeps, and in the worse case an internal time out occurs.
Also the conventional DTC determines a new number of startup only by the response time from the storage device (disk device) in the past, so if a response from the disk device temporarily delays, an issue of a new command to the disk device is restricted more than necessary, which makes it difficult to fully use the performance of the storage device.

Storage system and dynamic load management method thereof


The row decoder receives writing instruction signal and reading instruction signal to selectively activate one of the word lines according to an input state of row address signals. The data buffer receives a data input signal when the writing instruction signal is received, and drives corresponding one of the bit lines and amplifies a minute reading signal transmitted to one of the bit lines to output a data output signal when the reading instruction signal is received.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that can electrically read data or write data.
2. Description of the Related Art
Some of conventional semiconductor integrated circuits include one-time programmable memory (OTP memory) having relatively small capacity between several Kbits and tens of Kbits. Such an OTP memory is used for various applications such as storing information relating to a semiconductor memory device, a highly-integrated logic circuit, or a high-precision analog circuit formed together on the same chip (the information stored therein includes defect relief information, manufacturing information, adjustment information of circuit characteristics, individual chip intrinsic number, and the like).
As OTP memory employed in the above use, an OTP memory of gate-insulation film destruction type is known (for example, refer to JP2008-171477A). This OTP memory stores information based on whether a gate insulation film of a MOS transistor included in the memory cell is destroyed or not. That is, this memory cell stores "0" data in a state before the gate insulation film of the MOS transistor is destroyed (a high resistance state) while it stores "1" data in a state after the gate insulation film is destroyed (a low resistance state). Based on the electric property before and after the writing, the nonvolatile memory cell of the gate-insulation film destruction type is called an "antifuse element".
This gate-insulation film destruction type antifuse element has the same structure as a normal MOS transistor used in other integrated circuits formed together on the same chip. Thus, a special process is not required to be added to the manufacturing process. Moreover, the production cost is low. Furthermore, since it is characterized in that it does not need any additional production step, it does not suffer from any deterioration of properties of major semiconductor elements mounted in combination on the same chip, such as fine-patterned memory elements for large capacity storage, high-speed transistors contained in high-speed logic circuits, and transistors for analog circuits exhibiting a high-precision electrical property. With these excellent characteristics, the antifuse element may be referred to as an optimal nonvolatile memory element for the above use.
However, there is another problem that must be solved for the use of the antifuse element of the gate-insulation-film destruction type. The problem is caused by a method for storing information used in the antifuse element of the gate-insulation-film destruction type. The method includes a step of destroying the device by applying a high voltage. In general, destruction of the gate insulation film creates a pinhole having a diameter of about 50 nm. However, it is difficult to control a position where the pinhole is created, and a shape thereof. For example, when a pinhole is created in the vicinity of a center of a channel of the transistor, a read current is small in comparison with the case that the pinhole is created in the vicinity of a source or a drain. This can be a cause of false reading of data stored in a memory cell.
As countermeasures of this problem, the channel length of the MOS transistor may be shortened, or amount of overlap between the source/drain diffusion regions and the gate electrode may be increased. But none of these countermeasures are enough for solving the problem. Moreover, a state of the gate insulation film after destruction tends to be unstable.
For example, when destruction of the gate insulation film is not enough, a current at the time of the reading becomes extremely small, or a large reading current is provided at an initial state, but it the current decreases rapidly as the time lapses.
In contrast, when the gate insulation film is destroyed excessively, a crystal structure of silicon just beneath the gate insulation film or a junction structure of the silicon may also be destroyed. This causes a decrease of the read current, and generation of an abnormal leak current. This is regarded as a problem. As a countermeasure for the problem, write a current flowing in the antifuse element after the destruction of the gate insulation film may be controlled. This countermeasure is not enough for solving the problem, either.
In this way, a conventional antifuse element of the gate-insulation-film destruction type does not fully solve a problem about false reading due to the information-storing method thereof.

Non-volatile semiconductor memory device

Abstract: The power supply circuit supplies a certain voltage to the memory cell, and in response to the reading instruction signal, keeps the voltage at a ground potential.


A method for dynamically configuring a video stream, including: identifying player control metadata attributes for an input video stream, wherein the input video stream is received from an origin server; storing the identified metadata attributes to a memory device; and dynamically inserting the metadata attributes into an output video stream in real-time.

When video content is streamed to a client device over a remote connection—whether over a network connection, an Internet connection or otherwise—the video stream may require optimization to allow for continuous playback over the connection due to bandwidth, hardware, or other limitations. Content providers frequently provide their own media player on which the video stream is to be played, for example, in a flash player for a web browser. The media player is generally downloaded with the video stream and the video stream is played back at the client device on the media player.
Because the content providers often provide their own media player, the original video stream from the origin server may include attributes or customization for the video stream that allows the video stream to interact correctly with the media player and take advantage of the media player's specific functionalities. Optimization or re-encoding of the video stream in real time over a connection may cause problems with playback of the video at the client device because the optimization may remove or alter the player control attributes, leading to serious usability problems or a poor user experience.

Dynamic injection of metadata into flash video


A flicker detecting method for an image capturing device includes acquiring a first image, wherein pixel values of each row in the first image are acquired during a first period; acquiring a second image, wherein pixel values of each row in the second image are acquired during a second period; generating a third image according to the first image and the second image; and detecting flickers according to the third image; wherein the first period is different from the second period.

1. Field of the Invention
The present invention relates to a flicker detecting method for an image capturing device, and more particularly, to a flicker detecting method capable of detecting flickers in an image without being interfered by the image contents.
2. Description of the Prior Art
With advances of digital camera modules, almost all the electronic devices such as cell phones, tablets and personal digital assistants are now equipped with image capturing functions. When the electronic device captures images or videos under a fluorescent lamp, the flickers may exist in the captured images or videos due to the effects of alternating current provided to the fluorescent lamp.
Generally, the flickers in the images are detected via determining whether flicker patterns exist in the images. However, the searching of flicker patterns is easy to be interfered by the image contents. The accuracy of detecting the flicker is therefore downgraded. Thus, how to detect the flickers with a high accuracy becomes a topic to be discussed.

Flicker detecting method for image capturing device


Block copolymers comprising activated aromatic ether or thioether repeat units having utility as molding resins are prepared by contacting polymers comprising different activated aromatic ether or thioether repeat units in the presence of an exchange catalyst.

This invention relates to polyether copolymers. More particularly, the invention relates to poly(aryl ether/thioether) segmented block copolymers and to the preparation of such segmented block copolymers.
Poly(aryl ethers/thioethers) are well-known resinous materials for which there are numerous commercial applications. They have good thermal and mechanical characteristics, and exhibit a wide range of other physical properties. Poly(aryl ethers/thioethers) may be categorized as amorphous or crystalline. The crystalline polymers are exceptionally chemically resistant, costly, generally insoluble in common organic solvents, and have generally low glass transition temperatures which limits their use temperatures. By contrast, the commercially available amorphous poly(aryl ether/thioethers) generally have higher glass transition temperatures and are less costly, but are also less resistant to organic solvents.
Attempts to modify the properties of poly(aryl ether/thioether) resins by blending with other polymeric materials are quite often unsatisfactory because of the incompatibility of the poly(aryl ether/thioethers) with other resinous materials. To overcome this problem, it has been proposed to polymerize one poly(aryl ether/thioether) with other poly(aryl ethers/thioethers) in order to produce poly(aryl ether/thioether) segmented block copolymers. For example, the desirable characteristics of poly(aryl ether ketones) and poly(aryl ether sulfones), e.g., solvent resistance and high glass transition temperature (T.sub.g), may be achieved by preparing a poly(aryl ether) segmented block copolymer containing both chemical groups.
Methods for preparing random poly(aryl ether) copolymers are known. Poly(ether ketone) and poly(ether sulfone) have been copolymerized by a displacement reaction, utilizing a diaryl sulfone solvent, as disclosed in "Synthesis and Properties of Polyaryletherketones", T. E. Attwood, et al., Polymer, 22, 1096 (1981). However, attempts to prepare block copolymers were unsuccessful. In "Synthesis and Characterization of Poly(Arylene Ether Ketone Sulfone) Copolymers", S. D. Wu, et al., J. Am. Chem. Soc. Polymer Prep. 227, Vol (26)2 (1985), two processes were disclosed. The first combined poly(aryl sulfone) oligomers with difluorobenzophenone monomers in an N-methyl-2-pyrrolidinone solvent, to prepare a poly(aryl ether ketone sulfone) alternating copolymer. The article described this process as simple "chain extension". The poly(aryl sulfone) oligomers were subject to ether exchange, resulting in randomization of the copolymer. The second process produced alternating copolymers from difluorobenzophenone and chlorophenylsulfone monomers, reacted together in a diphenyl sulfone solvent. Likewise, ether interchange promoted randomization of the copolymer.

Preparation of poly(arylether/thioether) segmented block copolymers


A coin recycling machine (10) for receiving, sorting and dispensing coins, comprising a coin dispenser having a rotatable coin magazine (23) for holding respective denominations of coins and having an electronic control (100, 107), said electronic control (100, 107) being operable in response to a commanded total to control position of said coin magazine (23) to selectively dispense coins to provide the commanded total, a queuing device (52) for receiving the coins and arranging the coins in a queue, the queuing device (52) having an exit (66) directed towards said coin magazine (23) and having associated sensors (65, 72) for identifying a denomination of a next coin to pass through the exit (66) and the electronic control being responsive to the sensors (65, 72) associated with the queuing device for positioning the coin magazine such that coins are sorted into the coin magazine (23) by denomination as the coins exit the queuing device (52).

The invention relates to coin dispensers, and in particular to coin dispensers of the type for dispensing change. Such coin change dispensers are found, for example, at cashier checkout locations and ticket booths and many other places.
Perhaps the best known type of coin change dispenser has an in-line configuration in which a plurality of generally upright coin holding tubes are aligned in a row. Examples of such coin change dispensers are shown, for example, in Walton, U.S. Pat. No. 3,590,833 and Duplessy, U.S. Pat. No. 4,593,709.
Such dispensers are assembled from numerous small, mechanical parts requiring many machining operations during manufacture, especially the parts of the coin ejector mechanisms. A coin dispenser having nine coin tubes would typically provide nine coin ejector mechanisms and each of these would include many small parts.
An additional problem in the art is the need to replenish the dispenser during the work shift. This requires reloading coinage and performing cash settlement operations in a back room to account for the coinage being dispensed and the coinage being received at a cash register.
Several patent documents have disclosed machines to receive, sort and dispense coins. In a published European patent application EP 0 137 637 published Apr. 17, 1985, coins are sorted into four tubes, from which coins may be dispensed. Generally, this is a large apparatus, resembling the in-line coin dispensers described above, and further having a ramp of complex design and many additional mechanical parts. Four tubes are disclosed for sorting and dispensing of more than four denominations. To handle additional denominations, more coin tubes and still more internal parts would have to be included.
On the other hand, there are some lightweight devices which combine sorting and dispensing as disclosed in U.S. Pat. No. 5,106,337 and U.S. Des. Pat. No. 324,600. It appears that these devices would not handle the full coin set of any country without being enlarged. It is not clear that they would work well with a larger number of coin tubes or withstand heavy commercial use.
There is a need for a coin recycling dispenser that would receive, sort and dispense coins for a full coin set in busy cash handling locations. For global marketability, such a machine should be adaptable to the coin sets of many countries. Such a unit should have a relatively simple construction, and provide a lower manufacturing cost, and also be relatively compact in size.


A device for winding elongate flexible objects is disclosed herein. The device includes a rigid member extending along a central axis between first and second ends. The device also includes a first fork having a base mounted to the rigid member at the first end of the rigid member and a plurality of tines supported on the base. The device also includes a second fork member having a base mounted to the rigid member at the second end of the rigid member and a plurality of tines supported on the base. The first fork and the second fork are further defined as both being removably engaged with the rigid member.

1. Field of the Invention
The invention relates to a device for winding elongate flexible objects such as electrical power cords.
2. Description of Related Prior Art
U.S. Pat. No. 5,348,240 discloses a DEVICE FOR WINDING AND STORAGE OF CORDS. The storage device for electrical extension cords includes a substantially elongated hollow tubular member having hollow end caps at either end from which extend winding arms. The winding arms are adapted to have an electrical extension cord or the like wrapped around them to form a coil of wire along the elongated body member between the arms. At one end of the first end member there is a rotatable hook for mounting the entire assembly including an extension cord. Along the body of the elongated member are two clamps for holding the plugs at either end of the extension cord in place. The plug clamps are movable longitudinally along the body of the elongated member to allow for adjustment for different lengths of extension cord. A tubular extension member is partially mounted internally of the elongated member such that it may move in or out of the body of the elongated member to form an adjustable support for positioning against the ground during winding. When not in use, the extension member may be substantially entirely positioned within the elongated member.

Device for winding elongate flexible objects


According to one embodiment of the invention, a technique is provided for facilitating the relocation of data from a source page to a destination page in a computing system in which I/O devices may conduct DVMA transactions via an IOMMU. Before the relocation, it is determined whether any devices potentially are accessing the source page. If it is determined that a device potentially is accessing the source page, then the IOMMU's device driver (“bus nexus”) “suspends” the bus. The bus nexus allows any pending memory transactions to finish. While the bus is suspended, the kernel moves the contents of the source page to the destination page. After the kernel has moved the contents, the IOMMU's TLB is updated so that the virtual address that was mapped to the source page's physical address is mapped to the destination page's physical address. The bus nexus “unsuspends” the bus.

The physical memory of a computing system is usually divided into physical pages. Each physical page is the same size in bytes. For example, in some computing systems, each physical page is 8192 bytes long. Each physical page has a unique page frame number (PFN). A physical page's PFN may be determined by dividing the starting physical memory address of that physical page by the page size. Thus, in a system in which each physical page contains 8192 bytes, the PFN of a physical page that contains physical memory addresses 0 through 8191 is 0, the PFN of a physical page that contains physical memory addresses 8192 through 16383 is 1, and the PFN of a physical page that contains physical memory address 16384 through 24575 is 2.
In many computing systems that employ a virtual memory management scheme, virtual memory address space is segregated into "user" virtual memory address space and "kernel" virtual memory address space. Each executing user process has its own user virtual memory address space. The system kernel has its own kernel virtual memory address space. Some physical pages are mapped into the user virtual memory address space, and some physical pages are mapped into the kernel virtual memory address space. Inasmuch as multiple user processes may share the same data, some of the virtual memory address space of each of two or more user process may be mapped to the same physical pages. In fact, a physical page that is mapped to user virtual memory address space may be concurrently mapped to kernel virtual memory address space, at least temporarily.
Each physical-to-virtual page mapping has a corresponding entry in a Translation Lookaside Buffer (TLB), which is typically implemented in hardware. Usually, when a process attempts to access data at a particular virtual address, it invokes a mechanism called the virtual memory subsystem. The virtual memory subsystem is typically a part of the operating system.
The virtual memory subsystem first attempts to find the relevant virtual-to-physical page mapping in the TLB, using the virtual address as a key. If the virtual memory subsystem cannot find a relevant, valid mapping in the TLB (a circumstance called a "TLB miss"), then the virtual memory subsystem attempts to find a relevant, valid mapping in a Translation Storage Buffer (TSB), which is similar in structure to the TLB, but larger and slower, and typically implemented in software. If the virtual memory subsystem cannot find a relevant, valid mapping in the TSB (a circumstance called a "TSB miss"), then the virtual memory subsystem attempts to find a relevant, valid mapping in "page tables," which are implemented as hash tables. If the virtual memory subsystem cannot find a relevant, valid mapping in the page tables (a circumstance called a "page fault"), then the virtual memory subsystem invokes a mechanism called the "page fault handler." The page fault handler locates a relevant, valid mapping using information within kernel internal tables, which may refer to persistent storage. Significantly, the kernel internal tables are stored in physical pages that are mapped to the kernel virtual memory address space.
A computing system may comprise multiple system boards. Each system board may comprise one or more CPUs and some physical memory. Each system board has a different range of physical memory addresses that does not overlap with any other system board's range of physical memory addresses.
Sometimes, a particular system board may be experiencing errors. Under such circumstances, it may be desirable to remove that system board from the computing system.
A large computing system may be logically divided into multiple separate domains. Each domain may be allocated one or more system boards. Each domain may be used by a different group of users for different purposes. For example, one domain might be used to run a web server. Another domain might be used to run a database.
At some point in time, it may become desirable to change the allocation of system boards to domains. Under some circumstances, it might be desirable to change the allocation on a regular basis (e.g., daily), automatically and dynamically. It is better for such reallocation to be performed with minimum disruption to the computing system and the processes executing thereon. For example, it is better for such reallocation to be performed without shutting down and rebooting the entire computing system, because rebooting the entire computing system can be a relatively time-consuming process. Usually, user processes cannot execute during much of the time that a computing system is rebooting.
Whenever a system board is going to be removed from a computing system, or whenever a system board is going to be allocated to a different domain, the data stored in that system board's physical pages needs to be relocated to the physical pages of another system board. Relocation involves moving the data that is stored in one set of physical pages to another set of physical pages.
When a user process' data need to be relocated, the data may be moved from the "source" physical pages to other "target" physical pages that have different PFNs. Before the data are moved, all entries (in the TSB, the TLB, and the page tables) that contain physical-to-virtual page mappings that correspond to the "source" physical pages are marked "invalid" so that no processes will be able to access the "source" physical pages during the relocation. The relevant physical-to-virtual page mappings are modified so that the appropriate "target" physical pages, to which the data have been moved, are mapped to the same virtual pages to which the "source" physical pages were mapped. The modified mappings are stored in the TLB, the TSB, and the page tables, and the entries containing the modified mappings are marked "valid." The user process continues to access its data using the same virtual addresses.
According to current approaches, a page fault handler is not invoked in response to a page fault that involves a mapping of a physical page to the kernel virtual memory address space. This is because the kernel internal tables that contain the mapping for which the page fault handler would be searching are stored in a physical page that is, itself, mapped to the kernel virtual memory address space. If the contents of that physical page were currently being relocated, then the virtual memory subsystem would not be able to locate a valid virtual-to-physical page mapping for that physical page in the TLB, the TSB, or the page tables; all of the entries containing that mapping would have been invalidated due to the relocation. An unending recursive cascade of page faults and page fault handler invocations would likely result, causing the entire computing system to fail.
Because a page fault handler is not invoked in response to a page fault that involves a mapping of a physical page to a virtual page that is in the kernel virtual memory address space, under current approaches, physical pages that are mapped to the kernel's virtual memory address space can only be relocated through a firmware-implemented technique.
Under the aforementioned firmware-implemented technique, all of the user processes executing in the computing system are quiesced (i.e., placed in a "suspended" state). Then, for each driver in the computing system, a "suspend entry point" for that driver is called. As a result, all of the drivers are quiesced as well. Then, all of the CPUs in the computing system, except for one CPU on a system board other than the "source" system board, are quiesced. Then the firmware of the one CPU that was not quiesced reads data from the "source" physical pages of the "source" system board and stores that data in the previously unoccupied "target" physical pages of a "target" system board. The firmware configures the physical memory addresses on the "target" system board to be the same as the physical memory addresses on the "source" system board. After the data has been copied from the "source" system board to the "target" system board, the "source" system board is removed from the computing system, the quiesced CPUs are resumed, the quiesced drivers are resumed, and the quiesced user processes are resumed.
When using the firmware-implemented relocation technique, the physical memory addresses on the "target" system board need to be the same as those on the "source" system board because, as is discussed above, it is not safe to invoke a page fault handler in response to a page fault that involves a mapping of a physical page to the kernel virtual memory address space. Therefore, under current approaches, all physical addresses that could be referenced by kernel processes need to remain the same throughout the relocation. This need makes it impractical for kernel virtual memory address space-mapped physical pages (hereinafter referred to as "kernel pages") to be spread throughout all of the system boards in a computing system.
For example, if kernel pages were distributed among all "N" of the system boards of a computing system, then relocating the data stored in those kernel pages would require an additional "N" more "target" system boards. The physical memory addresses on a given system board are required to be contiguous, so it is not possible, using the firmware-implemented technique, to move data from "N" "source" system boards onto fewer than "N" "target" system boards; at least "N" "target" system boards are required. However, it is usually not economically feasible to keep such a potentially large number of unused spare "target" system boards available.
According to one approach, sparsely populated system boards can be made into spare "target" system boards by moving user process data off of those system boards to other, more densely populated system boards. However, even this approach does not completely obviate the need to maintain all kernel pages within a limited subset of system boards.
Consequently, under current approaches, all of the kernel pages are confined to a limited subset of all of the system boards in a computing system, to compensate for the possibility that one or more of the system boards in that subset might be replaced at some point in time.
This confinement of kernel pages to a limited subset of all of the system boards has some negative consequences. Thousands of user processes might be concurrently executing on various system boards. At any given moment, many of these user processes may cause accesses to the kernel pages (e.g., as a result of page faults). Because all of the kernel pages are located on the same limited subset of system boards under current approaches, the input/output resources of the system boards in the limited subset are often subject to heavy contention. The overall performance of the entire computing system may be degraded as a result.
In order to reduce the contention on a limited subset of system boards, and thereby enhance overall computing system performance, techniques are needed for allowing kernel pages to be distributed among any or all of the system boards in a computing system.
One of the more difficult cases to consider when one desires to relocate kernel pages is the case in which kernel pages are being accessed via an "Input/Output Memory Management Unit," or "IOMMU," in a computing system that supports "Direct Virtual Memory Access," or "DVMA." In such systems, an IOMMU typically resides on a "host bridge chip" that sits between input/output (I/O) devices and physical memory. The I/O devices send virtual addresses to the IOMMU, which translates the virtual addresses into corresponding physical addresses. In such systems, for various reasons, the IOMMU typically cannot handle page faults correctly.
Therefore, previously, in such systems, the IOMMU needed to have access to valid virtual-to-physical translations at any time that a device attempted to access memory using DVMA. As matters previously stood, kernel pages could not be relocated while an I/O device was reading from or writing to those kernel pages using DVMA, because if a kernel page was being relocated at the time that an I/O device attempted to access that kernel page using DVMA, a fatal page fault might result.
Theoretically, one could attempt to solve the problem by mandating that all writers of device drivers everywhere must adapt their device drivers so that no device drivers would ever allow their corresponding I/O devices to perform DVMA relative to a kernel page that was being relocated. However, writers of device drivers would probably resist such a mandate, especially because platforms that allow DVMA might be a relatively insubstantial fraction of all platforms for which the writers produce the device drivers. In response to such a mandate, writers of device drivers might simply stop formally supporting the computing systems in which DVMA was performed. Additionally, some I/O devices might be so old that nobody is writing device drivers for those I/O devices anymore. Even if the mandate were uniformly followed, users of the computing systems would be burdened with the task of updating all of their device drivers.


An underwater tunnel system for vehicular traffic flow, including rail, automobile and truck traffic connecting the shores of opposed land masses separated by a body of water draws heavily from submarine, manufacturing and modular construction technology. It is environmentally benign and will not adversely dominate the skyline of the surrounding region. The system of the invention requires minimal, if any, dredging to insure its substantially level installation. A compensating ducting and valve system is utilized for initial tunnel submergence during construction and to provide dynamic stability subsequently during operation. Part of the ducting system utilized during submergence operations is also subsequently used for ventilation airflow throughout the tunnel system during operation. During operation, fresh air is introduced from both shores into the tunnel system and exhaust air may be selectively discharged at both shores or from the tunnel system at a location distant from both shores.

1. Field of the Invention
This invention relates generally to an underwater tunnel system for vehicular traffic flow, including rail, automobile and truck traffic and, more specifically, to a submerged floating tunnel system of modular construction which utilizes submarine technology to provide specific and adjustable buoyancy capabilities.
2. Description of the Prior Art
The prior art, comprising known or existing techniques for connecting two land masses, includes bridges and tunnels.
As a means of traversing a body of water between two land masses, bridge construction presents several major problems. Because bridge construction is performed substantially (about 95%) on site, delays and cost overruns are common, being subject to seasonal changes and inclement weather. In addition, the average construction time (including design) of a conventional bridge is five to seven years. Once in place, conventional bridges possess several characteristics which also present difficulty. Exposure to weather and the elements requires constant examination and continuous maintenance efforts. In addition, the same weather factors which hinder construction and shorten the life span of the resulting structure also adversely affect traffic conditions. Finally, conventional bridges can have significant environmental impact as well as degrading the scenery or skyline of the surrounding land mass areas.
Currently, underwater tunnels also contain serious flaws and weaknesses in both their design and technique of construction. Conventional tunnels require extensive boring beneath the seabed, riverbed, or the like. This is a process which results in both substantially lengthening the construction period and substantially increasing costs. Furthermore, the extensive boring required in the construction of conventional tunnels also can have negative effects on the surrounding marine environment.
While submerged and prefabricated tunnels already exist, these systems are not without flaws. Through this invention, both existing tunnel technology and design will be improved upon substantially. Presently, submerged tunnels utilize concrete tubes which, although about 60% prefabricated, require substantial on-site work. The prefabricated tubes used in concrete tunnels employ relatively short 300 foot sections. In order to build and install a concrete submerged tunnel on the floor of the body of water being traversed, additional concrete pours (above the waterline) are required to create the negative buoyancy necessary to submerge and lower these tube sections under the control of barge cranes. Extensive dredging is also required in order to produce the level of prescribed foundation to effectively join these tube sections together.
Finally, and most importantly, once a concrete tunnel of known design, is permanently weighted down with additional concrete in order to overcome positive buoyancy, repairs to the tunnel become difficult. Due to the permanent nature of the structure, maintenance and repair work can only be accomplished on site and underwater.
Numerous patents exist which are representative of a variety of fields of invention which must be considered when considering solutions to the problem being addressed by the inventors.
For example, U.S. Pat. No. 3,849,821 issued Nov. 26, 1974 to Arild et al. and No. 3,478,521 issued Nov. 18, 1969 to Petrik, disclose submerged tunnel bridges assembled underwater from prefabricated concrete modules.
U.S. Pat. No. 4,406,151 issued Sep. 27, 1983 to Simonsen et al., No. 4,165,196 issued Aug. 21, 1979 to Serrano, and No. 3,893,304 issued Jul. 8, 1975 to Pochitaloff-Huvale all disclose the fabrication of underwater structures.
U.S. Pat. No. 5,362,921 issued Nov. 8, 1994 to Birkelund et al., No. 4,892,442 issued Jan. 9, 1990 to Shoffher, No. 2,770,950 issued Nov. 20, 1956 to Collins, and No. 244,752 issued Jul. 26, 1881 to Hunter et al. all disclose various underwater cable constructions and techniques for their installation.
Numerous U.S. patents disclose the laying of underwater pipeline, of which the following are exemplary:
______________________________________ U.S. Pat. No. Inventor(s) Issue Date ______________________________________ 5,044,825 Kaldenback 09/03/91 4,778,306 Anselmi et al. 10/18/88 4,712,946 Greatorex 12/15/87 4,465,400 Adams 08/14/84 4,459,065 Morton 07/10/84 4,360,290 Ward 11/23/82 4,183,697 Lamy 01/15/80 4,120,168 Lamy 10/17/78 4,028,903 Dietrich 06/14/77 3,977,201 Bittner 08/31/76 3,835,656 McDermott 09/17/74 3,568,456 VanLoenen 03/09/71 3,479,831 Teague, Jr. 11/25/69 3,425,453 Fuller 02/04/69 3,086,369 Brown 04/23/63 1,946,389 Christiansen 03/06/34 612,485 Conover 10/18/1898 ______________________________________
In a similar fashion, the following U.S. patents disclose methods and apparatus for joining pipe sections underwater:
______________________________________ U.S. Pat. No. Inventor(s) Issue Date ______________________________________ 5,004,017 White 04/02/91 4,832,530 Anderson, et al. 05/23/89 4,468,155 Levallois et al. 08/28/84 4,171,175 Nobileau et al. 10/16/79 4,076,130 sumner 02/28/78 3,795,115 Bergquist et al. 03/05/74 375,464 Thacher et al. 12/27/1887 ______________________________________
It was in light of the foregoing and the inventors' expertise in submarine construction and design that the present invention was conceived and has now been reduced to practice.


An object of the present invention is to provide an automatic analysis method and an automatic analyzer which are suitable for improving throughput by changing reagents during analysis without placing a load on an operator, and without stopping the analysis. There is provided an automatic analysis method comprising the steps of: while moving a reagent transfer mechanism with respect to a reagent pipettor, dispensing a reagent placed in the reagent transfer mechanism by use of the reagent pipettor to cause a sample to react with the dispensed reagent; and measuring the reacted sample so as to analyze specified analysis items of the sample. A reagent is transferred from a reagent storage unit to a reagent changing mechanism. Then, the reagent changing mechanism is moved in synchronization with the reagent transfer mechanism so that reagents are changed during the synchronization.

1. Field of the Invention
The present invention relates to an automatic analyzer for performing qualitative/quantitative analysis of a biological sample such as blood and urine and more particularly to an automatic analyzer including a reagent cassette holding mechanism for holding a plurality of reagent cassettes.
2. Description of the Related Art
In general, for the purpose of making measurements on a plurality of analysis items, an automatic analyzer for performing qualitative/quantitative analysis of a biological sample such as blood and urine includes a reagent cassette storage unit for storing therein a plurality of reagents corresponding to the analysis items. An administrator of the automatic analyzer manages the reagent cassette storage unit so that reagents required for analysis for a day are stored. However, in the event that a reagent shortage occurs during the analysis, the analysis is temporarily interrupted to replace the reagents.
On the other hand, the number of analysis items to be analyzed by the automatic analyzer increases. Therefore, for the purpose of analyzing the other items, each reagent cassette is also miniaturized so that a large number of reagent cassettes can be placed. In this case, in comparison with the conventional analyzers, there is a higher possibility that a reagent shortage will occur during analysis. In response to the above problem, there is disclosed in JP-A-2005-37171 an automatic analyzer including a mechanism that is capable of automatically adding a reagent to a reagent cassette storage unit.


A sampling device for obtaining samples of internal body substances in the digestive system is a swallowable capsule which allows a sample of the body substance to enter the capsule through an inlet which opens in the digestive tract following contact with the substance to be collected. The capsule inlet initially is sealed and, after the capsule has been swallowed, the inlet opens following contact with the body substance. An inner chamber preserves a vacuum or substantial under pressure when the inlet is sealed by a blocking member adjacent to the inlet. The blocking member is elastic and has a flow permitting configuration which admits the body substance into the inner chamber and a flow preventing configuration which blocks the inlet from the inside of the chamber when the pressure difference has been equalized.

Examination of internal body substances, gases or solid particles in the digestive system or the gastrointestinal tract in the human or animal body provides essential medical information for diagnosing and treatment. Examination of a sample of the gastric fluid of a patient provides important information of pH, acid contents, abdominal enzyme activity as well as information for diagnosing gastric ulcer and gastritis, cancer and tumour diseases, etc. A gastroscopic examination gives the physician who is treating a patient important information and plays a great role for a diagnosis. These intubation examinations are thus used extensively. A gastroscopic examination, in which a tube, having a diameter of a little finger, is inserted into the patient's mouth or nose, through the esophagus and to the gastrointestinal system, is difficult to perform and demands the assistance of a physician. For the patient, the intubation of the digestive tract using these methods is a very unpleasant intervention, both physically and psychologically, especially during the insertion of the tube and also when it is pulled out. The intubation demands that the patient is given a local anaesthetic and in some instances even tranquilliser or a general anaesthetic to overcome the stress to which the patient is subjected. The intubation examination methods described above are disadvantageous since they are very time-consuming for a qualified physician and thus expensive and a very unpleasant intervention for the patient.
The application of a swallowable capsule for automatically obtaining samples of internal gastric fluids has been proposed as an alternative examination method and is described in U.S. Pat. No. 4,481,952. The capsule is equipped with mechanisms, which control the opening and closing of the capsule. The mechanisms are blocked by blocking mechanisms, including a mass which is dissolved after a short time following contact with the gastric fluid. The opening of the capsule, the collection of the sample and the reclosing of the capsule takes place automatically in the patient's stomach. The described sampling device is advantageous in many ways. However, it has proved to function unsatisfactorily and has therefore not been widely used. The described capsule is expensive, is mechanically complicated and comprises mutually movable parts, mostly metal parts. As a consequence, the parts tend to jam, fluids tend to leak between the parts, friction forces between the parts must be overcome, e.g. by spring forces, and metal parts, such as springs, may loosen in the gastrointestinal tract causing injuries to the patients.

Sampling device and method for obtaining samples of internal body substances and method for producing a sampling device


An organic EL display panel having a functional layer with a uniform film thickness is provided. The organic EL display panel of the present invention contains anode electrodes set on the substrate; organic EL layers set on the anode electrodes; line-state banks defining the organic EL layers in a line-state region; second banks defining two or more regions in the line-state region. The line-state banks and the second banks contain a fluorine resin, a fluorine concentration of the fluorine resin gradually changes along a thickness direction of each of the line-state bank and the second bank, and the fluorine concentration at a top of each of the line-state bank and the second bank is higher than the fluorine concentration at a bottom surface of each of the line-state bank and the second bank.

An organic device such as an organic semiconductor element, OEL element and the like usually has a functional layer containing an organic functional material set between an anode and a cathode. According to functions of the organic functional material, an organic device can be classified into a semiconductor element (transistor), a light-emitting element, a liquid crystal element and the like. The semiconductor element has an organic semiconducting material connecting a source electrode and a drain electrode set on a substrate surface, for example; and the organic EL element has a light emitting layer containing an organic EL material set between the anode electrode set on the substrate surface and the cathode electrode.
In order to pattern the organic functional material on the electrode, a barrier (that is, a bank) surrounding an electrode is formed, and a composition containing the organic functional material is applied to a region defined by the banks in some cases. A material of the bank may be a resin.
When ink containing the organic functional material is applied to the region including the electrode surface defined by the banks, it is preferable that the region to be coated (including the electrode surface) has high lyophilicity and the upper surface of the bank has low lyophilicity in general. That is to prevent the ink from leaking to the outside of the targeted region.
In general, a fluorine component is known to decrease the energy and the lyophilicity of a substance surface. The method to subject the bank surface to plasma-treatment with a fluorocarbon gas in order to decrease the lyophilicity of an upper surface of the bank, is known (See Patent Document 1). However, if the bank surface is plasma-treated with the fluorocarbon gas, usually, fluorine is not chemically bonded to a surface of the material of a bank but just adsorbed to the material surface by an intermolecular force. Therefore, even if fluorine is adsorbed to the material surface by plasma treatment, fluorine migration may occur by thermal process or the like. If fluorine is migrated to an organic functional layer of an organic device, for example, it deteriorates device property. Particularly, if a fluorine atom with large electron withdrawing is mixed in an organic light emitting layer, there is a fear that a light emitting exciter is deactivated and light emission efficiency or the like is adversely affected.
As means for solving the above problems, forming a bank using a fluorinated photoresist is proposed (See Patent Document 2). The bank formed with a photolithography process which comprises application step of applying fluorinated photoresist; development step; washing step; calcination step and the like has a feature that lyophilicity is low even without plasma treatment.    Patent Document 1: Japanese Patent Laid-Open Publication No. 2005-52835    Patent Document 2: Japanese Patent Application Laid-Open No. 2005-522000

Organic EL element including banks containing fluorine resin and manufacturing method thereof


An optical architecture is provided comprising at least one broadband light source, a mod/mux unit, and a plurality of premises stations in communication with the mod/mux unit via an optical distribution hub. The mod/mux unit is configured to permit selective modulation of demultiplexed components of a target wavelength band of an optical signal, multiplex the selectively modulated optical signal, and direct the target wavelength band and a bypass wavelength band of the multiplexed optical signal to the optical distribution hub. The optical distribution hub comprises an arrayed waveguide grating configured to demultiplex the multiplexed optical signal and distribute respective distinct wavelength portions of the target wavelength band and respective distinct wavelength portions of the bypass wavelength band to respective ones of the premises stations.

The present invention relates to optical data transfer system architectures and, more particularly, to Fiber-to-the-Premises (FTTP) architectures and components for use therein. There is a continuing drive in the industry to provide improvements to the hardware and methodology utilized for the delivery and receipt of data in a telecommunications and other types of data transfer networks.
Optical data transfer networks operate according to the general principle that information can be generated, shared, passed on, bypassed or otherwise manipulated or communicated within a network of data transfer lines. Network applications include LANs, MANs, WANs, SANs, intrabuilding and interbuilding communications, broadcast distribution, intelligent transportation systems (ITS), telecommunications, supervisory control and data acquisition (SCADA) networks, etc. It has been recognized that optical fiber data transfer lines embody a number of advantages over electrically conductive data transfer lines. Specifically, optical lines offer increased bandwidth, enhanced durability, easier installation, improved immunity to electromagnetic interference, and resistance to harsh environmental conditions. Accordingly, the present invention is directed at providing improved optical architectures for data transfer and, more particularly, to improved schemes for effectuating the transfer of data to and from homes, businesses, and other remote premises.


A computer-implemented method for improving efficiency in an electronic procurement system for sourcing resources, comprising, during digital electronic interactions of a buyer computer with one or more software platforms and without receiving explicit request for recommendations from the buyer computer: automatically generating, at a coding computer, implicit observation data of the buyer computer; automatically determining, at the coding computer, one or more active sourcing events from a plurality of sourcing events, based on at least the implicit observation data of the buyer computer; using the coding computer, causing to display at least one of the one or more active sourcing events in a graphical user interface.

The approaches described in this section are approaches that could be pursued, but not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section.
Electronic procurement or e-procurement has developed as a discrete technical field or technology in which programmed computers are applied to the telecommunication problem of how to connect distant user accounts associated with buyers and suppliers, negotiate terms of contracts for the supply of tangible or intangible goods or services, and track purchase orders, invoicing and payment. E-procurement is often practiced using networks of distributed computers and software-as-a-service or SaaS based online applications.
Computer-implemented sourcing, in e-procurement, is the technical process by which a buyer computer expresses decisions about supplier computers to contract with for goods or services that are purchased. Sourcing events allow buyer computers to digitally interact with other buyer computers to improve the efficiency of data transmissions relating to transactions and increase total purchasing power to more efficiently complete transactions with supplier computers. Third-party teams of computers run sourcing events and digitally negotiate on behalf of participants of the sourcing events. Participants lack visibility of other participants and do not have an ability to exchange communication amongst themselves or to negotiate for themselves and must rely on third-party teams. Fees associated with searching potential supplier computers and negotiating often result in inefficient sourcing solutions.
Computer-implemented sourcing solutions allow participant computers to search for sourcing events to participate in and to create their own sourcing event when they do not find any relevant sourcing events to join. Performing repeated searches to find a particular sourcing event to participate in is labor intensive and wastes tremendous amounts of computing resources including power, storage, and network bandwidth. Another inefficiency is creating redundant sourcing events for same or similar goods or services when a sourcing event is not found; that is, a buyer account of a first buyer computer could create a sourcing event because the buyer account is not storing digital data about a second buyer account that is already involved in a sourcing event for the same commodity or a similar commodity. By creating multiple sourcing events for the same or similar goods or services, buyer computers use excessive amounts of the resources noted above.
Therefore, there is a need to improve identification of relevant sourcing events to decrease the excessive use of computer processing resources and network bandwidth. The foregoing and other objectives, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of the invention, taken in conjunction with the accompanying drawings.

Automatically recommending community sourcing events based on observations


A device for restricting the bending diameter and bending strain exerted on elongated articles (1) such as cables, pipes, umbilicals and other elongated articles is used when installating such articles from a cable ship to a sea bed. There is used a number of wire elements (32,33) which are arranged for tensioning the annular elements into contact with each other. The wire elements (32,33) are equally distributed in or on the annular elements to ensure uniform compression of these elements.

1. Technical Field
The present invention relates to bending restrictors and bending strain restrictors designed for cables, pipes and other elongated articles such as umbilicals, which are installed in connection with offshore constructions. In the following the invention will be described in connection wish installation of a cable from a cable ship.
2. Description of the Prior Art
Offshore cables are designed to withstand strains caused by bending under tension such as passing the cable over a bow wheel of the ship. The cables are also to a certain extent designed to withstand repeated flexing after installation and during normal operation. In most cases at least one end of the cable is provided with a termination head for simplifying interconnection of the cable with an offshore construction such as a template arranged on the sea bed. In such cases a critical installation phase is to bring the cable with the termination head safely from the cable ship down to the template. Such termination heads may weigh 5 tons and more.
Bending strain restrictors are normally designed such that the combined stiffness of the elongated article itself and the restrictor is gradually reduced along the article from the position where the restrictor is clamped to installation head.
The main purpose of a bending restrictor (BR) is to limit the bending diameter of a cable to a minimum value, whereas the main purpose of a bending strain restrictor (BSR) is to restrict the strain in the cable when it is bent.

N.o slashed.rholmen; John .O slashed.ivind


The present invention is a composition that may be used for sealing applications in the manufacture of electronic devices. The composition includes organic vehicles that may be removed upon low temperature firing in air or inert atmospheres. The present invention is further a process for the use of the composition.

Compositions applied as a thick film paste are used in sealing sheets of glass in the manufacture of devices such as electronic displays. As described in sources such as    Alpha, Glass Sealing Technologies for Displays, Optics and Laser Technology, 8, 259-264 (1976); Kwon et al, Plasma Display Panel Vacuum In-line Sealing Technology by Using Bubble-reduced Frit, J. Vacuum Sci. and Technology, A, 21, 206-211 (2003); and Korczynski, Manufacturing Emissive Displays, Solid State Technology, 51, 54-56 (1999),current compositions require organic vehicle burnout by firing in air at about 350° C. or higher, followed by sintering of glass frit at 430° C. or higher in nitrogen containing 10 to 1000 ppm of oxygen, and more typically 500 to 1000 ppm oxygen. Air firing has typically been required for burnout of the organic vehicle being used. It does not appear that the organic vehicles used in these compositions were functionally fugitive in the absence of oxygen, nor could they burn out in oxygen at lower temperatures.
A need thus remains for sealing compositions that can be fired at lower temperatures, and this invention thus provides such compositions comprising organic vehicles that may be removed at lower temperatures in air or inert atmosphere. It has been found that lowering the firing temperature, or the use of an inert atmosphere, reduces the potential for oxidation of other components of the device, which are subject to the firing cycle along with the sealing composition.

Thick film sealing glass compositions for low temperature firing


Methods and system are provided for an adaptive vehicle locking system. The system includes a plurality of vehicle door locks, each configured to lock and unlock in response to a first signal, a plurality of sensors each configured to sense opening and closing of an associated vehicle door and to send second signals in response to opening and closing of the associated vehicle door, and a lock requester configured to send a third signal. A control module that includes a memory for storing a history of the second signals and a timer adaptively settable in response to the history of the second signals is configured to receive the second signals from the plurality of sensors and the third signal from the lock requester. The control module is also configured to send a first signal to the plurality of vehicle door locks causing the vehicle door locks to lock in response to timing out of the timer following receipt of the third signal.

In traditional vehicular power door locks, door locking is limited to two different approaches when a lock request is made and a door or doors are open. The locking system either immediately locks all doors upon receipt of the operator lock request, or it locks all the doors following a time delay after the open door or doors are closed. Immediately locking all doors upon operator request is often an inconvenience if the driver or passenger of the vehicle needs to retrieve something (such as a child, a briefcase, etc.) from the vehicle and must open a closed door to do so. In this situation, a time delay between the closing of the door or doors and lock activation is much more advantageous than immediately activating the door locks
In a lock delay system, the length of the time delay following door closure, but prior to lock activation, may be preset to any duration. A long time delay is more convenient than a short time delay, giving passengers adequate time to open and close the vehicle's doors and retrieve objects before lock activation. On the other hand, a short time delay is more secure than a long time delay, making the vehicle less likely to be entered by an unauthorized user. The length of the time delay, which may be set at the factory, is not otherwise easily adjusted, however, and it currently cannot adapt to different users or uses. One driver of the vehicle may typically require no time delay, while another driver may typically need a very long delay. Additionally, in those situations in which the driver or passenger opens several doors, the current system does not change the delay between different door openings; the time delay (if any) is the same for each opening and closing. Even if the driver or passenger requires less time to open a second door than to open the first door, the preset locking system provides the same delay for each door opening.
Accordingly, a need exists for a vehicle locking system with adaptive actuation that tailors the time delay between door or doors closing and vehicle locking to individual drivers and situations. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.

Adaptive actuation vehicle locking system and method


A method of making a micron gap thermal photovoltaic device wherein at least one standoff is formed on a photovoltaic substrate, a sacrificial layer is deposited on the photovoltaic substrate and about the standoff, an emitter is attached to the standoff and has a lower planar surface separated from the photovoltaic substrate by the sacrificial layer, and the sacrificial layer is removed to form a sub-micron gap between the photovoltaic substrate and the lower planar surface of the emitter.

It has been shown that electromagnetic energy transfer between a hot and cold body is a function of the close spacing of the bodies due to evanescent coupling of near fields. Thus, the closer the bodies, approximately one micron and below, the greater the power transfer. For gap spacings of 0.1 microns, increases in the rate of energy transfer of factors of five and higher are observed.
The dilemma, however, is forming and then maintaining the close spacing between two bodies at a sub-micron gap in order to maintain enhanced performance. While it is possible to obtain the sub-micron gap spacing, the thermal effects on the hot and cold surfaces induce cupping, warping, or deformation of the elements resulting in variations in gap spacing thereby resulting in uncontrollable variances in the power output.
Typically, in order to increase power output, given the lower power density of prior art devices, it has been necessary to increase the temperature. Temperature increases, however, are limited by the material of the device and system components.
Micron gap thermal photovoltaic (MTPV) systems are a potentially more efficient way to use photovoltaic cells to convert heat to electricity. Micron gap thermal photovoltaic devices are an improved method of thermal photovoltaics which is the thermal version of "solar cell" technology. Both methods make use of the ability of photons to excite electrons across the bandgap of a semi-conductor and thereby generate useful electric current. The lower the temperature of the heat source, the narrower the bandgap of the semi-conductor must be to provide the best match with the incoming spectrum of photon energy. Only those photons with energy equal to or greater than the bandgap can generate electricity. Lower energy photons can only generate heat and are a loss mechanism for efficiency. A preferred micron gap thermal photovoltaic system would include a source of heat radiated or conducted to an emitter layer which is suspended at a sub-micron gap above the surface of an infrared sensing photovoltaic cell.
By using a sub-micron gap between a hot emitting surface and a photovoltaic collector, a more enhanced rate of transfer of photons from solid to solid is observed than is possible with large gaps. Additional transfer mechanisms are involved other than simply Planck's law of the radiation, although the spectral distribution of the photons is that of a black body. The use of sub-micron gaps, however, implies that a vacuum environment is used to avoid excessive heat conduction across the gap by low energy photons that cannot excite electrons into the conduction band. To make efficient use of the source of heat, a high fraction of high energy photons must be generated. The structure used to separate the emitting surface from the photovoltaic cell must be both small in diameter and also a very good thermal insulator for the same efficiency considerations. The photovoltaic cell will generally have to be cooled somewhat so that it will function properly. At high temperatures, intrinsic carrier generation swamps the PN junction and it is no longer an effective collector of electrons.
Micron gap thermal photovoltaic systems function as though the emitter has an emissivity value greater than one. The definition of a black body is that it has an emissivity value equal to one and this value cannot be exceeded for large gap radiant energy transfer. Equivalent emissivity factors of 5-10 have been experimentally demonstrated by the Assignees hereof using gaps in the region of 0.30 to 0.10 microns.
There are at least two ways to take advantage of this phenomenon. In a comparable system, if the temperature of the emitting surfaces is kept the same, the micron gap thermal photovoltaic system can be made proportionately smaller and cheaper while producing the same amount of electricity. Or, if a comparable size system is used, the micron gap thermal photovoltaic system will run at a considerably lower temperature thereby reducing the cost of materials used in manufacturing the system. In a preliminary estimate, it was calculated that by using micron gap technology the operating temperature of a typical system could be reduced from 1,400° C. to 1,000° C. and still produce the same output of electricity. Such a lowering of temperature could make the difference in the practicality of the system due to the wider availability and lower cost of possible materials.
Additional energy transfer mechanisms have been postulated and the ability to build systems using narrow thermally isolated gaps may find use in many types of applications in accordance with the subject invention.
In the Assignee's previous patent, U.S. Pat. No. 6,232,546, incorporated herein by this reference, an array of emitters was supported on a panel by flexures and the top surface of each emitter spaced from the photovoltaic element or cell by spacers formed on each emitter. The micron gap thermal photovoltaic devices constructed to date according to the disclosure of the '546 patent have typically been small chips four square millimeters in area and not particularly well suited for the generation of sufficient electrical power in some applications.
The initial multi-piece construction method of achieving small gaps was to build thin, small diameter spacers on an emitter "heater chip" structure, clean the photovoltaic cell and the heater chip, and then place them together in an attempt to eliminate dirt particles or waviness in the surface which would limit achieving the desired small gap. This manufacturing technique could be difficult to accomplish on large area devices with dimensions on the order of inches or even feet.

Micron gap thermal photovoltaic device and method of making the same

The Charles Stark Draper Laboratory, Inc.


A ferroelectric thin film formed of a highly oriented polycrystal in which 180° domains and 90° domains arrange at a constant angle to an applied electric field direction in a thin film plane and reversely rotate in a predetermined electric field.

In recent years, research and development of a thin film such as PZT or SBT, and a ferroelectric capacitor and a ferroelectric memory device using such a thin film have been extensively conducted. The structure of the ferroelectric memory device is roughly divided into 1T, 1T1C, 2T2C, and simple matrix. Since the 1T ferroelectric memory device has retention time (data retention time) as short as one month due to occurrence of an internal electric field in the capacitor because of its structure, it is considered to be impossible to secure a 10-year guarantee generally required for semiconductors. The 1T1C and 2T2C ferroelectric memory devices have almost the same configuration as that of a DRAM, and include a select transistor. Therefore, the DRAM manufacturing technology can be utilized. Moreover, since the 1T1C and 2T2C ferroelectric memory devices realize a write speed equal to that of an SRAM, small capacity products with a capacity of 256 kbits or less have been produced on a commercial basis.
As the ferroelectric material, Pb(Zr,Ti)O3 (PZT) has been mainly used. PZT having a composition in or near a mixed region of a rhombohedral crystal and a tetragonal crystal, in which the Zr/Ti ratio is 52/48 or 40/60, is used after doping with an element such as La, Sr, or Ca. The reason why this region is used after doping is to secure reliability indispensable for a memory device.
PZT, which has been widely applied to a ferroelectric memory, is a solid solution of PbZrO3 and PbTiO3. In the case where PZT contains Zr at a ratio greater than Zr:Ti=52/48, PZT shows a narrow hysteresis shape. In the case where PZT contains a greater amount of Ti, PZT shows a hysteresis shape with excellent squareness.
The hysteresis shape immediately after writing data is better in the Ti-rich tetragonal region. The Ti-rich tetragonal region is suitable for memory applications if only the hysteresis shape is taken into consideration. However, PZT in the tetragonal region has not been put into commercial use as a ferroelectric memory device since reliability cannot be secured.
Among a number of reliability tests, a reliability test called a static imprint test is the most rigorous test. In this test, a ferroelectric memory in which data "1" or "0" is written, that is, a ferroelectric thin film polarized at "+" or "−" is allowed to stand at a predetermined temperature (85° C. or 150° C., for example) for a predetermined time (100 or 1000 hours, for example), and whether or not the originally written data can be read is tested.
As described above, the hysteresis shape immediately after writing data is better in the Ti-rich tetragonal region. However, the Ti-rich tetragonal region means that most of the crystal constituent elements consist of Pb and Ti.
Pb has a high vapor pressure, and produces PbO vapor at a low temperature of about 100° C. as known from the Ellingham diagram. Moreover, Pb has the smallest bond energy with oxygen (38.8 kcal/mol), and tends to cause Pb deficiency to occur in the PZT crystal. Ti has a bond energy with oxygen of 73 kcal/mol, which is about twice the Pb—O bond energy. However, since Ti has the smallest atomic weight (47.88) among the constituent elements of PZT, which is about half the atomic weight of Zr (91.224) which is also a B site constituent element, it is most likely that Ti is scattered during oscillating bombardment which occurs during the heat treatment in the static imprint test, whereby Ti deficiency tends to occur in the PZT crystal. These defects result in space charge polarization, and cause imprint characteristics to deteriorate.
Moreover, O deficiency occurs from the charge neutrality principle, whereby Schottky defects occur due to the ionic crystal structure. This causes leakage current characteristics to deteriorate, whereby reliability cannot be secured.
A reduction of the device size and the thickness of the ferroelectric thin film has progressed accompanying an increase in the degree of integration of the ferroelectric memory and the necessity of low voltage drive. Therefore, in the case of using PZT as the ferroelectric material, it is impossible to utilize the Zr-rich composition used for a small capacity memory. This makes it necessary to use PZT having a Ti-rich composition.
Specifically, since the relative dielectric constant is increased due to a reduction of the film thickness, the hysteresis shape becomes narrower. Zr-rich PZT has not posed problems relating to reliability such as imprint characteristics in practical application. However, if the hysteresis shape becomes further narrowed, deterioration of imprint characteristics will come to the surface. Therefore, in order to make the hysteresis shape closer to the hysteresis shape used for a small capacity memory by decreasing the relative dielectric constant, PZT having a Ti-rich composition must be used. This causes the above-described problems to occur. Therefore, it is impossible to increase the integration of the ferroelectric memory unless the problems of Ti-rich PZT are solved.
The simple matrix ferroelectric memory device has a cell size smaller than that of the 1T1C and 2T2C ferroelectric memory devices, and enables multilayering of the capacitors. Therefore, an increase in the degree of integration and a reduction of cost are expected. A conventional simple matrix ferroelectric memory device is disclosed in Japanese Patent Application Laid-open No. 9-116107, for example. Japanese Patent Application Laid-open No. 9-116107 discloses a drive method in which a voltage of one-third a write voltage is applied to unselected memory cells when writing data into the memory cell. However, this technology does not describe the hysteresis loop of the ferroelectric capacitor necessary for the operation in detail. The present inventors have advanced development and found that a hysteresis loop with excellent squareness is indispensable to obtain a simple matrix ferroelectric memory device which can be operated in practice. As a ferroelectric material which can deal with such a requirement, Ti-rich tetragonal PZT may be considered as a candidate. However, the most important subject is to secure reliability in the same manner as the 1T1C and 2T2C ferroelectric memories.
A ferroelectric thin film used for a ferroelectric memory is generally used in a state in which the polarization axis of the ferroelectric is aligned in the direction of an applied electric field.
In PZT, the Zr/Ti ratio of 52/48 is called a phase boundary, which is a mixed region of a rhombohedral crystal and a tetragonal crystal. If Zr exceeds 52, the crystal structure becomes rhombohedral. If Ti exceeds 48, the crystal structure becomes tetragonal.
In rhombohedral PZT, the polarization axis exists along the <001> axis. In tetragonal PZT, the polarization axis exists along the <111> axis. Therefore, in the case of using a PZT thin film for a ferroelectric memory, the PZT thin film is generally used in a state in which the orientation is aligned with the polarization axis direction, as described in 49th Japan Society of Applied Physics and Related Societies Meeting Preliminary Report 27a-ZA-6.
However, domains which are sources of ferroelectricity are present in the ferroelectric in addition to the crystal orientation. The domains include a 180° domain and a 90° domain.
In the case where the polarization axis is aligned with the crystal orientation axis, the 180° domain parallel to the applied electric field contributes to polarization, but the 90° domain does not contribute to polarization.
If an ideal ferroelectric capacitor is formed, since the 90° domain does not contribute to polarization, a serious problem does not occur even if the 90° domain exists. However, the contribution rate of the entire PZT thin film to polarization is reduced by an amount for the existence of the 90° domain.
In the actual ferroelectric capacitor, the uppermost surface of the electrode is not completely flat and has unevenness, and a crystal is grown in an inclined state in most cases. In this case, the 90° domain does not become completely perpendicular to the applied electric field, and is at an angle to the applied electric field to some extent. In this case, the 90° domain contributes to polarization. However, since the polarization axis exists in the direction approximately at right angles to the applied electric field, a considerably large electric field is necessary to cause the 90° domain to contribute as the polarization in comparison with the 180° domain. Specifically, it becomes difficult to use the ferroelectric capacitor at a low voltage.

Ferroelectric thin film, method of manufacturing the same, ferroelectric memory device and ferroelectric piezoelectric device


Disclosed is a charge-transporting varnish containing a charge-transporting organic material, a good solvent, at least one poor solvent with high leveling properties, and at least one volatile poor solvent. The charge-transporting organic material is composed of a charge-transporting material consisting of a charge-transporting monomer or a charge-transporting oligomer having a number average molecular weight of 200 to 5000, or alternatively composed of such a charge-transporting material and an electron-accepting dopant material or a hole-accepting dopant material. This charge-transporting varnish enables to form a uniform and smooth charge-transporting thin film by a spray method or an ink jet method on an exposed electrode portion such as ITO or IZO of a substrate on which a structure of a simple or complicated pattern is formed beforehand.

Where organic compounds, particularly polymers and oligomers, are used as an electronic device material, they are frequently employed as a thin film. For instance, mention is made of an insulating film, charge transporting film, protective film and flattened film.
In organic electroluminescent (hereinafter abbreviated as EL) devices, charge transporting thin films made of polymers or oligomers are used as a hole transport layer (buffer layer) and a charge injection layer (see, for example, Patent Document 1).
It is required that the charge transporting thin film can be formed on a flat electrode such as of indium tin oxide (hereinafter abbreviated as ITO), indium zinc oxide (hereinafter abbreviated as IZO) or the like in the form of a uniform, unevenness-free thin film. However, when a charge transporting thin film is formed actually in an electronic device, a structure is formed on the electrode in most cases. More particularly, a structure of at least one simple or complicated pattern having a thickness of several μm may be formed in some case. A charge transporting varnish of a type, which is used to selectively, flatly form a charge transporting thin film on an exposed ITO or IZO electrode portion of a substrate on which a structure constituted of a simple or complicated pattern has been formed, may frequently differ in liquid physical properties from a charge transporting varnish of the type used to form a charge transporting thin film uniformly on a flat electrode. Thus, the liquid physical properties of a charge transporting varnish adapted for the structure on a substrate need to be studied in detail.
Among electronic devices, on the other hand, an organic EL device has recently drawn attention as a next-generation thin display that is being put to practice, and is one of electronic devices, which is now under study for practical use. As it becomes more likely for the device to come into practical use, it has been required in the production line to make a highly reliable device inexpensively and in good yield and high efficiency. Especially, the inexpensiveness is a self-evident requirement, with a tendency to meet the requirement through a trial and error approach to processes of making a charge transporting thin film.
The process of making a charge transporting thin film can be broadly classified into a dry process, typical of which is a vacuum deposition process, and a wet process typified by a spin coating process. According to the comparison between the dry process and the wet process, the charge transporting thin film formed by the wet process rather than the dry process is higher in the ability of covering an electrode such as of ITO or IZO and is able to uniformly coat foreign matters on the electrode surface in even thickness, thereby drastically improving electric short-circuiting characteristics of an electronic device being fabricated. In this regard, the wet process is more advantageous and higher in superiority.
Hence, we made continued studies on the fabrication of a charge transporting thin film responsible for electronic devices, to which a wet process is applicable (see, for example, Patent Document 2).
The wet process needs a very large amount of a charge transporting varnish necessary for forming a charge transporting thin film, for example, by a spin coating process or printing process. More particularly, aside from a charge transporting varnish contributing to the formation of a charge transporting thin film, a ratio of a charge transporting varnish to be wasted becomes very large, resulting in poor cost performance.
For a process of making a charge transporting thin film in high efficiency, a spray process or ink jet process can be mentioned. Particularly, the spray process is effective, from the standpoint of the general versatility of apparatus, as a wet process capable of making a large-area device.
Consequently, it becomes necessary to provide a charge transporting varnish that is optimum for forming, according to a spray process or an ink jet process, a uniform, unevenness-free charge transporting thin film on an exposed ITO or IZO electrode portion of a substrate forming a structure of a simple or complicated pattern thereon.
This problem of forming a charge transporting thin film on a substrate forming a structure of a simple or complicated pattern thereon is important not only for the thin film for electronic devices, but also for other technical fields using thin films.
For the reasons set out above, there is a demand for development of a charge transporting varnish suited for the spray or ink jet process.
Patent Document 1:                JP-A 2002-151272
Patent Document 2:                PCT Patent Publication No. WO 2004/043117

Charge-transporting varnish for spray or ink jet application