A CAM block includes a CAM array having a plurality of rows and columns of 4-bit NAND-type CAM cells therein. Each of a plurality of the NAND-type cells includes a respective ladder-type compare circuit having four two-transistor rungs. At least one of the plurality of rows includes a first 4-bit NAND-type CAM cell having a first ladder-type compare circuit with four two-transistor rungs and a second 4-bit NAND-type CAM cell having a second ladder-type compare circuit with four two-transistor rungs. A match line segment is also provided, which is connected to four source terminals of transistors in the first ladder-type compare circuit and four drain terminals of transistors in the second ladder-type compare circuit.

In many memory devices, including random access memory (RAM) devices, data is typically accessed by supplying an address to an array of memory cells and then reading data from the memory cells that reside at the supplied address. However, in content addressable memory (CAM) devices, data within a CAM array is not accessed by initially supplying an address, but rather by initially applying data (e.g., search words) to the array and then performing a search operation to identify one or more entries within the CAM array that contain data equivalent to the applied data and thereby represent a "match" condition. In this manner, data is accessed according to its content rather than its address. Upon completion of the search operation, the identified location(s) containing the equivalent data is typically encoded to provide an address (e.g., block address+row address within a block) at which the matching entry is located. If multiple matching entries are identified in response to the search operation, then local priority encoding operations may be performed to identify a location of a best or highest priority matching entry. Such priority encoding operations frequently utilize the relative physical locations of multiple matching entries within the CAM array to identify a highest priority matching entry.
The cells within a CAM array are frequently configured as binary CAM cells that store only data bits (as "1" or "0" logic values) or as ternary (or quaternary) CAM cells that store data bits and mask bits. As will be understood by those skilled in the art, when a mask bit within a ternary CAM cell is inactive (e.g., set to a logic 1 value), the ternary CAM cell may operate as a conventional binary CAM cell storing an "unmasked" data bit. When the mask bit is active (e.g., set to a logic 0 value), the ternary CAM cell is treated as storing a "don't care" (X) value, which means that all compare operations performed on the actively masked ternary CAM cell will result in a cell match condition. Thus, if a logic 0 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 1 data bit, the compare operation will indicate a cell match condition. A cell match condition will also be indicated if a logic 1 data bit is applied to a ternary CAM cell storing an active mask bit and a logic 0 data bit. Accordingly, if a data word of length N, where N is an integer, is applied to a ternary CAM array having a plurality of entries therein of logical width N, then a compare operation will yield one or more match conditions whenever all the unmasked data bits of an entry in the ternary CAM array are identical to the corresponding data bits of the applied search word. This means that if the applied search word equals {1011}, the following entries will result in a match condition in a CAM comprising ternary CAM cells: {1011}, {X011}, {1X11}, {10X1}, {101X}, {XX11}, {1XX1}, . . . , {1XXX}, {XXXX}. A quaterna CAM cell is different from a ternary CAM cell because it has four valid combinations of states: ((data=0, mask=active), (data=1, mask=active), (data=0, mask=inactive), (data=1, mask=inactive)). Quaternary CAM cells are frequently treated as "ternary" CAM cells because two of the four states represent equivalent active mask conditions when search operations are performed. However, ternary CAM (TCAM) cells and quaternary CAM (QCAM) cells will be treated herein as separate categories of CAM cells.
CAM cells may use a variety of different memory cell technologies, including volatile SRAM and DRAM technologies and nonvolatile memory technologies. CAM cells based on these technologies are disclosed in U.S. Pat. Nos. 6,101,116, 6,128,207, 6,256,216, 6,266,263, 6,373,739 and 6,496,399, assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. In addition, U.S. Pat. No. 6,522,562 to Foss, entitled "Content Addressable Memory Cell Having Improved Layout," discloses a CAM cell that uses p-channel transistors as SRAM access transistors. These p-channel transistors purportedly improve layout efficiency by providing a balanced number of p-channel and N-channel transistors within each CAM cell. In particular, FIG. 4 of the '562 patent illustrates a CAM half-cell that includes a 6T SRAM cell defined by two PMOS access transistors P3 and P4, two PMOS pull-up transistors P1 and P2 and two NMOS pull-down transistors N1 and N2. One half of a 4T compare circuit is also illustrated as including two NMOS transistors N3 and N4. Unfortunately, because PMOS transistors typically have lower mobility relative to equivalently-sized NMOS transistors, using PMOS transistors as access transistors within an SRAM cell may require relatively large PMOS transistors that increase overall unit cell size.
CAM cells having small unit cell size can also be achieved using lower transistor count dynamic CAM cells. For example, FIG. 5 of U.S. Pat. No. 6,188,594 to Ong, entitled "Reduced-Pitch 6-Transistor NMOS Content-Addressable-Memory Cell," discloses a 6T CAM cell having a non-unity layout aspect ratio.
CAM cells may be configured with NOR-type or NAND-type compare logic. In the case of NOR-type compare logic, a match line associated with a row of CAM cells is typically switched high-to-low upon detection of at least one "miss" in the row during a search operation. NOR-type compare logic typically provides for faster CAM cell operation during search operations with relatively high match line power consumption. Because of the parallel configuration of NOR-type compare logic, parasitic leakage currents through the compare logic transistors may provide a significant pull-down force on a match line and lead to search failure. In contrast, in NAND-type compare logic, a match line signal is propagated across the compare logic and lower match line power is typically consumed. For example, in the conventional ternary NAND-type CAM cell 20 of FIG. 2A. a match line signal may be propagated across at least one of two parallel paths of a four transistor (4T) compare logic circuit when a match condition is present or blocked from propagation when a miss condition is present. A first one of these two parallel paths is defined by transistor NA, which is responsive to a data signal (DX) applied during a search operation, and transistor NB, which is responsive to a signal generated at a storage node of an X memory cell (SRAM SX). A second one of these two parallel paths is defined by transistor NC, which is responsive to a data signal (DY) applied during a search operation, and transistor ND, which is responsive to a signal generated at a storage node of a Y memory cell (SRAM SY). Unfortunately, because CAM cells having the NAND-type compare logic illustrated by FIG. 2A require serial propagation of match line signals, NAND-type CAM devices are typically slower in operation relative to NOR-type CAM devices. This serial propagation of a match line signal is demonstrated by the pair of NAND-type CAM cells 20′ of FIG. 2B. This pair of CAM cells 20′ includes a left cell containing transistors NA1, NB1, NC1 and ND1 and a right cell containing transistors NA2, NB2, NC2 and ND2. A worst case propagation of a match line signal ML from the left of the left cell to the right of the right cell requires a propagation through four serially-connected transistors NA1, NB1 (or NC1, ND1) and NA2, NB2 (or NC2, ND2). Because of this configuration of conventional NAND-type CAM cells, which may require long serial paths for match line propagation in wide CAM arrays, there exists a need for NAND-type CAM devices having higher speed characteristics while retaining low power characteristics.

High speed NAND-type content addressable memory (CAM)


A tube clip structure is disclosed. The clip structure comprises a lower clipping body, an upper clipping body, a pulling plate, an elastic member, the internal side of the lower clipping body being a lower clipping ring for firmly mounting on the protruded edge of a tube body and the internal side of the upper clipping ring for firmly mounting on the protruded edge of a tube body, and a clipping body pivoted rod connecting the upper clipping body and the lower clipping body being used to form an actuating body which can be closed and opened, and the other side end of the upper clipping body being provided with an upper pivotal slot, characterized in that the upper pivotal slot is provided with a pulling plate having a pivotal block which is connected by the pulling plate, and the side of the pulling plate pivot is the elastic member connected to the lower end of the pulling plate by the pulling plate peg so as to allow a fastening rod to mount to a lower fastening slot at the lower end of the lower clipping body, thereby the upper and lower clipping body clip and secure the pulling plate.

(a) Technical Field of the Invention
The present invention relates to a tube clip, and in particular, a clip which could effectively and rapidly fasten or release the edge of a tube body.
(b) Description of the Prior Art
FIG. 1 schematically shows a conventional tube body connection when a separate unit of a tube body 1 is to be connected to another one, generally, a protruded edge 11 is provided at the end of the tube body 1, and the protruded edge 1 is provided with hole. A bolt 12 and a nut 13 are used to fasten the connection of the tube body 1. The drawback of such conventional design is that the height of the protruded edge 1 has to be increased and more holes have to be provided to the protruded edge 11. Thus, precision and accuracy have to be observed.
As shown in FIGS. 2 to 6, there is shown a conventional tube clip 2 comprising a tube clip body 21, an upper clip body 22, and screw rod 25. For connection or closing of the tube clip 2, as shown in FIG. 2, the lower and the upper clip body 21, 22 are closed, and the screw rod 25 is upwardly reversed onto the upper pivot slot 222 of the upper clip body 222, and a screw nut 26 is depressed. As shown in FIGS. 3 and 4, the conventional clip 2, the lower and the upper clip body 21, 22 are opened to allow the lower clip ring 211 to be inserted into the tube body 1. The drawback of the conventional tube clip is that the rotating of the screw nut is done manually is laborious and it is difficult to operate, and the longevity is limited.


An extension agent system of an ISDN electronic exchange having a switching network to which interfaces grouped into groups are connected, wherein extension agent numbers are respectively assigned to the groups of the interfaces and each interface includes a plurality of channels, has a management unit which manages first information indicating, for each interface, the number of channels being used and second information indicating, for each interface, the number of available channels. The management unit includes a table which stores third information indicating, for each of the groups of the interfaces, a sequence of the interfaces to be accessed such that one of the interfaces receives a call having the extension agent number. The system also has a control unit which selects one of the interfaces for receiving a call having the extension agent number on the basis of the first information, the second information and the third information.

1. Field of the Invention
The present invention generally relates to an ISDN (Integrated Services Digital Network) electronic exchange having a central processing unit and a storage unit, and more particularly to an extension agent system installed in such an ISDN exchange.
2. Description of the Prior Art
In an extension agent system of an electronic exchange, an extension agent number is assigned to a plurality of terminals, such as telephone sets. When a call addressed to the extension agent number is received, the terminals are searched for in a predetermined sequence in order to determine whether or not an idle terminal is available. Then, the received call is transferred to an idle terminal which is first accessed.
The basic interface of the ISDN uses a plurality of channels (2B and D) for an interface. In an extension agent system configured in conformity with the ISDN basic interface, even if one of the channels of an interface is busy, this interface is recognized to be idle when the other channel is idle. In a case where a speech terminal is connected to one of the B channel in each interface forming the extension agent system and a terminal other than a speech terminal is connected to the other channel therein, each interface is recognized to be idle even when the speech terminal connected to each interface is busy. Hence, the extension agent system cannot operate.
FIG. 1 is a block diagram of an electronic exchange having a conventional extension agent system, and FIG. 2 is a flowchart showing the operation of the conventional extension agent system. The electronic exchange shown in FIG. 1 comprises a switching network (NW) 10, a central processing unit (CC: hereinafter simply referred to as a controller) 11, and a main memory (MM) 12. Terminals A-D connected to the switch 10 belong to an extension agent group. The main memory 12 includes an extension agent table 13, which has idle/busy information 13a and hunting group information 13b. The idle/busy information 13a show whether the terminals A-D belonging to the identical agent group are respectively busy or idle. The hunting group information 13b show a sequence of hunting in order to obtain an idle terminal.
Referring to FIG. 2, the controller 11 confirms, in step S1, completion of receipt of an extension agent number assigned to the agent group having the terminals A-D. For example, the extension agent number is aft identification number of the terminal A which has priority over the terminals B-D with respect to the hunting procedure. Further, in step S1, the controller 11 translates the received number and recognizes that the received number is the extension agent number. In step S2, the controller 11 refers to the busy/idle information 13a and the handling group information 13b stored in the table 13, and determines whether the terminal A located at the top of the handling sequence is idle or busy. When the terminal A is idle, the controller 11 makes a connection between a terminal sending the call and the terminal A in step S4. When it is determined, in step S2, that the terminal A is busy, the controller 11 refers to the table 13, and selects the terminal B which has the second priority in step S3. Then, the controller 11 determines whether or not the terminal B is idle or busy in step S2. In this manner, all the terminals indicated by the hunting group information 13b are sequentially accessed until an idle terminal is found. If it is determined that all the terminals A-D are busy, the controller 11 sends a busy tone to the calling terminal.
If the above-mentioned extension agent system is applied to an ISDN electronic exchange (see CCITT Recommendation Q. 931, "ISDN USER-Network Interface Layer 3 Specification For Basic Call Control", for example), the following problem will occur. As has been described previously, one interface between an user and the network 10 includes a plurality of channels (two B channels and one D channel). Each of the subscribers A-D has two B channels respectively having a bit rate of 64 Kbps and one D channel having a bit rate of 16 Kbps. It will now be assumed that each of the subscribers A-D respectively has only a speech-system terminal (normal telephone set). In this case, the controller 11 refers to the hunting group information 13b in response to receipt of an extension agent number, and determines whether or not the subscriber A is idle or busy. If the subscriber A is communicating with another subscriber via one of the two B channels, the other B channel is idle. In this case, the controller 11 tries to make a connection between the calling terminal and the idle B channel because all the B channels are not busy. A terminal other than the speech-system terminal is not connected to the extension of the subscriber A. Hence, the controller 11 receives no response from the subscriber A, and does not make a connection with the calling terminal. That is, the controller 11 does not hunt the subscriber B.

Extension agent system of ISDN electronic exchange


The present invention relates to an optical filter for flattening the gain spectrum of an optical amplification system (including at least one optical amplifier) inserted in a transmission line for transmitting a plurality of signal light components having wavelengths different from each other, and a transmission system including the optical filter. The optical filter according to the invention has a transmission spectrum with inverse characteristics to those of the gain spectrum of the optical amplification system for amplifying the plurality of signal light components. Particularly, the transmission spectrum of the optical filter is characterized in that, in the second wavelength range narrower than the first wavelength range corresponding to the signal light wavelength range and included in the first wavelength range, the difference between the maximum loss and the minimum loss of the transmission spectrum substantially equals the difference between the maximum gain and the minimum gain of the gain spectrum of the optical amplification unit in the first wavelength range.

1. Field of the Invention
The present invention relates to an optical filter applicable to an optical fiber transmission network for realizing long-distance large-capacity transmission of signal light components having wavelengths different from each other (to be referred to as wavelength-multiplexed signal light hereinafter) and an optical transmission system having the optical filter.
2. Related Background Art
Conventionally, large-capacity high-speed communication such as image communications or long-distance communication such as international communication has been performed using an optical fiber transmission network. From the viewpoint of large-capacity high-speed communications, these recent communication techniques mainly employ wavelength division multiplexing optical transmission (WDM optical transmission) for transmitting wavelength-multiplexed signal light through an optical transmission line. In addition, from the viewpoint of long-distance communication, optical amplifiers for amplifying signal light components are sometimes arranged in the optical fiber transmission line.
An Er-doped optical fiber amplifier (EDFA) generally used as the optical amplifier can amplify wavelength-multiplexed signal light components having wavelengths within the 1.55 .mu.m wavelength band at once.
The gain spectrum, being wavelength dependant is not flat but changes depending on the wavelength of the wavelength-multiplexed signal light. Generally, the gain spectrum has a tendency to have the gain at a maximum near the center wavelength of the wavelength band of the wavelength-multiplexed signal light and becomes smaller as the wavelength shifts from the center wavelength. The wavelength band of the wavelength-multiplexed signal light is defined as a difference between a maximum wavelength and a minimum wavelength of the wavelength-multiplexed signal light.
Signal light components having wavelengths different from each other, which are outputted from the EDFA, have different intensities depending on the wavelengths. When a number of EDFAs are arranged in the optical fiber transmission line, the signal light components have a predetermined intensity at the transmission terminal of the optical fiber. At the reception terminal of the optical transmission line, however, the intensity ratio between the signal light components becomes higher. In some cases, one of a plurality of signal light components may have a sufficient intensity at the reception terminal while the remaining signal light components may have lower intensities and therefore cannot be received.
Studies have been made to arrange, in the optical fiber transmission line, an optical filter (equalizer) having a transmission spectrum (loss spectrum) for canceling the gain spectrum of the EDFA such that the gain spectrum of the entire transmission line is flattened. The transmission spectrum of this optical filter has reverse characteristics to those of the gain spectrum. The transmission loss is maximum near the center wavelength within the band of wavelength-multiplexed signal light and becomes smaller as the wavelength shifts from the center wavelength. For such an optical filter, application of a fiber grating having an appropriately designed period has been examined.
For example, a technique is disclosed in A. M. Vengsarkar et al., "Long-period fiber gratings as gain-flattening and laser stabilizing devices" in which two fiber gratings having grating periods different from each other are cascaded and used as the optical filter, and the gain spectrum of the EDFA is canceled by the transmission spectrum of this optical filter to reduce the difference between the maximum gain and the minimum gain of the gain spectrum of the entire transmission line in the band of wavelength-multiplexed signal light to 0.2 dB or less.

Optical filter and optical transmission system having the same


A desktop tape dispenser is disclosed. The desktop tape dispenser of the present invention comprises a main body portion, an adjustment portion, a stopping portion and a return portion. A rotation shaft is disposed in the lower middle part of the main body portion. The adjustment portion may be used to set the tape output length. The stopping portion is fitted in the main body portion and has a wheel piece, which extends out of the main body portion and is positioned at a level higher than that of the rotation shaft. A cutter is provided on the front part of the main body portion. A user may set the tape output length with the control piece of the adjustment portion. The desktop tape dispenser of the present invention is easy to use and can reduce the waste of the tape.

1. Field of the Invention
The invention generally relates to a desktop tape dispenser. More particularly, the invention relates to a desktop tape dispenser that allows the tape output length to be set so as to reduce the waste of the tape and make the desktop tape dispenser easier to use.
2. Description of the Prior Art
As of now, tapes have been widely used by households, stores and private companies to tape up items or seal off boxes. Also, stores and private companies use larger amount of tape than households.
Without a tape dispenser, a user has to first find the free end of a roll of tape and pull out the free end; next, he has to use a pair of scissors or a cutter to cut up the tape; then, he places the free end back onto the roll of tape. Such use is very time-consuming and very inconvenient.
Hence, desktop tape dispenser was invented. A roll of tape is held in a tape dispenser, and a cutter is disposed in the front part of the tape dispenser. In use, a user pulls out the free end of the tape and pulls the free end downwards so that a length of the tape may be cut by the cutter. After the cutting, the free end of the tape sticks to the cutter. However, the tape output length can not be set and this makes the tape dispenser difficult to use.
From the above, we can see that the desktop tape dispenser of the prior art has many disadvantages and needs to be improved.
To eliminate the disadvantages of the desktop tape dispenser of the prior art, the inventor has put in a lot of effort in the subject and has successfully come up with the desktop tape dispenser of the present invention.


A lens alignment apparatus includes a main lens holding frame having a main lens secured thereto; an adjusting lens holding frame to which an adjusting lens to be aligned with the main lens is secured; at least one radial groove formed in one of adjacent end surfaces of the main lens holding frame and the adjusting lens holding frame; a centering hole, corresponding to the radial groove, formed in the other of the adjacent end surfaces of the main lens holding frame and the adjusting lens holding frame; and an alignment member including a centering pillar portion inserted in the centering hole and an aligning portion engaged in the radial groove, the aligning portion being provided with a plurality of pairs of parallel alignment surfaces having an identical width and different distances from the axis of the centering pillar portion.

1. Field of the Invention
The present invention relates to a lens alignment apparatus for correcting disalignment of a lens.
2. Description of the Related Art
Various lens alignment apparatuses for aligning an optical axis of a main lens (lens group) with an optical axis of an adjusting lens (lens group) upon assembly are known, and have been made commercially viable. The basic concept of such prior art lens alignment apparatuses is to continuously adjust the position of the optical axis of the adjusting lens relative to the optical axis of the main lens in a stepless manner. In such a stepless type of lens alignment apparatus, the operator is free to optionally select a desired adjustment position. However, lens products tend to have the same disalignment for each lot. Nevertheless, the operator must individually carry out an adjustment for each lens product to determine a correct position from different initial positions. Therefore, such disalignment adjustment is complicated and requires an increased amount of time. Moreover, the accuracy of the adjustment becomes irregular due to differences in the operator's skill or the quality of the lens products. Furthermore, once the lens assembly is disassembled, it is practically impossible to reproduce the aligned state thereof.
In view of the drawbacks of the prior art mentioned above, the present invention provides a lens alignment apparatus in which a lens alignment can be easily performed with a minimum number of operations and in a short time.


S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parameterized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

High frequency semiconductor devices are employed to form high frequency semiconductor circuits for communication and/or logic operations. The high frequency semiconductor devices may be a metal-oxide-semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a passive device such as a capacitor or an inductor, or any other semiconductor device that requires operation at a high frequency, which is typically greater than 1 GHz.
To characterize the high frequency semiconductor devices, high frequency measurements are required. High frequency measurement on a semiconductor device requires a pad set to allow access of a probe, which may be a vector network analyzer (VNA), to the semiconductor device due to microscopic dimensions of the semiconductor device and macroscopic dimensions of the components of the probe. Thus, the probe tests the semiconductor device by transmitting signals to, and receiving signals from, the semiconductor device through the pad set. An inherent consequence of the use of the pad set is that a device test structure (DTS), or the structure tested by the probe, is not an isolated semiconductor device, which is herein referred to as an "intrinsic device" or "device under test" (DUT), but a combination of the intrinsic device and the pad set. In other words, any test data from the DUT invariably involves effects of parasitic components of the pad set that are external to the DUT. The DUT is "embedded" in the device test structure in the sense that any measurement on the intrinsic device must be performed through the entirety of the device test structure, which contains the DUT and the pad set.
Test result obtained from the device test structure includes parasitic effects of the pad set. To extract device characteristics of the DUT, the device characteristics of the inherent device need to be "de-embedded" from the measured data of the DTS since the device characteristics of the inherent device are embedded within the measured data by virtue of the embedding of the inherent device within the DTS. In general, the pad set introduces significant parasitic effects at high measurement frequencies.
Referring to FIG. 1, a DTS containing a DUT and a pad set is shown. If each of the DTS and the DUT is treated as a 2-port network respectively, the pad set that generates the parasitic effect on the intrinsic device is a 4-port network. The electrical effect of the pad set is herein referred to as the "pad set parasitics." The first port 101 of the 4-port network comprises a port of the DTS. The second port 102 of the 4-port network comprises another port of the DTS. The third port 103 of the 4-port network comprises a connection point to the DUT. The fourth port 104 of the 4-port network comprises another connection point to the DUT.
Unfortunately, the 4-port network and the DUT are unknown. All measurement data is based on measurement on the DTS as a whole. To facilitate de-embedding of the measurement data, calibration standards are used to estimate and subtract the effects of the pad set parasitics of the 4-port network. Exemplary calibration standards include an "open dummy" or an "open network," a "short dummy" or a "short network," a "thru dummy" or a "thru network," the structures and netlist representations of which are described in Table 1.
TABLE 1Physical structures and netlist representations of commondummies in prior art de-embedding methodsType ofcalibrationstandardPhysical structureNetlist representationThru dummyDUT removed from DTS4-port network with the thirdand the third port 103port 103 and the fourth portand the fourth port 104104 directly connectedare connectedOpen dummyDUT removed from DTS4-port network with the thirdport 103 and the fourth port104 openShort dummyDUT removed from DTS4-port network with the thirdand the third port 103port 103 and the fourth portand the fourth port 104104 shortedare shorted
Traditionally, de-embedding is performed in two steps. Commonly used prior art de-embedding method is open-short (O-S) de-embedding, which requires two additional calibration standards of an open dummy and a short dummy. The open-short de-embedding simplifies the 4-port network by assuming that dominant parasitics are either near the probe pad or near the DUT, and are not distributed.
Referring to FIG. 2, an equivalent circuit for the 4-port network according to the O-S de-embedding method is shown. The equivalent circuit according to the O-S de-embedding comprises a first open parasitics component 210A, a second open parasitics component 210B, and a third open parasitics component 210C. The first open parasitics component 210A is connected directly between the two nodes of the first port 201 of the 4-port network, which is a first port of the DTS. The second open parasitics component 210B is connected directly between the two nodes of the second port 202 of the 4-port network, which is a second port of the DTS. The third open parasitics component 210C is connected between a signal node (marked with a "+" sign, as opposed to a ground node that is marked with a "−" sign) of the first port 201 of the 4-port network and a signal node of the second port of the 4-port network.
The equivalent circuit according to the O-S de-embedding further comprises a first short parasitics component 220A, a second short parasitics component 220B, and a third short parasitics component 220C. The first short parasitics component 220A is connected directly between the signal node of the first port 201 of the 4-port network and a signal node of the third node 203 of the 4-port network, which is a first port of the DUT. The second short parasitics component 220B is connected directly between the signal node of the second port 202 of the 4-port network and a signal node of the fourth node 204 of the 4-port network, which is a second port of the DUT. The third short parasitics component 220C is connected directly between the combined ground nodes (between which no parasitic components are assumed to be present in the O-S de-embedding method) of the third and fourth ports (203, 204) of the 4-port network and the combined ground nodes (between which no parasitic components are assumed to be present in the O-S de-embedding method) of the first and second ports (201, 202) of the 4-port network.
Referring to FIG. 3, a prior art open-short (O-S) de-embedding method is shown in a flow chart. Referring to step 310, scattering parameter (S-parameter) data is measured on the embedded device test structure containing the device under test (DUT) and the pad set. Scattering parameters are parameters that describe electrical behavior of a linear electrical network subjected to steady state stimuli by small electrical signals. In general, various electrical properties of the linear electrical network such as signal gain, return loss, voltage standing wave ratio, refection coefficient, and amplifier stability may be described with S-parameters. The idea behind the S-parameters is that the response of the linear electrical network may be considered as scattering of an input signal within the linear electrical network. Of particular concern for estimating the pad set parasitics with the prior art O-S de-embedding method are Y-parameters that represent admittance of the 4-port network and Z-parameters that represent impedance of the 4-port network.
Referring to step 320, the measured S-parameters are converted to Y-parameters. Methods of converting S-parameters to Y-parameters in a 2-port network are known in the art. Specifically, U.S. Pat. No. 7,075,312 to Fabry et al., U.S. Pat. Nos. 7,026,829 and 7,071,707 to Tiemeijer, U.S. Pat. No. 6,961,669 to Brunsman, U.S. Pat. Nos. 6,832,170 and 6,665,628 to Martens, U.S. Pat. No. 6,815,964 to Di Gregorio et al., and U.S. Pat. No. 6,211,541 to Carroll et al. are incorporated herein. It is noted that the S-parameters, Y-parameters, and Z-parameters of a 2-port network are given by 2×2 matrices.
Referring to step 330, calculations for subtracting open parasitics, i.e., the collective parasitics of the first open parasitics component 210A, the second open parasitics component 210B, and the third open parasitics component 210C, are performed at a predetermined frequency. The first operation calculates an open de-embedded DTS admittance YDTS—OP—DEEM, which is the admittance of the set of the DUT and the short parasitics, i.e., the collective parasitics of the first short parasitics component 220A, the second short parasitics component 220B, and the third short parasitics component 220C. The open de-embedded DTS admittance, YDTS—OP—DEEM is given by:YDTS—OP—DEEM=YDTS−YOPEN,  (Equation 1)wherein YDTS is the calculated admittance of the DTS that contains the DUT, the open parasitics, and the short parasitics, and wherein YOPEN is the calculated admittance of an open dummy that is supposed to contain only the open parasitics. The calculated admittance of the DTS YDTS and the calculated admittance of the open dummy, YOPEN are based on the S-parameters of the DTS and the open dummy that are measured at the predetermined frequency.
The second operation calculated a short de-embedded DTS admittance YSHORT—OP—DEEM, which is the admittance of the short parasitics that contains the collective parasitics of the first short parasitics component 220A, the second short parasitics component 220B, and the third short parasitics component 220C. The short de-embedded DTS admittance, YSHORT—OP—DEEM is given by:YSHORT—OP—DEEM=YSHORT−YOPEN,  (Equation 2)wherein YSHORT is the calculated admittance of a short dummy that is supposed to contain the open parasitics and the short parasitics. The calculated admittance of the short dummy, YSHORT is based on the S-parameters of the short dummy that are measured at the predetermined frequency.
Referring to step 340, a DUT Z-parameter, which is the Z-parameter of the DUT, is calculated. The DUT Z-parameter ZDUT is given by:ZDUT=Y−1DTS—OP—DEEM−Y−1SHORT—OP—DEEM,  (Equation 3)wherein Y−1DTS—OP—DEEM is the inverse matrix of the open de-embedded DTS admittance YDTS—OP—DEEM and Y−1SHORT—OP—DEEM is the inverse matrix of the short de-embedded DTS admittance, YSHORT—OP—DEEM.
Referring to step 350, the DUT Z-parameter ZDUT is converted back to an S parameter. It is noted that the manipulation of measured S-parameters is done for the preset frequency and that there is no fitting or any variable parameter in the prior art O-S de-embedding method. Thus, execution of one round of the calculation process provides DUT Z-parameter ZDUT at one frequency. To generate a frequency dependent profile for DUT Z-parameter ZDUT, the calculation process is repeated at multiple frequencies one frequency at a time.
While the open-short (O-S) de-embedding method provides a simple scheme for estimating the pad set parametrics, the assumption on dominant parametrics and nature of distribution of the pad set parametrics is not true in many cases, and introduces significant errors especially at high frequency, e.g., in GHz frequency ranges and above. This problem becomes more profound in noise de-embedding particularly in bulk complementary metal-oxide-semiconductor (CMOS) technology, which employs a bulk substrate that induces a large signal loss.
Some other de-embedding techniques have been proposed in the prior art to enhance accuracy of estimation of the 4-port network representing the pad set parasitics. For example, a "three step" de-embedding method employing 3 calibration standards and assuming a 9 element network for the 4-port network is known in the art. U.S. Patent Application Publication No. 2006/0114004 A1 to Tiemeijer that discloses the three step de-embedding method is herein incorporated by reference. A 4-port de-embedding method employing 4 to 6 calibration standards and assuming a 15 element network for the 4-port network is also known in the art. Q. Liang, et al., "A Simple Four-Port Parasitic Deembedding Methodology for High-Frequency Scattering Parameter and Noise Characterization of SiGe HBTs," IEEE Trans. Microwave Theory and Techniques, v. 51, n. 11, pp. 2165-2174 (2003) that discloses the complete de-embedding method is herein incorporated by reference. However, use of additional calibration standards to enhance accuracy of the de-embedding increases device characterization cost both by increasing a total test structure area on a semiconductor chip and by increasing the complexity of testing and data analysis. While benefits of use of increased number of calibration standards are known, the prior art methods also incur significant increase in cost, oftentimes rendering the characterization methods uneconomical.
In view of the above, there exists a need for an improved system and methods for representing the 4-port network of the pad set with an enhanced accuracy in the estimation of the of the pad set parasitics.
Further, there exists a need for an improved system and methods for de-embedding a device test structure in which a device under test (DUT) is embedded to extract device characteristics of the DUT with an enhanced accuracy.

System and method for de-embedding a device under test employing a parametrized netlist

International Business Machines Corporation


A printer (103) belongs to a service set (107) and communicates via an access point (101) in the infrastructure mode. The printer (103) searches for a beacon periodically. If a beacon is received from a terminal such as a digital camera (104), the printer registers the terminal address, service-set identifier and communication mode, which are contained in the beacon, in a function table. The printer sends each terminal, which has been registered in the function table, a frame that is for searching for a terminal that has a required function. If the response to the frame is positive, then the printer registers the fact that the search succeeded in the function table. A similar function search is conducted also by a digital camera (104) for which a print command has been issued, and the digital camera creates a function table. If there is a terminal (a printer) having the required function, the digital camera (104) transmits print data to this terminal.

A communication method that provides a first communication mode (infrastructure mode), in which wireless communication is performed between terminals via a master station, and a second communication mode (ad-hoc mode), in which data is sent and received directly between terminals, is defined by the IEEE 802.11 standard.
In the IEEE 802.11 standard, the frequency band utilized in communication is divided into 14 channels to thereby define a plurality of channels. Wireless communication terminals that utilize a common channel are capable of communicating with each other. An SSID (Service Set ID), which is an identifier for identifying the network, is specified. All wireless communication terminals retain a predetermined SSID and thus can identify the network.
A communication terminal that performs wireless communication in accordance with IEEE 802.11 (this terminal will be referred to simply as a "wireless communication terminal" below) transmits a beacon frame at prescribed timing. The beacon frame includes a channel ID that indicates the channel currently operating, the SSID of the network to which the apparatus belongs, and the communication mode. By passive or active scanning, a wireless communication terminal finds a wireless communication terminal with which it is to communicate. In passive scanning, for example, a beacon frame that includes an SSID identical with the terminal's own SSID is searched for by scanning the radio signal of each channel. A wireless communication terminal that has received the applicable beacon frame decides upon the channel that corresponds to the channel identifier contained in this beacon frame, or the channel that received this beacon frame, as the channel used in its own communication.
In active scanning, on the other hand, a wireless communication terminal broadcasts a frame, which is referred to as a "probe request", on each channel. In response, another wireless communication terminal that has received the probe request transmits a frame, which is referred to as a "probe response", to the wireless communication terminal that is the source of the probe request. The probe response includes the ID of the channel currently operating on the wireless communication terminal, the SSID and the communication mode. The wireless communication terminal that has received the probe response decides upon the channel that corresponds to the channel identifier contained in the probe response included in the SSID identical with that of this wireless communication terminal, or the channel that received the probe response, as the channel used in its own communication.
An autonomous distributed coordination method referred to as CSMA/CA and a centralized control method referred to as polling have been specified as access control methods in the infrastructure mode according to IEEE 802.11. On the other hand, in the ad-hoc mode, the access control method is such that only the autonomous distributed coordination method is specified. Owing to distributed control in the ad-hoc mode, data is sent and received directly between terminals. Among all terminals participating in communication at beacon transmission time decided by the beacon interval, at least one terminal transmits a beacon frame in the ad-hoc mode.
In the ad-hoc mode, a communication link is established between terminals if the channels used in communication between the terminal become the same, without the sending and receiving of an authentication frame and without the sending and receiving of an association request/association response.
Many methods of switching between the infrastructure mode and ad-hoc mode have been proposed heretofore. A method of changing over the mode when the processing capability of an access point no longer has any leeway is described in the specification of Japanese Patent Application Laid-Open No. 08-307934. The specification of Japanese Patent Application Laid-Open No. 11-252114 describes a method in which each station (wireless communication terminal) retains a list of stations capable of transferring data in the ad-hoc mode, with data being transmitted in the ad-hoc to stations in the list and in the infrastructure mode to stations not in the list. A method of changing over the access point depending upon the data rate of a mobile terminal is described in the specification of Japanese Patent Application Laid-Open No. 2000-209234. A method of changing over the access point in accordance with load information contained in a beacon is described in the specification of Japanese Patent Application Laid-Open No. 2001-298467. A method of changing over mode using the average frame size of a data frame as a trigger is described in the specification of Japanese Patent Application Laid-Open No. 2003-198564. A method of monitoring data reception in both communication modes and performing communication in the mode in which data was received is described in the specification of Japanese Patent Application Laid-Open No. 2002-199461.
Further, a method of changing an interval at which beacon scanning is performed has been proposed as a method of searching efficiently for a terminal to which a connection is to be made (see the specification of Japanese Patent Application Laid-Open No. 10-084572). However, this specification makes no mention of changeover of the communication mode.
In order for a user of a wireless communication terminal compliant with IEEE 802.11 to connect this terminal to the Internet, the access point is connected to the Internet in advance. The wireless communication terminal is connected to the network in the infrastructure mode.
In a network of this kind, a first wireless communication terminal that belongs to the same network (same service set) attempts to transmit data to a second wireless communication terminal that is performing communication in the infrastructure mode. In this case, the access point receives the data from the first wireless communication terminal temporarily and re-transmits it to the second wireless communication terminal. As a consequence, the sending and receiving of data takes time. Since both the first wireless communication terminal and the second wireless communication terminal can be connected to the Internet via access points, sufficient security measures must be taken with regard to illegal penetration from the Internet and leakage of information to the Internet.
Accordingly, performing communication upon changing over to the ad-hoc mode by a method of the kind illustrated in the prior art even in a case where communication is being performed in the infrastructure mode has been considered.
However, even if data can be sent and received in a link layer, the sending and receiving of meaningful data cannot be performed upon changing over the communication mode from the infrastructure mode to the ad-hoc mode unless there is data interchangeability with higher layers, namely the IP layer, transport layer or application layer.

Communication control method and wireless communication apparatus


Techniques and mechanisms are provided to monitor signals including critical signals at the endpoints, or leaves, of one or more signal trees in an integrated circuit device. Sensors or layers of sensors may be configured in fault detection circuitry to monitor signals and compare them to static or dynamically varying values. The fault detection circuits may include OR-gate daisy chains that output a fault detection signal to control circuitry if any signal at a particular leaf deviates from an expected signal. Fault detection circuits may also be configured to identify instances where two or more or N or more signals deviate from an expected signal. Mechanisms may also be provided to assure the reliability of fault detection circuitry itself.

A variety of systems and applications have high assurance specifications. For example, the Fail Safe Design Assurance (FSDA) specifications require that a single fault, such as an electrical open or short, not cause more than one region of device to malfunction in an undetected manner. Many existing solutions for meeting high assurance specifications involve using physically separate devices to provide isolation of functionality. In a conventional system, multiple devices having the same configuration and performing the same operations may provide outputs that are compared. If the outputs do not match, a fault is determined to have occurred.
However, using separate devices performing the same operations to determine whether a fault has occurred is inefficient in terms of system size, power consumption, weight, and cost. Single device solutions are limited, and do not sufficiently provide high assurance for signal lines. Single device solutions are also inefficient in terms of device size and power consumption.

Methods and apparatus for automatic fault detection


What is described is a trinucleotide cap analog comprising m7G(5′)p3-N1pN2 for increased efficiency of in vitro transcription of m7G(5′)p3-RNA, wherein m7G is N7-methylguanosine or analog, (5′)p3 is a 5′,5′-triphosphate bridge, and N1 or N2 or both ribonucleotide analogs linked to each other by a phosphate, p, and wherein the trinucleotide cap analog increases the efficiency of in vitro transcription.

Eukaryotic mRNAs have a cap structure at their 5′-termini. The cap consists of 7-methyl guanosine (m7G) and a triphosphate bridge, ppp (p3), linking the 5′OH of m7G to the 5′OH of the 5′-terminal nucleotide, N, denoted m7G(5′)pppN (m7G(5′)p3N). In eukaryotic cells, the cap structure participates in assembly of the translation initiation complex by binding eukaryotic translation initiation factor 4E (eIF-4E).
Although m7G(5′)p3 can be used to initiate transcription with T7 or SP6 DNA-dependent RNA polymerase in vitro, it has the disadvantage of having to compete with guanine nucleotide (G) as the initiating nucleophile for transcriptional elongation. As a result of this competition, less than half of mRNA produced in vitro have a cap structure at their 5′ termini.
Dinucleotide m7G(5′)p3(5′)G, in which a guanine nucleotide (G) is linked via its 5′OH to the triphosphate bridge, has been used as an initiator of transcription. This dinucleotide has the disadvantage that the 3′-OH of either the m7G or G moiety serves as the initiating nucleophile for transcriptional elongation that results in synthesis of two isomeric RNAs of the form m7G(5′)p3G(pN)n and G(5′)p37G(pN)n, with one third to one half of the caps oriented in the reverse direction, depending upon the ionic conditions of the transcription reaction. Further improvement of the orientation of the cap during in vitro transcription is possible using cap analogues that replace the 3′-OH group with hydrogen or —OCH3 (U.S. Pat. No. 7,074,596; Kore, 2006, Nucleotides, Nucleotides, and Nucleic Acids, 25: 307-14, and Kore, 2006, Nucleotides, Nucleotides, and Nucleic Acids, 25: 337-40).
Dinucleotide GG cap analogs m7G(5′)p3G and 3′-OMe-m7G(5′)p3G (ARCA) are sold commercially by TriLink BioTechnology, MilliporeSigma, ThermoFisher Scientific, and New England BioLabs Inc. 3′-OMe-m7G(5′)p3G (ARCA) is incorporated during transcription without reversal to G(5′)p3 m7G.
Trinucleotide cap analogs were disclosed by Ishikawa, 2009, Nucleic Acid Symp. Ser., 53:129-30. These are as follows:                m7G(5′)p3ApG, corresponding to the terminal trinucleotide of plant RNA;        m7G(5′)p3AmpG (Am is adenine with a 2′OMe-ribose), corresponding to the terminal trinucleotide of animal RNA;        m7G(5′)p3m6AmpG (m6A is N6-methyladenine), corresponding to the terminal trinucleotide of mammal RNA; and        m7G(5′)p3m6ApG, an unnatural trinucleotide.Ishikawa discloses that translational efficiency in a rabbit reticulocyte lysate system is greatest with mRNA transcribed with an animal-type, followed by a mammalian-type, the unnatural, and the plant-type cap structures, respectively, and that G(5′)p3Ampm7G-RNA, a result of transcribing in a reverse orientation, was not obtained. Id.
In view of the disclosure of these publications, there remains a need to identify modified cap structures that improve the efficiency of in vitro transcription.


The present invention is directed to a multi-compartment autoclave using inter-compartment dividers having one or more underflow openings for passing a feed stream between compartments.

Autoclave reactors have a wide range of applications in chemical processes. A typical autoclave has one or more compartments and operates at elevated pressures and temperatures. Most autoclaves are heated by steam injection, autogenous heat generated by reactions within the autoclave, or by a combination of both.
In most applications, autoclaves are stirred, multi-compartment reactors. An example of a multi-compartment, cylindrical autoclave is shown in FIGS. 1 and 2. The reactor 100 has a plurality of compartments 104a-f, each compartment 104 having at least one agitator 108a-g. In most applications, the agitators 108a-g rotate in the same direction. Adjacent compartments 104a-f are separated by a divider 112a-3 configured as an overflow weir. The input slurry 116 moves from compartment to compartment by overflowing the weirs as shown by the arrows in FIG. 1. To permit cascading flow of the slurry from compartment to compartment, the liquid level in the various compartments varies in a step-wise fashion, with the first compartment 104a having a higher liquid level than the second compartment 104b, the second compartment 104b having a higher liquid level than the third compartment 104c, and so on, with the sixth compartment 104f having the lowest liquid level.
An example of an overflow weir-type divider 112 is shown in FIG. 2. The divider 112 is cylindrically shaped to match the cylindrical profile of the autoclave and has a notch 200 located at the top of the divider. Liquid flows though the notch to move to the next (downstream) compartment. There is a sufficient height differential between notches in consecutive overflow weirs so that backmixing of liquid cannot occur and positive flow and flow through the vessel is maintained. To provide the desired step-wise gradient in liquid levels from compartment to compartment, the heights of the notches 200 in the compartments vary in the same manner as the liquid level, with the notch 200 in the first divider 112a between the first and second compartments being higher than the notch 200 in the second divider 112b, which in turn is higher than the notch in divider 112c and so on.
An example of a typical chemical reaction for an autoclave reactor is the pressure oxidation of sulfide sulfur to cause dissolution and/or liberation of base and precious metals from sulfide sulfur compounds. Pressure oxidation is typically performed by passing the input slurry 116, which contains a base and/or precious metal-containing material (such as base and/or precious metal ores and concentrates), through the sealed autoclave (operating at superatmospheric pressure) and sulfuric acid. To provide for oxidation of the sulfide sulfur in the slurry, a molecular oxygen-containing gas 120 is typically fed continuously to the autoclave by means of a sparge tube (not shown) located below each agitator. The molecular oxygen and elevated temperature cause relatively rapid oxidation of the sulfide sulfur to form sulfuric acid and the metal sulfides to form metal sulfates, which are soluble in the acidic slurry, thereby forming a pregnant leach solution. The pregnant leach solution, which commonly contains from about 10 to about 100 grams/liter sulfuric acid, from about 5 to about 100 grams/liter dissolved metal, and from about 4 to about 50% solids by weight, is removed from the last compartment of the autoclave as an output slurry 124. Additional details about this process are discussed in U.S. Pat. No. 5,698,170 to King, which is incorporated herein by reference. To maintain a desired pressure and atmospheric gas composition in the autoclave, the gas in the autoclave is continuously or periodically vented as an off gas 128. One autoclave configuration is discussed in U.S. Pat. Nos. 6,368,381 and 6,183,706.
In designing an autoclave reactor, there are a member of considerations. For example, it is desirable that the slurry have an adequate residence time in each of the compartments. Short circuiting, or moving to the next compartment with an unacceptably short residence time in a compartment, can cause a substantial decrease in metal extraction levels. For best results, the Residence Time Distribution or RDT in each compartment should be as close as possible to ideal plug flow conditions. It is desirable to have, in each compartment, sufficient power input and mixing efficiency to provide a high degree of reaction of the molecular oxygen with sulfide sulfur. To provide a high mixing efficiency, it is common practice to impart high levels of power to the agitators, thereby causing a highly turbulent surface in each compartment.


A disclosed thin light-emitting interface displays may be mounted to a surface on the gaming machine. The light-emitting elements used in the interface displays may be provided from electro-luminescent elements, organic light emitting diode (OLED) elements and combinations thereof. The thin light-emitting interface displays may be used to input and output gaming information on the gaming machine. The gaming information that is input and output via the interface display may be used to provide: 1) a game of chance played on the gaming machine, 2) player tracking services, 3) game services available on the gaming machine and 4) attract features. In one embodiment, a game input interface display is provided with a plurality of input buttons where a number and a format of the input buttons are dynamically configurable for different types of games of chance played on the gaming machine.

This invention relates to interfaces for gaming machines such as video slot machines and video poker machines. More particularly, the present invention relates to light-emitting interface displays using electro-luminescent elements and/or organic light emitting diode elements for providing player tracking interfaces and game playing interfaces.
There are a wide variety of associated devices that can be connected to a gaming machine such as a slot machine or video poker machine. Some examples of these devices are player tracking units, lights, ticket printers, card readers, speakers, bill validators, ticket readers, coin acceptors, display panels, key pads, coin hoppers and button pads. Many of these devices are built into the gaming machine or components associated with the gaming machine such as a top box which usually sits on top of the gaming machine.
Typically, utilizing a master gaming controller, the gaming machine controls various combinations of devices that allow a player to play a game on the gaming machine and also encourage game play on the gaming machine. For example, a game played on a gaming machine usually requires a player to input money or indicia of credit into the gaming machine, indicate a wager amount, and initiate a game play. These steps require the gaming machine to control input devices, including bill validators and coin acceptors, to accept money into the gaming machine and recognize user inputs from devices, such as button pads and levers, to determine the wager amount and initiate game play.
After game play has been initiated, the gaming machine determines a game outcome, presents the game outcome to the player and may dispense an award of some type depending on the outcome of the game. A game outcome presentation may utilize many different visual and audio components such as flashing lights, music, sounds and graphics. The visual and audio components of the game outcome presentation may be used to draw a players attention to various game features and to heighten the players interest in additional game play. Maintaining a game player's interest in game play, such as on a gaming machine or during other gaming activities, is an important consideration for an operator of a gaming establishment.
One related method of gaining and maintaining a game player's interest in game play may be to provide a gaming machine with a plurality of games. Traditionally, gaming machines have provided only a single game. When the game player has been playing a game on a first gaming machine and desires to play a different type of game, the player must physically leave the first gaming machine and locate a second gaming machine at the gaming location, such as a casino, that offers the different type of game in which they are interested in playing. When the player is allowed to select games for game play at the same gaming machine, the game player may participate in game play for a longer time. Therefore, it is desired within the gaming industry to provide gaming machines with the capability to offer multiple games that may be selected by the player.
One difficulty with providing a gaming machine with different games is that different games may require different inputs. For instance, a multi-payline slot game may require different inputs than a single payline slot game. As another example, a video black jack game may require different inputs than a slot game or a video poker game. Therefore, a design for an input interface may be complicated by different inputs required for different games. In view of the above, it would be desirable to provide apparatus and methods for a gaming machine input interface that may be used with many types of games.
Another related method of gaining and maintaining a game player's interest in game play are player tracking programs which are offered at various casinos. Player tracking programs provide rewards to players that typically correspond to the player's level of patronage (e.g., to the player's playing frequency and/or total amount of game plays at a given casino). Player tracking rewards may be free meals, free lodging and/or free entertainment. These rewards may help to sustain a game player's interest in additional game play during a visit to a gaming establishment and may entice a player to visit a gaming establishment to partake in various gaming activities.
Player tracking cards and player tracking programs are becoming more and more popular. They have become a de facto marketing method of doing business at casinos. The programs allow a casino to identify and reward customers based upon their previous game play history. In particular, a goal of the casinos is to identify and then to provide a higher level of service to certain groups of players identified as especially valuable to the casinos. An incentive of a casino for providing these services is to generate "brand" loyalty, and thus, repeat business from its valued customers. For instance, players that visit the casino, on average, once a week may be deemed as "special" customers and the casino may desire to cultivate a "special" relationship with these customers. In general, the selection of gaming services offered to players via loyalty programs, such as player tracking programs, is increasing. Also, the gaming services offered to a particular player are becoming more focused based upon the desires of a particular player.
A disadvantage of current player tracking units is that the player interface is not necessarily suited for providing increasingly complex and diverse gaming services to game players that are customized to an individual player's preferences. Further, it is not easy to modify current player tracking interfaces to enable them to provide new game services. In view of the above, it would be desirable to provide apparatus and methods for a player tracking unit interface that allows it to be configured for a diverse range of gaming services and is upgraded easily.

Light emitting interface displays for a gaming machine


Nut and bolt holder sockets for standard socket wrenches wherein legs, beams, cams and resilient means are used on different embodiments for accepting, retaining and releasing a nut inside a standard socket wrench to aid the user in the installation and removal of nuts and bolts in hard to reach places, specifically inside cavities where only a standard socket wrench extension can reach.

At the present time there are several types of fastener holders, Some are for holding nuts in open end wrenches, like U.S. Pat. No. 4,406,188--Blaine N. Mills and U.S. Pat. No. 4,787,273--Donald J. Griffith. These two devices are fine if the wrench has access to the nut from the side, but if the nut is inside a cavity where an open wrench can not reach, this tool would be useless.
The same applies to U.S. Pat. No. 3,507,172--James H. Smith, Pat. No. 2,722,148--Thomas M. Woyton and U.S. Pat. No. 2,664,772--Howard R. Elliot. These can only be used when the nut is accessible from the side by the wrench.
Other inventions like U.S. Pat. No. 4,939,959--Stephen Rokita, are designed to hold screws onto screw drivers. It is obvious that this tool can not help in the installation of nuts or bolts because nuts and bolts do not have grooves which are needed for a screw driver to perform its job.
Another device like U.S. Pat. No. 3,232,148--James C. Dearing, is a good tool to hold a nut in place when a bolt is screwed into a nut, but it can not be used to install a nut into a fixed stud.
With our invention, the same socket that rotates the nut and tightens the nut will have the capability of holding the nut or bolt in place during installation in hard to reach places, specifically inside cavities. Our tool does not need access from the side of the nut and it does not require getting the nut started with one tool and changing tools to tighten it with another tool, therefore saving time.
Our tool is excellent because it can be used with socket wrenches presently being used by mechanics.


An embedded magnet type motor is disclosed. The rotor core of the motor has radially extending first accommodation holes and V-shaped accommodation holes. Each V-shaped accommodation hole includes a second accommodation hole and a third accommodation hole. A first gap is formed in each first accommodation hole. The first gap is not occupied by the corresponding first magnet. A second gap is formed in each second accommodation hole. The second gap is not occupied by the corresponding second magnet. A third gap is formed in each third accommodation hole at a radially outer portion. The third gap is not occupied by the corresponding third magnet. Each second gap and the adjacent third gap form one V-shaped gap. The angular width θa of each first gap and the angular width θb of each V-shaped gap are determined to satisfy the expression: 0.60<θa/θb<1.60.

The present invention relates to an embedded magnet type motor.
Conventionally, a rotor core of an embedded magnet type motor has a plurality of accommodation holes aligned in the circumferential direction, and the accommodation holes perforate through the rotor core axially. In the accommodation holes, magnets are accommodated.
In the embedded magnet type motor disclosed in Japanese Laid-Open Patent Publication No. 2005-51982, each of a plurality of magnetic poles includes a pair of magnets arranged in a V shape to protrude radially inward. Specifically, when the number of magnetic poles of the embedded magnet type motor is P, the number of magnets is 2P. With this construction, a higher torque can be realized in comparison with a motor in which one magnet is provided per one magnetic pole.
However, when two magnets are provided per one magnetic pole, the number of parts increases and parts management cost and assembly cost also increase.
In the embedded magnet type motor of the publication described above, an outer bridge is formed between the radially outer end of each accommodation hole for accommodating a magnet and the outer peripheral surface of the rotor core. Two outer bridges are provided per one magnetic pole. Therefore, leakage fluxes passing through the outer bridges are excessive as a whole of the motor. This reduces the effective fluxes of the embedded magnet type motor and obstructs the torque increase.

This patent is subject to a terminal disclaimer.


A sheet housing part of a sheet handling machine is provided with a guide member for adjusting a size of a housing space of the sheet housing part. A tip end part of the guide member is made pivotable, and is provided with a biasing member for swinging the tip end part in a direction of a side wall of the sheet housing part. A gap provided between the guide member and an inner wall of the sheet housing part is closed with this construction, and thereby, a foreign matter is prevented from entering this gap.

The present invention relates to a sheet handling machine for handling sheets such as banknotes, and particularly to a sheet handling machine having a sheet housing part in which the size of a housing space for piling up and housing sheets is adjustable in accordance with the size of the sheets which are handled.


Annular mask lens for vision correction having diffraction-reducing edges. The lens body having an annular mask that forms a "soft edge" by gradually decreasing the transmissivity radially from the center aperture to the annular mask area.

Contact lenses are commonplace today. Most individuals with average refractive errors can quickly and easily acquire and use these lenses in place of prescription eye glasses. This is not true, however, for individuals who are presbyopic (i.e., those requiring multi-focal visual correction) or for those individuals with structural eye abnormalities. These individuals are left with little choice in selecting comfortable, effective contact lenses. Lenses which are available typically encumber these wearers with other difficulties, and are usually very expensive. Presbyopic individuals, for example, who choose to wear soft contact lenses are usually fitted in a "monovision" mode, where one eye is corrected for near vision, and the other eye is corrected for far vision. Notwithstanding the availability of such multifocal lenses, such lenses are not versatile in supplying simultaneous clear distance/near vision and are not commercially successful.
The long felt need to develop more versatile multifocal lenses has led designers to "pinhole" contact lenses (e.g., PCT Publication No. W095/08135 published Mar. 23, 1995). These lenses endeavor to utilize the known theories of pinhole imaging as a method to reduce or eliminate visual deficiencies. An annular mask with a clear center aperture of various sizes (conventionally up to 4 millimeters in diameter) is used to increase the depth of focus of presbyopic individuals. Unfortunately, the utility of this technology has been diluted because of designs and approaches inappropriate for effective corrective refractive prescriptions. For upwards of 50 years, pinhole contact lenses have been under consideration, yet they remain today commercially unsuccessful and largely unavailable. One of the principle reasons conventional pinhole contact lenses have been ineffective is that they suffer from diffraction effects at the sharp demarcation where the pinhole aperture stops and the opaque mask surrounding the aperture begins.
"Multiple Focal Contact Lenses", as described in U.S. Pat. No. 3,794,414, was one attempt to develop small-aperture contact lenses. This approach combined a pinhole-like aperture with radial slits and scalloped masking regions on a contact lens supposedly to correct both peripheral vision and the effects related to decentered contact lenses. The masked contact lenses were made from a rigid substrate, and "floated" on the eye, creating a need for apertures over a large portion of the lens. The disclosed designs though (i.e., the use of scalloped patterns and radial slits) actually encourage diffraction effects at the retina. This reduces image quality. The purpose of pinhole aperture correction is to correct geometrical aberrations in excess of diffraction. Therefore, the benefits achieved according to that patent by incorporating the pinhole aperture, are likely to be offset by undesirable diffraction effects.
Pinhole correction together with the normal functioning of the human pupil is considered in U.S. Pat. No. 4,955,904, which presents a masked intraocular lens surgically implanted within the eye. The patent, entitled "Masked Intraocular Lens and Method for Treating a Wearer With Cataracts", affords cataract wearers some form of vision correction through surgery. The intraocular lens is masked to form a pinhole that accommodates the function of the human pupil under different lighting conditions. However, the intraocular lens of that patent is also likely to be offset by undesirable diffraction effects created by the sharp demarcation at the junction of the pinhole and the opaque mask. U.S. Pat. No. 5,245,367 issued to Miller et al. discloses an annular mask contact lens wherein the optical opacity of the mask region can vary within the lens.

Annular mask lens having diffraction reducing edges


CMOS image sensors are provided. A CMOS image sensor may include a semiconductor substrate including a light-receiving region and a logic region adjacent the light-receiving region. The CMOS image sensor may include a photoelectric conversion region in the light-receiving region. Moreover, the CMOS image sensor may include an isolation region including an interface with a sidewall of the photoelectric conversion region. The isolation region may include a first refractive index that is smaller than a second refractive index of the semiconductor substrate, and the isolation region may be between the logic region and the sidewall of the photoelectric conversion region.

The present disclosure herein relates to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors. An image sensor is a device that converts optical images into electrical signals. With increased development of the computer and communications industries, there is an increased demand for high performance image sensors in a variety of applications such as digital cameras, camcorders, personal communication systems, gaming machines, security cameras, micro-cameras for medical applications, and/or robots.
CMOS image sensors may be operated using a relatively simple operation method and may be configured to have signal processing circuits integrated on a single chip, thus enabling products that include the CMOS image sensors to be scaled down. In addition, CMOS image sensors may operate with relatively low power consumption. Thus, CMOS image sensors may be applicable to portable electronic devices. Furthermore, CMOS image sensors may be fabricated using CMOS fabrication techniques, which may reduce manufacturing costs. Moreover, CMOS image sensors may provide high resolution images. Accordingly, the use of CMOS image sensors has increased.

CMOS image sensors including an isolation region adjacent a light-receiving region


A copolymer derived from a monomer mixture that includes monomers having the formulas: (A) and (B) wherein: Q is O or N; R10 is H or CH3; R11 is an organic group comprising a hydrolyzable silyl group; R12 is H or CH3; P is: (I); R1 is selected from H, an alkyl group, an aryl group, and a combination thereof; R2 is selected from an alkyl group, an aryl group, a combination thereof, and a Rf—Y—(CH2)x— group; Rf is a perfluorinated alkyl group; Y is selected from a bond, —S(O)2—N(CH3)—, —S(O)2—N(CH2CH3)—, —S(O)2—O—, —S(O)2—, —C(O)—, —C(O)—S—, —C(O)—O—, —C(O)—NH—, —C(O)—N(CH3)—, —C(O)—N(CH2CH3)—, —(CH2CH2O)y—, —O—, and —O—C(O)—CH═CH—C(O)—O—; n is an integer of greater than 2; x is an integer of at least 2; and y is an integer of at least 1.

Prevention of biofouling remains a challenging problem in numerous areas. These include, but are not limited to, biomedical applications, marine coating technologies, water filtration, transport, and storage systems. Undesirable consequences of this ubiquitous problem can include reduction in the efficacy/sensitivity of devices, operational losses, thrombosis, as well as microbial infections. Therefore, the development of new technologies and materials that reduce or completely prevent any undesired deposition of microorganisms is of great importance. However, tailoring an efficient non-fouling material requires understanding the interactions involved, which is hindered by the complexity of the process, making it challenging to provide solutions to the problem.
Biofilm formation generally starts within seconds following implantation of a given material (e.g., medical implant) in aqueous environments, such as blood, municipal and/or sea water. While biofilms can be formed by a single species, often they are composed of a community of different types of microorganisms. The first step of the process is often the adsorption of proteins on the substrate surface, which is followed by adsorption of a cascade of larger, more complex species that include microorganisms such as bacteria, fungi, and algae. Thus, one can argue that the larger microorganisms rarely interact with the clean surface but rather with the proteins adsorbed on it. One approach that has been employed to prevent the biofoulmg process is the incorporation of antimicrobially active ingredients into materials. This can be done by blending actives into the material during its manufacture, covalently attaching an active agent to the surface of the material, or coating/painting an antimicrobial onto a surface such that it can subsequently leach from the material. However, once a certain amount of organic material (e.g., cell debris) has formed, the surface activity decreases as the active material can no longer reach its target. An alternative approach is to prevent biofoulmg by preventing the attachment of a broad range of species, rather than killing them.
A key challenge in preventing biofilm formation is the design of smart materials or engineered surfaces that can effectively resist the irreversible attachment of a wide variety of species including proteins, microbial cells, and spores. Many approaches have been investigated, and hydrophilic modification of surfaces using polyethylene glycol) (PEG) and zwitterionic polymers with high wettability are among the most promising. However, larger microorganisms as well as proteins are inherently amphiphilic. They operate by different attachment mechanisms, with some having higher attachment affinity to hydrophobic surfaces and others to hydrophilic surfaces. Therefore, a desirable antifouling coating can be defined as one that can show stealth behavior against multiple species. With these findings, there is increasing demand for engineered materials, particularly amphiphilic materials, which, similar to living organisms, can restructure their surfaces depending on the environment. However, one should be aware that a delicate balance of hydrophilicity to hydrophobicity (or amphiphilicity) should be met for a particular surface/coating to be effective in prevention of biofilm formation across a wide variety of species.


A method of determining an output frame rate includes receiving an input sequence of frames of image data at an input frame rate, performing motion vector calculations on the frames of image data to produce motion vectors and motion statistics, determining a motion level in the frames using the motion statistics, and interpolating frames of image data at the output frame rate, wherein the output frame rate is based upon the motion level.

Frame rate interpolation reduces blur and judder to make the picture more lifelike. Frame interpolation typically generates frames in between frames in a current sequence of video frames. Blur occurs when details or edges in an image are lost due to motion. Judder generally refers to uneven or jerky video playback arising from the uneven movement of objects or edges or detail from one frame to the next. The generated frames of frame interpolation fill in the missing information that causes these issues.
Most frame rate interpolation processes detect an original, lower frame rate and then interpolate up to a higher frame rate, typically 120 Hz or above. This works well for televisions that support a high frame rate. For mobile panels, such as tablets, phones, etc., the frame rate interpolation process increases power consumption, which in turn reduces the time available for viewing.
In addition, not all content benefits from a higher frame rate. In fact, one of the main drawbacks of a converting film to 60 Hz or above is that it can destroy the look and feel of a scene. Typically, it creates what is called the soap opera effect (SOE). SOE results when the motion estimation motion compensation (MEMC) frame interpolation causes the resulting video look too smooth, that is, it makes the resulting scenes look like a cheap soap opera.


A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

1. Field of the Invention
This invention relates to digital photography, and more particularly to a low power analog-to-digital converter for a multiple-sampling digital pixel sensor.
2. Description of Related Art
Digital photography is one of the most exciting technologies to have emerged during the twentieth century. With the appropriate hardware and software (and a little knowledge), anyone can put the principles of digital photography to work. Recent product introductions, technological advancements, and price cuts, along with the emergence of email and the World Wide Web, have helped make the digital cameras one of the hottest new category of consumer electronics products.
Digital cameras, however, do not work in the same way as traditional film cameras do. In fact, they are more closely related to computer scanners, copiers, or fax machines. Most digital cameras use an array of pixel sensors or photosensitive devices, such as a charged-coupled devices (CCD) or complementary metal-oxide semiconductor (CMOS) sensors to sense an image. The array of these pixel sensors are arranged in the focal plane of the camera such that each sensor produces an electrical signal proportional to the light intensity received at its location.
The image thus produced has a resolution determined by the number of sensors in the array. A modern digital camera may have a million or more of these sensors. The resulting digital image has discrete picture elements (pixels) corresponding to the number of sensors in the array. Because of the correlation, the sensor elements themselves are often referred to as pixel sensors as well. The light intensity received by each pixel sensor is expressed as a discrete value.
It is known to organize the pixel sensor array in two dimensions, addressable by row and column. Once a row of elements has been addressed, the analog signals from each of the pixel sensors in the row are coupled to the respective columns in the array. An analog-to-digital converter (ADC) may then be used to convert the analog signals on the columns to digital signals so as to provide only digital signals at the output of the array, which is typically formed on an integrated circuit.
Because of a number of problems such as degradation of signal and slow read out times in prior art pixel sensor arrays, a xe2x80x9cdigital sensor pixelxe2x80x9d has been developed as described in, e.g., U.S. Pat. No. 5,461,425, which is hereby incorporated by reference. FIG. 1 illustrates an array 12 of digital sensor pixels 14 on an integrated circuit 10. Each digital sensor pixel 14 in the array 12 includes a photodetector and a dedicated ADC such that the pixel 14 outputs a digital rather than an analog signal as in prior art pixel sensor arrays. In contrast, prior art pixel sensor arrays did not have a dedicated ADC for each individual sensor in the array. Digital filters 16 on integrated circuit 10 are connected to receive the digital output streams from each digital pixel sensor 14 and convert each stream to, e.g., an eight-bit number representative of one of 256 levels of light intensity detected by the respective digital pixel sensor 14. Within the digital pixel sensor 14, the analog signal from the phototransistor is converted into a serial bit stream from its dedicated ADC clocked using a common clock driver 18. The digital filters 16 process the bit stream from each digital pixel sensor 14 to generate an eight-bit value per pixel element 14. These eight-bit values may then be output from the chip 10, using a suitable multiplexer or shift register, and temporarily stored in a bit-mapped memory 24.
Because a digital signal is produced directly by the pixel 14, several advantages over the prior art become apparent. For example, dynamic range is a critical figure of merit for pixel sensors used in digital cameras. The dynamic range of an pixel sensor is often not wide enough to capture scenes with both highlights and dark shadows. This is especially the case for CMOS sensors that, in general, have lower dynamic range than CCDs.
To address the need for increased dynamic range, U.S. Ser. Nos. 09/567,786 and 09/567,638, both filed May 9, 2000 and incorporated by reference herein, disclose an architecture for the digital pixel sensor in which the dynamic range of the sensor is increased by taking multiple samples of a subject during a single imaging frame, where each sample is taken over an interval of a predetermined duration. As used herein, a xe2x80x9cframexe2x80x9d shall denote the period of time during which the multiple exposures for a single image occur as formed by an array of digital pixel sensors.
Although this multiple sampling method provides an increased dynamic range, it may suffer from excessive power consumption by its analog-to-digital converters. For example, if a pixel""s image sample within a given frame approaches or reaches saturation, subsequent image samples from this same pixel within this frame provide no further information because they too will be saturated. Despite their saturation, however, the analog-to-digital converters will continue to process these signals, needlessly wasting power.
Accordingly, there is a need in the art for a digital imaging system whose analog-to-digital converters do not process signals from pixels that are saturated.
In accordance with one aspect of the invention, a system for performing low-power analog-to-digital conversion in a time-indexed multiple sampling digital imaging system is presented using an array of pixel sensors. Multiple exposure times are used for each pixel sensor to form an image during a single frame. An analog image signal is produced by each pixel sensor for each exposure time wherein, prior to satisfaction of a threshold value, an analog-to-digital converter converts each analog image signal into a corresponding digital image signal. The analog image signals are tested against a threshold value. If the threshold value is exceeded for a given pixel sensor, its analog-to-digital converter is prevented from converting the pixel sensor""s analog image signals from subsequent exposure times in the frame. However, those pixel sensors whose analog image signals have not exceeded the threshold value will continue to be converted by their analog-to-digital converters for this frame.
In accordance with another aspect of the invention a method of low power analog-to-digital conversion using a time-indexed multiple sampling technique is presented. The method uses a time-indexed multiple-sampling digital imaging system having an array of pixel sensors. Each pixel sensor in the array produces a plurality of analog image signals corresponding to a plurality of exposure times used for each frame. In addition, an analog-to-digital converter is configured to convert the analog image signals into corresponding digital image signals. The method includes a step of testing, after each exposure time, whether the corresponding analog image signal from each pixel sensor satisfies a threshold value. If the threshold is satisfied for a given exposure time in a given pixel sensor within the array, the method includes a further step of preventing the analog-to-digital converter from converting analog image signals from this pixel sensor resulting from exposure times subsequent to the given exposure time in the frame.
The invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.

Selective analog-to-digital conversion for a digital pixel sensor


Disclosed is a system, method, and program for mapping logical addresses to physical sectors on a storage device including at least one storage medium surface. A determination is made of logical addresses that are specified to be stored in a high throughput region on one storage medium surface. At least two read/write heads operate on the storage medium surface including the high throughput region to increase performance of access operations in the high throughput region. A mapping is generated of the determined logical addresses to the high throughput region. The logical addresses mapped to the high throughput region are capable of being non-contiguous.

1. Field of the Invention
The present invention relates to a method, system, and program for mapping logical addresses to high performance sectors on a storage medium and, in particular, high performance sectors capable of being accessed by multiple read/write heads.
2. Description of the Related Art
A hard disk drive receives input/output (I/O) requests, i.e., read/write request, with respect to locations on the disk drive. A hard disk drives includes a servo controlled actuator that moves a slider across the disk surface. A head is positioned at the end of the slider opposite the actuator to read and write data to the disk surface medium. FIG. 1 illustrates the arrangement of a recording surface of a disk drive 2 divided into concentric circular xe2x80x9ctracksxe2x80x9d on the disk surface. If there are multiple disks, then the vertical alignment of the tracks, on the disks aligned in parallel, together comprise a cylinder.
The outer cylinder is shown as reference 4. Each cylinder is further divided into user data regions 6a-h and prerecorded servo sectors 8a-h. A logical block address (xe2x80x9cLBAxe2x80x9d) is used to address a specific location within the disk stack and is mapped by the disk drive control electronics to a cylinder or track, head number indicating a particular head in a multi-disk system, and sector. Thus, the head indicates a disk and surface in a multi-drive and/or multi storage surface system. Sectors on the disk may comprise 512 bytes, which is the same size as a typical LBA. In this way, a location on the disk can be expressed according to Cylinder/Head/Sector (CHS). Each user data region 6a-h may include one or more sectors. Further, a sector may be split across data regions 6a-h.
The I/O commands may be received at a rate faster than they can be executed against the disk drive storage medium by the storage controller. In such case, the I/O commands are queued for execution by the controller one-at-a-time. The positioning time or total access time to process an I/O request includes: seek time, which is the time to move the actuator and head from one track to another, and latency time, which is the time the head has to wait for disk rotation until the target sector on the track is positioned under the head. These delay times multiply as the number of I/O requests directed toward a disk drive increases. Over the years increases in the storage capacity of disk drives has led to increases in the number of users and application processes accessing a single disk drive, thereby substantially increasing the number of I/O requests directed toward a specific drive.
To reduce the processing time of I/O requests, disk drive manufacturers have developed disk drives that place two separately movable heads on a single disk drive surface. One such disk drive, known as the Chinook disk drive made by Conner Peripherals, Inc., placed two actuator arms, each having a head, on each disk surface. The Chinook defines a disk drive system of five disk platters, where each platter has two disk drive heads per surface, hence twenty disk drive heads total. The Chinook multiple actuator disk drive including two heads per surface is described in U.S. Pat. No. 5,223,993, entitled xe2x80x9cMultiple Actuator Disk Drivexe2x80x9d and assigned to Conner Peripherals, Inc., which patent is incorporated herein by reference in its entirety. The Chinook places two separately movable actuators 180 degrees opposite each other on a disk surface such that both actuators are capable of accessing any position on the disk surface based upon which actuator can access the location in the shortest time. This arrangement effectively reduces the surface area assigned to each head and reduces the seek and latency times as any one of the heads is more likely to be closer to a random position on the disk than a single head. Thus, using two heads increases the speed of processing I/O requests because overall access times are reduced and two heads are available to handle two I/O requests concurrently.
One problem with the prior art disk drives employing multiple heads on each surface is the cost of the multiple heads. Cost issues in fact have significantly dampened demand for the Chinook and other similar disk drive systems including multiple heads on each disk surface.
Thus, there is a need in the art for providing a system that improves I/O request throughput to a disk drive and at the same time does not exceed consumer cost expectations.
To overcome the limitations in the prior art described above, preferred embodiments disclose a system, method, and program for mapping logical addresses to physical sectors on a storage device including at least one storage medium surface. A determination is made of logical addresses that are specified to be stored in a high throughput region on one storage medium surface. At least two read/write heads operate on the storage medium surface including the high throughput region to increase performance of access operations in the high throughput region. A mapping is generated of the determined logical addresses to the high throughput region. The logical addresses mapped to the high throughput region are capable of being non-contiguous.
In further embodiments, generating the mapping comprises associating a range of contiguous sectors in the high throughput region with at least two ranges of noncontiguous logical addresses. The ranges of non-contiguous logical addresses map to the contiguous sectors in the high throughput region.
In still further embodiments, the multiple read/write heads operating on the storage medium surface including the high throughput region are both capable of accessing every sector in the high throughput region.
Yet further, the logical addresses that are specified to be stored in the high throughput region comprise logical addresses used for a file system of a host operating system. Alternatively, the logical addresses that are specified to be stored in the high throughput region comprise logical addresses used for parity data in a RAID storage system. Still further, the specified logical addresses may be specified by the host computer or an application program thereon.
Preferred embodiments provide a relatively low cost method for providing a high performance region in a disk storage system where two heads can access the sectors in the high performance region. To optimize the use of the high performance region, the controller or the host computer may provide a mapping to map logical addresses (LBAs) used for frequently accessed files, e.g., the file system, operating system files, etc., to those sectors in the high performance regions where two heads operate. In this way, throughput is increased for those logical addresses that are most frequently accessed, thereby increasing the likelihood that I/O requests will be serviced from the high performance zone. Further, by not using multiple heads on the other disk surfaces, costs are minimized at the same time that throughput is optimized.

Method, system, and program for mapping logical addresses to high performance zones on a storage medium

International Business Machines Corporation