Various exemplary embodiments relate to a method performed by a policy manager network node in a network, the method including: receiving accounting threshold information relating to an access session associated with an access node; receiving accounting network usage measurement message relating to the access session; determining that a total network usage of the access session exceeds a threshold; and sending a change of authorization message to the access node, wherein the change of authorization message limits a first type of network access, redirects a user of the access node, and allows a second type of network access to continue.

In current networks a user may access a network via an access node. Such networks may include public networks such as, for example, the internet or private networks such as, for example, an internal corporate network. The user may use the network access to use various application and services, for example, web surfing, messaging, email, streaming audio, stream data, accessing databases, shopping, etc. Often a network access provider, for example an internet service provider (ISP), may limit the network usage of a user based upon a service agreement. When a certain threshold level is reached, for example, 90% the access provider may send a message to the user indicating that the user's usage is nearing its limit and/or the network provider may limit the data bandwidth available to the user. When the user reaches their network usage limit, the network provider may prevent further access of the network and redirect the user and present the user an opportunity to acquire more network usage authorization.

Traffic detection function based on usage based thresholds


In a field effect semiconductor device, in order to increase the operation speed and to make the device finer by lowering the sheet resistance, and to lower the production cost by reducing the process steps, the diffusion layer 17 is surrounded by SiO.sub.2 films 16 and 34 covering the tungsten polycide layer 35 provided as the gate electrode and by the SiO.sub.2 film 12 in the device isolating region, and the titanium polycide layer 44 is brought into contact with the entire surface of the diffusion layer 17 while being extended on the SiO.sub.2 films 12 an d 16. Accordingly, a large allowance in aligning the contact hole 25 with respect to the titanium polycide layer 44 can be assured to make the contact compensation ion implantation unnecessary.

The present invention relates to a field effect semiconductor device comprising a gate electrode and a diffusion layer, and to a process for fabricating the same.
In LSI's such as MPU's of which high speed operation is required, it is necessary to reduce the parasitic resistance by converting the diffusion layer of the field effect semiconductor device into suicides. FIG. 3 shows a process for fabricating a MOS transistor according to a first example previously suggested, in which the diffusion layer is converted into silicide.
In the first example referring to FIG. 3A, an SiO.sub.2 film 12 is formed on the surface of an isolating region of a Si substrate 11 by means of LOCOS process and the like, and another SiO.sub.2 film 13 is formed on the surface of the active region surrounded by the SiO.sub.2 film 12. Then, after forming a gate electrode using the impurity-doped polycrystalline Si film 14, implantation of impurity ions is effected by using the polycrystalline Si film 14 and the SiO.sub.2 film 12 as masks to form a lightly-doped diffusion layer 15.
After forming side walls made of an SiO.sub.2 film 16 or an SiN film and the like on the side of the polycrystalline Si film 14, a diffusion layer 17 containing impurity at a high concentration is formed by means of implantation of impurities ions using the polycrystalline Si film 14 and the SiO.sub.2 films 16 and 12 as masks. Then, Ti film 21 or Co film and the like is deposited over the entire surface.
Referring to FIG. 3B, the Si substrate 11 exposed where not masked by the SiO.sub.2 films 12 and 16 and the polycrystalline Si film 14 are reacted with the Ti film 21 or the like by means of annealing in the temperature range of from 600 to 800.degree. C. to form a TiSi.sub.2 film 22 or a CoSi.sub.2 film and the like. As a result, a titanium polycide layer 23 comprising the polycrystalline Si film 14 and the TiSi.sub.2 film 22 provides the gate electrode. Then the Ti film 21 and the like which remain non-reacted on the SiO.sub.2 films 12 and 16 are removed.
Referring to FIG. 3C, an interlayer, insulating film 24 is formed, and a contact hole 25 which reaches the TiSi.sub.2 film 22 provided on the surface of the diffusion layer 17 is formed in the interlayer insulating film 24. If the contact hole 25 should be misaligned from the TiSi.sub.2 film 22, the contact resistance becomes too high because the bird's beak of the SiO.sub.2 film 12 is etched as shown in FIG. 3C as to expose the portion of the Si substrate 11 having no diffusion layer 17 formed thereon.
Accordingly, an impurity 26 is introduced into the Si substrate 11 by means of contact compensation ion implantation to newly form a diffusion layer 27 (FIG. 3D). Then, referring to FIG. 3D, the contact hole 25 is filled with a tungsten plug 31, an interconnection is formed with an Al film 32, and a passivation film (not shown in the figure) is formed to obtain a complete MOS transistor of an LDD structure.
FIG. 4 shows a fabrication process of the first half of a second example previously suggested. In the process referring to FIG. 4A, a polycrystalline Si film 14, a WSi.sub.x film 33, and an SiO.sub.2 film 34 are processed into a pattern of a gate electrode as to form a gate electrode of a tungsten polycide layer 35 comprising the polycrystalline Si film 14 and the WSi.sub.x film 33. Then, referring to FIG. 4B, substantially the same process steps as those of the first example shown with reference to FIG. 3 are effected, except that the TiSi.sub.2 film 22 is formed only on the surface of the diffusion layer 17.
However, in both of the first and second examples above, the surface portion of the Si substrate 11 itself is converted into a silicide to form the TiSi.sub.2 film 22 on the surface of the diffusion layer 17. This induces high stress that is applied to the Si substrate 11, and particularly, to the Si substrate 11 in the vicinity of the bird's beak of the SiO.sub.2 film. Thus, crystal defects are found apt to form on the Si substrate 11, and in case the diffusion layer 17 is shallow, a junction leak current is likely to generate in the diffusion layer 17.
The junction leak current attributed to crystal defects can be prevented from occurring by deepening the diffusion layer 17 in such a manner that the crystal defects are included in the diffusion layer 17. However, if the diffusion layer 17 should be provided deep, it becomes difficult to suppress the short channel effect to make a fine MOS transistor unfeasible.
Furthermore, in case the diffusion layer 17 is provided deep as is shown in FIG. 5 when a diffusion layer 36 is provided as the so-called pocket layer, the position if the junction of the diffusion layer 17 cannot be determined, but varies in the longitudinal direction of the channel due to the variation in the width of the SiO.sub.2 film 16 provided as the side wall. This leads to the variation in width of the diffusion layer 36. Thus, as is clearly understood from FIG. 5, the shape of the depletion layer 37 also varies to make the threshold voltage undecided.
Furthermore, in CMOS transistors, although contact compensation ion implantation is performed to cope with the case the contact hole 25 is misaligned from the TiSi.sub.2 film as shown in FIG. 3C, an additional lithography step is required to cover the MOS transistor having the opposite conductive type. Accordingly, the number of process steps increases as a whole to elevate the cost of fabrication.
Furthermore, annealing at a temperature of 800.degree. C. or higher is necessary to activate the impurity 26 introduced by contact compensation ion implantation. However, at this process stage, the TiSi.sub.2 film 22 is already formed. Thus, the annealing grows and isolates the crystal grains in the TiSi.sub.2 film as to lead to a problematic increase in the resistance of the TiSi.sub.2 film 22.
To prevent the contact holes 25 from the misalignment with respect to the TiSi.sub.2 film, the distance between the contact hole 25 and the SiO.sub.2 film 12 may be increased by expanding the area of the element active region. But this means is in conflict with the aim of implementing a finer MOS transistor.

Field effect semiconductor device having improved connections


A first array of elongate pads is formed on a first surface, such as that of an integrated circuit substrate, and a second array of elongate pads is formed on a second surface, such as that of a printed circuit board. An array of solder balls are reflow attached to the pads of the first array and then to the pads of the second array, to thereby electrically connect the substrate to the printed circuit board. The reflow solder balls thereby conform to the elongate shapes of the pads to be configured like truncated ellipsoids. Due to the surface tension forces between the pads and the balls therebetween, the "ellipsoids" advantageously have a high standoff. Also, the pads on each of the sides of the perimeter of the array are aligned longitudinally perpendicular to the respective sides. Thereby, wide channels between adjacent elongate pads are defined, through which one or more additional traces can advantageously be routed on the surface between the pads.

The present invention relates to reflow ball-grid-array mounted integrated circuit packages and to methods of attaching semiconductor chips and packages with solder bumps to substrates.
Packaged integrated circuits are advantageously mounted on printed circuit boards or motherboards using surface mount technology. A preferred form of this technology is known as ball grid array mounting, and includes forming conjugate planar arrays of mounting pads or contacts on surfaces of integrated circuits and circuit boards, and interconnecting the contacts using arrays of solder balls.
A conventional microelectronic assembly can comprise a packaged integrated circuit which is mounted on a printed circuit board by means of an array of electrically-conductive solder balls. The integrated circuit can have a variety of configurations. The circuit can comprise a ceramic substrate including one or more electrically insulative layers and electrical metallization layers. An integrated circuit chip can be attached to the top of the substrate and electrically interconnected therewith by wire bonds or the like. The chip and wire bonds are preferably environmentally protected from physical damage and contamination by an encapsulation formed of epoxy resin or the like.
Another conventional ball grid array mounting configuration comprises an integrated circuit which is mounted on the circuit board in the same manner as the integrated circuit. However, the circuit comprises a substrate having three layers, the top two layers of which are formed with aligned openings that define a cavity. The integrated circuit is mounted on top of the bottom layer in the cavity and interconnected with the substrate by wire bonds. The die faces away from the circuit board, whereby the configuration is known as "die-up" mounting. The cavity provides ease of wire bonding and improved cooling, and is likewise sealed by an encapsulation.
Another conventional assembly is known as "cavity down" or "die-down" mounting. In this assembly, an integrated circuit includes a substrate having two layers, with an opening formed in the bottom layer to define a cavity which faces the circuit board. The downwardly facing cavity is protected with encapsulation.
The number of electronic devices on each chip is increasing to handle more complex tasks, requiring additional traces or wiring to provide the needed connections. The traces are formed on the surfaces of the components passing between adjacent solder ball pads. The chips are also to be made smaller to increase their operating speed. These developments present design and manufacturing problems of routing the traces through narrower channels, thereby limiting chip capabilities.
These problems can be understood referring to FIGS. 1-4. FIG. 1 shows generally at 100 a prior art flip chip substrate showing the locations of an evenly spaced array of solder bumps 104 on a chip. Some have traces or wires 108 coming out of them as shown on this chip side, some have wires coming out on the other chip side, and some are power and ground pads and thus do not have wires coming out of them. The square 112 in the center represents VDD and VSS bumps. The wires 108 are shown routed between the pads or bumps 104 out the sides, away from the chip center. A simplified view of another prior art array of (circular) solder pads 116 is shown in isolation in FIG. 2 generally at 120.
The width of the space between adjacent pads (104 or 116) determines how many wires (108) can be routed therebetween. As an example, FIG. 3 shows pads 120, 124 having a 0.5400 millimeter diameter 128 and spaced with a 1.0000 millimeter pitch 132 therebetween. With a spacing 136 of 0.1350 millimeter, only three wires 140, 144, 148 can be routed between these pads 120, 124. (A 0.135 micron pitch is a reasonably manufacturable pitch on today's substrate technologies.) The circular pads (120, 124) cannot be made too small, because they must have a certain amount of surface area to maintain sufficient reliability. They cannot be too fragile, because they must be able to handle certain levels of shear forces. The part must be robust and manufacturable, and also large enough to accommodate the needed routing, preferably using standard substrate suppliers.
Spherical solder balls are reflow attached to respective ones of the circular pads 120, 124 of FIG. 3 (or 104 of FIG. 1 or 116 of FIG. 2). Then they are reflow attached at their opposite ends to round pads on another electronic structure. One of the resulting solder balls 152 is shown enlarged and in isolation for illustrative purposes in different views in FIGS. 4a-c. As shown, the ball 152 has a round, compressed and truncated configuration.
Another problem associated with prior art ball grid array configurations is that, due to the relatively small height of the solder balls, the arrays are susceptible to mechanical and thermal stresses which can result in an unacceptably high failure rate.


A CMOS programmable gain amplifier (10) is disclosed which provides exponential gain using a single gain element (19) which may be implemented in either bipolar or CMOS technology. An embodiment of the present invention includes a first and second sampling impedance (12, 14), a first and second feedback impedance (16, 18) and a gain element (19). The gain element (19) having an inverting input, a non-inverting input and an output. The inverting input connects to the first sampling impedance (12). The non-inverting input connects to the second sampling impedance (14). The first feedback impedance (16) connects between the inverting input and the output. The second feedback impedance (18) connects between the non-inverting input and the output.

The present invention relates to programmable gain amplifiers and, more particularly, to a programmable gain amplifier having impedance networks enabling exponential gain and loss which may be implemented in bipolar and CMOS technologies.
Programmable gain amplifiers (PGAs) are used in many applications including digital cameras, camcorders and disk drives. Advances in integrated circuit design and manufacturing have enabled low cost, highly integrated, high performance image processing products such as the digital camera and camcorder. The market for smaller disk drives having reduced power consumption has increased the need for integrated read channel electronics on a single mixed-signal CMOS chip. Existing standard bipolar PGAs dissipate a substantial amount of power and exhibit linear gain. Since a PGA forms an important component of the read channel and helps to stabilize the voltage supplied to the detector and filter sections of the reach channel, it too must be integrated into a single mixed-signal CMOS chip. Previous attempts at developing a CMOS compatible PGA have resulted in a PGA design having the necessary gain control characteristics yet still dissipating substantial power.
An example of such, disclosed in U.S. Pat. No. 5,486,791, which is incorporated by reference herein, presents a PGA including a first and second gain element connected by an impedance selector which allows programmability of the gain of both gain elements. The impedance selector places impedance in the feedback path of the first gain element or the input path of the second gain element. This approach, however, dissipates a substantial amount of power and has a linear gain increase. Exponential gain to linear control voltage characteristic is preferred over linear gain for read channel automatic gain control loops to minimize variations in the output voltage. Thus, most disk drives require that the PGA exhibit exponential gain. Therefore, this approach is not suitable for read channel automatic gain control loops.
An approach having an exponential gain is disclosed in U.S. Pat. No. 6,049,252, which is incorporated by reference herein. The PGA provides sufficiently fine and linear gain control to provide an exponential output according to the logic levels of control signals. It includes a cascade connection of differential amplifiers and a current controller for controlling a product of corresponding emitter currents supplied to each of the differential amplifiers according to the logic levels of binary control signals. The current controller has a current mirror circuit in which the emitter of each bipolar transistor is connected to the ground through a MOS transistor having a relative on-resistance designed to be in inverse proportion to the relative emitter size of the bipolar transistor, so that the emitter current can be exactly controlled. Bipolar transistors having the same size or units of impedance are used in this design to implement the exponential gain. The use of these transistors, however, limits the range of the PGA. Furthermore, each transistor may not be linear. Moreover, even though this design may result in a PGA having the necessary gain control characteristics, it still dissipates substantial power. A significant percentage of this power is dissipated in generating the exponential current output for the linear voltage input. Although this approach, is implemented in bipolar technology, it is not easily implemented in CMOS as is explained in reference to a third approach.
This third approach disclosed in xe2x80x9cA Low-Power CMOS VGA for 50 Mb/s Disk Drive Read Channels,xe2x80x9d Ramesh Harjani, IEEE Transactions on Circuits and Systemsxe2x80x94II: Analog and Digital Signal Processing, Vol. 42, No. 6, June 1995, is a methodology for generating the desired exponential transfer characteristics intrinsically using only MOS devices within the variable gain amplifier structure. This approach appears to be a CMOS implementation of the second approach cited above. Since CMOS transistors have a square root relationship, however, it necessitates the implementation of duplicate circuitry to get rid of the square root relationship. As a result of multiplying two square root circuits to eliminate the square root relationship, linear gain exists. In addition, this implementation is very cumbersome to implement, the range is limited, and distortion exists.
Besides the desired exponential transfer characteristics, applications such as the digital camera require that a PGA operate under conditions where current is not continuously supplied. The conventional digital camera includes an image sensor, an analog front end (AFE), and a digital image processor. Most AFEs include three elements: a correlated double sampler (CDS), a programmable gain amplifier (PGA) and an analog to digital converter (ADC). In operation, a signal comes into the camera and is held. No continuous signal exists in such an application. The third approach presented above, however, requires that current be continuously applied to the PGA input in order to operate correctly.
Thus, there exists a need for a CMOS PGA having an exponential gain that operates given non-continuous current conditions.
To address the above-discussed deficiencies of programmable gain amplifiers (PGAs), the present invention teaches a PGA having an exponential gain including a gain element wherein the PGA may be implemented in either bipolar or CMOS technology.
One embodiment of the present invention includes a sampling impedance, a feedback impedance, and a gain element. The gain element having an input and an output. The input connects to the sampling impedance. The feedback impedance connects between the input and the output.       "LeftBracketingBar"                            V          0                +                  -                      V            0                          -                              V          i                +                  -                      V            i                          -              "RightBracketingBar"    =                              (                      1            +            X                    )                                  C          S                                      (                      1            -            X                    )                                  C          S                      =                  1        +        X                    1        -        X
Another embodiment of the present invention includes a first and second sampling impedance, a first and second feedback impedance and a gain element. The gain element having an inverting and non-inverting input and an inverting and non-inverting output. The inverting input connects to the first sampling impedance. The non-inverting input connects to the second sampling impedance. The first feedback impedance connects between the inverting input and the non-inverting output. The second feedback impedance connects between the non-inverting input and the inverting output.
In another embodiment of the present invention includes a first and second sampling impedance, a first, second, third and fourth feedback impedance and a gain element. The gain element having an inverting and non-inverting input and an inverting and non-inverting output. The inverting input connects to the first sampling impedance. The non-inverting input connects to the second sampling impedance. The first feedback impedance connects between the inverting input and the non-inverting output. The second feedback impedance connects between the non-inverting input and the inverting output. The third feedback impedance connects between the inverting input and the inverting output. The fourth feedback impedance connects between the non-inverting input and the non-inverting output.
Advantages of this design include but are not limited to programmable gain amplifier implementable in bipolar or CMOS technology. This PGA has exponential gain characteristics without dissipating substantial power. Since the gain characteristic of the programmable gain amplifier in accordance with the present invention depends upon the impedance of a capacitor, the gain is more precise than others.

Capacitor-based exponential programmable gain amplifier


According to one embodiment, when being notified of an interruption of an external electric power supply, a second processor performs a saving operation for storing management information and data stored in a first volatile memory to a first non-volatile memory, and records a progress log, indicating a progress of the saving operation, into a second volatile memory. The first processor periodically checks whether the progress log is recorded in the second volatile memory or not, and when the progress log is recorded in the second volatile memory, the first processor stores the progress log into the second non-volatile memory.

A memory system provided with non-volatile memory has a backup power source, such as a battery or a capacitor, for an invalid interruption of electric power supply. When detecting the invalid interruption of electric power supply, the memory system switches the power source to the backup power source from an external power source, and saves necessary data to the non-volatile memory from volatile memory within the period of supplying electric power by the backup power source in order to protect the data from being lost.
During the data saving operation, the non-volatile memory stores a progress log indicating the progress of the data save in order that the progress log is used for data recovery or failure analysis upon the data save.
Electric power exceeding the capacity of the backup power source cannot be consumed upon non-volatilization of the data and the progress log. Therefore, it is necessary to reduce the power consumption as much as possible to extend the backup time of the power source.

Memory system and controlling method of memory system


The present invention relates to a method for manufacturing an electrically conductive pattern by printing a layer comprising metal oxide on a carrier substrate (2) and reducing the metal oxide to metal. The reduced layer is transferred to an application substrate (7). The present invention also relates to the use of the method.

In prior art relating to circuit board manufacture, e.g. in specification U.S. Pat. No. 5,261,950, a method is disclosed wherein a fine-grained copper oxide powder having a granular size of the order of 10 μm or less is used for the formation of a paste. The paste is formed from copper oxide powder, a binding agent, alloying elements and additives. From the paste, a blank of an electrically conductive pattern of desired shape is formed on the surface of a substrate. The blank on the surface of the substrate is reduced using e.g. hydrogen (i.e. metallized) and sintered using a high temperature to produce a continuous copper foil.
In prior-art methods of this type using copper oxide powder as a starting material, which is reduced and sintered to form a metallic copper foil, the aim is always that the copper foil should remain permanently fixed to the surface of the underlying substrate. For this purpose, the prior-art paste contains a glass additive, among other things, which forms a strong bond to the underlying ceramic substrate. Since the metallization and sintering are performed at a very high temperature, which usually has to be at least of the order of over 500° C. to ensure adequate sintering, the substrate must be made of a material having a good heat resistance, such as ceramic.
The prior-art method has the advantage that a copper foil, which has a good electric conductivity, can be formed by a fast and low-cost procedure from copper oxide, which is cheap and has the characteristics of an insulator. Copper oxide powder as a starting material is chemically stable, unlike e.g. pure copper powder, which is so active that it tends to oxidize. In addition, copper oxide is cheap. In the copper foil manufacturing process, no copper oxide is wasted, so the efficiency and yield are good.
The problem with the prior-art method is that it is not suited for use in the formation of a electrically conductive pattern in practical applications where an electrically conductive pattern formed from copper foil having good electrical conductivity is to be laminated onto a plastic or paper substrate. Such applications include e.g. inductive sensors and antennas for various electrotechnical applications. It is obvious that a plastic or paper substrate would be destroyed if it were exposed to high temperatures as mentioned above.
A special application, which uses thin conductive metal foil on a 20 plastic and/or paper substrate are transponders. The transponders refer in this application to products, which comprise a circuitry pattern and an integrated circuit on a chip. The circuitry pattern is located on a substrate, and the integrated circuit on the chip is electrically connected to the circuitry pattern.
The transponders can be activated e.g. by an external HF or UHF field, so they need no power source. The transponders can be used for the identification of objects (products, persons, animals, etc.) by using memory data stored in the integrated circuit on the chip. Identification takes place from a distance, which varies depending on the used technology and the effective regulations. For the identification, the antenna produces an electric current for the integrated circuit when in the field of a reader. The substrate of the transponder can be provided with an adhesive surface to allow it to be attached to an object. The transponders may be disposable, like those used on foodstuff and other consumer goods packages, being destroyed after use, or they may be designed for continuous use, such as those used in logistic applications, bankcards, personal identification cards or other ID applications.
A typical circuitry pattern of a transponder has a thickness of 5-50 μm. The printed circuitry pattern is generally produced by the silk-screen printing technique. Electrical conductivity is provided by using conductive powder, which may be produced from e.g. silver, copper and graphite. Besides printed antennas, antennas are nowadays also made from e.g. thin copper wires by coiling and flattening the wires so as to form a thin foil. Other production methods include evaporating and electrolytic or chemical precipitation. From a continuous copper foil, which may be produced by different methods, the unnecessary parts are etched away to create an antenna pattern. The portion to be etched away may well exceed 50%. As the removal of the extra metal requires separate work stages, efforts are continuously being made in the field to create an antenna that is as near net shape as possible already at an early stage of the manufacturing process.
There are also prior-art methods wherein an RF-ID antenna is formed by die cuffing from a thin metal foil. The problems are that in this manufacturing method the quality is poor and most of the metal foil is lost as waste.
Specification EP 0991014 discloses a photolithographic method of forming an RF-ID antenna from silver powder using various light sensitive films, at least one intermediate agent facilitating the processing and two types of conductive metallic powder. Silver is expensive, so the antenna produced by this method is also expensive.
Especially in an RF-ID application, there is the problem that RF-ID tag antennas produced by prior-art manufacturing methods are expensive, which is an impediment to their more widespread use in disposable applications, such as e.g. foodstuff packages.
Generally known is also a method for producing a thin continuous foil e.g. by an electrolytic precipitation process. This method involves a cathode drum rotating in an electrolysis vessel and an arc-shaped anode consisting of one or more parts in the bottom part of the vessel. An electrolyte is supplied between the anode and the cathode, and the aim is to precipitate a copper foil as continuous and uniform as possible onto the surface of the cathode drum. When the deposited foil rises above the electrolyte, it is detached from the cathode and passed on to a further treatment process. The method has been under development since the 1930's, and it is described e.g. in U.S. Pat. No. 2,044,415 and in published patent application US 2002/5363.

Method for manufacturing in electrically conductive pattern


A no-thread fishing fly includes an attractor attached to a fish hook, the fish hook having a hook disposed at one end of a shank and an eye disposed at an opposite end of the shank. The eye includes a distal end disposed adjacent to and spaced from the shank. The distal end of the eye includes an integrally formed blocker. In an alternate embodiment, a no-thread fishing lure includes an attractor disposed at one end of a shank and an eye disposed at an opposite end of the shank. The eye includes a distal end disposed adjacent to and spaced from the shank. The distal end of the eye includes an integrally formed blocker.

Fishing equipment is available in a variety of sizes, shapes, colors and configurations for attracting and catching different species of fish. Several examples of fishing lures include spinner baits, jigs, and plastic worms. Another example of fishing equipment used to attract fish such as trout and bass is a fishing fly.
Fishing flies are generally constructed by tying colored materials, such as feathers, yarn, or hair, to a small fish hook so that the completed fishing fly resembles any one of a variety of species of insect that a particular species of fish feeds upon. Accordingly, the fish hooks used for constructing fishing flies are generally very small. For example, a size #18 fish hook for a fishing fly measures approximately 7 millimeters in length.
Fish hooks for constructing fishing flies generally include a J-shaped hook with a barb at one end of a shank for catching the fish and an eye at an opposite end of the shank for tying tippet, fishing line, leaders, or other materials so that the fishing fly can be cast and retrieved. Additionally, other fishing equipment and fishing lures, such as spinner baits and jigs, also include an eye at one end for attaching fishing line or leaders.
Fishing lures and fishing flies, however, suffer several disadvantages. For example, since fishing flies are generally constructed to resemble insects, the size of the fishing fly is generally very small. Accordingly, the fish hook and the eye of the fish hook are generally very small, thereby making it extremely difficult to thread tippet, fishing line, or leaders through the eye of the fish hook. With average or below average eyesight; poor lighting conditions; inclement weather; wind; a necessity to change the fly quickly; or stiff, cold or wet hands; the difficulty and problem of threading the eye of the fish hook is greatly magnified.
Additionally, the size of the eye generally determines the size of tippet, fishing line, or leader that may be used with the fishing fly or fishing lure. The smaller eyes of the fish hooks or fishing lures require smaller fishing line or tippet. Consequently, the fishing line or tippet material becomes smaller in diameter, more limp, more difficult to see, and increasingly difficult to handle. For example, a size #18 fly is approximately 7 millimeters in length, has a fish hook eye outside diameter of approximately 0.75 millimeters, a fish hook eye inside diameter of approximately 0.30 millimeters, and will generally accommodate fishing line or tippet material through the eye of the fish hook of approximately 0.13 millimeters or less. Thus, the flexibility of using a variety of sizes of fish hooks, lures, flies or other fishing devices with different diameter fishing line is limited.


An assembly comprising first and second structural components and a packer disposed between the first and second components, wherein the first component and the packer have mating part-spherical surfaces, and the first and second components are fixed relative to one another. Also, a method of aligning first and second structural components relative to one another to form an assembly, the method comprising bringing together first and second structural components with a packer disposed between the components, wherein the first component and the packer have mating part-spherical surfaces, sliding adjustment of the first component relative to the packer until the first and second components are aligned in a desired relationship, and then fixing the first and second components relative to one another.

During the assembly of complex structures such as aircraft wings where the close fit of various sections is critical in the transfer of load and aerodynamic performance, or important in ensuring excessive build loads are not introduced during assembly, much time and expense is expended understanding, managing and mitigating tolerance build up.
These tolerances can consist of variations in length, thickness, width, angle, and profile all acting in combination. Traditionally these tolerances are analysed in detail during the design phase and a datum structure and allowable range defined. In the case of complex surfaces containing three dimensional curvature such as aircraft wings a point may be reached where datum structures between different parts compete for control of features critical for performance, such as aerodynamic profile, or manufacturability.
Often the cost of further improvements in control over these features has to be balanced against increasingly complex tolerance chains, so it may also be necessary to consider the time needed to assemble such complex structures.
In such cases a convenient way of compensating for various tolerances that still allows the primary performance drivers to meet their requirements will benefit cost, ease of assembly and performance.
Shimming is often used to provide compensation for manufacturing tolerances. However, it is not always acceptable in highly loaded joints for stress or material compatibility reasons. Fettling is also possible but time consuming, and in the case of aircraft structure may require highly skilled operators and machinery if complex parts are to be machined to fit during the assembly phase. The adoption of composites with their inherent limitations in machineability and health and safety limitations on dust creation also provide significant manufacturing challenges.
Significant gains in productivity can be made in areas where complex tolerance interactions can be simply mitigated.


An object, such as a dried and pressed flower, is to be mounted between a transparent electrostatic vinyl sheet and a cover film with the object being tightly sealed therebetween. The electrical properties of the electrostatic vinyl film are to permit the resulting sealed ornament to be applied onto a clean, flat, non-porous surface with the static electricity of the electrostatic vinyl film fixing the sealed ornament in position.

1) Field of the Invention
The field of this invention relates to ornaments, more particularly to an ornament which is constructed in a sheet material form with the ornament comprising a displayable item secured between thin, transparent, flexible plastic sheets of material.
2) Description of the Prior Art
Ornaments are numerous in configuration. A typical object to be utilized to construct an ornament could be a photograph, a drawing, a small painting, and even natural items such as dried and pressed flowers. It has been known to seal objects between transparent layers of plastic with the transparent plastic layer permitting the visualization of that object. The ornament is then to be secured by some type of securing means onto a surface with it being common that this surface is located vertically. Commonly used securing means would include an adhesive or a nail. Some of the disadvantages of such types of securing means are that nails leave marks and an adhesive usually leaves a residue on the surface to which the ornament is applied. This residue would detract from the physical appearance of the surface upon the sealed ornament being removed and possibly moved to another location. Also, any nail hole would mar the physical appearance of the surface.


The present invention relates to methods for making highly crystalline polymeric material, for example, highly crystalline cross-linked and not cross-linked ultra-high molecular weight polyethylene (UHMWPE). The invention also provides methods of making additive-doped highly crystalline polymeric material using high pressure and high temperature crystallization processes, medical implants made thereof, and materials used therein.

Cross-linking by irradiation decreases the fatigue strength of UHMWPE. In addition, post-irradiation melting further decreases the fatigue strength of the UHMWPE. Radiation and melting also decrease the yield strength, ultimate tensile strength, toughness and elongation at break of UHMWPE.
Melting in combination with irradiation creates cross-links and facilitates recombination of the residual free radicals trapped mostly in the crystalline regions, which otherwise would cause oxidative embrittlement upon reactions with oxygen. However, cross-linking and the decrease in the crystallinity accompanying post-irradiation melting are thought to be the reasons for the decrease in fatigue strength, yield strength, ultimate tensile strength, toughness and elongation at break of radiation cross-linked and melted UHMWPE. Some or all of these changes in properties limit the use of low wear highly cross-linked UHMWPE to low stress applications. Therefore, a cross-linked UHMWPE with higher crystallinity is desirable for low wear and high fatigue resistance for high stress application that require low wear.
It is, therefore, desirable to reduce the irradiation-created residual free radical concentration in cross-linked UHMWPE without reducing crystallinity, so as to achieve high fatigue resistance for high stress application that require low wear. Alternative methods to melting can be used to prevent the long-term oxidation of irradiated UHMWPE to preserve higher levels of crystallinity and fatigue strength.
The effect of crystallinity on the fatigue strength of conventional UHMWPE is known. Investigators increased the crystallinity of unirradiated UHMWPE by high-pressure crystallization, which increased the fatigue crack propagation resistance of unirradiated UHMWPE by about 25% (Baker et al., Polymer, 2000. 41(2): p. 795-808). Others found that under high pressures (2,000-7,000 bars) and high temperatures (>200° C.), polyethylene grows extended chain crystals and achieves a higher crystallinity level (Wunderlich et al., Journal of Polymer Science Part A-2: Polymer Physics, 1969. 7(12): p. 2043-2050). High pressure crystallization may improve the fatigue strength of irradiated UHMWPE despite no significant changes in ultimate tensile strength (Pruitt et al., 7th World Biomaterials Congress, 2004. p. 538. Bistolfi et al., Transactions, Orthopaedic Research Society, 2005. p. 240) through first melting than pressurizing. The crystallization behavior of not cross-linked or highly cross-linked polyethylene at high pressures through first pressurizing, then heating at the high pressures has not been determined.
Polyethylene undergoes a phase transformation at elevated temperatures and pressures from the orthorhombic to the hexagonal crystalline phase. The hexagonal phase can grow extended chain crystals and result in higher crystallinity in polyethylene. This is believed to be a consequence of less hindered crystallization kinetics in the hexagonal phase compared with the orthorhombic phase. One could further reduce the hindrance on the crystallization kinetics by introducing a plasticizing or a nucleating agent into the polyethylene prior to high-pressure crystallization. The polyethylene can be doped with a plasticizing agent, for example, α-tocopherol or vitamin E, prior to high-pressure crystallization. The doping can be achieved either by blending the polyethylene resin powder with the plasticizing agent and consolidating the blend or by diffusing the plasticizing agent into the consolidated polyethylene. Various processes of doping can be employed as described in U.S. application Ser. No. 10/757,551, filed Jan. 15, 2004, PCT/US/04/00857, filed Jan. 15, 2004, U.S. Provisional Application No. 60/541,073, filed Feb. 3, 2004, and PCT/US2005/003305, filed Feb. 3, 2005, the entireties of which are hereby incorporated by reference.
Reduction in adhesive/abrasive wear of ultra-high molecular weight polyethylene (UHMWPE) components can be achieved by decreasing the large-scale deformation ability of the polymer. Cross-linking by ionizing radiation is generally used for this purpose (see Muratoglu et al., J Arthroplasty, 2001. 16(2): p. 149-160; Muratoglu et al., Biomaterials, 1999. 20(16): p. 1463-1470; and McKellop et al., J Orthop Res, 1999. 17(2): p. 157-167) with a concomitant decrease in strength (Oral et al., Biomaterials, 2005).
In order to increase the strength of UHMWPE, high pressure crystallization (HPC) of UHMWPE has been proposed (see Bistolfi et al., Transactions of the Orthopaedic Research Society, 2005. 240; Oral et al. Transactions of the Orthopaedic Research Society, 2005. p. 988, U.S. Provisional Application No. 60/541,073, filed Feb. 3, 2004, and PCT/US2005/003305, filed Feb. 3, 2005). High pressure crystallization of unirradiated GUR1050 UHMWPE at above 160° C. and 300 MPa yielded an approximately 70% crystalline UHMWPE, compared to 50-60% for conventional UHMWPE. This is due to a phase transition of the UHMWPE crystals from the orthorhombic to the hexagonal phase at high temperatures and pressures as discussed above. In the hexagonal phase crystals grow to larger sizes and crystallinity increases (see Bassett et al., J Appl. Phys., 1974. 45(10): p. 4146-4150).
While high pressure crystallization can be used to increase the strength of UHMWPE, it has been shown to decrease the wear resistance of unirradiated UHMWPE (see Bistolfi et al., Transactions, Orthopaedic Research Society, 2005. p. 240). It appears that the decrease in ductility accompanying high pressure crystallization may adversely affect the wear resistance.

This patent is subject to a terminal disclaimer.


A class AB amplifier includes an input stage having a pair of differential input terminals, first and second differential output terminals, and a local common mode feedback circuit. The input stage includes a local common mode feedback circuit having cascode transistor to achieve relatively high gain. The amplifier also includes an output stage having first and second pairs complementary transistors coupled between first and second power supply nodes. One of the complementary transistors in each pair has a gate coupled to the first and second differential output terminals, respectively. The output stage includes a pair of cascode transistor connected to one of the pairs of complementary output transistors. The amplifier can be used to supply a bias voltage to a highly capacitive load, such as voltage sampling capacitors in a CMOS imager.

As is well-known in the art, class AB amplifiers are amplifiers containing circuits that are conductive only part of the time. As a result, class AB amplifiers generally have the advantage of using relatively little power. One prior art amplifier 10, which is described in an article entitled "An Integrated Low-Voltage Class AB CMOS OTA" by Ramesh Harjani, et al. and published in IEEE J. Solid-State, vol. 34, pp 134-142, February 1999, is shown in FIG. 1. The amplifier 10 is based on the principle of a self-biased input transistor. As shown in FIG. 1, two such NMOS transistors 12, 14 are combined in a common source configuration. The drains of the transistors 12, 14 are connected to the drains of respective NMOS transistors 16, 18, which have their gates connected to the gates of the transistors 12, 14, respectively. The transistors 16, 18 are connected to ground through respective current sinks 20, 22, and voltages VA, VB are generated at the sources of the transistors 16, 18, respectively. These voltages VA, VB are connected to an input of respective operational amplifiers 30, 32, which have their outputs connected to the gates of respective NMOS transistors 36, 38 that are connected in series with the transistors 12, 14. As further shown in FIG. 1, the transistors 12, 14 are connected in series with respective PMOS diode-connected transistors 40, 42, which have their gates coupled in current mirror fashion to respective transistor 46 and output transistor 48. The transistor 46 is, in turn, connected in series with a diode-connected NMOS transistor 50, and the output transistor 48 is connected in series with a diode-coupled output transistor 52, which have its gate coupled to the gate of the transistor 50. An output node 54 is formed at the interconnected drains of the transistors 48, 52.
In operation, when a differential input Vinp and Vinm, respectively, is zero, the voltages at the nodes designated VS, VA and VB are equal to common mode input voltage minus (VT+ΔV), where ΔV=√{square root over (2IB/K(W/L))} and VT is threshold voltage of the transistors 12, 14. Negative feedback ensures that the common source voltage of the transistors 12, 14 is always forced to track the smaller of the two voltages VA and VB, whereas VA and VB are (VT+ΔV) below Vinm and Vinp, respectively. More specifically, for example, if the input voltage Vinp is larger than the gate voltage Vinm, the voltage VB will be larger than VA. As a result, the output voltage of the operational amplifier 30 is effectively pulled down, which turns OFF the transistor 36. In such case, the current I1 through the transistor 14 is given by the formula:
                                                                        I                1                            =                                                1                  2                                                                  K                                                        (                                          W                      L                                        )                                                                                (                                          Vinp                      -                      VS                      -                      VT                                        )                                    2                                                                                =                                                1                  2                                                                  K                                                        (                                          W                      L                                        )                                                                                (                                          Vinp                      -                      VA                      -                      VT                                        )                                    2                                                                                (                  Equation                                                              1                )            where W/L is the channel width to length ratio of the transistor 14.
Further, using the relationship between VA and Vinm, i.e.,Vinm=VA+ΔV+VT  (Equation 2)where VT is the threshold voltage of the transistor 16.
The above Equation 1 for the current through the transistor 14 can be written as:
                              I          1                =                              1            2                                          K                                      (                              W                L                            )                                                                    (                              Vinp                -                Vinm                +                                  Δ                                                                                V                                            )                        2                                              (                  Equation                                                              3                )
A slight difference between the input voltages Vinp and Vinm turns OFF one of the output transistors 46 or 48 and directs a large current, which is proportional to square of differential input voltage, Vinp−Vinm, to the other output transistor 48 or 46. The amplifier 10 is well suited for low-voltage applications. But, because all active loads are connected through diode-coupled transistors 46, 50 and 48, 52, the DC gain of the amplifier 10 is relatively low. As a result, the amplifier 10 is generally used only for low current application, which biases the transistors 46, 50 and 48, 52 to sub-threshold levels.
Attempts have been made to improve upon the amplifier 10 shown in FIG. 1 using an amplifier 60, which is shown in FIG. 2. This amplifier 60 is described in an article entitled "Low-Voltage Super Class AB CMOS OTA Cells With Very High Slew Rate and Power Efficiency" by Antonio J. Lopez-Martin, et al., which is published in IEEE J. Solid-State, vol. 40, pp 1068-1077, May 2005. The amplifier 60 includes a pair of PMOS input transistors 62, 64 receiving input voltages Vinm and Vinp, respectively. The transistors 62, 64 are coupled to ground through respective NMOS transistors 66, 68, which have their gates connected to each other and to their drains through respective feedback resistors 70, 72. A voltage "x" is generated at a node 74 formed by the interconnected drains of the transistors 62, 66, and a voltage "y" is generated at a node 76 formed by the interconnected drains of the transistors 64, 68. The voltage "x" is applied to the gate of an NMOS output transistor 80, which is connected in series with a diode-coupled PMOS transistor 82. Similarly, the voltage "y" is applied to the gate of an NMOS output transistor 84, which is connected in series with a PMOS transistor 86, which has its gate connected to the gate of the transistor 82. An output node 88 is formed at the interconnected drains of the transistors 84, 86. Finally, the respective sources and gates of the input transistors 62, 64 are connected to an adaptive biasing circuit 90, which is described in greater detail below.
In operation, the common mode voltage at the drain of the transistors 66, 68 is fed back to their common gates to provide additional current boosting. This technique is sometimes known as Local Common-Mode Feedback ("LCMFB"). The loads at the nodes 74, 76 where the voltages "x" and "y" are generated are approximately equal to the resistances of the feedback resistors 70, 72, respectively. Without the resistors 70, 72 the load at these nodes 74, 76 would be significantly smaller, i.e., on the order of 1/gm of the transistors 66, 68. This increased impedance at the nodes 74, 76 increases the DC gain of the amplifier 60. Furthermore, if the amplifier 60 drives a large capacitive load, which is common in many applications, the dominant pole of the amplifier is determined by the capacitance and is independent of the impedance of the resistors 70, 72.
A prior art circuit 100 used for the adaptive biasing circuit 90 in the prior art amplifier 60 is shown in FIG. 3. For purposes of brevity and simplicity, only one-half the circuit is shown in FIG. 3 along with the PMOS transistor 62. The circuit 100 uses a pair of PMOS transistors 102, 104 connected in series with a current sink 106 between VCC and the drain of the transistor 62. The gate of the transistor 102 is connected to the node between the source of the transistor 104 and the current source 106, and the gate of the transistor 104 is connected to the gate of the input transistor 62, as also shown in FIG. 2.
A variety of techniques are used in the prior art to connect the circuit 100 shown in FIG. 3 with another of the circuits 100. However all of these exhibit a significant problem. Specifically, since the transistor 102 is diode-connected, and because the electrical characteristics of the transistor 62 should duplicate the electrical characteristics of the transistor 104, therefore the common mode input voltage must be precisely controlled. Otherwise, the transistors 62, 104 operate in their triode or ohmic region rather than in their amplification region, which would adversely impact the gain of the amplifier 60 using the circuit 100. Therefore, if the circuit 100 is used in the amplifier 60, and the amplifier 60 is used as an input buffer, the differential input voltage must be within a very small range to prevent the transistors 62, 104 from operating in their triode or ohmic region. Furthermore, the limits of the acceptable range varies with supply voltage, process variations, temperature and current supply.
There is therefore a need for a class AB amplifier that has the desirable attributes of the amplifiers 10, 60 without the above-described disadvantages.

Class AB amplifier and imagers and systems using same


A sub-rate time switch switches a digital multiplexed signal having a basic-rate signal included in a first time slot of the digital multiplexed signal and N sub-rate signals included in a second time slot thereof where N is an integer. Each the sub-rate signals has a sub-rate which is equal to 1/N times a basic rate of the basic rate signal. A speech path memory temporarily stores the digital multiplexed signal input to the sub-rate time switch. A channel signal is read out from the speech path memory and has a plurality of channels corresponding to time slots of the digital multiplexed signal. A control part controls write and read operations of the speech path memory so that the channel signal includes N consecutive channels. Each of the N consecutive channels includes N identical sub-rate signals, and each of the N identical sub-rate signals corresponds to one of the N sub-rate signals included in the second time slot of the digital multiplexed signal.

(1) Field of the Invention
The present invention generally relates to a digital switching system, and more particularly to a sub-rate time switch which switches a digital multiplexed signal including a plurality of sub-rate signals in one time slot.
(2) Description of the Prior Art
A general switching method of a digital switching system handles 64 kbps signals. Recently, there has been considerable activity in the development of methods of compressing speech information in order to efficiently utilize digital transmission lines. In such compression methods, speech information is compressed to a sub-rate of, for example, 32 kbps, 16 kbps or 8 kbps, while a basic rate is 64 kbps. It is required that such compressed data be exchanged by a time switch which switches 64 kbps data.
Conventionally, speech information is converted to a 64 kbps PCM signal according to the CCITT recommendations. Particularly in Japan and the United States, the .mu.-law is employed to convert the speech information into a 64 kbps signal. In the 64 kbps signal, it is necessary to transmit 8 bits every 125 .mu.sec. For this reason, a 64 kbps switch system is generally employed.
Taking into account the recent activity in the research and development of speech compression schemes, the CCITT has issued the final recommendations about a 32 kbps ADPCM (Adaptive Differential PCM). The final recommendations have been practically used in some systems. Further, many companies have studied and proposed their own 16 kbps or 8 kbps compression schemes.
FIG. 1 shows a conventional digital exchange system which handles sub-rate signals, and FIG. 2 shows an input/output format of a codec LSI device shown in FIG. 1. Further, FIG. 3 shows the structure of a conventional 64 kbps time switch used in the system shown in FIG. 1, and FIG. 4 shows the structure of a conventional 32 kbps time switch used in the system shown in FIG. 1.
Referring to FIG. 1, the system includes a network NW including a path switch, subscriber lines 71 and 72, digital trunk (junction) lines 73 and 74 mutually connecting exchange systems, and a speech compression/decompression multiplexing unit 75 (hereafter simply referred to a multiplexing unit). In FIG. 1, subscribers (telephone sets) A and B are connected to the network NW via respective line circuits LC, and communicate with subscribers C and D via another exchange system (not shown), respectively. Digital signals, each having a basic rate of, for example, 64 kbps, are transferred between the subscribers A and B and the network NW. Signals transferred via each of the digital trunk lines 73 and 74 respectively include two sub-rate signals in one time slot in order to efficiently utilize the digital trunk lines 73 and 74. Each sub-rate signal has a sub-rate of 32 kbps.
The multiplexing unit 75 is provided for exchanging the basic-rate signals with the sub-rate signals. On the input side of the multiplexing unit 75, 64 kbps speech signals (8-bit digital signals) sent out from the subscribers A and B are assigned to time slots "0" and "1" by the network 70. Further, 32 kbps sub-rate signals (four-bit digital signals) sent from the subscribers C and D via the digital trunk line 74 are assigned to time slot "2" by the network 70. An input time slot signal (INPUT TS) 1 having a format shown in FIG. 1 is input to the multiplexing unit 75. For the sake of convenience, one frame consists of four time slots (or channels) "0" to "3", as shown in FIG. 1.
The input time slot signal (INPUT TS) 1 is changed to an input channel signal (INPUT CH) 2 by a primary time switch (SW0) 76 of the multiplexing unit 75. During this process, the signals, each having the basic rate, are output to a 32 kbps ADPCM codec (CODEC) 77 without any change, while the time slot "2" including two sub-rate signals is divided so that the two sub-rate signals are placed in separate channels (CH; the same as TS). The input channel signal 2 has a format shown in FIG. 2.
The input channel signal 2 is input to the codec 77, which encodes each of the basic-rate signals contained therein to a sub-rate code and decodes each of the sub-rate signals to a basic-rate code. Then, the codec 77 outputs an output channel signal (OUTPUT CH) 3 having a format shown in FIG. 2. The output channel signal 3 is input to a secondary time switch 78 of the multiplexing unit 75, at which the positions of time slots are changed by a random-write/sequential read procedure of the secondary time switch 78. Then, an output time slot signal (OUTPUT TS) 4 having a format shown in FIG. 1 is produced at the output side of the multiplexing unit 75. As shown, the format of the output time slot signal 4 includes, in time slot "0", the sub-rate signals from the subscribers A and B.
The primary time switch SW0 has the function of placing the plural (two) sub-rate signals which are present in one time slot of the input time slot signal into corresponding, plural a plurality of, (two) channels of the input channel signal, and the secondary time switch SW1 has the function of placing the plural (two) sub-rate signals which are present in the output channel signal into corresponding, plural (two) channels of one time slot of the output time slot signal.
A conventional 64 kbps time switch will now be described with reference to FIG. 3. In general, an input signal which is input to the 64 kbps time switch is a multiplexed signal obtained by multiplexing 8-bit signals, each being generated for every 125 .mu.s interval and has a frame which consists of 32 channels (time slots). The input signal is sequentially written into a speech path memory SPM (Speech Path Memory) of the 64 kbps time switch. During the write operation, write addresses are generated by a counter CT0. In FIG. 3, A0L-A2L are three low-order bits, which specify a write position (area) in which each bit in a specified input time slot is written, and A3L-A7L are five high-order bits of the counter CT0. The bits A3L-A7L specify a write position (area) corresponding to each input time slot number ("0"-"31"). The contents of the speech path memory SPM are read out therefrom at a time specified by software in the random read manner.
More specifically, a control memory CM has information about the time slots on the write side of the speech path memory SPM with respect to the time slot positions on the read side. The information about each time slot on the write side of the speech path memory SPM shows which position of the speech path memory SPM should be read. Such information can be written into the control memory CM under the software control of a controller (not shown). The time slot information on the write side is read from the control memory CM for each time slot on the read side thereof. The readout time slot information on the write side is input to the speech path memory SPM, from which data specified by the readout time slot information is read. During the above read operation, the position of each bit in each time slot is indicated by three-bit data generated and output by a counter CT1. In the above manner, data is read out from the speech path memory SPM in serial form.
In FIG. 3, each time slot, of all the time slots, has a basic-rate signal. In order to efficiently switch information having different frequency ranges, such as 64 kbps, 32 kbps, 16 kbps and 8 kbps, it is necessary for the controller (not shown) to know information about the frequency ranges.
FIG. 4 shows a conventional 32 kbps time switch capable of exchanging 64 kbps signals with 32 kbps signals in four-bit unit. The time switch shown in FIG. 4 writes the input signal in the speech path memory SPM in the sequential write manner while the write addresses are generated by the counter CT0. For example, when 32 kbps data is exchanged, the time slot number on the write side of the speech path memory SPM is placed at an address corresponding to the time slot position on the read side thereof. At this time, bit "2" is supplied, as bit information, to the speech path memory SPM. The bit "2" discriminates the first four bits "0"-"3", out of eight bits consisting of "0"-"7", from the second four bits "4"-"7". In the above manner, the time slot position of 32 kbps data (four bits) is exchanged.
When 64 kbps data (eight bits) is exchanged via the time switch shown in FIG. 4, two addresses of the control memory CM are needed because the time switch shown in FIG. 4 is designed to handle 32 kbps data (four bits). Thus, the read operation on the control memory CM must be carried out twice in order to handle 64 kbps data, and the software realizing the above-mentioned operation has a load which is twice that of the structure shown in FIG. 3.
The primary and secondary time switches SW0 and SW1 shown in FIG. 1 are formed with the time switches as shown in FIG. 4 in order to handle signals having different frequency ranges. Thus, the software of the multiplexing unit 75 has a large load.
Referring to FIG. 5, a speech path memory SPM0 and a control memory CM0 form the time switch 76 shown in FIG. 1, and a speech path memory SPM1 and a control memory CM1 form the time switch 78 shown in FIG. 1. The addresses of the control memories CM0 and CM1 which are directly handled by software are denoted by 0-7. Taking the control memory CM0 as an example, when 64 kbps data A is switched to the input channel from the input time slot, it is necessary to respectively write TS0,0 and TS0,1 in areas indicated by the addresses 0 and 1 of the control memory CM0 because A is placed in the areas of the addresses 0 and 1 of the speech path memory SPM0. Meanwhile, 32 kbps data `a` is placed in an area specified by address 4 of the speech path memory SPM0, and thus TS2,0 is written into an area specified by the address 4 of the control memory CM0.
When 64 kbps data is handled by a 16 kbps time switch, the address setting by software must be carried out four times. Similarly, when 64 kbps data is handled by an 8 kbps time switch, the address setting by software must be carried out eight times.


A dipole antenna includes a substrate, a first radiating member and a second radiating member. The substrate has a first surface and a second surface opposite to the first surface. The first radiating member and the second radiating member are symmetrically disposed on the first surface and the second surface of the substrate, and electrically connected to a grounding point and a feeding point, respectively. The first radiating member has a first radiating part, a second radiating part and a third radiating part, which are respectively disposed on the first surface and the second surface of the substrate and electrically connected to one another. The second radiating member has a fourth radiating part, a fifth radiating part and a sixth radiating part, which are respectively disposed on the first surface and the second surface of the substrate and are electrically connected to one another.

1. Field of Invention
The invention relates to an antenna, and more particularly to a dipole antenna with an effectively reduced dimension.
2. Related Art
The rapidly developed radio transmission has brought various products and technologies applied in the field of multi-band transmission, such that many new products have the performance of radio transmission to meet the consumer's requirement. The antenna is an important element for transmitting and receiving electromagnetic wave energy in the radio transmission system. If the antenna is lost, the radio transmission system cannot transmit and receive data. Thus, the antenna plays an indispensable role in the radio transmission system. Selecting a proper antenna can match the feature of the product, enhance the transmission property, and further reduce the product cost. Different methods and different materials for manufacturing the antennas are used in different application products. In addition, considerations have to be taken when the antenna is designed according to different frequency bands used in different countries. The commonly used specifications of frequency band include IEEE 802.11, the most popular bluetooth communication (IEEE 802.15.1), and the like. The bluetooth works at the frequency band of 2.4 GHz. IEEE 802.11 is further divided into 802.11a, 802.11b and 802.11g, wherein the 802.11a specification corresponds to the frequency band of 5 GHz, and the 802.11b and 802.11g specifications correspond to the frequency band of 2.4 GHz.
The most-frequently used antennas in the industry include a monopole antenna, an inverted-F antenna, and a dipole antenna. Because the dipole antenna can effectively radiate and receive the electromagnetic wave, it is widely used in various communication fields. However, if the conventional dipole antenna wants to reach the better polarization effect, its dimension cannot be effectively reduced, and the product dimension has to be increased and cannot meet the miniaturization trend of the current electrical device.
Therefore, it is an important subject of the invention to design a dipole antenna with an effectively reduced dimension such that the product can be minimized.


There is disclosed novel color-developing agents of the formula (I). There is also disclosed silver halide photographic light-sensitive materials and image-forming methods, using the color-developing agent. The color-developing agent is excellent in color-forming property, and the image obtained from the color-developing agent is good in hue. ##STR1## wherein R.sub.1 to R.sub.4 each represent a group of nonmetal atoms required to form, together with the carbon atom, a monocyclic 5-membered aromatic ring or a 5-membered aromatic ring condensed with another ring, with the proviso that at least two of R.sub.1 to R.sub.4 are nitrogen atoms; and Z represents an acyl group, a carbamoyl group, an alkoxycarbonyl group, an aryloxycarbonyl group, a sulfonyl group, a sulfamoyl group, an amidino group, or an imidoyl group.

In color photographic light-sensitive materials, when the photographic material is exposed to light image-wise and then color-developed, the oxidized color-developing agent and couplers are reacted, and an image is formed. In this system, color reproduction by the subtractive color process is used, and, to reproduce blue, green, and red colors, dye images are formed that are yellow, magenta, and cyan in color, respectively complementary to blue, green, and red.
Color development is accomplished by immersing the light-exposed color photographic material in an aqueous alkali solution in which a color-developing agent is dissolved (a developing solution). However, the color-developing agent in an aqueous alkali solution is unstable and liable to deteriorate with a lapse of time, and there is the problem that the developing solution must be replenished frequently in order to retain stable developing performance. Further, used developing solutions containing a color-developing agent are required to be discarded, and this, together with the above frequent replenishment, creates a serious problem regarding the treatment of used developing solutions that are discharged in large volume. Thus, low-replenishment and reduced discharge of developing solutions are strongly demanded.
One effective measure proposed for realizing low-replenishment and reduced discharge of developing solutions is a method wherein an aromatic primary amine developing agent or its precursor is built in a hydrophilic colloid layer of a color photographic material. Examples of the developing agents that can be built in include compounds described, for example, in British Patent No. 803,783, U.S. Pat. Nos. 3,342,597, 3,719,492, and 4,060,418, British Patent No. 1,069,061, West German Patent No. 1,159,758, JP-B ("JP-B" means examined Japanese patent publication) Nos. 14,671/1983 and 14,672/1983, and JP-A ("JP-A" means unexamined published Japanese patent application) Nos. 76,543/1982 and 81,643/1984. However, color photographic materials having these aromatic primary amine developing agents or their precursors built therein have a defect that satisfactory color formation is not attained when they are chromogenically developed.
Another effective measure proposed is a method wherein a sulfonylhydrazine-type developing agent is built in a hydrophilic colloid layer of a color photographic material, and examples of the color-developing agent that can be built in include compounds described, for example, in European Patent Nos. 545,491A1 and 565,165A1. However, even the developing agent mentioned therein cannot attain satisfactory color formation when color-developed; and further, when, for this sulfonylhydrazine-type developing agent, use is made of a coupler having a substituent at an active position (a position where coupling with the oxidation product of the developing agent will take place), there is the problem that color formation hardly takes place. In comparison with couplers unsubstituted at the active position, couplers having a substituent at the active position have the advantages that stain due to couplers can be reduced, and that the activity of the couplers can be easily adjusted by the substituent. Accordingly, there is strong need for a developing agent that, even when built-in, can provide satisfactory color formation when developed, and that also can show good color-formation property in developing an image, even when a coupler having a substituent at the active position is used.

Color-developing agent, silver halide photographic light-sensitive material and image-forming method


A test fixture for collecting particulate matter carried in the exhaust gas stream of an engine has a pair of coaxially aligned mounting plates, each having a filter cartridge holder mounted thereon. One of the mounting plates is moveable with respect to the other along a predefined longitudinal axis of the test fixture between an open position, whereat a filter cartridge is easily placed or removed, and a closed position at which a filter media mounted in the filter cartridge is sealed during a prescribed test sequence. An actuator mounted on a third coaxially aligned mounting plate has an extendable rod connected to the second mounting plate to effect movement of the second mounting plate between the open an closed positions.

1. Technical Field
This invention relates generally to a test fixture for holding a filter exposed to an exhaust gas stream, and more particularly to such a test fixture for collecting particulate matter emitted from an engine during a defined test sequence.
2. Background Art
The U.S. Environmental Protection Agency (EPA) has set very stringent emissions standards for nonroad engines and heavy-duty highway vehicle engines. The standards are directed at reducing smog-causing emissions from stationary engines, off-road vehicles, trucks, buses, recreational vehicles, and motor homes. In particular, standards set forth for model year 2007 limit heavy-duty highway engine particulate matter (PM) emissions to 0.01 g/bhp-hr.
Extensive engine development, testing, and validation will be required to achieve and certify that engines manufactured in 2007, and later, meet the required emissions standards. The U.S. Environmental Protection Agency (EPA) has issued revised procedures for testing various engine categories. This common set of test requirements is set forth in 40 CFR part 1065 and is intended to streamline laboratory efforts, beginning in 2007, for both the EPA and industry and provide a basis for internationally harmonized test procedures for nearly all categories of engines.
The laboratory testing procedures set forth in part 1065 determine brake-specific emissions for duty-cycle testing using an engine dynamometer. This typically consists of one or more test intervals, each defined by a duty cycle, which is a sequence of speeds and torques that an engine must follow. The EPA is also adopting a requirement that manufacturers of heavy-duty highway engines use ramped-modal testing to show that they meet steady-state emission standards using the Supplemental Emissions Test (SET). Much like the part 1065 procedures, ramped-modal testing becomes mandatory in the 2010 model year. Ramped-modal testing involves a single, continuous emission measurement as the engine operates over the test modes in a defined sequence, including short transition segments between modes.
Regardless of the specific test procedure, it is imperative that the various constituent components of the exhaust gas be accurately collected and measured. Particulate matter (PM) is typically collected on a new fine-mesh filter that has been tare-weighted and loaded into a clean filter cartridge. The loaded cartridge is then placed in a test fixture connected to at least a representative portion of the exhaust gas stream produced by the test engine. During the test, PM is collected on the filter during engine operation over a specified duty cycle. The filter is then removed from the test fixture and weighted. The difference between the initial tare weight and the after-test weight is the mass of the collected particulate matter.
Heretofore, the test fixtures used to house a filter cartridge during a test have been containers, such as clamshell or hinged holders that are loaded and moved to a test chamber where they were connected, or plumbed, into all or a predefined portion of the engine exhaust gas stream. These fixtures were cumbersome to use and time consuming to connect. Typically, the exhaust gas flowing through the test fixture is diluted with air to reduce the flow stream temperature. Prior to a test, the test fixture is heated to a prescribed elevated test temperature, for example 47° C., and maintained at that temperature throughout the test. Accordingly, the individual installing or removing the filter cartridge had to use extreme caution, or use special handling tools to prevent burn injuries. The use of gloves when handling a test cartridge is discouraged because of potential contamination of the sample media.
The present invention is directed to overcoming the problems associated with loading, housing and removing filters used a sample collection media in particulate matter engine emission testing. It is desirable to have a test fixture for collecting particulate matter that can be preinstalled as an integral component of a laboratory testing system. It is also desirable to have such a test system that has a sealable filter containment chamber that is readily accessible for installing, sealing, and removing a sample collection filter without connection or disconnection with a laboratory testing system. Moreover, there is a need for a test fixture for collecting particulate matter discharged in the exhaust gas from an engine that does not require extensive cooling time or the use of special handling equipment to remove the test fixture or the filter collection media after a test.

Test fixture for collecting particulate material


A system and method to enable a person to interact in both a physical world and an electronic world and enable a person to make Identity Protected Secured Purchases (IPSP) is described. The system includes a blank card containing an encoded strip, a password, a wireless communication device (cell phone with two-way satellite communication), and a server that delivers purchase approvals. The assigned blank card contains encoded information exclusive to the client that when presented, allows the retailer to request purchase approval from the server. The password is a series of numbers known only by the client. The assigned wireless communication device transmits its EIN (exclusive to the client) to the server and allows the client to input their password. The server includes a matching process that matches information from the client's blank card, password and, wireless communication device with information from retailers and other hosts that warrant the purchase approval. In the method, the client's identity is never exposed to the retailer. The client simply takes their receipt, the validation server authorizes the transaction and records it and the validation server keeps a record of the purchase.

1. Field of the Invention
The present invention relates to secure purchasing using credit in which a blank card containing information and a wireless communication device are coordinated with a validation server to provide a secured transaction.
2. Description of Related Art
Conventional credit card and debit card payment systems provide cashless payment for goods and services at points of purchase by use of a credit or debit card. The identity of the purchaser is shown on the front of the credit and/or debit card and a signature of the purchaser is provided on the back of the credit and/or debit card. It is often difficult for a merchant to determine from the signature if the purchaser presenting the credit and/or debit card is attempting to make a fraudulent transaction.
U.S. Pat. No. 7,014,107 describes a transaction method for secure payment by credit cards or debit cards for goods or services with the use or mobile devices. The payment authorization center delivers a public portion of the authorization token to the service provider via the existing communication channels and the private portion of the authorization token is delivered to the mobile device via SMS or USSD or e-mail short message. The mobile device delivers the private authorization token to the service provider via a private local network based on bluetooth, infrared or other short radio frequency based technology. The credit card or debit card number is never revealed and a temporary card token replaces it. This method is cumbersome and the response time is slow for approval.
It is desirable to provide an expeditions system and method for identity protected secured purchasing.

System and method for identity protected secured purchasing


A method is disclosed for performing a defect scan for a disk drive. Data is recorded on a first data area of a disk substantially free from defects and on a second data area of the disk substantially affected by at least one defect. A defect scan parameter is initialized with an initial setting. The first data area is read to determine a first defect threshold, and the second data area is read to determine a second defect threshold. A margin is saved representing a difference between the first and second defect thresholds. The setting for the defect scan parameter is adjusted, and the elements of reading the first and second data areas and saving a corresponding margin are repeated at least once. A setting is then selected for the defect scan parameter in response to the saved margins.

1. Field
The present invention relates to disk drives for computer systems. In particular, the present invention relates to calibrating a defect scan parameter for a disk drive.
2. Description of the Related Art
The disk in a disk drive is coated with a magnetic material which is magnetized with a write element (e.g., a write coil) in order to record information onto the surface of the disk. Various influences may render portions of the disk surface unusable (i.e., defective), for example, if the magnetic coating is not evenly applied to the disk surface or if a particle contaminates the magnetic coating. During a manufacturing "defect scan" procedure, the defective areas of the disk are located and "mapped out" so they are not used during normal operation. The defect scan typically entails writing a high frequency pattern (e.g., a 2T pattern) to the disk, and then reading the high frequency pattern while monitoring a quality metric, such as an amplitude of the read signal, a mean-squared-error of the read signal, a bit error of the read signal, a timing error of the read signal, or the output of defect scan filters having impulse responses matched to defect signatures. If the quality metric falls below a predetermined defect scan threshold, a defect is detected.
The disk is typically formatted to comprise a plurality of radially spaced, concentric data tracks each comprising a number of data sectors, wherein the defect scan maps defective data sectors to spare data sectors. If a defective data sector is not detected during the defect scan procedure, there is a risk of catastrophic data loss, either immediately, or over time as the uniform alignment of the magnetic grains deteriorates (magnetic entropy). Conversely, if the defect scan threshold is set too low in an attempt to detect more defective data sectors, more good data sectors will be identified as defective and mapped out unnecessarily, thereby reducing the capacity and performance of the disk drive.
There is, therefore, a need to improve the defect scan procedure of a disk drive by reducing the chance of missing defective data sectors without significantly increasing the number of good data sectors identified as defective.

Calibrating a defect scan parameter for a disk drive


A chemical-free and no-microbe method for pre-treating a broad range of waste waters is presented. The said method involves electrocoagulation (EC) operated in synchronization with electrolytic ozone (EO3). In the combinatory method, each technique not only applies its own treatments, they also create synergistic effects from real-time reactions among the reagents generated by electrolysis. Two refractory waste waters, seawater and tannery effluent, are tested by the combinatory method, EC+EO3, to assess the viability of the said method. Without adjustment, each of the said waste waters is remedied by EC+EO3 from its raw state to a clean condition more effectively and more economically than that can be delivered by the respective prevailing processes of pretreatment for each of the said waste waters.

1. Field of the Invention
This invention relates to a combination of two electrochemical techniques into a multi-effects method for pre-treating miscellaneous wastewaters. More specifically, the invention relates to electrocoagulation (EC) and electrolytic ozone (EO3) working simultaneously for quick abatement of the major pollution indices including COD, coloration, TSS, TOC, heavy metals, microorganisms and TDS of the treated waters without using chemicals and/or microbes.
2. Background of the Related Art
Water is vital to the survival of all life on the earth. Regardless of the water sources, water often requires some form of purification before use. Purification of water, or water treatment, is determined by the goals of end-use, such as, irrigation, aquatic cultivation, industrial production, or human consumption. Water can always be treated to the desired level of purity but, at a cost. When deciding a water-treatment protocol, one needs to consider the following factors: capital cost, power consumption, maintenance, throughput, foot-print area, secondary pollution, as well as post-treatment cost. Practically, capital cost and energy consumption are two most essential factors.
Seawater covers about 71% of the earth's surface, and it is the most abundant source of water. When water becomes scarce, people frequently look to the sea or ocean for water. Nevertheless, seawater is a complex waste water with average salinity of about 30 to 38 parts per thousand (ppt), or 30,000 to 38,000 parts per million (ppm), or 3.0 to 3.8%. The salinity of water is also referred as total dissolved solids (TDS) which is associated with water conductivity. In the 10 principal inorganic salts of seawater, the leading 2 ions are Cl− (55.04%) and Na+ (30.61%), followed by SO42−, Mg2+, Ca2+, K+, HCO3−, Br−, BO33− and Sr2+ to constitute 99% of the seawater salinity collectively. Besides the normal organic matter (NOM), seawater contains other organic materials depending on the estuary where seawater is taken for desalination. Distillation and reverse osmosis (RO) are the two most popular techniques for desalination around the world. For protecting boilers, heat exchangers and RO membranes from fouling by the inorganic salts and organic matters in seawater, various antiscalants or scale inhibitors, inorganic acids/bases, coagulants/precipitation agents and oxidants are employed for pre-treating the seawater as taught in U.S. Pat. No. 4,713,195; U.S. Pat. No. 7,862,727; and U.S. Pat. No. 7,931,809, as well as in Ning et al., Desalination and Water Treatment, Volume 9, pp 92-95 (2009), just to name a few. Distillation and RO are energy-thirst techniques, while distillation spends energy on heating seawater, RO consumes energy in the form of high pressure to extract freshwater out of seawater. In addition to power consumption, the use of chemicals and polymers in the pretreatments not only escalates the operation cost, but it also add burden to environment and post-treatments. Especially, RO expels treated water more polluted than the feed water to the sea, which causes severe damage to the ecology of discharge area.
Leather tanning is a centuries-old industry which provides materials for making shoes, furs/clothing, furniture, gloves, bags and belts. Leather is made from raw hide or skin, a byproduct of the meat industry, requiring an intensive use of water in many mechanical and chemical processing steps. For processing 850 Kg raw hide, it generally consumes 25-50 m3 of water and 150 Kg chemicals resulting in 250 Kg finished leather with 25-50 m3 waste water and 600 Kg solid wastes. Apparently, there are 150 Kg chemicals and 600 Kg solids dissolved or dispersed in the effluent needed to be removed prior to the discharge or re-use of the water. Although modern tannery fabrication techniques have significantly reduced the usage of water and metal, the tannery effluent is still a highly contaminated and hard-to-treat waste. Virtually all tannery effluents are black in color filled with fat, oil, grease (FOG), high SS (suspended solids, up to 3,000 ppm), high sulfide (strong foul smell), high COD (chemical oxygen demands, up to 50,000 ppm), high TKN (total Kjeldahl Nitrogen) and high TDS (up to 90 ppt). The pretreatment of tannery effluent includes flotation of FOG by dissolved air for skimming, and oxidation of sulfides by liming and aeration as taught in U.S. Pat. No. 4,913,826; U.S. Pat. No. 5,472,619, U.S. Pat. No. 6,649,067 and U.S. Pat. No. 7,670,493. In the pretreatment, a huge amount of power is spent on driving pumps, blowers, mixers and dryers (dehydrators). Furthermore, the process employs several large pools for outdoor exposure and flotation, which is space demanding and lack of sanitation. In the following primary and secondary treatments of tannery effluent, precipitation agents, coagulants and bacteria are extensively applied resulting in secondary pollution and high cost for handling the sludge produced.
Seawater and tannery effluent serve as two stubborn liquids for proving the principle and performance of the combinatory technique, EC+EO3, as a viable pretreatment method for remedying waste waters. The instant invention will present data on treating seawater and a tannery effluent by EC+EO3 using only electricity. As no chemical or microbe is involved in the treatments, the sludge formed in treating each of the said waste waters is a useful resource, an added value to the treatments by EC+EO3. The EC+EO3 treatment is also fast, energy effective and pollution free.


A vehicle seat includes a seat cushion, and a sliding apparatus provided underneath the seat cushion. The sliding apparatus has a lower rail, and an upper rail that slidably attaches to the lower rail. The seat cushion has a frame body that includes a pipe member. The pipe member has a main body portion that extends along an end edge of the seat cushion, a leg portion that extends downward toward the upper rail from an end portion of the main body portion, and a mounting portion that extends from a lower end portion of the leg portion and is flattened such that a hollow portion of the pipe member is small, all integrated together. The mounting portion has a flat surface that abuts against the upper rail, and is mounted to the upper rail.

1. Field of the Invention
The invention relates to a vehicle seat mounted in a vehicle or the like.
2. Description of the Related Art
A vehicle seat according to related art has a seat cushion and a sliding apparatus provided beneath the seat cushion, for example (see Japanese Patent Application Publication No. 7-51145 (JP-A-7-51145)). The sliding device has a lower rail and an upper rail that is slidably attached to the lower rail. The seat cushion has a frame that includes a pipe member. The pipe member is attached to the upper rail by a bracket.
However, in order to reduce the number of parts, there is a need for a vehicle seat in which the pipe member can be directly and easily attached to the upper rail.