Wipe dispensers are provided wherein particular wipe-gripping and wipe-ripping structures are provided to overcome problems encountered with the prior art. Particularly, gripping and ripping structures are provided to prevent the removal of more than one wipe at a time from a dispenser and to prevent a following wipe from falling back into the interior of a container when separated from a lead wipe being removed from the container. In particular embodiments, structures are provided to avoid pinching an individual's finger when feeding a wipe up through the gripping and ripping structures. In yet other particular embodiments, a boss is provided to prevent wipes from bunching up during the dispensing thereof.

Wipes dispensers are now in widespread use to provide individual wipes for various applications. Wipes dispensers typically include a container holding a plurality of wipes that are individually dispensed through an aperture in the container. The containers may be rigid plastic containers or flexible containers, for example, those made out of foil materials. The plurality of wipes may be provided on a roll, with individual wipes being defined between perforations in the roll. The plurality of wipes might also be provided as individual wipes interleaved together, much like a common box of tissues. The perforated roll and interleaved structures are provided so that pulling a lead wipe through a dispensing aperture in the container will cause another wipe to follow, and, once the lead wipe is removed and separated from the following wipe, the following wipe (hopefully) remains accessible at the exterior of the container, becoming the new lead wipe to thereafter be removed when desired. This is all very well known.
In order for the lead wipe to be separated from the following wipe, it is important that the following wipe be subjected to some type of resistance so that the lead wipe can be ripped off of the remainder at its perforations (in the case of a perforated roll of wipes) or disengage from being interleaved with the following wipe (in the case of an interleaved stack of wipes). Thus, a large number of different dispensing orifices exist in the prior art to provide resistance to the removal of wipes from a container. In some prior art embodiments, star-shaped or other specially-shaped apertures are provided so that, when a leading wipe is pulled through the aperture the special shape of the aperture serves to provide resistance to the following wipe, with the resistance intended to be sufficient for causing the separation of the lead wipe from the following wipe. In other embodiments, the aperture is provided as a slit in an elastomeric element, with the slit providing resistance to the pulling of the wipes out of the container.
These dispensing orifices of the prior art are provided to (a) separate individual wipes from a perforated web or interleaved stack of wipes, and (b) hold the lead wipe in such a manner that it is easily accessed for removal, when desired. That is, the dispensing orifice not only serves to separate a lead wipe from a following wipe but also to prevent the following wipe from falling back into the container, where the user would then have to take steps to access the interior of the container in order to access the wipe. However, it is well known that the dispensing orifices of the prior art often fail to separate a lead wipe from a following wipe, allowing what is herein termed a "roping" of the plurality of wipes. Roping occurs when separation is not achieved and multiple wipes are pulled from the container as a continuous string or rope. This is perhaps more common with a perforated roll of wipes but can occur with interleaved wipes as well. This leads to waste when only one wipe is desired, and is therefore not acceptable to the end user. When the dispensing orifice does successfully separate a lead wipe from a following wipe it serves what is termed herein an "anti-roping" function.
It is also well known that the dispensing orifices of the prior art often cause a lead wipe to separate from a following wipe too early, before the lead end of the following wipe has exited the interior of the container through the dispensing orifice. If this occurs, the following wipe remains inside the container, which must then be opened to access the wipes. The dispensing orifice thereby fails to serve what is termed herein an "anti-fallback" function.
Those familiar with the prior art will readily appreciate that the dispensing orifices do not always serve the anti-fallback and anti-roping functions. Indeed, it is quite common for the average user to pull more than one wipe from the interior of the container because the dispensing orifice has failed to separate a line of perforation or an interleaved connection. It is also common for the dispensing orifice to disconnect the wipes in such a way that the following wipe remains under the dispensing orifice and is not exposed at the exterior of the container, thus requiring the user to access the interior of the container to access the wipe. Quite simply, the dispensing orifices of the prior art fail to adequately and consistently perform both the anti-roping and anti-fallback features for which they are intended. The present invention seeks to provide a wipes dispenser having structures sufficient to consistently provide both anti-roping and anti-fallback functions.
Upon the initial purchase of a wipes dispenser containing a bulk supply of wipes, or, alternatively, in those instances when a wipe falls back into the interior of the wipes container, the user must access the bulk supply of wipes and feed the lead wipe through the dispensing orifice. Many dispensing orifices are formed in planar structures of generally rigid material, and, when the user inserts the lead wipe through the dispensing orifice by pressing the lead wipe up through the orifice with his or her finger, the planar structures in which the orifice is defined are deformed, and the finger is pinched upon retraction, as the rigid material returns to the planar structure. For example, the well known dispensing orifice structure in U.S. Pat. No. 6,554,156 presents a grip orifice defined by peripheral surfaces that spread under finger pressure and then move closer together as the finger is removed, thus pinching the finger. This is an annoyance to the end users, and the art would benefit from grip orifice structures that do not pinch a finger when a lead wipe is fed therethrough in a direction from the interior of the container to the exterior.
In a perforated roll of wipes, the wipes are fed to the dispensing orifice from the center of the roll. This is well known. As the string of wipes is fed from the center of the roll, the plurality of wipes tend to kink and twist and, at times, overlap and stick together, particularly when the wipes are wet. This twisting and bunching can result in multiple wipes bunching up directly under the dispensing orifice, and this can significantly increase the amount of force that must be applied to pull a lead wipe through the dispensing orifice. Additionally, when the wipes bunch up under the dispensing orifice it is more likely that the lead wipe will separate underneath the dispensing orifice and result in fallback of a following wipe. Thus, the art would benefit from structures serving to reduce or eliminate this tendency of the wipes to bunch up underneath the dispensing orifice.
When creating dispensing orifice structures, it is preferred that the structures be simple to manufacture. When somewhat rigid plastic materials are employed, it is preferred that the dispensing orifice structures be capable of being manufactured through simple open-and-close molds. Thus, in addition to addressing the issues raised above with respect to dispensing orifices, the art will benefit by providing dispensing orifices that solve one or more of the above problems and also can be made through molding in a simple open-and-close mold.


Method and apparatus for retaining a semiconductor wafer upon a pedestal within semiconductor wafer processing equipment. An electrostatic chuck contains a wafer support having a surface. Embedded beneath the surface is a number of electrodes defining a number of chucking zones. The electrodes are energized by a number of non-zero voltages thereby creating a variable, non-zero chucking force in each of the chucking zones. The method of retaining a substrate to a substrate support consists of biasing at least one of the electrodes with a first voltage of a first magnitude and biasing each previously unbiased electrode with a voltage of unequal magnitude of the initially biased electrode and every other previously unbiased electrode such that a non-zero chucking force exists in every zone. Wafer chucking zones of differing force improve uniformity of heat transfer gas layer distribution.

1. Field of the Invention
The invention relates generally to an apparatus and a concomitant method for retaining a workpiece within a semiconductor wafer processing system and, more specifically, to an improved electrostatic chuck that provides zones of varying chucking force to reduce heat transfer gas leakage, and improve heat transfer gas layer uniformity beneath the workpiece.
2. Description of the Background Art
Electrostatic chucks are used for retaining a workpiece in various applications ranging from holding a sheet of paper in a computer graphics plotter to holding a semiconductor wafer within a semiconductor wafer process chamber. Although electrostatic chucks vary in design, they all are based on the principle of applying a voltage to one or more electrodes in the chuck so as to induce opposite polarity charges in the workpiece and electrodes, respectively. The electrostatic attractive force between the opposite charges presses the workpiece against the chuck, thereby retaining the workpiece.
In semiconductor wafer processing equipment, electrostatic chucks are used for clamping wafers to a pedestal during processing. Since the materials and processes used to process a wafer are extremely temperature sensitive, temperature control is an important aspect of wafer processing. Should the materials be exposed to excessive temperature fluctuations resulting from poor heat transfer during processing, performance of the wafer process may be compromised resulting in wafer damage. As such, the pedestal may form a chucking electrode as well as a heat sink or heater as used in etching, physical vapor deposition (PVD) or chemical vapor deposition (CVD) applications.
To optimally transfer heat between the wafer and pedestal, a very large, nearly uniform electrostatic force is used in an attempt to cause the greatest amount of wafer surface to physically contact a support surface of the chuck. However, due to surface roughness of both the wafer and the chuck, small interstitial spaces remain between the chuck and wafer that reduce contact area and thus reduce optimal heat transfer. To improve heat transfer during processing, an inert heat transfer gas is pumped into the volume formed by the interstitial spaces between the support surface of the chuck and the wafer. This gas acts as a thermal heat transfer medium from the wafer to the chuck that has better heat transfer characteristics than the vacuum it replaces.
Since the distribution of heat transfer gas to the interstitial spaces is osmotic and the interstitial spaces may not be interconnected, some spaces do not receive any heat transfer gas. This condition leads to a non-uniform temperature profile across the backside of the wafer during processing and results in wafer damage. The uniformity of the chucking force serves to compound the problem as the wafer is held in place evenly across the support surface. Since effective and uniform heat transfer from the wafer is an important aspect of the manufacturing process, maximizing wafer exposure to the heat transfer gas contributes to the greatest heat transfer rate.
In addition to maximizing wafer exposure to the heat transfer gas, minimizing leakage of the heat transfer gas is also a wafer processing concern. Traditionally, the electrostatic chuck or the pedestal which supports the chuck contains an outer diameter raised rim. The rim is approximately the same diameter as that of the semiconductor wafer. As such, the wafer is supported at its outer edge by this rim. When an electrostatic clamping force is applied to the chuck, the wafer is pulled down to the support surface effectively creating a seal on the backside of the wafer at the rim. As discussed previously, a heat transfer gas into the process chamber is introduced to the backside of the wafer to improve heat conduction away from the wafer. Unfortunately, gas pressure drops significantly at the edge of clamped wafer because the volume of the interstitial spaces increases as the radius of the wafer increases. Additionally, a large amount of heat transfer gas leakage is known to occur at the rim. The clamping force pulls the wafer down while pressure from the heat transfer gas on the backside of the wafer pushes the wafer up causing the wafer to flex during processing. These opposing forces reduce the area of the wafer that is in contact with the rim. If the wafer is not seated properly on the support surface, a sudden reduction in chucking force occurs or a sudden increase in heat transfer gas pressure occurs due to an anomaly during wafer processing, substantial leakage of the heat transfer gas occurs at the reduced contact area.
Existing art in electrostatic chucks is limited by the uniform chucking force that chucks the wafer to the support surface. The uniform chucking force dictates that the wafer will be subject to the same downward force across the entire support surface regardless of characteristic weaknesses (i.e., reduced contact at the outer diameter rim and non-uniformity of heat transfer gas diffusion in some interstitial spaces) of the chuck. Two examples of such apparatus are disclosed in U.S. Pat. Nos. 4,384,918 issued May 24, 1983 to Abe and 5,452,177 issued Sep. 19, 1995 to Frutinger.
Therefore, there is a need in the art for an improved apparatus for retaining a wafer that modulates electrostatic chucking force across the support surface. Greater force is applied where it is needed most and reduced where uniform heat transfer gas diffusion would otherwise be inhibited. As such, temperature uniformity across the bottom surface of the wafer is attained.

Method and apparatus for improved retention of a semiconductor wafer within a semiconductor wafer processing system


In a hybrid car, or an electric motor-driven four-wheel-drive vehicle, in which an electric motor is driven directly by an output from a generator, vehicle running performance is enhanced. The output from the generator is controlled so as to maintain a generator torque in a range, in which the vehicle does not stall. Specifically, a driving apparatus for the hybrid car includes a second generator 2 driven by an engine 1 for driving one pair of either front or rear wheels 14, 15, an electric motor 5 driven through directly receiving the output from the second generator 2 and driving the other pair of either the front or rear wheels 14, 15, and a four-wheel-drive control unit 6 controlling driving of the second generator 2 and the electric motor 5. When the engine 1 is in an overloaded condition, the four-wheel-drive control unit 6 limits the output of the second generator 2.

1. Field of the Invention
The present invention relates to a hybrid car having an internal combustion engine and an electric motor as driving sources and a driving apparatus therefor. The present invention also relates to a hybrid type four-wheel-drive car having a transmission with a clutch and a control apparatus therefor.
2. Description of the Related Art
Examples of hybrid cars having an internal combustion engine and an electric motor as driving sources are known from Japanese Patent Laid-open Nos. 2000-272367 and 2001-63392. Disclosed in Japanese Patent Laid-open No. 2000-272367 is a four-wheel driving apparatus, in which a generator is driven by an engine driving a front wheel and an electric power generated by the generator is used to drive an electric motor driving a rear wheel (refer, for example, to page 3 and FIG. 1 of Japanese Patent Laid-open No. 2000-272367). In Japanese Patent Laid-open No. 2001-63392, a front-and-rear wheel drive vehicle is disclosed, in which an engine driving a front wheel drives a generator, while a motor generator driving a rear wheel is driven by an electric power generated by a generator and supplied by way of an inverter or an electric power accumulated in a capacitor (refer, for example, to page 3 and FIG. 1 of Japanese Patent Laid-open No. 2001-63392).
A hybrid four-wheel-drive car having an engine for driving either pair of front or rear wheels and a motor for driving the other pair of wheels, either front or rear, is disclosed, for example, in Japanese Patent Laid-open Nos. 2002-218605 and Hei 8-300965 and in the November issue (No. 578) of "Nikkei Mechanical" (pp. 53 to 58). An automatic manual transmission for a parallel type hybrid car is disclosed, for example, in Japanese Patent Laid-open No. 2000-272360.
Disclosed in Japanese Patent Laid-open No. 2002-218605 among other prior art techniques is a control apparatus of a driving force for a vehicle provided with an internal combustion engine driving at least either pair of front or rear driving wheels and a generator driven by the power from the internal combustion engine. This driving force control apparatus for a vehicle is provided with driving wheel slip estimation means that estimates whether or not the driving wheels slip during acceleration. The control apparatus is further provided with generator control means that is activated when the driving wheel slip estimation means estimates that the driving wheels slip in acceleration and controls so as to bring torque of the generator to a level equivalent to a power generating load torque corresponding to the amount of acceleration slip the driving wheels make.
Disclosed in Japanese Patent Laid-open No. Hei 8-300965 is a front-and-rear wheel drive vehicle having an engine for driving either pair of front or rear wheels and an electric motor for driving the other pair of wheels, either front or rear. This front-and-rear wheel drive vehicle is provided with means for detecting the value of μ on a road surface. The vehicle is further provided with control means that operates the electric motor so as to bring an output torque of the electric motor to a predetermined value corresponding to the detected value of μ when the vehicle is started with the detected value of μ being a predetermined value or less.
In an electric motor-driven four-wheel-drive vehicle, in which the electric motor is driven directly by an output from a generator (hereinafter referred to as the "motor-driven four-wheel-drive vehicle"), the following control is provided. Specifically, when, for example, an attempt is made to start a vehicle or get the vehicle out of a rut, in which case there is a great torque requirement with a low vehicle speed, a current value and a voltage value of a power output from the generator are controlled so that a large current value and a small voltage value of a power input to the electric motor are provided. While the vehicle is running, in which case there is a small torque demand with a high vehicle speed, on the other hand, the current value and the voltage value of the power output from the generator are controlled so that the small current value and the large voltage value of the power input to the electric motor are provided. That is, the motor-driven four-wheel-drive vehicle is controlled so that the maximum torque is output from the electric motor when the vehicle is started and the torque of the electric motor decreases as the vehicle speed increases.
According to such control as mentioned above, driving performance comparable with that offered by a mechanical type four-wheel-drive vehicle can be provided by the motor-driven four-wheel-drive vehicle over a wide operating range. There is, in the motor-driven four-wheel-drive vehicle, a need for improving vehicle running performance even further so as to bring it near that achieved in a mode in which two wheels are driven (hereinafter referred to as the two-wheel-drive mode).
In Japanese Patent Laid-open No. 2000-272360, an automatic clutch type transmission mounted in a two-wheel-drive parallel hybrid car is disclosed for improved fuel economy. It is, however, difficult to apply this clutch type transmission to a four-wheel-drive hybrid car having an engine for driving either pair of front or rear wheels and a motor for driving the other pair of wheels, either front or rear. Japanese Patent Laid-open Nos. 2002-218605 and Hei 8-300965 are not, on the other hand, concerned with disconnection of torque generated when the clutch is disengaged during a gearshift. Unless a driving force is obtained during a gearshift, there is likelihood that acceleration performance will be degraded during a gearshift, performance in getting the vehicle out of mud will be degraded, and other performance degradation will result.
To solve these problems, it will readily occur to those skilled in the art that, in the hybrid car using the clutch type transmission, a battery or a capacitor mounted therein is used during a gearshift to apply an electric power to the motor when the clutch is disengaged, thereby obtaining a driving force. Simply detecting a disengaged condition of the clutch and letting the motor generate torque could give a driver an awkward feeling that does not exactly match his or her intention. There is still another problem that the battery and capacitor are expensive. There is therefore a need for obtaining the driving force using a simpler and easier method.

Hybrid car and control apparatus therefor, and hybrid four-wheel-drive car and control apparatus therefor


Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive of the bit lines.. The supply timing for the power supply voltage to each sense amplifier bank is controlled according to the wiring length between the supply nodes CT0, CT1, CT2 for the power supply used for the driving of the sense amplifiers and each sense amplifier bank SB0 to SB16, and since the supply time for the overdrive voltage to the sense amplifier bank SB0 at the near end is set short and the supply time for the overdrive voltage is set successively longer as it goes towards the far end, the sensing delay that originates in the voltage drop that is generated in the wiring between the supply nodes and the sense amplifier banks is compensated for, uniformity of the overdrive for the bit lines at both the far and near ends can be achieved, the excessive overdrive at the sense amplifier bank (memory cell mat) at the near end can be avoided, and by extension, a reduction of the power consumption can be realized.

FIG. 12 shows one construction example of a memory array for a semiconductor memory device, for example, a DRAM. In FIG. 12, the memory array is constructed by means of the word lines WL0 to WL5, bit lines (or complementary bit lines) BL0, BL0.sub.--, BL1, BL1 and the memory cells MC.sub.0,0, MC.sub.0,1, MC.sub.0,2, . . . , MC.sub.1,4, MC.sub.1,5 that are respectively connected at the intersection points of these word lines and bit lines (and complementary bit lines). In this Figure, only a portion of the memory array is shown for the purpose of explanation. The bit line pair comprising bit line BL0 and complementary bit line BL0.sub.-- are connected to the sense amplifier SA0, and the bit line pair comprising bit line BL1 and complementary bit line BL1.sub.-- are connected to the sense amplifier SA1. During memory access, the bit line and the complementary bit line comprising a bit line pair are respectively held at different voltage levels by means of the sense amplifier. For example, when the bit line BL0 is held at a high level (power supply voltage V.sub.DD level, the complimentary bit line BL0.sub.-- is held at a low level (common voltage V.sub.SS level). The word lines WL0 to WL5 are selected and driven by means of the word line drive circuit WD. In FIG. 12, the word line drive circuit WD is omitted.
The memory cells MC.sub.0,0, MC.sub.0,1, MC.sub.0,2, . . . , MC.sub.1,4, MC.sub.1,5 are arranged at the intersection points of the word lines WL0 to WL5 and the bit lines BL0, BL0.sub.--, BL1, BL1.sub.--, respectively. As is shown in the FIG.ure, the memory cells of the DRAM, for example, the memory cell MC.sub.1,1 is constructed by means of a single transistor Q.sub.1,1 and a single capacitor C.sub.1,1, the gate of transistor Q.sub.1,1 is connected to the word line WL1, and is controlled to the ON/OFF state by means of the voltage of word line WL1. During memory access, one of the word lines among the word lines WL0 to WL5 is selected by means of the word line drive circuit WD in response to the input address signal, and since the selected word line is activated and held at a high level, the transistor for the memory cell that is connected to the selected word line is held in the ON state.
For example, if word line WL1 is selected by means of the word line drive circuit WD and held at a high level, transistor Q.sub.1,1 of memory cell MC.sub.1,1 is placed in the ON state. During writing, the level of the bit line is designated in response to the write data by means of the sense amplifier at the same time as the selection of the word line. For example, bit line BL1 is held at a high level (power supply voltage V.sub.DD level), and complementary bit line BL1.sub.-- at the low level (common voltage V.sub.SS level), respectively, by means of the sense amplifier SA1. By this means, the charging voltage and the charge of the capacitor C.sub.1,1 is held as the storage data.
On the other hand, when the storage data are read from the memory cell MC.sub.1,1, the bit line BL1 and the complementary bit line BL1.sub.-- are set beforehand via the sense amplifier SA1 to a precharge of, for example, V.sub.DD /2, which is half of the power supply voltage V.sub.DD. When the word line WL1 is activated by means of the word line drive circuit WD and held at a high level, the transistor Q.sub.1,1 is placed in the ON state, the bit line BL1 and the capacitor C.sub.1,1 are shorted, and the potential of the bit line BL1 is slightly changed in response to the accumulated charge of the capacitor C.sub.1,1. By means of this slight potential change on the bit line BL1 being detected and amplified by means of the sense amplifier SA1, the storage data for the memory cell MC.sub.1,1 are read.
Accompanying the change to a large capacity for the DRAM, the memory array has been further divided into multiple subarrays (memory cell matrices), and have become a construction that arranges sense amplifier banks comprising sense amplifiers on the side of each subarray. The sense amplifier banks are constructed by means of sense amplifiers of the same number as the bit line pairs for each subarray, and each sense amplifier bank is jointly used by means of sub-arrays that are arranged on both the right and left sides. Also, means of reducing the number of sense amplifiers by means of lengthening the bit lines and widening the subarrays, a reduction of the surface area that the sense amplifier banks occupy in the entire chip is accomplished, and a reduction of the chip size is accomplished. However, the deterioration of the characteristics that accompanies an increase in the resistance and parasitic capacitance of the bit lines due to their lengthening becomes a problem. Systems such as a construction in which the bit lines are changed to tiers have been proposed for purpose of handling this.
Also, along with the advances in the change to high capacity and miniaturization of the semiconductor memory devices, the miniaturization of the elements has advanced, and the change to thin films for the purpose of low voltage operations has also advanced. In order to ensure the gate voltage tolerance of the transistors that construct the memory cell, an internal voltage V.sub.DL that is lower than the external power supply voltage in which the external power supply voltage V.sub.DD has been dropped is being used inside the memory array. Accompanying this, the lowering of the access speed has become a problem with the sense amplifier. In order to avoid this, the so-called overdrive OVD system is being used, which supplies the external voltage power supply voltage V.sub.DD to the sense amplifier for a normal fixed period, for example, the period until the bit line has reached the memory array voltage (internal operating voltage V.sub.DL).
Incidentally, because a voltage drop originating in the sense amplifier voltage wiring resistance appears between each memory cell mat with the above-mentioned overdrive system used in the past, even if it is within the same memory array block, the optimum sense amplifier overdrive amount is different between each memory cell mat.
For example, in the 64 Mb (megabit) DRAM used in the past, in order to ensure sufficient writing at the farthest end, the timing for the overdrive was optimized at the farthest end (worst case). By this means, the overdrive at the farthest end was ensured, but it became a surplus overdrive at the nearest end, and the surplus charge was discarded. In other words, at the sense amplifier for the near end, a voltage application was conducted that was greater than necessary during memory access, and there were disadvantages in that this invited the deterioration of the characteristics of the transistors that construct the sense amplifier, and invited an increase in the power consumption.
FIG. 13 shows the changes in the bit line voltage for the memory cell mat of the near end and far end when reading is performed. In the case of this example, the power supply voltage V.sub.DD is, for example, 3.3 V, and the lowered voltage V.sub.DL that is used within the memory array is, for example, 2.2 V. As is illustrated, before reading, the bit line BL and the complementary bit line BL- are precharged to a voltage level of one half of the internal power supply voltage V.sub.DL, for example, 1.1 V, and after starting reading, in response to the storage data of the memory cell, for example, the bit line BL- is charged by means of the power supply voltage V.sub.DD, and the complementary bit line BL is discharged by means of the common voltage V.sub.SS. Since the application time for the power supply voltage V.sub.DD to the bit lines BL in other words, the time T.sub.OVD for the overdrive is sent by matrixching it to the sense amplifier for the farthest end, the bit line that is connected to the sense amplifier for the farthest end is properly charged to the internal power supply voltage V.sub.DL by means of the overdrive operation, but at the bit line BL that is connected to the sense amplifier for the near end, it is charged to a surplus due to the same overdrive time T.sub.OVD, and when the overdrive is completed, is held at a level that is higher than the internal V.sub.DL. Since the complementary bit line BL.sub.-- is discharged by means of the common voltage V.sub.SS in the case of either the far end or the near end, its voltage is about the same.
This invention was made after reviewing this information, and its purpose is to offer a semiconductor memory device in which the timing for the overdrive can be controlled in response to the arrangement positions of the memory cell matrices, the bit lines can be driven at the optimum voltage, a reduction in the power consumption can be accomplished, and the timing design for the overdrive can be simplified.


Systems, devices, and methods for provisioning a device receive authentication information from a user interface; send the authentication information to an identity provider device; receive a token at the registration device from the identify provider device; send the token, device information of a new device, and a provisioning request from the registration device to a provisioning service; receive an activation code at a user interface of the new device; send the activation code and the token from the new device to the provisioning device; and receive a key from the provisioning device, the key being associated with the device identifier of the new device.

1. Technical Field
This description generally relates to provisioning devices.
2. Background
Many devices are equipped to provide services to users or devices over a network connection. For example, multi-function printers ("MFPs") may implement web servers and may be able to communicate with remote users via an intranet or even the Internet. Additionally, devices are often configured to operate in a certain environment (e.g., network settings, user permissions, device relationships). Device provisioning prepares a device to provide services to users in an environment.

Devices, systems, and methods for device provisioning


A blade member 1 is used for removal of residual toner 5 remaining on a surface of a counterpart member 4 in an image forming device employing an electrophotographic system, by sliding contact with the counterpart member 4. The blade member 1 includes a blade body 11 made of a polyurethane rubber using diphenylmethane diisocyanate and a polyester polyol as main raw materials, and a film 12 that covers at least a surface of a sliding contact portion of the blade body 11 to contact with the counterpart member 4. The polyurethane rubber has an international rubber hardness degree of 65 to 85 IRHD, a tan δ peak temperature of 8° C. or lower, and a tan δ peak value of 1.1 or less. The film 12 contains a hydrocarbon polymer as a main component.

In a conventional image forming device employing an electrophotographic system, a cleaning blade including a blade member has been disposed around a photoreceptor, the blade member has been in sliding contact with the photoreceptor, and residual toner remaining on the surface of the photoreceptor is removed by scraping off. For the material of the blade member, a flexible and relatively inexpensive polyurethane rubber is generally used. The cleaning blade generally has various functions for a reduction in frictional force with the photoreceptor.
For example, Patent Document 1 discloses a blade for an electrophotographic device, in which a flexible diamond-like carbon film (hereinafter, sometimes referred to as "FDLC film") is formed on a contact portion of an elastomer made of a polyurethane rubber, with a counterpart member, by the plasma CVD method.


A method of detecting a target substance includes contacting the target substance with a substrate. The substrate has a first receptor bound to the substrate. The target substance binds to the first receptor. The method further includes contacting a second receptor with the substrate. The second receptor is associated with the target substance. The second receptor is biotinylated. The method also includes contacting an anti-biotin antibody conjugated paramagnetic particle with the substrate.

Increasingly, industry is seeking detection methods for low concentration analytes. From detection of early stages of disease to early warning of chemical and biological hazards, detection of analytes increasing is becoming of concern to society.
In particular, medicine is seeking to detect viral infections, such as HIV, at earlier stages. Early stage detection leads to treatment when a disease in manageable. For example, anti-viral medications have shown increased efficacy, possibly to the point of curing infected HIV patients when administered early. In other examples, early detection of avian influenza may lead to improved treatment of patients and prevention of epidemics.
In another example, militaries and civil defense agencies are seeking early warning and detection systems for chemical and biological agents. With increased threat of terrorism and rogue governments, concern about chemical or biological attacks has grown. Detection of analytes and residue relating to such agents may lead to improved security and faster response, ultimately saving lives.
Further, analyte detection is useful in research. Industry is seeking to automate and miniaturize experimentation, leading to a desire for detection methods that are sensitive and may be performed with small quantities. However, traditional methods are often expensive and inefficient. For example, gas chromatography and mass spectrometry use large cumbersome equipment that is expensive to maintain. In other exemplary methods, such as test strips and titration, the output is less sensitive to reagents and analytes. In addition, such methods, while convenient, are inaccurate and often, subjective. For biological samples, culture methods are time consuming and use expert training to achieve results. In particular, DNA testing through gel electrophoresis is time consuming and utilizes a large quantity of DNA. While the DNA may be replicated to produce the quantity used in testing, such replication adds time to the testing process.
As such, an improved method of detecting analytes would be desirable.

Systems and methods for detecting target analytes


Bowling lane conditioning oil in an aerosol container which has a propellant for dispensing the oil through a spray nozzle in an aerosol form. The oil includes a mixture of mineral oil, a leveling agent, and an antistatic agent. The mineral oil is a combination of paraffin and petroleum based mineral oils, and in some embodiments, the mixture also includes isopropyl alcohol, a fluorescent whitening agent, and a lubricity agent.

1. Field of the Invention
This invention pertains generally to the preparation and care of bowling lanes and, more particularly, to a conditioning oil for use on bowling lanes.
2. Related Art
Conditioning oil is applied to the surface of bowling lanes to provide proper ball action. The oil is applied to the head and center portions of each lane so that the ball will slide over them and then grip the surface as it approaches the pin deck.
The oil has a significant effect on the manner in which the ball travels down the lane, and proper oiling is very important for consistent action and scoring. If the oil gets picked up by the ball and carried down the lane or is pushed down the lane ahead of the ball, the oil can get onto the pin deck where it can cause the pins to slide around instead of falling. If the oil gets into the bail return machine, and it can gum the machine it up and interfere with its operation.
With too little oil, the ball does not slide far enough before taking hold of the lane, which results in too much hook or hooking or in an unpredictable and uncontrollable manner.
In addition, channels can form in the oil where the balls have travelled, causing uneven oiling and further inconsistencies in the manner in which the balls behave on the lane.
In the head area, the oil needs replenishing more often than in other portions of the lane because the balls tend to carry the oil out of that area and down the lane. Also, the ability of the oil to fill back in behind the ball and thereby prevent the formation of channels is particularly important in the head area.
At one time, conditioning oil was applied to bowling lanes with Hudson sprayers similar to the hand pumped pressurized sprayers used in gardening applications. However, those sprayers have not been available for years, and the oil is currently applied with machines having rollers which apply the oil to the lanes.


A process for forming pliable elements curable by hot pressing to form high temperature resistant elements is disclosed. In this process, a metal, a metal compound, or a mixture thereof, which has some water of hydration, is mixed with orthophosphoric acid in an amount sufficient to form a resultant mixture having a pH value no greater than 0.85. A refractory material is added to the mixture and a resultant pliable curable material is formed. An element of a preselected configuration is formed from the pliable curable material. The element is dried at a temperature less than about 100.degree. C. for a period of time sufficient to form a pliable curable element having a stable unitary mass. The pliable element is cured by "false melt" processing techniques.

A process for forming elements for use in high temperature environments using the "false-melt" processing technique has been disclosed in U.S. Pat. No. 5,620,645, issued to Crumpacker et al. This process is useful for forming high temperature resistant elements by pre-heating and hot pressing "green" parts to within the "false-melt" range and then allowing the part to cure. However, these "green" parts are very hard and stiff in their dry uncured state and thus may not easily conform to complex geometrical shapes.
It has been very desirable to have an improved "false-melt" process to form "green" parts that, when dried, are soft and pliable, thus formable into a pliable tape or film, or pliable sheets. It has been desirable to form pliable sheets so that the sheet can be easily pressed to mimic complex geometrical shapes in a mold prior to pre-heating and hot pressing, without cracking such "green" parts.
The present invention is directed to overcome one or more of the problems as set forth above.

Process for forming a high temperature resistant, flexible, pliable elements curable by false-melt technique


A networked computer with a networking framework that can operate in accordance with a standard protocol or may be configured to perform one or more functions that alter or extend processing according to the standard. The framework includes extensibility points and a mechanism to receive plug-ins that may perform extensibility functions. Network profile information indicates configuration of the extensibility points, including specific extensibility functions to be executed at the extensibility points. This information may be used to configure the extensibility points so that, as the computer operates, the extensibility functions are selectively executed instead of or in addition to standard functions.

The rapidly evolving networking industry introduces new standards and innovation by independent software vendors (ISVs) and independent hardware vendors (IHVs) at a rate that often outpaces the development schedule of operating system providers. Consequently, when ISVs and IHVs want to implement a new functionality that is not supported by a computer's operating system, they must develop a customized application which typically requires replacing substantial, if not all, portions of existing operating system networking services.
For example, if an ISV wants to implement some security aspect or proprietary extension to the networking software that is unsupported by the operating system, there are several pieces of software that must first be written by the ISV or another third party to enable connectivity by the new device. The ISV must provide a driver to manage the device, connectivity software that runs whenever the device is enabled, and various experience elements, which determine how connection and disconnection will occur, how connection status will be reported, how ISV profiles will be installed and propagated.


This invention relates to a polymeric vehicle which is effective for providing a high solids formulated coating composition. The polymeric vehicle comprises a blend of at least one nonmesogenic substantially linear oligoester diol and at least one hardener which is a mesogenic polyol, phenolic ester alcohol or crystalline polyol, which blend is effective for reaction with a crosslinker which is reactive with the nonmesogenic oligoester and hardener.

One of the primary components in paint is the "film-former" that provides a film for the protective function for a substrate coated with the paint. Film forming components of liquid paints include resins which have required organic solvents to provide the resins with suitable viscosities such that the paint can be applied by existing commercial application equipment. Use of organic solvents, however, raises at least two problems. In the past and potentially in the future, petrochemical shortages mitigate against the use of organic solvent in great volumes. Second, environmental concern mitigates against the use of organic solvents and requires such use be minimized.
Environmental concern has become increasingly important. This concern not only extends to preservation of the environment for its own sake, but extends to public safety as to both living and working conditions. Volatile organic emissions resulting from coating compositions which are applied and used by industry and by the consuming public are not only often unpleasant, but also contribute to photochemical smog. Governments have established regulations setting forth guidelines relating to volatile organic compounds (VOCs) which may be released to the atmosphere. The U.S. Environmental Protection Agency (EPA) has established guidelines limiting the amount of VOCs released to the atmosphere, such guidelines being scheduled for adoption or having been adopted by various states of the United States. Guidelines relating to VOCs, such as those of the EPA, and environmental concerns are particularly pertinent to the paint and industrial coating industry which uses organic solvents which are emitted into the atmosphere.
To reduce organic solvent content and VOCs, researchers have developed high solids coating compositions and powdered coating compositions. High solids compositions generally are liquid and are designed to minimize solvents. Powdered coating compositions are solid powders and generally eliminate solvents. While each have advantages, each coating composition has disadvantages.
Coating compositions which include high solids polymeric vehicles based upon polyesters have become popular. In high solid polyesters are opposed to "conventional" compositions which use organic solvents, high molecular weight generally needs to be achieved during crosslinking rather than being attained from the basic polyester polymer. Hence, high solids polyesters normally supply a greater number of reactive sites (predominantly hydroxyl groups) available for crosslinking. The resultant polymers typically exhibit 70-80% solids-weight when reached stoichiometrically with isocyanate crosslinkers, but frequently yield empirical solids up to 18% lower, when crosslinked with melamine resins. Despite their reduced use of organic solvents, high solids polyester coating compositions can be produced on the same equipment and be employed in many of the same applications as lower solids "conventional" polyester coating compositions. Further, as a result of their many strengths such as ease of manufacturing and use, low volatile emissions, reduced energy requirements, greater application efficiency, lower handling and storage costs, and excellent physical properties, high solids polyester coating compositions have enjoyed spectacular growth in manufacture and use. They still require organic solvents, however, and are a source of VOCs.
Powder coatings and UV-curable coatings are desirable ultrahigh or 100% solids coatings. However, there are limitations as to the technique and the equipment which are used to apply the powdered composition.
To reduce solvent content and VOCs in polymeric vehicles and formulated coating compositions for paints, researchers have been driven by three major objectives: controlling the reactivity of the film forming components in the paint; keeping the viscosity of the components in the paint low to minimize the organic solvents in the paint and to keep the VOCs in the paint at the lowest possible level; and keeping the components in the paint at a low volatility to minimize VOCs.
One way to reduce VOCs is to further reduce organic solvent content and increase the solids level of the coating composition to an ultra high solids level. High viscosity is a major problem which needs to be solved in ultrahigh solids coatings. In high solids polyester coatings, the viscosity of concentrated polyester solutions depends on several variables. Molecular weight and molecular weight distribution are two important factors. According to polymer physics theory, the viscosity of polymers in the liquid state depends mainly on the average molecular weight and the temperature, so it is desirable to reduce average molecular weight for solventless polyester coating. The major factor controlling number average molecular weight (M.sub.n) of a polyester is the mole ratio of dibasic acid/diol or polyol. A dibasic acid to diol or polyol ratio of the order of 2:3 is typical. However, loss of polyol during the production of the polyester can result in a significantly higher number average molecular weight than predicted from the starting ratio. It is necessary to add some extra glycol to compensate for loss. Further, in ultra high solids coatings, the low molecular weight fraction of resin in the polymeric vehicle may be volatile enough to evaporate when a thin film is baked. Such loss has to be counted as part of the VOC emissions.
The number of functional groups per molecule also affects the viscosity because of hydrogen bonding. Most oligomers or polymers require high functionality to achieve a highly crosslinked film and reasonable Tgs to have adequate film properties for most applications. The high functionality tends to increase the viscosity significantly.
An object of the invention is to provide a polymeric vehicle which will reduce or eliminate VOCs.
Another object of this invention is to provide polymeric vehicles which are not only low in VOCs, but which provide coating binders with good film properties such as hardness and impact resistance.
Yet another object of this invention is to control the viscosity to low levels at a specific shear rate of a liquid polymeric vehicle or liquid formulated coating composition without using organic solvents or water for such control.
Further, objects and advantages of the invention will be found by reference to the following description.

Polymeric vehicle for high solids coatings


A method for planar transformer with an odd turn ratio includes: determining a turn ratio and winding parameters of a transformer to be manufactured; if the turn ratio is odd, determining that there is respectively one winding turn on a first middle layer and a second middle layer and two winding turns on a top layer and a bottom layer; determining widths of winding wires on marginal layers as well as widths of winding wires on middle layers; winding and parallelly connecting an inner winding wire on the top layer to an inner winding wire on the bottom layer, and then serially connecting the parallel-connected inner winding wires to an outer winding wire to form a primary winding; and parallelly connecting the winding wire on the first middle layer to the winding wire on the second middle layer to form a secondary winding, so as to obtain the transformer.

In recent years, scientific and technological advances bring continuous improvement of power electronics. Isolation transformers have been widely used in the fields of new energy and distributed generation. Furthermore, with continuous improvement of magnetic integration, planar transformers have received more extensive attention on the aspects of application and technical research. The winding of most planar transformers is performed on printed circuit boards (PCBs), and single-layer winding or asymmetric multi-layer winding are generally adopted in a case of odd turn ratio. Such traditional winding modes require a large window area of magnetic cores or an increase in layers of the PCBs. As a result, the volume and design cost of the transformers are increased. Besides, asymmetric structures such as 2+1 structures will be caused by multi-layer structures in most cases. This may affect the distribution of magnetic fields of the transformers, and reduce the efficiency of the transformers.
When a planar transformer with an odd turn ratio is manufactured, asymmetry of the magnetic fields and low operating efficiency will be caused by the traditional winding modes.

Method for manufacturing planar transformer with odd turn ratio


There are provided a connector body having an accommodating recess in which a pair of ferrules and a pair of springs, respectively fitted over a pair of optical fibers, are accommodated, as well as a connector cover. The connector cover is provided with fixing pins, and the connector body is provided with fixing holes into which the fixing pins are press fitted. A spring pressing portion is provided on the connector cover for pressing the spring with a natural length in the direction toward its distal end at two positions when the fixing pins are press fitted into the fixing holes, and for holding the spring in a compressed state when the fixing pins have been press fitted. A guide taper is formed at a tip of the spring pressing portion. A pressing-portion fitting groove for inserting and guiding the spring pressing portion is provided in the connector body.

1. Field of the Invention
The present invention relates to an optical connector which is used in interconnecting a pair of optical fibers or interconnecting an optical fiber and a photoelectric conversion element.
2. Description of the Related Art
An optical signal transmission path using optical fibers is generally laid by optically connecting the optical fibers by using optical connectors or the like at appropriate distances. As conventional optical connectors of this type, those described in, for example, Japanese Utility Model Unexamined Publication No. Sho. 61-126204 and Japanese Patent Examined Publication No. Hei. 8-7306 are known.
Namely, in the optical connector disclosed in Japanese Utility Model Unexamined Publication No. Sho. 61-126204, a housing for accommodating a pair of ferrules is split into upper and lower parts, and accommodating grooves for accommodating the ferrules and a pair of springs (compression coil springs) or the like are formed in the upper and lower parts of the split housing. In this structure, the upper and lower parts of such a housing are secured to each other by screwing down in a state in which the ferrules and the springs or the like are clamped from both upper and lower sides in the portion of the accommodating groove and are thereby prevented from coming off and are held.
On the other hand, the optical connector disclosed in Japanese Patent Examined Publication No. Hei. 8-7306 is provided with a plug body and a floating holder disposed floatably within the plug. A ferrule accommodating recess 102 and a holding-member fitting recess 103 are formed in this floating holder 101, as shown in FIG. 36.
Then, ferrules 105 and springs 106 which are fitted over distal end portions of optical fibers 104 are inserted into the ferrule accommodating recess 102 and the holding-member fitting recess 103 of the floating holder 101, and a ferrule pressing member 107 is inserted into the holding-member fitting recess 103. As a result of the insertion of this ferrule pressing member 107, retaining portions 107a of the ferrule pressing member 107 are engaged in retained portions 101a of the floating holder 101, and are thereby prevented from coming off and held.
At this time, the ferrules 105 are urged in the inserting direction, i.e., in the direction toward their distal ends, by the springs 106 which are in the compressed state.
In this structure, the floating holder 101 in the assembled state is accommodated in the aforementioned plug body of the type split into the upper and lower parts, and the upper and lower parts of the plug body are screwed down and are secured to each other.
However, in accordance with the above-described structure in which the housing or the plug body having the structure split into upper and lower parts is fixed by screwing down, there has been a drawback in that since the number of assembling steps increases, the assembling operation is time-consuming and troublesome. In addition, a screw and a nut are required, so that there is another problem in that the number of parts used increases.
Further, in accordance with the system disclosed in Japanese Patent Examined Publication No. Hei. 8-7306 in which the ferrule pressing member 107 is inserted into the holding-member fitting recess 103 in the direction in which the springs 106 are compressed, and the retaining portions 107a are engaged in the retained portions 110a, since the insertion is effected while compressing the springs 106, there has been a possibility that the components become disassembled due to the spring force during the assembly, making the assembly difficult. In addition, after the assembly, the spring force of the springs 106 set in the compressed state constantly acts on the ferrule pressing member 107 in the coming-off direction. Hence, there has been a possibility that if the optical connector is used over a long period of time, the engaging portions of the retaining portions 107a and the retained portions 110a become not longer able to withstand the load, resulting in spontaneous disassembly.
Also, the optical connector is provided with a protective boot, as necessary, for preventing damage to a portion of an optical fiber extending from the optical connector due to the bending or the like of such an extending portion depending on the laid condition and the like.
For example, as a structure for attaching a boot in an optical connector of this type, a structure in which the boot is attached by screwing down is known, as disclosed in U.S. Pat. No. 4,744,629. Also, a structure is known in which a retaining protrusion is provided along a peripheral edge portion of the boot, a fitting groove portion is provided in a corresponding connector housing, and the boot is attached by fitting and retaining the retaining protrusion in the fitting groove portion, as disclosed in Japanese Utility Model Unexamined Publication No. Sho. 61-126204.
However, in accordance with the above-described structure for attaching the boot by screwing down, attachment is troublesome, and there is a possibility of the boot from coming off due to the loosening of the screw. Further, in accordance with the attaching structure in which the boot-side retaining protrusion is fitted and retained in the connector housing-side fitting groove, a single thin-walled retaining protrusion is merely fitted in the fitting groove portion, so that there has been a drawback in that this structure is weak against a tensile force.

Optical connector that reduces the number of components used, that facilitates assembly, and that prevents spontaneous disassembly, and structure for attaching a boot to an optical connector


An electronic deadbolt lock arrangement including a lock having a bolt movable between locked and unlocked conditions. The lock includes a manual control and a power drive to operate the lock that are connected by a decouplable transmission enabling the lock to be operated by either the manual control or the power drive. The transmission includes two concentric cylinders that can be locked or unlocked for relative rotational movement, with manual operation of the lock decoupling the power drive. A biased pin engages co-operating apertures in the cylinders to lock the two cylinders to each other. A cam operated by the manual drive acts against the pin to cause the two cylinders to be decoupled.

Traditionally secure locking systems such as deadbolts have been operated and controlled manually. However, the use of electronic systems for the control and operation of locks is becoming increasingly common. The present invention is directed to an arrangement that permits the electronic and manual control of the lock operation to be separated to allow manual operation of the lock independently of the electronic drive system for the lock. The lock of the present invention is useful in situations where an electronic controller is temporarily unavailable, for example where a controller has been lost, misplaced or damaged.


A method of forming a polycrystalline silicon active layer for use in a thin film transistor is provided. The method includes forming a buffer layer over a substrate, forming an amorphous silicon layer over the buffer layer, applying a catalytic metal to a surface of the amorphous silicon layer, crystallizing the amorphous silicon layer having the catalytic metal thereon into a polycrystalline silicon layer, annealing the polycrystalline silicon layer in an N2 gas atmosphere to stabilize the polycrystalline silicon layer, etching a surface of the polycrystalline silicon layer using an etchant, and patterning the polycrystalline silicon layer to form an island-shaped active layer.

1. Field of the Invention
The present invention relates to a method of crystallizing amorphous silicon, and more particularly, to a method of fabricating a polycrystalline silicon thin film transistor (TFT). Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving electrical characteristics of the thin film transistor.
2. Discussion of the Related Art
In a conventional process for forming a polycrystalline silicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a Plasma Chemical Vapor Deposition (PCVD) method or a Low Pressure Chemical Vapor Deposition (LPCVD) method. After the amorphous silicon layer has a thickness of about 500 Å (angstroms), it is re-crystallized into a polycrystalline silicon layer by using a crystallization method. The crystallization method is generally classified into one of an Excimer Laser Crystallization (ELC) method, a Solid Phase Crystallization (SPC) method, a Metal Induced Crystallization (MIC) method, and a Metal Induced Lateral Crystallization (MILC).
In the ELC method, an insulating substrate where an amorphous silicon layer is formed is heated to a temperature of about 250° C. An excimer laser beam is then applied to the amorphous silicon layer to form a polycrystalline silicon layer. In the SPC method, the amorphous silicon layer is heat-treated at a high temperature for a long time to be crystallized into a polycrystalline silicon layer. In the MIC method, a metal layer is deposited on the amorphous silicon layer and the deposited metal is used for crystallization. In the MIC method, a large-sized glass substrate can be used as an insulating substrate. In the MILC method, a metal is first formed on the amorphous silicon layer, and then the amorphous silicon layer is crystallized. Also in the MILC method, an oxide pattern is formed on a predetermined active portion of the amorphous silicon layer. The amorphous silicon layer becomes polycrystalline silicon by a lateral growth of grains.
The Excimer Laser Crystallization (ELC) process has also been used with some advantages in annealing amorphous silicon. The excimer laser allows areas of the amorphous silicon film to be exposed to very high temperatures for very short periods of time. Theoretically, this offers a possibility of annealing the amorphous silicon film at an optimum temperature of less than 400 degrees Celsius without degrading the underlying substrate upon which it is mounted. However, use of this method has been limited by the lack of control over some of the process steps. Typically, an aperture size of the laser is relatively small. Due to the aperture size, power of the laser, and a thickness of the film, multiple laser passes or shots may be required to complete an annealing process. Since it is difficult to precisely control the laser, the multiple shots introduce non-uniformities into the annealing process. Further, the substrates must be annealed serially in a furnace rather than simultaneously in a furnace. As a result, TFTs made by this method are significantly more expensive.
In the SPC method, a buffer layer is formed on a quartz substrate that can stand a temperature higher than 600° C. The buffer layer serves to prevent a contamination from the quartz substrate. Thereafter, an amorphous silicon layer is deposited on the buffer layer and is sufficiently heat-treated in a furnace at a high temperature so as to form a polycrystalline silicon layer. However, because the SPC method is performed at the high temperature for a long period of time, it is difficult to acquire a desired crystalline silicon phase.
In the process of SPC method, because the crystalline grains develop without a continuous directionality, the polycrystalline silicon layer may have an irregular surface. For a thin film transistor, a gate insulating layer covers the polycrystalline silicon layer. Therefore, if the polycrystalline silicon layer has the irregular surface, the gate insulating layer is also irregularly formed, thereby decreasing a breakdown voltage of the thin film transistor. In addition, the sizes of the polycrystalline silicon grains formed by the SPC method are very irregular, thereby deteriorating electrical characteristics of a device adopting the polycrystalline silicon layer. Furthermore, the quartz substrate used for the SPC method is very expensive, thereby increasing the fabrication costs.
Unlike the SPC method that uses an expensive quartz substrate, the MIC method and the MILC method may utilize a relatively inexpensive glass substrate for forming polycrystalline silicon. In the MIC method and the MILC method, however, metal impurities may remain in the polycrystalline silicon network, thereby deteriorating the quality of the polycrystalline silicon layer. To alleviate this residual impurity problem, the conventional art employs the following method, which will be described with reference to FIGS. 1A to 1C and 2A to 2E.
FIGS. 1A to 1C are perspective views illustrating process steps of forming a polycrystalline silicon layer according to the conventional art.
Referring to FIG. 1A, a buffer layer 12 and an amorphous silicon (a-Si:H) layer 4 are sequentially deposited on a substrate 10. The buffer layer 12 is silicon nitride (SiNx) or silicon oxide (SiO2), and prevents alkali substances included in the substrate 10 from spreading into the amorphous silicon layer 4. Thereafter, the amorphous silicon layer 4 is dehydrogenated by a heat-treatment.
Referring to FIG. 1B, a catalytic metal 16 is formed on the surface of the amorphous silicon layer 4. For the catalytic metal 16, Nickel (Ni), Lead (Pb) or Cobalt (Co) is preferably employed. An ion shower method, an ion doping method, a sputtering method or a chemical vapor deposition (CVD) method is employed for the formation of the catalytic metal 16. After forming the catalytic metal, the amorphous silicon layer 4 is heated and then converted into a polycrystalline silicon layer 15 as shown in FIG. 1C.
FIGS. 2A to 2D are cross-sectional views illustrating process steps of forming a thin film transistor having a polycrystalline silicon layer according to the conventional art.
Referring to FIG. 2A, a buffer layer 2 is first formed on the substrate 10. Thereafter, a polycrystalline silicon layer is formed on the buffer layer 2 using the process mentioned with reference to FIGS. 1A to 1C, and then patterned to form an island-shaped active layer 8.
Referring to FIG. 2B, a gate insulation layer 11 and a gate electrode 12 are formed on the active layer 8. The active layer 8 is divided into two areas: a first active area 14 that is an intrinsic silicon area, and second active areas 16 and 17 where impurity ions are to be doped. The gate insulation layer 11 and the gate electrode 12 are disposed to define the first active area 14. The second active areas 16 and 17 of the active layer 8 are positioned on respective sides of the first active area 14. The gate insulation layer 11 is made of silicon nitride (SiNx), silicon oxide (SiO2) or Tetra Ethoxy Silane (TEOS).
After forming the gate insulation layer 11 and the gate electrode 12 on the first active area 14 of the active layer 8, p-type ions, such as boron, are doped into the second active areas 16 and 17. Since the gate electrode 12 is disposed above the first active area 14 and acts as an ion stopper, the dopant p-type ions are not doped into the first active area 14. Thus, the first active area 14 remains as an intrinsic silicon region, whereas the second active areas 16 and 17 become doped silicon regions. Namely, the second active areas 16 and 17 become source and drain regions, respectively. The above-mentioned dopant (p-type ions) includes a group III element, such as boron (B). For example, B2H6 is used for the dopant. After the ion doping is finished, the doped portions 16 and 17 of the island-shaped active layer 8 includes p-type semiconductor source and drain regions.
Referring to FIG. 2C, an interlayer insulator 18 is formed to cover the gate electrode 12, the first active area 14, and the second active areas 16 and 17. A source contact hole 16a and a drain contact hole 17a are formed throughout the interlayer insulator 18, thereby exposing the second active areas 16 and 17, respectively. As mentioned above, the second active areas 16 and 17 are source and drain regions on which source and drain electrodes are formed, respectively.
Referring to FIG. 2D, a source electrode 20 and a drain electrode 22 are formed on the interlayer insulator 18. The source and drain electrodes 20 and 22 electrically contact the source and drain regions 16 and 17, respectively, through the respective source and drain contact holes 16a and 17a. This completes a thin film transistor having p-type polycrystalline source and drain regions.
Thereafter, a passivation layer 26 is formed to cover the source and drain electrodes 20 and 22, and then patterned to form a pixel contact hole 27 that exposes a potion of the drain electrode 22. On the surface of the passivation layer 26, a transparent conductive material is deposited and then patterned to form a pixel electrode 28. Thus, the pixel electrode 28 formed on the passivation layer 26 electrically contacts the drain electrode 22 through the pixel contact hole 27.
In the conventional process of fabricating the polycrystalline silicon TFT, since the catalytic metal is used for the amorphous silicon crystallization, the residue of the catalytic metal can remain in the active layer of the thin film transistor. The residual catalytic metal adversely affects the carrier mobility in the thin film transistor, thereby causing the malfunction of thin film transistor and degradation of electrical properties. Furthermore, the residual catalytic metal in the active layer contributes to increased leakage current in the thin film transistor, and causes the increase of a threshold voltage.

Method of fabricating polysilicon thin film transistor with catalyst


Apparatus and methods are disclosed for adding minimum pulse widths to the coarse resolution output of a multi-reference switching amplifier. This acts to null any detectable resultant differential by addition of a dynamic offset pulse width to the fine resolution output; thus extending operation to zero while presenting the imposed minimum pulse widths as a common-mode (null) signal. A preferred method according to the invention includes the steps of separating the input signal into coarse and fine resolution outputs, adding a minimum pulse width to the coarse resolution output; and adding a dynamic offset pulse width to the fine resolution output so as to null differential signals which would otherwise be present across the load. In terms of circuitry, a data separator is employed for separating the input signal into coarse and fine resolution outputs, and a summer adds the minimum pulse width to the coarse resolution output. Pulse-width modulation converters transform the modified coarse- and fine-resolution outputs prior to presentation to the load through routing logic.

This invention relates generally to electronic amplifiers and, in particular, to apparatus and methods for enhancing the dynamic range of multi-reference switching amplifiers.
Many electronic devices operate on the principle of providing the integral of two or more switched voltage or current levels as an analog output. In order to modulate this analog output, the effective duty cycle of the switched voltages or currents is changed by various means in accordance with an input source. In such devices, predictable monotonic resolution is attainable only at pulse widths above the minimum imposed by the aggregate propagation delays of the physical system. Below this minimum, pulse widths obtained do not correlate linearly to their commanded width.
Multiple-reference switching amplifiers enhance resolution by switching two or more reference voltages to a load. Configurations of this type are described in patent application PCT/US99/26691, entitled xe2x80x98Multi-Reference, High-Accuracy Switching Amplifier,xe2x80x99 the contents of which are incorporated herein by reference.
Although the addition of a second reference voltage improves resolution, it does not directly address resolution near zero output, where propagation delays impact crossover distortion. In many applications, such as audio amplification, dynamic range requirements often make operation below this minimum desirable. Accordingly, a need exists to extend operation of these switching devices to facilitate resolutions significantly lower than their propagation delay.
This invention is directed to apparatus and methods for adding minimum pulse widths to the coarse resolution output of a multi-reference switching amplifier, and nulling any detectable resultant differential by addition of a dynamic offset pulse width to the fine resolution output; thus extending operation to zero while presenting the imposed minimum pulse widths as a common-mode (null) signal. Although the technique is described with reference to the coarse-resolution signal, it is equally applicable to the fine-resolution signal, or both.
A preferred method according to the invention includes the steps of separating the input signal into coarse and fine resolution outputs, adding a minimum pulse width to the coarse resolution output; and adding a dynamic offset pulse width to the fine resolution output so as to null differential signals which would otherwise be present across the load.
In terms of circuitry, a data separator is employed for separating the input signal into coarse and fine resolution outputs, and a summer adds the minimum pulse width to the coarse resolution output. Pulse-width modulation converters transform the modified coarse- and fine-resolution outputs prior to presentation to the load through routing logic.


A BIOS address decoder for addressing an extended BIOS memory for storing additional microprograms in a computer system. A system component is connected from the bus for receiving program instruction addresses in a first address range and providing corresponding BIOS memory addresses in a corresponding first BIOS address range. The BIOS address decoder includes the system component to receive a first subset of bus address bits representing bus addresses in the first instruction address range and responsive to the first subset of bus address bits to generate corresponding BIOS addresses in the first BIOS address range and a BIOS address indication indicating that the first subset of bus address bits indicates a bus address in the first instruction address range. An extended BIOS decoder is connected from the bus to receive a second subset of bus address bits representing bus addresses including an extended instruction address range and from the system component to receive the BIOS address indication output and is responsive to the second subset of bus address bit and the BIOS address indication for generating an extended BIOS memory enable output having a first state when the second subset of bus address bits does not represent a bus address including the extended instruction address range and a second state when the second subset of bus address bits represent a bus address including the extended instruction address range.

Most computer systems, and in particular, computer systems implemented using microprocessors as the central processing unit, such as the Intel 86xxx and Pentium.TM. families of microprocessors or the Motorola 68xxx family of microprocessors, are provided with a plurality of layers of programs for directing operations of the systems. The program layers commonly include a user layer, an operating system layer and a BIOS layer. The user layer is comprised of programs for executing applications programs directly under the control of a system user and for directing the system to perform specific user tasks, such as word processing or spreadsheet operations. The operating system layer contains programs that are responsive to the applications programs and user commands and that direct higher level operations of the system that are not specific to a particular application, such as UNIX.TM., DOS.TM. and Windows.TM.. Finally, the BIOS level contains programs responsive to the operating system level programs for controlling the detailed operations of the system hardware.
The most common of such microprocessor based systems are those that have evolved from the original IBM personal computer family of systems, that is, systems using the Intel 86xxx and Pentium.TM. family of microprocessors and either the Microsoft DOS.TM. or Windows.TM. operating systems or the UNIX.TM. operating system. Originally developed as relatively simple systems for use by a single user to perform single, relatively simple tasks, the development of increasingly more powerful microprocessors and larger and less costly memory has resulted in microprocessor based systems evolving into systems that approach or equal the speed and power of many mainframe and supermini computers. The increasing power and memory of such systems has interacted with the design of programs running on the systems, however, so that the user programs and operating systems have become increasingly larger and more complex, as have the functions performed by the systems, thereby demanding even more powerful processors and more addressable system space, particularly for memory for storing and executing programs.
Although the increases in microprocessor power and speed and the increases in affordable memory have kept pace with the increasing demands imposed by user and system programs, there have been recurring problems in the continuing development of such systems. Many of these problems arise from architectural features that originated in the first systems of this type as reasonable design features and that were carried forward through successive generations of development, to maintain compatibility between successive generations of systems, to now present severe limitations on the further development of the systems.
One of the most significant and persistent of these problems is in memory allocation and management in the microprocessor systems based on the Intel 86xxx and Pentium.TM. family of microprocessors and, more specifically, in the allocation of system address space in these systems. In particular, in the original generations of these systems a maximum system address space on the order of 512-640 kilobytes was allocated as meeting reasonably foreseeable system needs and that space was allocated accordingly, with certain address ranges assigned to processor registers, input/output devices, and so on. The remainder of the system address space was allocated to memory for storing and executing programs as it was foreseen that user and operating system programs would require variable amounts of memory space. The BIOS programs and the memory for storing BIOS programs, however, were assigned a fixed range of address space that appeared, at the time, to be adequate for future requirements.
In later generations of these systems, however, and with increasingly more powerful microprocessors and increasingly larger user programs and correspondingly larger operating system programs taking advantage of the increased power and speed of the microprocessors, there was an increasing demand for an ever larger address space for program memory. This has been met, however, in the case of user and operating system programs by various methods that have taken advantage of the fact that the address space originally assigned to user and operating system programs was variable to provide extended or expanded address spaces for the user and operating system programs.
Recent developments in microprocessor based systems, however, have led to a requirement for additional address space for BIOS programs as the microprocessors and system components controlled by the BIOS programs and the functions to be performed by the BIOS programs have grown more complex and numerous. The address space allocated to BIOS programs, however, was originally fixed as to location and range, rather than variable as in the case of user and operating system programs, and thus does not readily lend itself to the extension and expansion methods used for user and operating system programs. In addition, the need to expand the BIOS address space has appeared long after the need to expand user program and operating system memory space, so that much of the address space that might have been assigned to extend the BIOS address space has already been used for other purposes.
The present invention provides a solution to these and other problems of the prior art.

BIOS memory address decoder for providing an extended BIOS memory address space by reclaiming a portion of non-BIOS address space


An ophthalmologic surgical work station has a microscope and a foot switch corresponding thereto. The microscope is connected to the foot switch via a console. The microscope and the foot switch are coarsely prepositioned and a change of the relative position between the microscope and the foot switch with respect to each other is only possible via a fine positioning.

It is conventional to utilize many highly developed apparatus in surgical procedures in eye surgery. Great care, much experience and a high measure of caution by persons working in the operating room are required in order to achieve a high level of safety. This concerns, inter alia, connecting elements between the individual apparatus such as connecting cables, hoses and the like. It is of importance that in an operating room: for example, none of the persons active there trip over such connecting elements; no insert connection is lost because of an unwanted hand movement or two connecting elements, which do not belong to each other, are coupled to each other. In addition to the danger of an accident in the operating room, there also is the additional danger that a surgical success cannot be obtained for the patient because of such unwanted actions.
The complexity of the apparatus to be used in a surgical procedure on the eye leads to the situation that much time must be expended in order to ensure the high measure of care and caution during an operation. While a cataract operation mostly only requires approximately 15 minutes of surgery time, a similarly long time span must be provided for the preparatory measures and the safety measures. If these accompanying measures would take less time, then more surgical procedures can be carried out in a work shift and a higher productivity can be obtained.


A semiconductor integrated circuit having a plurality of ultrasound pulsers corresponding to a plurality of respective channels, and integrally formed on a small area. The ultrasound pulsers each include a MOSFET gate drive circuit in which an input voltage pulse is converted into a current pulse, and the current pulse is converted again into a voltage pulse on the basis of a high potential side voltage +HV, and a low potential side voltage −HV, applied to a transducer drive circuit, and in which a voltage level shift in the input voltage pulse is attained, and a voltage pulse swing is generated by the MOSFET gate drive circuit on the basis of the high potential side voltage +HV, and the low potential side voltage −HV. The MOSFET gate drive circuit is DC-coupled with the transducer drive circuit.

There has been available a conventional pulser for a medical ultrasound system having a drive circuit for converting a predetermined input pulse into a high-voltage pulse to be thereby sent out, and an output transistor to be driven for switching by the high-voltage pulse, for sending out an output pulse for oscillation to an ultrasonic transducer (refer to, for example, JP-B No. 06 (1994)-53113). Besides, there has been available a driver (refer to, for example, JP-A No. 2005-340624 and JP-A No. 2000-156495) for driving a plasma display panel, or a pulser similarly having a driver circuit disposed in a front stage, and an output transistor connected to a succeeding stage thereof, in a driver (refer to, for example, JP-A No. 11 (1999)-205112) for driving a high-voltage resistant power integrated circuit for household appliance use, automobiles use, industrial use, and so forth.
Further, there has been available a conventional pulser for a medical ultrasound system (refer to, for example, Supertex Inc., HV732 data sheet) comprising a gate drive circuit made up of voltage level translators, and voltage buffers, for receiving logical pulses to thereby drive a gate unit in a succeeding stage, and a transducer drive circuit made up of an output transistor and the gate unit including a clamping circuit, for driving an ultrasonic transducer in a succeeding stage, wherein the gate drive circuit is coupled to the transducer drive circuit via capacitors.

Semiconductor integrated circuit capable of directly coupling low-voltage signals with high-voltage signals


Method and apparatus for vapor phase free methyl radical transport of indium dopant species for precise predetermined reproducible doping concentrations to control electrical properties for MOCVD grown materials.

1. Field of the Invention
The invention relates, in general, to semiconductor fabrication using metalorganic chemical vapor deposition crystal growth, and more particularly to vapor phase transport of the dopant species indium by methyl free radicals, for controlled doping in a reproducible manner.
2. Prior Art
The Manasevit patents 4,368,098 and 4,404,265 describe methods and apparatus for growing thin film single crystal Group III-V wide band-gap compound semiconductors, wherein the thin film may be produced in situ on a heated substrate in an MOCVD reactor by reaction of an organic compound containing a Group III constituent with a Group V hydride.
These patents are assigned to a common assignee of the present application, and techniques disclosed in the patents are used in the present invention.
In the manufacturing of electrically active mercury cadmium telluride single crystal materials by metalorganic chemical vapor deposition (MOCVD), precise control over the carrier concentration in the materials is essential. A common way to control carrier type and concentration is by intentionally doping the material during growth with a dopant species which will provide the correct carrier type at the desired concentration in the crystalline material.
The problem which has existed with present doping schemes in MOCVD growth is a lack of precise control and reproducibility at low dopant concentrations. One of these schemes which exhibits problematic behavior is alkyl-doping. This is where the dopant species is introduced in the form of a presynthesized metalorganic chemical, and is subsequently decomposed in the growth zone of the crystal growth reaction chamber by heat energy which emanates from a localized heat source, as in the Manasevit patents (supra). The dopant flux in this arrangement is controlled by the partial pressure of the metalorganic compound in the gas phase. The partial pressure is established by the concentration of metalorganic compound in the vapor transporting the compound as a diluent gas, hydrogen, through a network of stainless steel tubing which interconnects the chemical source and the reaction chamber. One problem that occurs with this configuration is the intolerable decay of dopant levels due to condensation, and/or adsorption/desorption processes, of the metalorganic chemicals in the transport lines. This is commonly referred to as the "memory effect." It is this memory effect which complicates the issue of fabricating abrupt transitions in electrically active dopant species. This memory effect phenomena may require numerous growth runs, in which the dopant species is not introduced, for the dopant concentration to fall below deleterious levels.

Technique for doping mercury cadmium telluride MOCVD grown crystalline materials using free radical transport of elemental indium and apparatus therefor


A new and distinct variety of nectarine tree. The following features of the tree and its fruit are characterized with the tree budded on ‘Nemaguard’ Rootstock (non-patented), grown on Handford sandy loam soil with Storie Index rating 95, in USDA Hardiness Zone 9, near Modesto, Calif., with standard commercial fruit growing practices, such as pruning, thinning, spraying, irrigation and fertilization. Its novelty consist of the following combination of desirable features:                1. Tree with vigorous, upright growth.        2. Regular and productive bearer of large size fruit.        3. Fruit having a high degree of attractive red skin color.        4. Fruit with a mild, sweet, low acid flavor and excellent eating quality.        5. Fruit with firm, yellow flesh with good handling and shipping quality.

1. Field of the Invention
In the field of plant genetics, we conduct an extensive and continuing plant-breeding program including the organization and asexual reproduction of orchard trees, and of which plums, peaches, nectarines, apricots, cherries, almonds and interspecifics are exemplary. It was against this background of our activities that the present variety of nectarine tree was originated and asexually reproduced by us in our experimental orchard located near Modesto, Stanislaus County, Calif.
2. Prior Varieties
Among the existing varieties of nectarine trees, which are known to us, and mentioned herein, 'Honey Royale' Nectarine (U.S. Plant Pat. No. 12,008), 'Honey Gem' Nectarine (U.S. Plant Pat. No. 21,836), 'Honey Lite' Nectarine (U.S. Plant Pat. No. 18,400) and our non-patented proprietary nectarine seedling selections '228LP484' and '52LD434'.


A method for producing a plurality of optoelectronic semiconductor components in combination is specified. A plurality of radiation-emitting and radiation-detecting semiconductor chips are applied on a carrier substrate. The semiconductor chips are potted with a respective potting compound. The potting compounds are subsequently severed by sawing between adjacent semiconductor chips. A common frame is subsequently applied to the carrier substrate The common frame has a plurality of chambers open toward the top. The frame is arranged in such a way that a respective semiconductor chip is arranged in a respective chamber of the frame. A semiconductor component produced in such a way and the use of the semiconductor component are furthermore specified.

Conventionally, semiconductor components having a radiation-emitting semiconductor chip and a radiation-detecting semiconductor chip are usually not produced in combination. By way of example, although conventionally a plurality of semiconductor chips are applied on a common carrier substrate, the carrier substrate is singulated to form individual semiconductor components before a frame is applied. Respective individual frames are subsequently applied to the singulated components.
On account of this further processing in the singulated state, however, the production costs and also the production time disadvantageously increase.

Method for producing a plurality of optoelectronic semiconductor components in combination, semiconductor component produced in such a way, and use of said semiconductor component


A process for manufacturing a component on which in-service stresses are imposed by in-service loading conditions. The process generally entails fabricating the component such that residual stresses are induced in the component that substantially offset one or more primary stresses which would otherwise limit the maximum service life of the component. The residual stresses are induced by creating compressive stresses in the component that extend sufficiently beneath the working surface of the component during fabrication. In order to appropriately attain the necessary residual stresses, the process of this invention includes developing a model of the component, and then applying the in-service loading conditions to the model to determine the in-service stresses on the component. Thereafter, at least one of the in-service stresses is identified as being critical, i.e., a stress that establishes the maximum service life of the component. Finally, the component is fabricated such that necessary residual stresses are induced in the component in order to offset the identified critical stress.

1. Field of the Invention
The present invention generally relates to methods and process sequences employed in the manufacture of components. More particularly, this invention relates to a manufacturing method which entails selecting optimal processing conditions by which residual stresses are created in a component at sufficient levels to offset service stresses imposed on the component, such that optimal service life is achieved for the component.
2. Description of the Prior Art
A major inefficiency in the manufacturing of hardened, high precision components is the number of processes or steps necessary to finish the component. As an example, the current method of producing the surface of a bearing race involves forming, annealing, rough turning, hardening, several types of grinding and, finally, abrasive-based superfinishing, as illustrated by FIG. 1. An additional setup is required for each process, with occasional inspections being necessary between processes. Therefore, there is a considerable economic motivation to extend one process or machine tool's capability so that other processes in the production sequence can be eliminated, thus reducing setup times and the complexity of the manufacturing schedule, and gaining significant benefits for flexibility and system efficiency.
The difficulty with which the above benefits are achieved is complicated by the service requirements of a component. Components such as bearing races are often subject to severe in-service stresses that may cause premature failure of the component. A major factor determining the service life of a component is surface integrity, which the industry defines as the result of alterations produced in a surface layer during manufacture of the component and which affect the material properties and performance of the component's surface in service. Typically, three factors are considered for surface integrity: surface finish, microstructure and residual stress. The prior art has long given considerable attention to a component's surface finish and physical and material properties in order to meet design requirements such as strength, fatigue and wear, with finish grinding, honing, lapping, polishing, electropolishing and abrasive superfinishing techniques used to readily achieve surface finishes of 16 microinches Ra and less for components that require a polished finish or superfinish. However, because the shape and orientation of the abrasive particles used in finish grinding and other finishing techniques cannot be controlled, material removal by such techniques likewise cannot be controlled in a manner that will predictably and controllably alter certain surface integrity characteristics, such as residual stresses in the surface. Consequently, the prior art has conventionally relied on additional processing steps, such as shot peening, to improve residual stresses in a component.
Research directed specifically to surface integrity has generated more interest of late, particularly with respect to the effect that certain fabrication practices may have on the microstructure and residual stresses of a component. However, improvements in one surface integrity characteristic have generally been achieved at the expense of others. The prior art has been successful in producing machined surfaces characterized by enhanced surface integrity in terms of minimal effects on microstructure and identifying certain machining parameters that affect residual stresses. However, such efforts have been limited to minimum surface finishes of 32 microinches (0.81 micrometer) Ra, which is inadequate for many applications such as bearing races. Furthermore, the prior art has not succeeded in identifying and selecting processing variables that could specifically enhance the service life of a component based on its particular service environment.
Thus, it would be desirable to provide a method for improving the service life of a component through optimizing fabrication parameters based on intended service loads, including improvements in surface integrity and finish of a component. Ideally, such a method would also be achieved while reducing the number of processing steps necessary to finish the component, and thus reduce setup times and processing complexity.


An improved lighted rail system is provided in the present invention. In one embodiment, the lighted rail system includes a rail member having a plurality of spindle-receiving holes formed in a first side, at least one wire routed through the rail member; and a plurality of light elements coupled to the wire. In another embodiment, a rail member utilized in a lighted rail system includes an upper portion of a rail member having a conduit formed therein, a spindle-receiving portion configured to receive a spindle, a spindle stop formed in the rail member separating the conduit from the spindle-receiving portion, and a lighting system disposed in the rail member.

1. Field of the Invention
Embodiments of the present invention generally relate to rail lighting system suitable for use deck rails, fences and the like.
2. Background
Conventional deck and fence lighting systems are typically mounted to the posts that support one or more sections of rails or fences. Many such lighting systems are mounted on top of the post, which is at or near eye level. This elevation of the lighting system undesirably produces uncomfortable glare that reduces the enjoyment of the area.
Therefore, there is a need for an improved lighting system.