According to an aspect, a wireless station uses a low-frequency clock during sleep intervals and a high-frequency clock during awake intervals. Drift between the low-frequency clock and the high-frequency clock are corrected to enable aligning a wake time instant of the wireless receiver with start of beacon transmissions from an access point, and thereby to reduce power wastage. According to another aspect, errors between the clock of an access point and that of a wireless station are corrected. The wireless station computes an error between the clocks, and extrapolates the error for a sleep interval to compute a wake-up time instant. The correction and extrapolation are performed in every awake interval. Again, undesired power consumption in the wireless station is thereby reduced.

Technical Field
Embodiments of the present disclosure relate generally to wireless devices, and more specifically to techniques for correction of clock errors in wireless devices to enable reduction of power consumption.
Related Art
A wireless network generally includes two or more wireless devices (wireless stations) that communicate with each other over a wireless medium. A wireless local area network (WLAN) designed to operate according to IEEE 802.11 standard(s) is an example of a wireless network. One or both of a pair of wireless stations that communicate with each other may be designed to be operable in a low-power (or sleep) mode either periodically or sporadically. As an example, in an infrastructure basic service set (BSS) according to IEEE 802.11, a wireless station and another wireless device termed an access point may communicate with each other.
The wireless station may only periodically (or sporadically) be "fully awake" to receive communication (e.g., beacons) from the AP, being in a low-power/power-down mode otherwise. Typically, the radio portion (containing receive and transmit signal processing chains) is set to the low-power mode, since the radio portion is usually the highest power-consuming portion of a wireless station. Additionally, at least some portions of the rest of the wireless station (e.g., some portions of a processor and some peripherals in the wireless station) may also be set to a low-power mode.
Each of the AP and the wireless station maintains time using corresponding clock circuitry. However, the clocks of the AP and the wireless station may not be perfectly synchronized or aligned with respect to each other, and in general may not keep perfect synchronized time. Due to such clock errors (deviations from synchronization), the power-up instants of the radio portion (and/or any other portion set to low-power mode) of the wireless station may not coincide perfectly with a desired (ideal) wake-up time instant. Instead, the wireless device may wake-up either too early or too late with respect to start of transmission instants of communication (e.g., beacons) from the AP. In either scenario, undesired power consumption occurs in the wireless station.
Several embodiments of the present disclosure are directed to correction of clock errors in a wireless station, and thereby to enable reduction of power consumption in the wireless station.
The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Correction of clock errors in a wireless station to enable reduction of power consumption


A gaming machine has a display and a game controller arranged to control images displayed on the display. The game controller is arranged to play a game wherein random events are caused to be displayed on the display and, if a predefined winning event results, the machine awards a prize. If the predefined result includes a trigger condition which results in an initial series of free games awarded to a player and, during the initial series of free games, another trigger condition arises, a subsequent series of free games, including a bonus feature, is awarded and implemented immediately during the existence of the initial series of free games. The bonus feature applicable to the subsequent series of free games is applied to the remaining games of the initial series of free games as well as to the games of the subsequent series of free games.

This invention relates to a gaming machine. More particularly, the invention relates to a gaming machine and to an improvement to a game played on such a gaming machine.
Players who regularly play gaming machines quickly tire of particular games and therefore it is necessary for manufacturers of these machines to develop innovative game features which add interest to the games. In so doing, it is hoped to keep players amused and therefore willing to continue playing the game as well as to attract new players. Also, with the growth that has occurred in the gaming machine market, there is intense competition between manufacturers to supply various existing and new venues. When selecting a supplier of gaming machines, the operator of a venue will often pay close attention to the popularity of various games with their patrons. Therefore, gaming machine manufacturers are keen to devise games which are popular with the players as a mechanism for improving sales, retaining customers and attracting new customers.
According to the invention, there is provided a gaming machine having a display means and a game control means arranged to control images displayed on the display means, the game control means being arranged to play a game wherein random events are caused to be displayed on the display means and, if a predefined winning event results, the machine awards a prize, the gaming machine being characterised in that if the predefined result includes a trigger condition which results in an initial series of free games awarded to a player and, during the initial series of free games, another trigger condition arises, a subsequent series of free games, including a bonus feature, is awarded and implemented immediately during the existence of the initial series of free games with the bonus feature applicable to said subsequent series of free games being applied to the remaining games of the initial series of free games as well as to the games of the subsequent series of free games.
In a preferred embodiment of the invention, the game includes an initial bonus feature awarded during the initial series of free games. Then, when the subsequent series of free games occurs, the bonus feature of the subsequent series of free games supersedes the initial bonus feature applicable in respect of the remainder of the games of the initial series so that the bonus feature applicable to the subsequent series of free games applies to all the remaining free games.
It will be appreciated that, in the subsequent series of free games, if the trigger condition again arises to trigger a further series of free games, the further series of free games has a further bonus feature associated with it. The further bonus feature may supersede the bonus feature of the remaining games of the subsequent series of free games as well as any remaining games of the initial series of free games.
The awarding of yet further bonus features when additional free games are triggered may occur, optionally, a finite number of times.
Any suitable bonus feature may be applicable. Thus, the bonus feature may include at least one of changes in definitions of symbol functions, for example, to scatters, substitutes, bonus symbols, feature triggers, etc, paytable variations or an increase in the number of free games awarded.
Preferably, the bonus feature for the initial series of free games is a paytable where all wins are doubled in comparison with the paytable applicable to a base game, the bonus feature for the subsequent series of free games is a paytable where all wins are trebled, the bonus feature for the further series of free games is a paytable where all wins are multiplied by five and the bonus feature for a fourth series is a paytable where wins are multiplied by ten. Any series of free games after the fourth series of free games has the bonus feature of the fourth series of free games applied to them. In other words, no further bonuses are awarded.
The invention may be applicable in respect of any types of base games played on a gaming machine. Thus, although the invention would be particularly applicable in respect of spinning reel-type base games, it could apply also in respect of card games, ball games such as Keno, or the like.
The trigger condition which triggers the subsequent and any further series of free games is the same as the trigger condition which triggered the initial series of free games. For example the trigger condition may be the appearance of three scatter symbols anywhere on the display means.


An apparatus comprising: a processing unit configured to execute a plurality of threads; a profiling unit configured to: profile the operation of the processing unit over a time period to generate an activity profile indicating when each of the plurality of threads is executed by the processing unit over the time period; analyse the generated activity profile to determine whether a signature of the processing unit's thread execution for the time period matches a signature indicating a baseline of thread execution for the processing unit; output an alert signal if the signature of the processing unit's thread execution for the time period does not match the signature indicating a baseline of thread execution for the processing unit.

Computing devices typically include one or more processing units that execute program instructions to perform tasks specified by those instructions. Processing units could be, for example, central processing units (CPUs) or graphics processing units (GPUs).
A processing unit may support multithreading, which is the ability of the processing unit to execute multiple threads of instructions. To do this, the processing unit may schedule threads of instructions for execution so that a single thread is being executed by the processing unit at any given time. A thread can be 'swapped out'—meaning execution of that thread stops—and another thread 'swapped in'—meaning execution of that thread begins. Over a given period of time, a thread may be swapped in and out one or more times. In other words, the processing unit may perform multithreading by interleaving execution of different threads over time.
It may be desirable to obtain information on the performance of the processing unit as it executes the threads of instructions. This might be for the purpose monitoring the performance level of the processing unit and/or as part of threat and security management.

Performance profiling for a multithreaded processor


A heater containing viscous fluid, which is sheared to generate heat. The heater is provided with an electromagnetic solenoid that includes a case, a solenoid coil housed in the case, and a core extending through the case. The heater further has a heating chamber and a sub-oil chamber. Viscous fluid is moved between the heating chamber and the sub-oil chamber through a communication bore. The core extends toward the communication bore. A coil spring urges the core toward the communication bore. Excitation of the electromagnetic solenoid moves the core away from the communication bore. The core opens and closes the communication bore and pumps the viscous fluid into the communication bore when the solenoid is cycled on and off. As a result, the heat output is accelerated.

The present invention relates generally to a viscous fluid heater that generates heat by rotating a rotor in a heating chamber containing viscous fluid. More particularly, the present invention pertains to a viscous fluid heater capable of controlling heating performance.
An automotive vehicle is generally provided with a hot-water type heater. In a vehicle having such a heater, coolant is used to cool the engine. The coolant is heated by engine heat. The heater typically has a heater core housed in a duct. The heated coolant is sent to the heater core. This heats the air sent to the passenger compartment and warms the passenger compartment.
In a diesel engine vehicle or a lean burn engine vehicle, the amount of heat produced by the engine is relatively small. Thus, the amount of heat transmitted to the coolant is small. It is difficult for the coolant to reach a certain temperature such as 80.degree. C. when the amount of heat sent to the heater core is small. Therefore, the heat used to warm the passenger compartment may be insufficient.
To solve this problem, a viscous fluid heater arranged in an engine coolant circulating circuit has been proposed. The viscous fluid heater is used for heating the coolant and includes a housing, which houses a heating chamber and a water jacket (heat exchange chamber). The heater also has a drive shaft and a rotor that are driven by the engine. Viscous fluid (such as high viscosity silicone oil) is contained in the heating chamber and is sheared by the rotor. This causes fluid friction and generates heat. The heat raises the temperature of the fluid (engine coolant) circulating through the water jacket.
The temperature of the viscous fluid contained in the heating chamber increases as the engine speed increases, regardless of the temperature of the circulating fluid flowing through the circulating circuit. When the high viscosity silicone oil is heated to a temperature of, for example, 250.degree. C. or higher, the silicone oil becomes vulnerable to thermal deterioration caused by the heat and mechanical deterioration caused by the shearing. Such deterioration decreases the heating efficiency during the shearing. As a result, the heating performance of the heater, which is used to warm the passenger compartment, is degraded.
To prevent deterioration of the silicone oil, a heater that varies its heating performance has been proposed. U.S. Pat. No. 4,974,778 describes such a heater. When the passenger compartment is sufficiently warm, the heating performance is lowered to stop unnecessary shearing of the silicone oil with the rotor.
The heating performance is varied by moving the silicone oil between a heating chamber and a reservoir chamber to adjust the amount of silicone oil in the heating chamber. However, the high viscosity of the silicone oil slows the movement of the silicone oil from the reservoir chamber to the heating chamber, especially when adjusting the heating performance under lower temperatures. Such slow movement of the silicone oil interferes with the smooth charging of the silicone oil into the heating chamber. This degrades the responsiveness of the heater when varying the heating performance.

Kabushiki Kaisha Toyoda Jidoshokki Seisakusho


Apparatus for testing an electrical circuit having: a base for receiving a printed circuit board carrying the electrical circuit, wherein the base section includes a plurality of test pins for contacting a corresponding plurality of solder pads formed on a surface of the circuit board; a cover section comprising a test head facing an opposite surface of the printed circuit for shorting together a plurality of contacts of a component of the electrical circuit connected to the plurality of solder pads and mounted on the opposite surface of the circuit board; means for applying a stimulus signals to at least one test pin; and means for detecting a signal at a second test pin.

In a typical automated high volume manufacturing facility for fabricating electronic products, such as computer visual displays or television receivers, the operation of each electronic circuit in the product is automatically tested by a functional tester. The functional tester typically comprises a test fixture for receiving a printed circuit board carrying components of the electronic circuit to be tested. Generally, a test fixture includes a base and a cover pivotably mounted on the base. The printed circuit board to be tested is placed on the base and the cover is then closed over the base for safety. An array of test pins is provided in the base. The pins are positioned to engage solder pads on the printed circuit board received in the fixture. Test instrumentation is connected to the pins to test the function, or at least to ensure continuity of connection of electronic components soldered to the pads. The instrumentation identifies a failure condition if, for example, the solder joint at the pad is defective, or if the component soldered to the pad has failed.
Some electrical components, such as connectors, have electrical contacts on both sides of the printed circuit board. To facilitate testing such components, it is usual to supply test pins on both the base and the cover of the fixture so that both sides of the component can be probed. The accuracy of insertion of such components into the circuit board is critical to the effectiveness of the test pins on the cover part of the fixture. This is especially true in the case of so-called "header" connectors, i.e., a male part of a multi-pin connector. Headers typically comprise an array of upstanding pins engaging a multiple contact socket. Ideally, the header is soldered to the circuit board, in a pin-in-hole arrangement (rather than, for instance, surface mount), keeping the pins perpendicular to the board. However, it is not unusual for the header to be soldered in place to the pins at a slight angle from the perpendicular direction. Although this does not affect the general function of the header, it does affect the functional testing, because the test pins positioned to probe the header pins from above miss their targets. The test instrumentation may thus erroneously indicate a failing condition. Furthermore, the test pins mounted in the cover of the fixture may be bent or otherwise damaged during use, leading to reduced reliability. The populated printed circuit board is placed on a "bed of nails" tester for functional testing. In the bed of nail tester, test pins are selectively brought up from the test bed to engage with pads on the printed circuit board.

Apparatus and method for testing a circuit board

International Business Machines Corporation


An M-sequence signal is generated in an M-sequence generation circuit, and the M-sequence signal, which is successively delayed by a column-electrode driving circuit or a row-electrode driving circuit, is applied to a column-electrode group or a row-electrode group. A correlator finds a correlation between the M-sequence signal and a detection signal that has been detected by amplifying electrostatically induced voltage that appeared in the detection electrode of an electronic pen so that a position specified by the electronic pen is detected by a detection circuit as a coordinate signal. Thus, it is possible to obtain a coordinate detection signal having a superior S/N ratio without reducing the coordinate detection speed, and consequently to carry out a coordinate detecting operation with high precision.

Tablets in which graphic and character recognition and command execution can be carried out by instructions that are given with a pen, finger or other means have been known in the art as one type of input devices that carry out predetermined input operations to computers, word processors, and other apparatuses. Moreover, Japanese Laid-Open Patent Publication No. 53726/1993 (Tokukaihei 5-53726) and Japanese Laid-Open Patent Publication No. 314166/1994 (Tokukaihei 6-314166) disclose display-integrated type tablet devices which achieve inexpensive constructions by commonly using electrode constructions and driving circuits in liquid crystal panels and other components, which are regarded as further advanced tablets.
It is required for such coordinate input devices to carry out coordinate detection with high precision at high speeds. In recent years, pixels in the display device become smaller and smaller, and such fine display has further increased the demands for high precision of the coordinate detection.
However, high speed and high precision of the coordinate input device form two effects that are inconsistent with each other; therefore, the problem with the prior art coordinate input device is that the coordinate detecting precision can not be improved with high-speed coordinate detection maintained as it is. In other words, high-speed coordinate detection needs to widen the frequency band width, resulting in degradation in the precision.
Among these coordinate input devices, especially in the display-integrated type devices, the coordinate detecting precision further deteriorate for the following reasons: For example, the arrangement of the above-mentioned Japanese Laid-Open Patent Publication No. 53726/1993 (Tokukaihei 5-53726) is designed to provide the display and coordinate detection functions by carrying out the image display and coordinate detection in a time-sharing manner. In this case, the coordinate detection period is set as short as possible in order for the coordinate detection operation not to give adverse effects on the display. Further, the applied voltage used for detection in not increased so much since it is limited by the resistance to voltage of the display driver. Moreover, in the case of duty-type liquid crystal, since this system utilizes the electrostatic coupling that is exerted between the tip electrode of an electronic pen and the transparent electrode group on one side through the gap of the electrode group on the other side, only a minute detection voltage is obtained. Consequently, the above-mentioned display-integrated type tablet devices only provide a coordinate detection signal with an inferior S/N ratio.
Moreover, the above-mentioned Japanese Laid-Open Patent Publication No. 314166/1994 (Tokukaihei 6-314166) shows an arrangement wherein a tablet function is added to a TFT (Thin Film Transistor) liquid crystal panel using the addressing system. In order to improve display quality, a present trend in TFT liquid crystal panels is to improve the aperture ratio by narrowing the widths of gate electrodes and source electrodes so as to widen the areas of pixel electrodes. In this case also, since the coordinate detection signal is detected in proportion to the coupling capacitance between the tip electrode of an electronic pen and the gate electrodes or the source electrodes, the coupling capacitance decreases with the improvement of the aperture ratio, thereby resulting in degradation in the S/N ratio of the detection signal. Here, in the TFT liquid crystal panels also, it is needless to say that the coordinate detection period should be maintained as short as possible so as not to give adverse effects on the display.
Furthermore, in the prior art coordinate input devices, it is essential to provide a connecting line for the electronic pen so as to supply power to the electronic pen and to output the coordinate detection signal. Here, this connecting line is a disturbing object for the user to operate the electronic pen, causing degradation in the operability.
Additionally, another tablet using the pressure-sensitive system, which has two superimposed sheets of transparent electrodes with an insulating spacer inserted therebetween and which gives specified coordinates by using a current that flows between the detection electrodes when pressed by a pen point or a finger, has been proposed. However, the problems with this system are that merely an inferior visibility is obtained due to the transmittance and reflection of the transparent electrodes and that a finger and a pen cannot be used at the same time.
Further, U.S. Pat. No. 4,639,720 has proposed an arrangement wherein a pen-input function is achieved by intersecting transparent electrodes in liquid crystal so as to measure the electrostatic coupling capacitance between them, a pen point or a finger. However, this arrangement has a deficiency in that a complicated structure and driving method are required since the liquid crystal electrodes have to be designed to intersect each other on the same plane.


A differential gradiometer comprising a substrate with at least a pair of resonators disposed thereon, wherein each of the at least a pair of resonators is sensitive to environmental factors which produces differential strains between the resonators, a first one of said pair of resonators being connected with a circuit for forming a first oscillator, the second one of said pair of resonators being connected with another circuit for forming a non-linear oscillator, an output of the first oscillator being applied to the non-linear oscillator for generating a comb of frequencies, wherein an addition oscillator is locked to the nth tooth of the comb thereby increasing the sensitivity of the gradiometer by a factor of n.

Resonant mode sensors/gradiometers operate by detecting a relative frequency shift between a pair of resonators. For mechanical sensors, this relative frequency shift is usually produced by a change in the differential strain on the resonators from an external influence. Typically, this relative frequency is detected by either an analog or digital phase lock loop (PLL). The sensitivity is determined by the size of the frequency shift compared to the stability of resonators/oscillators. The stability is affected by temperature drifts at low frequency and electronic noise in the sustaining circuits at higher frequencies. If the magnitude of the frequency shift can be amplified in some manner, the signal-to-noise ratio (SNR) of the sensor/gradiometer can be enhanced. This disclosure presents a method for enhancing the frequency shifts to enhance the SNR by using phononic frequency combs.
Magnetostrictively-driven piezoelectric resonators offer the possibility of sensing magnetic RF fields with high sensitivity with extreme sub-wavelength (<<λ) structures and at room temperature. See T. Nan, et. al., "Acoustically Actuated Ultra-Compact NEMS Magnetoelectric Antenna," Nature Communications, 8:296, DOI: 10.1038/s41467-017-00343-8 (2017) and J. Zhai, et. al., "Detection of Pico-Tesla Magnetic Fields using Magneto-Electric Sensors at Room Temperature," Applied Physics Letters, 88, 062510 (2006), the disclosures of which is hereby incorporated herein by reference.
The sensitivity can be enhanced by the high mechanical gain (Q) of the resonator, thereby amplifying the piezoelectric voltage produced by the resonator. In addition, the magnetic layer can introduce a modulated strain in the piezoelectric resonator which can shift the oscillator frequency if the resonator is used with a feedback sustaining circuit. This frequency or phase shift can then be used as a measurement of the amplitude of the incident magnetic field. Both sensor designs can be implemented in a wafer-level (yielding ultra-thin antennas) process with high-Q quartz resonators using the HRL QMEMS process. See the related patent applications identified above.
Currently, there is a desire for these devices to achieve noise floors similar to quantum-based SQUID devices (˜1 fT √Hz in a shielded environment) which require cryogenic cooling to 4.2K (See J. Vrba, SQUID Sensors: Fundamentals, Fabrication and Applications, edited by H. Weinstock Kluwer Academic, Dordrecht, The Netherlands, 1996 p. 117) or SERF (spin exchange relaxation-free) atomic magnetometers (see Kominis, I. K., Kornack, T. W., Allred, J. C. & Romalis, M. V. "A subfemtotesla multichannel atomic magnetometer," Nature 422, 596-599 (2003)). However, even by incorporating high-Q resonators with high permeability (μr>1000) magnetic films, the predicted sensitivities for many SoA magnetostrictively-driven resonators is only near 100 fT/√Hz to 1 pT/√Hz.
In order to achieve SQUID-like performance with small MEMS-based resonators, an additional gain in sensitivity of roughly two order of magnitude is needed. We recently disclosed a method of increasing the sensitivity for small MEMS resonators using flux concentrators. See U.S. Provisional Patent Application Ser. No. 62/826,757 filed 29 Mar. 2019 referenced above.
However, for certain magnetostrictive layers, increasing the magnetic flux can interfere with the built-in magnetic bias when exposed to the earth's magnetic field. When used with a phase detection method, the ability to increase the phase shift for a given magnetic field while not interfering with the optimized built-in bias point is desirable.
In this disclosure we present a method for increasing the magnetic sensitivity using nonlinear effects to amplify the phase separation between two oscillators incorporating magnetostrictively-coated resonators without the need to amplify the local magnetic field at the sensor. This technique provides for enhanced sensitivity and measurement accuracy in ambient earth environments. The technique can also be applied to other gradient sensors (gradiometers) which use relative frequency shifts as the measure of the gradient amplitude of a physical parameter. Examples, are pressure or gravity gradiometers. The disclosed technique of generating a comb using a pair of resonators to enhance detection of physical parameters may well have a wide application for differential field measurements.
As mentioned above, this disclosure addresses a method to produce MEMS-based gradiometers with high sensitivity. U.S. Provisional Patent Application Ser. No. 62/881,063 filed 31 Jul. 2019 and entitled "Magnetostrictive MEMS Magnetic Gradiometer" and its corresponding U.S. Non-Provisional patent application Ser. No. 16/932,427 filed on the same date as this application and also entitled "Magnetostrictive MEMS Magnetic Gradiometer" teaches a MEMS based magnetic gradiometer using magnetostrictive material on its MEMS resonators. This disclosure relates to an improvement over that disclosed by the just mentioned U.S. Patent Application in that a new method and apparatus is proposed to increase the sensitivity of the differential magnetic field measurement. In order to obtain SoA RF magnetic sensitivity with small and low power sensors, current MEMS-based magnetostrictive magnetic field sensor need to improve their sensitivities by several orders of magnitude. There are various approaches to obtain that improvement. For on-resonant antennas that produce a voltage out for a given input magnetic field, several antennas can be arrayed in series to increase the voltage output. Alternatively, built-in vertical magnetic moments are predicted to strongly increase the coupling to shear-mode resonators. However, when used to detect a frequency shift for wide bandwidth applications, other methods are required. One could increase the stress applied to the resonator for a given magnetic field using alternate resonator designs or one can increase the local magnetic field that the resonator sees. However, if the optimal bias point for a magnetostrictive layer is below about 100 Oe, then increasing the local earth's magnetic field (about 0.5 Oe) by a factor of 100× can result in modifying the pre-set bias conditions and thus reducing the AC sensitivity.


A method of reserving bandwidth in a network includes the steps of receiving a reservation request for a bandwidth for a hose having one ingress point and at least one egress point, and reserving the requested bandwidth for each link in the hose and assigning a reservation identifier to the hose.

Metropolitan area networks are currently the focus of intense network development and competition for market share for network equipment developers. The developers are seeking the right mix of technology, quality of service (QoS) features, and traffic engineering methodologies that would provide the differentiating factors that propel them ahead of the competition. In general, traffic engineering or management are methodologies that allow network service providers to take advantage of over-subscription of network resources to reduce network cost, efficient bandwidth utilization, and QoS guarantees.


A lighting module comprising a base panel and a plurality of light-emitting diode (LED) chips attached directly to the base panel. The LED chips are in electrical communication with conductive traces on the base panel, which deliver a current to the LED chips. Various embodiments of this generally described lighting module are also presented. Additionally, methods of preparing such a lighting module, and system components of the lighting module are presented.

1. Field of the Invention
The present invention is directed to lighting modules. More specifically, the present invention is directed to lighting modules comprising light-emitting diode chips.
2. Background
A light-emitting diode (LED) is a semiconductor device that emits light when excited by electrical energy. In general, an LED comprises an LED chip disposed within a package. The LED chip is a semiconducting material (or combination of materials) impregnated, or doped, with impurities to create a p-n junction. When electrical current is passed through the LED chip in a forward-bias, electrons "jump" across the p-n junction and emit light. The package is usually a plastic or ceramic material having electrical connections to couple the LED chip to a current source. The main disadvantage of an LED package is that the thermal resistance of the package can be quite large (i.e., greater than 100° C./W), which degrades the life and performance of the LED chip. The terms "light-emitting diode chip," "LED chip," "chip," or "LED die" are used to refer to the semiconducting p-n junction, and thereby differentiate from the term LED, which generally includes both a chip and its packaging.
LEDs are more efficient light sources than incandescent light sources. However, one challenge with using LEDs as light sources for general lighting applications is in obtaining sufficient light out of an individual LED chip. In other words, an individual LED chip does not provide enough light as compared to other light sources such as, for example, tungsten filaments. However, when several LEDs are combined into an array of LEDs, the combination and cumulative effect of all the LED chips in the array produce a light source with sufficient light.
LEDs are seeing increased use in lighting applications. Early uses of LEDs in lighting fixtures have tended to employ high-power LEDs (typically, 1W chips) grouped together in what is generally referred to as a lighting module. One or more lighting modules may then be employed in a lighting fixture. In order to create a uniform light source, the LEDs must be placed close enough to "blend" light through a diffuser. Additionally, there is an increased demand to minimize the thickness of light fixtures, requiring the LEDs to be placed even closer together. As the LEDs are moved closer together, there is an increased need for exotic thermal management solutions (e.g., fans, cooling fins, heat pipes, etc.).
In addition to heating issues, lighting modules using LEDs must be designed to address optical issues such as color uniformity and binning. For example, depending on the semiconducting material used, LED chips can deliver light of different colors. In order to produce white light, two techniques are generally employed. In one technique, three LED chips (one red, one blue, and one green) are bundled together such that the cumulative output results in a white light source. The second technique employs a UV/blue LED chip coated or packaged with a phosphor. The LED chip emits light of a specific wavelength (in the UV or blue region). The emitted light excites the phosphor, which results in the emission of white light. However, when LED chips are manufactured, a single semiconducting wafer can produce LED chips of varying wavelengths. LED chip manufacturers must then employ an expensive binning procedure to organize (or bin) the LED chips by wavelength. In order to ensure uniformity, a manufacturer of LED lighting modules would require LED chips from a small range of bins. Such a limitation adds to the production costs of the lighting module.


A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence. The look-ahead contacts allow for overlapping or substantially simultaneously stressing and/or testing dies of dies of a die set currently under probe and dies of a second die set located prior to or after the current probe head position (i.e., not under probe).

After a semiconductor wafer has been fabricated, a number of the dies on the wafer are inoperable. Manufacturers of semiconductor devices typically test the individual dies for functionality prior to singulation into individual dies, to evaluate various electrical parameters of the integrated circuit components contained on each die, and verify that certain standards are met. Integrated circuits (IC) devices typically undergo three separate test cycles: (1) in-process testing and monitoring of sheet resistivities, junction depths, and device parameters such as current gain and voltage breakdown; (2) wafer-probe testing of electrical parameters prior to die separation; and (3) final testing of reliability and performance after die packaging is completed. Testing of ICs is expensive and time consuming, and it is desirable to keep testing costs low since these add directly to the cost of producing the parts.
Semiconductor wafers are typically subjected to test probing tested prior to singulation into individuals dies using a wafer-level test system. As illustrated in FIG. 1, a typical test system 10 includes a wafer handler 12 for handling and positioning the wafers 14, a test circuit 16 for generating test signals, a probe card (probe head) 18, and a probe interface board 20 for routing signals from the test circuit electronics to the probe card 18. The wafer probe card 18 typically includes multiple probe elements 22, typically in the form of probe pins or needles, for making temporary electrical connections with contacts on the dies disposed on the wafer 14, the contacts typically in the form of bond pads, fuse pads or test pads arranged in a dense area array. The wafer handler 12 typically includes a wafer chuck 24 configured to move in X and Y directions (i.e., horizontally backward-forward and side-to-side) to align the wafer 14 with the probe card 18, and in the Z direction (vertically up-down) to move the wafer into contact with the probe pins 22. Exemplary prior art test systems are described, for example, in U.S. Pat. Nos. 6,300,786 (Doherty, et al.) and U.S. Pat. No. 6,246,245 (Akram et al.), both assigned to Micron Technology, Inc.), the disclosures of which are incorporated herein.
An example of a prior art semiconductor wafer 14 is illustrated in FIGS. 2–3. The wafer 14 includes multiple semiconductor chips or dies 26 fabricated using processes that are well known in the art. The dies 26 are typically singulated by use of a wafer saw, which grinds the wafer 14 along wafer scribe lines 28, usually referred to "streets" or "avenues", that separate the dies 26 from each other. As shown in FIG. 3, each die 26 includes multiple die pads 30. The die pads 30 are in electrical communication with integrated circuits contained on the die 26. For illustrative purposes, each die 26 includes eight die pads 30, which is merely exemplary. The die pads 30 are illustrated as bond pads, but can also be dedicated test pads or fuse pads, disposed on the dies 26 or on other portions of the wafer 14.
Conventionally, each die on a wafer is tested by placing the probe elements 22 of a probe card connected to a test system on the pads 30 of the die. The test system supplies the proper power levels and signals to the pads on the die.
An example of a prior art probe card 18 is illustrated in FIG. 4, and typically comprises an insulating substrate 21, such as a glass filled resin, that includes electric traces (not shown) in electrical communication with the contacts or probe pins 22. The probe pins 22 on the probe card 18 are arranged in patterns corresponding to the patterns of the die pads 30. The probe pins 22 can be configured to make electrical connections with the die pads 30 on a specific die 26 or, as in the illustration in FIG. 4, with a group of dies (i.e., four dies) on the wafer. The probe pins 22 on the probe card 18 are arranged in groups 32a–d and configured on the substrate to correspond to the pattern of the die pads 30 on the die 26 to be contacted. Each group 32a–d of probe pins 22 represents a single test site. Typically, two or more test sites are included on the probe card 18 to accommodate testing of multiple dies at the same time. The probe card 18 can be formed with any desired number of test sites. The probe card 18 can also be configured to test a complete semiconductor wafer 14, or a portion of the dies 26 in a partial wafer. In the illustrated example in FIG. 4, the probe card 18 includes four test sites such that four dies 26 on the wafer 14 can be tested simultaneously. During a test procedure using a probe card, stepping techniques can be used to step the wafer 14 or the probe card 18, and test a number of dies 26 within a section on the wafer until all the dies 26 on the wafer have been tested. In those cases where dies 26 are positioned along the peripheral edge of a round wafer 14 (not shown), some of the probe pin groups 32a–d may not have an associated die under test, and the software that controls the stepping process is typically programmed to register valid test sites.
Manufacturers of semiconductor memory devices typically perform several operations on each device to examine various electrical parameters of the device and verify that certain minimum standards are met. A full range of functionality and timing characteristics of the memory devices are tested in order to determine if there is a defect in the array of cells that may fail over time. The test system 16 can transmit specific combinations of voltages and currents and/or signals to the probe interface board 20 and through the probe pins 22 of the probe card 18 to dies 26 under probe on the semiconductor wafer.
Burn-in stressing of dies is typically performed to accelerate failure using elevated voltage and temperature levels to stress, and determine operable voltages, currents, and temperatures. The test system can also run diagnostic tests on the memory device(s), which includes furnishing a sequence of commands (e.g., address, data and control signals) to the memory device for storing first data in memory cells of the memory device. The memory device can perform operations in response to the commands, and the operations synchronized to a clock signal. After the sequence, second data can be read from the memory cells and the first and second data can be compared to detect memory speed, timing, failures, and so forth. The integrated circuits that do not meet specification can be marked or mapped in software. Following testing, defective circuits can be repaired by actuating fuses (or anti-fuses) to inactivate the defective circuitry and substitute redundant circuitry.
In addition to the use of an external test system, memory testing can also be performed by means of a built-in self-test (BIST) circuit, which incorporates test circuitry and test data into the die 26 itself. In a BIST operation, the die is run in a way similar to how it is ultimately meant to be run. Activating BIST circuitry requires a Vcc power source, GND ground potential, and can also require signals from a test system. On a wafer level, the BIST circuitry can be disposed in the scribe lines ("streets") 28 between dies 26 or in the unused edge portions along the periphery 34 of the wafer 14, or can be included within the dies 26 themselves.
Because each memory cell or bit of the memory device must be tested, the time and equipment necessary for testing memory devices represents a significant portion of the overall manufacturing cost of such devices. The more chips that can be tested simultaneously, the greater the savings in testing time and manufacturing cost per chip. Still more time could be saved if different testing protocols could be performed on a plurality of memory devices simultaneously.

Probe look ahead: testing parts not currently under a probehead


The present invention entails a removable modular security enclosure for the internal cargo area of prisoner transport vans where each compartment within the security enclosure is defined by an interconnection of four walls and a roof panel. Any of the components defining the enclosure may be comprised of multiple interconnected sections. Sections and components of the enclosure are interconnected by such means as fasteners or interlocking devices. The walls of the enclosure are connected to the floor of the van where said floor serves as the floor of the enclosure. Access to a compartment is provided by a securable port in one of the defining walls. Benches may be provided along the walls inside the enclosure. When the security enclosure is composed of two separate compartments, a common wall may be used where the two compartments are in contact. Any compartment may also be provided with an adjustable vertical partition for dividing the compartment into two smaller subcompartments. A locking device between the partition and another component of the compartment serves to fix the position of the partition. A partition or any of the components defining a compartment may be constructed to allow at least partial translucency into or between compartments.

Transportation of prisoners naturally evokes concerns of security in the means of transportation used for the purpose. One means of prisoner transport is by road-going vehicles. Such vehicles are available on the market, specifically designed and built with the necessary security infrastructure for the purpose of transporting prisoners. However, these specialty vehicles are often very expensive.
An alternate and commonly used option is to modify the internal cargo area of a conventional passenger van with a security enclosure. However, the components of said security enclosure are often welded together and/or welded to the structure of the van itself, thus forming a permanent fixture. If the modified van is involved in an accident or reaches the limit of its useful service life, the replacement van cannot use the old security enclosure, but must be modified with an entirely new and different security enclosure at an additional cost.
It is advantageous to have a security enclosure for prisoner transport vans that is not permanently attached to the structure of the van and that is also designed to facilitate ease of assembly and disassembly within the confines of the cargo area of the van. In the event of an accident or retirement of a vehicle, the security enclosure can simply be disassembled and moved to a new vehicle. Further advantage is gained if different makes and models of vans may be equipped with the security enclosure with only minimal modifications to the components. This advantage may be facilitated by the use of sectional construction of components, whereby only a section of component may need to be modified instead of the entire component.

Removable modular security enclosure for prisoner transport vehicles


A bit error rate test on a transceiver is accelerated by adding a phase offset to data phase encoding and decoding in the transceiver and by mapping bit error rate test results from an elevated error rate condition to a normal error rate condition for the transceiver. The elevated error rate is accomplished by adjusting the phase of the phase encoder and decoder with the value of the phase offset so that the encoded data transmission signal is not as robust against noise as it normally would be. Noise in the form of an interference signal is introduced during the transmission, and the bit error rate is measured after the receiver has decoded the signal. The bit error rate (BER) data with an elevated propensity for error is mapped against bit error rate data for normal operations. A mapping function is built to map BERE (bit error rate elevated) data—data from the elevated error rate condition for data encoding, to BERN (normal bit error rate) data—data from the normal error rate condition for data encoding. The BERE data is mapped to BERN data using the mapping function so that the BER performance of the transceiver may be measured using far fewer test sequences of digital bits.

In wireless short-range high-data-rate communication, ultra-wideband communications has emerged as the standard of choice. Further, orthogonal frequency division multiplex mode (OFDM) has been applied to the frequency range to divide it into multiple bands. Hence, this ultra wide-band technique has been given the name multiband OFDM or MB-OFDM.
When production tests are performed on ultra-wideband (UWB) tranceivers, the test specification includes bit error rate (BER), sensitivity, "in-band" interference and synchronization. Among these tests for UWB transceivers, the BER test and its tolerance to "in-band"/adjacent channel interference is a critical specification to be met during manufacturing test. In effect, this test is a measure of the quality of the data transmission performance of the transceiver.
Manufacturing test cost of transceivers has become a significant portion of the total manufacturing cost for present-day wireless products. The test cost may amount to as much as 40% of the overall production cost. This is due to the cost of sophisticated test equipment required and the extended length of time needed to perform a BER test on a transceiver. Accordingly, there is a need for a test technique that reduces test time, and there is a need for a less complex and thus less expensive test system.

Measuring bit error rate of radio frequency transceivers


A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.

Embodiments relate to a semiconductor device in which a gettering layer is formed in a semiconductor substrate and a method for forming the same, and more particularly to a technology for improving reliability of the semiconductor substrate including the gettering layer.
In recent times, semiconductor devices have been rapidly developed to implement higher speed, higher integration, and lower production costs. In order to implement higher integration and lower production costs of semiconductor devices, a technology for increasing the integration degree of semiconductor devices through Multi Chip Package (MCP) or System In Package (SIP) in a packaging process of the semiconductor devices, has been widely used in various technical fields. For example, MCP or SIP semiconductor devices, in which multiple semiconductor chips are stacked through at least 9 stages, have been mass produced.
However, there is a need to develop a technology for integrating 10 to 20 semiconductor chips. For such multi-layered packaging, a thickness of a semiconductor substrate including a semiconductor device should be greatly reduced. Also, there is a demand of developing light-weight and high-integration semiconductor devices for mobile communication. MCP or SIP-shaped semiconductor devices are also called on to meet such demands. To fabricate MCP or SIP-shaped semiconductor devices, there is a need to fabricate a semiconductor chip having a thinner thickness. In early 2000's, a semiconductor device was been fabricated to have a thickness of 200˜150 μm. In recent semiconductor fabrication processes, a thickness of the recent semiconductor device is gradually reduced to about 60 μm, and it is expected that a thickness of the semiconductor device will be reduced to 60 μm or less in future.
However, a thinner substrate may encounter unexpected issues. The thinner substrate includes a gettering zone configured to capture a pollution source (e.g., metal ion) generated in a semiconductor fabrication process. Assuming that a substrate of the semiconductor device is fabricated to a thickness as thin as about 50 μm or less, there is little or no space to form the gettering zone. Thus, the gettering zone may be removed, deteriorating a gettering function.

Semiconductor device and method for forming the same


An image processing device obtains a depth information image representing a distribution of depth information about an object on the basis of first and second images that have different degrees of blurring and that are captured by an image sensor including groups each including pixels that obtain different color information about the object. The image processing device includes an extracting unit configured to extract signals, each corresponding to one of the pixels of each group, from the groups and generate first and second extracted images respectively corresponding to the first and second images, and a calculating unit configured to calculate the depth information image from a difference in degree of blurring between the first and second extracted images. The signals each corresponding to one of the pixels of each group and extracted from the groups are signals corresponding to pixels that obtain the same color information.

Field of the Invention
The present invention relates to an image processing device and an image capturing apparatus for obtaining a depth information image, which represents a distribution of depth information about an object, from a plurality of captured images. The present invention also relates to an image processing method for obtaining a depth information image, which represents a distribution of depth information about an object, from a plurality of captured images.
Description of the Related Art
Japanese Patent Laid-Open No. 01-167610 describes a "depth from defocus" (DFD) method for obtaining the distance to an object in the depth direction by using a two-dimensional image of the object captured by an image capturing apparatus. In the DFD method, a plurality of images that have different degrees of blurring are obtained by controlling the shooting conditions (also referred to as the shooting parameters) of an image capturing optical system. Then, the correlation between the sizes or the degrees of blur of a plurality of images is calculated by using a distance-measuring pixel and the surrounding pixels. The correlation between the sizes or the degrees of blur changes in accordance with the distance from the focus position of the image capturing optical system to an object. Therefore, the distance from the focus position of the image capturing optical system to the object can be obtained by using the correlation.
Japanese Patent Laid-Open No. 2010-016743 describes a distance-measuring apparatus for calculating the object distance by using a blur correlation, which is calculated for each of regions to be processed by using a DFD method. The distance-measuring apparatus sets a weight coefficient for the blur correlation for each of pixels in a region to be processed and calculates a weighted average of the blur correlation by using the weight coefficients.
In general, an image capturing optical system of an image capturing apparatus has an axial chromatic aberration, and therefore the focus positions differ between colors (wavelengths). As a result, in the case where depth information is calculated by using a correlation between the sizes or the degrees of blur, the calculated depth information has an error due to a color (wavelength). In other words, when depth information is calculated by using a DFD method or the like using a color image, a distance-measurement error due to a color (wavelength) occurs.
Japanese Patent Laid-Open No. 01-167610 and Japanese Patent Laid-Open No. 2010-016743 do not describe the occurrence of an error in depth information due to a color (wavelength).
The present invention provides a technology for obtaining depth information about an object with high precision by using a DFD method using a color image.

Image processing device, image capturing apparatus, and image processing method


Methods and apparatus to generate wide dynamic range images are disclosed. An example apparatus includes a first processing block having first input, second input to receive input data from an image sensor, and first output; a second processing block having third input, fourth input to receive input data from the image sensor, and second output, at least one of the first and second outputs to output a WDR image based on at least two of the first, second, third and fourth inputs; an architecture recognizer having fifth input and third output, the third output to convey an architecture type of the image sensor; a function selector having fourth output to identify at least one of the first and second processing blocks based on the third output; and a sensor adapter having seventh input coupled to the fourth output and having fifth output coupled to the first and third inputs.

Wide Dynamic Range (WDR) imaging techniques enable capturing photographs with high light variations (e.g., >60 dB) within a given image. Typically, imaging sensor manufacturers support WDR using proprietary image processing techniques relating to actual physical capture techniques and/or transmission format methodologies.
The figures are not to scale. Wherever appropriate, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts.


A method for automatic loading to a host of a functional unit driver stored as part of an executable program on a memory of a first functional unit, the method comprising physically connecting the first functional unit to the host and the first functional unit reporting itself to the host as being a generic storage device to make use of a generic mass storage class driver in the host. An operating system of the host reads an autorun file forming part of the executable program to load and execute on the host a driver set up program forming a part of the executable program. The host uses the driver set up program as executed on the host to install and execute the functional unit driver on the host.

"Plug and Play" is a combination of hardware and software that enables a computer system to recognize and adapt to hardware configuration changes with little or no user intervention. With "Plug and Play", peripheral and other devices may be added or removed dynamically, without awkward and confusing manual configuration, and without an intricate knowledge of computer hardware.
In order to install or use a peripheral or other device without an external driver, the peripheral or other device must conform to at least one of a number of specific classes. Operating systems such as, for example, "Windows" 2000 must pre-load the corresponding class driver. With the class driver preloaded, the operating system may then perform the following tasks:                (a) automatic and dynamic recognition of installed hardware including initial system installation, recognition of any "Plug and Play" hardware changes that have occurred since the last system boot, and response to run-time hardware events such as, for example, dock or undock and device insertion or removal; and        (b) loading of appropriate drivers by the "Plug and Play" manager determining which drivers are required to support a particular functional unit and the loading of those drivers.
However, the driver only includes certain common and existing classes such as, for example, a generic mass storage class, a human interface device class, and a video class. A particular class driver may no longer be applicable if the functional unit manufacturer has added some new features. In this case the functional unit manufacturer may need to supply their own driver preloaded in a non-volatile memory such as a CDROM, or via the Internet. Without the driver the functional unit is not usable on the host, or any other host computer.

Method and system for automatic installation of a functional unit driver on a host


Disclosed herein is an assembly for plasma generation comprising a cathode plate comprising a fixed cathode tip, the cathode tip being integral part of the cathode plate. The assembly further comprises at least one cascade plate, at least one separator plate disposed between the cathode plate and the cascade plate, an anode plate, and an inlet for a gas. The cathode plate, separator plate, cascade plate and anode plate are “electrically isolated” from one another, and the electrically isolated cathode plate, separator plate, and cascade plate define a plasma generation chamber. The cathode tip is disposed within the plasma generation chamber.

This invention relates to an apparatus for generating a consistent and stable plasma. More particularly, it relates to an assembly (this assembly is also referred to as an "arc") for generating a consistent and stable expanding thermal plasma (hereinafter referred to as "ETP"), which assembly is easy to maintain and operate.
Known methods for depositing an adherent coating onto a surface of a substrate by plasma deposition typically comprise passing a plasma gas through a direct current arc plasma generator to form a plasma. A substrate is positioned in an adjoining vacuum chamber (The vacuum chamber is also referred to as the "deposition chamber"). The plasma is expanded into the vacuum chamber towards the substrate. A reactant gas and an oxidant are injected downstream into the expanding plasma. Reactive species formed in the plasma from the oxidant and/or reactant gas contact the surface of the substrate for a period of time sufficient to form an adherent coating.
Plasma sources are used to provide a variety of surface treatments for a number of articles. Examples of such surface treatments include deposition of various coatings, plasma etching, and plasma activation of the surface. An array of multiple plasma sources may be used to coat or treat larger substrate areas. The characteristics of the plasma process are strongly affected by the operating parameters of these plasma sources.
Operating parameters typically used for the current arc design are the flow rate and pressure of the plasma gas, the electrical current applied to the arc and the voltage between cathode and anode. These operating parameters together with the arc geometry and design influence the degree of ionization of the plasma gas and hence surface properties and coating performance of parts coated in a plasma deposition process. In a typical plasma deposition process the gas flow rate and the arc current are controlled and result in control of the operating pressure and voltage.
During plasma treatment, conditions and geometry within the plasma source may drift, i.e. cathode voltage or operating pressure may change without changes in the current or gas flow. These changes can be attributed to a variety of causes within the plasma source. Sources of variability include changes brought about as a result of the erosion of the cathode. Other plasma source components subject to erosion include the cascade plate and the separator plate. During the operation of the plasma source copper can erode from the cascade plate and re-deposit across the insulator leading to reduced resistance between the two isolated plates and ultimately to shorting. Yet another cause leading to resistance changes or shorting of the arc is the presence of water between the electrically isolated plates, e.g. by a failure to exclude water from the environment or by leakage of coolant water into the interior of the plasma source. To counteract such drift, particularly the permanent changes caused by erosion of plasma source components, disruption of the plasma deposition process and disassembly of the plasma source are usually required.
An array of multiple plasma sources may at times be used to coat larger substrate areas. Ideally, the individual plasmas generated by each of the plasma sources in the array should have the same characteristics. In practice, however, source-to-source variation in plasma characteristics is frequently observed. Consequently, articles coated in a plasma deposition device comprising multiple plasma sources can demonstrate undesirable variability in surface coating properties at different locations on the coated substrate surface. Thus there is a need to reduce variability among multiple plasma sources in multi-source plasma deposition devices.
The plasma sources employed in plasma deposition devices have finite lifetimes and must be serviced or replaced periodically. Among typical plasma deposition devices, in order to service (i.e. repair or replace) the plasma source, the plasma deposition chamber must be vented to the atmosphere. Venting the plasma deposition chamber to the atmosphere requires that the plasma deposition process be shut down. This results in downtime and production losses. Furthermore the plasma source design typically comprises a variety of different components, which have to be machined to different tolerances. Thus, in some instances downtime for servicing the plasma source increases due to lack of availability of a component needed as a replacement part.
Typically, drift within a single plasma source cannot be corrected for in real time because such corrections require disruption of the process and disassembly of the plasma source. Where multiple plasma sources are used, minimization of source-to-source variation in the generated plasmas is often desirable. Therefore, what is needed is a simplified apparatus for the generation of a plasma, which apparatus is capable of generating a consistent and stable plasma, is easily serviceable, and which apparatus provides for greater efficiency in plasma mediated surface treatment processes, said efficiency being due in part to a reduction in apparatus downtime during servicing.


Conductive circuits are formed by first metallizing a surface of a molded synthetic resin substrate to form an electrically conductive metallic film coating thereon of a thickness (e.g., between 0.2 to 2 .mu.m) effective to exhibit sufficient electrical conductivity for subsequent electroplating thereon. Non-circuit portions of the metallic film coating are thereafter removed with laser light so as to expose an underlying surface portion of the substrate and thereby form a circuit pattern on the substrate surface which is established by a portion of the metallic film remaining on the substrate surface. An additional metal layer may then be electroplated directly onto the remaining portion of the metallic film to thereby form the conductive circuit.

Conventional SKW and PCK processes form circuits on the surface of a molded article. According to these conventional processes, an article body is double-molded by using, for example, two kinds of materials having different plating properties. A portion of the body on which a circuit is to be formed is selectively plated utilizing the plating property differences between the circuit and non-circuit portions of the body. In such a manner, a metallic circuit is formed thereon. However, these conventional processes require two molding steps thereby making them relatively complicated and uneconomical. Moreover, it is difficult to improve the adhesion of the interface of the two kinds of resins. Thus, plating liquid may enter and remain in the article body.
Conventional circuit forming processes using photoresist have many steps including a photoresist coating step, a circuit pattern exposing step, a circuit pattern developing step, a copper etching step and a photoresist removing step. These conventional photoresist processes, therefore are quite complicated. Moreover, in order to form a three-dimensional conductive circuit on the surface of a three-dimensional molded article, a circuit which meets the desired purpose to a certain extent can be obtained by parallel-ray projection exposure. However, such a process has a problem concerning the accuracy of the circuit. In addition, there is a limit to the solution of this problem when the substrate in use has a certain three-dimensional shape.
Circuit forming processes using laser beams have been developed in recent years. For example, a process having the steps of forming a metallic film of a sufficient thickness as a conductive circuit on the surface of a molded article, and then driving off in small pieces the portion of the metallic film which is not to be used as a conductive circuit with a laser beam to obtain a conductive circuit directly has been devised. This conventional laser process does not need double molding or photoresist coating, and as a result, is relatively simple to practice. However, conventional laser processes require that a sufficiently thick conductive metallic layer (for example, more than 10 .mu.m) be formed in order to obtain a sufficiently high conductivity. Accordingly, when an unnecessary part of such a metallic layer is removed with a laser beam, the laser output level must be increased. Therefore, even molded articles formed of a synthetic resin can be damaged by the intense laser resulting in a diminished external appearance of the product. Moreover, the synthetic resin is carbonized resulting in a deterioration of its insulation properties.

Process for forming conductive circuit on the surface of molded article


A two dimensional sensor array is used to collect light diffracted from the inspected substrate. The signal generated by each individual sensor is passed through a threshold. Those signals which are below the threshold are amplified and are summed up. The summed signal is then passed through a second threshold. Summed signals which pass the second threshold are flagged as indicating suspect locations on the substrate. In the preferred embodiment, the entire circuitry is provided in the form of a CMOS camera which is placed in the Fourier plane of the diffracted light.

This invention relates to systems for inspection of substrates, especially semiconductor wafers and reticles. More specifically, the invention relates to a novel system which utilizes a sensor array in conjunction with two threshold arrangement, preferably integrated on a CMOS camera.
Several systems are known in the art for the inspection of wafers and reticles. Three examples of such systems that are currently available on the market are depicted in FIGS. 1-3. In the system exemplified in FIG. 1, the wafer 100 is illuminated with a light beam emanating from a light source 110 and reaching the wafer at a 90xc2x0 angle (generally referred to as normal illumination). Preferably, light source 110 provides coherent light, i.e., source 110 may be a laser source. The light beam is scanned over the wafer by a scanner 120, typically an acousto-optical deflector (AOD) or a rotating mirror, in the direction marked by the double-headed arrow. The wafer 100 is moved in the perpendicular direction by moving the stage upon which the wafer rests. Thus, a two dimensional area of the wafer can be scanned by the light beam.
Since the wafer has basically a mirror-like top surface, the light beam is specularly reflected back per Snell""s law at 180xc2x0. This specularly reflected light is collected by a light sensor 140 and its signal is used to obtain a xe2x80x9cbright fieldxe2x80x9d image, i.e., an image created from specularly reflected light. However, whenever the light beam hits an irregularity on the wafer, such as a particle, the light scatters in various directions. Some of the diffracted/scattered light is then collected by the light sensors 130, and their signal is used to obtain a xe2x80x9cdark fieldxe2x80x9d image, i.e., an image created from diffracted/scattered light. Thus, irregularities appear in the dark field image as stars in a dark sky.
In the system exemplified in FIG. 2, the wafer 200 is illuminated by a light beam emanating from light source 210, but reaching the wafer at a shallow angle, generally referred to as grazing illumination. The light beam is scanned over the wafer by a scanner 220, typically an acousto-optical scanner or a rotating mirror, in the direction marked by the double-headed arrow. The wafer 200 is moved in the perpendicular direction by moving the stage upon which the wafer rests. Thus, a two dimensional area of the wafer can be scanned by the light beam.
Since the light reaches the wafer at a grazing angle xcex8, its specular reflection is at a corresponding angle, xcex8xe2x80x2, according to Snell""s law. This light is collected by sensor 240, and its signal is used to create the bright field image. Any scattered light is collected by sensors 230, the signal of which is used to create dark field images.
It should be appreciated that in the above exemplified systems, with respect to each sensor the image data is acquired serially. That is, each two dimensional image, whether bright or dark field, is constructed by acquiring signals of pixel after pixel, per the scanned light beam. This is time consuming serial operation, which directly affects the throughput of such systems. Moreover, the scan speed of such systems is limited by the scanner""s speed (i.e., the band-width for an acousto-optic scanner) and by the electronics that support the detectors, e.g., the PMT (Photo-Multiplier Tube). Thus, a need exists to develop a system that does not utilize a scanned light beam.
Another difficulty with systems which use coherent light is diffraction caused by features arranged in a repeated order, thereby effectively forming a grating. Specifically, in semiconductor devices many features are constructed in a repeated order fashion. When these features are illuminated by a coherent light beam, they diffract the light in much the same manner as a diffraction grating would diffract the light. However, such constructive diffraction can be mistaken by the system for a defect. One way to overcome such a problem is to use a spatial filter in the Fourier plane, as exemplified by filters 235 in FIG. 2. This problem and proposed solutions are disclosed in, for example, U.S. Pat. Nos. 4,898,471, 4,806,774, and 5,276,498, which are incorporated herein by reference.
The system depicted in FIG. 3 performs a bright field inspection only, but does not use a scanner to scan the light beam. Instead, light source 310 provides a relatively broader light beam which illuminates the wafer 300 with a relatively large spot 315. A TDI sensor is used to image an elongated strip 325 of the illuminated spot. The length of the strip corresponds to the width of the TDI sensor. For example, if the TDI sensor comprises a 2048xc3x972048 pixels, then the scanned strip is of size 2048xc3x971. As the wafer is moved by the stage, strips are imaged and collected to form a bright field two-dimensional image of the inspected area.
Looking forward, as design rules shrink, the importance of detecting increasingly small irregularities becomes paramount. With design rules such as 0.18 and 0.15 xcexcm, very small irregularities, such as particles of sub-micron size, can be killer defects and cause the device to malfunction. However, in order to detect such small irregularities, one needs to use a very small wavelength light source, such as ultra violate (UV) or deep ultra violate (DUV) light source. This presents at least two crucial problems: first, optical elements operating in the DUV regime are expensive and, second, small short wave implies small spot size of the light beam; thus, the scanning speed and collection data rate need to be increased.
The small size of killer defects also present a formidable challenge for bright field system which do not use scanning, such as the TDI system depicted in FIG. 3. Specifically, since bright field system construct an actual image of the inspected area, the image includes multitude of structural elements built upon the wafer. Thus, the resulting image looks much like a maze, and it is increasingly difficult to detect a small irregularity in the maze-like image. Thus, the system requires a complicated image processing algorithm to recognize the defect, thereby increasing the processing power and time required and increasing the cost of purchasing and operating the system. It is not clear at this time whether even the most sophisticated algorithm may be unable to detect such small irregularities.
According to the present invention, a two dimensional sensor array is used to collect light returned from the inspected substrate. The signal generated by each individual sensor is passed through a threshold. Those signals which are below the threshold are amplified and are summed up. The summed signal is then passed through a second threshold. Summed signals which pass the second threshold are flagged as indicating suspect locations on the substrate.
The preferred implementation of the present invention is an integrated CMOS camera. Specifically, both thresholds, the amplifiers and the adder are integrated into the CMOS camera. This implementation is advantageous in that it enables much faster throughput of the system.

Inspection systems using sensor array and double threshold arrangement


The invention relates to a locking device for an anchor rod which may be mounted to a wall formwork. Moreover the invention relates to an associated wall formwork as well as process for mounting the locking device to the wall formwork. Moreover the invention relates to a system having a locking device and wall formwork. A locking device having a locking means for mounting the locking device to one end of an anchor rod and a mounting device for mounting the locking device to a wall formwork is provided. The mounting device comprises a screw which is tilted such that it may be secured in a hole of a supporting element of a wall formwork. A wall formwork thus advantageously does not require a thread in order to be able to mount the locking device to a wall formwork.

In formwork technology difference is made between a first formwork and a closing formwork. A first formwork is a formwork which is mounted first. Subsequent to this the closing formwork is mounted opposite to the first formwork. Concrete is cast in the interstitial space between the first formwork and the closing formwork. By curing the concrete a wall is produced.
Generally one or both ends of an anchor rod have threads into which screw nuts are inserted as an anchor fixation. The central area of such an anchor rod to which, during concrete casting, concrete may be adjacent advantageously either has a smooth surface or at least will be encased by a bushing having a smooth surface. Otherwise the thread of an anchor rod would be set in concrete. The anchor rod then may not be easily pulled out of the cured concrete.
The maximum effective length of the anchor rod and hence the strength (thickness) of the wall to be concrete cast is regularly defined by the length of the central range of the anchor rod having a smooth surface. At the same time pressure exerted onto the formwork facing by liquid concrete during casting will be dissipated via the screw nuts. The anchor rods thereby will be tensile-strained.
Between the formwork facings spacers may be inserted into the volume of the wall to be cast which may absorb the compressive forces emerging during casting, thereby assuring these compressive forces not to affect the wall thickness in an undesirable manner, i.e. reducing the wall thickness. Alternatively or additionally the locking devices may also be mounted onto the wall formworks so that the latter may also be able to absorb compressive forces.
From the document WO 2008/089737 A1 an anchoring system having two locking devices and one anchor rod for a wall formwork having first and a second formwork elements is known. The anchor rod on each of its both ends has a thread which is inserted into the screw nut elements of the locking devices. Each locking device comprises a calotte plate which is mounted to a back side of a wall formwork by way of mounting means. The anchor system may hence absorb both tensile and compressive forces.

Locking device having wall formwork locking device and process


To provide a polypeptide having ceramidase activity, and a gene encoding thereof useful as an reagent for lipid engineering and as indices for diagnosis of atopic dermatitis, an easy method for detecting the polypeptide and method for detecting the gene as well as a method for detecting atopic dermatitis. A polypeptide having an amino acid sequence as shown in SEQ ID NO: 1 in Sequence Listing, or a polypeptide having an amino acid sequence which has substitution, deletion, addition or insertion of one or more amino acids in the amino acid sequence of SEQ ID NO: 1 and having ceramidase activity; a gene encoding the polypeptide; a gene capable of hybridizing with the above genes under stringent conditions, and encoding a polypeptide having ceramidase activity; an oligonucleotide probe or primer, which is capable of hybridizing under stringent conditions with the above genes or with a gene having a nucleotide sequence complementary thereto; a method for detecting a gene encoding a polypeptide having ceramidase activity, by using the oligonucleotide probe and/or primer; an antibody or a fragment thereof, which is capable of specifically binding to the polypeptide; a method for detecting a polypeptide having ceramidase activity, by using the above antibody or fragment thereof; a method for detecting atopic dermatitis, by the methods.

1. Field of the Invention
The present invention relates to a polypeptide having ceramidase activity, and a gene encoding said polypeptide. More particularly, the present invention relates to an amino acid sequence of ceramidase as well as a nucleotide sequence encoding the amino acid sequence which are useful as an reagent for lipid engineering for analyzing structure and action of ceramide and as an index for diagnosis of atopic dermatitis. In addition, the present invention relates to a method for producing a polypeptide having ceramidase activity by gene engineering. Further, the present invention relates to a method for detecting the polypeptide, and a method for detecting a gene encoding the polypeptide. Further, the present invention relates to a method for detecting atopic dermatitis by utilizing the above method for detecting the polypeptide and the above method for detecting the gene.
2. Discussion of the Related Art
Ceramidase is an enzyme that hydrolyses ceramide, which is one of sphingolipids, into sphingosine and a fatty acid. Sphingosine formed by hydrolysis of ceramide by ceramidase has various physiological activities, such as inhibition of protein kinase C, activation of phospholipase D, inhibition of a calmodulin-dependent enzyme, and the like, and is an important substance which is considered to have a role in regulating cellular functions through its involvement in cell proliferation and intracellular signal transduction. The regulation of the level of such sphingosine is an important role played by ceramidase.
Ceramidases are classified on the basis of its optimum pH into an acidic ceramidase and a neutral/alkaline ceramidase. There have been reported that ceramidases having optimum pH in an acidic region are present in mammalian tissues such as rat brain [Biochemistry, 8, 1692-1698 (1969)], guinea pig epithelial cell [J. Biol. Chem., 270, 12677-12684 (1995)], human kidney [Biochim. Biophys. Acta, 398, 125-131 (1975)], spleen [Biochim. Biophys. Acta, 1004, 245-251 (1989)], fibroblast [Biochem. J., 205, 419-425 (1982)] and epithelium [FEBS Lett., 268, 110-112 (1990)]; human urine [J. Biol. Chem., 270, 11098-11102 (1995)], and the like.
Among these ceramidases, the amino acid sequences and the nucleotide sequences of ceramidase purified from human urine have been determined [J. Biol. Chem., 271, 33110-33115 (1996)]. Utilizing the homology with this gene, a ceramidase gene of a mouse has also been obtained [Genomics, 50, 267-274 (1998)]. However, all these are acidic ceramidases derived from mammals, and no amino acid sequences or nucleotide sequences of neutral/alkaline ceramidase or of ceramidases derived from microorganisms have yet been determined.
On the other hand, a ceramidase-producing microorganism is known to be present on the epidermis of lesion of atopic dermatitis, and this enzyme is suggested to be causative of or be involved in the exacerbation of atopic dermatitis. However, this enzyme is ceramidase of which optimum pH is within an alkaline region (hereinafter referred to as alkaline ceramidase) [J. Biol. Chem., 273, 14368-14373 (1998)].
When a naturally-occurring ceramidase is produced from a ceramidase-producing microorganism, it is necessary to add an expensive sphingolipid to a culture medium in order to induce the production of an enzyme, and in purification step, it is necessary to separate and remove the remaining sphingolipid or a degradation product thereof from a fraction containing ceramidase. In addition, since enzymes other than ceramidases such as sphingomyelinase are simultaneously produced during the culture, it is difficult to isolate and purify only a desired ceramidase from these enzymes. Moreover, the amino acid sequences or the gene structures of microorganism-derived alkaline ceramidase are completely unknown, so that the method for producing ceramidase by gene engineering cannot be utilized.
Furthermore, although the presence of the ceramidase-producing microorganism is expected to be used as an index for diagnosing atopic dermatitis and as a method for confirming a therapeutic effect, no means for simply detecting or identifying such a microorganism has yet been known. Conventional methods have necessitated extremely complicated processes that the microorganism is isolated and then cultured, and thereafter its ceramidase activity is assayed. Thus, a method for producing a high-purity ceramidase derived from microorganisms at a lower cost is desired as well as a method for detecting a ceramidase-producing microorganism in a simple, non-time-consuming procedure.
A first object of the present invention is to provide a polypeptide having ceramidase activity. A second object of the present invention is to provide a gene encoding the above polypeptide. A third object of the present invention is to provide a transformant harbouring the above gene. A fourth object of the present invention is to provide a production method capable of easily and massively producing high-purity ceramidase utilizing the above transformant. A fifth object of the present invention is to provide an oligonucleotide probe or a primer capable of specifically hybridizing with the gene of the present invention. A sixth object of the present invention is to provide an antibody or a fragment thereof, which is capable of specifically binding to a polypeptide of the present invention. A seventh object of the present invention is to provide a method for detecting a ceramidase gene by using the oligonucleotide probe or the primer of the present invention. An eighth object of the present invention is to provide a method for detecting ceramidase by using the antibody or the fragment thereof of the present invention, and a kit used therefor. Furthermore, a ninth object of the present invention is to provide a method for detecting atopic dermatitis by utilizing a method for detecting the ceramidase gene or method for detecting ceramidase of the present invention.
As a result of intensive investigation in order to isolate a gene encoding a polypeptide having ceramidase activity, the present inventors have succeeded in isolation of a gene encoding a polypeptide having ceramidase activity and elucidation of the nucleotide sequence of the gene. In addition, based on such findings, the present inventors have established a method capable of easily and massively producing high-purity ceramidase; a method for detecting a polypeptide having ceramidase activity; and a method for detecting the ceramidase gene, and the present invention has been completed thereby. In addition, the correlation between such ceramidase and atopic dermatitis has been found, whereby a method for simply detecting atopic dermatitis has been able to be established.
Specifically, the gist of the present invention follows:
[1] a polypeptide having an amino acid sequence as shown in SEQ ID NO: 1 in Sequence Listing, or a polypeptide having an amino acid sequence which has substitution, deletion, addition or insertion of one or more amino acids in the amino acid sequence of SEQ ID NO: 1 and having ceramidase activity;
[2] a gene encoding the polypeptide of the above item [1];
[3] the gene according to the above item [2], wherein the gene has a nucleotide sequence as shown in SEQ ID NO: 2 in Sequence Listing, or a nucleotide sequence which has substitution, deletion, addition or insertion of one or more bases in the nucleotide sequence of SEQ ID NO: 2 and encodes a polypeptide having ceramidase activity;
[4] a gene capable of hybridizing with the gene of the above item [2] under stringent conditions, and encoding a polypeptide having ceramidase activity;
[5] a transformant harbouring the gene of the above item [2];
[6] a method for producing a polypeptide having ceramidase activity, comprising culturing the transformant of the above item [5], and collecting a polypeptide having ceramidase activity from the resulting culture;
[7] an oligonucleotide probe or a primer, which is capable of hybridizing under stringent conditions with the gene of the above item [2] or with a gene having a nucleotide sequence complementary thereto;
[8] a method for detecting a gene encoding a polypeptide having ceramidase activity, by using the oligonucleotide probe and/or the primer of the above item [7];
[9] a kit for detection of a gene encoding a polypeptide having ceramidase activity, comprising the oligonucleotide probe and/or the primer of the above item [7];
[10] an antibody or a fragment thereof, which is capable of specifically binding to the polypeptide of the above item [1];
[11] a method for detecting a polypeptide having ceramidase activity, by using the antibody or the fragment thereof of the above item [10];
[12] a kit for detection of a polypeptide having ceramidase activity, comprising the antibody or the fragment thereof of the above item [10];
[13] a method for detecting atopic dermatitis, comprising detecting a gene encoding a polypeptide having ceramidase activity by the method of the above item [8]; and
[14] a method for detecting atopic dermatitis, comprising detecting a polypeptide having ceramidase activity by the method of the above item [11].


In a transmission for a motor vehicle of a reduction gearing design with power branching including a main shaft and a counter shaft, a first component transmission and a planetary gear unit, power is branched to the countershaft by the first component transmission in certain gears and recombined via the planetary gear unit and a direct power transmission path is provided wherein the countershaft is decoupled selectively by means of a control device.

The invention relates to an automated transmission of a reduction gearing design having a plurality of discrete transmission stages and power branches for a motor vehicle and to a method of operating such a transmission.
U.S. Pat. No. 5,381,703 and DE 100 51 354 A1 disclose transmissions of a reduction gearing design, in which, in direct gear, an input shaft of the transmission is connected to an output shaft of the transmission so as to rotate with it and without intermediate intermeshing gearwheels. In such a direct gear the countershaft is decoupled from the input shaft and the output shaft gear shifting elements are shifted into a neutral position. In this way it is possible to improve the efficiency in direct gear since the countershaft and transmission elements, which are possibly connected to the countershaft, are not rotating. As a result, it is possible, on the one hand, to reduce the inertia of the drive train. On the other hand, bearing friction and any churning losses of the countershaft with assigned transmission elements in an oil sump do not rotate so that the power loss is minimized.
Furthermore, DE 198 53 824 A1 discloses a double clutch transmission in which the drive torque in one component transmission is transmitted via a countershaft while in another component transmission a direct gear is provided.
If the latter component transmission is activated via the double clutch in direct gear, this is accompanied by a release of the drive connection to the countershaft of the first component transmission by releasing the assigned clutch of the double clutch so that the countershaft is also decoupled from an input shaft of the transmission.
Furthermore, documents DE 27 36 834 A1 and DE 27 36 929 A1 disclose a vehicle transmission of a reduction gearing design, in which power branching takes place in all the forward gears as well as the reverse gear with the exception of a direct, highest gear. For the power branching, a gearwheel of a countershaft has a drive connection both to the one countershaft and to the other countershaft via an intermediate gearwheel which is mounted so as to be rotatable with respect to a main shaft. Power is output by combining the two power paths at a gearwheel which is mounted so as to be rotatable with respect to the main shaft and which has a drive connection at its circumference to, in each case, one gearwheel which has a fixed drive connection to a countershaft. Accordingly, the power is divided between the two countershafts so that it is ensured that the mechanical loading for transmission elements lying in the power flux downstream of the branching point is also halved. However, the abovementioned power branches can be combined only if the two countershafts rotate at the same rotational speed, which makes the periphery conditions for dividing the power outputs between the power branches and the configuration of the possible transmission ratios more difficult.
Finally, WO 03/025431 A1 discloses an automated transmission for a motor vehicle which has a plurality of discrete transmission stages and is of a reduction gearing design. The countershaft has a continuous drive connection to a transmission input shaft via an input constant. At the output end, a three-shaft transmission or variable-ratio gear unit is connected downstream of the reduction gearing unit and thus forms a further component transmission. At the lowest gears, a transmission element of the three-shaft transmission is locked by means of a brake, while the reduction gearing unit is embodied in a customary fashion with a single power branch which extends via the countershaft. For further transmission gears power branching takes place, with a sun wheel of the three-shaft transmission being connected directly to the transmission input shaft in a first power branch, while the second power branch extends via the countershaft. The two power branches are joined in the three-shaft transmission, with the transmission output shaft being coupled to the web of the three-shaft transmission.
Continuously variable transmissions relate to a different branch of technology in which it is necessary to ensure the continuously variable ratio change in transmission power branch by what is referred to as a CVT, together with combination of the power branches in a planetary gear unit. Such transmissions, for example corresponding to DE 199 44 792 A1, DE 196 31 216 A1, U.S. Pat. No. 4,682,511, U.S. Pat. No. 4,662,240 are therefore not transmissions of the generic type with a plurality of discrete transmission stages.
It is the object of the present invention to improve a transmission of the generic type with different shift states, a number of gears that can be implemented and also the synchronization procedures.
Furthermore, it is an object of the invention to improve a method of operating a transmission in a motor vehicle by reducing losses, wear, noise, shifting times and/or shifting processes.

Automated motor vehicle transmission and method of operating the same