A microprocessor by a pipeline control method with the process of a machine instruction divided into several stages for performing the parallel processing in each stage comprises a register file for holding the data necessary for the internal arithmetic processing and providing an arithmetic circuit with the data, a plurality of timing registers for temporally holding the parallel processed data in each stage, and a short pass circuit connected between the output of the arithmetic circuit as well as the timing registers of holding the operation result by the arithmetic circuit and the timing registers of holding the input data for the arithmetic circuit, the short pass circuit selecting operands the register file can't provide with at a time from the output of the arithmetic circuit or from the output of the timing register of holding the operation result by the arithmetic circuit and simultaneously providing the timing registers of holding the input data for the arithmetic circuit with the data of the operands.

1. Field of the Invention
The present invention relates to a microprocessor, and more particularly to a pipeline controlled microprocessor.
2. Description of the Related Art
This kind of a conventional pipeline controlled microprocessor has been used in order to improve the throughput for a machine instruction during a given period. For example, FIG. 6 is a block diagram showing a first example of the conventional pipeline controlled microprocessor.
The conventional pipeline controlled microprocessor of the first example comprises a register file 408 having two read ports and holding the data necessary for the internal arithmetic processing of a machine instruction, an ALU 411 and a shifter 414 constituting an arithmetic circuit for performing an arithmetic and logic operation by the use of the data held in the register file 408, a plurality of timing registers 406, 407, 412, 413, 415, 416, 417, 419 and 424 for holding the parallel processed data in the respective stages into which the process of the machine instruction is divided.
The microprocessor further comprises an instruction cache 401, an instruction aligner 402, a program counter 403, an incremental counter 404, an address selector 405, bypass selectors 409 and 410, arithmetic output selectors 418 and 423, a data address register 420, a data cache 421, a data aligner 422 and a write buffer 425.
The microprocessor of the first example divides the process of a machine instruction into the following five stages; IF (Instruction Fetch), RF (Register Fetch), EX (Execute), DF (Data Fetch) and WB (Write Back), and parallely processes the movement as follows in the respective stages.
In the stage of IF, the microprocessor reads a machine instruction from the instruction cache 401 through the instruction aligner 402, and holds the data in the timing register 406.
In the stage of RF, the microprocessor decodes the machine instruction read out therefrom, decides the type of the operation, reads out the data within the register operand-designated by the instruction from the register file 408, and holds the data in the timing registers 412 and 413, or the timing registers from 415 to 417.
In the stage of EX, the microprocessor executes the operation decided by the machine instruction by the use of the read data within the register, and holds the result in the timing register 419 or writes the operation result into the program counter 403 as an address, thereby performing an instruction branch.
In the stage of DF, the microprocessor writes the data within the register file 408 into the data cache 421 by the use of the operation result, reads out the data within the data cache 421 and holds the data in the timing register 424, or holds the operation result held in the timing register 419, in the other timing register.
In the stage of WB, the microprocessor writes into the register file 408 the data read out from the data cache 421 or the data within the timing register 424 holding the operation result.
The case of executing the following machine instruction string will be explained as a concrete example.
______________________________________ xor r1, r4 ; exclusive OR shld3 r2, r3, r4 ; connection and left shift add r6, r7 ; addition ______________________________________
The first instruction `xor` is an instruction so as to execute the exclusive OR operation for a first operand and a second operand and store the result into the second operand. The second instruction `shld3` is an instruction of three operands so as to connect the second operand and a third operand, shift it to the left for the shift number designated by the lower five bits of the first operand, and store the resultant upper 32 bits into the third operand. The third instruction `add` is an instruction so as to execute the addition of the first operand and the second operand and store the result into the second operand.
FIG. 9 is a timing chart showing the movement of the microprocessor executing the machine instruction string described above.
At first, the microprocessor reads the first instruction `xor` from the instruction cache 401 through the instruction aligner 402, and holds the data in the timing register 406.
In the next cycle, the microprocessor decodes the first instruction `xor` read out therefrom, reads out the data within the register r1 and the register r4 designated as the first operand and the second operand by the instruction from the register file 408, and holds each data in the respective timing registers 412 and 413 providing the ALU 411 with the data through the respective bypass selectors 409 and 410. Simultaneously, the microprocessor reads the second instruction `shld3` and holds the data in the timing register 406.
In the next cycle, the microprocessor executes the exclusive OR operation of the first instruction `xor` by means of the ALU 411 and holds the operation result in the timing register 419. Simultaneously, it decodes the second instruction `shld3`, reads out the data within the register r2 and the register r3 designated as the first operand and the second operand by the instruction from the register file 408, and holds each data in the respective timing registers 415 and 416 providing the shifter 414 with the data through the respective bypass selectors 409 and 410.
However, the third operand designated by the instruction `shld3` is not prepared in this cycle because of only two sets of read ports in the register file 408 and bypass selectors provided there. Accordingly, shift operation can't be performed in the next cycle, so that the third instruction `add` read into the timing register 406 won't be performed in the next cycle.
In the next cycle, the operation result of the first instruction `xor` held in the timing register 419 for adjusting the timing to write the data into the register r4 is further held in the other timing register 424 as well as in the timing register 417 providing the shifter 414 with the third input data. The third instruction `add` read into the timing register 406 is reserved in this cycle.
In the next cycle, the operation result of the first instruction `xor` held in the timing register 424 is written into the register r4 of the register file 408. The microprocessor executes the operation of the second instruction `shld3` and holds the operation result in the timing register 419. It further decodes the third instruction `add`, reads out the data within the registers r6 and r7 designated as the first operand and the second operand by the instruction from the register file 408, and holds each data in the respective timing registers 412 and 413 providing the ALU 411 with the data.
As illustrated in FIG. 9, delay for one cycle in the instruction operation occurs in the pipeline controlled process of the machine instruction string in the respective cycles, because of the incapacity to prepare the third operand at the same time as the other operands when executing the connection and left shift operation explained as the second instruction `shld3`, which is called a structure hazard. The presence of time slot killed by the structure hazard is shown in FIG. 7. Such structure hazard similarly occurs in the instructions requiring three input operands like the instruction `shld3`.
FIG. 7 is a block diagram showing a second example of the conventional pipeline controlled 32 bits microprocessor.
The conventional pipeline controlled microprocessor of the second example comprises a register file 508 having three read ports and holding the data necessary for the internal arithmetic processing of a machine instruction, an ALU 512 and a shifter 515 constituting an arithmetic circuit for performing an arithmetic and logic operation by the use of the data held in the register file 508, a plurality of timing registers 506, 507, 513, 514, 516, 517, 518, 520 and 525 for holding the parallel processed data in the respective stages into which the operation process of the machine instruction is divided, and a bypass selector 511 for selecting the data to be held in the timing register 518.
Other blocks are the same as those of the conventional microprocessor of the first example shown in FIG. 6, and hence the explanation thereof is omitted.
When the conventional microprocessor of the second example similarly executes the machine instruction string which has been used for explaining the movement of the conventional microprocessor of the first example, such a structure hazard that occurs in executing the instruction `shld3` by the conventional microprocessor of the first example doesn't occur in the second example. This is why the register file 508 has three read ports capable of simultaneously providing the shifter 515 with three operands necessary for the internal arithmetic processing of the instruction `shld3`.
The register file 508 having three read ports, however, requires a chip area about one and a half times larger than the register file 408 having two read ports indicated in FIG. 6.
Hereinafter, a parallel arithmetic processing unit disclosed in the Japanese Unexamined Patent Publication (Kokai) No. Heisei 5-88893 will be briefly described as a third example of the prior art with reference to FIG. 8.
The parallel arithmetic processing unit comprises arithmetic means 601 and 602, a data storage means 603, a judging means 604, bypass means 605 and 606, and an arithmetic control means 607.
When there is dependency between arithmetic instructions, the arithmetic control means 607 selects an arithmetic means 601 for executing a depended arithmetic instruction and an arithmetic means 602 for executing a depending arithmetic instruction according to the judgment by the judging means 604, and outputs the input data corresponding to the respective arithmetic means 601 and 602 from the data storage means 603. Simultaneously, the output data in the arithmetic means 601 executing the depended arithmetic instruction is directly output from the data storage means 603 through the bypass means 605 as an input data for the arithmetic means 602 executing a depending arithmetic instruction, thereby to prevent the data hazard. When there is no dependency between the arithmetic instructions, the arithmetic control means 607 selects the arithmetic means 601 or 602 corresponding to each arithmetic instruction, and outputs the input data corresponding to the arithmetic means 601 or 602 from the data storage means 603.
When the arithmetic means 601 or 602 is a shifter 414 as indicated in FIG. 6 of the first example, a structure hazard occurs due to queuing of the third operand because there is no means to provide three input operands at a time as designated by the three operand instruction.
When a register file holding the data necessary for the internal arithmetic processing of a machine instruction has two read ports as explained in the 32 bits microprocessor of the first example, a machine instruction requiring two or less input operands could be executed efficiently, without disturbing the pipeline control. However, a machine instruction requiring three input operands demands extra time for preparing the third operand, causing a structure hazard such as to disturb the pipeline control, which results in deteriorating the instruction throughput of the microprocessor. The like problem occurs in the parallel arithmetic processing unit of the third example.
When a register file holding the data necessary for the internal arithmetic processing of a machine instruction has three read ports as explained in the 32 bits microprocessor of the second example, a machine instruction requiring three input operands causes no structure hazard such as to disturb the pipeline control because of the capability to provide three operands at a time. However, a register file having three read ports needs a register file chip area about one and a half times larger than a register file having two read ports. This results in increasing the chip area of the microprocessor and decreasing the yielding per a semiconductor wafer.
In the case that one read port is provided in the register file, because the number of a transistor increases with 2 pcs per one bit, the number of transistors needed for a general register files having the structure of 32 bits.times.32 registers increases with 2048 pcs.
A logical circuit is also necessary for controlling the read port of a register file. More transistors demands more power consumption, and an expensive package for sealing such a microprocessor is also necessitated, which results in raising the price of the microprocessor products. Increase in power consumption is not preferable considering the recent market tendency toward less consumption. Increase in price and power consumption will deteriorate competitive power in the market.


A method of computing an inversion (X) of a nearly Toeplitz n by n matrix (A). A perturbation matrix (E) is first determined such that the sum of the nearly Toeplitz matrix (A) and the perturbation matrix (E) is a Toeplitz matrix (T). The inversion is solved by solving the equation X=T−1(B+EX), where B is a vector or matrix of dimension n by m. An initial estimate X(0) is selected and estimates of the inversion X are iteratively computed through the recursion X(n−1)=T−1(B+EX(n)). The initial estimate X(0) may be equal to an inversion (T−1) of the Toeplitz matrix (T). The present invention may be utilized in a radio receiver to efficiently compute (1) a least-squares (LS) channel estimate, (2) minimum mean squared error (MMSE) prefilter coefficients for a decision feedback equalizer (DFE), or (3) an autoregressive (AR) noise-spectrum estimation from a finite number of observed noise samples.

The present invention relates generally to radio telecommunication networks. More particularly, and not by way of limitation, the present invention is directed to an efficient method of inverting nearly Toeplitz or block Toeplitz matrices in adaptive wireless receivers.
The ability to adapt to different propagation and interference conditions is highly important in modern wireless receivers. In a typical adaptive receiver, various parameters that characterize the current communication link conditions, such as channel response and interference statistics, are often estimated over a limited number of received signal samples. The core of such estimation processes often requires the inversion of matrices that have approximately Toeplitz or block Toeplitz forms. A Toeplitz matrix is any n×n matrix with values constant along each top-left-to-lower-right diagonal. More precisely, if T is a Toeplitz matrix, then the element in the i-th row and the j-th column, for any i and j, can be expressed as [Tij]=a(i-j) for some scalar function, a(k), where k is an integer, as shown below:
  T  =      [                                        a                                      (              0              )                                                            a                                      (                              -                1                            )                                                …                                      a                                      (                              -                                  (                                      n                    -                    2                                    )                                            )                                                            a                                      (                              -                                  (                                      n                    -                    1                                    )                                            )                                                                        a                                      (              1              )                                                            a                                      (              0              )                                                            a                                      (                              -                1                            )                                                ⋮                                      a                                      (                              -                                  (                                      n                    -                    2                                    )                                            )                                                            ⋮                                      a                                      (              1              )                                                            a                                      (              0              )                                                            a                                      (                              -                1                            )                                                ⋮                                                  a                                      (                              n                -                2                            )                                                ⋮                                      a                                      (              1              )                                                            a                                      (              0              )                                                            a                                      (                              -                1                            )                                                                        a                                      (                              n                -                1                            )                                                            a                                      (                              n                -                2                            )                                                …                                      a                                      (              1              )                                                            a                                      (              0              )                                            ]  A block Toeplitz matrix is defined in the same manner except that a(k) is a p×p matrix function where n is divisible by the integer p.
An exemplary use of nearly Toeplitz or block Toeplitz matrices is found in equalizers that address the problem of multipath fading of wireless channels. Multipath fading is a key phenomenon that makes reliable transmission difficult in a wireless communication system, and is typically caused by reflections of the transmitted radio signal from numerous local scattering objects situated around the receiver. Not only is such multi-path fading time-varying, but it also causes intersymbol interference (ISI) at the receiver. To mitigate the detrimental effect of ISI, a wireless receiver typically uses an equalizer. One of the best and most popular equalization method is the maximum-likelihood sequence estimation (MLSE). To operate properly, an MLSE equalizer requires an accurate estimate of the wireless channel. Because of the time-varying nature of the fading channel, the channel estimate often needs to be updated periodically. The least-squares (LS) method is one of the most commonly used methods of channel estimation. To compute an LS channel estimate, it is known that the inversion of so-called Fisher information, which is a matrix that is nearly, but not exactly Toeplitz, is required. (See, Crozier, S. N. et. al., "Least sum of squared errors (LSSE) channel estimation," IEEE Proceedings-F 1991, pp. 371-378, which is hereby incorporated by reference.)
Although an MLSE equalizer can provide excellent performance in terms of reducing the overall bit error rates, its complexity of implementation grows exponentially with the length of the channel estimate. Consequently, in situations where the channel response is relatively long, a reduced complexity equalizer, such as the decision-feedback equalizer (DFE) is often used instead. A DFE equalizer demodulates the transmitted symbols sequentially one after another and uses the demodulated symbols of previous time instants to estimate the effect of ISI that these previous symbols cause at the next time instant. In order to improve the estimate of ISI, a prefilter is often used before a DFE equalizer to transform the effective channel response so that most of the energy of the resulting channel response, after prefiltering, is concentrated in the front-most channel tap. Since the original channel response may vary with time, the prefilter also needs to be computed periodically. One of the most commonly used prefilters is the minimum-mean-squared-error (MMSE) prefilter. To compute an MMSE prefilter, the receiver needs to invert a nearly Toeplitz matrix that depends on the channel response as well as the variance of noise in the received signal. (See, Proakis, John G., Digital Communications, 2nd edition, McGraw-Hill, 1989, which is hereby incorporated by reference.)
For yet another example, consider a high-capacity cellular communication network where radio frequencies are being reused in different geographical areas within close proximity. In such a network, mutual interference among users occupying the same radio channel is often a major source of signal disturbance. Thus, mobile receivers that are capable of suppressing interference are highly desirable. A simple and effective method of suppressing interference is to model the interference as colored noise and to attempt to whiten the noise using a linear predictive filter, commonly referred to as a whitening filter. The whitening filter flattens the frequency spectrum of the noise (or "whitens" the noise) by subtracting from it the portion that is predictable using estimates of noise samples from previous time instants. Through this whitening process, the noise power is reduced. Since the spectrum of the interference typically varies with time, the receiver often needs to adaptively compute such a whitening filter based on the received signal. A popular and effective method of computing this whitening filter, or equivalently of estimating the interference spectrum, is the covariance method. (See, Kay, S. M., Modern Spectral Estimation, Theroy & Application, Prentice-Hall, 1988, which is hereby incorporated by reference.) The covariance method requires the calculation of the inverse of a noise covariance matrix that is nearly, but not exactly Toeplitz. This covariance matrix becomes a block Toeplitz matrix when the received signal consists of multiple branches, which may come from multiple antennas or oversampling of the received signal.
As can be seen from the above examples, in channel estimation processes, these matrices are typically not known a priori, and since they need to be inverted in real time, efficient techniques for inverting nearly Toeplitz matrices are highly desirable. While efficient algorithms exist for inverting Toeplitz and block Toeplitz matrices, relatively little is known about inverting nearly Toeplitz matrices. Typically, nearly Toeplitz matrices have been inverted using techniques for solving linear equations such as the Gaussian elimination, Cholesky decomposition, and the Gauss-Seidel algorithm. However, these techniques do not exploit the nearly Toeplitz structure, and thus tend to be too complex to implement efficiently. In Friedlander, B., et al., "New Inversion Formulas for Matrices Classified in Terms of Their Distance From Toeplitz Matrices," Linear Algebra and its Applications, Vol. 27, pp. 31-60, 1979, an algorithm was proposed for inverting a class of nearly Toeplitz matrices based on the notion of displacement rank. This algorithm is quite complex to implement and provides computational benefits only for those matrices with low displacement ranks. In co-owned PCT application WO 02/15505, an algorithm is proposed for inverting a specific form of nearly Toeplitz matrix of the form, (CHC+σ2I), where C is an Lf×Lf truncated convolutional matrix of the channel response. However, the algorithm proposed in WO 02/15505 is also complex and only works for matrices in this specific form, but not for other nearly Toeplitz matrices in general.

Method of inverting nearly Toeplitz or block Toeplitz matrices


A connecting means adapted to fix or release a first element (4) and a second element (5) includes a locking pin (1) which is moveable to remote activation means between a locked position. In which leg (8) expends wall (9) into recess (10), and an unlocked position. The remote activation means may be magnetic, electro-magnetic or any other suitable means. A method of fixing or releasing first and second elements by remote activation means is also disclosed. The invention further provides a first element having first means (166) adapted to cooperate with second means (165) on a second element to facilitate connection of the first and second elements. A method of manufacturing the first element includes the steps of depositing discrete amounts of setable material on a surface of the first element and inverting the element to permit the material to set under the influence of gravity. A method of reducing the spacing between first and second elements by remote activation means is also disclosed.

The need to fix one element to another, such as a panel to a stud, has given rise to a large technology relating to fasteners. Primitive versions, such as nails and screws, are labour intensive and have the drawback that the fixing means are visible externally. It is desirable to fix one element to another so that the fixing means are not visible externally. This desirability may be based on aesthetic or economic reasons. For some applications, it may be desirable that the fixing means are not visible externally, for security purposes.
Common construction practice is to provide a first fixing stage, followed by a "final fix" stage. This is labour intensive and generally results in post-finishing. It is desirable to eliminate the need for the first fixing stage and to fix only after assembly has been completed.
Further, common methods of fixing are rarely reversible without damage to the elements being fixed. It is desirable to devise a fixing system which, at least in some aspects, is reversible without damage.
Still further, it is common to fix one element to another by the use of connectors which are separate from the first and second elements. It is desirable to incorporate at least part of a connector in a first or second element.


In a digital communication system where a received stuff-synchronized TDM signal is demultiplexed into data signals each containing a sequence of frames. Each frame contains a pointer to indicate the start timing of the frame and specify positive, negative or zero destuffing. A pointer is detected from each data signal and compared with a previous pointer of the data signal stored in a memory. From this comparison the type of destuffing to be performed on a frame is determined, and in response to it, +1, -1 or 0 is added to the previous pointer to produce a current pointer, which is then used to rewrite the previous point. A binary block count value is generated by a single phase counter and compared with the current pointer to generate a start-of-frame signal if it equals the current value.

The present invention relates generally to digital communication systems, and more specifically to a destuffing circuit for a TDM (time division multiplex) signal.
As shown in FIG. 1, a prior art destuffing circuit comprises N identical units associated respectively with data signals demultiplexed from an incoming TDM (time division multiplex) signal. In each unit, the data signal is a sequence of frames each containing a pointer representing the start timing of the frame and the type of stuff either positive, negative or zero stuffing. The pointer is detected by a pointer detector 30-i (where i=1, 2, . . . N) and supplied to a stuff discriminator 31-i in which it is examined to see if the frame of the pointer is to be positively or negatively stuffed or zero-stuffed. The output of stuff discriminator 31-i is applied to a selector 32-i for selectively passing one of high-, medium- and low-rate clock pulses from a clock generator 36 to a phase counter 33-i in which the selected clock is counted to produce a binary output. This binary output is applied to a comparator 34-i in which it is compared with the pointer detected by the associated detector 30-i to detect a coincidence therebetween. When this occurs, comparator 34-i produces a signal indicating the start timing of a frame. A timing circuit 35-i is connected to comparator 34-i to generate various timing signals necessary for processing the data signal by using the start-of-frame signal.
However, it is disadvantageous to provide as many phase counters as there are data signals demultiplexed from a single incoming TDM signal as they add to the complexity and overall dimensions of the destuffing circuit.

Destuffing control by modifying detected pointer with differential value


An allyloxymethylatedpolyamide composition is disclosed, the allyloxymethylatedpolyamide being represented by Formulae I and II: ##STR1## wherein: n is a positive integer sufficient to achieve a weight average molecular weight between about 5000 and about 100,000,. R is an alkylene unit containing from 1 to 10 carbon atoms, PA1 between 1 and 99 percent of the R.sub.2 sites are --H, and PA1 between 1 and 99 percent of the R.sub.2 sites are --H, and the remainder of the R.sub.2 sites is between 25 percent and 99 percent --CH.sub.2 --O--(CH.sub.2).sub.w --CH.dbd.CH.sub.2, wherein PA1 R.sub.1 and R are independently selected from the group consisting of alkylene units containing from 1 to 10 carbon atoms, PA1 between 1 and 99 percent of the R.sub.3 and R.sub.4 sites are --H, and between 25 percent and 99 percent of the remainder of the R.sub.3 and R.sub.4 sites are --CH.sub.2 --O--(CH.sub.2).sub.w --CH.dbd.CH.sub.2, PA1 (a) heating an allyloxymethylatedpolyamide in the presence of a free radical catalyst, and PA1 (b) hydrosilation of the double bond of the allyloxy group of the allyloxymethylatedpolyamide with a silicon hydride reactant having at least 2 reactive sites. PA1 a substrate, PA1 at least one photoconductive layer, and PA1 an overcoat layer comprising. w is 1, 2 or 3, PA2 between 1 and 75 percent of the R.sub.2 sites are --CH.sub.2 --O--R.sub.5, and PA2 R.sub.5 is an alkyl unit containing 1 to 4 carbon atoms, and ##STR2## wherein: m is a positive integer sufficient to achieve a weight average molecular weight between about 5000 and about 100,000, PA2 wherein PA2 a hole transporting hydroxy arylamine compound having at least two hydroxy functional groups, and PA2 a cross linked allyloxymethylatedpolyamide film forming binder.. w is 1, 2 or 3, and PA3 between 1 percent and 75 percent of the R.sub.2 sites are --CH.sub.2 --O--R.sub.5 PA4 wherein R.sub.5 is an alkyl unit containing 1 to 4 carbon atoms.. The allyloxymethylatedpolyamide may be synthesized by reacting an alcohol soluble polyamide with formaldehyde and an allylalcohol.. The allyloxymethylatedpolyamide may be cross linked by a process selected from the group consisting of. A preferred article includes. A stabilizer may be added to the overcoat.

This invention relates in general to allyloxymethylatedpolyamide, and, more specifically, to allyloxymethylatedpolyamide compositions, processes for synthesizing allyloxymethylatedpolyamide, and devices containing allyloxymethylatedpolyamide.
Tough cross linked materials are highly desirable for long life articles and coatings. For some applications, the need for an acid to cross link polymers such as polyamides led to defective products having undesirable physical and electrical properties. For example, cross linking of Luckamide polyamides through acid catalyzed condensation of methoxymethyl groups attached to a polyamide backbone unavoidably produced a low molecular weight molecule which may be trapped in the bulk and sometimes give rise to a bubble defect upon thermal expansion. Moreover, improvements were desirable in mechanical strength and abrasion resistance when exposed to alcohol, hydrocarbons and other solvents.
Electrophotographic imaging members, i.e. photoreceptors, typically include a photoconductive layer formed on an electrically conductive substrate. The photoconductive layer is an insulator in the dark so that electric charges are retained on its surface. Upon exposure to light, the charge is dissipated.
Many advanced imaging systems are based on the use of small diameter photoreceptor drums. The use of small diameter drums places a premium on photoreceptor life. A major factor limiting photoreceptor life in copiers and printers, is wear. The use of small diameter drum photoreceptors exacerbates the wear problem because, for example, 3 to 10 revolutions are required to image a single letter size page. Multiple revolutions of a small diameter drum photoreceptor to reproduce a single letter size page can require up to 1 million cycles from the photoreceptor drum to obtain 100,000 prints, a desirable goal for commercial systems.
For low volume copiers and printers, bias charging rolls (BCR) are desirable because little or no ozone is produced during image cycling. However, the micro corona generated by the BCR during charging, damages the photoreceptor, resulting in rapid wear of the imaging surface, e.g., the exposed surface of the charge transport layer. For example wear rates can be as high as about 16.mu. per 100,000 imaging cycles. Similar problems are encountered with bias transfer roll (BTR) systems. One approach to achieving longer photoreceptor drum life is to form a protective overcoat on the imaging surface, e.g. the charge transporting layer of a photoreceptor. This overcoat layer must satisfy many requirements, including transporting holes, resisting image deletion, resisting wear, avoidance of perturbation of underlying layers during coating. Although various hole transporting small molecules can be used in overcoating layers, one of the toughest overcoatings discovered comprises cross linked polyamide (e.g. Luckamide) containing N,N'-diphenyl-N,N'-bis(3-hydroxyphenyl)-[1,1'-biphenyl]-4,4'-diamine (DHTBD). This tough overcoat is described in U.S. Pat. No. 5,368,967, the entire disclosure thereof being incorporated herein by reference.
Since N,N'-diphenyl-N,N'-bis(3-hydroxyphenyl)-[1,1'-biphenyl]-4,4'-diamine (DHTBD) is sensitive to the oxidative species produced by the various charging devices, a chemical stabilizer is desirable for longer imaging member cycling life. An improved overcoating has been achieved with cross linked polyamide (e.g., Luckamide) and N,N'-diphenyl-N,N'-bis(3-hydroxyphenyl)-[1,1'-biphenyl]-4,4'-diamine (DHTBD) and bis-[2-methyl-4-(N-2-hydroxyethyl-N-ethyl-aminophenyl)]-phenylmethane (DHTPM) as an image deletion stabilizer material. Although excellent overcoatings have been achieved with bis-[2-methyl-4-(N-2-hydroxyethyl-N-ethyl-aminophenyl)]-phenylmethane (DHTPM) as the stabilizer, bis-[2-methyl-4-(N-2-hydroxyethyl-N-ethyl-aminophenyl)]-phenylmethane (DHTPM) is difficult to purify and handle. Moreover, it is expensive, a semi-solid at room temperature and oxidized relatively easily as evidenced by color change of the material during storage. However, since bis-[2-methyl-4-(N-2-hydroxyethyl-N-ethyl-aminophenyl)]-phenylmethane (DHTPM) is soluble in alcohols, the solvents required for forming coatings containing polyamide (e.g. Luckamide), it can be solution coated with a polyamide.
Overcoats should be relatively thin due to their relatively poor charge mobilities. Some of the strength of a thin layer depends on how well secured it is to the substrate on which it is coated. This adhesion can be affected by the choice of solvent mixtures used to coat from. Some solvent systems that produce good films and yield formulations with long pot life produce poorly adhered overcoats. Also, during any cross linking process the morphology at the interface with the underlying layer can change in response to the forces produced by the reaction process thereby adversely affecting adhesion.
Thus, the overcoating layer has many requirements, including hole transport, deletion resistance, wear resistance to both abrasion and corona, coatabillity without producing adverse effects in previously formed layers, and adhesion to the transport layer. In addition to the properties of the final film, the coating solution must also possess certain other properties. Among these are the necessary solids concentration and solution viscosity to achieve the required overcoating layer thickness and a pot life long enough to achieve maximum economy for the coating process.

Allyloxymethylatedpolyamide synthesis compositions and devices


For tube welding, use is made of a locator element intruding into the tube and running with the tube, to position the edges of the tube-round ahead of the welding point with its laser beam (4). The running locator element has a plurality of stops (8, 9, 10, 11) arranged on a driven revolving chain (7). Forming elements (15, 15xe2x80x2) act on the outside of the tube-round to position the edges. A precise edge-positioning for welding, in particular for tube welding, can thus be achieved.

The invention relates to a method and an apparatus for positioning sheet metal edges for butt welding.
When welding thin-walled tubes meaning tubes with a ratio of tube diameter to tube material thickness of, say, a 65 it is known from DE-C-4432674 to hold the tube with a clamping device involving the use of an inner support arm. Positioning the tube in this clamping device is relatively tricky and expensive. Meanwhile there is an increasing demand for welded thin-walled tubes in extremely diverse cross-sections which can subsequently be shaped into components e.g. for the motor vehicle industry e.g. by internal high pressure forming (hydroforming). The forming process depends on the presence of a weld seam of high quality, which in turn requires the abutting edges to be precisely located during welding. The same requirement also arises, of course, in the butt welding of flat sheet-metal items.
Hence one fundamental problem of the invention is to provide a method and/or an apparatus allowing the edges to be precisely positioned.
This problem is solved, in the case of a method of the kind by a method and apparatus for positioning sheet metal edges as they are moved to a welding point for welding by a laser. An endless locator projects between the edges and travels with the edges along a leg of a conveyor path leading to a welding point. The locator element is formed by a revolving chain or belt and has a plurality of stops. At least one endless forming element also travels with the edges toward the welding point for acting on the sheet margin. The forming element may be a chain or belt with a plurality of forming pieces preferably exchangeably arranged thereon.
By providing a locator element travelling with the edges to be welded, the edges can be positioned against this element with suitable force without any possibility of the positioning""s being compromised by friction forces between edges and locator element.
Preferably, the locator element is adapted to assist the bringing together of the edges by provided it with wedge-shaped stops projecting between the edges to different depths. A preferred application of the method lies in the welding of preformed rounds into tubes, particularly into thin-walled tubes. The exact positioning and bringing together of the edges that can be achieved is especially advantageous in this application.
A further problem of the invention is to provide an apparatus for positioning sheet-metal edges.
This is accomplished, in the case of the apparatus stated at the outset, in which the locator elements project between the edges of the sheet metal along the leg of the conveyor path.
The endless element moving with the edges provides a stop that allows frictionless contact to be made between the sheet-metal edges being conveyed, and hence allows precise positioning.
Preferably, the apparatus has wedge-shaped stops and moreover preferably has an adjustable carrier for the endless element enabling the latter""s point of insertion and depth of insertion to be adjusted.
According to the state of the art, rollers are used on the outside of the sheets: in particular, profiled rollers adapted to the outer contour of the tube are used near the welding zone to position the sheets, tube-round, or sheet edges. These rollers are positioning elements acting merely in line, and in the welding zone they have to be cooled, which is expensive.
Therefore the problem exists of providing a means of acting on the sheet to position the sheet, again with a particular view to obtaining the weld quality required for tubes, and thin-walled tubes in particular, especially when the tubes are to be subsequently subjected to internal high pressure forming. A similar problem of edge positioning can also arise in the welding of flat sheets.
The problem is solved, in the case of a method of the kind stated at the outset.
By subjecting the sheet to the action of an endless forming element which moves with the sheet along a leg of the conveyor path, regions of the sheets can be acted upon in a way that allows their edges to be very accurately positioned with respect to each other. Because the endless forming element travels past the welding point and does not remain stationary, special cooling for the said element is usually unnecessary.
The forming element is preferably provided as a cup-shaped containing element for the sheet, particularly in the upper part of a tube-round, and on either side of the weld line.
A further problem of the invention is to provide an edge-positioning apparatus which does not possess the above-mentioned disadvantages.
This is solved, in the case of an apparatus of the kind stated at the outset.
The endless forming element provides a continuous rest for the sheet margins, allowing precise positioning of the edges, even if the sheets are very thin. Furthermore, the forming element does not need cooling.
A further problem of the invention is to cater for the welding of tapered tubes, preferably by the above-mentioned methods. This is realized by arranging a conically preformed tube-round in a conical die and a weld side upper closure of the die has at least one endless forming element conveyed with the die.
A further problem of the invention is to provide an apparatus for welding tapered tubes, preferably corresponding to one of the above-mentioned apparatuses.
This problem is also solved by a conical die to contain the tube-round and at least one forming element that is conveyed with the die to a welding station.

Method and device for positioning edges, especially in tube welding


A mobile station includes a voice mail password in an outgoing call message for a call, a data communication and the like. A mobile telephone switching center determines whether the voice mail password of the outgoing call message from the mobile station is consistent with the voice mail password from the voice mailing system, and provides the call service to the corresponding mobile station when they are consistent with each other. The voice mail password can be registered or changed after the user connects to the voice mailing system and is identified for the voice mail service. Therefore, the user can just merely change the voice mail password, thereby preventing unauthorized use of the mobile station.

1. Field of the Invention
The present invention relates generally to a user identification method in a mobile communication system and a mobile station, and a mobile communication system therefor.
2. Description of the Related Art
In general, a mobile station in a network of a mobile communication system, can only communicate with the network system after user identification (or authentication) is completed. For example, in commercially available Global System for Mobile communications (GSM), user identification is performed as follows: When a mobile station is turned on, the mobile station transmits data stored in a subscriber identification module, which is required for user identification (hereinafter, referred to as a "SIM"), to the network. The network receives the data which is transmitted from the mobile station, and checks the data required for user identification, such as registration information, charge delinquency information, a password and the like. If it is determined that the user allowable, the mobile station is identified (or authorized).
Accordingly, a technology for the user identification using Electric Serial Number (ESN), International Mobile User Identification (IMSI), and Temporary Mobile User Identification (TMSI) in a GSM mobile communication system has been developed.
However, in conventional GSM portable phones, a separate SIM card must be coupled to the Portable Phone (e.g., by sliding the SIM card into a SIM slot.) so that the portable phone can perform user identification. Therefore, when a user of the GSM portable phone loses the portable phone and/or the SIM card, the SIM card can be used or reproduced without authorization for unauthorized use.
Further, when a user loses a mobile station using other communication systems such as, for example, a code division multiple access (CDMA) system or a universal mobile telecommunications system (UMTS), unauthorized persons can use or reproduce the mobile station for unauthorized purposes and the use.
Conventionally, when a user loses a mobile station and/or a SIM card, the user can request a stop in service for the missing mobile station from the mobile station's service provider so as to prevent possible unauthorized use of the mobile station. Accordingly, when a mobile station is lost, the user, should, in order to obtain the stop in service, find a telephone number of the service center and call to the service center to request the stop in service. The service stop process can be inconvenient to the user as it may require a lengthy period until a service provider's representative answers the call. Moreover, personal information may be required which the user may not want to release for various reasons.

User identification method in mobile communication system and mobile station, and mobile communication system therefor


Methods, systems, techniques, and devices for smart factory reset procedures are described. In accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. The memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. The memory system may update a mapping of the memory system based on identifying the first portion and the second portion. The memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.

The following relates generally to one or more systems for memory and more specifically to smart factory reset procedures.
Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programing memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read, or sense, the state of one or more memory cells within the memory device. To store information, a component may write, or program, one or more memory cells within the memory device to corresponding states.
Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3-dimensional cross-point memory (3D Xpoint), not-or (NOR), and not-and (NAND) memory devices, and others. Memory devices may be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed states over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed states for extended periods of time even in the absence of an external power source.
In some systems that include a memory system, a factory reset procedure may be performed. For example, a user may wish to restore a memory system to a factory (e.g., initial or prior) state. However, conventional approaches to factor reset procedures may suffer from one or more deficiencies.

Smart factory reset procedure using one or more commands at least on user data and system data


An obstacle detection apparatus detects an obstacle to a vehicle by a sensor section including a transmitter which transmits a wave to a predetermined detection area, and a receiver which receives an echo of the wave reflected by the obstacle. The obstacle detection apparatus measures a distance to the obstacle from the output of the sensor section. A detection-distance change circuit changes predetermined detection distances in the maximum detection distance. Alarm means gives an alarm step by step in accordance with the detection distances.

1. Field of the Invention
The present invention relates to an obstacle detection apparatus which prevents the collision of a vehicle.
2. Description of the Related Art
Conventionally, there has been proposed an obstacle detection apparatus which detects presence of on obstacle behind a vehicle and informs a person in the vehicle with an alarm. The obstacle detection apparatus has an ultrasonic sensor on a rear bumper of a vehicle, and receives an echo of the ultrasonic wave emitted from that sensor, hit on and reflected by the obstacle, thereby detecting the obstacle behind the vehicle from that echo.
In a four-wheel drive vehicle, however, when an openable/closable body like a tailgate is opened, or when a tire, a ski carrier, etc. are placed at the rear of the vehicle, the distance from the ultrasonic sensor to the obstacle differs from the distance from the rearmost part of the vehicle to the obstacle. This raises a problem that the vehicle has already come closer to the obstacle than is realized by the person in the vehicle, at the time the obstacle is detected by the ultrasonic sensor.
To resolve such a problem, Japanese Unexamined Patent Publication No. 2002-318282 (Patent Literature 1) discloses an obstacle detection apparatus which changes the maximum detection distance of a sensor section, or, specifically, increases the maximum detection distance in accordance with a distance between an ultrasonic sensor and the rearmost part of a vehicle, thereby informing presence of an obstacle early to allow a driver to maneuver the vehicle to avoid the obstacle. Japanese Unexamined Patent Publication No. 6-242238 (Patent Literature 2) discloses a vehicular obstacle detection apparatus which corrects the distance from a sensor section to an obstacle to a proper value for avoiding the obstacle.
According to the technology of Patent Literature 1, a person in a vehicle (driver) backs the vehicle while usually checking the distance to the obstacle. When that distance becomes a shorter, or, when an alarm starts beeping because of the detection of presence of the obstacle in the maximum detection distance, the driver carefully backs the vehicle with the help of that beeping alarm, thereby avoiding a collision with the obstacle. However, in a case where there is a difference between the distance from the ultrasonic sensor to the obstacle and the distance from the rearmost part of the vehicle to the obstacle, when the maximum detection distance changes, the alarm starts beeping at a point where the obstacle is yet sufficiently away from the rearmost part of the vehicle. Accordingly, the driver may feel awkward, and may have to pay unnecessary attention. According to the technology of Patent Literature 2, the distance from the detector to the obstacle is corrected for avoiding the collision of a bumper with the obstacle. Because the alarm sound is constant, however, the driver cannot know how close to the obstacle the vehicle has come from that alarm sound.
The invention has been made in view of the above-described problems. It is an object of the invention to provide an obstacle detection apparatus which can accurately inform a person in a vehicle of the distance to an obstacle without giving awkward feeling to the person in the vehicle.


An epicyclic gear system includes sun and ring gears (2, 4), planet pinions (6, 8) arrayed (a, b) between these gears, and a carrier (10) to which planet pinions are coupled through flexpins (30). The pinions are located between carrier walls (20, 22) with flexpins for the respective arrays cantilevered from opposite walls. The carrier is subjected to externally applied torque which transfers through the system. The load path (pa) for one array is shorter than that (pb) for the other array, which disparity causes carrier distortion with flexpins on one wall angularly displaced from flexpins on the other wall. The system compensates for this by one wall having areas (40, 44) of weakness where the flexpins cantilever from it. This enables the pinions of the two arrays to better mesh under a load and share torque transfer more evenly.

The typical epicyclic gear system has a sun gear, a ring gear surrounding the sun gear, and planet pinions located between and engaged with the sun and ring gears, and in addition, it has a straddle-type carrier that provides pins about which the planet pinions rotate, with the pins being anchored at both ends in the carrier. A gear system so configured has the capacity to transfer a large amount of power in a relatively compact configuration—or in other words, it has a high power density.
But heavy loads tend to distort the carrier and its pins and skew the axis about which the planet pinions rotate. Under such conditions, the planet pinions do not mesh properly with the sun and ring gears. This causes excessive wear in the planet pinions and the sun and ring gears, generates friction and heat, and renders the entire system overly noisy.
A planetary system in which the planet pinions are supported on and rotate about so-called flexpins mitigates the skewing. In this regard, a flexpin for a planet pinion at one end is anchored in and cantilevered from the wall of a carrier of which it is a part. The other end of the flexpin has a sleeve fitted to it, with the sleeve extending back over, yet otherwise spaced from the flexpin. The sleeve supports the planet pinion, in that it serves as a component of a bearing for the pinion. In other words, flexpin technology employs a double cantilever to offset the skewing that would otherwise occur. See U.S. Pat. Nos. 6,994,651 and 7,056,259, which are incorporated herein by reference, for a further discussion of flexpin technology.
The cantilevers produce high stresses in the flexpins, and to have more moderate stresses, some carriers have two walls with flexpins anchored in each of the walls and, of course, a separate planetary pinion around each flexpin. This doubles the number of flexpins to share the torque transferred through the system and thus reduces the unit load applied to each flexpin. The planet pinions are arranged in two arrays between the walls, there being for each pinion in the one array and corresponding pinion aligned with it in the other array. Spaces exist between pairs of corresponding pinions and webs extend between the two walls in these spaces. The carrier, whether it rotates or not, is subjected to an externally applied torque at one of its walls. The planet pinions transmit torque through the system, but the lengths of the load paths from the flexpins on the two walls differ, the load paths from the flexpins on the primary wall, which is subjected to the external torque, being considerably shorter than the load paths from the flexpins on the other or secondary wall. This renders the array, identified with the shorter load paths stiffer than the array identified with the longer load paths. The carrier undergoes a distortion that causes the flexpins on the secondary wall displace angularly with respect to the flexpins on the primary wall, reference being to the axis of the planetary system. Since the planet pinions of the two arrays mesh with the sun and ring gears, the displacement causes an uneven sharing of the torque transmitted at the teeth where the pinions mesh with the sun and ring gears.

Epicyclic gear system having two arrays of pinions mounted on flexpins with compensation for carrier distortion


A sensorless brushless motor driving circuit for a motor having three phases includes a position detecting circuit for detecting the position of the rotor from the terminal voltages of the motor, a commutation switching circuit for generating commutation switching signals based on a position signal from the position detecting circuit, a motor driving transistor circuit for supplying a motor driving currents to the motor in response to driving signals, a buffer circuit for supplying the driving signals according to the commutation switching signals, and a neutral feedback amplifier for detecting a neutral potential of terminal voltages of the motor, comparing the neutral potential with a reference voltage, outputting a first output to the buffer circuit when the neutral potential of the terminal voltages of the motor is higher than the reference voltage and outputting a second output to the buffer circuit when the neutral potential of the terminal voltages of the motor is lower than the reference voltage.

1. Field of the Invention
The present invention relates to a driving circuit for a sensorless brushless motor. The invention particularly relates to a driving circuit for a sensorless brushless motor which detects accurately a rotational position of a three phase motor by keeping the neutral potential of the three phase motor constant.
2. Description of the Prior Art
FIG. 18 shows a conventional driving circuit for a sensorless brushless motor. In FIG. 18, a terminal voltage compressing circuit 300 receives induced voltages of a three phase motor 10 from terminals U, V, and W and compresses or divides the terminal voltage. A terminal voltage correcting circuit 400 detects the current flowing through the motor 10 via a resistor 108, and corrects the terminal voltage according to the motor current. A position detecting circuit 500 detects the rotational position of the motor. A commutation switching circuit 600 switches a commutation current applied to the motor 10, and turns on or off driving transistors 101-106 in a motor driving transistor circuit 100 to rotate the motor.
In the conventional embodiment shown in FIG. 18, for example, focusing on only the U phase, an output voltage of the upper part of the U phase waveform is saturated, as shown in FIG. 24A. If an output current increases, as shown by U' of FIG. 24B, the bottom of the waveform expands, but the upper part of the waveform does not expand, since the upper part of the waveform is saturated. Therefore, the neutral potential is also shifted downward as shown by the arrow in FIG. 24B. Accordingly, the position of the rotor is detected at a different point. To avoid this difference, the terminal voltage correcting circuit 400 is indispensable.
The operation of the conventional driving circuit of the current sensorless brushless motor is explained using FIG. 18. FIG. 19 shows a detailed circuit of a terminal voltage compressing circuit 300. FIG. 20 shows a detailed circuit of a terminal voltage correcting circuit 400. FIG. 21 shows a detailed circuit of a position detecting circuit 500. FIG. 22 shows a detailed circuit of a commutation switching circuit 600.
A specific construction of the terminal voltage compressing circuit 300 is explained below. FIG. 19 shows only one phase of the terminal voltage compressing circuit 300. The terminal voltage from each terminal of the motor 10 is input to an input terminal 301. The voltage divided by resistors 303 and 305 is output from an output terminal 302, relative to a neutral voltage selected by resistors 304 and 305 connected in series between a power supply 310 and a ground 311. This terminal voltage compressing circuit 300 is arranged to supply an appropriate voltage to an input terminal of the terminal voltage correcting circuit 400. The phase voltages U1, V1, W1 are output from the terminal voltage compressing circuit 300 to the inputs of the terminal voltage correcting circuit 400.
The phase voltages U1, V1, W1 supplied from the terminal voltage compressing circuit 300 are input to the terminal voltage correcting circuit 400 of FIG. 20. The terminal voltage correcting circuit 400 of FIG. 20 includes npn transistors 20-34, a pnp transistor 35, resistors 36-56, and constant current sources 57-60. A U-phase terminal voltage U1 is input to the base of the npn transistor 20, a V-phase terminal voltage V1 is input to the base of the npn transistor 25, and W-phase terminal voltage W1 is input to the base of the npn transistor 30. The base of the pnp transistor 35 is connected to a resistor 108 via a terminal 61. The terminals 62-67 are supplied with correction switching signals for changing the correction of the terminal voltage. The corrected terminal voltages of each phase are output as U2, V2, and W2.
The operation of the terminal voltage correcting circuit 400 is explained below using the drawings. In FIG. 20, the terminal voltage correcting circuit for three phases, U, V, and W, are shown, however, only the U-phase terminal voltage correcting circuit is explained.
Assuming that the terminal 62 and the terminal 63 are at high levels, the collector voltages of the npn transistor 22 and the npn transistor 24 reach 0, so the emitter voltages of the npn transistor 21 and the npn transistor 23 reach 0. Therefore, current does not flow through the resistor 37 or the resistor 40. Accordingly, a current i1 supplied from the constant current source 57 only flows through the resistor 36 (resistance: R1). The voltage at the U-phase output terminal of the terminal voltage correcting circuit 400 is obtained by subtracting the voltage drop of the resistor 36 and the base-emitter voltage (Vbe) of the transistor 20 from the input voltage of the terminal voltage correcting circuit 400 as follows. EQU U2=U1-Vbe-R1.multidot.i1 (1)
Assuming that the terminal 62 and the terminal 63 are at low levels, and the voltage Vir is input to the terminal 61. The collector voltages of the npn transistor 21 and the npn transistor 24 become Vir+Vbe (V), so the emitter voltages of the npn transistor 21 and the npn transistor 23 become Vir. Therefore, the current Vir/R2 flows through the resistor 37 (resistance: R2) and the resistor 40 (resistance: R2), respectively. Accordingly, the current flowing through the resistor 36 becomes the sum of the current i1 supplied from the constant current source 57 and the currents flowing through the resistor 37 and the resistor 40. The voltage at the U-phase output terminal of the terminal voltage correcting circuit is obtained from the formula (2) as follows. EQU U1=U-Vbe-R1.multidot.i1-R1.multidot.Vir/R2 (2)
If the terminal 62 is at a high level and the terminal 63 is at a low level, or the terminal 62 is at a low level and the terminal 63 is at a high level, since a current of Vir/R2 flows through the resistor 37 or the resistor 40, the voltage at the U-phase output terminal of the terminal voltage correcting circuit is obtained from the formula (3) as follows. EQU U2=U1-Vbe-R1.multidot.I1-R1.multidot.Vir/R2 (3)
Therefore, the terminal voltage can be corrected by setting the terminal 62 and the terminal 63 at a high level when the voltage drop must be added (current direction: V.fwdarw.U, W.fwdarw.U). In the meantime, when the voltage drop must be subtracted (current direction: U.fwdarw.V, U.fwdarw.W), the terminal voltage can be corrected by setting the terminal 62 and the terminal 63 to low levels.
When the U-phase is not a current-carrying phase and does not need to be corrected (current direction: V.fwdarw.W, W.fwdarw.V), the terminal 62 may be set at a high level and the terminal 63 may be set at a low level, or vice versa. In the same way, as for the V-phase, when the voltage drop must be added (current direction: U.fwdarw.V, W.fwdarw.V), the terminal 64 and the terminal 65 may be set at a high level, when the voltage drop is must be subtracted (current direction: V.fwdarw.U, V.fwdarw.W), the terminal 64 and the terminal 65 may be set at a low level, and when no correction is necessary (current direction: U.fwdarw.W, W.fwdarw.U), the terminal 64 may be set at a high level and the terminal 65 may be set at a low level, or vice versa.
Furthermore, as for the W-phase, when the voltage drop must be added (current direction: U.fwdarw.W, V.fwdarw.W), the terminal 66 and the terminal 67 may be set at high levels, when the resistance drop must be subtracted (current direction: W.fwdarw.U, W.fwdarw.V), the terminal 66 and the terminal 67 may be set at low levels, and when no correction is necessary (current direction: U.fwdarw.V, V.fwdarw.U), the terminal 66 may be set at a high level and the terminal 67 may be set at a low level, or vice versa. The conducting phases and the terminals 62-67 as described above are supplied with correction switching signals K1-K6 as shown in the timing chart of FIG. 25B. The correction switching signals K1-K6 are generated, for example, in a commutation switching circuit 600 described later.
The position detecting circuit 500 is explained below using FIG. 21. In FIG. 21, the position detecting circuit 500 comprises resistors 70-81, differential amplification circuits 82-84, and comparators 85-87. The corrected U-phase terminal voltage U2 is applied to a non-inverting input terminal of a differential amplification circuit 82 and an inverting input terminal of a differential amplification circuit 83, via a resistor 70, and a resistor 75, respectively. The corrected W-phase terminal voltage W2 is applied to a non-inverting input terminal of a differential amplification circuit 83 and an inverting input terminal of a differential amplification circuit 84, via a resistor 74, and a resistor 79, respectively. The corrected V-phase terminal voltage V2 is applied to a non-inverting input terminal of a differential amplification circuit 84 and an inverting input terminal of a differential amplification circuit 82, via a resistor 78, and a resistor 71, respectively. The inverting input terminals of differential amplification circuits 82, 83, and 84 are connected to output terminals of the differential amplification circuits 82, 83, and 84 via resistors 73, 77, and 81, respectively. Each output terminal of the differential amplification circuits 82, 83, and 84 is connected to non-inverting input terminals of comparators 85, 86, and 87, respectively. Furthermore, the reference voltage Vref is input to the non-inverting input terminals of the differential amplification circuits 82, 83, and 84 and inverting input terminals of comparators 85, 86, and 87. The differential amplification circuit 82 outputs differential amplification signals U2 and V2 around the center voltage Vref. The comparator 85 compares the differential amplification signal with Vref and outputs a position signal BU. By the same process, position signals BW and BV are obtained. These position signals, BU, BW, and BV shown in FIG. 25A, are supplied to a commutation switching circuit 600 in the next stage.
FIG. 22 illustrates a conventional commutation switching circuit 600. In FIG. 22, the commutation switching circuit 600 comprises input terminals 601-603 where position signals BU, BW, and BV are respectively input. The commutation switching circuit 600 further comprises inverters 604-606, AND gates 611-616 and output terminals 621-626. Each of position signals BU, BW, and BV input to input terminals 601-603 is applied to an input terminal of an AND gate as illustrated in FIG. 22. When position signals BU, BW, and BV shown in FIG. 25A are applied, the commutation switching circuit 600 generates driving signals K1-K6 shown in FIG. 25B according to the logic circuit shown by FIG. 22. These driving signals K1-K6 are applied to the driving transistors 101-106 in the motor driving transistor circuit 100 as shown in FIG. 18 to rotate the motor 10.
FIGS. 26A-26C show the timing relationship between the output of the commutation switching circuit 600 and the U-phase output in a conventional motor driving circuit. The U-phase driving signals K1 and K2 generated by the commutation switching circuit 600 are respectively input to the driving transistors 101 and 104. In FIGS. 26A and 26C, when K1 is at logic "L", the current flows through the driving transistor 101 to generate a positive voltage at the U-phase. On the other hand, in FIGS. 26B and 26C, when K2 is at logic "H", the current flows through the driving transistor 102 to generate a negative voltage at the U-phase.
This circuit detects a current flowing through the motor 10 via the resistor 108. However, in the resistor 108, the base currents of the driving transistors 104-106 flow in addition to the current flowing through the motor 10. Therefore, it is impossible to detect a accurate current flowing only through the motor 10. Accordingly, it is inevitable to correct the terminal voltage according to the motor current. Further, it is impossible to detect accurately the position of the rotor since the errors generated in the terminal voltage compressing circuit 300 are added.
Furthermore, since the transistors 101-106 in the motor driving transistor circuit 100 are switched by the rectangular wave voltage applied to the motor 10 for commutation, a spike voltage shown in FIG. 27 is included in the output voltage. When the spike voltage is in the audible frequency band, it causes the audio noise.

Driving curcuit for sensorless brushless motor

Mitsubishi Electric Engineering Co., Ltd.


A method of manufacturing a bipolar junction transistor (BJT) array may include forming a substrate of doped silicon and forming a plurality of BJTs on the substrate. Each of the BJTs may have a first region and a second region sandwiching a base region vertically. The first region may be in contact with the substrate, where the BJTs are formed in a first row and a second row. The first row and the second row may each have BJTs separated from one another by a word line distance and the first row and second row may be separated by a bit line distance. A plurality of word line contacts may be formed laterally enclosing and electrically connected to each base region of the BJTs. The word line contacts may have a lateral thickness more than one half the word line distance and less than one half the bit line distance.

The present disclosure relates to resistive memory, and more specifically, to vertical bipolar junction transistors for accessing an array of resistive memory elements.
Resistive memory material may be used in resistive memory elements. Resistive memory material changes phase when electrical current is applied at levels suitable for implementation in integrated circuits. Different phases of resistive memory material may be characterized by different resistive properties, which may be used to indicate data, i.e., a logical "1" or "0."

Symmetrical bipolar junction transistor array

International Business Machines Corporation


The present disclosure relates to a surgical cannula with a removable seal at one end. The surgical cannula is a wide gauge surgical cannula, that allows materials and tools to be introduced into a body during a surgical procedure. The cannula includes a seal structure at one end, which may be attached to and detached from the cannula body as desired. The seal structure includes one or more valves that retain pressure within the cannula. The one or more valves are configured to allow a tool through the valve(s), while retaining pressure inside the cannula, so that surgical tools may be inserted through the cannula even when the seal structure is attached to an end of the cannula.

Surgical cannulas are generally well-known in the art of arthroscopic surgery. For example, various types of cannulas are used to control the inflow or outflow of fluids, to allow access for tools into the tissue, and for other functions. In some types of surgeries, a graft or other substrate material may be introduced into a surgical site. Additionally, many arthroscopic surgeries, such as joint surgeries, use pressurized irrigation fluid to keep tissue separated apart from other tissue. In particular, pressurized irrigation fluid may be used to aid in visualization of the surgical site as well as to prevent bleeding from vasculature surrounding the surgical cuts. Other types of surgeries, such as gastrointestinal procedures, use pressurized gas to provide access to and visualization of the surgical site.
Accordingly, there is a need in the art for cannulas that address the need to serve these several functions during an arthroscopic surgery.

Surgical cannula with removable pressure seal


The application provides a particle analyzer based on sheath flow impedance method comprising a flow cell and a counting circuit, wherein the flow cell includes a front chamber and a back chamber, the front chamber includes a particle suspension liquid inlet and a front sheath liquid inlet, the back chamber includes a back sheath liquid inlet and a waste liquid outlet, an aperture being provided between the front and back chambers and each of the front and back chambers being connected to the counting circuit via an electrode respectively. The particle analyzer further comprise a back sheath liquid isolating chamber, the back sheath liquid stored on the bottom of the back sheath liquid isolating chamber flowing into the back chamber automatically and continuously due to the liquid level difference between the liquid in the back sheath liquid isolating chamber and the liquid in the back chamber, or due to a combination of said liquid level difference and the interior negative pressure of the back chamber. The particle analyzer may further comprise a waste liquid isolating chamber, which causes isolation of the internal fluid passageway connecting the inlet and the outlet of the waste liquid isolating chamber by the interior air. Back-flow of the liquid specimen can be prevented during a detection process, noises can be mitigated effectively, the sensitivity for detection of particles can be improved, and introduction of electromagnetic noises to the flow cell from the back sheath liquid or the waste liquid can be avoided.

Techniques for detecting the number or the volume of particles by using the impedance of a sheath flow (known as "sheath flow impedance method") may be dated back to U.S. Pat. No. 3,793,587 and No. 3,810,010 in 1974. These patents involve some common elements, such as a flow cell including a front chamber and a back chamber, an aperture (or a small through hole), a sample tube, electrodes and a detection circuit. Here, the front and back chambers are connected via the aperture, with which the specimen tube is disposed coaxially. The outlet of the specimen tube is located at a position in the front chamber near the aperture, so as to introduce the particle suspension liquid to be detected (referred to as liquid specimen hereafter) into the flow cell. Each of the front and back chambers has a conductive particle free liquid source, hereafter referred to as front sheath flow and back sheath flow, respectively. The pressure of the front sheath flow is equal to the pressure of the liquid specimen at the outlet of the specimen tube; while the pressure of the back sheath flow may be much lower than the pressures of the former two.
In the counting circuit based on the sheath flow impedance, an electrode connected to the high-potential has to be placed in one of the front and back chambers, which is abbreviated as high-potential chamber; and a zero-potential electrode is placed in the other chamber, which is abbreviated as zero-potential chamber. To pass all the currents from the high-potential to the zero-potential through the aperture of the flow cell and ensure that interference will not be introduced or the sensitivity of the sensor will not be reduced due to the existence of other branch currents, it is preferable to isolate the high-potential chamber from the upstream of all liquid passages that supply conductive liquid to it, so as to avoid the possibility that branch currents are formed by connecting the upstream of these liquids to the zero-potential.
In U.S. Pat. No. 4,070,617 and No. 4,198,160, sheath liquid driving is implemented in the manner of driving by the liquid level difference. In U.S. Pat. No. 4,165,484, an exterior pressure source is introduced, in which a common air supply drives the sheath liquid in the storing chamber, and the liquid in the sheath liquid storing chamber is driven under the pressure to provide sheath liquid to the flow cell. To reduce the interference brought from the liquid storing chamber to the counting circuit, the inventors of U.S. Pat. No. 4,165,484 proposes a method of serially connecting a glass capillary tube within the sheath liquid supply passage, so as to increase the resistance of the liquid passage, and thus to achieve an effect of electromagnetic isolation. In this way, however, the liquid passage from the sheath liquid storing chamber to the flow cell plays a role of a conductive line unavoidably, thus introducing electromagnetic interfering signals into the flow cell. The signals will be superimposed on the impedance signals of the aperture, which makes it harder to identify signals. To decrease interferences, the glass capillary tube should be long and slim, which increases the operational risks. Meanwhile, to decrease interferences and avoid introducing additional electromagnetic interferences, electromagnetic valve, which is smaller and easily controllable, should be avoided to control the liquid passage. Furthermore, the driving pressure of the back sheath flow is larger in this method, thus causing increased consumption of liquid.
In U.S. Pat. No. 5,905,214, a positive pressure is applied and the driving force for ejecting the back sheath liquid into the back chamber is the positive pressure from the upstream chamber. To ensure that the positive pressure can be transmitted to the back chamber, the liquid passage along the way has to be sealed very nicely and a continuous liquid supply is a must. Consequently, it would be difficult to prevent exterior exoteric interfering signals from entering into the back chamber. In U.S. Pat. No. 6,909,269, the flow cell is placed within a special shielding box, which may attain shielding effect to some extent but cannot prevent occurrence of back-flow of the liquid specimen and generation of fake signals after the liquid specimen enters into the back chamber.

Particle analyzer based on sheath flow impedance method

Shenzhen Mindray Bio-Medical Electronics Co., Ltd.


A fitted bed sheet or mattress pad with elasticized head and foot panels comprising a first panel including a top portion and first and second side portions for covering the top and sides of the mattress. Elasticized head and foot panels are secured to the head and foot ends of the top portion with the head and foot panels defining a trapezoidal shape. The head and foot panels are comprised of a highly elasticized material with the design of the panels being such that it permits the bed clothing to accommodate various sizes of conventional innerspring mattresses or waterbed mattresses for any given size classification.

1. Field of the Invention
This invention relates to improved bed clothing such as bed sheets and mattress pads adapted to fit various sizes of conventional innerspring mattresses and waterbed mattresses for any given size classification.
2. Description of the Related Art
Many types of fitted bed sheets and mattress pads have been previously designed although the sheets and mattress pads are normally designed to fit a particular size mattress with the results being that a large number of the sheets and mattress pads must be manufactured and kept in inventory to accommodate the various sizes of mattresses. With the advent of the high profile mattress (extra depth mattress) and the waterbed mattress, a need has arisen for a product both in bed sheets and mattress pads which will accommodate the various sizes and shapes of mattresses.

Fitted bed sheet or mattress pad with elasticized head and foot panels


Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a charge preservation layer on the entire surface of the etching stop layer; depositing an insulating layer on the surface of the resulting structure; and forming an metallic interconnect on the insulating layer.

The use of plasma in semiconductor device fabrication provides directionality, low temperature, and processing convenience. Accordingly, plasma is typically used in etch and deposition processes for fabricating semiconductor devices. However, the plasma also introduces a potential for increased semiconductor damage due to surface charging of a semiconductor device. This surface charging during the plasma processing is often referred to as plasma charging damage. As the thickness of a gate oxide layer continue to decrease to improve device performance, the plasma charging damage is becoming a large concern because it can severely and directly degrade the electrical properties of the gate oxide layer. Especially, after the formation of a first metallic interconnect having the highest antenna ratio among metallic interconnects and in contact with a transistor, the probability of the occurrence of the plasma charging damage is getting greater. However, a conventional Pre-Metallic Dielectric (PMD) layer does not contain any material that can prevent the occurrence of the plasma charging damage.
Referring to FIG. 1, a conventional PMD layer including a nitride layer 11 as an etching stop layer, a BPSG layer 12, and an oxide layer 13 as a capping layer are placed on a substrate with at least one structure. A metallic interconnect 14 is placed on the PMD layer. A first Inter-Layer Dielectric (ILD) 15, a second insulating layer 16, a second metallic interconnect 17, and a second ILD 18 are sequentially and repeatedly placed on the device.
However, the nitride layer 11, the BPSG 12, and the oxide layer 13 have shortcomings such as poor charge preservation and are, therefore, unable to protect the semiconductor device from the plasma charging damage.

Devices and methods of preventing plasma charging damage in semiconductor devices


Embodiments of the claimed subject matter provide a method and apparatus coordinating downlink multipoint transmissions. One embodiment of the method includes transmitting, from a first base station, first information indicating a first constraint on a starting position for downlink data transmission by the first base station or one or more second base stations. This embodiment of the method also includes transmitting, from the first base station, second information that includes a bit. A combination of the bit and the first information indicates the starting position for the downlink data transmission.

This application relates generally to communication systems, and, more particularly, to wireless communication systems.
Wireless communication systems provide wireless connectivity to access terminals using a network of interconnected access nodes or base stations. Communication over the air interface between the access terminals and the base stations takes place according to various agreed-upon standards and/or protocols. For example, the Third Generation Partnership Project (3GPP, 3GPP2) has specified a set of standards for a packet-switched wireless communication system referred to as Long Term Evolution (LTE). The LTE standards support downlink transmission using orthogonal frequency division multiplexing (OFDM). Access terminals (such as base stations or eNodeBs) can concurrently communicate with multiple users over control and data channels formed by allocating symbols in different sets of non-overlapping Fourier-coefficients or sub-carriers. The LTE standards also support multiple-input/multiple-output (MIMO) communication over the air interface using multiple antennas deployed at transmitters and/or receivers. The carrier bandwidth supported by LTE is approximately 20 MHz, which can support a downlink peak data rate of approximately 100 Mbps and a peak data rate of the uplink of approximately 50 Mbps.
The LTE standards also support coordinated multipoint (CoMP) transmission techniques including dynamic point selection (DPS) or joint transmission (JT). Coordinated multipoint transmissions for user equipment are coordinated by the serving cell for the user equipment using information communicated between the serving cell and other neighboring cells that are participating in the coordinated transmission. The serving cell can then schedule downlink transmissions to user equipment, e.g., based on channel conditions between the user equipment, the serving cell, and the neighboring cells. In dynamic point selection, the serving cell can schedule transmissions by the neighboring cells for different subframes one cell at a time. In joint transmission, the serving cell schedules concurrent transmissions by multiple cells, which may or may not include the serving cell.

Control signaling for downlink coordinated multipoint wireless communication


To reduce the damage to the inner portion of a seat back caused by the mounting part of a headrest on the seat back. A vehicle seat (S) includes a headrest guide (6) having an insertion hole (6A) into which a headrest stay (12) of a headrest (S3) is inserted, a holder (8) mounted on a seat back frame (2) and configured to hold the headrest guide (6), and a cover member (10) configured to cover at least a part of the outer surfaces of the headrest guide (6) and the holder (8) and detachable from the seat back frame (2).

In a vehicle seat, a headrest with which an occupant's head is contacted is detachably mounted on a seat back that is a backrest surface. For example, in Patent Literature 1 below, a headrest is mounted on a seat back by a mechanism in which a holder holds a guide into which two stays hanging down from the headrest is inserted, the holder being fixed to a seat back frame forming the skeletal frame of the seat back.


A floral arranging vase cover provides enhanced decoration and for supporting floral arrangements within a vase. The floral arranging cover includes a circular ring, inner bands and outer bands. Preferably, the floral arranging cover includes four to twelve inner bands which are arcuate in shape and have first and second ends which rotatably affix to the circular ring. The outer bands are also arcuate in shape and include first and second ends which attach to the circular ring. Preferably, the outer bands project outwardly from the ring and are arranged in an overlapping manner. Moreover, the outer bands are preferably affixed to adjacent bands to prevent their rotation about the circular ring. The floral arranging cover is placed upon a vase with the circular ring substantially adjacent to the vases' rim. The inner bands project inwardly to form a grid-like structure having openings for floral and plant stems. The outer bands project outwardly from the vase to support the floral arranging cover upon a vase and provide enhance decoration for the entire assembly. In addition, decorative elements may be affixed to the outer band to provide still additional ornamentation.

The present invention relates generally to plant and floral arranging aids. More particularly, the present invention relates to a floral arranging aid for vases which provide enhanced ornamentation and support for flowers within a vase.
Various constructions have been utilized for supporting flowers and maintaining flowers erect in a vase. These constructions have primarily been grid-type structures which include a variety of apertures for placement of floral stems. A typical floral grid is circular and made of plastic and sized to cover the top surface of a vase. The circular end includes a plurality of circular or square holes for receipt of flower stems. The grid may be attached to the vase using an adhesive or tape. Unfortunately, these grids are typically sized to fit only one size of vase and do not provide any decorative enhancement for the floral arrangement.
An example of a grid floral-arranging aid is described in U.S. Pat. No. 5,758,452. The aid includes a circular body having a plurality of apertures for holding flower stems. In addition, the grid openings are coded for cross-referencing purposes and the aid includes a plurality of tabs which bend downwardly for engaging the sidewalls of a vase. Meanwhile, U.S. Pat. No. 5,477,637 also describes a grid-type structure for holding flower stems. The grid is circular and includes a plurality of openings. In addition the flower stems are tied at their bottom extremities in a way so as to make the bouquet appear larger than standard bouquets.
Unfortunately, the prior grid floral arranging aids suffer from numerous drawbacks. The grids are sized to cover only one size of vase opening. In addition, the floral arranging aids are particularly unsightly and do not provide for the addition of any ornamental features for further enhancing the beauty of a floral arrangement.
Thus, it would be highly desirable to provide a floral arranging device which is capable of mating to vases of various sizes.
It would also be desirable to provide for a floral arranging device which is highly decorative and pleasing to the eye.
In addition, it would be desirable for the floral arranging device to provide a structure for affixing additional ornamental elements.
Moreover, it would be advantageous to provide a floral arranging device that maintained the floral arrangement in a desired manner during floral removal from and reinsertion into a vase for the rapid replacement of water.