Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: a core layer having a first circuit wiring layer formed on one surface or both surfaces thereof; an insulating layer laminated, as at least one layer, on one surface or both surfaces of the core layer; and a second circuit wiring layer formed on one surface of the insulating layer, wherein a conductive core is included in upper and lower insulating layers contacting the second circuit wiring layer requiring an electromagnetic wave shielding, or the conductive core is included in the insulating layer or the core layer contacting the first circuit wiring layer requiring the electromagnetic wave shielding.

1. Technical Field
The present invention relates to a printed circuit board and a method of manufacturing the same, and more particularly, to a printed circuit board including a electromagnetic wave shielding structure and a method of manufacturing the same.
2. Description of the Related Art
A printed circuit board (PCB), which forms and prints line patterns on an electrical insulating board using a conductive material such as copper, indicates a board immediately before an electronic component is mounted thereon. That is, the PCB indicates a circuit board on which a mounted position of each electronic component is secured and a circuit wiring connecting electronic components to each other is printed on a flat plate surface and is fixed in order to densely mount many various kinds of electronic components on the flat plate.
Recently, in accordance with the development of an electronic industry, the use of a package in which memory chips are mounted on many electronic devices has rapidly increased. Therefore, in accordance with miniaturization, lightness, and multi-functionalization of an electronic product, thinness of an electronic product packaged has been required. As a result, the thinness or an increase in density of the printed circuit board which is one of important components has also been demanded.
Meanwhile, while a trend of slimness and lightness of a portable mobile and the electronic device for display has rapidly progressed, a transfer speed of signal between components in the device is speeded up, and the circuit board becomes a micro-circuit having high density, damage of electromagnetic interference (EMI) according to an electromagnetic wave noise occurring between circuits adjacent to each other has become increased.
In order to effectively shield the electromagnetic wave as described above, it is required to enclose the printed circuit board by a conductor film having excellent electrical conductivity to allow the electromagnetic wave occurring in the printed circuit board to be decreased through the conductor.
Therefore, the electromagnetic wave is shielded by attaching a metal thin film such aluminum foil or silver foil having excellent conductivity to the circuit board or uniformly applying a conductive paste which is manufactured by dispersing a conductive powder into a binder resin on the surface of the circuit board. Alternatively, a conductive adhesive sheet type product, or the like, in which the conductive paste is made in a sheet form and heated and attached may be applied.
In this connection, Korea Patent Laid-Open Publication No. 10-2001-0006198 suggests a board including a transmission line, a shield unit of shielding the transmission line which is arranged so as to enclose around the transmission line, and an insulating layer arranged between the transmission line and the shield unit.
However, the shield unit having the above-mentioned structure cannot but occupy one layer in an inner space of the board. Therefore, the number of layers of the board increases, such that the demand for the thinness of the board and the increase in density of the board is not met.

Printed circuit board and method of manufacturing the same


An API (Application Programming Interface) for an adaptive computing system (ACS) may be used to create a system for performing an application on different types of ACS platforms. The API may be used to generate a system object including a host and a number of nodes and channels. A system data structure is created which describes the nodes, which may be FPGA (Field Programmable Gate Array)-based ACS accelerator boards. The API may enable source-code porting and scaling from small research platforms to larger field-deployable platforms.

An adaptive computing system (ACS) is a system that can reconfigure its logic and/or data paths in response to dynamic application requirements. The system may include a number of connected adaptive computing boards, each board including a reconfigurable FPGA (Field Programmable Gate Array) integrated circuit.
Applications to be performed by ACS systems may be developed and implemented on different platforms. For example, many ACS applications require strict VME (Versa Module Europa) environments found in large, embedded systems, yet much of the algorithm mapping may be done in university research labs using PCI (Peripheral Component Interconnect)-based systems.
Replicating these VME environments in university labs may be prohibitively expensive because of the cost of chassis, single-board computers, and real-time software development tools. In addition there is a learning curve associated with programming and debugging embedded systems that make them a poor choice for an application development platform for graduate students. Conversely, allowing the university partners to develop their applications on commercial ACS boards in a PC environment may also be impractical because no path exists to transition to the deployed environment. Accordingly, it may be desirable to provide an open, distributed, and scalable ACS system architecture that includes an API (Application Programming Interface) which enables source-code porting and scaling from small research platforms to larger field-deployable systems.

System level applications of adaptive computing (SLAAC) technology


Method, apparatus, and computer readable medium for determining signal routing cost within an integrated circuit is described. In an example, the integrated circuit is divided into topology units and includes routing resources. A respective span is determined in terms of one or more of the topology units for each of the routing resources. A cost value is assigned to each of the routing resources using the respective span associated therewith. A routing resource is selected from the routing resources. At least one distance between the routing resource and at least one other of the routing resources is calculated. A future cost value for the at least one distance is computed using the cost value assigned to the routing resource.

A programmable logic device (PLD) is a digital circuit implementation platform that can be configured by the end user to implement a logic circuit of their choice. The two most common types of PLDs are field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Many PLD vendors provide computed-aided design tools to help their customers to implement logic designs in their PLDs. One type of PLD, the FPGA, is used as an example to illustrate the invention. It should be noted that, in addition to PLDS, the invention is applicable to other integrated circuit implementation technologies, for example, application specific integrated circuits (ASICs), mask-programmed gate arrays, and standard cell devices.
In a conventional architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources, which are comprised of metal wire segments and programmable routing switches, also referred to as programmable interconnection points (PIPs). These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into the FPGA. State-of-the art FPGAs contain tens of thousands of CLBs. For such devices, the task of establishing the required interconnections between the primitive cells inside a CLB and between the CLBs themselves becomes so onerous that it can only be accomplished within a reasonable amount of time with the assistance of computed-aided design tools. Accordingly, the manufacturers of FPGAs have developed place and route software tools which may be used by end customers to implement their respective designs in their FPGAs.
Routing tools are very important in determining the performance of a circuit implemented within an FPGA. If signals are not routed properly, an excessive amount of resources are used to carry signals. This could lead to a design with poor timing and power performance. Furthermore, routing tools are very difficult to develop and very time consuming to execute. Consequently, it is important to improve routing tools.

This patent is subject to a terminal disclaimer.

Integrated circuit signal routing using resource cost assignment and costing data


The present invention is directed to a wheel end assembly having a high temperature warning system for giving a warning in the event that the temperature in the assembly reaches a predetermined value such as caused by hub bearing failure or a brake related failure. In one embodiment the system may be a stand-alone system for installation on any vehicle such as a trailer. In another embodiment the system may be combined with an automatic tire inflation system.

In the event of a wheel end assembly hearing failure or brake related failure on a vehicle such as a tractor trailer, the temperature in the assembly and axle spindle area can reach a temperature to where the tires or lubricant may ignite causing the vehicle to burn or the wheel to lock up. It is also the possibility, due to the intense heat caused by any failure that the wheel can detach from the axle.

Wheel end assembly high-temperature warning system


There is dsiclosed a flame retardant resin composition comprising the following components (A), (B), (C), (D), (E) and (F), wherein 1-10 parts by weight of (C), 2-10 parts by weight of (D), 0.05-2 parts by weight of (E) and 0.01-10 parts by weight of (F) are contained per 100 parts by weight of a resin whose weight ratio of (A)/(B) is 75/25-90/10.. (A) a polycarbonate resin whose viscosity-average molecular weight is 16,000-29,000, PA1 (B) a polyalkylene terephthalate resin, PA1 (C) a copolymer containing a rubbery polymer and at least one selected from the group consisting of aromatic vinyl monomers, vinyl cyanide monomers, acrylic acid, acrylic esters, methacrylic acid, methacrylic esters and maleimide-type monomers as components, PA1 (D) an organic phosphorus-type flame retardant, PA1 (E) a fluorocarbon-type resin, and PA1 (F) an epoxy compound not containing halogens.. The flame retardant resin composition is halogen-free and possesses well-balanced properties of flame retardancy, impact strength, heat resistance, moldability, chemical resistance and heat-induced discoloration resistance, and is improved in silver streaks formation.

Of molded articles, electric and electronic parts used in an OA (Office Automation machines)-field for some specific uses are required to be of resin compositions excelled in physical properties such as flame retardancy, impact strength and heat resistance. For example, required are those not less than 40 kg-cm/cm in notched Izod impact strength and heat resistance of not less than 100.degree. C. in HDT (heat distortion temperature). Besides those properties, chemical resistance and moldability are further required. As such resin compositions, polycarbonate-type resins or ABS resins are being used widely.
In recent years, especially with resins used as materials of electric or electronic parts, are required to be safe to fire, hence the material resins are often required to have a high degree of flame retardancy to pass UL-94 (U.S. Underwriters Laboratory Standard) V-0 and, therefore, various flame retardants have been developed and studied.
For the impartation of such a high degree of flame retardancy to a resin composition, generally used is a halogen-type compound as a flame retardant, if necessary, in combination with a flame retardant auxiliary such as antimony trioxide. Halogen-type compounds with their high flame retardant effect, however, have such defects as free halogen gases or halogen compounds resulting from the decomposition of the halogen-type compounds during resin processing is likely to cause corrosion of an extruder cylinder or die surface or corrosion of metal portions of electric or electronic parts, which possibly causes contact failure or poor conduction. The gases resulting from the decomposition of the halogen-type compounds include poisonous ones in extremely minute amounts, Hence, strongly desired is development of a flame retardant resin composition not containing even traces of halogen-type compounds.
As one of such flame retardants, a kind of phosphorus-type compounds is being studied in good earnest with regard to their application possibilities. Generally, however, the flame-retarding effect of the phosphorus-type compounds is lower than that of halogen-type ones, hence addition of a greater amount thereof is required if a high degree of flame retardancy is needed. And this results in lowering of physical properties such as impact strength and heat resistance and it comes to be extremely difficult to keep them sufficiently high together with flame retardancy.
Various studies have been made to date for solving such problems and resin compositions comprising polycarbonate resins, polyalkylene terephthalate resins, graft copolymers, phosphorus-type compounds and fluorocarbon-type resins with or without limitations of their blending ratios are disclosed in, for example, Japanese Laid-open Patent Publication No. 6-192553 and Japanese Patent Publication No. 6-242055.
The resin compositions mixed with such phosphorus-type flame retardants, unlike those mixed with halogen-type flame retardants, have particular phenomena caused by the decomposition of the phosphorus-type flame retardant during resin processing such as yellowing of molded articles and easy formation of silver streaks in the surface thereof. As to yellowing, in particular, there is a further problem, among others, of increased yellowing of the molded articles when they are used under high-temperature conditions.
Of the required physical properties, especially important is the chemical resistance, which is often required to be much higher with spread of uses for such electric parts in recent years.
An extensive series of studies have been made for solving of such problems and with regard to the improvement of resistance to heat-induced discoloration, flame retardant resin compositions admixed with specific organic phosphoric diesters and alkali metal salts thereof as additives for polycarbonate resins are disclosed in, for example, Japanese Laid-open Patent Publication No. 5-9371 and Japanese Laid-open Patent Publication No. 6-207088. Although this method is effective against discoloration of resin compositions dwelling in an injection molding machine, organic phosphoric esters and alkali metal salts thereof accelerate thermal decomposition of polycarbonate resin which enhances silver streaks formation. In Japanese Laid-open Patent Publication No. 6-228426, Japanese Laid-open Patent Publication No. 5-1079 and Japanese Laid-open Patent Publication No. 5-92986 there is disclosed a method for decreasing the degree of discoloration of molded articles by the use of specific phosphoric esters as a phosphorus-type flame retardant. The disclosed method, however, may not be sufficiently effective or, worse, even fail to improve chemical resistance or to prevent silver streaks formation.
For the simultaneous improvement of effect for increasing resistance to heat-induced discoloration and decreasing silver streaks formation, a method of adding organic phosphorus-type compounds and melamine cyanurates to polyamide resins is disclosed in Japanese Laid-open Patent Publication No. 6-145508. The melamine cyanurates, however, accelerate foaming of polycarbonate-type resin and cause increased dripping, hence this method is difficult to apply to polycarbonate-type resin compositions.
Meanwhile, as a method of improving the chemical resistance of polycarbonate resins, there is disclosed in, for example, Japanese Published Patent Publication No. 5-87540, a method of adding graft copolymers and high-density polyethylene resins to a resin composition of polycarbonate resins and thermoplastic polyester resins, but there arises a problem of the resin composition flame retardancy being deteriorated by the high-density polyethylene resins as it is applied to a flame retardant recipe. In Japanese Laid-open Patent Publication No. 5-21754, there is a description about a method of improving the chemical resistance of flame retardant polycarbonate resin compositions using halogenated bisphenol-type epoxy resins, but no reference is made to resistance to heat-induced discoloration or silver streaks formation, and the problems caused by halogen-type compounds are still involved.
Although, as mentioned above, there are proposed various methods for improving resistance to heat-induced discoloration as well as for prevention of silver streaks formation, there are still included problems of the intended improving effect being insufficient or of causing deterioration of the innate excellent physical properties of the resin compositions. Under such conditions, there have been awaited development of halogen-free resin compositions excelled in physical properties such as flame retardancy, impact strength, heat resistance and moldability and, more important, also excelled in chemical resistance and resistance to heat-induced discoloration and silver streaks formation.
The present invention is aimed at providing a halogen-free flame retardant resin composition excelled in physical properties such as flame retardancy, impact strength, heat resistance and moldability and, more important, also excelled in chemical resistance and resistance to heat-induced discoloration and silver streaks formation.
The present inventors made extensive and intensive studies for solving the aforementioned problems and to their astonishment discovered that a flame retardant resin composition satisfying the aforementioned properties was obtainable by blending in specific quantities a polycarbonate resin, a polyalkylene terephthalate resin in specific molecular weight, a specific copolymer, an organic phosphorus-type flame retardant and an epoxy compound not containing halogens, and thus could arrive at the present invention.

Kanegafuchi Kagaku Kogyo Kabushiki Kaisha


A strap joint rotator is for use in a strapping machine of the type for feeding a strapping material around a load, positioning, tensioning and sealing the strapping material around the load. The strap joint rotator includes a driven wheel having an axis of rotation generally perpendicular to the sealed strap loop, a first drive operably connected to the driven wheel for rotating the driven wheel and a pinch wheel having an axis of rotation parallel to and spaced from the driven wheel. The driven wheel and pinch wheel are moveable toward one another and engageable with one another and moveable away from and disengaged from one another. A second drive is operably connected to the driven wheel and the pinch wheel for moving the driven wheel and pinch wheel parallel to their axes of rotation into the strap loop plane and out of the strap loop plane. The driven wheel and pinch wheel are moved into the strap loop plane and the driven wheel and pinch wheel are engaged with one another to pinch the strap therebetween. The driven wheel is actuated to rotate the strap loop around the load.

The present invention is directed to a strap joint rotator. More particularly, the present invention is directed to a strap joint rotator used with a strapping machine for compressible materials.
Strapping machines are well known in the art for securing straps around loads. In one configuration a strapping machine is used to strap compressible loads such as baled cotton or other textile materials. Often, the bales are large, so, in a typical arrangement, multiple straps are fed, tensioned and sealed around the load to create the baled load. Typically, such bales are strapped with plastic strap material.
The strapping machine that is used to create the bale includes several separate but interdependent feed and strapping heads, strap chutes and other components for positioning the multiple straps around the load. Each strapping unit operates in conjunction with each other unit so that the strapping occurs simultaneously at each of the several units. In this manner, the strapping operation is carried out in an efficient and time effective operational mode.
A typical baling and strapping machine is a side seal machine, that is, the seal is made at a strap section along a side of the chute (as opposed to at a section of the strap at the bottom or top of the chute). Because the material has to be compressed to effectively strap the load, the sides (or front and rear) and bottom portions of the strap chute are relatively conventional, but the top portion of the chute is within a movable platen that contacts and compresses the load. The strap chute sections are formed within the platen.
When the compression plate or platen is released, the material expands to "fill" the loop created by the sealed strap. As such, the expanding material creates a stress (a strain) in the strap. This is particularly so in that the direction of expansion of the load is in the direction of the strap at the seal. This results in higher stresses at the seal.
Moreover, the side of the bale is often that portion of the bale that is the "bottom" of the load for purposes of shipping, handling and storage. As such, given that the seal is along the side, the seal may be at that portion of the strap that is in contact with the ground or other object and can possibly be damaged.
Accordingly, there is a need for a device to reposition a strap on a load. Desirably, such a device repositions the strap to relocate the seal relative to the load. More desirably, such a device repositions the strap without twisting or otherwise adversely affecting the load.


As a switch circuit SW1 is incorporated in an integrated circuit, the number of IC terminals is proportionately reducible. On receiving a mute input signal Min, a mute circuit 13 generates a mute control signal M1 and subsequently a mute control signal M2 later than M1. On receiving the mute control signal M1, the switch circuit SW1 grounds the signal line of an audio output signal A, whereas on receiving the mute control signal M2, a switch circuit SW2 cuts the signal line of an audio input signal I later. A muting function can thus be fulfilled stably.

The present invention relates generally to audio signal amplifier circuits and more particularly to audio signal amplifier circuits used for audio signal processing circuits in, for instance, audio equipment, televisions and VTRs, and to an audio signal amplifier circuit in the form of a one-chip integrated circuit having a muting function.
In an audio signal amplifier circuit that employs transistors and the like, unpleasant sound like so-called pop sound ensues when a power switch is turned on and if the worst comes to the worst, a speaker connected to a power amplifier may be damaged. It is therefore the practice generally followed to insert a mute circuit in order to compulsorily cut or ground a path for an audio signal until the power amplifier and the like arrive at a steady stable state.
Referring to a block diagram of FIG. 2, the construction and operation of a specific audio signal amplifier circuit having such a mute circuit will be described.
Numeral 1 denotes an audio signal amplifier circuit which is normally an integrated circuit and comprises an amplifier 2, a mute circuit 3, a switch circuit SW2 and the like. On receiving an audio input signal I, the amplifier 2 amplifies the signal and outputs it as an audio output signal A. The mute circuit 3 receives a mute input signal Min generated (a generator circuit is not shown) to suppress an audio signal, depending on the condition of a power supply circuit or the switch input, and produces a mute control signal M accordingly. The mute control signal M is supplied to an IC terminal 1a and the switch circuit SW2. On receiving the mute control signal M, the switch circuit SW2 cuts the signal line of the audio input signal I. Moreover, a switch circuit SW1 provided outside the integrated circuit grounds the signal line of the audio output signal A on receiving the mute control signal M via the terminal 1a. In this way, a muting function is fulfilled by compulsorily cutting both the input and output sides of the audio signal or reducing them to a reference potential when the conventional audio signal amplifier circuit receives the mute input signal Min.
In the conventional audio signal amplifier circuit, the switch circuit SW1 has thus been arranged as a discrete part but not incorporated in the audio signal amplifier circuit in the form of an integrated circuit. For this reason, the mute control signal M has to be sent to the switch circuit SW1 and one IC terminal is specifically allotted for the purpose.
However, any increase in the number of IC terminals is undesirable because it is against a demand for reducing the IC size and the apparatus itself as well.
Since one mute control signal is used simultaneously to switch two of the switch circuits SW1, SW2, in the case of the operating times of the switch circuits being varied, the switch circuit SW1 of the output side may fail to suppress the noise produced by switching of the switch circuit SW2 of the input side. Accordingly, the muting function is not guaranteed to perform in stability. In other words, the problem is that more man-hours are needed for adjustment and so forth.


The high-density connector for high-speed transmission comprises a female connector having a connector body formed with a plurality of contact accommodating concave portions and a plurality of female contacts, and a male connector having a connector body and a plurality of male contacts. The female contacts are arranged in zigzag in a plurality of rows such that adjacent female contacts in a front-back direction are diagonally positioned to each other. Contact portions of the male contacts are arranged in zigzag in a plurality of rows corresponding to the arrangement of the female contacts. Among the rows of the female contacts, two adjacent rows in the front-back direction are rows of a pair of signal line contacts, and one row on either side in the front-back direction of the pair of signal line contacts is a row of a ground contact.

As a high-density connector that makes a connection between printed circuit boards as electrical components, there is conventionally known a high-density connector disclosed in Patent Document 1. In the high-density connector disclosed in Patent Document 1, signal line contacts are mutually arranged in zigzag in order to enable high-speed transmission of a signal and high-density connection of signal lines.    Patent Document 1: Japanese Patent No. 3413080

High-density connector for high-speed transmission


A particle beam irradiation system which can increase an availability factor. An ion beam extracted from one proton beam linac is bent at 90 degrees by a switching magnet and is introduced to RI production equipment through a beam line. In the RI production equipment, a RI is produced using the introduced ion beam. An ion beam extracted from the other proton beam linac is bent at 90 degrees by the switching magnet and is introduced to a synchrotron through a beam line. The ion beam extracted from the synchrotron is irradiated to a patient from irradiation equipment. If one proton beam linac comes into an abnormal state, the one proton beam linac is stopped in operation and checked. During the check, the ion beam extracted from the other proton beam linac is selectively introduced to the RI production equipment and the synchrotron by the switching magnet.

1. Field of the Invention
The present invention relates to a particle beam irradiation system. More particularly, the present invention relates to a particle beam irradiation system suitably used in not only inspection employing equipment of Positron Emission Tomography (hereinafter abbreviated to "PET") for producing a radioactive isotope (RI), e.g., fluorine 18, which is employed in a radioactive drug (hereinafter referred to as a "PET drug") and applied to a patient (subject) going to take the inspection, but also in treatment of cancers.
2. Description of the Related Art
As known in the art, proton-beam cancer treatment equipment used for treatment of cancers employs an ion beam accelerating system including a linear accelerator (linac) having an acceleration capability in the range of several to 10 MeV as a beam introducing unit and a synchrotron, or an ion beam accelerating system including a cyclotron. On the other hand, in equipment for producing the PET drug, a cyclotron (or a linear accelerator) having an acceleration capability in the range of 7 to several 10's MeV is employed to accelerate a proton beam and irradiate the accelerated beam against a target, thereby producing the radioactive isotope capable of radiating positrons.
Hitherto, a facility employing the proton-beam cancer treatment equipment and a facility employing the PET drug production equipment have been separately constructed corresponding to the fact that application fields of those equipments have been separated into treatment and diagnosis of cancers. With recent widespread use of the PET equipment and the proton-beam cancer treatment equipment, however, a demand has increased for a treatment plan capable of diagnosing the treatment effect with higher accuracy and further increasing the treatment effect. Such a demand has brought about a tendency to construct the proton-beam cancer treatment equipment and the PET equipment in combined layout. Because the half-life period of a RI (e.g., fluorine 18) used in the PET drug is very short, the PET equipment is required to include the PET drug production equipment, i.e., RI production equipment.
Patent Document 1; JP,A 2001-85200 discloses examples of combined layout of the proton-beam cancer treatment equipment and the RI production equipment. According to Patent Document 1, in a treatment system including a linear accelerator and a synchrotron, an ion beam extracted from the linear accelerator is introduced to the RI production equipment, thereby producing a RI. More specifically, the treatment systems disclosed in Patent Document 1 comprise the linear accelerator, the RI production equipment, and the synchrotron. The treatment system further comprises a switching magnet serving as a beam path switching unit and disposed downstream of the linear accelerator. The switching magnet introduces the ion beam extracted from the linear accelerator to the synchrotron or the RI production equipment. When the ion beam is irradiated to a patient, the ion beam extracted from the linear accelerator is introduced to the synchrotron by the switching magnet. The ion beam is accelerated in the synchrotron so as to have a preset level of energy and then irradiated to the patient. When the RI is produced, the ion beam extracted from the linear accelerator is introduced to the RI production equipment by the switching magnet and then irradiated to a target in the RI production equipment.
In a particle beam irradiation system disclosed in the above-cited Patent Document 1, the ion beam extracted from the linear accelerator is introduced to the synchrotron or the RI production equipment with the switching operation of the switching magnet.


A system and method for accelerating customer sales transactions in a retail store. A customer checkout accelerator provides a customer user interface to initiate a request for a preapproval amount for a sales transaction before reaching the point of sale terminal for completion of the purchase transaction. A card reader integrated into the customer checkout accelerator reads a customer payment card number when the payment card is swiped through the reader. A customer checkout accelerator server module resident on a store controller server determines a preapproval amount for the sales transaction and transmits the request to an external card services system for payment approval. The customer checkout accelerator also provides the ability to purchase additional promotional items in the checkout lane with this process integrated into the payment preapproval process. Once payment approval is obtained from the external card services system, an entry is placed in a preapproval database associated with the customer checkout accelerator server module on the store controller server. The server module forwards the approval notification to the point of sales terminal where it is placed in a preapproval cache for use in completing the actual sale transaction.

Merchants are continuously looking for ways to speed up the checkout process in retail establishments. A simple saving of a few seconds for each transaction can result in major savings when the seconds are applied to the hundreds or thousands of checkout lanes that may exist across all the retail stores of an enterprise.
The problem that exists today is that the checkout process is very heavily loaded on the back-end, specifically, the payment side of the sales transaction. Over the years, improvements have been made in the front-end of the sales process with the innovation of scanners, etc., but there is still much room for improvement in the payment area of the sales process.
In retailing technology, there are now many technology innovations that can enhance the customer checkout process. These include touch screen displays, Java-based graphical terminal sales applications, etc. Java-based graphical terminal sales applications include a Java-based customer graphical user interface (GUI) that is basically a read-only device used to display details of a sales transaction to the customer as it is occurring in real time, as well as optionally displaying advertising data to the customer. In addition, there is currently an increasing trend in the use of customer loyalty cards. There is also a further technology trend to combine the multiple loyalty cards with a credit card, onto a smart card. Versions of the "combination-loyalty cards" are already in use in several areas of the country.
There is a need for a system to enhance the payment processing in retail stores. Such a system will reduce the amount of time it takes to process a retail sales transaction. Such a solution can be taking the existing state-of-the-art technologies, (e.g., touch screen, smart cards, Java-based applications, etc.) and combining them into an application and system that reduces the amount of time it takes to complete each retail transaction.

International Business Machines Corporation


A system for detecting a mismatch between how a motor drive is connected electrically and how it is configured for operation is disclosed. The motor drive may either be connected in a stand-alone mode to control operation of a motor from an AC source without connection to another motor drive or be connected electrically to other motor drives, for example, in a paralleled mode, shared DC bus mode, or a combination thereof. A parameter identifies the expected electrical configuration of the motor drive. The power transferred to the DC bus is compared to the power transferred from the DC bus in the motor drive. If the difference between the power transferred to the DC bus and the power transferred from the DC bus exceeds a predetermined threshold, the motor drive detects the mismatch between how a motor drive is connected electrically and how it is configured for operation.

The subject matter disclosed herein relates generally to a system for detecting misconfiguration of a motor drive and, more specifically, to detecting that the selected operating mode of the motor drive does not match the wiring to the motor drive.
As is known to those skilled in the art, motor drives are used to convert a fixed voltage input into a variable amplitude and variable frequency output to control operation of a motor. The voltage input may be a single phase or three phase alternating current (AC) voltage. The motor drive typically converts the AC voltage into a direct current (DC) voltage present on a DC bus and subsequently converts the DC voltage into the variable amplitude and variable frequency output voltage. Conversion of the AC voltage to the DC voltage is performed by a converter and conversion of the DC voltage to the variable amplitude and variable frequency output voltage is performed by an inverter.
It is also known that motor drives or motor drive systems may be arranged in many different configurations. In one application, a single motor may be controlled by a single motor drive in a stand-alone configuration. In other applications, multiple motors may require control. Although individual drives may still be connected in a stand-alone configuration to control multiple motors, the motor drives may also be configured such that the AC inputs and/or the DC busses of the motor drives are connected in a shared AC, shared DC, or shared AC/DC configuration. According to still another option, a first motor may have a drive including a converter having a sufficient power rating to provide power to multiple motors. Each additional motor may have a motor drive with an equal or lower power rating connected in a shared DC bus configuration such that the additional motor drives receive power from the first motor drive. Although the motor drives or motor drive systems may have many different configurations, it is commercially advantageous to provide a single device capable of being configured to operate in each of the configurations.
A motor drive capable of being configured to operate in the various configurations includes terminals providing electrical connections to the converter, DC bus, and inverter within the device. Electrical conductors are connected between the terminals and a power source, another DC bus, or a motor according to the application requirements. In addition, the device includes one or more parameters corresponding to the configuration. A single parameter may be set to identify an operation mode, which, in turn, may be used to set additional parameters. Optionally, multiple parameters may be individually adjusted to configure the device. The parameters may configure, for example, overload warning and/or fault levels. If the parameters are not properly configured, the drive may be subject to alarms and/or faults occurring at levels inconsistent with the wiring or the drive may post alarms and/or faults unrelated to the real problem, namely that the parameters are not configured according to how the drive is wired.
Thus, it would be desirable to provide a system for detecting a difference between the configuration of the parameters of a motor drive and the configuration of the wiring connected to the motor drive.

Method and apparatus for detection of drive misconfiguration in a multi-axis configuration


There is provided a fly sewing machine. A fly supply unit is configured to supply flies to a transfer passage. A fly transfer unit is configured to transfer and send the fly supplied by the fly supply unit toward the downstream side thereof. A chain feed unit is configured to feed a slide fastener chain onto the flies sent by the fly transfer unit. An auxiliary conveyance unit is configured to press the flies and the slide fastener chain which are overlapped by the chain feed unit from above or below, and to send the flies and the slide fastener chain toward the downstream side thereof. A sewing machine part is configured to stitch together the flies and the slide fastener chain sent by the auxiliary conveyance unit.

As is known in the related art, a fly sewing machine includes a fly supply unit which supplies flies from the upstream side along a fly transfer passage which is provided on a stand, a fly feed unit which sequentially transfers the flies supplied by the fly supply unit, a transfer speed-adjusting part which sends the flies transferred by the fly transfer unit to a sewing machine part in the downstream side at required timing, and a chain feed unit provided between the transfer speed-adjusting part, the chain feed unit sending a continuous slide fastener chain to the sewing machine part in synchronization with the sewing speed of the sewing machine part (e.g., refer to Patent Document 1).


An electronic network filter for classified partitioning in an ATM network. The filter has a classified network buffer for identifying whether data is classified or unclassified to define invalid and valid data packets. Invalid data packets are dropped from the classified network buffer and valid data packets are sent to an unclassified network for testing without interrupting the operation of the classified network. In one embodiment, the classified network buffer is programmable to adapt to the continually changing requirements of classified networks.

The Broadband Integrated Services Digital Network (BISDN) is serviced by Asynchronous Transfer mode (ATM) switching networks and is used in a variety of applications, which apply to both classified and unclassified ATM networks. Some applications, such as testing of software developments, require the connection of networks having different classification levels. Current requirements for connecting networks having differing classifications, dictated by the National Industrial Security Program Operating Manual (formerly the Department of Defense Industrial Security Manual for Safeguarding Classified Information), include the need to re-certify security on the network for any software changes. However, the extensive testing required for a developmental test would interrupt the network service. Additionally, the testing procedure may compromise the security of a classified network. These are unacceptable consequences of testing software updates for classified networks.
There is a need for a secure method of changing and/or testing software changes on an electronic network, and particularly on a classified network that does not interfere with the operation of the network.

Electronic network filter for classified partitioning


Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

Unlike carbon nanotubes, nanostructures of germanium, a group IV semiconductor, have not been fully explored. Germanium and associated compounds at nanoscale are promising candidates for future nanoelectronics based technologies, e.g., nanotube metal oxide semiconductor field effect transistor (MOSFET) devices, which can extend the device scaling roadmap while maintaining good short channel effects and providing competitive drive current.
Techniques for forming nanotubes from a thin solid film of material have been proposed. See, for example, Schmidt et al., "Nanotechnology: Thin solid films roll up into nanotubes," Nature 410, 168 (March 2001) which describes a process by which films that are released from a substrate roll up into the shape of a nanotube. It is however difficult to achieve nanotubes with consistent dimensions using this type of process, and the process is not efficient enough for large-scale production.
Therefore, improved techniques for producing nanostructured materials would be desirable.


A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device containing non-volatile memory transistors.
2. Description of the Related Art
A representative memory cell used in a non-volatile semiconductor memory device such as a NAND flash memory is described in a document 1 (R. Shirota).
In the document 1, the details of the development of products of 256-Mbit NAND flash memories using an STI (Shallow Trench Isolation) structure, particularly, for element isolation is described.
The memory cell unit described in the document 1 has a structure in which selection transistors are arranged on both sides of a plurality of series-connected memory cell transistors. The plurality of memory cell transistors are formed in respective element active regions. The element active regions are separated by element isolation regions such as STI regions and the element active regions and STI regions are formed to extend in parallel so as to configure a memory cell array.
Part of the floating gate layer of the memory cell transistor is formed to cover the STI region. The volume of the covering part contributes to an increase in the ratio of the capacitance between the floating gate layer and the channel region to the capacitance between the floating gate layer and the control gate layer, that is, a so-called "coupling ratio".
In order to form the above memory cell transistor, it is necessary to form an extremely narrow slit-form pattern or so-called "slits" in the conductor layer used as part of the floating gate layer. FIG. 28 shows a step in which slits 103 are formed.
As shown in FIG. 28, conductive layers 104 are conductive material layers used as parts of the floating gate layers of memory cell transistors and the gates of selection transistors. Each of the slits 103 is formed in parallel with the STI region in a portion of the conductive layer 104 which lies on the STI region. The width of the slit is smaller than that of the STI region. By forming the slits 103 in the conductive layers 104, it becomes possible to separate the floating gate layers for the respective memory cell transistors.
In a normal NAND flash memory, memory cells are miniaturized by serially connecting a plurality of memory cell transistors and reducing the number of contacts between bit lines and memory cell units.
However, as shown in FIG. 29, if the number of memory cell transistors is reduced to as a small number as one or two, the distance DSG-SG between the gates of the selection transistors is relatively narrowed. If the distance DSG-SG is relatively narrowed, it becomes difficult to form the slits 103 in the conductive layers 104.
According to the document 1, it is described that the process of forming a region which is narrower than a region patterned by lithography can be realized by so-called spacer processing.
However, if the distance DSG-SG is narrowed, it becomes difficult to form the slit 103 having width sufficiently larger than the width of the element isolation region required in the memory cell unit when taking the processing conversion difference or the like into consideration. Further, when the width of the STI region and the width of the element activation region AA are determined based on the minimum processing dimension, it is difficult to form the slits 103 by use of a patterning process by exposure.
A case wherein the number of memory cell transistors in the memory cell unit is reduced is described in a document 2 (K. Imamiya, et al.), document 3 (Jpn. Pat. Appln. KOKAI Publication No. 2000-149581 (Sakui, et al.) and document 4 (G. Tao, et al.), for example.
In the document 2, for example, utilization of a memory cell transistor is reported when one memory cell transistor is provided. It is an EEPROM using a so-called three-transistor cell unit. In such a flash memory, the process for miniaturizing the same tends to be influenced by the above-described problems.
Therefore, as described in a document 5 (S. Aritome, et al.), a method of forming a floating gate layer in self-alignment with an STI region is proposed.
However, as described in the document 5, if the floating gate layer is formed in self-alignment with the STI region, portions used as parts of the gate layers of the selection transistors may be separated for each selection transistor like the portions used as the floating gates of the memory cell transistors.
(Reference Documents)
1. R. Shirota, "A Review of 256 Mbit NAND Flash Memories and NAND Flash Future Trend", Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2000 pp 22-31.
2. K. Imamiya, et al., "32 kbyte three-transistor flash for embedded applications using 0.4 μm NAND flash technology", Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2000 pp 78-80.
3. Jpn. Pat. Appln. KOKAI Publication No. 2000-149581. (U.S. Pat. No. 6,307,807 B1.)
4. G. Tao, et al., "Reliability aspect of embedded floating-gate non-volatile memories with uniform channel FN tunneling for both program", Non-Volatile Semiconductor Memory Workshop (=NVSMW) 2001 pp 130-132.
5. S. Aritome, et al., "A 0.67 μm 2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs" IEDM (1994) pp 61-64.


A nonvolatile ferroelectric memory device comprises a cell array block, a sense amplifier unit, a main amplifier unit and a data bus unit. The ferroelectric sense amplifier effectively senses and amplifies cell data having a small voltage difference applied to a main bit line, thereby improving operation characteristics in a low voltage. Also, a sensing voltage of the main bit line is lowered, thereby reducing a cross talk noise effect between main bit lines.

1. Field of the Invention
The present invention generally relates to a sense amplifier of a nonvolatile ferroelectric memory device, and more specifically, to a ferroelectric sense amplifier for effectively sensing and amplifying cell data having a small voltage difference applied to a main bit line, thereby improving operation characteristics in a low voltage.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter referred to as 'FeRAM') has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter referred to as 'DRAM') and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FeRAM are disclosed in Korean Patent Application No. 1999-14400 or a patent by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
However, as the operating voltage of the FeRAM becomes lower and its power consumption also becomes lower, a cell sensing voltage is reduced, which results in difficulty in embodiment of rapid operation speed. As a result, a change is required in a method for sensing data. Additionally, as the structure of cell arrays becomes diverse, it also requires diverse methods for sensing data.


A semiconductor wafer carrier fork cover to prevent damage to prevent breakage of the semiconductor wafer carrier forks mounted on a robotic semiconductor wafer transfer system during preventative maintenance procedures is described. A semiconductor wafer carrier fork cover has a lower support unit. The lower support unit will fit onto the base of a robotic semiconductor wafer transfer system. An upper covering unit is integrally attached to the lower support unit and will shield the semiconductor wafer carrier forks during preventive maintenance procedures.

1. Field of the Invention
This invention relates to robotic semiconductor wafer transfer system used in the moving of semiconductor wafers between a wafer cassette to a wafer boat within a vertical furnace and more particularly and guards and shields to protect components of the semiconductor wafer transfer system during preventive maintenance procedures.
2. Description of Related Art
Referring to FIG. 1, a robotic wafer transfer system 5, similar to that described in U.S. Pat. No. 5,380,137 (Wada), will pick wafers W from a wafer cassette 15 and place them in a wafer boat 20. The wafer boat 20 is housed within a vertical oven (not shown). The vertical oven will be sealed and a step of the semiconductor process such as chemical vapor deposition will be performed on the semiconductor wafers. At the completion of the step of the process involving the vertical oven, the wafers W are removed from the wafer boat 20 and returned to the wafer cassette 15.
The semiconductor wafers W are supported on the semiconductor wafer carrier forks 10. These semiconductor wafer carrier forks 10 are manufactured of a ceramic and contain an electro-optical sensor. The design of the semiconductor wafer carrier forks 10 coupled with the electro-optical form a unit that is extremely fragile.
Preventive maintenance to repair or replace components of the vertical oven and robotic wafer transfer system and other machinery involved in the semiconductor process requires the disassembly of the subunits of the these systems. As the subunits are disassembled, parts such as screws, nuts, or bolts may dropped. If the work area is above the wafer carrier forks 10, they may be broken or damaged necessitating replacement.
U.S. Pat. No. 4,785,962 (Toshima) describes a slit valve for sealing a vacuum chamber within the semiconductor wafer process and shows a robotic transfer system for conveying semiconductor wafer to the vacuum chamber.

Chartered Semiconductor Manufacturing Ltd.


The present invention describes an apparatus and teaches a method for removing particulate matter from a plurality of vessels. Examples of these vessels include aquariums, spas, fountains and pools. An ordinary hand held power drill motor is connected via a drill motor pump to a pick-up head containing a pair of hoses. Upon activation, a first hose applies suction to the pick-up head drawing both water and particulate into a chamber. The water continues through to a pump mounted in a housing, through the pump and out the discharge hose while the particulate is trapped within the chamber by a filter for later removal.

Ponds, pools, spas (or the more modern term "hot tubs") and aquariums have been in use for millennia. From the earliest recorded history to the present, humans have enjoyed the presence of water and the environments that are associated with water. Vessels of varying size from very small to very large have been used for a wide range of aesthetic and utilitarian purposes.
One problem has plagued vessels of all sizes: keeping particulates out of the water contained. The problem is worse for outdoor, unprotected vessels such as pools or hot tubs, but even indoor installations such as aquariums or fountains suffer from particulate contamination. Keeping these particulates out of the vessel is an ongoing and difficult proposition.
Contemporary solutions for cleaning some of the vessel types exist. For example, there are numerous examples of pool cleaners; some are automatic and some are manual, but all work on generally the same principle. Regardless of the exact implementation, all share a common need for connection to some source of motive power and each contains a filter/trap combination to capture the particulates. Solutions for other vessel types exist as well, for example spa cleaners. These also require some source of motive power and use the filter/trap cleaning methodology.
Aquariums present a special case since the gravel that lines the bottom of many aquariums appear as particulate matter to many vacuum type cleaning systems. The problem is compounded by restricted space and the presence of aquatic species. Existing methods include pump and filter mechanisms and others, but are useful only for aquariums and the walls forming the vessel.
What would be desirable would be a method and apparatus that was adaptable to all vessel types. Further, it would be desirable that the device be portable, contain its own source of power, and be easy to use and to configure. The present invention provides these and other advantages as discussed in detail below.

Drill motor operated portable water-tolerant suction cleaner


A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line.

1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to a method for reducing the risk of cracks in semiconductor chips.
2. Description of the Related Art
Semiconductor chips are formed on a silicon wafer. The chips are placed adjacent to one another on the wafer, and after fabrication processes are completed, the wafer is diced by cutting the wafer along kerfs. This separates the chips from each other. The dicing processes may induce stress into the chips. This stress may cause stress cracks to form through the semiconductor chip structure. Cracks may also form due to latent stresses in the semiconductor chip structure. Cracks typically form along interfaces between, for example, metal structures and dielectric materials. Some portions of the semiconductor structures are particularly susceptible to crack propagation.
Referring to FIG. 1A, a partial cross-sectional view of a metal structure is shown in accordance with the prior art. A substrate 10 includes diffusion regions 12, which are part of devices or components, such as transistors, capacitors, resistors, etc. A first level contact 14 connects diffusion region 12 to a first metal line 16. First metal line 16 runs into and out of the plane of the page, and is employed, for example, in making connections between devices on the substrate level or to higher metal layers. Another contact 18 connects metal line 16 to a metal line 20, which also runs into and out of the plane of the page. Contact 22 is employed for making connections between metal line 20 and higher metal layers. In this case higher metal layers include a terminal via (TV) 24 which is connected to metal line 20 by a contact 22. Terminal via 24 is typically employed for providing a test probe contact area and an area for connecting lead wires for electrically connecting the chip to a leadframe for packaging the chip.
The structure shown in FIG. 1A is susceptible to crack propagation. Stresses present in the chip or induced by processes, such as dicing, causes cracks to propagate along the structure in areas 26. Cracks form at the interface between dielectric material 28, for example, silicon dioxide, and metal lines/contacts. Cracks, which propagate down to substrate 10, have the potential for causing chip failures over time. Cracks also expose metal lines and contacts to ambient environments, which can cause corrosion/oxidation which degrade chip performance.
Referring to FIG. 1B, a top view taken at section line 1Bxe2x80x941B of the prior art structure of FIG. 1A is shown. Contacts 14 (18 and/or 22) are circular in shape and contact a small area of metal lines (e.g., 16 and 20) and/or terminal via (24). This area mismatch lends itself to stress concentrations, which may be detrimental to the reliability of the chip over time.
Therefore, a need exists for an improved crack stop design, which provides additional contacts between metal lines with a different geometry. A further need exists for a crack stop design, which includes an air crack stop.
A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line. The crack stop structure provides multiple contacts at each level to improve crack resistance.
Another semiconductor chip of the present invention, includes a substrate and a crack stop structure. The crack stop structure includes a first conductive line disposed over the substrate, and at least two first contacts are connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the substrate. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A dielectric material surrounds the crack stop structure, and the dielectric material includes an air-filled trench over the second conductive line to improve crack growth resistance.
In alternate embodiments, the at least two first contacts may include three contacts. The at least two second contacts may include three contacts. The chip may include a dielectric material surrounding the crack stop structure, and the dielectric material may include an air-filled trench over the second conductive line. The second conductive line may include a terminal via for testing the chip.
The chip may further include a third conductive line disposed over a portion of the second conductive line, and at least two third contacts connected to the second conductive line and the third conductive line, the at least two third contacts being spaced apart from each other and extending longitudinally along a length of the third conductive line. The third conductive line may include a terminal via. The first and second metal lines and the at least two first contacts and the at least two second contacts may form a serpentine structure. The serpentine structure is preferably located adjacent to a dicing channel of the chip. The at least two first contacts and the at least two second contacts may extend over the entire length of the first metal line.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

Chip crack stop design for semiconductor chips

International Business Machines Corporation


An obstacle detecting apparatus includes sensors and a processing unit. Each of the sensors are rendered operational by predetermined parameters. The processing unit transmits the parameters to the sensors and includes a vehicle state detector, a condition determiner, a communication controller, and a parameter setting processor. The vehicle state detector detects a running state of the vehicle. The condition determiner determines that the running state of the vehicle is one of an operating condition indicating that the sensors should be operated and a forbidding condition indicating that the operation of the sensors should be forbidden. The communication controller performs communication with the sensors. The parameter setting processor transmits the parameters to the sensors and receives a response indicating completion of the process. The parameter setting processor repeats the process upon either a parameter of one sensor not being set, or communication being terminated while the forbidding condition is identified.

Conventionally, there is known an obstacle detecting apparatus including a plurality of sensors and a control device, which are connected to each other through a bus (for example, see Japanese Patent Laid-Open Publication No. 2003-152741). According to an obstacle detecting apparatus disclosed in this patent reference, for example, a control device sequentially sets, through a bus, the IDs of connecting positions of the ultrasonic sensor from the ultrasonic sensor closest to the control device based on pre-stored connection sequence and IDs of ultrasonic sensors. Then, when the ID setting is completed for the last ultrasonic sensor, the control device starts communicating with each of the ultrasonic sensors.
In the above-described conventional obstacle detecting apparatus, each of the ultrasonic sensors functions as a sensor only after a parameter such as an ID to be set can be normally received in the first communication with the control device. Therefore, unless the parameter can be normally received, each of the ultrasonic sensors cannot function as a sensor.
Accordingly, if a communication error occurs during parameter setting, a process of setting a parameter again or stopping the communication with a sensor, which cannot receive a parameter is required to be performed.
In the parameter resetting, however, it is required to retransmit a parameter after each of the sensors is once powered OFF. Therefore, a long time is needed to reset a parameter so as to reestablish the communication. Moreover, if the communication with the sensor that cannot receive the parameter is continuously interrupted in the case where a temporary communication error such as the interference of an electromagnetic wave noise occurs, the communication with the sensor cannot be reestablished thereafter.

Obstacle detecting apparatus with error detection and recovery


A bathenette seat for bathing a baby is provided where the seat has a headrest with an opening which is sized and shaped to accept the back of the head of the baby being bathed so as to allow the washing of the back of the baby's head without allowing soap to get into the baby's eyes or ears. The bathenette further includes a leg support spaced from the headrest and a sprayer located on the leg support. The sprayer is positioned to spray water on the baby reclining in the seat. The bathenette also includes a height adjustment mechanism to vary the position of the headrest and a band around the opening of the headrest to further support the baby's head.

The present invention relates to a baby bathenette seat for supporting an infant during bathing.
Bathenettes are well-known for washing infants. It is also well-known to employ a seat within the bathenette to support the baby and help keep the baby from accidentally becoming emersed in the bath water.
Even with the use of such a seat, however, it is difficult to wash the baby's hair while keeping soap and water out of the infant's eyes and ears.
Apparatus to assist in washing the hair of a prone adult are known. However, these devices generally utilize a support placed behind the neck with the head being suspended over an open reservoir. Such a design is wholly unsuitable for use with an infant as the infant's head should be supported at all times to prevent injury.
Thus, there is a need for a simple, safe and inexpensive bathenette seat which will facilitate the washing of an infant's hair while protecting the baby's ears from emersion in water and the baby's eyes from damage from harsh soaps or shampoos.


Disclosed is a multiple separation filter including a microfiltration membrane, an active carbon-based filter and a ceramic filter stacked in order, wherein the active carbon-based filter is obtained by mixing active carbon with at least one selected from zeolite, gold, silver and a mixture thereof, treating the mixture with plasma gas of 60,000° C. to 70,000° C., and then quenching the mixture to −200° C. to −273° C. under vacuum, and the ceramic filter is obtained by quenching plasma gas generated by heating magnesium at 60,000° C. to 70,000° C. to −200° C. to −273° C. under vacuum. Disclosed also is antioxidant water obtained by using the multiple separation filter. The antioxidant water has a negative oxidation reduction potential.

As an income level and standard of living are improved, purified water with better quality as general water for living is increasingly in demand. In addition, with regard to drinking water, use of high-quality functional water such as ionized water, alkaline reduced water or soft water is increasingly in demand. Under these circumstances, functional products having various functionalities imparted to conventional filter structures, such as a water softener, water ionizer, system for producing alkaline reduced water and a bidet, have been developed actively.
In general, it is recognized that alkaline reduced water that has been subjected to electrolysis sufficiently is effective for treating abnormal fermentation in the stomach, chronic diarrhea, indigestion, hyperacidity and constipation, and thus most systems for ionizing water to produce electrolyzed alkaline water are thought as medical production systems rather than water purifiers. In addition, such alkaline water forms a part of health aid agents as antioxidant water.
In this context, commercially available systems for producing antioxidant water are those for producing alkaline antioxidant water through the electrolysis of water using galvanism. However, since such electrolysis systems are very expensive, many approaches using various mineral-based ceramics have been suggested.
With regard to a system for producing alkaline antioxidant water using mineral substances such as ceramics, Korean Laid-Open Patent No. 10-2007-0007979 discloses a multi-layer filter having filter layers including various ingredients and stacked in order. Herein, such a multi-layer filter for producing alkaline antioxidant water includes a first hydrogen reduction filter layer having anion-generating layers of beads, pH-adjusting layers of beads, reduction catalyst layers, and secondary hydrogen reduction filter having anion-generating alkaline layers of beads layer.
Particularly, the antioxidant water produced and commercialized by the methods according to the related art is also called electrolyzed reduced water or hydrogen-enriched water, when it is obtained by electrolysis of water. However, since hydrogen molecules contained in such electrolyzed reduced water are scattered in the air gradually with time, resulting in a decrease in amount of hydrogen, such water cannot function as antioxidant water. In addition, the system for producing electrolyzed reduced water is expensive in itself and requires high holding cost.
On the other hand, there is a commercialized product having a hydrogen-generating mineral stick attached to a water container and developed in a simple and cost-efficient manner. Such a product allows production and intake of reduced water as desired and is highly cost-efficient. However, in this case, there still exists the above-mentioned problem of a rapid decrease in hydrogen content in antioxidant water with time. Moreover, the hydrogen-generating mineral stick has no water-purifying function, and thus can be used merely in the case of purified water.

Multiple separation filter and antioxidizing water produced using the same


A storage service manager facilitates an operator's task for managing large-scale storage facilities. Allocating access paths on the storage network is accomplished by the use agent programs which interface to various components comprising a data path from the client to the storage system. The agent programs hide various vendor-specific and technology-dependent aspects of the storage network components from the user.

The present invention relates to computer network systems and in particular to management of storage in a networking environment.
The adoption of computer use in every aspect of our lives has created a great demand for storage capacity. Adequate data storage is an important component in most modern enterprises. The infrastructure technology that has developed to support the Internet has been exploited to provide a variety of network-based storage solutions. FIG. 24 shows a range of storage architectures, including simple single storage/single server systems, and fibre channel technologies such as fibre channel (FC) storage area networks (SANs) and wider area FC SANs. Though not yet realized, the natural progression is toward a fully generalized IP-based (internet protocol) storage area network (shown in the figure by the dashed lines).
Several types of storage devices are manufactured. They include RAID (redundant arrays of inexpensive disks) arrays, JBOD (just a bunch of disks) configurations which are spanning architectures that do not conform to the RAID definition, NAS (network attached storage) configurations, and so on. Accessing storage devices requires communication from the host, through the switching fabric, and through servers using any of a variety of protocols; e.g. fibre channel (FC), iSCSI (internet SCSI—Small Computer System Interface), NFS, and so on.
Given such a heterogeneous collection of intermediate components, it is not a trivial task to provision storage suitable for secured access, or with a guaranteed minimum throughput, and so on. As can be appreciated, each subsystem typically can be provided by a different hardware and software manufacturers. Thus, provisioning suitable storage access typically requires detailed knowledge of each subsystem in order to provide an appropriate access path. For example, a different user interface ("agent") for configuring each component typically is required. This necessitates the use of one or more operators to administer each component (e.g., host), and to collectively coordinate the configuration of the myriad components to connect the user's host system to her storage media with the access characteristics that she requires.
It can be appreciated that there is a need to provide access to storage in a storage area network for users who have disparate storage needs in a storage system which subsystems have disparate administrative requirements. There is a need to facilitate the establishment and subsequent management of network paths in a storage area network based, for example, on security criteria.

Method and apparatus for storage network management


An electronic device includes: an integrated circuit having a first circuit part, a second circuit part, a first power source line of the first circuit part, a second power source line of the second circuit part, and a coupling switch coupling the first power source line and the second power source line; a power source supply part which generates a power source to be supplied to the first and second circuit parts and which has a power source supply control circuit controlling the supply of power source to the second circuit part; and a power source control part that controls the power source supply control circuit and the coupling switch, wherein the power source control part controls the power source supply control circuit so as to supply a power source in accordance with the operating state of the second circuit part and closes the coupling switch.

In a transistor used in a semiconductor integrated circuit, a current (leak current) flows even in a state in which no operation is carried out, consuming electric power. Because of this, a method has been adopted, which electrically disconnects the power source of a circuit not in operation in order to reduce the leak current. FIG. 1 shows an example of a configuration of an electronic device system including a conventional image processing LSI 6. In image processing LSI 6, a first circuit part 7 and a second circuit part 8 are provided. First circuit part 7 is a memory (hereinafter, explained as SRAM), such as SRAM, to save a decryption key necessary to decode encrypted data, or a circuit, such as a timer, which is always in operation, and it is necessary for first circuit part 7 to be in an operating state or in a data holding state at all times. On the other hand, second circuit part 8 is a logic circuit for image processing etc., and is a circuit that may be put into a suspended state without the need to supply power when not in operation.
First circuit part 7 and second circuit part 8 are coupled to external power source lines 11 and 12 via internal power source lines 13 and 14 and a power source is supplied from an external power source supply part 9 via these power source lines. A low potential side power source GND is common. When second circuit part 8 is not in operation, no power source is necessary and therefore a switch SW1 is provided within power source supply part 9, which may be controlled to turn on/off by a control signal S1 from a CPU 1, and thus the supply of power source may be controlled. On the other hand, first circuit part 7 is always supplied with a power source in order to hold stored data. CPU 1 mounted on an LSI chip different from image processing LSI 6 is coupled to image processing LSI 6 and transmits image data or processing programs. CPU 1 is coupled with an operation part 4, a display part 3, and an external memory 2 via a bus 5, and thus, the transmission of data with any of the devices is enabled.
The control of SW1 by CPU1 when a user decodes image data in memory 2 and displays it on display part 3 in this system is explained. As an initial state, in first circuit part 7 of image processing LSI 6, data necessary for decode processing is saved. For example, a decryption key necessary to decode encrypted data is saved. It is assumed that SW1 is electrically disconnected (opened) because the data in second circuit part 8 does not need to be saved.
When a user presses a button of operation part 4, a control signal to instruct activation is sent from the operation part to CPU 1. CPU 1 sends power source supply control signal S1 to power source supply part 9 in order to close SW1. Upon receipt of the power source supply control signal, power source supply part 9 closes SW1. CPU 1 transfers image data and a processing program from memory 2 to first circuit part 7 of image processing LSI 6 and commands execution of the processing program. In image processing LSI 6, second circuit part 8 reads the program, the image data, and the decryption key from first circuit part 7 to carry out processing and writes image data after the processing in first circuit part 7. The image data after the processing is sent to display part 3 from first circuit part 7. When all of the processing is completed, image processing LSI 6 sends a control signal indicative of the completion of the processing to CPU 1. CPU 1 sends power source supply control signal S1 to power source supply part 9 in order to open SW1. Upon receipt of power source supply control signal S1, power source supply part 9 opens SW1.
As explained above, in an electronic circuit system having a multi-power source LSI, the circuit within the LSI is divided into a plurality of circuit parts and the supply of power source to each circuit part is carried out via distinct power lines and thus it may be possible to terminate the supply of power source from the power source supply part to a circuit part not in operation within the LSI. In order to separate the supply of power source to each circuit part, an electrode pad to be coupled to power source line 13 of first circuit part 7 and an electrode pad of the LSI package to be coupled to power source line 11 are coupled by a boding wire etc., and similarly, an electrode pad to be coupled to power source line 14 of second circuit part 8 and an electrode pad of the LSI package to be coupled to power source line 12 are coupled by a boding wire etc.
Patent document 1 (Japanese Unexamined Patent Publication (Kokai) No. H5-291368) and patent document 2 (Japanese Unexamined Patent Publication (Kokai) No. 2005-109238) describe a configuration in which the circuit within an LSI is divided into a plurality of circuit parts and the supply of power source to each circuit part is carried out via distinct power source lines. Further, patent documents 1 and 2 describe a configuration in which switches that couple a power source line of a plurality of circuit parts of an LSI to another are provided within the LSI. In this LSI, when a rated voltage is applied to the LSI, the switch is put into a state of out of conduction and normal operation is carried out and when a voltage that exceeds the rating is applied at the time of test, the switch is brought into conduction and thus the number of probes that are caused to come into contact with the electrode pad at the time of the test of LSI may be reduced.
Patent document 3 (Japanese Unexamined Patent Publication (Kokai) No. 2005-101325 describes a configuration in which a switch that couples an input terminal of an external power source of an LSI to another is provided and when a voltage that exceeds the rating, such as a surge voltage, is input, the switch is brought into conduction and thus a raise in voltage is suppressed.
However, none of patent documents 1 to 3 describe a configuration in which the supply of power source to part of the circuit within the LSI is terminated.
Patent document 1: Japanese Unexamined Patent Publication (Kokai) No. H5-291368
Patent document 2: Japanese Unexamined Patent Publication (Kokai) No. 2005-109238
Patent document 3: Japanese Unexamined Patent Publication (Kokai) No. 2005-101325

Electronic device having multi-power source integrated circuit


The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.

In semiconductor and memory device applications, an electrode is a conductor through which electric current is passed. The electrode is typically comprised of a metal, such as copper, tungsten, silver, lead, or zinc. The electrode may also be in the form of a nonmetallic conductor, including a semiconducting material, such as doped polysilicon. Phase change random access memory (PRAM) devices store data using a phase change material, such as, for example, a chalcogenide alloy, that transforms into a crystalline state or an amorphous state or vice versa during heat treatments or during quench following heat treatments. Each state of the phase change material has different resistance characteristics. Typically, the phase change material in the crystalline state has low resistance and the phase change material in the amorphous state has high resistance. The crystalline state is typically referred to as a "set state" having a logic level "0", and the amorphous state is typically referred to as a "reset state" having a logic level "1". In some phase change random access memory devices, electrodes supply energy, i.e., heat, to the phase change material to induce phase changes.

Phase change element extension embedded in an electrode


Disclosed is a chip contact mechanism for a developer cartridge. The chip contact mechanism comprises a chip holder movably provided on the developer cartridge and a lever for enabling the chip holder to move. The chip holder is provided with a chip installation position. A return member is provided between the chip holder and the cartridge body. Disclosed is also a developer cartridge which comprises the chip contact mechanism.

Electrophotographic imaging forming apparatus such as laser printers, utilizing the principle of electronic photography, which at least involve charging, exposing, developing, transferring, fixing, and cleaning processes to form images on the medium such as paper. The imaging forming apparatus usually use detachable developer cartridges to complete the above processes.
In the charging process, a photosensitive member, such as photosensitive drum, is uniformly charged with a given amount of charge by a corona discharge method or by using a charging roller. In the exposure process, the surface of the charged photosensitive member is selectively exposed. Due to the photosensitive characteristics of the photosensitive member, the charge of the exposed region disappears by grounding. Therefore, after exposure, an electrostatic latent image is formed on the surface of the photosensitive member through the distribution of charge which corresponds to the designed image. In the developing process, the developing device, such as the developing roller, transfers the developer, such as toner, to the electrostatic latent image region with the force, such as the electric force, to visualize the electrostatic latent image. In the transferring process, the transferring device, such as the transfer roller, transfers the developer of the electrostatic latent image on the photosensitive member surface to the imaging medium such as paper. In the fixing process, the image fixing device firmly fixes the developer onto the imaging medium. In the cleaning process, the cleaning device, such as the wiper blade, removes the residual developer from the surface of the photosensitive member to avoid printing defects in the next image forming cycle.
Conventional developer cartridges usually have a toner hopper unit and a waste bin unit. The toner hopper unit comprises a developing roller, a doctor blade, a toner adder roller and an agitating frame. The waste bin unit comprises a photosensitive drum, a charging roller and a wiper blade. Some developer cartridges only have a toner hopper unit, but do not have waste bin units. In the prior art, some developer cartridges are provided with chip contact mechanisms which are fixed on the cartridge body. The chip contact mechanism has a chip installation position and the chip is fixed on the chip installation position. When the developer cartridge is installed inside the printer, the chip on the developer cartridge is in contact with the contact inside the printer, the circuit is turned on, and the developer cartridge starts working. However, this method creates relatively high impact on the contact of the imaging forming apparatus which may damage the contact of the imaging forming apparatus, resulting in poor contacting and interference with the work of the developer cartridge.

Chip contact mechanism and developer cartridge

PRINT-RITE • UNICORN IMAGE PRODUCTS CO., LTD. OF ZHUHAI