A method, apparatus, and article of manufacture for accessing a database management system. A database management system (DBMS), executed by a server computer, manages one or more datastores stored on the computer. The DBMS includes an Open Transaction Manager Access (OTMA) that provides a high level application programming interface (API) for an application program to access the DBMS and its datastores, wherein the OTMA allows the application program to create an authorized connection with the DBMS. The server computer also executes a TCP/IP OTMA Connection (TOC) that establishes and manages connections between the DBMS and the application program. In the preferred embodiment, the application comprises a Java servlet or applet executed by a Java Virtual Machine (JVM). A TOC Connector for Java interfaces the JVM to the TOC, wherein the TOC Connector for Java includes one or more objects for establishing a connection between an applet or servlet executed by the JVM and the OTMA of the DBMS, so that transactions can be transmitted from the application program to the DBMS over the established connection and results of the transmitted transactions can be received at the application from the DBMS.

1. Field of the Invention
The present invention relates generally to computerized methods for accessing databases, and in particular, to system message objects for communicating between an application and a database management system.
2. Description of Related Art
It is well known in the art to use database management systems, such as IBM""s IMS (Information Management System) database management system DBMS), to manage computerized databases. Indeed, IMS has been used for decades and remains in use today. Currently, there is a need to access such xe2x80x9clegacyxe2x80x9d databases using. application programs. However, such tasks are complex and there are few tools available to assist application program developers.
IMS Open Transaction Manager Access (OTMA) is a high performance client/server protocol that allows application programs to access an IMS DBMS. However, the application program must include an interface to the IMS OTMA, which can be difficult to develop. To interface with an IMS DBMS requires rather extensive knowledge of the architecture of the IMS DBMS, as well as the architecture of the MVS operating system. Moreover, because of security considerations with regard to accessing an IMS DBMS, a great deal of skill is involved in establishing a connection between an application program and the IMS DBMS, since it must interface with the operating system as a secure and trusted xe2x80x9cuserxe2x80x9d.
In order to more fully provide access to an IMS DBMS, it would be advantageous to have an easier mechanism to connect to the IMS DBMS and run transactions thereby. Thus, there is a need in the art for improved techniques for accessing a hierarchical database management system.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method, apparatus, and article of manufacture for accessing a database management system. A database management system (DBMS), executed by a server computer, manages one or more datastores stored on the computer. The DBMS includes an Open Transaction Manager Access (OTMA) that provides a high level application programming interface (API) for an application program to access the DBMS and its datastores, wherein the OTMA allows the application program to create an authorized connection with the DBMS. The server computer also executes a TCP/IP OTMA Connection (TOC) that accepts and manages connections between the DBMS and the application program. In the preferred embodiment, the application comprises a JAVA servlet or applet executed by a JAVA Virtual Machine UVM). A TOC Connector for JAVA interfaces the JVM to the TOC, wherein the TOC Connector for JAVA includes one or more objects for establishing a connection between the servlet or applet executed by the JVM and the OTMA of the DBMS, so that transactions can be transmitted from the application program to the DBMS over the established connection and results of the transmitted transactions can be received at the application from the DBMS.

System message objects for communicating between an application and a database management system

International Business Machines Corporation


Apparatus, techniques and systems for preventing illegal use of software and other digital files based on operations of a data storage device controller in a computer or computer system. For example, a method for preventing illegal use of software includes: configuring a computer to use a data storage device controller to control use of each digital file stored on one or more data storage devices; before a use of each digital file, operating the data storage device controller to access a storage device on which the digital file is stored to check whether the digital file meets a condition for use; and operating the data storage device controller to block use of the digital file when the condition is not met and to allow execution of the digital file when the condition is met. The digital file can be an application software or other digital documents.

With the progress of the computer technology, more and more applications software are developed to process sophisticated operations including calculation, graphic rendering, audio synthesis, etc., as well as developed a lot of corresponding file types, like multimedia files, text files, etc.
It has already used many methods to prevent the illegal use of the content protected files and commercial software. However, hereto, each of the protection methods has its own drawbacks, so some users can illegally use software by cracking.
The term "Cracking" means breaking the various copy-protection and registration techniques being used.
It is understood by those skilled in the art that the proposed protection way can be used to protect any files which can be stored on data storage device, like:
Data files,
Program Files:                Applications software files.        Systems software files.
The applications software will be used as a sample to explain proposed protection method. Applications software includes programs that do real work for users. For example, word processors, spreadsheets, and database management systems fall under the category of applications software.
FIG. 5 shows a conventional method for protecting applications software. After obtaining an applications software, the user installs files associated with it on a data storage device 3. As used herein, the data storage device 3 includes any devices able to store digital data therein such as hard disk, compact disk (CD), digital versatile disk (DVD), floppy disk, magnetic tape, flash memory, network memory, etc., and all devices which can be a source to launch and execute the applications software 2. Various files 2 of the installed applications software are in an unprotected state. The user can crack the applications software 2 through a crack program 1, so that the contents for preventing illegal use of applications software files will be modified to achieve an object of illegal use of the software. After modifying the files of applications software 2 so as to release a software protection, the user can execute this applications software through an operation system 4 (for example, Windows®, Linux, Unix). Specifically, the operation system 4 sends instructions to a data storage device controller 5 mounted on a motherboard 6 and operation system 4 can read and execute the files of applications software 2 stored on the data storage device 3. Since the internal protection of this application program has already been removed by the cracking program 1, this application program regards this user as a legal user, and performs its functionalities under the operation system 4. As it can be seen, the crack program 1 can freely remove limitations on the execution of the applications software 2 by modifying the files of applications software 2. Therefore, internal self protection of the applications software can not effectively prevent the illegal use of the applications software.
FIG. 6 shows another conventional method of the protection of applications software. Similar to the method shown in FIG. 5, after obtaining an applications software, the user installs files associated with it on the data storage device 3. At the same time, a dedicated protection software program 7 is also installed on the data storage device 3 for providing a protection against illegal use of the installed applications software 2. However, the dedicated protection software program 7 and an operation system 4 are still in an unprotected state. The user can modify the files of dedicated protection software program 7 and the files of operation system 4 through a crack program 1, so that the contents for preventing illegal use of these files are modified to achieve an object of illegal use of the software. The result of the cracking of the dedicated protection software program 7 and the operation system 4 is a release of the protection of the dedicated protection software program 7 to the applications software 2. The user can execute this applications software through the operation system 4. Specifically, the operation system 4 sends instructions to a data storage device controller 5 mounted on a motherboard 6 and operation system 4 can read and execute the files of applications software 2 stored on the data storage device 3. Since the external protection by the dedicated protection software program 7 has already been removed by the crack program 1, the dedicated protection software program 7 regards this user as a legal user, and the applications software performs its functionalities under the operation system 4. As it can be seen, the crack program 1 can freely remove limitations on the execution of the applications software 2 by modifying the files of the applications software 2, the files of dedicated protection software program 7 and the files of operation system 4. Therefore, the protection which is provided by dedicated protection software can not effectively prevent the illegal usage of applications software.
FIG. 7 shows another conventional method for protecting the applications software. This method uses a hardware control unit "Watchdog" to provide the protection. Similar to the method shown in FIG. 5, after obtaining an applications software, the user installs files associated with it on the data storage device 3. When the applications software is executed, this program sends an instruction to read the Watchdog 8 and receives a corresponding return value from the Watchdog 8. If the return value is correct, then the software is considered to be legally used, otherwise, if the return value is incorrect, then the software is considered to be illegally used and is terminated. However, since various files 2 of the installed applications software and the files of operation system 4 are in an unprotected state, the user can modify the files of applications software 2 and the files of operation system 4 through a crack program 1, so that the contents for preventing illegal use of these files are modified to achieve an object of illegal use of the software. After modifying the applications software files 2 and the files of operation system 4, the user can execute this applications software through the operation system 4. Specifically, the operation system 4 sends instructions to a data storage device controller 5 mounted on a motherboard 6 and operation system 4 can read and execute the applications software 2 stored on the data storage device 3. Since the internal protection of the application program has already been removed by the crack program 1 and the applications software no longer reads the watchdog 8, or the operation system 4 performs interceptions when the applications software reads the watchdog 8 and a correct value is returned, the applications software regards this user as a legal user, and performs its functionalities under the operation system 4. As it can be seen, the crack program 1 can freely remove limitations on the execution of the applications software 2 by modifying the files of applications software 2 and the files of operation system 4. Therefore, a protection to the software by means of the watchdog 8 can not effectively prevent user's illegal use of the applications software.
As it can be seen from FIGS. 5, 6 and 7, there are some protected files and some files involved in the protection procedure for protecting the protected files. Both of types of the files are always in a unprotected state and thus can be illegally modified to remove software protection.
In general, FIGS. 5, 6, 7, show that there exist some basic problems in software protection—software is protected by the same or other software, which can be cracked as soon as its files are installed on hard drive of current PC. It is obvious, that above mentioned problems are true for all kinds of software like data files and program files.

Method for preventing illegal use of software


Bio-information sensors acquire bio-information about a user, and environmental condition sensors acquire environmental information about the user. A call-sound generating unit generates audio data from the bio-information and the environmental information, and the audio data is recorded in a ROM. Upon detecting a call signal transmitted from a base station, a CPU causes the call-sound generating unit to read the audio data. The CPU causes the call-sound generating unit to supply the audio data to a speaker that generates the sound from the audio data.

1. Field of the Invention
The present invention relates to a portable terminal device and a method of informing the user of the arrival of calls. More particularly, the invention relates to a portable terminal device that waits for signals from any external network and informs the user of the arrival of the signals, and also to a method of informing the user of the arrival of calls.
This application claims priority of Japanese Patent Application No. 2003-286056, filed on Aug. 4, 2003, the entirety of which is incorporated by reference herein.
2. Description of the Related Art
Conventional portable tar devices, such as mobile telephones and PDAs, generate call sound, informing the users of the arrival of calls or mails. The audio data for the call sound, which represents either music or mimetic sound, is recorded in a memory such as a ROM incorporated in the conventional portable terminal device. A part of the audio data recorded in the memory is designated as data that represents the call sound. To change the call sound to another one, the user manually selects another part of the audio data and sets it as the data representing the new call sound (see Jpn. Pat Appln. Laid-Open Publication No. 15-051865).
With the conventional portable terminal device, the user cannot help but select one of a few audio data, as data representing the call sound. In other words, the user can use only a small part of the large audio data recorded in the memory. The same also holds true of the video data stored in the terminal device. Only a part of the video data is used to represent the call-arrival image or the call-wait image on the display provided on the portable terminal device.

Portable terminal device and method of generating call sound


An MIS device which includes a source diffusion layer and a drain diffusion layer under the surface of a semiconductor substrate, and a plurality of gate insulation films on the surface of the semiconductor substrate. Further, a plurality of gate electrodes are formed on the plurality of gate insulation films in series with one another between the source diffusion layer and the drain diffusion layer. Moreover, inter-gate-electrode diffusion layers are formed under the surfaces of regions of the semiconductor substrate among the plurality of the gate electrodes. Insulating side walls are provided on both sides of each of the gate electrodes. Furthermore, conductive layers are provided, each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes and covering the insulating side walls provided on that one inter-gate-electrode diffusion layer, and filling a depression surrounded by the insulating side walls and that one inter-gate-electrode diffusion layers. An insulation layer covers the gate electrodes and the conductive layers, at least partly. A conductive wiring layer on the insulation layer is in contact with a part of the conductive layer, which is not covered by the insulation layer. The conductive layers at both sides of at least one of the gate electrodes are selectively interconnected on that gate electrode. Thus at least one of the inter-gate-electrode diffusion layers provided among the plurality of the gate electrodes, which are used in a memory cell, is covered by a conductive layer. As the result, the transconductance of an enhancement type transistor can be increased. An amplification factor and a switching speed of the enhancement type transistor can be improved. Consequently, a high-speed operation can stably be performed.

1. Field of The Invention
This invention relates to a metal-insulation-silicon (hereunder abbreviated as MIS) type semiconductor device, which can be employed as, for example, a read-only memory, and a method for producing an MIS type semiconductor device.
2. Description of The Related Art
In recent years, there has been a marked tendency to develop a large capacity and highly-integrated semiconductor device. Moreover, there has been increased a demand for a very fine semiconductor device. Thus, a layout of a semiconductor pattern and a structure of a semiconductor device, which are more advantageous for producing a very fine semiconductor device (namely, for microminiaturizing a semiconductor device), are required. This holds true for a read-only memory.
Meanwhile, a threshold voltage of an MIS type transistor can be controlled according to the kinds and concentrations of impurities to be added to a semiconductor substrate, which is employed as a channel, in a diffusion process. In a read-only memory, information is selectively stored according to whether or not an operating threshold voltage of a gated transistor is greater than a reference voltage. An example of a conventional MIS type semiconductor device (hereunder sometimes referred to as a first conventional MIS type semiconductor device), as well as a method for producing such a conventional MIS type semiconductor device, will be described hereinbelow by referring to FIGS. 8 and 9.
FIG. 8 is a sectional view of the first conventional MIS type semiconductor device. As illustrated in this figure, the first conventional MIS type semiconductor device consists of a gate oxidation film 132 formed on a silicon substrate 131, a plurality of gate electrodes comprised of a gate-electrode polysilicon layer 133 and connected in series with one another, a source diffusion layer 134 and a drain diffusion layer 135 which are formed in the silicon substrate 131, n-type diffusion layers 136 formed between the gate electrodes, an n-type diffusion layer 139 for forming a depletion type metal-oxide semiconductor (hereunder abbreviated as DMOS) channel, an insulation layer (hereunder sometimes referred to as an inter-layer insulation film) 137 and an aluminum wire 138.
FIGS. 9(a) to 9(d) are sectional views of the first conventional MIS type semiconductor device for illustrating the method for producing the first conventional MIS type semiconductor device. Hereinafter, this method will be described by referring to these figures.
First, as shown in FIG. 9(a), a photoresist mask 140 for separating an n-type diffusion area is formed on the silicon substrate 131. Then, an n-type ion implantation is performed by shooting streams of ions 141 and using the photoresist mask 140 as a mask for the ion implantation. Thus n-type impurities are selectively diffused in the silicon substrate 131. As the result, the diffusion layer 139 for forming a DMOS channel is formed in order to control the threshold voltage of the conventional semiconductor device.
Next, as shown in FIG. 9(b), a photoresist mask 142 for forming a gate electrode is formed after the gate oxidation film 132 and the gate-electrode polysilicon layer 133 are formed.
Subsequently, as shown in FIG. 9(c); an etching of the gate-electrode polysilicon layer 133 is performed by using the photoresist mask 142 as a mask for the etching process. Then, n-type impurities are diffused by effecting an n-type ion implantation of streams of ions 143. Thus, the source diffusion layer 134, the drain diffusion layer 135 and the diffusion layers 136 are simultaneously formed.
Next, as shown in FIG. 9(d), the inter-layer insulation film 137 and the aluminum wire 138 are formed.
In the conventional MIS type semiconductor device produced as above described, the n-type diffusion layer 139 for forming a DMOS channel is present under the second gate electrode from left as viewed in FIG. 8. Thus the second transistor from left becomes a DMOS. In contrast, each of the other transistors (namely, the first, third and fourth transistors from left) is an enhancement type MOS (hereunder abbreviated as EMOS).
As is understood from the foregoing description, a read-only memory employing the first conventional MIS type semiconductor device has a structure in which data stored in a transistor thereof is discriminated as 1 or 0 according to which of DMOS and EMOS the transistor is.
A memory cell comprised of the first conventional MIS type semiconductor device constructed described above has a structure commonly called a single-layer polysilicon NAND type gate. In recent years, this structure is employed in many memory cells of mass read-only memories because of the fact that only one contact is provided therein correspondingly to a plurality of gate electrodes and thus this structure is favourable to realization of a highly integrated circuit.
Notwithstanding such an advantage, the first conventional MIS type semiconductor device and the method for producing such a conventional semiconductor device have the following drawbacks.
First, a period of time from the beginning of a programming of a read-only memory to the completion thereof is long, because the n-type diffusion layer 139 for forming a DMOS channel is formed before the gate electrodes are formed.
As a countermeasure to eliminate this drawback, it can be considered to form a diffusion layer made of impurities in a silicon substrate by performing an ion implantation posterior to the formation of the gate electrodes by accelerating ions to high velocity, which is sufficient to cause the ions to penetrate the gates. Such a countermeasure, however, has defects in that it requires an ion implantation apparatus which can accelerate ions to high energies in the range of several hundred kilo-electronvolts (KeV) to several mega-electronvolts (MeV) and in that the throughput of such an ion implantation apparatus becomes extremely low because a large quantity of ions to be accelerated is needed due to the facts that it is difficult to obtain a large beam current and that the gates hinder ions from reaching the silicon substrate.
Moreover, an ion implantation to be effected by accelerating ions to high velocity is attended with harmful effects that a device-isolation failure becomes liable to take place due to an occurrence of penetration of the n-type impurities through a device-isolation oxidation film. Thus a countermeasure to the penetration of the n-type impurities (for example, employment of trench isolation or a thick isolation oxidation film) becomes further needed.
Second, it is hard to realize a high-speed operation because the plurality of gate electrodes are arranged in series with one another and thus transistors of each memory cell cannot draw a large electric current (namely, cannot have large current driving ability).
The current flowing through the transistor of each memory cell depends on characteristics of the EMOS and DMOS transistors thereof.
Hereinafter, two respects noted by the inventor of the present invention to realize a high-speed operation of an MIS type semiconductor device will be described.
Generally, the transconductance g.sub.me of an MOS transistor is obtained by the following equation: EQU g.sub.me =g.sub.m /(1+R.sub.s .times.g.sub.m)
where R.sub.s denotes the resistance (hereunder sometimes referred to as the source resistance) of the source area of the MOS transistor; and g.sub.m the transconductance thereof in case where the source resistance R.sub.s is neglected.
Namely, when the source resistance R.sub.s increases, the transconductance g.sub.me is extremely degraded. As the result, characteristics such as an amplification factor and a switching speed of the MOS transistor are deteriorated.
In case of the device of the present invention, the characteristics of an MOS transistor can be improved by decreasing the source resistance R.sub.s of the MOS transistor.
Moreover, generally, in case where a diffusion layer made of n-type impurities is formed in a silicon substrate by an ion implantation or the like in order to form a channel of a DMOS transistor, the electrical resistance tends to decrease and the current driving ability of the DMOS transistor is apt to increase in proportion as the concentration of impurities is risen by increasing a quantity of implanted ions.
However, the elements of the impurities, of which the quantity exceeds a solid solubility limit, cannot dissolve in a silicon layer. Therefore, the quantity of the impurities, which can dissolve in a silicon layer, saturates at a certain value of the electrical resistance. It is, accordingly, difficult to make the value of the electrical resistance lower than the certain one thereof. Even if what is called an activation rate of ions of the impurities are increased, the electrical resistance can be lowered only to a specific value thereof. Instead, the diffusion layer of the impurities in the silicon layer is substantially extended as the result of an annealing or heat treatment for increasing the activation rate. This is disadvantageous to the production of a very fine memory element.
In case of the device of the present invention, the electrical resistance of an area corresponding to a channel of the DMOS transistor is lowered to have the same effects as would be obtained in case of improving the current driving ability of a DMOS transistor.
It is, therefore, an object of the present invention to provide an MIS type semiconductor device which can improve the transconductance of an enhancement type transistor thereof and characteristics of the transistors thereof to realize a high-speed operation thereof.
Further, it is another object of the present invention to provide a method, by which such an MIS type semiconductor device can stably be produced or fabricated.
Next, another example of a conventional MIS type semiconductor device (hereunder sometimes referred to as a second conventional MIS type semiconductor device), as well as a method for producing such a conventional MIS type semiconductor device, will be described hereinbelow by referring to FIGS. 11(a) and 11(b).
FIG. 11(a) is a plan view of a primary part of a layout of the second conventional MIS type semiconductor device.
FIG. 11(a) illustrates the layout of the semiconductor device comprised of a device-isolation region 201, memory-cell transistor gate electrode regions 202, selection line transistor gate electrode regions 203, an n-type diffusion region 217 for forming a DMOS channel, a drain region 218 and a contact pattern region 205 for forming a contact which touches the region 218.
Data is written to a read-only memory, which is produced by using this layout, according to which of DMOS and EMOS transistors a memory cell, to which the data is written, has correspondingly to the presence or absence of the n-type diffusion region 217.
In case of using the conventional patter layout, there is necessity of separating the layout pattern from gate electrode region by a distance of an overlapping margin 206 for forming the contact as a limit to the layout of the contact patter region 205.
This results in that the distance 207 between the selection line transistor gate electrode regions 203, which are respectively located at end portions of couples of the regions 203 upwardly and downwardly from the contact pattern region 205 as viewed in FIG. 11(a), should be more than a distance obtained by adding a length, which is twice the overlapping margin 206, to the length of the contact pattern region 205 in the vertical direction thereof as viewed in this figure.
FIG. 11(b) is a sectional view of the primary part of the layout of the second conventional MIS type semiconductor device, taken along the vertical line passing through the center of the contact pattern region 205 of FIG. 11(a). In FIG. 11(b), reference numeral 208 denotes a silicon substrate; and 219 a device-isolation oxidation film. Reference numerals 209 and 210 designate a memory-cell transistor gate electrode and a selection line transistor gate electrode 210, respectively, each of which has a gate oxidation film and a gate electrode polysilicon layer. Further, reference numeral 211 represents a drain diffusion layer formed in the silicon substrate 208; 215 an inter-layer insulation film; and 216 an aluminum wire employed as a bit line.
Incidentally, the n-type diffusion region for forming a DMOS channel and the n-type diffusion region provided between the gate electrodes are not shown in the sectional view of FIG. 11(b). However, these n-type diffusion regions are present in a portion, in which the device-isolation oxidation film 219 is not present, of the device.
Further, the overlapping margin 206 for forming the contact, as well as the distance 207 between the selection line transistor gate electrode regions 210, is shown in this sectional view.
A memory cell comprised of the second conventional MIS type semiconductor device constructed as shown in FIGS. 11(a) and 11(b) also has a structure commonly called a single-layer polysilicon NAND type gate. This conventional technique, however, has a drawback in that it is disadvantageous to fabrication of a very fine semiconductor device because an overlapping margin for forming an extra contact is required in case of fabricating a further highly integrated device.
Moreover, this conventional technique has another drawback in that the interconnection cannot stably be formed because an aspect ratio of a contact (namely, a ratio of the contact's depth to the contact's diameter) formed in a drain region and an aspect ratio of a contact formed in a source region are large.
Furthermore, this conventional technique has a further drawback in that a period of time from the beginning of a programming of a read-only memory to the completion thereof is long, because an n-type diffusion layer for forming a DMOS channel is formed before gate electrodes are formed.
Additionally, similarly as in case of the first conventional MIS type semiconductor device, the second conventional MIS type semiconductor device has still another drawback in that it is disadvantageous to a high-speed operation because a plurality of gate electrodes are arranged in series with one another in the pattern layout and thus transistors of each memory cell cannot draw a large electric current (namely, cannot have large current driving ability) which depends on characteristics of the EMOS and DMOS transistors thereof. The inventor of the present invention takes note of the two respects described above in order to realize a high-speed operation of an MIS type semiconductor device.
It is, therefore, a further object of the present invention to provide an MIS type semiconductor device which can be microminiaturized and can improve the transconductance of an enhancement type transistor thereof and can make the resistance of a region corresponding to a channel of a DMOS transistor low in order to have similar effects as obtained by improving the current driving ability of the DMOS transistor, thereby realizing a high-speed operation thereof, and which can shorten a period of time from the beginning of a programming of a read-only memory to the completion thereof.

MIS type semiconductor ROM programmed by conductive interconnects


The disclosure relates generally to wireless communication with an implantable medical device. An implantable medical device (IMD) may initiate the establishment of a communication session by sending a wakeup communication to an external device with which the IMD desires to communicate. The external device may operate in low power state (sometimes referred to as a sleep state or a low current state) in which the external device occasionally powers up telemetry circuitry to monitor for the wakeup communication from the IMD. Upon receiving the wakeup communication, the external device transitions from the low power state to a high power state to establish the communication session with the IMD. Operating the external device in the low power state when no communication session is established reduces the amount of power consumed by the external device when no telemetry is occurring, thus enabling the external device to be powered by a battery.

A wide variety of implantable medical devices (IMDs) that deliver a therapy to or monitor a physiologic or biological condition of a patient, or both, have been clinically implanted or proposed for clinical implantation in patients. An IMD may deliver therapy to and/or monitor a physiological or biological condition with respect to a variety of organs, nerves, muscles or tissues of the patients, such as the heart, brain, stomach, spinal cord, pelvic floor, or the like. The therapy provided by the IMD may include electrical stimulation therapy, drug delivery therapy, or therapy to reduce or eliminate a condition or symptoms of the condition of the patient.
The IMD may exchange communications with another device. The IMD may exchange communications with an external device, such as a programming device or a monitoring device (e.g., either attached to the patient or otherwise located near the patient). The information exchanged may be information related to a condition of the patient, such as physiological signals measured by one or more sensors, or information related to a therapy delivered to the patient. This information may be previously stored or real-time information. The IMD may also receive information from the external device, such as configuration information that may be used to configure a therapy to be provided to the patient.

Wireless communication with an implantable medical device


An instruction flow monitoring mechanism performs control flow error detection in a reduced instruction set computer (RISC) processor using signature monitoring. The signature monitoring is integrated into the RISC processor such that the instruction set of the RISC processor is enhanced to perform signature checking under all execution conditions. A signature monitor instruction causes the instruction flow to be checked for errors by comparing a pre-computed reference signature with a current signature and raising an error condition if the two signatures are unequal. The instruction also initializes the current signature.

A popular design for central processing units is reduced instruction set computer (RISC) processors using pipeline architecture. With pipeline architecture, the tasks performed by a processor are broken down into a sequence of functional units referred to as stages or pipeline stages. Each functional unit receives one or more inputs from the previous stage and produces one or more outputs, which may then be used by a subsequent stage. Thus, one stage's output is usually the next stage's input. Consequently, all of the stages are able to work in parallel on different, although typically sequential, instructions in order to provide greater throughput.
Typical stages of a RISC pipeline include instruction fetch, register fetch, arithmetic execution, and write-back to registers. In order to improve performance, a pipeline receives a continuous stream of instructions fetched from sequential locations in memory using addresses that are typically stored in a program counter or other suitable device. When several instructions are concurrently executing and each pipeline stage is performing its designated task for one of these instructions, a single instruction can be executed approximately every processor clock cycle. This design offers greater efficiency than other architectures, such as Complex Instruction Set Computer (CISC), where an instruction is executed in more than one processor clock cycle. In general, the architectural concepts behind RISC and CISC designs greatly differ, as is appreciated by those of ordinary skill in the art.
Because of the many advantages of the RISC architecture, only a few of which are discussed above, RISC processors enjoy a wide variety of applications including safety critical environments such as transportation, health care, manufacturing, defense, and space environments. The increased use of RISC architecture in such applications demands improvements in the dependability of these processors; that they perform what is expected correctly with a very high degree of probability by tolerating failures.
A detectable fault may generate a processor error that is represented by a processor output that violates expectations. The error may either be due to a fault in the data or in the instruction execution control flow. The detection of control flow errors in RISC processors is considered by many to be difficult because of the nature of control flow errors and the amount of hardware overhead associated with constructing the requisite detection logic. Examples of control flow errors include processing an incorrect sequence of valid instructions, improperly decoding and/or improperly executing an instruction, and vectoring a processor to an incorrect address. Control flow errors can be hardware induced, such as the erroneous calculation of an address or the faulty operation of the decode logic, or software induced, such as by viruses. It is generally accepted that detectors used in detecting data related errors such as error correction codes (ECC) are not adequately successful in detecting control flow errors. Other error detection methods that have been proposed include master/checker, sink check, and signature monitoring.
In master/checker error detection systems, a duplicate set of logic is provided to check the operation of a system. In essence, a boundary is drawn around a functional block of a system with transfers across the boundary being checked via comparison with the duplicate logic circuit. This provides excellent error detection, but more than doubles the amount of logic required. In addition, master/checker systems are prone to common mode errors wherein both the master and checker logic circuits produce the wrong data or execute the wrong control sequence. In such cases, the outputs of both circuits are the same, and no error is detected when the two outputs are compared.
In sink check systems, a sink detection circuit tries to verify that a required action for a particular command is executed. For example, sink detection logic for verifying that a command to write to a register was executed may be implemented by monitoring the write enable control to the register. However, sink logic does not provide extensive error coverage and is generally limited to simple control systems.
In signature monitoring systems, an instruction is considered part of an execution thread that consists of a series of processor-level instructions, i.e., machine code, with a known instruction execution sequence. Since the sequence is determined by the design and development of the software, i.e., the computer program, that will ultimately be executed by the RISC processor, a unique signature can be derived based on the operation codes for those instructions during development. This is called the reference signature. The reference signature code is used to verify the proper instruction execution sequence during system operations. During operations, a current signature is computed and compared with a pre-computed reference signature. The two signatures should be identical in the absence of a control flow error. It is noted that there are two methods of signature monitoring commonly used: horizontal and vertical signature monitoring. Horizontal monitoring checks the signature of every instruction executed by comparing the current signature with the reference signature. This method provides low detection latency because it validates correct execution for every instruction, but requires that the reference signature be supplied with each instruction. Thus, a trade-off occurs between optimizing the ability to detect errors, or error coverage, and the amount of increased overhead due to saving and processing signatures for each instruction. Vertical monitoring, on the other hand, checks the signature of a set of instructions. This method only adds overhead to the control flow when the signature is checked, but causes error detection latency to increase. Detailed discussion of signature monitoring can be found in numerous publications, including J. P. Shen and K. Wilken, "Concurrent Error Detection Using Signature Monitoring and Encryption," 1.sup.st International Working Conference on Dependable Computers in Critical Applications, Santa Barbara, Calif. August (1989).
Current technical literature document signature monitor applications on CISC processors. However, these implementations are enhancements that are external to the processor itself. This type of external implementation reduces the error coverage potential for signature monitoring because it is difficult to capture state changes that affect instruction execution flow, i.e., control branch operations, where these changes are not communicated outside the processor.
Therefore, a heretofore unresolved need existed in the industry for a control flow error detection system and method that provides improved error detection in the instruction execution flow of RISC processors with minimum hardware overhead.

Systems and methods for control flow error detection in reduced instruction set computer processors


The present invention involves a heat sink clip which engages a slot of a heat sink to press a power component into a heat sink of an electronic module, such as a power converter circuit for a vehicle. A power converter module for a vehicle comprises a casing having at least one heat sink with a plurality of fins, power converter circuitry disposed within the casing and including at least one power component; and a clip for pressing the power component into the heat sink. The clip has a first end engaging a slot of the casing and a second end extending from the first end with a resilient biasing that presses the power component into thermal contact with the heat sink. The casing slot includes a lip which retains the clip within the slot, and a sloped surface which facilitates entry of the clip. The clip has a generally L-shaped configuration for engaging the slot, with a corner that abuts a lip of the casing slot to retain the corner within the slot. The clip also includes an end flange for engaging the slot in an interference fit. A thermally conductive, electrically insulating layer is disposed between the power component and the heat sink, and the clip includes an articulated portion extending beyond said power component so that only the clip second end contacts the power component. The clip is made of a metallic material.

1. Field of the Invention
The invention generally relates to heat sinks for electronic circuits. More specifically, the field of the invention is that of attachment arrangements for maintaining thermal connection between electronic circuitry and heat sinks such as in power transformers and amplifier circuits for automobiles and other vehicles and other applications.
2. Description of the Related Art
In conventional vehicle power converters, such as those transformers and amplifier circuits for automobiles and other vehicles, the power transistors and rectifiers are used to scale down AC line voltage to suitable 12 volt DC currents. As a result of this step down transformer circuitry, the power transistors and rectifiers used in the circuit generate substantial amounts of heat. Conventionally, the casings of these units are built with heat sinks, typically on the lateral walls, so that the heat generated by the electrical components can be dissipated. Because of the space limitations in the vehicles, these casings are configured to minimize the amount of space occupied, resulting in the electrical components being closely positioned together within the casing often with little or no internal ventilation. The heat generating electrical components are placed into contact with the heat sink to dissipate the generated heat. In order to maximize the heat dissipation of the heat sink, it is important to maintain the direct physical contact of the power transistor or rectifier component against the heat sink material of the casing.
A conventional method of mounting the power transistor or rectifier components to the heat sink includes drilling a hole in the heat sink material and screwing down the component. Typically, this requires a physical extension of the component which is large enough to have a screw hole, and which is rigid enough to hold the body of the component against the heat sink when the screw fastens the component down. One difficulty with this arrangement involves matching the locations of the component screw hole and the hole of the heat sink, because the component is usually located at a fixed position on the circuit board. These complications can interfere with the quality of the connection of the component with the heat sink, can stress the electrical connections, as well as increasing the time needed to manufacture the unit.
Alternative methods of maintaining the thermal connectivity of the component and the heat sink involve screwing down a hold down bar or a clamp to hold the component in place, or forming a screw hole or channel in the power transistor or rectifier component so that the component may be directly screwed to the heat sink. These methods similarly have disadvantages in terms of material cost, manufacturing cost, and heat dissipation effectiveness. The additional cost of the screw and allocating manufacturing resources to providing the hole for the screw and the labor to install the screw increase the cost of the unit. Any loosening of the set screw will decrease the thermal connectivity of the component with the heat sink. Further, the location and placement of the screws must be carefully made so that other portions of the transformer or amplifier are not damaged.
Similar problems confront other types of electrical circuit devices. Computers, telecommunications equipment, medical imagining equipment, and other types of electronics include package semiconductors which generate heat during operation. Many varieties of clamping devices, some spring activated, are used in such circuitry to hold a semiconductor package in thermal contact with the heat sink. Typically, additional structural elements are needed on the semiconductor package or the circuit board to create the clamping effect. However, these required additional structural elements prevent such arrangements from being used with conventional semiconductor package or circuit board configurations.
What is needed is an effective method of maintaining the thermal connectivity of the heat generating component to the heat sink wall.


A hydraulic control device for rotating a cam shaft of an internal combustion engine has a sprocket wheel driven by an internal combustion engine, a couple member engageable with a cam shaft and supported by one end of the sprocket wheel and engaging in a central bore hole of the sprocket wheel, a magnet valve arranged so that the couple member is axially displaceable by a liquid pressure controlled by the magnet valve to bring about a relative rotation of the cam shaft relative to the sprocket wheel, and a main piston acting on the couple member and arranged so that the liquid pressure acts on the main piston. A hydraulic body is mounted on the drive wheel, and an axial piston pump is arranged in the hydraulic body and has axial bore holes and a plurality of additional pistons which slide in the bore holes and having outer rounded portions which contact a wobble plate. Outlet valves are arranged at an outlet side of the bore holes and connected to a pressure space defined by the main piston. The main piston and the couple member are arranged so that an element providing a mechanical force acting against a force of the main piston acts on the couple member.

The present invention relates to a hydraulic control device for rotating a cam shaft of an internal combustion engine.
More particularly it relates to a hydraulic control device which has a couple member which is longitudinally displaceable by pressure force and has a first toothing engaging a toothing at an inner circumference of a cam shaft and supported in a sprocket wheel driven by the internal combustion engine and a second toothing engaging with an inner toothing of a sprocket wheel bore, wherein the couple member is actually displaceable by a liquid pressure controlled by a magnet valve.
Hydraulic control devices of the above-mentioned general type are known in the art. One such hydraulic control device is disclosed in the German patent document DE-OS 32 47 916. In such a known control device in particular the pump and the magnet valve are arranged externally, which is relatively complicated particularly in view of the necessary pressure medium connections and also entails a considerable cost in construction.


Disclosed and claimed are shortening systems and methods for making and using the shortening system The shortening system can contain vegetable oil and a stearine fraction obtainable from the glycerolysis of a saturated fat or oil, such as a stearine fraction enriched with diglycerides, or at least one monoglyceride and/or diglyceride such as one which is normally solid at room temperature and/or such as one which is enriched with diglyceride. The shortening system has a synergistic amount of solids and crystal matrices and has surprisingly superior properties and imparts those surprisingly superior properties to food products, as well as provides food products with improved organoleptic properties. Chemically leavened and yeast-raised bakery products (e.g., savory crackers, biscuits basecakes, cookies etc.) which incorporate the shortening system so as to allow substantial nutritional improvements over partially hydrogenated fats while giving organoleptically improved properties are disclosed. The incorporation of the mono and diglyceride fractions into non-hydrogenated oils provide the formation of crystal matrices which allow functional aspects of the shortening system such as improved eating qualities (texture/taste) and improved stability in both the processing and the finished product, without the incorporation of positional and geometrical (trans) isomers of unsaturated fatty acids common to partially hydrogenated fats.

Currently in the U.S., partially hydrogenated fats are employed in the production of many chemically leavened and yeast-raised bakery products (e.g., cakes, crackers, cookies). The partial hydrogenation of domestic oils originating from soybean, cottonseed, corn, sunflower, and/or canola allow the chemical reduction of the unsaturated fatty acids to saturated fatty acids which provide greater oxidative stability.
Hydrogenation is a physical modification of these liquid oils, imparting thereto a solid fat content and an increased melting point, as saturated fatty acids are solid at room temperature whereas unsaturated fatty acids are liquid at room temperature As a result, the oils which are naturally liquid can be transformed into a semi-solid fat with a particular melting profile. To provide maximum eating pleasure with this form of the fats, the hydrogenation process of these fats is highly controlled and allowed to proceed only partially, that is, to allow only some of the unsaturated fatty acids and/or bonds thereof to be reduced to the saturated form. These types of fats and fatty acids are called "partially hydrogenated fats" or "partially hydrogenated oils" or "partially hydrogenated fatty acids".
In addition to the reduction of the unsaturated fatty acids to the saturated form, in partial hydrogenation, a side reaction occurs in which the natural form of the unsaturated bond (referred to as a cis isomer) will twist in the plane, to form what is now referred to as a trans isomer of the bond of the of the unsaturated fatty acid.
Generally, cis isomers are those naturally occurring in food fats and oils. Although very small amounts of trans isomers occur in fats from ruminants or can result from the deodorization step in refining of vegetable fats and oils, most trans isomers result from the partial hydrogenation of fats and oils. Also, it is possible for the unsaturated bond to move laterally along the fatty acid chain and this is referred to as a positional isomer. These isomers are formed at the high temperatures (e.g., 180.degree.-240.degree. C.) common during the hydrogenation reaction and when the Nickel catalyst typically employed during the hydrogenation reaction unsuccessfully introduces a hydrogen atom to both sides of the unsaturated bond. These isomers are rather stable and will then remain unless the hydrogenation reaction is continued until there is a complete reduction of the unsaturated fatty acids. Therefore, partially hydrogenated fat will always contain some proportion of these positional and geometrical isomers; and, as discussed herein, those isomers can present problems.
For instance, typically, shortenings employed in bakery products may contain 15-25% trans isomers. The use of these isomers has become more scrutinized by nutritional science in the last several years. There have been clinical studies reporting observed negative health effects correlated to the presence of trans fatty acids formed during the partial hydrogenation of oils, e.g., a positive correlation with coronary heart diseases an increase in the ratio of plasma low density lipoproteins (LDL) to high density lipoproteins (HDL) and thus a possible increase in the risk of coronary heart disease (see, e.g., Elias, B. A., Food Ingredients Europe: Conference proceedings, London, October 1994 (Publisher: Process Press Europe, Maarssen); Willet, W. C. et al., Lancet 341 (8845); 581-585 (1993); Khosla, P. et al., J. Am. Col. of Nutrition, August 1996, 15(4):325-339 (American College of Nutrition, NY, N.Y.)).
Thus, a problem in the art is the use of partially hydrogenated fats and oils in foodstuff; and, a related problem is the need for a suitable replacement for partially hydrogenated fats and oils in foodstuff.
Fats or oils which contain naturally a sufficient amount of saturated fatty acids to form solids include palm oil, palm kernel oil, coconut oil, lard, and tallow.
However, in the U.S. the use of tropical fats or oils is basically limited to a few non-dairy and confectionery applications due to concerns relating to their naturally high content of short chain saturated fatty acids. Also the application of animal fats is restricted due to such issues religious dietary restrictions, e.g. rabinical law for kosher certification.
Thus, the problems presented by partially hydrogenated fats or oils cannot be addressed by merely employing naturally saturated fats or oils; and, the use of naturally saturated fats and oils present problems. It would be desirable to be able to employ naturally saturated fats or oils such as tropical fats or oils in more foodstuff, especially in more foodstuff in the U.S. than is currently typical, without triggering the bases for the concerns relating to their content of short chain saturated fatty acids.
Another possible replacement for partially hydrogenated fats or oils is interesterified fats based on liquid oils and fully hydrogenated fats. These interesterified fats are from a process wherein the fatty acids on the triglycerides of two fats are randomized, resulting in a triglyceride composition that can provide a suitable melting profile.
This option presents problems insofar as the food manufacturor or processor would be required to include the fully hydrogenated fat on the product label, and the ultimate consumer may likely associate trans isomers with the full or complete hydrogenation process, such that the food product would likely not be commercially successful.
Polyunsaturated fatty acids are considered a highly essential component of a healthy diet according to the U.S. Food and Nutritional Board's Recommended Dietary Allowances (tenth ed. 1989) (e.g., amound of dietary linoleic acid for humans should be a minimum of 2% of dietary calories and preferably 3%; and, the requirement for linolenic acid has been estimated to be 0.54% of calories)
While it would be desirable to replace partially hydrogenated fats simply with natural vegetable oils since natural vegetable oils have a relatively high ratio of polyunsaturated to saturated fatty acids, attempts to do this so far have also proven to be quite unsatisfactory in regard to either the processing or organoleptic (e.g., taste, texture, eating) aspects of the food product. For example, there may be insufficient oil retainment in the dough or batter resulting in separation of oil. Or, oils may depart from the food product too quickly in the mouth, imparting an off-taste and off-feel to the product as it is being consumed.
Another related problem in the preparation of food products is "bloom"; a phenomenon wherein certain fats or oils permeate to the surface of a food product, such as a cookie, and leave a scoring on the surface of the food product. This "bloom" renders the food product not visually appealing and ergo not consumable. It would be desirable to provide a shortening system which does not suffer from "bloom."
In the production of food surfactants or emulsifiers, a triglyceride is reacted with glycerol and to form a reaction product containing the desired product, the monoglycerides. Thus, the reaction product is typically subjected to a treatment to isolate a monoglycerides product from a diglycerides and triglycerides product; the diglycerides and triglycerides product is considered a by-product of the reaction of a triglyceride with a glycerol to obtain monoglycerides for surfactants or emulsifiers. The diglycerides and triglycerides product is sometimes discarded, or recycled back to a reactor wherein the reacting with glycerol is occurring so as to enhance the production of monoglycerides (see, e.g., Lauridsen, "Food Surfactants, Their Structure And Polymorphism Technical Paper TP 2-1e Danisco Ingredients, Braband Denmark, and references cited therein).
It would be desirable to provide alternative uses for this by product from emulsifier or surfactant preparation
Systems functioning as or containing fats or oils have been proposed (see, e.g., CN 1078353, U.S. Pat. Nos. 5,458,910, 5,612,080, 5,254,356, 5,061,506, 5,215,779, 5,064,670, 5,407,695, 4,865,866, 4,596,714, 4,137,338, 4,226,894, 4,234,606, 4,335,157, 3,914,452, 3,623,888, DD 291240A). However, these systems have not sufficiently addressed the problems in the art; and, these systems have not been reported to provide the synergistic, and surprisingly superior properties, including improvement in organoleptic properties of foodstuff, of the present invention.

Shortening system, products therewith, and methods for making and using the same


A vehicular structure includes: a first member formed in a tubular shape and having protrusions on an outer periphery thereof; and a second member formed in a tubular shape and having a locking wall with a hole in which the first member is inserted. The first member is joined to the second member such that a portion of the first member that is inserted in the hole of the second member is expanded, and the protrusions are in contact with the locking wall of the second member.

A metal called high-tensile-strength steel, which has a low specific gravity and exhibits high strength, is used to reduce weight and to improve safety of vehicles. Using such high-tensile-strength steel is effective for weight reduction and safety improvement of vehicles, but the effect of weight reduction is limited as compared with materials of further low specific gravity, such as aluminum alloy. In addition, using high-tensile-strength steel causes problems due to its high strength, such as decrease in formability, increase in forming load, decrease in dimensional accuracy, and decrease in rigidity involved by thinning. In recent years, extruded materials, cast products, and press-formed products of aluminum alloy, which has a lower specific gravity than steel, have been used for vehicle parts to solve the above problems. Aluminum alloy has a low specific gravity and thus is effective for reducing weight of vehicles, but is lower in strength and higher in price than high-tensile-strength steel. Therefore, multi-materialization is being promoted by using steel parts, such as high-tensile-strength steel parts, in combination with aluminum alloy parts.
In such multi-materialization, an important issue is to join dissimilar metals together, such as steel parts and aluminum alloy parts. For example, JP 2016-147309 A discloses a method of joining members that enables joining of dissimilar metals in multi-materialization by utilizing an elastic body. Specifically, in the method of joining members of JP 2016-147309 A, an aluminum pipe is inserted into a hole of a steel part, and a rubber member (an elastic body) that has been inserted inside the aluminum pipe is applied with a pressure to be deformed. Thereby, the aluminum pipe is enlarged and deformed, so that the steel part and the aluminum pipe are crimped together.


Sensors, systems, and methods for monitoring environmental conditions, such as physical, electromagnetic, thermal, and/or chemical parameters within an environment, over extended periods of time with the use of one or more electromechanical sensing devices and electronic circuitry for processing an output of the sensing devices. The sensing devices each include a cantilevered structure and at least one contact configured for contact-mode operation with the cantilevered structure in response to the cantilevered structure deflecting toward or away from the contact when exposed to the parameter of interest. The cantilevered structure has at least first and second beams of dissimilar materials, at least one of which has at least one property that changes as a result of exposure to the parameter.

The present invention generally relates to electromechanical devices. More particularly, this invention relates to electromechanical devices and electromechanical device-based sensors, systems, and methods capable of monitoring environmental conditions, such as physical, electromagnetic, thermal, and/or chemical parameters within an environment.
Wireless sensors are capable of high reliability, efficiency, and performance and enable ambient intelligence, total visibility, and smart adaptive systems. As such, wireless sensors have found uses in a wide range of applications including supply chain and logistics, industrial and structural monitoring, healthcare, homeland security, and defense. Wireless sensors also find use as nodes of wireless networks, including the Internet of Things (IoT) that connects objects together and to people. Wireless sensors typically include a battery or other energy source.
Generally, it is desired to minimize the power dissipation, size, and cost of wireless sensors by minimizing their power requirements. Wireless sensors can be equipped with integrated miniature batteries or capacitors as a dedicated on-board power source, as well as configured for operation without a power storage device. In many applications, battery less operation may be preferred or required due to lack of battery replacement feasibility or stringent cost, form factor, and lifetime requirements. One approach to address this need is scavenging energy from environmental sources such as ambient heat, radio and magnetic waves, vibrations, and light, provided that at least one of these parameters is adequately available. Another approach is to remotely power a sensor by inductive or electromagnetic coupling, in which case energy may be optionally stored on an integrated capacitor so that sensor operation may occur over a short period of time prior to the capacitor becoming completely discharged. Finally, there are sensors that do not need any external energy source for sensing because they operate based on chemical reactions or mechanical events resulting in a color change or another change in their properties that can be detected by visual inspection or with use of an electronic detection system. The latter types of wireless sensors are generally in the form of sensor labels and do not readily lend themselves to automation.
U.S. Pat. Nos. 7,495,368, 7,619,346, 7,827,660, 7,907,037, 8,487,508, and 8,677,802 and U.S. Patent Application Publication No. 2017/0102249 disclose digital micro-electro-mechanical-system (MEMS) sensing devices that can be manufactured and packaged at wafer-level with integrated circuits to yield a sensing module. The sensing devices can be fabricated to form arrays configured to respond to different levels of an environmental condition or parameter to cumulatively measure the environmental condition.

Sensing devices, sensors, and methods for monitoring environmental conditions


A binding strap assist mechanism. The binding strap assist mechanism can be retrofit onto standard snowboard binding straps to bias the binding straps and an open configuration. Binding straps pass through the binding strap assist mechanism so that tensile stress along the length of each of these binding straps during use is not significantly conveyed to the binding straps assist mechanism. The tensile stress are thus isolated to the binding straps which are intended to carry such stresses. The present invention provides a safe and convenient feature to snowboard bindings and other bindings. Safety is achieved because even if the binding strap assist mechanism breaks or fails to function, the binding straps will continue to function as normal.

Snowboard bindings secure a snowboarder's foot onto his or her snowboard. Current bindings are effective during snowboarding, but still cumbersome to bind to a foot.
Snowboard binding need to be removed often, unlike ski bindings. This is because of the nature of most chair lifts. Upon boarding a chair lift, one foot needs to be removed from the snow board binding and reattached after exiting the chairlift. The reattachment of the one foot into the binding is preferably done rapidly and efficiently. Upon chairlift egress, the snowboarder typically slides down a slope with one foot bound and one free. The snowboarder must stop to re-attach the binding prior to commencing further down-hill travel.
Difficulty is found when the snow board binding strap overlays and area where the foot is to be inserted. This requires the snowboarder to bend over and physically remove the binding strap then insert the foot. This may sound simple, but when one is wearing bulky snow pants and a thick jacket, bending is not easy. On a slippery snow-covered hill there may be movement of the snowboard down the hill during this process. Accordingly it takes a special degree of skill to efficiently move the binding strap from the foot area, insert the foot into the binding while bent over, and to attach the binding strap. Both novices and experienced boarders recognize the cumbersome nature of re-attaching the binding every time a chairlift is used.
U.S. Pat. No. 6,679,515 B2 to Carrasca discloses a mechanism that helps the binding strap sets to more likely be free from the foot area. In particular, each binding strap set includes two sides. One side has a buckle and another side has ribs that engage the buckle. A hinge attaches the side with the buckle to the snowboard binding. The hinge enables the one side of the binding strap to flay open and thus enable the foot to be placed into the foot area of the binding.
While this represents a step forward in the art of binding straps, several drawbacks of this design are apparent. In particular there is a possibility when the binding strap is open such as during an exit from the chairlift that it could interfere with stability of the snowboard. There is also a possibility that the hinged side of the binding strap could flop inwards and cover the foot area thus providing little benefit to a snowboarder that must bend over and remove the strap from the foot area. A third drawback is that the hinge is in line with the strap. Every time the strap is tightened stress is endured by the hinge this creates a situation where either failure of the hinge is possible or very robust hinges are required.
U.S. Pat. No. 7,487,992 B2 to Pascal et al. discloses a pivoting binding strap hinge that biases a snowboard strap into the open position. While the pivoting binding strap hinge performs multiple functions, it also suffers from the drawback that the pivot mechanism and biasing mechanism are in line with the strap. This causes the mechanisms to endure stress applied by the strap.
U.S. Pat. No. 8,597,318 B2 to Hall discloses a strap design for snowboard bindings. Each strap is bifurcated with materials of varying thicknesses to enable the strap to naturally bias into an open position. This also represents a step forward in the art of snowboard bindings however, there are drawbacks. One limitation is that the width of the binding strap near where it's mounted to the snowboard binding is much greater than the width of a normal strap. This is cumbersome.
What is desired is a better way to bias a snowboard binding strap into an open position. It is also desired is a way of biasing the snowboard binding strap into an open position which is reliable, not cumbersome, and that can retrofit on existing snowboard straps.

Binding strap assist mechanism with a torsion spring


Disclosed is a nonvolatile electrically-erasable semiconductor memory having an array of storage cells divided into sub-arrays, where the memory is formed on a semiconductor substrate doped with a first type of conductive impurity having a first well doped with a second type of conductive impurity. The storage cells for each sub-array are formed in a pocket well formed in the first well and doped with the first type of conductive impurity. A programming operation is performed by applying a programming voltage, such as 18 V, to the control gates of only those storage cells that are selected to be programmed, applying a ground level voltage to the pocket well corresponding to the selected storage cells, and applying an anti-programming voltage, such as 7 V, to the pocket wells corresponding to the storage cells that are not selected for programming. An erasing operation is performed by applying a ground level voltage to the control gates of the storage cells selected for erasure, applying an erasing voltage, such as 20 V, to the pocket well corresponding to the selected storage cells, and applying a prescribed voltage, such as from 4 V to 14 V, to the pocket wells corresponding to the storage cells that are not selected for erasure.

1. Field of the Invention
The present invention concerns a nonvolatile semiconductor memory and, more particularly, an electrically erasable and programmable read-only memory (EEPROM).
2. Description of the Related Art
As a nonvolatile semiconductor memory device becomes more highly integrated in order to increase storage capacity and raise the operating speed, new problems appear. A nonvolatile semiconductor memory is constructed with a plurality of storage cells (memory cells), which are each composed of a floating gate transistor. Each floating gate transistor, in turn, consists of a floating gate, a control gate, a source and a drain. The storage cells are arranged in a matrix consisting of rows and columns. The control gates for each row of storage cells are all connected to a single shared word line while the drains for each column of storage cells are connected to a common bit line. A memory cell array will thus consist of a plurality of the storage cells together with a plurality of word and bit lines by which data is stored and read from the cells of the array.
In order to enhance the operating speed of a nonvolatile semiconductor memory, the data stored in the storage cells connected with a selected word line are simultaneously read out through the plurality of corresponding bit lines in what is called a page read. The data read out during the page read are stored into a plurality of data latches called page buffers. In contrast, the write operation (programming) is achieved by sequentially storing data into the page buffers through a data input/output (I/O) pad or terminal, and then simultaneously transferring the data stored in the page buffers into the storage cells connected to a selected word line. This method for writing data into a memory array is called page programming. The page read and programming operation are described in further detail in commonly-assigned Korean Laid-Open Patent Publication No. 94-18870 published on Aug. 19, 1994.
To describe the page read, programming and erasing operations in greater detail, page programming data into memory cells is achieved by applying a high level programming voltage, e.g. 18 V, to a word line connected to the control gates of the memory cells and a ground level voltage to the respective bit lines connected with the channels of the memory cells so that the voltage difference between the control gates of the memory cells and the channels causes electrons to penetrate the thin oxide film, otherwise known as the Fowler Nordheim Tunneling phenomenon, in order to reach the floating gate thereby changing the threshold voltage of the transistor controlled by the control gate. The erasing operation is achieved by reversing the process and applying an erasing voltage, typically 20 V, to a large block of memory cells and the ground level voltage to the word line connected to the control gates so that the voltage difference between the transistor wells of the cells and the control gates of the transistors causes the electrons stored in the floating gates to tunnel away from the floating gates in order to discharge the floating gates and once again change the threshold voltage of the transistors in the block. Since the threshold voltage of each memory cell has a negative or positive value depending on whether it is in a programmed or an erased state, the read operation is achieved by applying zero voltage to the control gate of the memory cell and sensing the voltage difference between the drain and source of the cell. This type of nonvolatile semiconductor memory is called flash memory and is described in the papers entitled "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme" and "A 35 ns Cycle Time 3.3 V Only 32 Mb NAND Flash EEPROM", IEEE Journal of Solid-State Circuits, Vol.30, No. 11, Nov., 1995.
FIG. 1 illustrates a conventional memory cell array with a control circuit, where the array has 8,192 rows and 4,096 columns for 32 megabits (4,096.times.8,192) of memory cells. The memory cell array is divided into blocks B1-B512 of 64K each (4096.times.512), where block B1 is shown in greater detail. The control gates of the storage cells are connected through 8,192 word lines and the drains are connected through 4,096 bit lines. The block B1 includes NAND cell units NU0, NU1, . . . , NU4095 wherein each of the NAND cell units consists of 16 storage cells MO-M15 connected in series between the source of a first selection transistor ST1 and the drain of a second selection transistor ST2. The drain of each first selection transistor ST1 is connected to a corresponding bit line BL0, BL1, . . . , BL4095 through a resistor (not shown). The source of the second selection transistor ST2 is connected with a common source line CSL.
In each of the row blocks B1-B512, the control gates of the first selection transistors ST1 for each of the NAND units NU0-NU4095 are all commonly coupled to a first selection line SSL. Similarly, the control gates of storage cells M0-M15 of each NAND units NU0-NU4095 are all commonly coupled to a corresponding word line WL0-WL15, respectively. And the control gates of second selection transistors ST2 are all coupled in common to a second selective line GSL.
The first selective line SSL is driven by a first row decoder 102A and the second selective line GSL is driven by a second row decoder 102B. Further, the even numbered word lines WL0, WL2, . . . , WL14 are also driven by the first row decoder 102A while the odd numbered word lines WL1, WL3, . . . , WL15 are driven by the second row decoder 102B. Even numbered bit lines BL0, BL2, . . . , BL4094 are coupled to lower page buffer 101B while odd numbered bit lines BL1, BL3, . . . , BL4095 are coupled to upper page buffer 101A. The upper page buffer 10A and lower page buffer 101B each have internal data latches which temporarily store input data signals received through the input/output pins of the semiconductor memory device in order to perform various functions, such as controlling the execution of data programming operations as well as read-out and erase operations.
FIG. 2 illustrates the physical structure of a row of stacked memory cells. In the physical structure, a second conductive n-type well 202 is formed on a first conductive p-type semiconductor substrate 201. A first conductive-type pocket well 203 is placed on the second conductive n-type well 202. Each of the memory cells has a floating gate 206 and a control gate 208 in an active region. The individual stacked memory cells are separated from each other by a field insulator film 204. The reference number 208 also represents a word line because all the control gates in a given row are connected to the same word line. The floating gate 206 and control gate 208 are separated from each other by insulator film 207, such as ONO (Oxide/Nitride/Oxide). An insulator film 209 is formed on the word line 208 and the bit lines BL0-BL4095 are formed on top of insulator film 209. The thin oxide film 205 represents the area where electrons tunnel through to the floating gate 206.
In the nonvolatile semiconductor memory of FIG. 2, the second conductive n-type well 202 and the first conductive-type pocket well 203 are electrically connected to each other and a ground potential voltage is applied to them in order to perform data programming operation. The high level programming voltage is applied to the word line 208 connected to the control gates of the memory cells and the data are input through the bitlines BL0-BL4095 which are connected to the channels of the memory cells.
When some of the memory cells connected to a selected word line are not to be programmed, the VCC or higher voltage is directly or indirectly applied to channels corresponding to the memory cells so as to prevent those cells from being programmed.
Note that as the capacity of nonvolatile semiconductor memories is continuously improved by integrating the memories on a very large scale, that there is necessarily a resulting increase in the number of memory cells connected to a single word line and, accordingly, an increase in the number of memory cells that required to not be programmed during a given programming operation. This increase in the number of cells that are not to be programmed leads, in turn, to an increase in the power consumption of the bitlines which supply the channel voltage that prevents the state of the memory cell from being programmed. In addition, when the channel voltage is dropped, the memory cells that are required not to be programmed can be erroneously programmed by the voltage change causing corruption of the stored data.
For a data erasing operation, the ground voltage is applied to the word line 208 connected to the control gates of the memory cells to be erased. The erasing voltage (20 V) is applied to the second conductive n-type well 202 which is electrically connected to the first conductive-type pocket well 203 thereby erasing the data in all the memory cells connected to the word line. The increased level of integration of the memory device results in a larger number of memory cells connected each word line which causes both greater power consumption and a deterioration of the reliability of the device because a larger number of memory cells must be erased or programmed in order to make a correct in a small amount of data.
U.S. Pat. No. 4,878,199 is directed to solving the problems described above for nonvolatile semiconductor memory. The nonvolatile semiconductor memory proposed in U.S. Pat. No. 4,878,199 has opposing first and second conductive-type wells that are formed on a substrate. The first and second wells each simultaneously form the same number of memory cells which are jointly connected to the corresponding bit and word lines. One of the first and second wells forms an auxiliary memory cell array, where a back bias voltage is applied to the auxiliary memory cell array in order to increase the threshold voltage of the memory cells and prevent the redundant data read-out and operating data of the auxiliary memory cell array that is necessary when changing data of the main memory array. Thus memory faults are avoided and the memory device is more reliable.
However, the above method suffers from the disadvantage that two memory cells must be provided for storing one bit of data which cuts the memory density achieved through large scale integration in half. Also, the breakdown voltage at the bit line junction of the auxiliary array must be raised above the value of the bit line voltage plus the back bias voltage in order to prevent breakdown of the memory cell transistors in the auxiliary array.
Generally, in the memory cell array area, a high level erase voltage of 20 V is applied to a large number of memory cells during an erase operation, and is thus transferred to the peripheral circuits outside of the memory cell array, which results in junction breakdown or destruction of the gate oxide films in the peripheral circuits. The entire area of the cell array is formed by n-type wells, and the pocket wells are p-type wells formed inside of the n-type wells so as to prevent the high voltage applied to the p-type wells from being transferred to the peripheral circuitry during the data erasing operation.
However, as the density of nonvolatile semiconductor memory devices is increased to improve capacity, the number of rows and columns of the cell array also increases, thus increasing the length of the word lines. Typically, the word lines of a nonvolatile memory are made of polysilicon which has a sheet which is on the order of several tens of ohms. When the length of the word line is increased, the resistance of the word line also becomes greater so that the programing or read-out voltage drops when it is applied to the farthest memory cells which malfunction as a result. In addition, the erasing operation is performed on the level of blocks B1-B512, which means that an entire block must be erased and reprogrammed in order to correct a single byte of data.
The number of memory cells within the each of NAND units NU0-NU4095 is usually eight or sixteen. In large scale integration, the memory density is increased by using 32 or 64 memory cells in a single NAND unit. The size of a page of memory is usually 512 bytes, whereby the block size is 4K bytes or 8K bytes. Currently, in order to correct one byte of data, the entire memory block of 4K bytes or 8K bytes must be erased and then reprogrammed. This process for data correction is not only complicated and time-consuming, but also shortens the operational life of the memory cells.
Furthermore, the increase in memory density also increases the number of memory cells connected to the same word line which causes the page size to increase. The number of memory cells connected to the unit string also increases resulting in an increase in block size. For example, in the case of a 256 Megabit NAND-type flash memory, the size of a page is 2K bytes, and if the number of memory cells of the unit NAND memory are 32, then the size of a block is 64K bytes.
Also, since the number of cells that must be erased and reprogrammed in order to correct a byte of data is increased, the power consumption to perform an erase is also increased and the cells which are not required to be erased and reprogrammed are considerably deteriorated in terms of the their operational lifetime due to the repeated erasing and reprogramming operations. Furthermore, in the worst case for erasing and reprogramming a block, when only one bit data needs to be reprogrammed and the remaining data are not required to be reprogrammed, the back bias voltage used to prevent cells from being reprogrammed must be applied to all the remaining bit lines, which also leads to power consumption and additional operation time for charging the additional bitlines.

Nonvolatile semiconductor memory having sub-arrays formed within pocket wells


A projector includes a projection optical device and a projection position adjusting device that includes a fixed member defining a hole having a step portion, a first plate that supports the projection optical device and a second plate disposed between the fixed member and the first plate. The projection position adjusting device further includes a connecting member having a step and being disposed in the hole of the fixed member and connected to the first plate, and an urging member disposed between the connecting member and the step portion of the hole of the fixed member. The urging member urges the step portion of the hole and the step of the connecting member away from each other, and urges the first plate into direct contact with the fixed member.

1. Technical Field
The present invention relates to a projector.
2. Related Art
There is known a projector that modulates, according to image information, a light beam emitted from a light source and magnifies and projects the light beam on a screen using a projection optical device.
In such a projector, the light beam is tilt-projected upward with the projector fixed in a low position, tilt-projected downward with the projector fixed in a high position, and, besides the projection in the vertical direction, tilt-projected in the horizontal direction. Therefore, there is known a projector including a projection position adjusting device that moves, with respect to an optical system such as an optical modulation device, a projection optical device in a direction orthogonal to a direction in which a light beam is irradiated (a projecting direction) (see, for example JP-A-2006-133419).
The projection position adjusting device disclosed in JP-A-2006-133419 includes a fixed plate, a first moving plate that moves in the vertical direction and the horizontal direction in a plane orthogonal to a projecting direction, a second moving plate that engages with the first moving plate and moves in the horizontal direction together with the first moving plate, an adjusting and moving unit that moves the first moving plate and the second moving plate, and an auxiliary plate that is connected to the fixed plate and holds the first moving plate and the second moving plate between the auxiliary plate itself and the fixed plate. The fixed plate, the first moving plate, the second moving plate, and the auxiliary plate are stacked and arranged in the projecting direction in this order. Plural urging members are disposed between the first moving plate and the second moving plate. The first moving plate is urged to the fixed plate by the urging members to bring the first moving plate into contact with the fixed plate.
With such a configuration, backlash of the first moving plate (backlash of the projection optical device supported by the first moving plate) is prevented. Even when the projection optical device is moved by the projection position adjusting device, shift of a back focus position of the projection optical device is prevented and focus accuracy of a projected image projected from the projector is maintained.
However, the projection position adjusting device disclosed in JP-A-2006-133419 adopts the configuration in which the first moving plate and the second moving plate are supported by using the auxiliary plate in addition to the fixed plate and the first moving plate is brought into contact with the fixed plate by the urging members. Therefore, because a large number of members are used, it is difficult to realize a reduction in size and weight of the projection position adjusting device.

Projector with a projection position adjusting device


The lightning rod of the present invention is an absorbed type lightning rod which absorbs all lightning stroke current. This absorbed type lightning rod includes a conductive pole, a circular cone-shaped primary rod having an acute point, placed on the top of the pole, and a secondary rod having an acute point lower than that of the primary rod. In this lightning rod, the lightning induction of the primary rod is enhanced by the secondary rod.

1. Field of the Invention
The present invention relates to absorbed type lightning rod which absorbs lightning discharge current and which discharges the current to the ground to prevent the damage due to lightning, and an absorbed type lightning discharging apparatus utilizing the lightning rod.
2. Description of Related Art
When the thunder clouds approach, a conductive sharp material at the ground starts discharge to the thunder clouds (corona discharge or upward streamer), and the thunder clouds also start discharge to the conductive sharp material (downward streamer). Further, when insulation of air is lost under some weather condition, both discharges are coupled (called coupled streamer). This phenomenon is called cloud-to-ground discharge or lightning stroke. As the tip of the sharp material is more acute, the discharge to the thunder clouds occurs more.
Some conventional lightning rods are shown in FIGS. 1A, 1B, 2, 3A, 3B. As shown in FIGS. 1A and 2, a lightning rod B receives the lightning discharge current E (hereinafter called lightning stroke current) due to the lightning stroke X at a point, and discharges the current E to the ground. The lightning rod B also splashes the lightning stroke current, which means the lightning rod cannot absorb, (hereinafter called splashed lightning current E1) outsides the certain area (safety area). From the research results, it is well known that the corona discharge occurs more and lightning absorptivity becomes higher as the point of the lightning rod B is more acute. Accordingly, the point of the lightning rod B is preferably acute, and generally, "Franklin Rod" that is a circular cone-shaped pointed rod is used.
The lightning rod B has higher lightning induction and higher lightning absorptivity as the point thereof becomes more acute; however, the splashing area of the splashed lightning current E1 becomes narrow. Therefore, the point angle is made approximately 90 degrees to secure.
The modified lightning rod is disclosed in Japanese Patent Laid-open No. Hei 5-121192. This rod is that as shown in FIGS. 3A, 3B, a ring B1 is provided at the middle of the lightning rod B and that the angle between the point of the lightning rod and the circumference of the ring B1 (hereinafter called splash angle) is in the range of 90-180 degrees. For example, in FIG. 3A, the splash angle is 90 degrees, and in FIG. 3B, it is 126 degrees. In this lightning rod B, the point angle of the lightning rod B1 is made 60 degrees to maintain the lightning induction and the safety area widen owing to the ring B1; however, since the splashed lightning current E1 still exists, the secondary disaster due to the splashed lightning current E1 struck the lightning rod B1 cannot be avoided.
The modified lightning rod is also disclosed in Japanese Laid-open No. Hei 1-10600 and French application No. 9212860. The object of these inventions is to enhance the lightning induction by modifying the shape of the point of the lightning rod but the prevention of the secondary disaster is not the object.
The lightning stroke current conducted to the ground with the lightning rod B momentary becomes large, and very high potential is generated at an earth electrode C in the ground (see FIG. 2). The conventional earth electrode C is a thin metal plating rod having a conductive plate as a primary electrode and it is driven to the ground until the desired earthing resistance (Japanese standard is less than 10 ohms) is obtained. Accordingly, the earthing resistance in conformity with the standard is obtained but the instantaneous lightning stroke current cannot instantaneously and smoothly be discharged to the ground. In result, the lightning stroke current is stopped at the earth electrode C and flows back to the lightning rod B (see FIG. 1B). This reverse current E2 generates the flush over and the excess electromagnetic induction. Moreover, it generates the Joule's heat, which induces the tertiary disaster such as the damage of the lightning rod B.
Further, since the earth electrode C such as a conductive plate and a metal rod is only driven to the ground, the some space is formed between the earth electrode and the ground, which decreases the discharge effect.
The lightning stroke current absorbed by the lightning rod flows through the surface of the conductive wire. Conventionally, since the lightning rod and the earth electrode are coupled only with a conductive wire, the lightning stroke current is leaked from the surface of the conductive wire. If the object to be protected is a building, the leakage current is not a problem. However, if the object to be protected is an antenna or electric line, the leakage current causes the bad influences to the object to be protected.

Absorbed type lightning rod and absorbed type lightning discharging apparatus


An improved data compression method and apparatus is provided, particularly with regard to the compression of data in tabular form such as database records. The present invention achieves improved compression ratios by utilizing metadata to transform the data in a manner that optimizes known compression techniques. In one embodiment of the invention, a schema is generated which is utilized to reorder and partition the data into low entropy and high entropy portions which are separately compressed by conventional compression methods. The high entropy portion is further reordered and partitioned to take advantage of row and column dependencies in the data. The present invention enables not only much greater compression ratios but increased speed than is achieved by compressing the untransformed data.

Data compression systems, which encode a digital data stream into compressed digital code signals and which decode the compressed digital code signals back into the original data, are known in the prior art. The methods utilized in data compression systems serve to reduce the amount of storage space required to hold the digital information and/or result in a savings in the amount of time required to transmit a given amount of information. For example, the extensive transactional records accounted for by companies such as banks and telephone companies are often stored for archival purposes in massive computer databases. This storage space is conserved, resulting in a significant monetary savings, if the data is compressed prior to storage and decompressed from the stored compressed files for later use.
Various methods and systems are known in the art for compressing and subsequently reconstituting data. For example, a compression scheme used pervasively on the Internet today is "gzip," designed by Jean-Loup Gailly. See "DEFLATE Compressed Data Format Specification version 1.3", RFC 1951, Network Working Group May 1996; "GZIP file format specification version 4.3," RFC 1952, Network Working Group, May 1996. Gzip utilizes a variation of the well-known LZ77 (Lempel-Ziv 1977) compression technique which replaces duplicated strings of bytes within a frame of a pre-defined distance with a pointer to the original string. Gzip also uses Huffman coding on the block of bytes and stores the Huffman code tree with the compressed data block. Gzip normally achieves a compression ratio of about 2:1 or 3:1, the compression ratio being the size of the clear text relative to the size of the compressed text.
Gzip is a popular but suboptimal compression scheme. Nevertheless, the inventors, while conducting experiments on compressing massive data sets of telephone call detail records, managed to achieve compression ratios of around 15:1 when using gzip. The substantial reduction in size effected by merely using a conventional compression technique such as gzip suggested to the inventors that additional improvements to the compression ratio could be devised by a careful analysis of the structure of the data itself.

This patent is subject to a terminal disclaimer.