An exhaust system component (5) is provided for an exhaust system (1) of an internal combustion engine, especially of a motor vehicle, with an inner shell (6), which defines an exhaust-gas-guiding inner area (7), with an outer shell (8), which is arranged on an outer side of the inner shell (6) turned away from the inner area (7), with a cavity formed between inner shell (6) and outer shell (8), and with heat insulation (10) arranged in the cavity (9). The heat insulation of the component (5) includes insulation (10) having at least one microporous molding (molded body) (11).

Such components of exhaust systems are, for example, exhaust gas treatment means, for example, catalytic converters, particle filters and mufflers, inlet elbows, tail pipes as well as tube sections for connecting exhaust gas treatment means, elbows and tail pipes. For reducing obnoxious emissions of an internal combustion engine, it is important for the exhaust gas purifying means of the exhaust system to reach its operating temperature as fast as possible in case of a cold start of the internal combustion engine. This can especially be supported in that the exhaust system or its components are heat insulated towards the outside to thus reduce the radiation of heat into the environment. At the same time, in vehicle applications, vehicle components that are arranged adjacent to the exhaust system are protected against overheating.

Eberspächer Exhaust Technology GmbH & Co. KG


A simplified cell design is provided for a battery utilizing the 18650 form-factor, the simplified cell design reducing manufacturing cost, battery weight and the risk of shorting between the battery case and the battery terminal. In the cap assembly of the disclosed battery, the safety vent element, which is recessed relative to the top of the cell case, also serves as the battery terminal. Additionally, the insulating gasket positioned between the cell case and the cap assembly is designed to cover a large portion of the outer surface of the safety vent/battery terminal.

Batteries have been used for decades to supply power to a variety of different electrical and electro-mechanical devices. Early batteries, referred to as disposable batteries, were simply used until depleted and then discarded and replaced with one or more new batteries. A newer type of battery, referred to as a rechargeable or secondary battery, is capable of being recharged and then reused, therefore offering economic, environmental and ease-of-use benefits compared to a disposable battery.
For many applications in which multiple batteries are required, a battery pack is used in which the batteries are housed within a single or multi-piece housing. Although initially battery packs were relatively small, for example housing just a few batteries, many battery packs used today, such as those used in hybrid and electric vehicles, house tens to thousands of cells. As such, battery weight is of critical importance, as are manufacturing simplicity and cost. Additionally, due to the large number of cells required for such a sizeable battery pack, it is important that the batteries can be safely and easily transported, stored and assembled with minimal risk of battery shorting. Accordingly, what is needed is a simplified cell design that reduces manufacturing cost, weight, and the risk of shorting. The present invention provides such a design.

Cell cap assembly with recessed terminal and enlarged insulating gasket


This invention provides a simple vacuum level switch to be used inside the feedhead's vacuum plenum to detect when the vacuum level exceeds a predefined threshold. This switch is composed of an opening in the plenum that is covered by a cap which is in turn spring-loaded against the opening. The mechanical properties of the spring are such that the cap is pushed away from the opening by ambient air pressure at the point when the vacuum threshold has been reached during sheet acquisition. A Hall Effect or optical sensor is used to detect this motion and the corresponding signal is sent to the feeder controller. This enables more intelligent control of the feeder while also providing an inexpensive method for tracking sheet acquisition times.

While the present invention can be used in any paper feeding marking system, it will be described herein for clarity as used in electrostatic marking systems such as electrophotography or xerography.
By way of background, in marking systems such as xerography or other electrostatographic processes, a uniform electrostatic charge is placed upon a photoreceptor belt or drum surface. The charged surface is then exposed to a light image of an original to selectively dissipate the charge to form a latent electrostatic image of the original. The latent image is developed by depositing finely divided and charged particles of toner upon the belt or drum photoreceptor surface. The toner may be in dry powder form or suspended in a liquid carrier. The charged toner, being electrostatically attached to the latent electrostatic image areas, creates a visible replica of the original. The developed image is then usually transferred from the photoreceptor surface to an intermediate transfer belt or to a final support material such as a paper sheet. When the paper is fed to the system from a paper stack of a feeder mechanism, some papers could be off the home position by many mm and these fed paper sheets need to be rapidly and properly fed.
In high speed commercial printing machines, precise timing and positioning of fed paper is critical to producing consistently high quality images. Generally, in the sheet feeding assembly, an apparatus blows gas or air against a sheet stack on a sheet stacking unit; then the sheet feeding apparatus suctions an uppermost one of the sheets to a conveyance belt via take-away rollers (TAR) to be carried through the marking system for contact with the latent image on the photoreceptor. The sheet feeding apparatus is precisely controlled by appropriate sensors and controllers to ensure that the acquisition time (to rollers and conveyance belt) is exactly uniform and according to the desired timing.
Sheet feeding assemblies used in marking systems are disclosed in U.S. Pat. No. 7,461,839 (Ikeda), and U.S. Pat. No. 7,258,336, the disclosures of these two patents are incorporated by reference into the present disclosure. In U.S. Pat. No. 7,461,839 a sheet-feeding assembly similar to the present invention is disclosed using a suction assembly where the suction openings are closed after contact with the uppermost sheet of the sheet stack; the conveyance belts are driven after the suction-detecting hole is closed according to the negative pressure in the suction duct. A primary distinction from the present invention is that in Ikeda's system the closing of the suction openings by the upper most sheet also causes the cap on the suction-detecting hole to close, while in the present invention the pressure difference between the interior and exterior of the feedhead due to the suction openings being closed creates a force that lifts the cap away and opens the suction-detecting hole. The advantage in the present invention is that by using the pressure difference between the feedhead interior and ambient to open the suction-detecting hole instead of relying on a pressure difference due to a buildup of air flow between the cap and hole to close the suction-detecting hole, it takes much less time than closing the suction-detecting hole which could present a problem in a high speed printing apparatus. Thus, it takes substantially less time to open the suction-detecting hole which is a huge advantage in high speed systems. Also, a further advantage is that the design of the current invention is more straight forward as there is no need to carefully control the distance between the open cap and the suction-detecting hole such, which would be necessary with the prior invention. The feeder of the present invention can equally be used in monochrome or color high speed systems.
In addition, currently, vacuum corrugated feeders operate via open loop control in which actuations or closing of ports of the various mechanisms occur according to a preset timing chart. More specifically, it is expected that the acquisition of a single sheet by the feedhead will occur within a preset period of time after which the feedhead transports the sheet to the take away rolls. If the sheet was not acquired in time, a misfeed will be declared. While it would be advantageous to detect the acquisition of the sheet by the feedhead, the pressure sensor needed to perform this function is relatively expensive.

Vacuum level switch for a vacuum corrugated feeder


A P2X4 receptor antagonist such as paroxetine, a diazepinedione derivative having the following formula (IX) is used as an agent for preventing or treating zoster-associated pain in acute phase:

Herpes zoster is a viral disease caused by a varicella zoster virus (VZV). Initial infection of VZV is usually in childhood to cause varicella. The infected host may acquire humoral and cellular immunities against VZV to cease proliferation of virus. At the same time, virus may partly be incorporated into the peripheral end of sensory nerve fibers distributed in the skin, ascend the sensory nerve fiber along a retrograde axonal flow, and cause latent infection in ganglion. When the specific cellular immunity against VZV is lowed in the host, virus is reactivated to develop the syndrome of the herpes zoster. The reactivated virus descends the sensory nerve fiber along an antegrade axonal flow to reach the skin and cause zonary exanthema. The exanthema is naturally healed generally within about three weeks.
The zoster-associated pain is generally classified into an acute phase pain and a chronic phase pain. The chronic phase pain is a general problem, which continues over a long term after healing the exanthema. The chronic phase pain is called postherpetic neuralgia, which is considered as neuropathic pain caused by neural degeneration in central and peripheral nervous systems (Non-patent documents 1, 2, and 3). Tricyclic antidepressant, opioid, antiepileptic drugs or the like are used for the present to treat postherpetic neuralgia, and their treatment effects are reported.
On the other hand, the acute phase pain is prodrome or pain in an acute phase, which causes neuralgia-like pain several days before development of exanthema. It includes neuritis pain caused by proliferated virus and inflammatory pain within the area of exanthema. The area of exanthema can be the center of algesthesia, and pain runs along the nerve. The strength of the pain widely ranges from lightly stimulated symptom to heavy pain losing sleep at night. A HSV-1 infected rat has been used as a herpes zoster model. It has been confirmed that the rat can be spontaneously excited without inflammatory syndrome in the spinal posterior root ganglion. It is suggested that acute phase pain may be expressed with spontaneous hypersthenia of the primary neuron cell body (Non-patent document 4).
The acute phase of herpes zoster is treated for the present by using a combination of antiviral agent such as Valaciclovir, Aciclovir, Famciclovir or the like with an analgesic such as NSAIDs. The NSAIDs has an effect on inflammatory pain, but no effect on neuritis-like pain. Further, whole body administration of opioid is sometimes used. It has been known that the above-mentioned pharmacotherapy can have an accelerating effect of healing exanthema, and show a partial effect on acute phase pain, but it cannot suppress the pain completely. Therefore, nerve block treatments, such as epidural block, stellate block, peripheral nerve block has been used in the case that the exanthema and pain are serious (Non-patent document 5). For the reasons mentioned above, it has been desired to develop a method of treating acute phase of herpes zoster pain in view of QOL of the herpes zoster patients.
The present inventors have found that paroxetine, a diazepinedione derivative or the like having a P2X4 receptor antagonism can be used as an agent for preventing or treating neuropathic pain, and filed patent applications (Patent documents 1 and 2).
The patent documents, however, do not clearly describe that the above-mentioned compounds are available as an agent for preventing or treating zoster-associated pain in acute phase.

Preventive or therapeutic agent for pain associated with herpes zoster in acute phase

Abstract: wherein R1 is hydrogen, a C1-8 alkyl group, or the like;                each of R2 and R3 is hydrogen, a C1-8 alkyl group, or the like;        each of R4 and R5 is hydrogen or the like; and        W is a five-membered or six-membered heterocyclic ring optionally having one or more substituents and comprising one to four nitrogen atoms as the members of the ring.


A sense.multidot.input/output gate includes MOS transistors which are provided for each bit line pair and have their gates and drains cross-coupled together, separating transistors arranged between the gates and the drains of the MOS transistors, and column selecting gates connecting the drains of the MOS transistors to internal data transmitting lines. The semiconductor memory device further includes a load circuit which precharges the internal data transmitting lines to a predetermined potential in a test mode, and a line test circuit which determines existence and nonexistence of a defective memory cell based on the potentials of the internal data transmitting lines. In the data reading operation, the column selecting gates become conductive while the separating transistors are in OFF state, and the potential of the internal data transmitting line changes by virtue of the discharge through one of the cross-coupled MOS transistors. In this construction, the sense amplifier is used also as the read gate. Therefore, high-speed reading of data is allowed, and tests for many memory cells in up to one row can be simultaneously performed. Accordingly, a test time is reduced in a highly integrated semiconductor memory device.

1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a construction for increasing an operation speed and a degree of integration and facilitating test thereof.
2. Description of the Prior Art
FIG. 28 is a block diagram schematically showing a whole construction of a conventional semiconductor memory device. The construction of the semiconductor memory device shown in FIG. 8 is disclosed, for example, in a paper entitled "1.5V Circuit Technique for 64Mb DRAM", by Nakagome et al, 1990 Symposium on VLSI Circuits, pp. 17 and 18.
Referring to FIG. 28, the conventional semiconductor memory device includes a memory cell array 196 including memory cells arranged in a matrix of rows and columns, a row decoder 199 for selecting a corresponding row in the memory cell array 196 in accordance with an internal row address signal, and a column decoder 192 which generates a column selecting signal for selecting a corresponding column in memory cell array 196 in response to an internal column address signal. Memory cell array 196 includes dynamic memory cells arranged in a matrix of, e.g., 256 rows and 256 columns.
Conventional semiconductor memory device further includes an input/output gate 193 which is responsive to a column selecting signal supplied from the column decoder 192 to connect a corresponding column in memory cell array 196 to internal data transmitting lines IO and /IO, a sense amplifier circuit 194 which detects and amplifies data of memory cells in one row selected by row decoder 199, a precharging circuit 195 for precharging respective columns in memory cell array 196 to a predetermined potential (e.g., a half of the sum of a supply potential Vcc and a ground potential Vss) in a standby state of the semiconductor memory device, an IO (input/output) line precharging circuit 197 for precharging internal data transmitting line pair IO and /IO to a predetermined potential (e.g., "H" level) in a standby state, and an input/output circuit 198 connected to internal data transmitting lines IO and /IO.
Input/output circuit 198 produces internal write data in accordance with an external write data Din and transmits it to internal data transmitting lines IO and /IO in a data writing operation. In a data reading operation, input/output circuit 198 produces an external read data Dout in accordance with internal read data (transmitted from a selected memory cell) on internal data transmitting lines IO and /IO.
In the construction of the semiconductor memory device shown in FIG. 28, a memory cell, which is located at an intersection of the row and column designated by row decoder 199 and column decoder 192, is selected, and the data is written in or read from the selected memory cell.
FIG. 29 shows a construction of a main portion of the semiconductor memory device shown in FIG. 28. In FIG. 29, there is representatively shown a circuit portion related to one column in memory cell array 196. Referring to FIG. 29, memory cell array 196 includes a pair of bit lines BL and /BL providing a column line, and word lines WL1 to WL256 providing row lines each of which is connected to the memory cells in one row. Each memory cell is located at the intersection of each word line and each bit line pair. Specifically, memory cell MC1,1 is located at the intersection of word line WL1 and bit line BL, memory cell MC1,2 is located at the intersection of word line WL2 and complementary bit line /BL, and memory cell MC1,256 is located at the intersection of the word line WL256 and complementary bit line /BL.
Memory cells MC the (reference character "MC" will be used for generically indicating memory cells hereinafter) include dynamic memory cells each of a one-transistor/one-capacitor type. In the dynamic memory cells of the one-transistor/one-capacitor type, capacitors (210, 211 and 212) store information in the form of electrical charges. The information stored in a capacitor is transmitted to a corresponding bit line (BL or /BL) via a transmission gate (207, 208 or 209) in response to a signal WL, which generically indicates a word line selecting signal on the corresponding word line.
Precharging circuit 195 includes precharging transistors 204 and 205 which are responsive to a precharge instructing signal .phi.E to precharge respective bit lines /BL and BL to a predetermined precharge potential VH, and an equalizing transistor 206 which is responsive to precharge instructing signal .phi.E to equalize the potentials of bit lines BL and /BL. Precharging transistors 204 and 205 each are formed of n-channel MOS transistors. Transistor 204 is responsive to precharge instructing signal .phi.E to transmit a precharge potential VH (normally, Vcc/2; Vcc is an operating supply voltage) to complementary bit line /BL. Transistor 205 is responsive to precharge instructing signal .phi.E to transmit precharge potential VH to bit line BL. Equalizing transistor 206 is responsive to precharge instructing signal .phi.E to short-circuit the bit line BL and the complementary bit line /BL.
Sense amplifier circuit 194 includes an N-type sense amplifier NSA which is responsive to an N-type sense amplifier drive signal .phi.N to discharge the potential of the bit line at a lower potential in bit line pair BL and /BL, and a P-type sense amplifier PSA which is responsive to a P-type sense amplifier drive signal .phi.P to charge the potential of the bit line at a higher potential in bit line pair BL and /BL. N-type sense amplifier NSA includes a pair of cross-coupled n-channel MOS transistors 202 and 203. This n-channel MOS transistor 202 has a gate connected to bit line BL, one conduction terminal (drain) connected to complementary bit line /BL and the other conduction terminal (source) for receiving N-type sense amplifier drive signal .phi.N. The n-channel MOS transistor 203 has a gate connected to complementary bit line /BL, one conduction terminal (drain) connected to bit line BL, and the other conduction terminal (source) coupled to receive the N-type sense amplifier drive signal .phi.N.
P-type sense amplifier PSA includes a pair of cross-coupled p-channel MOS transistors 213 and 214. This p-channel MOS transistor 213 has a gate connected to bit line BL, one conduction terminal (drain) connected to complementary bit line /BL, and the other conduction terminal coupled to receive the P-type sense amplifier drive signal .phi.P. The p-channel MOS transistor 214 has a gate connected to complementary bit line /BL, one conduction terminal (drain) connected to bit line BL, and the other conduction terminal coupled to receive the P-type sense amplifier drive signal .phi.P.
Input/output gate 193 includes column selecting gates 201 and 200 which are responsive to a column selecting signal Y1 supplied from the column decoder (see FIG. 27) to connect bit lines BL and /BL to internal data transmitting lines IO and /IO, respectively. Column selecting gates 200 and 201 are formed of n-channel MOS transistors, respectively. Now, operations will be described with reference to an operation timing diagram of FIG. 30.
First, description will be made of a data reading operation in such a case that a selected memory cell MC1, 1 holds the data of "H".
At time t0, a memory cycle starts when precharge instructing signal .phi.E falls to "L". In response to the fall of precharge instructing signal .phi.E, equalizing circuit 195 is inactivated, and bit lines BL and /BL enters a floating state at precharge potential VH.
At time t1, row decoder 199 decodes a received internal row address, and the potential of the corresponding word line WL1 rises to "H". Responsively, transmission gate 208 of memory cell MC1, 1 becomes conductive, so that data of "H" held in the memory capacitor 211 is transmitted to bit line BL. This increases the potential of bit line BL. Since the memory cell does not exist at the intersection of complementary bit line /BL and word line WL1, the potential of complementary bit line /BL remains at precharge potential VH.
At time t2, N-type sense amplifier drive signal .phi.N lowers from an intermediate potential Vcc/2 to "L", and P-type sense amplifier drive signal .phi.P rises from intermediate potential Vcc/2 to "H". Thereby, N-type sense amplifier NSA and P-type sense amplifier PSA are activated, and a potential difference between bit line BL and complementary bit line /BL is differentially amplified. Specifically, the potential of bit line BL changes to "H", and the potential of complementary bit line /BL changes to "L".
At time t3, column decoder 192 generates a column selecting signal Y1 in accordance with a result of decoding of an internal column address, and thus column selecting gates 200 and 201 become conductive. Potentials on bit line BL and complementary bit line /BL are transmitted to internal data transmitting lines IO and /IO. Thereby, the potentials of internal data transmitting lines IO and /IO which have been precharged to a predetermined potentials changed corresponding to those of bit lines BL and /BL. Specifically, the potential of internal data transmitting line IO rises to "H", and the potential of complementary internal data transmitting line /IO slightly lowers.
In the above operation, the potential of complementary internal data transmitting line /IO does not lower to the level of "L", because IO line precharging circuit 197 has pull-up means and the gate transistors 200 and 201 has a relatively large resistance, which suppresses the lowering of the potential. The reason of slight change of the potentials of bit lines BL and /BL at time t3 is that bit lines BL and /BL are connected to internal data transmitting lines IO and /IO precharged to the predetermined precharge potential, and receive the influence of the potential change thereof.
The data read to internal data transmitting lines IO and /IO is detected by an output circuit contained in input/output circuit 198 shown in FIG. 28. This output circuit detects that internal data transmitting line IO has the potential higher than that of internal data transmitting line /IO, and produces external output data Dout of "H".
Then, description will be made of an operation for writing the data of "L" in memory cell MC1,1.
The operation before time t4 is similar to that for reading a data. At time t4, input/output circuit 198 responds to write data Din of "L" to set the potential of internal data transmitting line IO at "L" and set the potential of complementary internal data transmitting line /IO at "H". The data on internal data transmitting lines IO and /IO are transmitted through column selecting gates 201 and 200 to bit lines BL and /BL. Input/output circuit 138 includes an input circuit of which driving ability is larger than latching abilities of sense amplifiers PSA and NSA, and thus bit lines BL and /BL have potentials corresponding to the write data. The data of "L" on bit line BL is transmitted through transmission gate 208 in memory cell MC1,1 to memory cell capacitor 211. Thereby, writing of the data of "L" in memory cell MC1,1 is completed.
At time t5, precharge instructing signal .phi.E is changed to "H". Precharging circuit 195 is activated, and the potentials of bit lines BL and /BL are set at predetermined precharge potential VH for the next memory cycle. Before precharge instructing signal .phi.E rises to "H" at time t5, word line selecting signal WL1 on word line WL1 and column selecting signal Y1 have already lowered to "L" and also sense amplifier drive signals .phi.N and .phi.P have returned to the intermediate potential.
In the semiconductor memory device shown in FIGS. 28 and 29, timing for generating a column selecting signal Y must be as early as possible in order to reduce a time required for reading the data. It is inhibited to generate column selecting signal Y1 before time t2 at which sense amplifiers NSA and PSA are activated, because a slight potential difference generated between bit lines BL and /BL is further reduced due to the connection by the signal Y1 to internal data transmitting lines IO and /IO, and thus sense amplifiers PSA and NSA cannot perform an accurate amplifying operation.
A similar problem is caused in a case that the time t3 at which column selecting signal Y1 is generated is set closer to the time t2 immediately after the generation of sense amplifier drive signals .phi.N and .phi.P. Specifically, if bit lines BL and /BL are connected to internal data transmitting lines IO and /IO before sense amplifiers NSA and PSA sufficiently amplify the potentials of bit lines BL and /BL, the potential difference to be amplified by sense amplifiers NSA and PSA is reduced. Therefore, the sense amplifiers malfunction, and thus cannot accurately amplify the data, resulting in incorrect reading of the data.
Therefore, in the semiconductor memory device shown in FIGS. 28 and 29, it is necessary to generate column selecting signal Y1 in such a state that sense amplifiers NSA and PSA have been activated and the potentials on bit lines BL and /BL have been settled. Therefore, it is impossible to sufficiently reduce an access time in the data reading operation.
In addition, the configuration shown in FIG. 32 does not allow a line test mode operation in which memory cells on a row are simultaneously tested because of the following reason.
In order to carry out the line test mode operation, data of all the memory cells on a row have to be read out simultaneously. If all the bit lines are connected to the internal data transmission lines IO and /IO in order to accomplish the simultaneous reading of data, all the bit lines are interconnected with each other, and a defective memory cell can not be detected because an erroneous data are turned into a correct data by such interconnection. In order to carry out the line test mode operation, a register for storing a test data and a comparator for comparing the test data and a data read out from an associated selected memory cell are required for each respective pair of bit lines. In operation, the output of all the comparators are transferred to a dedicated test data line to be wired-ANDed. Such construction increases the memory cell array area. If a memory device is not provided with the line test mode of operation, memory cells are tested bit by bit, resulting in a long testing time.
FIG. 31 shows another construction of a conventional semiconductor memory device. The semiconductor memory device shown in FIG. 31 is also disclosed, for example, in the previously mentioned paper of 1990 Symposium on VLSI Circuits by Nakagome et al.
Referring to FIG. 31, the semiconductor memory device includes a memory cell array 318 including memory cells arranged in a matrix, a row decoder 319 for selecting a row in memory cell array 318, a column decoder 313 for selecting a column in memory cell array 318, a precharging circuit 317 for precharging each column line in memory cell array 318 to a predetermined potential, and a sense amplifier circuit 316 for detecting and amplifying data of the memory cells in memory cell array 318 selected by row decoder 319, as in the memory device shown in FIG. 28.
The semiconductor memory device shown in FIG. 31 further includes a read gate 315 which transmits a data of a memory cell in the memory cell array 318 selected by the row decoder 319 and column decoder 313 in a data reading operation onto read data transmitting lines O and /O, and a write gate 314 for transmitting a write data to a selected memory cell in memory cell array 318 in the data writing operation. Write gate 314 and read gate 315 are responsive to a column selecting signal from column decoder 313 to connect a corresponding column in memory cell array 318 to internal data transmitting lines I and /I, and O and /O.
For the internal read data transmitting lines O and /O, there are provided an output line precharging circuit 322 for precharging internal read data transmitting lines O and /O to a predetermined potential, and an output circuit 321 for producing an external read data Dout from an internal read data on the internal read data transmitting lines O and /O. For the internal write data transmitting lines I and /I, there is provided an input circuit 320 for transmitting an internal write data to the internal write data transmitting lines I and /I in response to an external write data Din.
The semiconductor memory device shown in FIG. 31 has separated IO structure, in which internal data transmitting lines are separated into the read data transmitting lines O and /O for transmitting read data and the write data transmitting lines I and /I for transmitting write data, and a data reading is carried out before the activation of sense amplifier circuit 316 for reducing an access time in the data reading operation.
FIG. 32 shows a circuit portion related to one column in the semiconductor memory device shown in FIG. 31. Referring to FIG. 32, sense amplifier circuit 316, precharging circuit 317 and memory cell array 318 have the same constructions as sense amplifier circuit 194, precharging circuit 195 and memory cell array 196 shown in FIG. 29, respectively. Only differences therebetween are reference numerals allotted to the respective components and elements, and the constructions of these circuits is not be described in detail.
Read gate 315 includes discharging transistors 224 and 225 which are responsive to the potentials on bit lines /BL1 and BL1 to discharge the potentials of read data transmitting lines O and /O, respectively, and read column selecting gates 222 and 223 which are responsive to a column selecting signal Y1 from column decoder 313 to connect the discharging transistors 224 and 225 to the read data transmitting lines /O and O, respectively. Discharge transistors 224 and 225 include n-channel MOS transistors having gates connected to bit lines /BL1 and BL1, respectively. Each of discharging transistors 224 and 225 has two conduction terminals, one (source) of which is connected to the ground potential.
Read column selecting gates 222 and 223 have gates which receive column selecting signal Y1 for connecting the other conduction terminals (drains) of discharging transistors 224 and 225 to read data transmitting lines /O and O, respectively.
Write gate 314 includes n-channel MOS transistors 220 and 221 which turn on and off in response to a write instructing signal W, and write column selecting gates 218 and 219 which are responsive to column selecting signal Y1 from column decoder 313 to connect the transistors 220 and 221 to the write data transmitting lines /I and I, respectively. Write column selecting gates 218 and 219 are responsive to column selecting signal Y1 to connect the one-conduction terminals of respective transistors 220 and 221 to the read data transmitting line /I and I.
Thus, write gate 314 connects a selected column to write data transmitting lines /I and I only in the data writing operation.
IO line precharging circuit 322 includes pull-up means and precharges the read data transmitting lines O and /O to a predetermined potential ("H" level). Precharging circuit 322 also includes a pull-up stage for pulling up both read data transmitting lines O and /O to "H". Precharging circuit 322 and discharging transistors 244 and 255 form a current-detection type sense circuit for detecting a current. Operations thereof will be described below with reference to an operating waveform diagram of FIG. 33.
In FIG. 33, the following is assumed. Memory cell MC1,1 is selected for writing and reading of data. Memory cell MC1,1 has held data of "H". In the data writing operation, data of "L" is written in memory cell MC1,1.
At time t0, precharge instructing signal .phi.E lowers to "L", and a memory cycle starts. Bit lines BL1 and /BL1 are held in a floating state with precharge potential VH of the intermediate potential. Read data transmitting lines O and /O have been precharged to "H" level.
At time t1, the potential of word line WL1 rises to "H" based on the result of decoding of row decoder 319. Transmission gate 232 of memory cell MC1,1 becomes conductive, and the data of "H" held in memory cell capacitor 235 is transmitted to bit line BL1, so that the potential of bit line BL1 slightly increases. Complementary bit line /BL1 maintains the precharge potential VH.
As the selecting signal WL1 rises, column selecting signal Y1 rises to "H" substantially simultaneously or with a slight delay. A row address signal and a column address signal have been simultaneously applied to the semiconductor memory device in a non-multiplex manner. Row address signal and column address signal, however, may be applied in a time-division multiplexing manner. It is required only to generate column selecting signal Y1 before the activation of sense amplifier circuit 316.
In response to column selecting signal Y1, read column selecting gates 222 and 223 contained in read gate 315 become conductive.
Since the potential of bit line BL1 is higher than that of complementary bit line /BL1, the conductivity of transistor 225 is higher than that of transistor 224, so that the potential of read data transmitting line O is reduced to be lower than the potential of complementary read data transmitting line /O. In this operation, transistor 224 also reduces slightly the potential of complementary read data transmitting line /O.
Output circuit 321 detects the potential difference of read data transmitting lines O and /O to produce a corresponding external output data Dout. Specifically, the output circuit 321 supplies data Dout of "H" when it detects that the potential of internal data transmitting line O is lower than the potential of internal data transmitting line /O.
Then, at time t2, N-type sense amplifier drive signal .phi.N and P-type sense amplifier drive signal .phi.P are changed from the intermediate potential to "L" and "H", respectively, so that N-type sense amplifier NSA and P-type sense amplifier PSA are activated. Thereby, the potential difference between bit line BL and complementary bit line /BL is amplified. In the data reading operation, sense amplifiers NSA and PSA perform the amplifying operation on bit lines BL and /BL, whereby a restoring operation is conducted for restoring the read out data in the selected memory cell MC1,1. This operation completes data reading cycle.
Then, data writing operation will be described. Operations till the activation of sense amplifiers PSA and NSA are identical with those in the data reading process. Input circuit 320 sets the write signal W at "H" at time t3. Before time t3, input circuit 320 also sets the potentials of write data transmitting lines I and /I at levels corresponding to the write data. In this operation, write data transmitting line I is set at "L", and complementary internal write data transmitting line /I is set at "H". In FIG. 33, it is shown that input circuit 320 has set the potential of internal write data transmitting lines I and /I to the levels corresponding to the write data before time t2 at which sense amplifiers PSA and NSA are activated. The timing for generating internal write data by input circuit 320 may be between time t2 and time t3.
At time t3, upon generation of write signal W, transistors 220 and 221 become conductive. Column selecting signal Y1 has already risen to "H". In response to the write data, the potentials of bit lines BL and /BL change to "L" and "H", respectively. The change of signal potentials of bit lines BL and /BL is also transmitted through the read gates formed of transistors 222, 223, 224 and 225 to the read data transmitting lines O and /O, so that the potentials of read data transmitting lines O and /O also change.
The data of "L" on bit line BL is written in memory cell capacitor 235 through transmission gate transistor 232 in memory cell MC1,1.
Then, word line selecting signal WL1 and column selecting signal Y1 are set at an inactive state of "L", and, at time t4, precharge instructing signal .phi.E is set at "H", whereby the data writing cycle is completed. The potentials of bit lines BL and /BL1 return to the intermediate potential VH, and a standby state is set for the next data writing or reading operation.
In the construction shown in FIGS. 31 and 32, the data reading is performed before the time at which sense amplifiers PSA and NSA are driven. In other words, when word line selecting signal WL1 rises to "H", column selecting signal Y1 is set at "H" prior to the activation of sense amplifiers PSA and NSA. Thereby, the data can be read to internal data transmitting lines O and /O before time t2 at the activation of the sense amplifier, so that the time required for reading a data out of a memory cell, i.e., the access time can be reduced.
As described above, in the construction of the semiconductor memory device shown in FIGS. 31 and 32, read data transmitting lines and write data transmitting lines are independently arranged, which enables the data reading at a high speed. In the construction of the semiconductor memory device shown in FIG. 29, the input/output gate are formed of only two transistors, i.e., transistors 200 and 201. In the semiconductor memory device of the separated IO type shown in FIGS. 31 and 32, however, the write gate requires four transistors, i.e., transistors 218, 219, 220 and 221, and the read gate requires four transistors, i.e., transistors 222, 223, 224 and 225. This semiconductor memory device of the separated IO type, therefore, requires totally eight transistors for the read gate and write gate, and thus requires additionally six transistors as compared with the semiconductor memory device in FIG. 29, which disadvantageously increases the chip area.
Further, after the manufacturing, the semiconductor memory devices are subjected to a test for determining whether or not each memory cell can perform a correct operation for storing data. A merged match line test and data line configuration is employed in the construction shown in FIGS. 31 and 32 in order to carry out the line test mode operation. The merged match line test and data line configuration is disclosed in, e.g., "45ns 64Mb DRAM with Merged Match Line Test And Data Line System" by Mori et al., 1991 IEEE, ISSCC, Digest of Technical Papers, pp. 110 and 111.
In this merged match line test and data line configuration, all the column selecting signals are raised to "H" in the test mode. Thereby, all the data of the memory cells connected to a selected one row is simultaneously read onto the read data transmitting lines O and /O. The data on read data transmitting lines 0 and /O is supplied to a test circuit in the test mode. The test circuit detects the potentials of read data transmitting lines O and /O to determine whether or not memory cells in this one row contains a defective memory cell(s). If it does not contain any defective memory cell, the same data has been written in all the memory cells, so that the potentials of read data transmitting lines O and /O change to "H" and "L", respectively. If it contains at least one defective memory cell, both the potentials of read data transmitting lines O and /O change to "L", and the existence of the defective memory cell can be detected.
This simultaneous testing of the memory cells in one row can reduce the test time. In this case, although the test time can be reduced, components in the read gates and the write gates increase in number, resulting in increase of the chip area.

Semiconductor memory device and method of testing the same


A shielded medical device implanted in a biological organism. The device has a magnetic shield, and the magnetic shield contains a layer of nanomagnetic material; such layer has a morphological density of at least 98 percent. The nanomagnetic material in such layer has a saturation magnetization of from about 1 to about 36,000 Gauss, a coercive force of from about 0.01 to about 5,000 Oersteds, a a relative magnetic permeability of from about 1 to about 500,000, and an average particle size of less than about 100 nanometers.

Applicants' U.S. Pat. No. 6,502,972 describes and claims a magnetically shielded conductor assembly comprised of a first conductor disposed within an insulating matrix, and a layer comprised of nanomagnetic material disposed around said first conductor, provided that such nanomagnetic material is not contiguous with said first conductor. In this assembly, the first conductor has a resistivity at 20 degrees Centigrade of from about 1 to about 100 micro ohm-centimeters, the insulating matrix is comprised of nano-sized particles wherein at least about 90 weight percent of said particles have a maximum dimension of from about 10 to about 100 nanometers, the insulating matrix has a resistivity of from about 1,000,000,000 to about 10,000,000,000,000 ohm-centimeter, the nanomagnetic material has an average particle size of less than about 100 nanometers, the layer of nanomagnetic material has a saturation magnetization of from about 200 to about 26,000 Gauss and a thickness of less than about 2 microns, and the magnetically shielded conductor assembly is flexible, having a bend radius of less than 2 centimeters. The entire disclosure of this United States patent is hereby incorporated by reference into this specification.
The nanomagnetic film disclosed in U.S. Pat. No. 6,506,972 may be used to shield implanted medical devices from external electromagnetic fields; and, when so used, it provides a certain degree of shielding.
It is an object of this invention to provide an improved nanomagnetic coating.


The present invention provides methods, processes and reaction mixtures, which produce sulfated heparosan polysaccharides. This invention also provides methods and reaction mixtures for the synthesis of N-deacetylate N-sulfate derivatives of non-sulfated N-acetyl heparosan (HS) polysaccharides.

Sulfated saccharides play important roles in many biological processes. For example, the sulfated Lea tetra- and pentasaccharides are potent E-selectin inhibitors and sialyl Lewis x with a sulfate group at the 6-position of galactose is a ligand for L-selectin. These sulfated sugars play important roles, among others, in cell adhesion in response to inflammatory reactions. The sulfation of hydroxysteroids provides hydrophilic forms for excretion. Many glycosaminoglycans [GAGs] are sulfated and are involved in numerous cellular functions. GAGs are long linear polysaccharides consisting of disaccharide repeats that contain an amino sugar and are found in most animals. Chondroitin [β(1,4)GlcUA-β(1,3)GalNAc]n and heparin/heparan [α1,4)GlcUA-[β(1,4)GlcNAc]n, (typically with an n=20 to 100) are sulfated at various positions. These GAGs play both structural and recognition roles on the cell surface and in the extracellular matrix.
In the course of oligosaccharide sulfation, 3-Phosphoadenylsulfate, also known as 3′-phosphoadenosine-5′-phosphosulfate (PAPS), is a substrate and cofactor for the enzymatic sulfation of oligosaccharides and steroids via sulfotransferases. Of the twenty-eight sulfotransferase enzymes [EC 184.108.40.206-28] listed in Enzyme Nomenclature 1992, E. C. Webb, ed., Academic Press, San Diego, Calif. 1992, pages 299-303, all but one enzyme utilize PAPS as the sulfate donor. Sulfotransferase activity varies with respect to the donor and/or acceptor compounds with which they work. Known sulfotransferases include those acting on carbohydrate: heparin/heparan sulfate N-sulfotransferase COST); chondroitin 6/keratan 6 sulfate sulfotransferase (C6ST/KSST); galactosylceramide 3′-sulfotransferase; heparan sulfate 2-sulfotransferase (Iduronic acid); HNK-1 sulfotransferase (3-glucuronic acid); heparan sulfate D-glucosamino 3-O-sulfotransferase (3-OST); etc., as well as those acting on phenols, steroids and xenobiotics: aryl sulfotransferase I & II, hydroxy-steroid sulfotransferases I, II & III, dehydroepiandrosterone (DHEA); etc.
The efficiency of oligosaccharide sulfation is limited by PAPS availability as a sulfate donor. PAPS synthesis has been reported, however, the synthesis procedures involve numerous steps with poor yields, which in turn limit the sulfated oligosaccharide product yield.
Despite numerous advances in the chemical synthesis of sulfated oligosaccharides and polysaccharides, to date, existing approaches are cumbersome, time-consuming and inefficient.

Methods for synthesis of sulfated saccharides


An apparatus for providing back tension onto a print media web comprises a plate having a post extended perpendicularly therefrom. The post is adapted to support a roll of print media thereon such that a web of the print media roll is paid out by rotation of the roll about the post. A constant-force spring is attached to a portion of the media plate at and has a handle coupled to an opposite end of the spring. A pressing element is coupled to the handle such that the spring is biased to urge the pressing element against the media supply roll to maintain the roll firmly in contact with the post during rotation of the roll. The force provided by the pressing element onto the media supply roll imparts sufficient back tension on the print media web to maintain a constant pay out rate. The present back tension apparatus provides a relatively simple mechanism that is readily adaptable for many conventional printers, such as a thermal transfer printer.

1. Field of the Invention
The present invention relates to thermal printing, and more particularly, to an apparatus for providing back tension on a print media web as it is transported through a thermal printer.
2. Description of Related Art
In the field of bar code symbology, vertical bars of varying thicknesses and spacing are used to convey information, such as an identification of the object to which the bar code is affixed. Bar codes are often printed onto a print media comprising individual paper substrate labels having an adhesive backing layer that enables the labels to be affixed to objects to be identified. To read the bar code, the bar and space elements of the bar code may be scanned by a moving light source, such as an articulating laser beam. Alternatively, the bar and space elements may be imaged in one or two-dimensions by a photosensitive imaging element, such as a charge coupled device. Since the bar and space elements have differing light reflective characteristics, the information contained in the bar code can be read by interpreting the reflected light or image pattern from the bar code. In order to accurately read the bar code, it is thus essential that the bar code be printed in a high quality manner, without any streaking, blurring or misregistration of the bar code. At the same time, it is essential that the adhesive backing layer of the labels not be damaged by heat generated during the printing process.
In view of these demanding printing requirements, bar codes are often printed using direct thermal or thermal transfer printing techniques. In direct thermal printing, the print media is impregnated with a thermally sensitive chemical that is reactive upon exposure to heat for a period of time. Thermal transfer printing requires an ink ribbon that is selectively heated to transfer ink to the print media. These printing techniques are referred to collectively herein as thermal printing.
To print the bar code, the print media is drawn between a platen and a thermal print head of the printer. The thermal print head has linearly disposed printing elements that extend across a width dimension of the print media. The printing elements are individually activated in accordance with instructions from a printer controller. As each printing element is activated, the thermally active chemical of the ribbon activates at the location of the particular printing element to transfer ink to the printed area of the print media. The print media is continuously drawn through the region between the platen and the thermal print head, and in so doing, the bar code is printed onto the print media as it passes through the region. Other images, such as text, characters or graphics, can be printed in the same manner. The thermal printer includes a mechanism for transporting the print media from a supply hub to the print region. Such printers typically include a media post or hub onto which is mounted a supply roll of the print media material. The media post is substantially smaller in cross-section than the core of the media supply roll so that the post can accommodate media supply rolls of various sizes. As the media supply roll is rotated under take-up tension applied by the transporting mechanism, a web of the print media is paid out and transported past the thermal print head.
The movement of the print media must be precisely coordinated with the operation of the thermal print head in order to ensure accurate registration of the printed information to the print media. Top-of-form registration refers to the alignment of the printed information to the beginning or leading edge of a print media label. A top-of-form registration error occurs when the printing begins either too soon or too late. Sensing circuits are often utilized to detect the gap between adjacent labels in order to accurately coordinate the printing to the leading edge. Lateral registration refers to the alignment of the printed information to the left and right side edges of the label, and a lateral registration error occurs when the print media supply roll is not properly stabilized with respect to the media post. Print media labels often include pre-printed material with designated spaces for printing bar codes and other information. Thus, registration errors can result in overlapping between the pre-printed material and the newly printed information, causing the newly printed information to become obscured. In some cases, a lateral registration error could cause the bar code symbol or text to run off the edge of the label, rendering the bar code unreadable.
Both types of print registration error conditions can be adversely effected by insufficient back tension applied to the print media web. Initially, the weight of the media supply roll is sufficient to maintain a positive connection between the media supply roll and the media post to prevent the web from paying out at an uneven rate or wandering laterally on the media post. As the media supply roll is paid out, however, its size and weight decreases until it no longer provides sufficient back tension to the web. Thereafter, the supply roll starts lifting off of the media post and shifting position laterally along the media post. In turn, this causes the pay out rate of the print media to fluctuate which ultimately results in undesirable degradation of both lateral and top-of-form registration.
Accordingly, it would be desirable to provide a mechanism for a thermal transfer printer that would provide sufficient back tension on the rotating media supply roll in order to maintain a consistent transport rate of the media web as it is paid out. At the same time, the mechanism should not overly complicate the printer or substantially increase its production cost.

Apparatus for providing back tension on a print media web


A microprocessor 10 has a processor core 20 and a debug module 30. The processor core 20 executes a user program and a monitor program for debugging a user target system 70. The debug module 30 serves as an interface with a debug tool 60, to let the processor core 20 execute the monitor program stored in the debug tool 60. The debug module 30 makes an interrupt or exception request to switch the processor core 20 from the user program to the monitor program.

1. Field of the Invention
The present invention relates to a microprocessor and debug system having a function of tracing a program counter and a function of externally notifying that a preset address or data has been accessed.
2. Description of the Prior Art
FIG. 1 shows a debug system called an in-circuit emulator according to a prior art.
The system includes a user target system 500 and a debugger 505 for debugging the target system 500. The target system 500 has a microprocessor 501, a memory 503, and an I/O unit 502. The debugger 505 has a debugging microprocessor 506 and a monitor program memory 507.
To debug the target system 500, the microprocessor 501 is removed or disabled, and probes of the debugger 505 are connected to the place of the microprocessor 501 so that the microprocessor 506 may operate instead of the microprocessor 501. The microprocessor 506 executes a monitor program stored in the memory 507, to control a user program stored in the memory 503.
The microprocessor 506 executes the user program, accesses data in the memory 503, and accesses the I/O unit 502. The debugger 505 has a trace memory 508, so that the microprocessor 506 may provide trace information about an internal state such as the value of a program counter that is usually not provided by the microprocessor 501 through a processor bus 504.
The prior art of FIG. 1, however, must connect the debugger 505 to all pins of the microprocessor 501 of the target system 500. The microprocessor 501 has, for example, 70 pins for 30 address signals, four byte-enable signals, a read signal, a write signal, a read acknowledge signal, a write acknowledge signal, and 32 data signals. The debugger 505 must have probes for these pins, and therefore, is expensive and unstable. The microprocessor 506 must switch buses from one to another to access the memory 503 of the target system 500 and the memory 507 of the debugger 505, and therefore, is not applicable to a high-speed microprocessor.
If the target microprocessor has peripheral elements, it may have a different pin arrangement. In this case, the debugger must have probes proper for such a pin arrangement. When connected to the target system 500, the probes of the debugger 505 may influence and destabilize signals in the target system 500.
FIG. 2 shows a debug system called a ROM monitor according to another prior art.
A user target system 510 has a serial interface 512 connected to a host computer 517. A memory 513 stores a monitor program 514. A microprocessor 511 executes the monitor program 514 to access the memory 513, an I/O unit 515, and a register 516. A software break instruction is used to execute and control a user program.
This prior art employs the user memory 513 to store the monitor program 514. If the memory system of the target system 510 is imperfect, the monitor program 514 itself will be unstable. If the capacity of the memory 513 is small, there will be no space to store the monitor program 514. Since a monitor mode is started by a user interrupt, some program may not be debugged. The serial interface 512 mounted on the target system 510 is imperative for debugging but is useless after debugging. The debugging performance of this prior art is poor because it has no hardware break point and because it is incapable of tracing a program counter.
FIG. 3 shows a debug system according to still another prior art.
A user target system 520 has a microprocessor 521, which incorporates a serial interface 526 and a sequencer 525. The serial interface 526 communicates with a debug tool 529. The debug tool 529 sends signals to the interface 526, and the sequencer 525 interprets the signals. In response to the signals, the sequencer 525 temporarily stops the execution of a user program, accesses a register 528, uses a bus controller 527 to access an I/O unit 523 and a memory 524, and controls the user program. The serial interface 526 is usually incapable of directly communicating with a host computer 530. Accordingly, the debug tool 529 converts a command from the host computer 530 into a signal understandable by the microprocessor 521, and a signal from the microprocessor 521 into a data format understandable by the host computer 530.
The microprocessor 521 incorporates the sequencer 525, which must access the microprocessor 521 as well as the debug tool 529. In this way, this prior art employs a complicated connection logic to increase a chip area. If the target system 520 is provided with an additional register, the sequencer 525 must be modified accordingly through a complicated work. This prior art is incapable of tracing a program counter.
As explained above, the prior arts are incapable of tracing a program counter, or even if they can, they must connect many signals between a debug processor and a target system through a processor bus. According to the prior art of FIG. 1, the microprocessor 506 of the debugger 505 must access the memory 503 and I/O unit 502 of the target system 500, and it is difficult to control the timing of these access operations.
The prior art of FIG. 2 stores a monitor program in the user memory 513, to reduce a user memory space. Debugging by this prior is unsure and insufficient.
The prior art of FIG. 3 incorporates the sequencer 525 in the microprocessor 521 of the target system 520, to interpret and execute signals sent from the debug tool 529. Namely, this prior art involves a complicated connection between a target system and a debug tool. If it is required to modify the microprocessor 521, the sequencer 525 must also be modified through a complicated work.
The prior arts of FIGS. 2 and 3 have no trigger function. The prior art of FIG. 1 may have the trigger function in the debugging microprocessor 506 but with additional signals for providing trigger information.


A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T.sub.c, superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T.sub.c, superconductive layer. The dielectric layer and the first high-T.sub.c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T.sub.c, superconductive layer (second base electrode layer) 54 directly on the first high-T.sub.c superconductive layer, a normal barrier layer 56 on the second high-T.sub.c superconductive layer, and a third high-T.sub.c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ionmilling. A plasma etch step can be performed in-situ to remove the photoresist layer 62 following formation of the ramp edge. A normal-superconductive (NS) structure can be optimally formed directly on the ramp edge following the plasma etch step to form an SNS junction 70. The SNS and NS structures are preferably formed in-situ.

The invention is directed to the field of superconducting Josephson junctions and, more particularly, to a high-temperature superconductive--superconductive-normal-superconductive (SSNS) Josephson junction and a high-temperature superconductive-normal-superconductive (SNS) Josephson junction and a method of making the junctions.
High-temperature superconductive (HTS) materials have a normal-to-superconducting transition temperature, T.sub.c, of more than 25 K. At lower temperatures, these materials exhibit no resistance to electrical current flow. High-T.sub.c superconductive materials are used in HTS circuits. In comparison to low-temperature superconductive (LTS) circuits, HTS circuits operate at significantly higher temperatures, typically about 25-100 K as compared to about 4-10 K for LTS circuits. HTS circuits are highly advantageous as compared to LTS circuits due to their relatively reduced cooling and insulation requirements.
HTS circuits can be used in a wide range of defense, industrial and commercial applications. HTS circuits can be used in analog-to-digital (ADC) applications such as analog signal processors (ASP), digital signal processors (DSP), high-speed computers, asynchronous transfer mode (ATM), switching networks, telecommunications, commercial satellites; rf applications such as resonators, band-pass filters, phased-array antennae for cellular/satellite telecommunications; and sensors such as magnetic sensors for mine-detection, anti-submarine warfare, and bio-magnetic diagnostic and non-destructive magnetic sensors.
HTS circuits are a vital next generation technology capable of replacing existing semiconductor technologies and having a tremendous growth potential within the next decade.
Despite providing important advantages, known HTS circuits have performance limiting problems as well. One basic problem of HTS circuits is the non-uniformity of the active devices. The basic active device used in HTS circuits is the Josephson junction. A key junction technology is the SNS Josephson junction. SNS Josephson junctions include two superconductive layers and an intermediate barrier layer (N layer) comprised of a normal material. During operation, a supercurrent flows through the barrier layer via the Josephson tunneling effect.
In known ramped high-T.sub.c SNS Josephson junctions, the SNS junction is formed by depositing the normal barrier layer and a high-T.sub.c superconductive counterelectrode layer on a ramped high-T.sub.c, superconductive base electrode. One of the performance-limiting problems associated with known ramped SNS junctions is the occurrence of interfacial electric resistance at the base electrode/normal barrier layer interface at the ramp edge. This interfacial resistance is the result of the conventional fabrication process used to form the junction. Particularly, the base electrode is exposed to ambient conditions and to chemical treatments during the patterning process. As a result, the top several monolayers of the base electrode are degraded and deoxygenated, reducing the quality of these monolayers as compared to the bulk of the layer, and producing a resistive and/or nonuniform interface.
A resistive and/or non-uniform junction interface adversely affects process quality control by increasing the non-uniformity of the junction characteristics.
A technique that has been used in an attempt to overcome the problem of interfacial resistance in SNS junctions is low- energy ion-etch cleaning of the interface surface, either ex-situ before depositing the normal barrier layer and the counterelectrode layer, or, alternately, in-situ in the same vacuum system in which the barrier layer and counterelectrode layer are deposited. Ion-etch cleaning invariably also produces lattice damage in the exposed ramp edge of the base electrode, adversely affecting the interfacial electrical properties. Thus, this technique has not overcome the problem of interfacial resistance between the base electrode and the normal barrier layer in known SNS junctions.
A known technique of fabricating high-V.sub.c SNS Josephson junctions in-situ employs shadow masking. Particularly, a shadow mask is patterned on the substrate, and the base electrode is deposited by orienting a source at an angle relative to the shadow mask to form the ramp edge. The substrate is then rotated, and the barrier layer and the counterelectrode layer are deposited with the source oriented at a vertical angle relative to the substrate. The shadow mask is then removed.
This technique has proven less than satisfactory because the steps for forming the ramp edge are directional dependent and, so, junctions cannot be fabricated in an arbitrary direction of the substrate. This factor is a major limitation in integrated circuit process technology. In addition, the substrate cannot be rotated during the deposition process; consequently, the thickness of each of the deposited layers can vary significantly across the substrate. This non-uniformity is particularly severe in off-axis sputtering techniques which form a thickness gradient across the substrate unless the substrate is rotated, or unless special techniques are employed to randomize material deposition across the substrate.
Thus, there is a need for an improved high-T.sub.c Josephson junction that (i) overcomes the problem of electrical resistance at the base electrode/normal barrier layer interface and preserves the quality of the interfaces between the normal barrier layer and the adjacent superconductive layers; (ii) provides enhanced junction I.sub.c, and enhanced junction V.sub.c uniformity; and (iii) can be formed by a non-directional dependent process.

High-temperature SSNS and SNS Josephson junction and method of making junction


The invention provides an apparatus for metering pulverulent filling material, comprising at least one metering wheel with a plurality of metering chambers for accommodating filling material, wherein a plurality of metering chambers are formed by means of a common component, and the common component can be displaced in the radial direction of the metering wheel using an adjusting means in order to change the volume of the metering chambers.

The present invention relates to an apparatus for metering pulverulent filling material. An apparatus of the relevant type is already known from DE 10 2007 018 036 A1. This comprises a filling wheel with at least one metering chamber for accommodating filling material, wherein the metering chamber is arranged in a sleeve element. An adjusting device is provided for adjusting a position of the sleeve element in the radial direction of the filling wheel. The sleeve element is arranged in an opening in a housing.
It is the underlying object of the invention to indicate an apparatus for metering pulverulent filling material which allows simple adjustment of the metering volume with a multiplicity of metering chambers in a particularly simple manner.

Apparatus for metering pulverulent filling material


An exhaust gas purification apparatus for an internal combustion engine is designed to prevent a decrease in the accuracy of measurement by a PM sensor (17). The apparatus includes an NOx catalyst (7) provided in an exhaust passage (3) of an internal combustion engine (1) to reduce NOx by reducing agent supplied to it, a supplying device (6) that supplies urea to the NOx catalyst (7) from the upstream of the NOx catalyst (7), the PM sensor (17) that detects the amount of particulate matter in the exhaust gas in the downstream of the NOx catalyst (7), and a restriction part (10) that restricts supply of urea by the supplying device (6) when the amount of particulate matter adhering to the NOx catalyst (7) is equal to or larger than a threshold.

Patent document 1 describes an NOx selective reduction catalyst (which will be also referred to simply as "NOx catalyst" hereinafter) and a PM sensor provided downstream of a filter for trapping particulate matter (which will be sometimes referred to as "PM" hereinafter) in exhaust gas.
Patent document 2 describes that deposition of PM contained in exhaust gas on a catalyst deteriorates the catalytic effect.
Patent document 3 describes that when it is determined that a catalyst is in a poisoned condition, a determination as to the degree of deterioration of the catalyst is disabled, or outputting of a result of a determination as to the degree of deterioration of the catalyst is disabled.
Patent document 4 describes that adhesion of HC, SOF, and PM etc. to an exhaust gas purification catalyst leads to a deterioration (poisoning) of the purifying function.
Patent document 5 describes that since liquids such as condensed water have electrical conductivities higher than PM, whose main ingredient is carbon, a change in the capacitance caused by adhesion of condensed water to an electrode part of an PM sensor is significantly larger than a change in the capacity caused by adhesion of PM to the electrode part of the PM sensor.
Even if a filter is provided upstream of an NOx catalyst, a certain amount of PM passes through the filter, and consequently PM adheres to the NOx catalyst in some cases. For example, if the filter has a crack, a large amount of PM adheres to the NOx catalyst. If the surface of the NOx catalyst is covered with PM adhering to the NOx catalyst, the hydrolysis of urea is hindered. In consequence, urea passes through the NOx catalyst without being used to remove NOx in the NOx catalyst. If such urea adheres to the PM sensor, the urea affects the output value of the PM sensor, possibly leading to a deterioration in the accuracy of PM detection. In the case where a cover for protecting a PM sensor element is provided, if reducing agent adheres to the cover, PM is hard to reach the element, possibly leading to a deterioration in the accuracy of PM detection. Although a failure of the filter can be determined using the PM sensor, adhesion of urea to the PM sensor makes the determination of filter failure difficult.

Exhaust gas purification apparatus for internal combustion engine


A communications system is disclosed that allows users to effectively communicate.

In 1997, studies presented in MarkeTrak reports (MarkeTrack—The US Hearing Instrument Market, Sergei Kochkin, Ph.D., Published by Knowles Electronics, Itasca Ill.) estimated that of the 24 to 28 million Americans believed to experience significant hearing loss, approximately 21% of this population actually used hearing aids. It has also been projected in these and other studies that the impaired population is growing primarily as a result of the increase in the U.S. aging population, and due to an increase in exposure to high level sounds by the general population.
Individuals with hearing loss commonly have difficulty hearing low volume sounds as well as discriminating speech masked by speech like noise. In spite of the technical and marketing efforts of those producing hearing aids, market penetration of this population has not changed significantly. This is an unfortunate situation in that many individuals who suffer from hearing loss, and do not obtain help, tend to experience significant emotional stress by removing themselves from many desired social situations, due to an inability to effectively function.
A number of reasons have been documented, that contribute to the low penetration of hearing aid sales such as: 1) The fact that hearing loss typically comes on gradually and is not immediately obvious to an individual ("I am not convinced that 1 have a hearing problem"); 2) The negative stigma of being handicapped, associated with being a hearing aid user; 3) The belief that hearing aids do not create the same degree of improvement as say eyeglasses; and, 4) The fact that modern hearing aids are relatively expensive for their perceived value.
Hearing aid technology has however made steady improvements with respect to making sounds more audible and comfortable, as well as improving the perceived signal-to-noise ratio of amplified speech masked by noise.
In addition, products have also been developed that allow wireless connectivity between a microphone positioned near a desired but distant talker and a small radio receiver connected to a Behind-the-Ear (BTE) hearing aid. Wireless devices such as these are primarily used in teaching situations where one transmitter can serve a large number of students much like a radio station. Variations of such products have been developed as well for personal use, and in some cases allow remote communication from a cellular telephone or remote microphone by means such as a Bluetooth transmission link to a radio receiver connected to a user's hearing aid.
In general however these devices tend to be expensive, require a fair amount of user skill to operate, involve wireless transmission links that are often not secure to others monitoring the same radio channel, and do not allow two or more impaired individuals to communicate with each other in a wide variety of "real life" interactive situations.
These factors clearly indicate that products and technology that would enable the growing hearing impaired population to effectively communicate at home, in vehicles, and in a variety of private and public gatherings while at the same time removing barriers of cost, unimpressive performance, and the stigma of traditional hearing aids, is a highly desirable but unmet need.
In an embodiment, an objective of the current invention is to provide a means for individuals with varying degrees of hearing loss to effectively and easily communicate with family, friends, and the public in a variety of basic living, social and public settings.
In an embodiment, an objective of the current invention is to allow individuals with varying degrees of hearing loss to easily interact with modern communications technology such as cellular telephones, televisions, radios, computers, personal digital assistants, GPS systems, and information data bases.
In an embodiment, an objective of the current invention is to allow individuals with or without significant hearing loss to communicate more effectively in a variety of real world situations where achieving adequate speech intelligibility is difficult at best, such as in noisy restaurants, large social gatherings, and crowded public spaces.
In an embodiment, an objective of the current invention is to allow groups of individuals to communicate more effectively in business situations by eliminating the echo, interactive problems and difficulties for listeners at distant locations associated with hands free speaker telephones particularly in teleconference situations, while at the same time allowing a high degree of mobility throughout a business environment.


An implantable cardiac stimulation device, such as a pacemaker or an implantable cardioverter-defibrillator, that includes an accelerometer-based activity sensor that processes one or more signals from the activity sensor to obtain parameters that are indicative of the heartbeat of the patient. The implantable cardiac stimulation device determines when the patient is at rest and the activity sensor provides a signal that corresponds to the acceleration of the sensor due to the heartbeat of the patient. This acceleration signal is integrated over time once to provide a contractility parameter, which is indicative of the contractility of the heart and is integrated over time twice to provide a displacement parameter, which is indicative of the displacement of the heart wall during the heartbeat. This displacement parameter is thereby indicative of the volume of blood pumped by the heart. A microprocessor uses either the contractility parameter, the displacement parameter or both to modify the delivery of therapeutic stimulation pulses to the heart.

Implantable cardiac stimulation devices are commonly used to provide therapy to regulate the functioning of the heart. These types of devices include pacemakers and implantable cardioverter-defibrillators (ICD). These devices have become more versatile since their original development as these devices are better able to regulate the function of the heart to optimize the performance of the heart to meet the patient's current needs.
In particular, the more sophisticated pacemakers include sensors, which are capable of sensing the function of the heart and the activity level of the patient. This information is then used to adjust pacing parameters so that the heart is regulated to beat in the optimum manner for the particular patient given the sensed conditions. A typical method of determining the activity level of the patient is to position an accelerometer within the housing that contains the control unit for the implantable cardiac stimulation device. The housing is generally positioned within the body of the patient, e.g., under the pectoral muscle for a pectoral implant device, and the accelerometer provides a signal which is indicative of the level of activity of the patient.
The function of the heart is quite often monitored through one or more of the leads that are positioned within the chambers of the heart which provide an intracardiac electrogram (IEGM) signal to the controller that controls the operation of the implantable cardiac stimulation device. The IEGM therefore provides a signal to the controller, which is indicative of the frequency at which the heart is beating. The controller can then use the IEGM signal and the activity signal provided by the activity sensor to ascertain when and how electrical stimulation pulse therapy should be provided to the heart to optimize the function of the heart for the activity level of the patient. The controller can also use the IEGM signal to detect the occurrence of arrhythmias, which would necessitate the delivery of anti-tachycardia stimulation pulses, low or high amplitude shocks to convert the arrhythmia.
While the IEGM provides an indication as to the heart rate, the IEGM does not generally provide the controller with an indication as to the volume of blood being pumped by the heart. It is understood that the amount of blood being pumped by the heart is a factor not only of the heart rate, but also of the stroke volume of the heart. To optimize the hemodynamics of the heart, it is generally preferable that the largest volume of blood be pumped for a given heart rate. Hence, it is desirable that the controller receive some sort of signal as to the contractility or displacement of the heart which can then be used as a basis for determining the hemodynamic efficiency of the heart.
One such device is disclosed in U.S. Pat. No. 5,549,650 wherein an accelerometer is positioned within a lead that is located within one of the chambers of the heart. Preferably, this lead is attached to one of the walls of the heart so that movement of the wall of the heart is sensed by the accelerometer. The accelerometer then sends a signal to the controller, which is integrated twice. The integration of the lead accelerometer signal results in both a first signal indicative of the contractility of the heart and also a second signal, which is indicative of the physical displacement of the wall of the heart. This information can then be used by the controller to adjust the pacing parameters of the implanted device to improve the hemodynamic efficiency of the heart as this information is directly related to the volume of blood being pumped by the heart during each heartbeat.
While U.S. Pat. No. 5,549,650 discloses a device that is capable of providing information to a controller as to the volume of blood pumped during each heartbeat, it will be appreciated that mounting an accelerometer in a lead that is attached to one of the walls of the heart is both invasive and expensive. With many patients, the therapeutic benefit provided by the sensor disclosed in U.S. Pat. No. 5,549,650 would not be justified in light of the invasiveness and cost of mounting the sensor on the inner wall of the patient's heart. For these patients, the system disclosed in U.S. Pat. No. 5,549,650 does not provide a suitable solution for providing the controller with additional information to optimize the hemodynamic efficiency of the heart.
From the foregoing, it should be apparent that there is a need for a system that will provide information to the controller of an ICD or pacemaker relating to the hemodynamic performance of a patient's heart without requiring any additional implantation of hardware within the patient. In particular, there is a need for a device that will provide information about the contractility and displacement of the heart without requiring the implantation of an additional sensor within the heart of the patient.

System and method for measuring cardiac activity


A device having a checking function includes a detector for detecting unrelated data included in first inputted calculation data which is not related to a predetermined calculation to be performed on the first inputted calculation data. A memory controller is provided for controlling a memory so as not to store the unrelated data included in the first inputted calculation data when the detector detects the unrelated data. A check mode may be set whereby second inputted calculation data is compared with the stored first inputted calculation data and whereby it is then determined whether the second inputted calculation data is coincident with the stored first inputted calculation data. In addition, an indicator is provided for alerting a user when it is determined that the second inputted calculation data is not coincident with the stored first inputted calculation data.

1. Field of the Invention
The present invention relates to computers, and more particularly to a computer which has the functions of performing a calculating operation on an input series of calculation expression data, storing same and comparing the stored data with a series of calculation expression data input next to thereby perform a check operation.
2. Description of the Prior Art
Conventionally, a check operation is carried out to confirm the correctness of the result of any calculation. This check operation is performed as follows: after any calculation, the same calculation is again made and the result of the former calculation is compared with the result of the latter calculation.
A computer has been considered which has the function of checking the result of a calculation under control thereof. This computer sequentially stores a series of calculation expression data input first, and makes a calculation on the data to obtain the result of the calculation. Execution of the check operation is then designated. A second series of calculation expression data which is believed to be the same as the first input series of calculation expression data is newly input and compared sequentially with the stored first series of calculation expression data. As a result, if the first series of calculation expression data is not coincident with the second series of calculation data, this fact is reported.
However, the computer of this type stores the first input series of calculation expression data as is, inclusive of data unrelated to the actual calculation. Thus, when the check operation is performed, exactly the same input operation as that first performed is required to be performed even on any first input data unrelated to the calculation.


A gear arrangement comprising: a housing having a gear axis and a housing stop, the housing stop having a first and second abutment; a rotatable member mounted on the gear axis having a first side having a first stop and a second having a second stop, the first stop is positioned between the first abutment and the second abutment; and a gear mounted on the gear axis having a first gear side, and a second gear side having a gear stop, the gear stop is engageable and disengageable with the second stop during rotation of the gear about the gear axis, the rotatable member positioned between the housing and the gear; wherein said rotation of the gear is hindered while the gear stop and the second stop are engaged when the first stop enters into engagement with either the first abutment or the second abutment.

It is known that gear arrangements, e.g. such as those utilized in gear reduction mechanism, utilize an internal stop for a gear which rotates in both directions. However, one disadvantage of current internal stop designs is that the gear cannot rotate over an angle greater than 360 degrees in a selected direction until coming up against the internal stop.
As such, it is envisioned that alternative internal stop designs are needed to facilitate full travel end for rotations greater than 360 degrees. Accordingly, activation range of a motor (in a gear reduction mechanism) would be limited by the rotational range of its gearing e.g. part of a gear hitting a hard stop. Needed is an improved system that extends the rotation of the gear (e.g. driven by a motor) before the gear contacts a hard stop. It is recognized that hitting a hard stop in a gear reduction mechanism can cause a stall condition.

Rotary gear train assembly for increasing hard stop motor travel


Methods and apparatus for reducing deposits from a petroleum flow line are disclosed. An embodiment of an apparatus for removing deposits from a petroleum flow line may include a pipe capable of being attached to a petroleum flow line. The pipe may have a pipe axis that defines a direction for fluid flow in the petroleum flow line. The apparatus may also include a first and a second field winding circumferentially disposed around the pipe, and an electric wave generator adapted to electrically communicate an electric wave to the first field winding and the second field winding. In response to the electric wave, the first field winding is adapted to produce a first magnetic field having a first magnetic axis and the second field winding is adapted to produce a second magnetic field having a second magnetic axis. The first magnetic axis may be noncollinear with respect to the second magnetic axis, and at least the first magnetic axis may be noncollinear with respect to the pipe axis.

1. Field
The present patent application generally relates to petroleum production and more particularly to methods and apparatus for preventing, reducing, or removing deposits in petroleum pipes or pumping rods of pumping units.
2. Description of Related Technology
The global oil extraction industry has always been troubled by wax (e.g., alkanes, also known as paraffins) and dirt deposits in oil well pipes. Wax deposit causes erosion and obstruction of the pump rods, while dirt deposit leads to accelerated wear of the pump rods, thereby leading to decreased oil production and even shut down of the production in order to remove the wax with chemicals, which in turn results in chemical pollution of the environment. Serious dirt deposits may even require washing the well with hot water. Moreover, existing mechanical scrapers are both time and labor intensive, and materials and energy consuming, while the results are often less than ideal.
In order to increase oil production, currently existing technologies utilize physical and chemical principles, such as electromagnetic fields and ultrasonic waves, to reduce dirt accumulation by activating easily segregated dirt molecules using corresponding inductors, but the results are generally not satisfactory. For example, Chinese Utility Model Patent No. 99250279.9, titled "An Apparatus for Removing Wax Deposits from Oil Wells," uses a windlass to place a cable connected to a pulse signal transmitter at the bottom of a well, and transforms the pulse signal into ultrasound using a transducer in order to remove the wax deposits in the well. However, this apparatus can only function if placed inside a crude oil pipe.

This patent is subject to a terminal disclaimer.

Method and apparatus for reducing deposits in fluid conduits


A restorable sand or pellet pile is provided for use as an amusement or exercise device. A sand or pellet collection chamber has inclined side walls that converge toward each other in a downward direction and having a bottom surface connected to the side walls. A support deck is positioned above the side walls of the collection chamber and is adapted to support sand or pellets on its upper surface. A safety grating is formed around the perimeter of the support deck to allow sand or pellets to flow downwardly therethrough into the collection chamber as children or adults play or exercise on the pile. A diaphragm pump is positioned in the collection chamber and pumps sand upwardly through a vertically extending conduit to restore the pile. The pump may be operated intermittently or continuously. Other pumping mechanisms may be used. The preferred embodiment utilizes resilient inclined side walls in the collection chamber and a vibrator connected to the side walls to cause the side walls to vibrate. The vibration causes the sand or pellets to become fluidized and flow more easily into the intake of the pump.

The present invention relates generally to amusement devices and to training/exercise devices. More particularly, the present invention provides in one embodiment a restorable sand pile for use by children in which the sand is automatically collected as the pile becomes worn down and expands outwardly. The outwardly expanding sand drops downwardly through a perimeter grating and into a collection hopper. A pumping system periodically or continuously restores the sand pile to a conical shape. The present invention is capable of using materials other than sand for a restorable pile for use as an amusement device. One embodiment of the invention includes a diaphragm pump capable of pumping dry sand upwardly. The restorable sand pile may also be used for exercise or training purposes. For example, the user can run up the pile as it is being restored for cardiovascular and leg exercise.
Various devices are known in the prior art for conveying and lifting sand and other similar particulate materials that behave similar to a fluid. For example, U.S. Pat. No. 4,343,394 to Emmert et al teaches an apparatus for elevating fluent materials such as grain, sand or concrete onto a conveyor. The device utilizes a vertical auger working in conjunction with an elevated conveyor. There is no teaching or suggestion in Emmert of creating a rebuildable or restorable pile for use as an amusement or exercise device. The Carroll U.S. Pat. No. 4,887,400 teaches a granular material storage system. This system utilizes a rather complex mechanism for creating a conical storage pile for grain. This patent does not teach or suggest reconstituting a conical pile of materials for use as an amusement or exercise device. The Cipriani U.S. Pat. No. 5,967,704 teaches a pneumatic system for conveying granular material. Again, this patent does not teach or suggest a restorable conical pile of fluent material which is usable as an amusement or exercise device.
The present invention provides for the first time a sand or pellet pile for use as an amusement or exercise device which, in its preferred form, is automatically restorable. The present invention provides a system which can also be transportable to a site, such as a birthday party or other special occasion, in which a sand or pellet pile would be an attraction. The present invention includes a variety of built-in safety mechanisms and a relatively simple but, yet, rugged design capable of withstanding intensive use by children. Applicant believes this is the first mechanism ever for providing a mechanically and/or automatically restorable sand or pellet pile for use by children of all ages as an amusement or exercise device. The present invention provides, in its preferred embodiment, a diaphragm pump capable of pumping dry sand upwardly. The applicant believes this is the first pump capable of pumping dry sand in an upward direction.
A primary object of the invention is to provide an amusement device wherein a sand pile or pellet pile is automatically or mechanically restorable to a conical shape and which allows continuous use by children and/or adults.
A further object of the invention is to provide a conical pile of material, such as sand or pellets, for use as an amusement or exercise device which is automatically restorable to a conical shape.
Another object of the invention is to provide a simple but rugged design for a restorable sand pile, for example, capable of withstanding continuous use by children and/or adults.
Yet another object of the invention is to provide a transportable amusement or exercise device which includes an automatically or mechanically restorable conical pile of sand or other fluent material.
A further object of the invention is to provide a diaphragm pump capable of pumping dry sand either vertically upwards or upwardly at an angle.
Another object of the invention is to provide a sand collection hopper with tapered side walls wherein said tapered side walls are agitated or vibrated in order to fluidize said sand to cause the sand to flow more easily into the pump mechanism.
Other objects and advantages of the invention will become apparent from the following description and the drawings wherein:


This invention provides a method of screening or patterning a biomaterial in terms of their specificities to sugar chains by performing real-time and comprehensive measurement of an interaction between sugar chains and the biomaterial concurrently with a very small amount of the biomaterial without labeling. It is a method of measuring an interaction between a biomaterial and a sugar chain(s), the method including: bringing a solution containing the biomaterial in contact with a ligand carrier, the ligand carrier including a support whose surface includes a metal, and a ligand conjugate(s) immobilized independently on the surface, the ligand carrier carrying the ligand conjugate(s) in such a manner that 1 to 500 kinds of the ligand conjugate(s) is immobilized per cm2, and each ligand conjugate having a structure in which a sugar chain is bonded with a linker compound having a sulfur atom, and the biomaterial being at least one selected from the groups of proteins, viruses, cells, microorganisms, liposome, and micelles.

Sugar chains are compounds in which sugars are bonded via glycoside bonding. There are infinite combinations of sugars considering kinds and sequences of sugars constituting the sugar chains. Therefore, there are a great variety of the sugar chains. It is known that sugar chains interact with various biomaterial such as viruses, cells, microorganisms, proteins, etc. Thus, the interactions of the sugar chains with the biomaterials largely influence physiological conditions of living organisms.
For example, it is known that infections of influenza virus, AIDS virus, and hepatitis B virus, which causes severe diseases in infected people, are initiated by interaction of these viruses with sugar chains in cell membranes of human cells. Different viruses interact with different sugar chains. This accounts for differences of virus infections in their infection routs and symptoms that they cause in humans.
For example, as disclosed in Virology, 1997, 227, 493-499, it is understood that isolated influenza virus strain interact with different sugar chains that are different in constituent sugars and sugar sequences. It is known that human-infectious influenza viruses generally interact with N-acetyl neuraminic acid α2,6-galactose (Neu5Ac α2,6 Gal) more strongly than N-acetyl neuraminic acid α2,3-galactose (Neu5Ac α2,3 Gal).
Therefore, comprehensive measurement on interactions of a virus with sugar chains is weighed heavily in developing strategies for prevention and remedy against the infection of the virus.

Method of measuring interaction between biomaterial and sugar chain, method of evaluating biomaterial in sugar chain selectivity, method of screening biomaterial, method of patterning biomaterials, and kits for performing these methods