Prior to the reprogramming of a selected flash memory cell of a memory cell array, electrons being removed from the memory layer (M) in the channel region (C) by Fowler-Nordheim tunneling, a lower potential for incipient programming of the memory cell is applied to the relevant word line (WLn) while the associated bit line (BLm) remains at the basic potential. What is thereby achieved is that a gate disturb occurring during the programming operation does not lead to erratic bits along the affected word line (WLn).

The memory cells of a semiconductor memory component in each case have a transistor structure having a channel region in semiconductor material between source and drain, a gate electrode electrically insulated from the channel region, and associated electrical terminals. In a memory cell array with NOR architecture, for example, the gate electrodes are connected to one another row-wise via word lines and the drain regions are connected to one another column-wise via bit lines. For the programming of a memory cell, a memory layer is situated between the gate electrode and the channel, which memory layer is electrically insulated both from the gate electrode and from the semiconductor material of the channel region and may be a floating gate electrode, for example. A floating gate electrode is formed by an electrical conductor that is electrically insulated all around and is not connected to any potential. Charge carriers, preferably electrons, may be accumulated on the floating gate electrode and define the programming state.
Depending on the cell conception, the electrons pass for example by Fowler-Nordheim tunneling through the electrically insulating material between the channel region and the floating gate electrode or by injection of hot electrons from the channel (CHE, channel hot electrons) onto the floating gate electrode. In the case of the last-mentioned programming operation, electrons are accelerated in the channel region and pass as hot, i.e., high-energy, electrons via the lower insulation layer (gate oxide) into the memory layer. In the case of such memory cells, the erase operation is effected by Fowler-Nordheim tunneling of charge carriers through one of the insulation layers bounding the memory layer.
Instead of a memory layer made of conductive material, electrically insulating material may also be provided, as in the case of so-called charge trapping memory cells, in which the memory layer is, for example, a nitride layer between oxide layers. During the programming operation, electrons are accelerated in the channel region and pass as hot, i.e., high-energy, electrons through the lower oxide layer into the memory layer made of nitride. During the erase operation, Fowler-Nordheim tunneling of charge carriers through one of the oxide layers is effected in the case of such memory cells, too.
The further explanations relate specifically to the case of a flash cell with a floating gate electrode. A potential of 0 volts (ground) is in each case assumed as basic potentials for the word lines and the bit lines. During an erase operation of a memory cell row, a positive voltage is applied to the relevant word line, which voltage draws electrons onto the floating gate. During a programming operation by which a bit is written to the memory cell (write), a negative electrical potential is applied to the associated word line. The bit line of the column of the relevant memory cell is connected to a positive potential, while the nonselected columns have a bit line voltage of 0 volts. The negative electrical potential on the word line is present at all the gate electrodes of the memory cells of the relevant row. As a result, a so-called gate disturb occurs at all the nonselected memory cells and, in the case of the predominant number of memory cells, leaves the information stored therein unchanged.
However, there are a certain number of memory cells, which exhibit a significant shift in the threshold voltage after a gate disturb, so that the relevant cell is practically reprogrammed. Consequently, the relevant cell fails as an information carrier or must at least be programmed anew. These sporadically and randomly distributed incorrect programmings of the information content are referred to as erratic bits. Each memory cell may have such an incorrect behavior with a certain probability in each programming cycle. However, the entire memory is already incorrectly programmed if just a single bit has been incorrectly programmed. Therefore, an incorrect programming of the entire memory may occur with a relatively high probability in each programming cycle. However, the erratic bits do not have the effect that the memory as such is defective; the memory cells with erratic bits may already have a normal behavior again in the next cycle.
In principle, any cell may be affected by the occurrence of erratic bits. As a result, incorrect programmings may occur repeatedly in the application of the memory component. The problem cannot be eliminated by selection of functional components. Hitherto, the cells have been correctly programmed, as necessary, by repeated erase-write cycles. If appropriate, the error rate of the memory chip is reduced by means of an ECC (error correction code) at least to an extent such that specified product requirements are complied with. It would be desirable, however, to have a flash memory chip in which the occurrence of erratic bits is at least largely avoided.

Method for operating a memory cell array


A formulation and process for capturing CO2 use an absorption mixture containing water, biocatalysts and a carbonate compound. The process includes contacting a CO2-containing gas with the absorption mixture to enable dissolution and transformation of CO2 into bicarbonate and hydrogen ions, thereby producing a CO2-depleted gas and an ion-rich solution, followed by subjecting the ion-rich solution to desorption. The biocatalyst improves absorption of the mixture comprising carbonate compounds and the carbonate compound promotes release of the bicarbonate ions from the ion-rich solution during desorption, producing a CO2 gas stream and an ion-depleted solution.

Increasingly dire warnings of the dangers of climate change by the world's scientific community combined with greater public awareness and concern over the issue has prompted increased momentum towards global regulation aimed at reducing man-made greenhouse gas (GHGs) emissions, most notably carbon dioxide. Ultimately, a significant cut in North American and global CO2 emissions will require reductions from the electricity production sector, the single largest source of CO2 worldwide. According to the International Energy Agency's (IEA) GHG Program, as of 2006 there were nearly 5,000 fossil fuel power plants worldwide generating nearly 11 billion tons of CO2, representing nearly 40% of total global anthropogenic CO2 emissions. Of these emissions from the power generation sector, 61% were from coal fired plants. Although the long-term agenda advocated by governments is replacement of fossil fuel generation by renewables, growing energy demand, combined with the enormous dependence on fossil generation in the near to medium term dictates that this fossil base remain operational. Thus, to implement an effective GHG reduction system will require that the CO2 emissions generated by this sector be mitigated, with carbon capture and storage (CCS) providing one of the best known solutions.
The CCS process removes CO2 from a CO2 containing flue gas, enables production of a highly concentrated CO2 gas stream which is compressed and transported to a sequestration site. This site may be a depleted oil field or a saline aquifer. Sequestration in ocean and mineral carbonation are two alternate ways to sequester that are in the research phase. Captured CO2 can also be used for enhanced oil recovery.
Current technologies for CO2 capture are based primarily on the use of amines solutions which are circulated through two main distinct units: an absorption tower coupled to a desorption (or stripping) tower.
A very significant barrier to adoption of carbon capture technology on large scale is cost of capture. Conventional CO2 capture with available technology, based primarily on the use of amine solvents, is an energy intensive process that involves heating the solvent to high temperature to strip the CO2 (and regenerate the solvent) for underground sequestration. The conventional use of amines involves an associated capture cost of approximately US $60 per ton of CO2 (IPCC), which represents approximately 80% of the total cost of carbon capture and sequestration (CCS), the remaining 20% being attributable to CO2 compression, pipelining, storage and monitoring. This large cost for the capture portion has, to present, made large scale CCS unviable; based on data from the IPCC, for instance, for a 700 megawatt (MW) pulverized coal power plant that produces 4 million metric tons of CO2 per year, the capital cost of conventional CO2 capture equipment on a retrofit basis would be nearly $800 million and the annual operating cost and plant energy penalty would be nearly $240 million. As such, there is a need to reduce the costs of the process and develop new and innovative approaches to the problem.
Due to the high costs associated with amine systems, some work has been done based on carbonate solutions. In such carbonate systems, at pH higher than 10, the predominant mechanism for CO2 absorption is:CO2+OH−HCO2−HCO2−+OH−CO22−+H2O
At pH lower than 8, the principal mechanism is:CO2+H2OH2CO2 H2CO2+OH−HCO2−+H2O
The main advantages of carbonate solutions over amine based solutions are higher capacity, higher stability to oxygen and high temperatures and lower energy requirements for desorption. However, such known carbonate solutions are characterized by a low rate of absorption of CO2 which results in large capture equipment and corresponding capital costs.
Another feature of carbonate based solutions is that, as CO2 reacts with the compound, the product may form precipitates. The presence of solids in the absorption solution enables the shift of the chemical reaction equilibria resulting in a constant CO2 pressure when the loading of the solution increases.
Biocatalysts have also been used for CO2 absorption purposes. More specifically, CO2 transformation may be catalyzed by the enzyme carbonic anhydrase as follows:

Under optimum conditions, the catalyzed turnover rate of this reaction may reach 1×106 molecules/second.
Carbonic anhydrase has been used as an absorption promoter in amine based solutions to increase the rate of CO2 absorption. Indeed, particular focus has been made on amine solutions for use in conjunction with carbonic anhydrase in CO2 capture processes. One reason why amine solutions have been favoured is that they have relatively low ionic strength, which is a property viewed as significant for carbonic anhydrase hydration activity, since high ionic strength could be detrimental to the stability and function of the protein.
There is a need for a technology that overcomes at least some of the disadvantages of the processes and techniques that are already known, and offers an improvement in the field of CO2 capture.

This patent is subject to a terminal disclaimer.


The present disclosure provides systems and methods to detect and reduce any high driveline torsional levels, such as due to the cylinder deactivation in variable displacement system engines or aggressive lock-up strategies for fuel efficiency, in automobile transmissions. The present disclosure utilizes a controller in an automobile to operate a computationally thrifty method for quickly detecting noise and vibration disturbances in the transmission. This quick detection enables fuel economic calibrations that aggressively reduce the disturbances by controlling slip in a launch device of the transmission. As problem disturbances arise, they are detected before occupants notice objectionable behavior. Once detected, the disturbances are reduced, such as by increasing launch device slip, which effectively intercepts the objectionable disturbances before they are transferred through the entire drivetrain. The present disclosure can also apply to launch devices in Dual Clutch Transmissions and Electronically-controlled Manual Transmissions.

Variable displacement systems work by selectively turning off cylinders in an engine, such as a bank of cylinders in a V-type engine. An example of a variable displacement system is the Multi-Displacement System (MDS) available from DaimlerChrysler Corp. of Auburn Hills, Mich. For example, a variable displacement system can deactivate three or four cylinders in a V6 or V8 engine, respectively, when the torque demand of the engine is relatively low. Advantageously, such variable displacement systems improve fuel economy in modern automobiles.
Disadvantageously, disturbances can arise from any high driveline torsional vibration levels, such as due to the cylinder deactivation in variable displacement system engines or aggressive lock-up strategies to improve fuel efficiency. These disturbances can potentially cause objectionable noise, vibration, and harshness (NVH) to automobile occupants. Modern automobiles utilize conservative calibrations for controlling slip in a launch device of a transmission, such as a torque converter, to prevent NVH from disturbing occupants. However, such conservative calibrations waste fuel. Modern automobiles do not currently employ direct feedback to control the slip in the launch device. A toque converter utilizes a torque converter lock-up clutch to prevent converter slip, however there currently does not exist a direct feedback system to control the lock-up clinch. For example, there are instances when a lightly-loaded powertrain running in third or fourth gear with a locked torque converter at 1000 revolutions-per-minute (rpm) performs without objectionable NVH. However because some road conditions (e.g., a slight uphill grade) may induce disturbances, a locked-up converter during cylinder reduced operation at 1000 rpm in these gears cannot be permitted for fear of NVH.

Systems and methods for detecting and reducing high driveline torsional levels in automobile transmissions


A spin valve magnetoresistive head comprises a first spin valve device having a first magnetization free layer and a first magnetization pinning layer via a first non-magnetic intermediate layer, a second spin valve device having a second magnetization free layer and a second magnetization pinning layer via a second non-magnetic intermediate layer, whereby the first and second magnetization pinning layers are magnetized in anti-parallel to each other and the first and second magnetization free layers are magnetized rotatably based on an external magnetic field.

1. Field of the Invention
The present invention relates to a spin valve magnetoresistive head, a method of manufacturing the same, and a magnetic memory apparatus and, more particularly, to a spin valve magnetoresistive head for use in a magnetic disk drive, a magnetic tape unit, etc., a method of manufacturing the same, and a magnetic memory apparatus.
2. Description of the Prior Art
In recent years, with miniaturization and increase in storage capacity of the magnetic disk drive, higher performance of the magnetic head is required. As the design of magnetic heads meet such requirements, great attention has been given to a magnetoresistive type magnetic head (referred to as a "MR head" hereinafter) which can operate without depending on the moving speed of storage medium, can be applied to a small size disk, and can output higher outputs.
AMR (anisotropic MR) head using magnetically biased conductor layers, spin valve MR head, giant MR head, and others may be considered as the MR head.
The MR head that uses the magnetically biased conductor layers, such has a structure such that part of the MR layers and lead terminals are exposed to oppose to a magnetic recording medium. In the MR head having such structure, short-circuit or discharge between the magnetic head and the magnetic recording medium is possible when a flying height of the magnetic head from the magnetic recording medium is reduced. As a result, it is feared that the magnetic head would be damaged.
The magnetic head having a structure able to overcome such a problem has been set forth in Patent Application Publication (KOKAI) 63-23217, for instance, wherein the MR layers are arranged to flow sense currents in the same direction as the signal magnetic field and only grounding lead terminals are exposed to the magnetic recording medium side. This MR head is particularly effective in a contact region between a surface of the magnetic recording medium and the MR head. The MR magnetic head having such structure is called a vertical MR head.
In addition, it is very possible that thermal asperity occurs in the MR head when the MR head collides with projections on the surface of the magnetic recording medium. The thermal asperity is expressed as a raise of the temperature of the MR device because of collision of the MR head with projections to thus increase electric resistance value.
As one countermeasure to suppress generation of the thermal asperity, a dual element type MR head has been proposed. This MR head has been set forth in, for example, Thomas C. Anthony et al., IEEE Transactions on Magnetics, Vol.30, No.2, March 1994, pp.303-308.
In these MR head, as shown in FIG. 1 for illustrative purposes only, the first MR layer 103 and the second MR layer 104 connected to leads 101, 102 respectively are arranged in parallel and sense currents passing through these first and second MR layers 103, 104 are detected in a differential manner by directing respective directions of the sense currents I.sub.1,I.sub.2 to mutually opposite directions. Simbol H.sub.sig is a signal magnetic field.
Though resistance of the first and second MR layers 103, 104 are increased respectively, as shown in FIG. 2, once the thermal asperity has occurred, in-phase components of the resistance are canceled mutually since they are detected in a differential manner. Where the sense current I.sub.1,I.sub.2 is a constant current and therefore the change in resistance appears as the change in voltage.
Furthermore, the MR head having both the above vertical MR head and the dual element type MR head has been set forth in Patent Application Publication (KOKAI) 7-21530.
However, since the MR head set forth in the Patent Application Publication (KOKAI) 7-21530 is the MR head having biased conductive layers, no mention concerning a spin valve type MR head has been given in the Patent Application Publication (KOKAI) 7-21530 since a basic structure of the former differs from that of the latter. Accordingly, it is impossible to apply the structure disclosed in this Patent Application Publication (KOKAI) 7-21530 to the spin valve type MR head as it is.

Spin valve magnetoresistive head with spun valves connected in series


An exercise apparatus is provided including a frame and a pair of pedals pivotally coupled to the frame in a side-by-side relationship. A resistance mechanism is included for urging the pedals upwardly. Further, a fulcrum and rod combination is provided for ensuring that only one pedal is capable of being raised at a time.

1. Field of the Invention
The present invention relates to exercise apparatuses and more particularly pertains to a new shower exercise device for performing a stepping type exercise in a shower.
2. Description of the Prior Art
The use of exercise apparatuses is known in the prior art. More specifically, exercise apparatuses heretofore devised and utilized are known to consist basically of familiar, expected and obvious structural configurations, notwithstanding the myriad of designs encompassed by the crowded prior art which have been developed for the fulfillment of countless objectives and requirements.
Known prior art exercise apparatuses include U.S. Pat. No. 5,385,525; U.S. Pat. No. 4,111,416; U.S. patent Des. 281,343; U.S. Pat. No. 5,352,173; U.S. Pat. No. 5,263,910; and U.S. Pat. No. 4,911,437.
In these respects, the shower exercise device according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of performing a stepping type exercise in a shower.


A fuel tank for a spacecraft stores a liquid fuel and a pressurized propellant gas that drives the fuel out of the tank through a fuel extraction arrangement including a reservoir or collection container and a tank outlet. The collection container bounds a fuel reservoir space that communicates with the interior space of the tank, and fuel flow channels connect the reservoir space to an outlet pipe. A side or area of the collection container opposite the fuel flow channels is provided with one or more grooves. These structures produce a capillary pumping effect and use the surface tension to separate the fuel from the propellant gas.

Spacecraft such as rockets, shuttles, satellites, orbital stations, and other bodies flying in space are typically outfitted with suitable containers or fuel tanks for storing liquid fuels that are used to power the engines, including engines or thrusters for carrying out apogee maneuvers as well as position regulation in space. In order to drive or propel the liquid fuel out of the fuel tank, the fuel tank is typically also charged with a pressurizing gas or propellant gas, which serves to pressurize the fuel and drive the fuel to the combustion or reaction chambers of the engines. Inert gases such as helium (He) or nitrogen (N2) are typically used as the propellant gases, which are introduced under pressure into the fuel tank, and which thus serve to press the liquid fuel from the fuel tank into the piping system leading to the respective engine. The liquid fuel may be an aggressive storable liquid fuel such as MMH, N2O4, or hydrazine.
With such gas-charged fuel tanks, it is very important to achieve a complete, sure and reliable separation between the propellant gas serving as a conveying medium, and the liquid fuel that is conveyed or delivered to the engine. Namely, when the liquid fuel is delivered to the engine, it is crucial that the liquid fuel must be free of foreign gas inclusions or bubbles at the time of ignition of the fuel. Otherwise, the ignition of the fuel, and the reliable operation of the engine, could be jeopardized.
A fuel tank of the above described general type and operating according to the above described principle is known from the German Patent 100 40 755. Moreover, U.S. Pat. No. 5,293,895 discloses a fuel tank for use in space, whereby the outlet of the tank includes an arrangement of an outlet pipe connected with a reservoir or collection container via a plurality of bored holes.
A standard known method of separating liquids and gases from one another involves the use of screens or sieves, which block the throughflow of gases up to a certain pressure difference across the screen or sieve. Separating devices using such sieves, however, are relatively expensive and complicated. In small satellites with relatively low fuel volume delivery flows, it is possible to avoid the use of such relatively expensive sieves under certain circumstances. Namely, it is desirable to reduce the cost and complexity of the fuel separating arrangements if possible.
A special and often called-for requirement of such tanks is additionally the possibility of transporting the already-filled fuel tank in a horizontal orientation, while the tank is integrated in a satellite, as the satellite is transported to the launch location. This is especially significant, when limitations on the degree of tank filling are to be avoided. Due to dynamic effects, the forces arising during the transport can amount to or exceed a multiple of the forces arising due to normal earth's gravity. In the previously known tanks of this type, it has therefore either been necessary to limit the degree of tank filling in the direction of smaller or partial filling, so that the tank outlet would always be covered or surrounded with liquid, or been necessary to bound the tank outlet by a very narrow or tight channel, which, however, produces relatively high pressure losses when the fuel is withdrawn from the tank during operation. The maximum permissible pressure losses that can occur in that regard are typically prescribed.
A further requirement is the possibility that a satellite equipped with such a tank can be launched into orbit in an orientation perpendicular to the tank outlet. This possibility is especially pertinent for the transport of several small satellites that are arranged laterally horizontally on a central carrier structure. The high dynamic loads that arise during a rocket launch cause any exposed sieves or openings typically to loose their holding or retaining ability, that is to say an entry or penetration of the propellant gas into the outlet cannot be prevented. This leads to a failure if the fuel tank is not completely filled and sensitive components such as sieves and openings protrude out of the liquid. In that case, the propellant gas can penetrate through the sieves and openings to the tank outlet under high load conditions, which similarly lead to a failure of the engine. Therefore, with previously known tanks of the above described type, it has not been possible to carry out a rocket launch with a horizontally oriented tank.


A method and device for sidelink data duplication. The method includes: determining whether a sidelink data packet is to be duplicated based on a sidelink radio bearer on which the sidelink data packet is to be transmitted; performing sidelink data duplication of the sidelink data packet, when it is determined that the sidelink data packet is to be duplicated based on the sidelink radio bearer. Therefore, a solution provides for properly configuring data duplication for sidelink.

This section introduces aspects that may facilitate better understanding of the present disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
In release 14 of long term evolution (LTE), a plurality of extensions for device to device (D2D), or maybe referred to as ProSe or sidelink, support V2X (Vehicle-to-Everything) communications. In particular, the sidelink may refer to a UE to UE interface for sidelink communication, V2X sidelink communication and sidelink discovery. The sidelink corresponds to the PC5 interface as defined in 3GPP TS 23.303.
V2X may include any combination of direct communication between vehicles, pedestrians and infrastructures. V2X may take advantage of a network (NW) infrastructure when it is available, but at least a basic V2X connectivity should be possible even in case of lack of coverage.
V2X may carry both non-safety and safety information, where each of applications and services (or referred to as traffics) may be associated with specific requirements, e.g., in terms of latency, reliability and capacity. There are several different use cases defined for V2X, such as V2V (vehicle-to-vehicle), V2P (vehicle-to-pedestrian), V2N (vehicle-to-network) and V2I (vehicle-to-infrastructure).
On the other hand, there are two different resource allocation (RA) procedures for V2X on sidelink, i.e. centralized RA (which may be called "mode 3") and distributed RA (which may be called "mode 4"). One or more transmission resources are selected from one or more resource pools which is/are predefined or configured by a network device.
With the centralized RA, one or more sidelink resources for transmission may be scheduled by a network device and signaled to a terminal device using downlink control information (DCI), such as in DCI format 5A. This is the case for both physical sidelink control channel (PSCCH) and physical sidelink shared channel (PSSCH).
With the distributed RA, each terminal device may independently decide one or more sidelink resources for each transmission, such as for both PSCCH and PSSCH. The sidelink resources are selected by the terminal device from one or more resource pools configured by the network device using a broadcast signaling, such as a system information block (SIB).
In addition, a logical channel prioritization procedure is applied when a new transmission is performed. Each sidelink logical channel may have an associated priority, which may be referred to as ProSe per packet priority (PPPP). Multiple sidelink logical channels may have the same associated priority.
An application layer of the terminal device may set the PPPP for each V2X message when the message is transmitted to a lower layer for transmission. A packet delay budget (PDB) of a protocol data unit (PDU) may be determined from the PPPP. A low PDB may be mapped to a high priority value of the PPPP. The terminal device may indicate a traffic priority (e.g., PPPP) for a sidelink communication to the network device.

Method and device for sidelink data duplication


Systems and methods for cleaning and maintaining artificial airways sized for insertion within pediatric or neonatal patients (e.g., external diameters of less than 5 mm) are disclosed. The system includes a multi-port ventilator manifold configured to couple to a ventilation source, thereby forming a ventilator circuit with the patient. The manifold includes an occluder configured to advantageously reduce an amount of dead space in the manifold so as to prevent loss of positive end expiratory pressure of the ventilator circuit and reduce the likelihood of broncho-pulmonary dysplasia of the patient, or even premature death.

During an intubation procedure, endotracheal tubes can be placed in patients who are unable to effectively maintain life-sustaining ventilation and respiration on their own. An endotracheal tube is used in patient care to ensure a clear airway through the mouth, pharynx, and trachea into the lungs. Use of an endotracheal tube is appropriate when the integrity of the airway is, or may become, challenged due to trauma or pathology, or if a patient cannot otherwise breathe unaided. Often the endotracheal tube is coupled to a mechanical ventilator to aid the patient's respiration, and can be expected to remain in situ for an extended time until the patient is once again able to breathe on his or her own. The endotracheal tubes can be inserted within a patient's native airway for short periods of time (e.g., for a matter of hours during anesthesia for surgery) or the endotracheal tubes can remain in place to provide ventilator-assisted breathing for days or weeks.
The institution of mechanical ventilation can result in increased production of secretions within the patient's native airways and accumulation of those secretions within an artificial airway such as an endotracheal tube. The insertion of an endotracheal tube within the patient's trachea renders the normal cough mechanism for clearing of secretions ineffective, as the patient cannot transiently close the glottis to build up pressure in the airway that, when released, helps expel secretions. Also, the mucociliary system which helps transport secretions and debris from the tracheobronchial tree into the trachea for expectoration becomes ineffective in the sick, intubated patient. The secretions, therefore, can pool in dependent portions of the lung over time due to gravity and, if not removed in a timely manner, can result in ventilator-acquired pneumonia (VAP) or other undesired conditions or ailments. Closed suction systems may be coupled to the endotracheal tube and a suction catheter may be used to suction out the pooled secretions or other debris within the patient's native airways and/or the endotracheal tube. Intraluminal volume loss attributable to the accumulation of secretions on the interior wall of endotracheal tubes is not prevented by standard suctioning treatment. Secretion accumulation can lead to life-threatening occlusion of the endotracheal tube or at least increased work of breathing, which may result in increased difficulty in weaning, and prolonged mechanical ventilation and intensive care unit stay, especially for neonatal and pediatric-sized endotracheal tubes. Additionally, secretion accumulation on the inside of the endotracheal tube leads to colonization with potentially pathological organisms and this colonization is likewise implicated in the development of VAP.

Artificial airway management devices, systems and methods


To implement an electrode structure which brings about extinction of arc quickly in a reliable manner without maintaining discharge current, and provide an electron source and image display apparatus equipped with the electrode structure.

1. Field of the Invention
The present invention relates to an electron source with an electrode structure which reduces discharges as well as to an image display apparatus which uses the electron source.
2. Description of the Related Art
Conventional uses of electron-emitting devices include image display apparatus. For example, an evacuated flat electron beam display panel in which an electron source substrate and counter substrate are placed opposite each other in parallel is known, where the electron source substrate contains a large number of cold-cathode electron-emitting devices and the counter substrate is equipped with an anode electrode which accelerates electrons emitted from the electron-emitting devices and phosphor which acts as a light emitting member. The flat electron beam display panel can have lighter weight and larger screen size than cathode ray tube (CRT) display apparatus widely used today. Also, it can provide brighter, higher-quality images than other flat display panels such as flat liquid crystal display panels, plasma displays, and electroluminescent displays.
Thus, for image display apparatus which apply voltage between the anode electrode and cold-cathode electron-emitting devices to accelerate the electrons emitted from the cold-cathode electron-emitting devices, it is advantageous to apply a high voltage to maximize emission brightness. Emitted electron beams are dispersed before reaching the anode electrode depending on the type of device, and thus, to implement a high-resolution display, it is preferable to reduce inter-substrate distance between rear plate and face plate.
However, a shorter inter-substrate distance essentially results in a higher electric field between the substrates, making the electron-emitting devices more susceptible to breakage due to discharges. Japanese Patent Application Laid-Open No. H09-298030 discloses an image display apparatus which places an overcurrent protective member of a low melting-point material between a conductive film equipped with an electron-emitting area and device electrodes and thereby prevents impacts on other devices in case of a short circuit between device electrodes. Japanese Patent Application Laid-Open No. H09-245689 discloses an image display apparatus which places a fuse outside an active area. Japanese Patent Application Laid-Open No. H07-94076 discloses an idea of installing a resistive layer which is burnt out by a short-circuit current, to provide against an emitter-gate short circuit in an FED. It also discloses that by covering the resistive layer with an insulating layer, it is possible to prevent gas generation in case the resistive layer melts, and thereby prevent secondary discharges caused by gas.
However, the techniques disclosed in Japanese Patent Application Laid-Open No. H09-298030, Japanese Patent Application Laid-Open No. H09-245689 and Japanese Patent Application Laid-Open No. H07-94076 are not sufficient and there has been a demand for a method which can prevent the impact of discharges more reliably. If voltage applied to an image forming member is set at a high level, fuses burnt out by discharges can sometimes cause new discharges to be generated, resulting in discharging of large current for an extended period of time. This increases damage and fatally contaminates a vacuum atmosphere in the panel, posing a serious problem to device reliability.

Electron source and image display apparatus

Abstract: Device electrodes 2 and 3 are partially narrowed in areas where they are connected to scan wiring 6 and signal wiring 4, and an insulating layer 5 which insulates the scan wiring 6 and signal wiring 4 are extended to cover the narrow portions of the device electrodes 2 and 3.


A circuit is provided which generates a reference bias current using a difference in base-emitter voltages of two bipolar transistors imposed across a source terminal and a drain terminal of an MOS transistor. The circuit includes a circuit for compensating shifts in threshold voltage, and thus shifts in the current flowing therein, of the MOS transistor. In one embodiment, the bias circuit is configured to achieve superior efficiency in generating small bias currents. In another embodiment, the bias circuit is configured to operate using minimal voltage supplies. In all embodiments, the reference bias current generated thereby has a positive temperature coefficient and is substantially independent of process variations.

1. Field of the Invention
The present invention relates to the design of electronic circuits, and in particular, relates to the design of CMOS integrated circuits.
2. Discussion of Related Art
A reference bias current can be generating from the difference in the base-emitter voltages of two bipolar transistors of different current densities. One such reference bias current generation circuit is shown in FIG. 1. Referring to FIG. 1, reference bias current generation circuit 100 employs NPN bipolar transistors 102 and 104 to generate a reference bias current I.sub.ref which may be used to bias other circuits (not shown). In circuit 100, transistor 104 is designed to have a larger emitter area than does transistor 102 and, as a result, will thus exhibit a smaller current density than will transistor 102. P-channel MOS transistors 106 and 108 source equal currents to the respective collectors of transistors 102 and 104. Thus, when both transistors 102 and 104 are conducting in the linear region, a difference .DELTA.V.sub.BE between their base-emitter voltages results. The emitter terminal of transistor 104 is coupled to a current source 110 by a resistor 112. Thus, the current I.sub.ref generated by circuit 100 is determined by the resistance R of resistor 112, where I.sub.ref =.DELTA.V.sub.BE /R.
Another example of a reference bias current circuit is shown in FIG. 2. Reference bias current generation circuit 200 includes NPN bipolar transistors 202 and 204 which are designed to have different emitter areas and will thus exhibit different current densities. The emitter terminal of transistor 202 is coupled to a current source 206 by a resistor 208 having a resistance R. The emitter terminal of transistor 204 is coupled to current source 210. Current sources 206 and 210 are designed to sink substantially equal currents such that the emitter currents of transistors 202 and 204 are substantially equal.
In circuit 200, the voltage on node 212 (at the emitter terminal of transistor 204) and the voltage on node 214 are forced to be equal by the high gain of an operational amplifier 216, which provides a feedback signal at terminal 218 to control current sources 206 and 210. In equilibrium, the difference in base-emitter voltages of transistors 202 and 204 appears across resistor 208, where .DELTA.V.sub.BE =V.sub.be,Q202 -V.sub.be,Q204 =I.sub.ref R. Thus, the current I.sub.ref in each of current sources 206 and 210 is determined by the resistance R of resistor 208, where I.sub.ref =.DELTA.V.sub.BE /R. A current mirror can be used to generate a current equal to I.sub.ref or, in other embodiments, to any fraction or multiple of I.sub.ref.
In both of the prior art circuits discussed above, a reference bias current arising from the difference in base-emitter voltages of two bipolar transistors is generated by imposing such voltage difference across a resistor. However, if a small reference bias current is preferred, such a resistor would in an integrated circuit implementation require an unreasonably large amount of silicon real estate. For example, in circuit 200 of FIG. 2, if the emitter ratio between transistors 202 and 204 is 10:1, a .DELTA.V.sub.BE of approximately 60 millivolts is achieved. In such an implementation, providing reference currents I.sub.ref of 200 nanoamps and 60 nanoamps requires approximately 300 kilo-ohm and 1 Mega-ohm resistances R, respectively. Implementing such large resistances is uneconomical.
Alternatively, the resistor employed in the prior art circuits may be replaced by a field effect transistor (FET) operating in the non-saturation or "triode" region. Such an FET requires a much smaller silicon real estate than does a resistor conducting the same amount of current. However, the use of an FET has at least two disadvantages. First, the threshold voltage V.sub.T of such a transistor is known to vary substantially with variations in the manufacturing process. Consequently, the equivalent resistance attainable by such FET fluctuates with variations in the manufacturing process, thereby leading to large variations in the generated bias current. Secondly, the threshold voltage of such as FET is known to have a negative temperature coefficient. Consequently, the bias current generated by such an FET also has a negative temperature coefficient TC, which is undesirable for most amplifier applications.
FIG. 3 shows a reference bias current generating circuit 300 which overcomes the two disadvantages mentioned above by providing a matched reference transistor that tracks and effectively cancels process variations of the above mentioned FET such that the resistance of the FET is insensitive to process variations. Circuit 300 is described in detail in U.S. Pat. No. 5,469,111 issued to Kwok-Fu Chiu on Nov. 21, 1995 and assigned to National Semiconductor Corp, also the assignee of the present invention, hereby incorporated by reference.
Circuit 300 includes NPN transistors 302 and 304 which are designed to have different emitter areas and will thus exhibit different current densities. The emitter terminal of transistor 302 is coupled to a current source 308 by an NMOS transistor MN.sub.R having a resistance R. The emitter terminal of transistor 304 is coupled to a current source 310. Current sources 308 and 310 are designed to conduct substantially equal currents. Transistor MN.sub.R acts as a resistor in the reference bias current generation circuit 300, in that the difference .DELTA.V.sub.BE in base-emitter voltages of NPN transistors 302 and 304 appears across the drain terminal and the source terminal of transistor MN.sub.R. An operational amplifier 312 is employed in a feedback configuration to force the voltages on nodes 313 and 314 to be equal. The feedback signal of op-amp 312 is used to control the bias voltage of current sources 308-311. The current in sources 308 and 310 may be mirrored to an output terminal (not shown) in a conventional manner to provide a bias reference current I.sub.ref.
A diode-connected NPN transistor 306 biases transistor MN.sub.R at one V.sub.be below the supply voltage V.sub.cc, thereby forcing transistor MN.sub.R to operate in the triode region. A current source 311 sinks current from transistor 306. A diode-connected reference transistor MN.sub.ref is connected between V.sub.cc and the common base of NPN transistors 302 and 304 to bias the common base of transistors 302 and 304. The current in transistor MN.sub.ref is sunk by current source 309. Transistor MN.sub.ref is scaled to match the physical dimensions of transistor MN.sub.R.
The voltage on node 313 is equal to V.sub.cc minus the base-emitter voltage V.sub.BE of transistor 306 minus the gate-source voltage V.sub.GS of transistor MN.sub.R, i.e., EQU V.sub.313 =V.sub.cc -V.sub.BE(Q306) -V.sub.GS(MN.sbsb.R.sub.)
The voltage on node 314 is equal to V.sub.cc minus the gate-source voltage V.sub.GS of transistor MN.sub.ref minus the base-emitter voltage V.sub.BE of transistor 304, i.e., EQU V.sub.314 =V.sub.cc -V.sub.GS(MN.sbsb.ref.sub.) -V.sub.BE(Q304)
Equating the V.sub.BE 's of transistors Q304 and Q306 and rearranging terms gives EQU V.sub.GS(MN.sbsb.R.sub.) =V.sub.GS(MN.sbsb.ref.sub.)
In this manner, the V.sub.GS of transistor MN.sub.R, and thus the threshold V.sub.T and on-resistance R of transistor MN.sub.R, is set by reference transistor MN.sub.ref. Any process variations in transistor MN.sub.R are "mirrored" in and thus canceled by reference transistor MN.sub.ref, thereby allowing for the resistance R of transistor MN.sub.R to be substantially independent of process variations.
Since the operating points of transistors MN.sub.R and MN.sub.ref are in the linear and saturation regions, respectively, the drain current of transistor MN.sub.R may be expressed as: ##EQU1## where .beta. is substantially a constant. Noting that .DELTA.V.sub.BE is equal to the drain-source voltage V.sub.DS of transistor MN.sub.R, the drain current I.sub.D is substantially independent of the threshold voltage V.sub.T.
It is known that (i) the constant .beta. has a negative temperature coefficient (TC) approximately proportional to T.sup.-3/2, where T is the operating temperature, and (ii) V.sub.DS varies approximately with the operating temperature T. Thus, the current I.sub.D, as a whole, varies approximately with T.sup.1/2 and, thus, achieves a positive TC.
Although circuit 300 advantageously exhibits a positive temperature coefficient and substantially eliminates the dependence of transistor MN.sub.R 's resistance R upon process variations, circuit 300 consumes an undesirably large amount of current when generating small bias reference currents. For example, when configured to provide a reference bias current of 0.2 micro-amps, current sources 308-311 sink approximately 0.2, 0.4, 0.2, and 0.13 micro-amps, respectively, plus the current consumed by op-amp 312 (approximately 0.5 micro-amps). Accordingly, circuit 300 consumes almost 1.5 micro-amps of current to provide a reference bias current of just 0.2 micro-amps. Thus, it is desired to build a reference bias current generating circuit which not only is relatively insensitive to process variations and has a positive temperature coefficient but which also consumes a minimal amount of current.
Further, note that the minimum supply voltage required across circuit 300 is approximately 2.4 volts. That is, the base-emitter drop across transistor Q306 plus the gate-source voltage across transistor MN.sub.R plus the input common voltage required by op-amp 312, which is equal to the sum of a V.sub.BE and a V.sub.Dsat, equals approximately 2.4 volts. Therefore, circuit 300 is not capable of operating with voltage supplies of less than 2.4 volts. Thus, it would also be desirable to form a bias circuit which may be used with smaller supply voltages.

Low power bias circuit using FET as a resistor


A color video signal recorder is arranged to record on one and the same recording medium first and second signals which are obtained by frequency dividing at different phases the frequency modulation wave of a frequency modulated color video signal which includes a luminance signal and a carrier chrominance signal.

1. Field of the Invention
This invention relates to a color video signal recorder and more particularly to an apparatus for recording a wide-band color video signal.
2. Description of the Related Art
Various standards of TV signals of high definition and wide bands have recently been proposed for improvement in reproduced picture quality of the TV signals. For example, there have been proposed a so-called high definition TV signal which is arranged to have a frequency band of about 20 MHz for a luminance signal (hereinafter referred to as a HD-TV signal) and a so-called extended definition TV signal (hereinafter referred to as an ED TV signal) which has a band of about 8 MHz for a luminance signal and is arranged to be interchangeable with the conventional TV signal.
These wide-band TV signals are not recordable nor reproducible with the conventional video tape recorder which is arranged to have a recordable and reproducible band of only about 4 MHz. To solve this problem, there has been proposed various video tape recorders (hereinafter referred to as VTRs) which are arranged to perform recording or reproduction by converting the wide-band TV signal into a multi-channel signal with the band of each channel arranged to be about 4 MHz.
In performing such multi-channel recording, however, the VTR is required to completely eliminate the adverse effect of jitter or the like. This requirement results in a complex reproducing circuit arrangement even if a composite video signal which includes a luminance signal and a carrier chrominance signal is processed into a multi-track signal by a simple band dividing method or the like. Especially, in cases where the video signal is to be divided into a high frequency component and a low frequency component, the time constants of the circuits processing these two components differ from each other. Therefore, it is very difficult to restore the video signal with high fidelity to its original state during a reproducing operation by temporally matching these two components with each other.
Further, in the case of recording a composite video signal by dividing it into R, G and B component signals etc., since each of them is wide-band signal, they must be recorded in a multi-channelled manner. Therefore, the number of channels increases too much for high density recording. Further, a VTR is preferably arranged to be capable of recording an audio signal or a stereo audio signal, if possible, at a high relative speed. However, it has been difficult to accomplish such audio signal recording in accordance with the above stated method.
To solve this problem, there have recently been proposed various methods of recording video and audio signals by digitizing them. However, such a method hardly permits high density recording, because the digitizing arrangement further increases the band of each component signal.


A voltage feedback loop employed with a power distribution switch rapidly responds to a predetermined drop in output voltage to increase the resistance of the switch for a predetermined time. After this predetermined time, a current feedback loop controls the resistance until the output voltage recovers, while also isolating the voltage feedback loop from the switch.

Power distribution switches are used in power management integrated circuits to distribute power to subsystems. In one example, power distribution switches are used to limit the current flowing to an output device. For example, in a computer system a power distribution switch may couple a power source to an output terminal, thereby supplying power to an attached device. Some devices are limited to 0.5 amperes (A) of current for extended periods, but the devices may occasionally draw more current than this limit. If a device overdraws current for too long, the power distribution switch may increase its resistance, thereby reducing the current draw and preventing the device from significantly affecting the voltage level of the power source.
Conventional power distribution switches include analog feedback loops to monitor the input to the power distribution switch for excessive current draw by a device drawing power from the output. In an example, a sense resistor is placed in series with the current supply to generate a sense voltage that is compared to a desired reference voltage at an amplifier. In such arrangements, the output of the amplifier controls the power distribution switch coupling the power source to the output terminal, and increases the resistance of the switch if the sense voltage indicates that too much current is being drawn. However, in the case of a hard short circuit condition (e.g., a condition in which the resistance between an output terminal of the power distribution switch and ground drops to roughly 0.1 ohms), large currents may flow through the power distribution switch before the feedback loop can respond to increase resistance of the power distribution switch. This condition may be damaging to the power distribution switch, or may lead to a situation in which the power source voltage is pulled below tolerable levels.
One conventional approach, described in U.S. Pat. No. 7,817,393 (incorporated by reference herein in its entirety), addresses the undesired slow response to hard short by adding a digital voltage feedback loop that responds to the hard short more rapidly than the analog feedback loop. In response to detection of a hard short, the digital loop disables, and/or increases the resistance of, one or more conduction paths in the power distribution switch, thereby increasing its series resistance. For example, if the current limit of the switch is set to 1 A, the digital loop may rapidly disable ⅘ of the conduction paths, thereby limiting the current to 200 mA. This condition persists until the output terminal voltage recovers from the hard short. However, in some situations, the load device attached to the output terminal may require full current (e.g., significantly more than 200 mA) for start up, such that the output terminal voltage cannot recover while the 200 mA current limit condition persists.
It is desirable in view of the foregoing to provide for rapid current limit protection against shorts without requiring the output terminal voltage to recover before the current limit condition can be removed.

Power management apparatus with rapid short response and full load recovery


A method and an apparatus are provided for determining whether an enhanced physical downlink control channel (ePDCCH) transmission exists for a user equipment (UE) in a subframe. The UE receives a transmission on physical downlink control channel (PDCCH) resources of the subframe. Downlink control information (DCI) is extracted from the PDCCH resources. The DCI includes at least one bit indicating whether the ePDCCH transmission exists for the UE in the subframe. The UE determines whether the ePDCCH transmission exists using the at least one bit. Additional symbols of the subframe are buffered and decoded when the ePDCCH transmission exists.

1. Field of the Invention
The present invention relates generally to enhanced physical downlink control channel (ePDCCH) transmission, and more particularly, to a method and an apparatus for providing advanced notification of ePDCCH transmission for a user equipment (UE).
2. Description of the Related Art
In the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) standard, a physical downlink shared channel (PDSCH) carries all user data signaling messages and a physical downlink control channel (PDCCH) carries layer one downlink control information (DCI). PDCCH is transmitted in a downlink control region and is allocated within a number of orthogonal frequency division multiplexing (OFDM) symbols at the beginning of each subframe. This allocation allows a UE to decode the PDCCH first and determine its potential assignments early, without having to read and buffer the entire subframe. Therefore, the UE can ignore the remaining portions of the subframe when the UE determines that no downlink assignment exists for that UE in the PDSCH region of the subframe. This mechanism has the potential to save power and extend battery life of the UE.
In order to increase the capacity of control channels to accommodate more complicated features, the concept of ePDCCH has been introduced. FIG. 1 is a diagram illustrating the incorporation of ePDCCH into a subframe. Specifically, ePDCCH regions 102 are disposed between PDSCH regions 104 in frequency, and after a PDCCH region 106 in time, within the subframe. As illustrated in FIG. 1, the ePDCCH regions 102 have a time range that begins after the PDCCH region 106 and lasts until the end of the subframe. Thus, if an ePDCCH transmission to the UE is allowed on the subframe, the UE is required to buffer the entire subframe, and then attempt to decode an ePDCCH transmission targeted to the UE. If the UE successfully decodes DCI in the PDCCH that corresponds to a downlink assignment for the UE, the UE also attempts to the decode the corresponding PDSCH transmission.
The battery life of the UE is negatively affected when the receiver of the UE remains active for an entire subframe and when the UE reads and buffers the entire subframe for all subframes on which an ePDCCH transmission for the UE is allowed.

Method and apparatus for providing advanced indication for ePDCCH


An exemplary method includes delivering stimulation according to one or more stimulation parameters to cause contraction of the diaphragm, monitoring chest activity related to respiration and, in response to the monitoring, adjusting one or more of the one or more stimulation parameters during contraction of the diaphragm and continuing the delivering. Various other exemplary methods, devices, systems, etc., are also disclosed.

Intrinsic respiration depends on occurrence of many events during a respiratory cycle. Replication of all of these events by an in vivo device is impractical. Indeed, conventional methods for artificial activation of the diaphragm typically rely on a fixed set of parameters that is known to stimulate the phrenic nerve and cause abrupt inspiration. As such these attempts at in vivo activation of the diaphragm to achieve or augment respiration have met with limited success in their ability to mimic intrinsic respiration. Consequently, a need exists for techniques that can more closely mimic intrinsic respiration or achieve more desirable respiration. Various methods, devices, systems, etc., disclosed herein aim to address this need and/or other needs.

Multi-variable feedback control of stimulation for inspiratory facilitation


The invention relates to a method to manufacture a shaft (22) as well as a device containing such a shaft (22), in particular an armature shaft (22) of an electromotive drive (10), which is held by at least one shaft mounting, whereby a curved, rounded stopping tip (40) that can support itself on an axial stopping face (32, 34) is formed at least one fore part (28, 30) of the shaft (22) by means of material displacement.

The invention relates to a method to manufacture a shaft with rounded stopping tips as well as a device containing such a shaft, as well as a device to manufacture such a shaft in accordance with the species of the independent claims.
With WO 01/65 668, a device has become known that is used, for example, to move window panes, sun roofs or seats. In order to avoid undesired longitudinal play in the armature shaft, it is proposed there that a damping rubber piece be pressed into a recess of the housing on at least one of the fore parts. The armature shaft features a rounded stopping tip on one of its fore parts, which is supported against a stop disk, which is pressed in turn against the damping rubber piece.
This type of rounded stopping tip is normally manufactured by means of turning on a lathe or grinding in a machining process on the fore part of the armature shaft before installation of the electric motor. Afterwards, the rounded stopping tip is polished in order to achieve a high surface quality and then hardened so that the rounded stopping tip does not get damaged when the electric motor is assembled. This method is very labor intensive and expensive.

Method for producing a shaft comprising stop caps device containing one such shaft


A digital-to-analog converter with cascaded coarse and fine resistor divider strings. The fine resistor string contains 2.sup.N or more resistor segments controlled by N number of fine divider control bits. Resistors located at each end of the fine divider string are a fraction of the nominal value for the remaining fine divider resistor segments. The on-resistance of switches coupling the coarse and fine resistor divider strings is less than or equal to a predetermined fraction of the nominal value for the fine divider resistor segments to minimize contributions to linearity error. The DAC uses all CMOS devices including NMOS and PMOS switches which utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. The DAC provides linearity of about one-fourth LSB.

Prior art potentiometric digital-to-analog converters (DAC) utilize two cascaded resistor divider strings, as shown in FIG. 1. A course resistor divider is connected between ground and a reference voltage and provides 2.sup.M equal resistor segments where M represents the number of course divider bits used to select where to tap a voltage along the course resistor divider. A fine resistor divider is connected through a set of coarse divider switches across one of the coarse divider segments selected by the M coarse divider bits. The fine resistor divider has equally valued segments and subdivides the resistance of the selected coarse divider segment to provide an analog voltage output. Typically, the fine resistor divider is controlled by N fine divider bits, and the resolution of the DAC is M+N bits.
A major problem with the prior art DAC is a linearity error caused by the switches which couple the fine and coarse resistor dividers. Typically, the coupling switches are NMOS transistors, as are known in the art, which carry current which produces a voltage drop across the switch introducing the linearity error. As the error approaches the voltage step defined by the least significant bit (LSB), the DAC will produce an incorrect voltage output. The prior art proposes to mitigate the linearity error of the switches by using a fine divider which consists of only 2.sup.N -1 resistors and attempting to match the on-resistance of the coupling switches to a fraction of the resistance of a fine divider segment. In this way, the error introduced by the coupling switches should be less than the resolution defined by a fine resistor divider segment. However, the attempt to match resistance is extremely poor due to process and temperature variations. Therefore, differential non-linearity degrades significantly in the prior art DAC.
Another major problem with the prior art DAC is that the attempts to match the resistances of the coupling switch and divider segment require the reference voltage to be less than half of the supply voltage. Generally, this requires the addition of an amplifier to approximately double the output voltage to restore its voltage range. However, as a result, the integral linearity and noise immunity performance of the prior art DAC is degraded by about one-half.
There is a need for a precision high-resolution DAC that has a linearity better than a resolution of 1/2 LSB. There is also a need for a DAC that can utilize approximately the full rail-to-rail voltage of the voltage source without the use of additional amplifiers. In addition, it would be an advantage to provide a DAC with a minimal number of switches so as to reduce size and cost. Another improvement, would be to provide a DAC utilizing all CMOS devices and including NMOS and PMOS switches while minimizing the linearity error contribution by the on-resistance of the switches.

Segmented DAC using PMOS and NMOS switches for improved span


A power generator or sensor apparatus is provided. In another aspect, a power generator is used for water wave energy harvesting. A further aspect provides a power generator including a buoyant, waterproof and/or enclosed outer shell, at least one enclosed inner shell located within the outer shell, a first plurality of balls located between the outer and inner shells, a second plurality of balls located within the inner shell, and spaced apart electrodes affixed to an interior surface of the outer shell. Moreover, an aspect of the present power generator uses fluid, such as water wave movement and wind blowing, to cause nested shells to move which moves multiple balls therein between spaced apart electrodes to generate triboelectric charges or energy for a variety of applications.

The present disclosure generally pertains to power generators or sensors, and more particularly to a power generator or sensor apparatus for water wave energy harvesting.
Ocean wave energy has many promising advantages like high power density, wide distribution and independence of time of day, weather or seasons. It is estimated that the global power by waves breaking around the coastlines worldwide is around 2-3 TW. However, developing effective energy harvesting devices that can reliably extract that energy and withstand the ocean environment is challenging, and up to now there is still a lack of cost-effective energy harvesting technologies to exploit this renewable energy resource.
Over the years, different kinds of energy harvesters have been attempted to capture the energy from ocean tides or ocean waves based on electro-magnetic generators ("EMGs"). These conventional devices, however, exhibit low energy harvesting efficiency at low ocean wave frequencies and have the drawbacks of complex design, high cost and corrosion in seawater. Therefore, the development of a new kind of low-cost, robust and highly efficient wave energy harvester is desirable for harvesting energy especially from low-frequency water waves.
More recently, triboelectric nanogenerators ("TENGs") have been experimented with for converting mechanical energy into electricity based on the coupled effect of triboelectrification and electrostatic induction. Compared with traditional EMGs, TENGs are advantageous for ocean wave energy harvesting due to their superior efficiency in capturing low-frequency (<3 Hz) wave energy as well as low-cost and simplicity in installation of the devices. Examples of experimental TENGs can be found in: J. Nie et al., "Electrically Responsive Materials and Devices Directly Driven by the High Voltage of Triboelectric Nanogenerators," Adv. Funct. Mater. (2018) at 1806351; C. Wu et al, "Triboelectric Nanogenerator: A Foundation of the Energy for the New Era," Adv. Energy Mater. (2018) at 1802906; T. Jiang et al., "Structural Optimization of Triboelectric Nanogenerator for Harvesting Water Wave Energy," ACS Nano (2015); U.S. Pat. No. 9,571,009 entitled "Rotating Cylindrical and Spherical Triboelectric Generators" which issued to Wang et al., on Feb. 14, 2017; and U.S. Pat. No. 9,394,875 entitled "System For Harvesting Water Wave Energy" which issued to Wang et al. on Jul. 19, 2016. The prior patents are incorporated by reference herein. However, these conventional TENG experiments typically utilize a single large ball moving within a single structure, resulting in a low energy harvesting efficiency and wastage of the limited volume space in the device.
In accordance with the present invention, a power generator or sensor apparatus is provided. In another aspect, a power generator is used for water wave energy harvesting. A further aspect provides a power generator including a buoyant, waterproof and/or enclosed outer shell, at least one enclosed inner shell located within the outer shell, a first plurality of balls located between the outer and inner shells, a second plurality of balls located within the inner shell, and spaced apart electrodes affixed to an interior surface of the outer shell. Moreover, an aspect of the present power generator uses fluid, such as water wave movement, to cause nested shells to move which moves multiple balls therein between spaced apart electrodes to generate triboelectric charging or energy. Methods of manufacturing and using nested shells with multiple freely movable balls therein, are also provided.
The present apparatus is advantageous over conventional devices since the present apparatus more efficiently generates electrical charges or energy, especially at low-frequency wave motions. Furthermore, the present apparatus advantageously maximizes energy generation within a small packaging area by nesting multiple sets of electrodes and/or using multiple balls which can freely rotate between a pair of the electrodes. Moreover, it is also envisioned that the present apparatus is more cost effective to manufacture and has a lighter weight as compared to various traditional devices. Additional features and advantageous of the present apparatus will become apparent from the following description and appended claims taken in conjunction with the associated drawings.

Power generator, wave energy converter or sensor apparatus for water wave energy harvesting

Board of Trustees of Michigan State University


An electron beam lithography system which generates phase shift pattern data relating to main patterns, and exposes the phase shift pattern on a mask plate by using an electron beam in accordance with instruction from a computer. An electron beam lithography system is provided which can remarkably decrease a time needed for preparing phase shift pattern data. The apparatus is furnished with a parameter table for storing equations to generate phase shift pattern data, and generates the phase shift pattern data by assigning original pattern data into equations in accordance with a corresponding instruction for applying a phase shift method, and automatically exposes the phase shift pattern.

The present invention relates to an electron beam lithography system, and especially, to an apparatus preferable for exposing LSI (Large Scale Integrated Circuit) patterns.
Methods for exposing LSI patterns and phase shift patterns on a target mask plate by a phase shift method exist in the art. Patterns exposed by the phase shift method are, for example, a part of the wiring layers, VIA holes, and contact holes which are especially wanted to be more precisely exposed than other patterns in whole LSI layers, and the phase shift patterns are respectively arranged around the above described partial patterns. Accordingly, in order to make the following explanation clear, such a square or a rectangular pattern as the contact hole is taken as an example pattern which is exposed by the phase shift method, and is called a main pattern or an original pattern in contrast with the phase shift pattern. The following explanation can be naturally applicable to other patterns.
The LSI pattern data are put into the electron beam lithography system after being converted in format by the data converter, and are exposed on the mask plate. During the above described process, the original pattern is exposed at a designated position.
Next, phase shift pattern data which is converted in format by the data converter is transferred to the electron beam lithography system, and the phase shift patterns are exposed around the original pattern.
In the phase shift method, the original pattern is exposed precisely by interference of light passing through the phase shift patterns with light passing through the original pattern when a chip region of a LSI wafer is exposed using the mask plate.
Accordingly, in order to cause the above described interference of light certainly at a designated portion, the position and the shape of the respective phase shift patterns are precisely and definitely defined depending on shape of the corresponding original pattern.
But, in such a conventional technique as above described, there was a problem in that a long time was needed because the pattern design, format conversion by the data converter, and exposure by the electron beam lithography system were independently repeated to both the original pattern and the phase shift pattern. For example, in a case of 0.3 .mu.m rule devices, about ten hours were required only for a format conversion of the phase shift pattern, and consequently, throughput was remarkably lowered.


A method for checking the integrity of GPS measurements for a moving vehicle includes determining a first inter-vehicle distance between a first vehicle and a second vehicle based on GPS measurements obtained at both vehicles, independently determining a second inter-vehicle distance based on relative motion of the first vehicle and the second vehicle obtained using INS sensors at both vehicles, and comparing the first and second inter-vehicle distances. The integrity of the GPS measurements are checked if the first and second inter-vehicle distances are nearly equivalent. Methods for error detection and for mapping GPS multipath levels at each point in a vicinity for an entire range of satellite constellations are also described.

Generally, most systematic sources of error in differential GPS (DGPS), such as clock error, can be canceled or corrected to a large degree using conventional techniques. However, two sources of error which currently cannot be readily canceled or corrected are receiver error, and errors caused by multipath interference. Receiver errors typically arise from a malfunction in a component of a receiver tuned to a particular GPS satellite and have little correlation with the position of the receiver. In contrast, multipath interference, i.e., the interference caused by arrival of a signal from a single source at a receiver at slightly different times due to different path lengths, depends directly on the geometry of reflecting surfaces in the vicinity of the receiver in question.
More precisely, multipath interference depends on the positions of the receiving antenna, the reflecting object(s) and the satellite geometry. Therefore, there are three distinct ways that multipath interference changes over time. Satellite movements change the line-of-sight vector (between the receiver and the satellite) in a slow, smooth and predictable manner. The resulting multipath changes correlated with such satellite movements reflect this, in that they are low frequency, slowly changing and "smooth". Reflectors can be divided into two classes: moving (such as nearby vehicles) and fixed (such as the ground and nearby buildings). Multipath interference from moving objects tends to be high frequency in nature, and weakly correlated to antenna position, whereas multipath interference caused by fixed objects is highly correlated to antenna (and satellite) position. In addition, when the antenna is on a mobile vehicle, its own movements can vary widely in terms of speed and direction. Owing to the variability of these conditions over even short lengths, there is usually little correlation of multipath-errors for baselines longer than a few meters.
Multipath interference therefore severely limits the achievable accuracy of DGPS. In urban areas having a high density of buildings (potential reflectors), the accuracy of DGPS can easily degrade from about 1–2 m under multipath-free conditions to up to tens of meters. This renders DGPS unsuitable for applications that demand high accuracy and integrity, and in particular, forbids the use of DGPS for safety relevant applications.

Method for improving GPS integrity and detecting multipath interference using inertial navigation sensors and a network of mobile receivers


A forming method of the present invention includes forming a first patterned conductive layer, which includes a transparent conductive layer and a metal layer stacked together on a substrate, where the first patterned conductive layer functions as gate lines, gate electrodes, common lines and predetermined transparent pixel electrode structures; and forming a second patterned conductive layer on the substrate. The second patterned conductive layer includes data lines and reflective pixel electrodes, and be directly connected to doping regions, such as source regions/drain regions. According to the forming method of the present invention, pixel structures of a transflective liquid crystal display device can be formed through five mask processes. Therefore, the manufacturing process of the transflective liquid crystal display device is effectively simplified, so the product yield is improved and the cost can be reduced.

1. Field of the Invention
The present invention relates to a method for forming a pixel structure, and more particularly, to a method for forming a pixel structure of a transflective liquid crystal display (LCD) device.
2. Description of the Prior Art
Most liquid crystal displays (LCDs) can be categorized into a transmissive type, a reflective type, and a transflective type. The transmissive LCD uses backlight as a source for emitting light. The light emitted by the backlight will pass through the LCD panel to let an observer see the image displayed on the LCD panel. The reflective LCD has a reflective electrode, such as an aluminum electrode. When displaying the image, the ambient light of the reflective LCD will enter the LCD from the observer side of the LCD and then be reflected by the reflective electrode. The reflected light will pass through the surface of the LCD panel again, and finally the observer can see the image displayed on the LCD. The transflective LCD has the characteristic of both transmissive type and reflective type. In other words, each sub-pixel region of the LCD panel comprises a transmission region and a reflection region, where the transmission region uses a backlight as a light source, and the reflection region uses an ambient light as a light source.
Please refer to FIG. 1, which is a schematic diagram of a traditional transflective LCD panel. As shown in FIG. 1, a traditional transflective LCD panel 10 includes an array substrate 20, a color filter substrate 30, and a liquid crystal layer 40 disposed between the array substrate 20 and the color filter substrate 30. The array substrate 20 includes a plurality of pixel regions 22, and each of the pixel regions 22 includes a reflection region 27 and a transmission region 28. For clarity, only one pixel region 22 for example is shown in FIG. 1. The array substrate 20 includes a plurality of thin-film transistors 23 disposed in the reflection regions 27, a plurality of reflective electrodes 24 disposed on the thin-film transistors 23, a dielectric layer 26 disposed between the thin-film transistors 23 and the reflective electrodes 24, and a plurality of transparent pixel electrodes 25 disposed in the transmission regions 28. Both the reflective electrodes 24 and the transparent pixel electrodes 25 are electrically connected to the thin-film transistors 23, so the thin-film transistors 23 can control and drive the pixel electrodes. On other hand, the color filter substrate 30 includes a plurality of color filters 32 disposed corresponding to the pixel regions 22, and a black matrix 34 disposed around the pixel regions 22.
According to processes of forming the traditional transflective LCD device, the traditional method usually takes eight or nine photo mask to define patterns of the elements so as to form a pixel structure of a transflective LCD device. However, every photo mask process for defining patterns should include a plurality of steps, such as deposing, cleaning, lithography, etching, checking, etc, so the processes of forming the traditional transflective LCD device are too complicated. Due to the traditional processes, the output quantity of the LCD devices is quite limited, and it is hard to decrease the cost of forming the traditional transflective LCD device.

Method for forming pixel structure of transflective liquid crystal display


A printed circuit board having interstitial vias. The printed circuit board has a plurality of overlying electrical conductors disposed within an inner region of the printed circuit board. The overlying electrical conductors are separated by dielectric material. The printed circuit board has an aperture passing through a portion of the plurality of overlying electrical conductors printed circuit board. The overlying electrical conductors have ends with recesses therein. An electrical conductive via passes through the aperture with distal portions of the via projecting into the recesses.

As is known in the art, it is frequently required to make electrical contact from the upper surface of a multi-level printed circuit board to underlying electrical conductors within the board such as shown in FIG. 1A. Such connections are typically made by drilling a hole from the upper surface into the printed circuit board with such hole cutting through the desired underlying as shown in FIG. 1B. The walls of the hole are, after cleaning, coated with an electrically conductive material thereby forming an interstitial via, as shown in FIG. 1C.
Military products have often been processed with extreme positive or negative etch back features. The positive feature is produced by removing resin from the hole wall until the inner-layer copper foil (i.e., the underlying electrical conductor) protrudes as a tongue into the hole. Electro-less and anodic copper is then plated to the resin barrel on the via and also over-plates the protruding (so called positive) tongue. Negative etch back is produced by etching inner-layer copper foil away from the hole wall so that the edges of the foil are recessed inwardly from the walls of the drilled hole as shown in FIG. 2A. The electroless and anodic copper then penetrate the circumferential etch recess or groove, associated with each inner-layer foil plane, thus making a recessed interconnect as shown in FIG. 2B. Military standards also require rectangular interface structures with minimal copper wedge at the plane to via barrel transition. Positive and Negative Etch Back features are not typically found in commercial products. This is due to the yield and cost burden associated with the additional process requirements.

Multi-level printed circuit board interstitial vias


A plasma display panel for improving brightness and as reducing power consumption is disclosed. In the plasma display panel, transparent electrodes make a pair at each of discharge cells. Protruded transparent electrodes are protruded from the respective transparent electrodes with a structure in which a square shape is connected to a trapezoidal shape. Connectors connects the protruded transparent electrodes arranged at adjacent discharge cells to each other to be stepped from one end of the protruded transparent electrode positioned at the middle portion of the discharge cell.

1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a plasma display panel that is adaptive for improving brightness as well as reducing power consumption.
2. Description of the Related Art
Recently, a plasma display panel (PDP) feasible to a manufacturing of a large-dimension panel has been highlighted as a flat panel display device. The PDP usually controls a discharge period of each pixel in accordance with a digital video data to thereby display a picture. The PDP typically includes a three-electrode, alternating current (AC) type PDP that has three electrodes and is driven with an AC voltage as shown in. FIG. 1.
FIG. 1 is a perspective view showing a structure of each cell arranged in a matrix type en a conventional AC type PDP, and FIG. 2 is a plan view showing the sustain electrode pair shown in FIG. 1.
Referring to FIG. 1 and FIG. 2, the conventional PDP includes an upper plate provided with a sustain electrode pair 14 and 16, an upper dielectric layer 18 and a protective film 20 that are sequentially formed on an upper substrate 10, and a lower plate provided with an address electrode 22, a lower dielectric layer 24, barrier ribs 26 and a phosphorous material layer 28 that are sequentially formed on a lower substrate 12. The upper substrate 10 and the lower substrate 12 are spaced in parallel by the barrier ribs 26.
Each of the sustain electrode pair 14 and 16 is comprised of stripe-shaped transparent electrode 14A and 16A having a relatively large width and made from a transparent electrode material (e.g., ITO) to transmit a visible light, and metal electrodes 14B and 16B having a relatively small width to compensate for a resistance component of the transparent electrodes 14A and 16A. In this case, the transparent electrodes 14A and 16A of the sustain electrode pairs 14 and 16 are opposed to each other with having a gap of approximately 60 μm to 80 μm therebetween. The scan electrode 14 is mainly supplied with a scanning signal for a panel scanning and a sustaining signal for a discharge sustaining, whereas the sustain electrode 16 is mainly supplied with a sustaining signal. Electric charges are accumulated in the upper and lower dielectric layers 18 and 24. The protective film 20 prevents a damage of the upper dielectric layer 18 caused by the sputtering to thereby prolong a life of the PDP as well as to improve the emission efficiency of secondary electrons. This protective film 20 is usually made from magnesium oxide (MgO). The address electrode 22 crosses the sustain electrode pair 14 and 16. This address electrode 22 is supplied with an address signal for selecting cells to be displayed. The carrier ribs 26 are formed in parallel to the address electrode 22 to thereby prevent an ultraviolet ray generated the discharge from being leaked into adjacent cells. The phosphorous material layer 28 is coated on the surfaces of the lower dielectric layer 24 and the barrier ribs 26 to generate any one of red, green and blue visible lights. A discharge space is filled with an inactive gas for a gas discharge.
The cell of the PDP having the structure as mentioned above is selected by an opposite discharge between the address electrode 22 and the scan electrode 14, and thereafter sustains the discharge by a surface discharge between the sustain electrode pair 14 and 16. In the PDP cell, the phosphorous material 28 is radiated by an ultraviolet ray generated upon sustain discharge to thereby emit a visible light into the exterior of the cell. In this case, the PDP controls a discharge sustain period, that is, a sustain discharge frequency of the cell in accordance with a video data to thereby implement a gray scale required for an image display.
Such an AC surface-discharge PDP is driven with being divided into a plurality of sub-fields, so as to realize gray levels of a picture. A light-emission having a frequency proportional to a weighting value of a video data is made in each sub-field period to thereby express a gray level. For instance, if it is intended to display a picture of 256 gray levels using an 8-bit video data one frame display interval (i.e., 1/60 second=about 16.7 msec) at each discharge cell 11 is divided into 8 sub-fields SF1 to SF8. Each of the 8 sub-fields SF1 to SF8 again is divided into a reset period, an address period and a sustain period, and the sustain period is given bad a weighting value at a ratio of 1:2:4:8, . . . , :128. Herein, the reset period is a period for initializing the discharge cell; the address period is a period for generating a selective address discharge in accordance with a logical value of a video data; and the sustain period is a period for sustaining a discharge at the discharge cell having generated the address discharge. The reset period and the address period are identically assigned in each sub-field interval.
If electrode widths of the scan electrode 14 and the sustain electrode 16 are defined narrowly in order to reduce power consumption of such a PDP, then a discharge path upon discharge is shortened to thereby limit a light-emission area. Thus, an emission amount of an ultraviolet ray is reduced and hence brightness is deteriorated. On the other hand, if electrode widths of the scan electrode 14 and the sustain electrode 16 are defined widely in order to enhance brightness of the PDP, then a capacitance value rises to increase a discharge current and power consumption.
Furthermore, the conventional PDP is made into a larger dimension screen than other flat panel display (FPD) devices having 40, 50 and 60 inches, etc. Accordingly, in the conventional PDP, a voltage drop caused by an electrode length has a relatively large difference between the middle portion and the peripheral portion of the PDP. Also, since a discharge gas is injected into the interior of the PDP at a lower pressure than the atmospheric pressure, a force applied to the substrates 11 and 16 at the middle portion where the upper/lower substrates 10 and 12 are supported only by the barrier ribs 26 becomes different from that at the peripheral portion where the upper/lower substrates 10 and 12 are joined with each other by a sealant (not shown). As a result, although the conventional PDP has somewhat difference depending upon a size of the panel, it has a brightness difference between the middle portion and the peripheral portion thereof in each of the horizontal direction and the vertical direction to thereby cause a non-display area at which any discharge does not occur.

Plasma display panel provided with pairs of trapezoidal shaped transparent electrodes


A method of and apparatus for beam steering. A feed horn is arranged so that the feed horn illuminates a tunable impedance surface comprising a plurality of individually tunable resonator cells, each resonator element having a reactance tunable by a tuning element associated therewith. The tuning elements associated with the tunable impedance surface are adjusted so that the resonances of the individually tunable resonator cells are varied in a sequence and the resonances of the individually tunable resonator cells are set to values which improve transmission of information via the tunable impedance surface and the feed horn.

The prior art includes the following:                (1) The tunable impedance surface, invented at HRL Laboratories of Malibu, Calif. See, for example, the following U.S. Pat. Nos.: 6,483,480; Sievenpiper, and Sievenpiper, U.S. Pat. No. 6,538,621. The tunable impedance surface is described in various incarnations, including electrically and mechanically tunable versions. However, the tuning technology disclosed herein is different in that relates to a tuning method that allows for the independent control of the phase preferably at each element of the tunable impedance surface.        (2) Phased array antennas. These are described in numerous patents and publications, and references. See, for example, U.S. patents by Tang, U.S. Pat. No. 4,045,800; Fletcher, U.S. Pat. No. 4,119,972; Jacomini, U.S. Pat. No. 4,217,587; Steudel, U.S. Pat. No. 4,124,852; and Hines, U.S. Pat. No. 4,123,759. Phased array antennas are typically built as arrays of independent receiving elements, each with a phase shifter. Signals are collected from each element and combined with the appropriate phase to form a beam or null in the desired direction. The disadvantage of the phased array compared to the present technology is that it is prohibitively expensive for many applications.        (3) Adaptive antennas. These are also described in numerous patents and publications, and references. See, for example, U.S. Patents by Daniel, U.S. Pat. No. 4,236,158; Marchand, U.S. Pat. No. 4,220,954; McGuffin, U.S. Pat. No. 4,127,586; Malm, 4,189,733; and Bakhru, U.S. Pat. No. 4,173,759. Adaptive antennas include analog or digital signal processing techniques that are used for angle of arrival estimation, adaptive beam forming, adaptive null forming, including the ability to track multiple sources or jammers. The disadvantage of traditional adaptive antenna methods compared to the present disclosure is the required complexity. Many of the same functions that are used in traditional adaptive antennas are handled by the presently disclosed technology using much simpler techniques.        (4) The prior art also includes the ESPAR antenna system developed by Ohria, U.S. Pat. No. 6,407,719. This antenna involves a series of passive antenna elements and a single driven antenna element. The resonance frequencies of the passive antenna elements are adjusted to vary the coupling coefficients among them, and to steer a beam or a null. The presently disclosed technology is related to this antenna in that it preferably uses passive, non-driven resonators as the beam forming apparatus. However, the presently disclosed antenna technology allows much higher gain because it allows the radiation striking a large area to be directed to a single feed, rather than relying exclusively on mutual coupling among the elements.
The technology disclosed herein improves upon the existing state of the art in that it provides a lower cost alternative to traditional phased arrays, while retaining the same functionality, including the ability to adaptively modify the phase profile by measuring a small number of parameters. Phased arrays are typically expensive, often costing hundreds of thousands or millions of dollars per square meter for an array operating at several GHz. The technology disclosed herein utilizes a tunable impedance surfaces, a concept that has been described in the U.S. Patents referred to above, but the presently disclosed technology provides the ability to adaptively modify the reflection phase to optimize a variety of parameters. If the number of measured variables is limited, then this method further reduces the cost compared to conventional techniques. Calculations that ordinarily require complex digital signal processing are handled naturally by the adaptive array without difficult data processing requirements.
The technology disclosed herein can be used in a variety of applications. For example, it can be used for a low-cost communication system. It can also be used for a low-cost in-flight Internet system on aircraft, where data would be directed to passengers or users in various parts of an aircraft. Since the technology disclosed herein is blind to the incoming phase profile, it is able to partially mitigate multipath problems. It can also be used as a low-cost beamforming technique for information kiosk applications or for 3G wireless networking, in order to provide much greater performance in a vehicle, for example, than is possible with handsets.
An advantage of the present technology compared to a conventional phased array, besides the fact that this technology is comparatively inexpensive to implement, is that conventional phased arrays typically involve explicit control of the phase of a lattice of antennas, while in the antenna systems disclosed herein, the phase at each point on the surface is an intermediate state that exists, but has no direct bearing on the control of the array. In other words, the user does not need to calibrate the array to know its phase, because the antenna can be steered using the method disclosed herein without explicit knowledge of the phase. Conventional phased arrays, on the other hand, typically require explicit knowledge of the phase at each point in the array.

Adaptive beam forming antenna system using a tunable impedance surface


A lock includes a body, a wheel, an outside spindle, and a locking plug. The outside spindle includes a front end having an extension not in contact with a circumferential wall defining a through-hole of the wheel. When the locking plug is in an unblocking position allowing retraction operation of a latch bolt, the front end of the outside spindle is engaged with the wheel to allow joint rotation of the outside spindle and the wheel. When the locking plug is moved from the unblocking position to the blocking position not allowing retraction operation of the latch bolt, movement of a push member pushes the front end of the outside spindle away from the through-hole of the wheel such that the front end of the outside spindle is disengaged from the circumferential wall of the through-hole of the wheel, thereby disengaging the outside spindle from the wheel.

1. Field of the Invention
The present invention relates to a lock. More particularly, the present invention relates to a lock with a clutch function, allowing free rotation of the outer handle when the lock is in a locked state.
2. Description of the Related Art
U.S. Pat. No. 4,583,382 to Hull discloses a door lock with an outside handle that cannot be turned when in a locked state. However, the internal parts of the door lock could be damaged if the outside handle is frequently depressed when the user is not aware of the locking state of the lock. Also, the internal parts of the door lock could be damaged if overtorque is applied to the outside handle.
U.S. Pat. No. 6,993,946 to Shen discloses a lock that allows free rotation of the outside handle when the lock is in a locked state. However, assembly of the lock is troublesome.