A battery module is disclosed having a plurality of battery cells and internal relay controllably coupled to an internal module controller, said controller having a plurality of programmed states. Transitions between programmed states are disclosed responsive to a secure command message, and responsive to a monitored operating condition. Passive and active states are disclosed. A modular battery pack is disclosed consisting of a plurality of modules connected in parallel, which can be individually and independently activated and deactivated responsive to a secure command message. Methods are provided for authentication of command messages and for authentication of the command message source.

A vehicle battery module typically has significant monetary value associated with it, often ranging in the hundreds or thousands of dollars.
Battery modules commonly known in the art are constructed to be permanently installed in a sealed battery pack that is not easily accessed or serviced. Due to this fact, there is no need seen to additionally secure, track, or deter theft of such modules. The difficulty of physically accessing and removing the modules known in the art is commonly considered sufficient deterrent to theft.
In the referenced co-pending application, the applicant discloses novel apparatus and methods for battery packs comprising a plurality of removable high voltage modules that are individually enabled and disabled.
Due to the ease of module removal and the ability to use same module in different packs which is inherent in the novel removable high voltage modules taught by the applicant, the need arises to track, control the use of, and deter theft of the modules.
Additionally, with battery packs configured to accept new or replacement removable modules, it is desirable to ensure that any newly installed modules are compatible with the specific pack and the apparatus powered by the pack, and are safe to enable for operation.
What is needed in the arts of vehicle batteries is a removable battery module design, and methods of operation of same, that facilitate control over the use of the modules, deter unauthorized or incompatible use, and facilitate both tracking of the modules in ordinary use and assist the recovery of any modules that are stolen.

Apparatus and methods for removable battery module with internal relay and internal controller


A zoom lens system for use in a camera having a color filter and a CCD achieves a magnification ratio of about 2.9 or greater and a back focus of about 9.2 or greater. The zoom lens system includes in order from an object side of the lens system, a first lens group having a negative refracting power, a second lens group spaced from the first lens group and having a positive refracting power and a third lens group spaced from the second lens group and having a positive refracting power. One or both of the fifth and an eighth lens surface has an aspherical surface, the fifth and eighth lens surfaces being counted from the object side. The second lens group includes five lenses with an extra lens being located at a far end of the second lens group relative to the object side. Each of the first, second and third lens groups is movable from a first position when the lens system is in a wide position to a second position when the lens system is in a tele position.

1. Field of the Invention
The present invention relates to an improved zoom lens system for use as a zoom lens in a video camera recorder, a digital still video camera or the like. More particularly, the present invention relates to a compact zoom lens system for varying a focal length and providing improved magnification and back focus.
2. Description of Related Art
In conventional zoom lens systems, most wide angle zoom lenses use a "two-lens group" system which are typically provided in single lens reflex film cameras which do not use a color filter or Charge Coupled Device (CCD) as is used in a video camera recorder or a digital still video camera.
A typical lens system for use in a conventional film camera and not adapted for use in a camera having a color filter or CCD is described in Japanese Koukoku Patent No. 3-20735. The zoom lens system of this prior art reference differs from the conventional two lens-group system by inserting a lens unit having positive refractive power at a space located between a first lens group having a negative refractive power and a second lens group having a positive refractive power, described from the object side, so as to provide three "lens groups." The lens system of this reference also provides desired spacing between the first lens group and the lens unit and between the second lens group and the lens unit to provide for more effective compensation of distortion, to miniaturize the lens system and to decrease a minimum object distance during focus adjustment. This zoom lens system performs zooming by displacing the first and second lens groups and the one lens unit independently while maintaining the position of the image surface constant.
With such a device, it is not required or desirable to have an image surface located or moved far from an exit pupil but instead, the image surface is preferably located close to the exit pupil. Further, the lens unit or third lens group is located between the first and second lens groups.
As is mentioned above, the zoom lens system of JP 3-20735 is not adapted for use with a color filter or CCD as is required in a video camera recorder or a digital still video camera. Designing a zoom lens system for use with a color filter and CCD presents special problems. In a typical device, a lens is spaced from a color filter, such as an infrared cut filter which may include low-pass filters disposed on either side of the infrared cut filter, and the color filter is spaced away from a CCD. The lens, the color filter and the CCD are aligned along an axis.
As is well known, the color filter includes a plurality of pixels which are aligned with a plurality of pixels contained in the CCD to ensure that an image passing through the lens, the color filter and the CCD is correctly formed without distortion and other defects. When any portion of a light flux passing through the lens to the color filter and then to the CCD is inclined relative to the optical axis, an image cannot be formed correctly and the image is distorted resulting in a poor telecentric character. Thus, when a light flux is inclined relative to the optical axis, a telecentric character is poor.
It was discovered that a poor telecentric character can be overcome and a good telecentric character can be provided if an exit pupil is located sufficiently far from an image surface. Thus, when a zoom lens system is arranged such that an exit pupil is located far from an image surface, the telecentric character is good.
Japanese Laid Open Patent Number 6-94996 teaches such a conventional zoom lens system for use with a camera having a color filter and CCD which provides a good telecentric character by arranging an exit pupil far from an image surface. The structure of the device described in JP 6-94996 is shown in FIG. 31 of the present application. As seen in FIG. 31, the zoom lens system of JP 6-94996, includes successively from an object side, a first lens group I having a negative refracting power, a second lens group II having a positive refracting power and a third lens group III having a positive refracting power. In this system, the first lens group I moves with the second lens group II as shown in FIG. 31 to correct the movement of the focus position according to the variable power. The third lens group III remains stationary during power variation. An aperture diaphragm is fixed between the first lens group I and the second lens group II.
Although the zoom lens system shown in FIG. 31 solves the problems described above and provides an acceptable telecentric character, the zoom lens system of FIG. 31 is only capable of achieving a relatively small magnification and back focus. For example, it has been determined that the lens system shown in FIG. 31 can only achieve a magnification ratio of 1.9 and a back focus of 6.1. Thus, the zoom lens system of FIG. 31 has serious disadvantages for use in a video camera recorder, a digital still video camera or the like because of the severely limited magnification ratio and back focus.


The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer transfers data between circuits running on different clocks. The present invention delays the initial output of data from the FIFO memory buffer until the memory buffer has received a threshold amount of data. After the threshold quantity of data has been received, the present invention allows output of data from the FIFO.

1. Field of the Invention
The present invention relates to a method and apparatus for transferring data between systems running at different clock rates. More specifically, the present invention relates to simplifying the flag control circuitry of a first in first out memory buffer which transfers data between a source system running at one clock rate, and a destination system running at a different clock rate.
2. Description of Related Art
A First-in, first-out (FIFO) buffer or memory unit can be used to temporarily store information for transfer between two circuits running at different clock rates. Separate input and output terminals on the FIFO allow data to be input into the FIFO at one clock rate and output from the FIFO at a different clock rate. Thus when placed between a source unit and a destination unit running on two different clock rates, the FIFO can match data flow between the two units by accepting data from a source unit at one rate of transfer and delivering data to a destination unit at a different rate. In particular if the source unit is slower than the destination unit, the FIFO can be filled with data at a slower rate and later emptied at a higher rate. Conversely, if the source unit is temporarily faster than the destination unit, the FIFO may store the bursts of data and output the data in the time interval between bursts.
Limited memory size requires that the aggregate data transferred into the FIFO and the aggregate data removed from the FIFO be approximately equivalent. Thus if the cumulative input of data into the FIFO significantly exceeds the cumulative output of data by the FIFO, memory overflow can result. Conversely, if the cumulative output of data from the FIFO exceeds the cumulative inflow of data over a significant period of time, memory underflow or the emptying of the FIFO memory and the output of invalid data may result. Thus to prevent either of these conditions from occurring, conventional asynchronous FIFOs use flag circuitry to indicate their status.
Conventional flag circuitry includes logic which continuously compares the values of the input and output data pointers and indicates when they are close (FIFO emptying) or distant (FIFO filling). Copies of the input (write) and output (read) pointers are synchronized and continuously compared. The comparison logic in the flag circuitry provides flexible status information, which may include multiple threshold information, as well as indicators which warn when the FIFO is empty or when the FIFO is full.
The primary problem with current flag circuitry is that complex comparison circuitry is required. The comparators themselves are complicated logic. Synchronization logic which enables comparison between the two time domains also adds to circuit complexity. In small FIFOs the complexity of the overhead logic is excessive.
Larger circuits suffer less from the overhead created by conventional flag circuitry because the increase in number of logic elements in a comparator and synchronization logic circuit is proportional to the base-2 logarithm of the FIFO size. The slow increase in computational requirements makes conventional FIFO flag logic acceptable for large FIFOs; however, in small FIFOs the complexity of the comparators and synchronizers can significantly exceed the complexity of the FIFO RAM and pointers. Small FIFOs are commonly used in video systems where close synchronization between different clocks make large FIFOs unnecessary
The complicated circuitry used to generate control flags for large FIFOs requires significant resources and is inefficient, particularly in applications where small FIFOs are used. Thus a simple and reliable flag control method for use in small FIFO memories is needed.

Control circuit for a buffer memory to transfer data between systems operating at different speeds


Herein disclosed is a semiconductor device simulation apparatus which is set the various parameters to be used for measuring a current value and a voltage value that varies depending on the internal resistance of a DUT, and simulates a current value or a voltage value that varies depending on an internal resistance of a DUT in accordance with various parameters and a prescribed test signal when receiving the test signal. Also disclosed is a semiconductor test program debugging apparatus using such a semiconductor device simulating apparatus.

The present invention relates to a semiconductor device simulating apparatus that is used in a program debugging apparatus for checking a test program by emulating a semiconductor test apparatus, as well as to a semiconductor test program debugging apparatus using such a semiconductor device simulating apparatus.
Semiconductor test apparatuses are known that perform a DC test, a function test, etc. on various semiconductor devices such as logic ICs and semiconductor memories before shipment. The tests that are performed by semiconductor test apparatuses are generally classified into the function test and the DC test. In a function test, a prescribed test pattern signal is applied to a semiconductor device to be tested (hereinafter referred to as xe2x80x9cDUTxe2x80x9d) and it is checked whether the DUT performs an expected operation for the test pattern signal. In a DC test, it is checked whether DC characteristics obtained at each terminal of a DUT are expected ones. Among the DC tests for example, there are voltage-application current-measurement tests which test whether an expected current can be output from a terminal when a known voltage is applied, and current source voltage measurement tests which test whether an expected voltage appears at a terminal when a known current is input or output. In case of function tests, in many cases, voltage conditions, current conditions, etc. that are applied to a DUT are changed in various manners such as changing a high-level-state voltage to 4 V that is lower than a regular voltage value of 5 V, for example, and changing a low-level-state voltage to 0.5 V that is higher than a regular voltage value of 0 V, for example.
In conducting a function test or a DC test, various conditions, that is, tests of what items are to be performed under what conditions are incorporated in advance in a semiconductor test program. Therefore, various tests can be performed on a DUT by running such a semiconductor test program. However, a semiconductor test program includes an enormous number of steps because it is required to control a wide variety of operations such as setting of test items, setting of test conditions, execution of a test, and judgment of a test result. When the kind of a DUT or its logic is changed, it is necessary to alter a semiconductor test program accordingly in various manners. When a semiconductor test program is newly generated or altered, it is necessary to evaluate it, that is, to check whether the program itself operates normally. One method is such that a semiconductor test program is evaluated by running it for a DUT that is known to be good or defective by using an actual semiconductor test apparatus. However, semiconductor test apparatuses themselves are expensive and are introduced in a small number. Therefore, testing whether a semiconductor test program operates normally by using an actual semiconductor test apparatus requires that operation of a semiconductor test line be stopped and hence is not preferable. In view of the above, conventionally, instead of evaluating a semiconductor test program by using an actual semiconductor test apparatus, whether the semiconductor test program operates normally is checked by emulating the semiconductor test apparatus by using a general-purpose computer such as a workstation.
For example, Japanese Patent Laid-Open No. 9-185519 discloses a technique in which a semiconductor test apparatus is emulated. This publication relates to a debugging apparatus for testing whether a semiconductor test program operates normally. This debugging apparatus configures an emulated semiconductor test apparatus by running a semiconductor test program to be debugged under the operating system of a general-purpose computer. A simulatory function test or DC test is conducted by connecting an virtual subject device section, test condition setting section, test item setting section, test result storage section, etc. to the emulated semiconductor test apparatus via an interface section and reading virtual data that are set in the virtual subject device section in accordance with test conditions that are set in the test condition setting section.
In the above debugging apparatus, instead of using an actual DUT, virtual data that are set in advance in the virtual subject device section are read into the emulated semiconductor test apparatus via the interface section in accordance with test conditions that are set in the test condition setting section. Judgments xe2x80x9cpassxe2x80x9d and xe2x80x9cfailxe2x80x9d are made when the virtual data are within or out of a range corresponding to the test conditions. As such, unlike the case of a DC test using an actual semiconductor test apparatus, the conventional virtual subject device section does not reflect operation of an actual DUT such as a value variation that depends on the internal resistance of a DUT that may occur when a voltage-application current-measurement test or a current-application voltage-measurement test is performed on a measurement subject pin (evaluation subject pin) of the actual DUT. That is, the conventional debugging apparatus merely reads virtual data that are set in advance in the virtual subject device section irrespective of the internal resistance of a DUT, and hence does not properly simulate the operation of the actual DUT.
There is another problem that when it is intended to debug a semiconductor test program by using such a virtual subject device section, part of it cannot be debugged sufficiently for the following reason. To judge the logical value of a signal, it is necessary to set high-level and low-level threshold values at proper values in consideration of a voltage variation due to the internal resistance of a DUT. However, the conventional debugging apparatus cannot judge whether threshold values that are set in a semiconductor device test program are appropriate because a voltage variation due to the internal resistance of a DUT is not taken into consideration.
The present invention has been made to in view of the above respects, and an object of the invention is therefore to provide a semiconductor device simulating apparatus capable of properly simulating and outputting a voltage value or a current value that varies depending on an internal resistance as in an actual DUT.
Another object of the invention is to provide a semiconductor test program semiconductor test program debugging apparatus capable of properly checking the contents of a semiconductor test program even in a case of using a virtual semiconductor device (hereinafter described as xe2x80x9cdevice modelxe2x80x9d) in the same manner as in a case where the semiconductor test program is run for an actual DUT.
According to an aspect of the invention, a semiconductor device simulating apparatus comprises parameter setting unit for setting various parameters to be used for measuring a current value or a voltage value that varies depending on an internal resistance of a DUT; input unit for inputting a test signal for the DUT; and simulating unit for simulating and outputting a current value or a voltage value that varies depending on the internal resistance of the DUT in accordance with the parameters and the test signal.
In general, a current value or a voltage value that is measured from a signal pin of a DUT varies depending on an internal resistance of the DUT. Therefore, by simulating a current value or a voltage value of a DUT with the simulating unit after setting, with the parameter setting unit, various parameters that are necessary for such a measurement, a current value or a voltage value that varies depending on an internal resistance can properly be simulated and output in the same manner as in the case of measuring an actual DUT.
In particular, it is desirable that the various parameters that are set by the parameter setting unit include a first parameter indicating a voltage value and a resistance value in a case where a signal pin of a DUT is in a high-level state, a second parameter indicating a voltage value and a resistance value in a case where the signal pin is in a low-level state, a third parameter indicating a resistance value in a case where the signal pin is in a high-impedance state, a fourth parameter indicating which of the high-level state, low-level state, and the high-impedance state the signal pin is in, and a fifth parameter indicating a current value or a voltage value to be applied to the signal pin in a current source voltage measurement or a voltage source current measurement. Further, it is desirable that the above described simulating unit simulates a voltage value that would appear at each signal pin of the DUT in the current source voltage measurement or a current value that would appear at each signal pin of the DUT in the voltage source current measurement based on these first to fifth parameters and the test signal.
When a voltage source current measurement or a current source voltage measurement is performed by applying a prescribed voltage or current in a case where a signal pin is in a high-level state, the fourth parameter indicates that a high-level state is established. Therefore, the simulating unit outputs a current value or a voltage value corresponding to the signal pin based on the voltage value and the resistance value that are indicated by the first parameter and the application voltage value or current value that is indicated by the fifth parameter. When applying a prescribed voltage or current in a case where the signal pin is in a low-level state performs a voltage source current measurement or a current source voltage measurement, the fourth parameter indicates that a low-level state is established. Therefore, the simulating unit outputs a current value or a voltage value corresponding to the signal pin based on the voltage value and the resistance value that are indicated by the second parameter and the application voltage value or current value that is indicated by the fifth parameter. When applying a prescribed voltage or current in a case where the signal pin is in a high-impedance state performs a voltage source current measurement or a current source voltage measurement, the fourth parameter indicates that a high-impedance state is established. Therefore, the simulating unit outputs a current value or a voltage value corresponding to the signal pin based on the resistance value that are indicated by the third parameter and the application voltage value or current value that is indicated by the fifth parameter. Since in this manner the various parameters are set so as to conform to a current source voltage measurement or a voltage source current measurement, a voltage value or a current value that varies depending on an internal resistance can properly be simulated and output in the same manner as in the case of measuring an actual DUT.
In particular, it is desirable that the various parameters that are set by the above described parameter setting unit include a sixth parameter indicating a resistance value corresponding to a power source pin of a DUT and a seventh parameter indicating a current value or a voltage value to be applied to the power source pin. In this case, it is desirable that the above described simulating unit simulates a voltage value that would appear at the power source pin in a current source voltage measurement or a current value that would appear at the power source pin in a voltage source current measurement based on the sixth and seventh parameters and the test signal.
When a voltage source current measurement or a current source voltage measurement is performed by applying a prescribed voltage or current to a power source pin, a current value or a voltage value corresponding to the power source pin is properly simulated and output from the simulating unit based on the resistance value indicated by the sixth parameter and the application voltage value or current value indicated by the seventh parameter.
In particular, it is desirable that the various parameters that are set by the above described parameter setting unit include a first parameter indicating a voltage value and a resistance value in a case where a signal pin of a DUT is in a high-level state, a second parameter indicating a voltage value and a resistance value in a case where the signal pin is in a low-level state, a third parameter indicating a resistance value in a case where the signal pin is in a high-impedance state, and a fourth parameter indicating which of the high-level state, low-level state, and the high-impedance state the signal pin is in. In this case, it is desirable that the test signal that is input by the input unit indicates a condition relating to a load that is to be connected to the signal pin.
In a case where a signal pin of a DUT is in a high-level state and the load condition is no load, the fourth parameter indicated that a high-level state is established. Therefore, the simulating unit outputs a voltage value corresponding to the signal pin based on the voltage value and the resistance value indicated by the first parameter and a test signal indicating a no-load condition. In a case where the signal pin is in a low-level state and the load condition is no load, the fourth parameter indicated that a low-level state is established. Therefore, the simulating unit outputs a voltage value corresponding to the signal pin based on the voltage value and the resistance value indicated by the second parameter and the test signal indicating a no-load condition. In a case where the signal pin is in a high-impedance state and the load condition is no load, the fourth parameter indicated that a high-impedance state is established. Therefore, the simulating unit outputs a voltage value corresponding to the signal pin based on the resistance value indicated by the third parameter and the test signal indicating a no-load condition. Similarly, in other cases such as a case where the load condition is an ideal voltage source and a terminating resistor or a programmable load with an ideal current source, the simulating unit outputs a voltage value based on such a load condition. By taking the load condition into consideration in this manner, a voltage value or a current value that varies depending on an internal resistance can properly be simulated and output in the same manner as in the case of measuring an actual DUT.
According to another aspect of the invention, a semiconductor test program debugging apparatus comprises tester emulating unit for setting various parameters to be used for measuring a current value or a voltage value that varies depending on an internal resistance of a DUT, and for emulating an operation of a semiconductor test apparatus by generating a simulatory test signal to be applied to the DUT based on a semiconductor test program; device simulating unit receiving the parameters and the test signal, for simulating and outputting a current value or a voltage value that varies depending on an internal resistance of the DUT in accordance with the parameters and the test signal; and debugging unit for debugging the semiconductor test program based on an output of the device simulating unit.
The device simulating unit corresponds to the above-described semiconductor device simulating apparatus. That is, the semiconductor test program debugging apparatus according to the invention is formed by using the above-described semiconductor device simulating apparatus. Therefore, the device simulating unit properly simulates an operation of a DUT by taking into consideration a voltage variation due to an internal resistance of the DUT. This makes it possible to conduct tests that cannot be performed conventionally such as a test as to whether high-level and low-level threshold values that are described in a semiconductor test program are appropriate. As a result, the accuracy of debugging of a semiconductor test program can be increased.

Semiconductor device simulating apparatus and semiconductor test program debugging apparatus using it


A thin film transistor (TFT), method of manufacturing the TFT and a flat panel display having the TFT are disclosed. In one aspect, the TFT comprises a substrate and an active layer formed over the substrate, wherein the active layer is formed of oxide semiconductor, and wherein the active layer includes two opposing sides. The TFT also comprises source and drain regions formed at the opposing sides of the active layer, a first insulating layer formed over the active layer, a gate electrode formed over the active layer, a second insulating layer formed covering the first insulation layer and the gate electrode, and a first conductive layer formed on the source and drain regions and contacting the second insulating layer.

Field
The described technology generally relates to a thin film transistor (TFT), a method of manufacturing the TFT and a flat panel display device having the TFT.
Description of the Related Technology
A thin film transistor (TFT) is used in various electronic devices including flat panel displays (FPDs), and the like. For example, the TFT can be used as a switching element or driving element in flat panel display devices including liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, electrophoretic display, and the like.
The TFT includes a gate electrode coupled to a gate line for supplying a scan signal, a source electrode coupled to a data line for supplying a signal to be applied to a pixel electrode, a drain electrode opposite to the source electrode, and a semiconductor layer electrically coupled to the source and drain electrodes.

Thin film transistor, method of manufacturing thin film transistor and flat panel display having the thin film transistor


A process for aligning liquid crystals adjacent to a surface of an optical alignment layer comprising: exposing at least one optical alignment layer, comprising anisotropically absorbing molecules, to polarized light; the polarized light having a wavelength within the absorption band of said anisotropically absorbing molecules; wherein the exposed anisotropically absorbing molecules induce alignment of a liquid crystal medium at an angle + and - with respect to the direction of the polarization of the incident light beam and along the surface of the optical alignment layer; and applying a liquid crystal medium to said optical alignment layer; wherein said anisotropically absorbing molecules consist essentially of diaryl ketones, is described. The invention also is directed to a liquid crystal optical storage medium, a liquid crystal display element, and a liquid crystal diffractive optical element made by the process of the invention and to novel polyimide compositions that are useful as optical alignment layers in the process of the invention.

The present invention relates to processes for aligning liquid crystals, compositions useful for generating alignment of liquid crystals and liquid crystal optical elements.
Liquid crystal compounds are used in human and machine readable displays, finding applications in instrument controls, such as those in motor vehicles, avionics, medical devices, process control devices and watches. Display devices are primarily comprised of liquid crystal cells having a glass or other substrate coated with a transparent conductive material in front and behind a liquid crystal medium. Light transmission through these devices is controled through orientation of the liquid crystal compounds or dyes dissolved therein. In this way, a voltage or, in some instances, a magnetic field may be applied to the cell so that the liquid crystals are oriented in a fashion such that all, some or none of the light is passed through. In addition, depending on the device geometry, polarizers may be used in conjunction with the liquid crystal medium to control light transmission.
Aligned liquid crystal cells in commerical use are typically oriented in directions suitable for controlling light transmission. That is, the molecules in the liquid crystal compostion are aligned so as to assume a homogeneous or homeotropic alignment. Without external stimuli the display will either appear opaque or transparent. By applying an electric field the molecules are rotated along a fixed axis so as to alter the transmission properties in a desired fashion.
Current liquid crystal display elements include a product that utilizes a twisted nematic mode, i.e. having a structure wherein the aligning direction of nematic liquid crystal molecules is twisted by 90.degree. between a pair of upper and lower electrode substrates, a product utilizing a supertwisted nematic mode, utilizing a birefringent effect, i.e. having a structure wherein the aligning direction of nematic liquid crystal molecules is twisted by 180.degree. to 300.degree., a product utilizing a ferroelectric liquid crystal substance or an antiferroelectric liquid crystal substance. Common to each of these products is a liquid crystal layer disposed between a pair of substrates coated with a polymeric alignment layer. The polymeric alignment layer controls the direction of alignment of the liquid crystal medium in the absence of an electric field. Usually the direction of alignment of the liquid crystal medium is established in a mechanical buffing process wherein the polymer layer is buffed with a cloth or other fibrous material. The liquid crystal medium contacting the buffed surface typically aligns parallel to the mechanical buffing direction. Alternatively, an alignment layer comprising anisotropically absorbing molecules may be exposed to polarized light to align a liquid crystal medium as disclosed in U.S. Pat. Nos. 5,032,009 and 4,974,941, both entitled "Process of Aligning and Realigning Liquid Crystal Media," both of which are hereby incorporated by reference.
The process for aligning liquid crystal media with polarized light is a noncontact method of alignment which can reduce dust and static charge buildup on alignment layers. Other advantages of the optical alignment process include high resolution control of alignment direction and high quality of alignment.
Requirements of optical alignment layers for liquid crystal displays include low energy threshold for alignment, transparency to visible light (no color), good dielectric properties and voltage holding ratios, long-term thermal and optical stability and in many, but not all, applications, a controlled uniform pre-tilt angle.
The process for aligning liquid crystal media with polarized light has many attractive features. To exploit this process for use in many liquid crystal device applications, anisotropically absorbing molecules that absorb in the ultraviolet (UV) region are desirable because they can be transparent in the visible region. Schadt, et al (Jpn. J. Appl. Phys., 1992, 31, 2155), for instance, has described polyvinyl cinnamates as a useful material for optical alignment of liquid crystals; and Hasegawa, et al (J. Photopolymer Sci. & Tech., 1995, 8, 241) has described UV exposure of a commercial polyimide and shown it to align liquid crystals.


A one-piece molded polymeric sight gauge shield with internal cylindrical bore and method for making same are disclosed, along with a liquid-containing urn including same. The shield is molded by mating first and second mold portions about first and second spaced-apart cores to define: (i) a first annular void about the first core; and, (ii) a second annular void about the second core. The first and second mold portions respectively comprise first and second stand-up portions that first and second sidewall voids between themselves and the mating mold portion. First and second end portions of a gauge shield member are molded by filling the first and second voids, while the first and second sidewalls of the gauge shield member are molded by filling the first and second sidewall voids. The molding operation is a single-axis straight-pull molding method.

The present invention relates to shields for sight gauges. It finds particular application in connection with the protection of sight gauges used in association with urns containing coffee or other liquids that are to be dispensed through an associated faucet.
Sight gauges for urns and the like are used to indicate the level of liquid in the urn and are provided in the form of an elongated tubular glass or polymeric member in fluid communication with the urn and secured adjacent an outer wall thereof and/or to the dispensing faucet thereof in a vertical orientation for convenient operator viewing. The tubular member is surrounded by a protective metal or plastic gauge shield that supports the tubular member and protects same against breakage during use and during shipping/handling of the urn.
To permit viewing of the tubular gauge member, prior gauge shields have included at least one slot formed through a wall thereof. The slot is formed by milling or is defined by a die during an extrusion process if the gauge shield is an extruded member. Known milled sight gauge shields have been deemed suboptimal in terms of cost for certain applications. Other lower-cost shields, e.g., extruded polymeric gauge shields, have been found to lack the desired aesthetics in that they do not resemble traditional milled shields.
It has been deemed desirable to provide a molded polymeric sight gauge shield that exhibits the desired aesthetics and performance characteristics with associated low-cost.


A burner assembly is provided. The burner assembly includes a support housing with a supply manifold, the supply manifold includes a fuel passage system, and fuel nozzles extending from the supply manifold and being supplied with fuel through the fuel passage system of the supply manifold. The supply manifold is sandwiched using at least two subparts.

A typical gas turbine burner assembly, as it is mainly used in so called canannular combustion systems is, for example, described in U.S. Pat. No. 6,082,111 and in US 2004/0055306 A1. Such burner assemblies typically comprise a cover plate to which a support housing is mounted. The support housing comprises a manifold with fuel and oil passages machined inside and fuel nozzles, so called rockets, extending from the manifold and being supplied with fuel through the gas and oil passages. Injection holes in the fuel nozzles guide the fuel out of the nozzles into a flow path of air delivered by the compressor of the gas turbine to the burner assembly. Swirlers are present in this flow path for providing a swirl to achieve a thorough mixing of fuel and air. This design of the support housing includes eight fuel nozzles (rockets), for example, which are welded to the manifold and also to the swirlers of a main swirler assembly.
However, the design described in the mentioned prior art is compromised by high costs for production of the manifold since machining of gas and oil channels into the manifold is elaborate and requires a high thickness of the manifold. After machining the fuel passages, cover plates are welded onto the manifold in order to close the passages. During the welding process care has to be taken not to induce too much stress in the manifold material due to the heat introduced during the welding process. Moreover, the material used for the manifold needs to be produced from a corrosion-resistant material since the fuel comes into contact with the walls of the gas or oil channels machined into the manifold. In addition, in use of the burner assembly the manifold will have a considerably higher temperature than the fuel delivered through the manifold. Hence, the material also needs to be stress resistant. Therefore, the manifold and the fuel nozzles of the state of the art burner assemblies are usually made from forged pieces which need to be finished by abrasive techniques in order to reduce susceptibility to tension cracks. The material requirements increase the cost for producing the manifold. In addition, corrosion resistant and stress resistant materials are usually difficult to machine, which even more increases production costs.


A connector terminal includes a hollow sheath portion to be inserted into a terminal space formed in a housing of an electric connector, and an elastic contact piece positioned in the sheath portion, the contact piece making mechanical and electrical contact with a male terminal of an opponent electric terminal when the male terminal is inserted into the sheath portion, the male terminal being inserted into the sheath portion through an insertion path formed in the housing, the sheath portion being formed with a projection on at least one of inner walls thereof facing each other, the projection introducing a distal end of the contact piece to be located out of a cross-section of the insertion path in a direction perpendicular to a direction in which the male terminal is inserted into the sheath portion.

1. Field of the Invention
The invention relates to a connector terminal including a hollow sheath portion to be inserted into a terminal space formed in a housing of an electric connector, and an elastic contact piece positioned in the sheath portion to make mechanical and electrical contact with a male terminal of an opponent electric terminal when the male terminal is inserted into the sheath portion.
2. Description of the Related Art
There is known a female connector terminal to be inserted into a terminal space formed in a connector housing to make mechanical and electrical contact with a male terminal of an opponent connector when the male terminal is inserted into the terminal space.
FIG. 15 is a perspective view of an example of such a female connector terminal, suggested in Japanese Patent Application Publication No. 2001-52791.
A female terminal 1000 illustrated in FIG. 15 includes a sheath portion 1001 and an elastic contact plate 1005 housed in the sheath portion 1001. The sheath portion 1001 is formed at a front edge 1003 aligning with an opening edge 1002 thereof with a stepped portion 1004. The elastic contact plate 1005 is formed at a front edge thereof with an engagement portion 1006 to be engaged with the stepped portion 1004.
In the female terminal 1000 illustrated in FIG. 15, when a male terminal (not illustrated) is inserted into the sheath portion 1001 through the opening thereof, the elastic contact plate 1005 does not move in a direction in which the male terminal is inserted into the sheath portion 1001, and hence, ear pieces 1007 formed at the elastic contact plate 1005 do not make intensive abutment with peripheral inner edges of windows 1009 formed at sidewalls 1008 of the sheath portion 1001. Thus, the elastic reaction of the elastic contact plate 1005 is not interfered with the male terminal in the female terminal 1000, and accordingly, it is not necessary to insert the male terminal into the sheath portion 1001 with an intensive force.
FIG. 16 is a perspective view of another example of the above-mentioned female connector terminal, suggested in Japanese Utility Model Publication H4 (1992)-8623.
A female terminal 1100 illustrated in FIG. 16 includes a sheath portion 1101 to receive a male terminal (not illustrated) therein, and an elongate flat spring 1102 housed in the sheath portion 1101. The flat spring 1102 is formed at opposite side edges thereof with outwardly projecting ear pieces 1103. By causing the ear pieces 1103 to be engaged to grooves 1104 formed at sidewalls of the sheath portion 1104, the flat spring 1102 is fixed in the sheath portion 1101.
The sheath portion 1101 is formed at sidewalls thereof with stepped portions 1105 in alignment with lower edges of the grooves 1104. Accordingly, the stepped portions 1105 support the ear pieces 1103 of the flat spring 1102, and the ear pieces 1103 are further supported on the lower edges of the grooves 1104 to thereby be located in a designed position.
The female terminal 1000 illustrated in FIG. 15 is accompanied with a problem that since the engagement portion 1006 formed at a front edge of the elastic contact plate 1005 is engaged only to the stepped portion 1004, the elastic contact plate 1005 may float up at the front edge thereof from a desired position.
If the male terminal is inserted into the sheath portion 1101 while the elastic contact plate 1005 is floating up at the front edge thereof, the male terminal makes contact with and pushes the front edge, resulting in that it is afraid that the elastic contact plate 1005 may be bent or damaged by the male terminal.
In the female terminal 1100 illustrated in FIG. 16, since the stepped portions 1105 are formed in alignment with the lower edges of the grooves 1104, the flat spring 1102 may be displaced at a front edge thereof to a level of the grooves 1104. Thus, if the flat spring 1102 is displaced at a front edge thereof to a level of the grooves 1104, the male terminal inserted into the sheath portion 1101 makes contact with and pushes the front edge of the flat spring 1102, resulting in that it is afraid that the flat spring 1102 may be bent or damaged by the male terminal.
As mentioned above, the conventional female terminals 1000 and 1100 are accompanied with a problem that when the male terminal is inserted into the sheath portion 1001 or 1101, it is possible that the male terminal may bend or damage the contact plate 1005 or the flat spring 1102 with the result of failure in electrical contact between the female and male terminals.


CrFC21 cDNA was cloned into two mammalian vectors: pCIneo and pCDNAI, both of which carry the strong CMV promoter for expression in mammalian cell lines. Various CrFC cDNA constructs transformed into P. pastoris and S. cerevisiae were expressed to yield full-length recombinant Factor C (rCrFC) protein of .about.130 kDa which is immunoreactive. The rCrFC is expressed in an intracellular, insoluble form. Intracellular localization of the nascent protein provides protection from premature digestion by proteases secreted by the host cell. Subsequent to its synthesis, rCrFC is solubilized and purified under pyrogen-free conditions. Using established protocols, the protein can be denatured and renatured to recover its biological functionality. By manipulation of the 5' end of CrFC26, truncated constructs containing this cDNA are expressed by S. cerevisiae to give immunoreactive rCrFC. The rCrFC produced from both CrFC21 and CrFC26 constructs, solubilized by Triton X-100 or SDS, is found to be immunoreactive. Solubilized rCrFC was purified as a proenzyme and reversibly protected from activation by addition of Me.sub.2 SO.

Articles of the scientific periodical and patent literature are cited throughout the specification. Each such article is hereby incorporated by reference in its entirety by such citation.
Gram negative bacterial endotoxin is a widespread contaminant of materials employed in biomedical arts, both research and clinical. All pharmaceutical solutions used for parenteral or injection administration must be certified as to endotoxin levels. Also, media used for tissue culture applications are typically tested for the presence of endotoxin. It is of great importance, therefore, to be able to produce a reliably reproducible test for the presence of endotoxin in a sample. Also, it would be an advance in the art to provide materials and methods for removing Gram negative bacterial endotoxins from formulations intended for pharmaceutical or other uses requiring preparations substantially free of endoltoxin.
Factor C is a component of the Limulus amoebocyte lysate (LAL) assay that is presently the standard method for testing for endotoxin. Factor C is a serine protease proenzyme that is the first protein in a cascade that leads to coagulation of the LAL upon contact with endotoxin. Factor C is the protein that actually binds to the endotoxin; upon binding of endotoxin, the serine protebase activity of Factor C becomes activated. The activated Factor C initiates a chain of proteolytic steps culminating in formation of a solid clot of protein from the LAL. The time for forming the LAL clot and the degree of gelation is indicative of the amount of endotoxin in a sample (Ho, B., Kim, J. C., and Ding, J. L., 1993, Biochem. Mol. Biol. Intl. 29, 687-694). However, this gelation assay is subjective, and variable in its sensitivity of detection of endotoxin due to batch-to-batch variation in the amoebocyte lysate preparation. It is therefore desirable to express recombinant Factor C which could be standardized for use in an assay for endotoxin detection.
There are other endotoxin tests presently known, for example, the United States Pharmacopeia (USP) rabbit pyrogen assay (Tomasulo, P. A., Levin, J. Murphy, P. A. & Winkelstein, J. A. 1977. J. Lab. Clin. Met. 89, 308-315) However, the USP rabbit pyrogen test is not only time consuming, it is also expensive and often gives variable results in detecting endotoxin in pharmaceuticals and parentals (Muller-Calgon, H., pp. 343-356; "Endotoxins and their Detection with the LAL test," S. Watson et al., ed., c. 1982 by Alan R. Liss, New York N.Y.).
Enzyme-linked-immunosorbent assay (ELISA) has been developed for testing evoked secretion of interleukin-6 from monocytic cell lines in response to pyrogen or endotoxin (Taktak, Y. S., Selkirk, S., Bristow, A. F., Carpenter, A., Ball, C., Rafferty, B., & Poole, S., J. Pharm. Pharmacol. 43, 578-582 (1991)). However, this test is probably more suited for research purposes.
One other form of endotoxin detection involves its localization in tissues of experimental animals during induced endotoxemia. An immunohistochemical method utilizes native Factor C (purified from T. tridentatus) to specifically bind the endotoxin. The Factor C-endotoxin complex is then revealed by labelled anti-Factor C antibody (Takeuchi, M. et al., Pathol. Res. Pract. 190(12): 1123-1133 (1994); Nakao, A. et al., Eur. Surg. Res. 27(4): 216-221 (1995)). This study indicates another utility for Factor C. It is therefore within the embodiment of this application to obtain truncated recombinant constructs (e.g., pHILD2/CrFC21/EE containing the 5' end of CrFC cDNA insert flanked by EcoR1 sites).
cDNAs encoding Factor C proteins from Carcinoscorpius rotundicauda have been previously described (U.S. Ser. No. 08/296,014 and J. L. Ding, A. A. Navas III and B. Ho, Mol. Marine Biol. and Biotech. 4:90-103 (1995)). Recombinant Factor C from Carcinoscorpius rotundicauda (rCrFC) has been produced in vitro by coupled transcription/translation systems (U.S. Ser. No. 08/296,014 and S. D. Roopashree et al. Biochem. and Mol. Biol. Int'l. 35:841-849 (1995)). However, the present invent-on resides partly in the development of in vivo systems, especially using yeasts as a host cell, for efficient production of rCrFC by expression of cloned DNA.
Also, the protection of rCrFC from activation and subsequent self-proteolysis by binding of endotoxin which may be present in solutions used in isolation of the protein is described in U.S. Ser. No. 08/296,014. Basically, dimethylsulfoxide (Me.sub.2 SO, DMSO) is added to solutions which are used during the purification process. Even greater protection of the rCrFC is achieved by also adding an agent effective for chelating divalent metal ions to the purification solutions.
As a means to circumvent difficulties in determining endotoxin in plasma due to endogenous interfering factors, a chromogenic LAL assay was modified to include a specific step to adsorb the plasma endotoxin using immobilized histidine. Endotoxin in samples was separated from interfering factors by chromatography through immobilized histidine in which endotoxin was specifically adsorbed and, subsequently quantified by fluorimetric LAL assay (Nawata, M., Minobe, S., Hase, M., Watanabe, T., Sato, T. & Tosa, T., J. Chromatogr., 597: 415-424 (1992); Minobe, S., Nawata, M., Shigemori, N. & Watanabe, T., Eur. J. Clin. Chem. Clin. Biochem., 32(10): 797-803 (1994). However, this method of endotoxin adsorption is limited only to small volumes of 0.5-1 ml, and there is no report on the use or feasibility of this method for removing endotoxin from large preparations. It has so far only been reported as an improved method of endotoxin assay, albeit one limited by infeasibility of chromogenic assay of the endotoxin bound to the column.
More recently, Qiagen (US) has marketed a `Qiagen` kit for purification of endotoxin-free plasmids (See, Qiagen News Issue No. 1, 1996). This may involve a specific (proprietary) reagent that removes endotoxin from the plasmid preparation.

Expression of carcinoscorpius rotundicauda factor C in eukaryotes


A process for making high specific viscosity copolymers of maleic anhydride and an alkyl vinyl either having as specific viscosity of at least 7, preferably 10-50, are made by copolymerizing maleic anhydride and an alkly vinyl ether monomers in the presence of added acetylene.

1. Field of the Invention
This invention relates to a process for making a copolymer of maleic anhydride and an alkyl vinyl ether, and, more particularly, to a process for making such copolymers of advantageously high specific viscosity.
2. Description of the Prior Art
British Patent 906,230 described the preparation of copolymers of maleic anhydride and methyl vinyl ether in benzene as solvent. Example 1 also disclosed a copolymerization process in absence of solvent in which powdered maleic anhydride, methyl vinyl ether and initiator were precharged into an autoclave and reacted at 55° C. The specific viscosity (SV) of the product, however, was only 3.45 (1% in methyl ethyl ketone, MEK).
Other processes and copolymer products described previously included U.S. Pat. Nos. 4,952,558; 5,034,488; 5,047,490; 5,874,510; 6,624,271; 6,184,325; and Re 36,657.
However, none of these processes are suitable for making such copolymers of advantageously high specific viscosity (and, correspondingly, high molecular weights).
Accordingly, it is an object of this invention to provide a process for making copolymers of maleic anhydride and an alkyl vinyl ether having high specific viscosities.
A feature of this invention is a process for making such copolymers in which the copolymerization is carried out in the presence of added acetylene.
Another feature of the invention is the provision of copolymers of maleic anhydride and methyl vinyl ether having a specific viscosity of at least 7, preferably at least 10 (1% in MEK, 25° C.), uncrosslinked or crosslinked.
These and other objects and features of the invention will be made apparent from the following description.

Process for making copolymers of maleic anhydride and alkyl vinyl ether of high specific viscosity


A method and an apparatus for testing a memory are provided, where the memory includes a plurality of sectors each of which includes a plurality of bytes, and the testing is performed to the memory byte by byte. The method includes: during the testing, once a first byte in a first sector fails the testing, stopping testing the rest bytes in the first sector which haven't been tested, and skipping the testing to a second byte in a second sector. Accordingly, if one byte of the first sector fails the testing, the testing will be skipped to a second sector, and the remained bytes of the first sector will not be tested any more, and other testing items will not be implemented to the first sector within the whole testing flow. Therefore, redundant testing steps can be avoided and testing efficiency can be improved.

In computer systems, memory devices are used for storing programs and data. Almost all information of the computer systems, such as original data, programs, intermediate results and ultimate results, can be stored in the memory devices. Under control of a controller, the memory device can operate a write process or a read processes in a specific position. Memory devices which are used for storing information, are indispensible components of the computer systems.
In order to ensure normal operation of a memory, a testing process is required after the memory is manufactured. The testing process can be implemented by a direct test, an embedded CPU (Central Processing Unit), a MBIST (Memory Built In Self Test), or the like.
In the testing process, if the memory under test has been found having a problem, such as fails to implement a write operation or a read operation, or loses data, then a repairing process is needed.
Usually, when a memory is found having a problem, the repairing process is only implemented to a portion of the memory which has the problem, rather than the entire memory. Further, a memory may include a plurality of sectors, and a sector may include a number of bytes. For example, the memory may include hundreds or thousands of sectors, and each of sectors may include 256, 512 or 1024 bytes. Accordingly, the repairing process may be implemented to one sector of the memory. Therefore, when a byte of a sector fails the testing process, then the repairing process is only implemented to the sector rather than the entire memory.
In existing testing processes, when one sector of a memory is taken as a repairing unit, the testing is implemented in an order of one sector by another. Furthermore, during testing the sector, all bytes of the sector are tested successively.
However, when one byte of a sector fails the testing, it can be obtained that the sector where the byte located should be repaired. Then, other bytes of the sector are not necessarily to be tested any more.
Memory test may include more testing items. Specifically, except standard write and read function, more special stress testing modes which screen potential reliability defect are included. So, the testing flow is longer. Furthermore, in existing testing methods including redundancy functions, even if one sector fails at the first testing item, for other testing items, the failed sector still will be tested each time. So, lots of testing time is wasted on the original failed sector. The testing efficiency is lower.
Accordingly, exiting testing processes are redundant, thus testing efficiency are lower. Therefore, a memory testing method which can avoid redundant processes and has higher efficiency is required.

Shanghai Huahong Grace Semiconductor Manufacturing Corporation


An intervertebral implant for fusing vertebrae is disclosed. The implant has a body with curved, substantially parallel posterior and anterior faces separated by, two narrow implant ends, superior and inferior faces having a plurality of undulating surfaces for contacting vertebral endplates, and at least one depression in the anterior or posterior face for engagement by an insertion tool, at least two vertical through-channels extending through the implant, a chamfer on the superior and inferior surfaces at one of the narrow implant ends, and a beveled edge along a perimeter of the superior and inferior faces. The implant configuration facilitates transforaminal insertion of the implant into a symmetric position about the midline of the spine so that a single implant provides balanced support to the spinal column. The implant may be formed of a plurality of interconnecting bodies forming a single unit. An implantation kit and method are also disclosed.

A number of medical conditions such as compression of spinal cord nerve roots, degenerative disc disease, herniated nucleus pulposus, spinal stenosis and spondylolisthesis can cause severe low back pain. Intervertebral fusion is a surgical method of alleviating low back pain. In posterior lumbar interbody fusion ("PLIF"), two adjacent vertebral bodies are fused together by removing the affected disc and inserting posteriorly one or more implants that would allow for bone to grow between the two vertebral bodies to bridge the gap left by the removed disc.
One variation of the traditional PLIF technique is the transforaminal posterior lumbar interbody fusion (T-PLIF) technique. Pursuant to this procedure, an implant is inserted into the affected disc space via a unilateral (or sometimes bilateral), posterior approach, offset from the midline of the spine, by removing portions of the facet joint of the vertebrae. The T-PLIF approach avoids damage to nerve structures such as the dura, cauda equina and the nerve root, but the resulting transforaminal window available to remove the affected disc, prepare the vertebral endplates, and insert the implant is limited laterally by soft tissue and medially by the cauda equina.
A number of different implants typically used for the traditional PLIF procedure have been used for the T-PLIF procedure with varying success. These include threaded titanium or polymer cages, allograft wedges, rings, etc. However, as these devices were not designed specifically for the T-PLIF procedure, they are not shaped to be easily insertable into the affected disc space through the narrow transforaminal window, and may require additional retraction of the cauda equina and nerve roots. Such retraction can cause temporary or permanent nerve damage. In addition, some of these implants, such as the threaded titanium or polymer cage, suffer from the disadvantage of requiring drilling and tapping of the vertebral endplates for insertion. Further, the incidence of subsidence in long term use is not known for such cages. Finally, restoration of lordosis, i.e., the natural curvature of the lumbar spine is very difficult when a cylindrical or square titanium or polymer cage is used.
As the discussion above illustrates, there is a need for an improved implant and instrumentation for fusing vertebrae via the transforaminal lumbar interbody fusion procedure.

Intervertebral implant for transforaminal posterior lumbar interbody fusion procedure


The present invention relates to an all-optical sensor utilizing effective index modulation of a waveguide and detection of a wavelength shift of reflected light and a force sensing system accommodating said optical sensor. One embodiment of the invention relates to a sensor system comprising at least one multimode light source, one or more optical sensors comprising a multimode sensor optical waveguide accommodating a distributed Bragg reflector, at least one transmitting optical waveguide for guiding light from said at least one light source to said one or more multimode sensor optical waveguides, a detector for measuring light reflected from said Bragg reflector in said one or more multimode sensor optical waveguides, and a data processor adapted for analyzing variations in the Bragg wavelength of at least one higher order mode of the reflected light.

A sensor is a device that detects a specific physical quantity belonging to the sensor environment, through the means of one or more detection mechanisms which converts the physical quantity to a sensor specific output signal. Well known examples of often used sensors include thermometers, speedometers, microphones, voltmeters, radars and seismometers. A subset of the general sensor concept is the mechanical sensors which detects a property of classical mechanics, e.g. acceleration, pressure and strain, and should be distinguished from sensors used for e.g. biological, medical and chemical sensing. The vast majority of modern mechanical sensors are made using microelectromechanical system (MEMS) technology, as MEMS allows for small scale sensors and inexpensive mass production. With the development of MEMS technology and the advent of micro optical sensing technologies the expanded term microoptoelectromechanical systems (MOEMS) has become widely accepted. MOEMS allows for much more versatile sensor designs and detection of quantities in more difficult accessible environments than previous technologies.
All-optical sensors have a number of advantages that make them interesting for a broader range of applications, such as the low transmission loss in optical fibers which enables remote sensing. However, compared to the vast number of electrical and opto-electrical sensors available today, all-optical sensors currently represent a small niche, since most all-optical sensors cannot in general compete with their electrical counterparts when it comes to sensitivity, dynamic range or price.
The dominating all-optical frequency modulated (FM)-based sensor today is the fiber Bragg grating (FBG) sensor where the deformation of a Bragg grating is used for modulating the signal. While FBGs have successfully been used for a number of applications they have several drawbacks, including the large physical size, low sensitivity, strict limitations on materials choice and component structuring as well as mass production shortcomings. The inventors have previously presented a novel highly sensitive all-optical pressure sensor for an audio microphone fabricated using MEMS technology. The sensing mechanism is based on modifying the effective refractive index of a hollow core anti-resonant reflecting optical waveguide (ARROW) incorporating a Bragg grating. By modifying the effective refractive index instead of the grating period a highly improved sensitivity is obtained. Sensitivities can be up to several magnitudes larger than in FBGs and comparable MEMS technology.


A planetary gear transmission typically for use on automobiles has first, second, and third planetary gear trains arranged coaxially with each other and each having elements including a sun gear, a carrier, and a ring gear. Two of the elements of each of the first, second, and third planetary gear trains are directly or disengageably coupled to elements of the other planetary gear trains between input and output members. The elements of the first, second, and third planetary gear trains are corotatably coupled into first, second, third, fourth, and fifth rotational members the first, second, and fifth rotational members being coupled to the input member, the fourth rotational member being coupled to the output member. The planetary gear transmission also has a separating clutch disposed between the elements of the second rotational member, for disengageably connecting the elements of the second rotational member.

1. Field of the Invention
The present invention relates to a planetary gear transmission which comprises three planetary gear trains.
2. Description of the Prior Art
Planetary gear transmissions are widely used as automatic transmissions for automobiles or the like. Many conventional planetary gear transmissions comprise two planetary gears such as Ravigneaux gear trains, Simpson gear trains, or the like, which are combined with each other, and generally have gear positions up to a fourth forward gear position. To meet demands for more gear positions for improved running characteristics, there have been proposed transmissions having gear positions up to and more than a fifth forward gear position, and some of those proposed transmissions have already been in use.
Transmissions with an increased number of gear positions are disclosed in Japanese Laid-Open Patent Publication No. 63-318349 and Japanese Laid-Open Utility Model Publication No. 61-103654, for example. The disclosed transmissions comprise two planetary gear trains each combined with three clutches and three brakes, and have six forward gear positions and one reverse gear position. Since only two planetary gear trains are employed, the disclosed transmissions may share components with conventional planetary gear transmissions. However, the disclosed transmissions are complex in transmission control because they cannot avoid gearshifts which require two engaging means (a clutch and a brake) to be disengaged and two other engaging means to be engaged at the same time.
For example, when the disclosed transmissions effect a gearshift from the second gear position to the third gear position or a gearshift from the third gear position to the second gear position, it is necessary for the transmission to disengage one clutch and one brake and also to engage another clutch and another brake.
Japanese Laid-Open Patent Publications Nos. 59-222644 and 1-320362, for example, disclose planetary gear transmissions each having three planetary gear trains. In the disclosed planetary gear transmissions, two elements of each planetary gear train are mechanically coupled to elements of the other planetary gear trains, and four clutches and three brakes are combined with the planetary gear trains. The disclosed planetary gear transmissions have five forward gear positions and one reverse gear position which can be selected by controlling the operation of the engaging means (i.e., the clutches and the brakes). More specifically, any gearshifts between adjacent ones of the five forward gear positions can be accomplished by disengaging one engaging means (a clutch or a brake) and engaging another engaging means. Therefore, controlling the disclosed planetary gear transmissions is relatively simple.
The above planetary gear transmissions with three planetary gear trains are, however, problematic in that in certain gear ranges (e.g., a LOW (1ST) range, a 5TH range, a REV range, or the like), either one of the elements (i.e., a sun gear, a carrier, and a ring gear) of the planetary gear trains rotates at a speed considerably higher than the speed of rotation of the engine (i.e., the input shaft), i.e., rotates at excessive speed. Consequently, the planetary gear transmissions may not be combined with engines that rotate at high speed, although they are suitable for use with engines that rotate at low speed, such as diesel engines.
Transmissions with five gear positions are often required to have a wider range of speed reduction ratios from the first gear position (LOW) to the fifth gear position for better running performance than transmissions with four gear positions. The wider range of speed reduction ratios is also conducive to the rotation of either planetary gear train element at excessive speed.

Clutch-separable planetary gear transmission


A system creates a configuration definition table to be used for accessing a physical disk according to a host I/O request, to decrease a memory size of the configuration definition table even if common firmware is used for models with different scales. For this, a model correspondence table to show the definition of each model is provided in a configuration setup processing module, the maximum values of this model are recorded in a memory based on this content, and a memory area for each item is secured. And the actual content of the configuration definition is developed on the secured memory. Therefore even for a diversity of models, the memory size of the configuration definition table can be decreased to a size matching the model, with common firmware regardless the model.

1. Field of the Invention
The present invention relates to a configuration definition setup method for a disk array apparatus for setting configuration definition information used by the firmware of a disk array apparatus on which a number of disk devices for storing data are installed, and to a disk array apparatus, and more particularly to a configuration definition setup method for a disk array apparatus for making the storage size of the configuration definition information variable according to a different scale of a model, and to a disk array apparatus.
2. Description of the Related Art
Recently as various data are computerized and handled on computers, a data storage apparatus (external storage apparatus) which can efficiently store large volumes of data with high reliability, independently from a host computer which executes data processing, is increasingly more important.
For this data storage apparatus, a disk array apparatus comprising a great number of disk devices (e.g. magnetic disks and optical disks) and a disk controller for controlling these disk devices is used. This disk array apparatus can receive disk access requests simultaneously from a plurality of host computers and control a great number of disks.
User demands for such disk array apparatus vary, so models in a plurality of scales must be provided according to the purpose of a user. In other words, the number of disk devices to be installed changes depending on the purpose of a user. As a result various models are demanded, for example, from a large scale disk array apparatus which can control a disk device group comprised of several thousand or more disk devices with several hundred terabytes or more of storage capacity by itself, to a small scale disk array device which has several tens of disk devices.
A change of the configuration of the disk array apparatus means that it is necessary to set the configuration information for controlling the disk devices according to the scale. In other words, in the case of a disk array apparatus, the configuration information is the configuration definition in the firmware of the controller, and is internal information unique to the disk array apparatus. Examples are the information and status of each disk device being installed, the set up contents of LUN (Logical Unit Number) and a RAID group, the hardware status of the controller and the type of the installed adapter.
The minimum required memory size of the configuration information differs depending on the model. Conventionally in a computer system, the configuration information is automatically created according to the configuration of the connected devices, and is stored in memory (e.g. Japanese Patent Application Laid-Open No. H9-54744).
In a disk array apparatus, on the other hand, the configuration information itself is diverse depending on the model. For example, since the number of installed disks is several tens to several thousands, in the case of each model of product for the low end/mid-range where the number of installed disks is little, so configuration information creation firmware is created for each model because of the relationship with the memory to be installed. In the case of each model of product for high end where the number of installed disks is large, a memory for the configuration definition for the maximum number of disk devices that can be installed is secured, although firmware is the same for all the models.
With the conventional method for creating firmware for each model, the development cost increases and the evaluation-manpower thereof also increases, which may cause delays in providing new disk array apparatus to market.
With the conventional method for creating a configuration definition using common firmware, on the other hand, the memory capacity for the maximum configuration must be secured. This is because the required memory capacity is in proportion to the number of installed disk devices and to the number of LUNs (Logical Unit Number), so the required cache size of the memory changes depending on the model. Therefore the memory size to be installed in the disk array apparatus must be decided depending on the cache size and the memory size to be used for the configuration definition. This operation is extremely troublesome when the number of different models increases, so it is effective to fix the memory size to be used for the configuration definition to the size required for the maximum configuration.
However if the number of installed disk devices is different, the memory size to be used for the configuration definition also changes, so in the case of the conventional method of securing the memory size for the maximum configuration, unnecessary memory is installed. And installing unnecessary memory increases the price of the product, which runs counter to recent demands for a low price apparatus. In particular, for a model where an enormous number of disk devices are installed is demanded, with this method of securing the memory size for the maximum configuration for a great number of models in which the range of the number of installed disk devices is wide, the price of unnecessary memory becomes high with respect to the apparatus price which can no longer be ignored.

Configuration definition setup method for disk array apparatus, and disk array apparatus


Methods and structures for providing single-color or multi-color photo-detectors leveraging cavity resonance for performance benefits. In one example, a radiation detector (110) includes a semiconductor absorber layer (210, 410A, 410B, 610, 810, 1010, 1030, 1210, 1230) having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer (220, 630, 830, 1020, 1040) coupled to the absorber layer (210, 410A, 41013, 610, 810, 1010, 1030, 1210, 1230) and having a second electrical conductivity type, and a resonant cavity coupled to the collector layer (220, 630, 830, 1020, 1040) and having a first mirror (240) and a second mirror (245).

1. Field
One or more aspects of embodiments according to the present invention relate to infrared detectors, and more particularly to infrared detectors employing a cavity resonator, and including two semiconductor layers to detect two wavelength ranges.
2. Description of Related Art
Infrared detectors are used in a wide variety of applications including, for example, remote sensing, infrared astronomy, and various military applications. Infrared detectors are generally sensitive to thermal noise, and may therefore be cooled to cryogenic operating temperatures, for example, approximately 77 Kelvin (K). Recently, there has been a significant interest in higher operating temperature (HOT) infrared detectors, particularly HOT infrared focal plane arrays (FPAs), to remove or reduce the need for expensive cooling systems. Current approaches to realizing HOT detectors have focused on either the material design to address fundamental mechanisms such as Auger recombination, or reducing the volume of the detector to reduce sensitivity to thermal noise. However, by focusing on only one aspect of the problem at a time (either recombination or volume reduction), current approaches limit their utility, and even when ideally implemented, these solutions do not necessarily achieve a high enough operating temperature to provide significant benefit. Further, volume reduction techniques typically focus on single absorber/single color devices, resulting in narrow band devices, limiting their usefulness. By including multiple absorbers multi-color and broadband devices are realizable.

Two color detector leveraging resonant cavity enhancement for performance improvement


This present invention relates to an ice fishing hole cover. The cover features a hinged door attached to the cover through mechanical attachments. The ice fishing hole cover includes a fishing line hole to allow a user to setup a fishing bait line through the cover. The hinged door enables the user to open a portion of the cover, and not the entire cover, to set up the fishing bait line or to access and land a fish caught while ice fishing. The ice fishing hole cover enhances the overall ice fishing experience of the users and eliminates the inconvenience of maintaining an open ice hole while fishing.

By way of background, ice fishing sport is popular in northern Europe, North America, and other regions that have seasonal frigid temperatures. Ice fishing is a practice which involves catching fish with fishing lines and hooks or spears, through an opening in the ice on a frozen body of water. Ice fishing can be enjoyed individually or in groups. Usually, a person digs a hole through the frozen water surface over a designated fishing spot, until the underwater is visible, and then sets up a line to catch fish. However, after digging the initial hole, a layer of snow or ice frequently forms over the fishing hole, which blocks the access underwater to perform ice fishing.
Ice fishers and others have been using various solutions to keep ice fishing holes from constantly freezing over. One of the easiest solutions is through the use of a plastic or steel scooper for scooping out the newly formed ice from the hole when the water starts freezing. However, it only works when the ice cover is still forming or a mushy ice layer is formed. Additionally, the individuals have to constantly check the hole and be close to the fishing hole, to prevent the hole from freezing completely. In situations where the hole freezes completely, it can become extremely difficult to scoop out the ice from the frozen hole.
Some ice fishers choose to carry a heater, which not only provides warmth during colder periods, but also keeps the fishing hole from freezing. Additionally, individuals may use the heater to boil lake water or shaved ice, and then pour the boiled water over the fishing holes frequently, to prevent the holes from freezing. However, the complete process of collecting lake water or shaved ice, heating it, and pouring the boiled water over the fishing holes is a tiresome process, causing individuals to get easily frustrated.
Devices such as ice fishing hole covers are also available in the market and can be set up over an ice fishing hole to prevent ice holes from freezing over again and again. A fishing line can be set through a central hole of the ice fishing hole cover to perform ice fishing. These ice hole covers provide insulation to the hole therebelow and prevent its exposure to the freezing environment, and in this manner prevent the ice holes from freezing over. However, when a fish is caught and is to be taken out, the complete ice fishing hole cover needs to be taken out, and then set up again. This can be a frustrating job, particularly when the user needs to frequently repeat the aforementioned process to access the caught fish.
Therefore, there exists a long felt need in the art for an ice fishing hole cover that prevents the ice fishing hole from freezing over, and that does not require an individual to constantly monitor the ice fishing hole to scoop out the mushy ice layer over it. Additionally, there is a long felt need in the art for an ice fishing hole cover that eliminates the need to carry heaters to boil lake water and pour it over the ice hole to prevent the same from freezing, and that minimizes the individual's exposure to the environment and allows the individual to fish hassle-free. Furthermore, there is a long felt need in the art for an ice fishing hole cover that does not require the individual to completely remove the cover to access any fish caught therethrough, and that eliminates the need to constantly drill out new holes in the ice to catch fish. Finally, there is a long felt need in the art for an ice fishing hole cover that is relatively inexpensive to manufacture and that is both safe and easy to use.
The subject matter disclosed and claimed herein, in one embodiment thereof, comprises a magnetic ice fishing hole cover for effectively protecting an ice fishing hole from freezing. The magnetic ice fishing hole cover covers the ice hole while fishing. The magnetic ice fishing hole cover further comprises: a generally circular cover made of polycarbonate or similar plastic having a top surface, a bottom surface, a magnetic hinged door; a central circular fishing hole to receive a fishing line therethrough; the magnetic hinged door is configured as a cut-out in the cover body and is hinged along an edge on the cover and includes a magnetic edge which is attached longitudinally to a magnetic attachment; the magnetic attachment is permanently fastened to the cover; and, the door swings along the hinged edge in an upward direction to create an opening to access the central circular fishing hole. The cover provides insulation and protects the ice fishing hole from freezing.
In this manner, the novel magnetic ice fishing hole cover of the present invention accomplishes all of the forgoing objectives and provides a relatively efficient and convenient solution to keep the ice fishing holes from freezing in a frigid environment. The magnetic ice fishing hole cover of the present invention comprises a hinged cover portion which allows the user to open a part of the cover and does not require the removal of the complete ice hole cover set up, in order to access fish caught while ice fishing. Additionally, the magnetic ice fishing hole cover is user-friendly, as it eliminates the need to constantly monitor the holes to scoop out newly formed ice layers or constantly drill out new holes in the ice to continue fishing.


An apparatus comprises a storage system having storage devices and an associated storage controller. In conjunction with initiation of a checkpoint, the storage controller sets a checkpoint started flag for the checkpoint, marks user data pages and metadata pages for write operations already entered in a write journal of the storage system as of the setting of the checkpoint started flag as checkpoint pages, and marks user data pages and metadata pages for new write operations entered in the write journal after the setting of the checkpoint started flag as non-checkpoint pages by altering information used to generate signatures for respective ones of the metadata pages. Metadata pages characterizing the same user data pages subject to write operations at different times thereby have different signatures depending on whether or not the checkpoint started flag was set when its corresponding write operation was entered in the write journal.

Storage systems are often configured to generate periodic checkpoints in order to capture the state of the system at corresponding points in time. Such a checkpointing arrangement allows the system state to be recovered from a previously-captured checkpoint in the event of a storage device failure or other issue arising at a later point in time. However, conventional checkpointing arrangements can be problematic, particularly in non-atomic persistent storage environments such as may be associated with a content addressable storage system comprising an all-flash storage array. For example, some conventional arrangements require that write operations of a given user in a content addressable storage system be interrupted while a checkpoint is generated for that user. Arrangements of this type are inefficient and have a significant adverse impact on the performance of the storage system.

Checkpointing of user data and metadata in a non-atomic persistent storage environment


A support apparatus in which a distribution of a load for a user can be designated. The load occurs at body parts of the user by a stand-up motion. A processor calculates a projection position of a center of gravity of the user onto a floor, calculates a region of the floor where the projection position is to be included at the stand-up motion, calculates a target position in the region based on the distribution, and calculates a direction from the projection position to the target position. The target position is nearer to one body part of the user to which a larger load distribution is designated than on other body parts to which a smaller load distribution is designated. A designation direction for the user to bend the body in advance of the stand-up motion is output based on the direction.

For example, when an aged person stands up from a chair where he/she was seated, an apparatus for supporting his/her stand-up motion is proposed. In this apparatus, the stand-up motion is stably supported while the aged person's physical burden is reduced. However, if a person is not using his/her muscle strength for a long time, it is well known that the muscle strength of this part is quickly fallen. Namely, for a person having some remaining physical ability to stand up, over-support by this apparatus will make the person's muscle strength be fallen.

Apparatus and method for calculating pressure distribution


Some embodiments and aspects presented herein provide methods and apparatus for vaporizing and/or mixing medication with air or other gases for oral delivery to a patient. Some methods and apparatus may include breaking liquid medications down to particle sizes no larger than about 1.0 to 3.0 micrometers in diameter. Such small particle diameters can be introduced directly to a patient's bloodstream via the lungs by crossing the alveoli membranes.

Many types of devices have been developed over the years for the purpose of converting liquids or aerosols into gas-phase fluids. Some such devices have been developed, for example, to discharge small droplets from an inhaler-type medicinal administration apparatus.
Typical inhalers include a pressurized canister with measured doses of medication inside. Squeezing the top of the canister converts liquid medication into an inhalable mist. Inhalers enable children and adults to deliver medicine directly to their lungs. Typical aerosol inhalers usually comprise a diverging nozzle at an outlet to the pressurized liquid, which tends to vaporize the liquid medicine to a droplet volume median diameter on the order of 50 μm.
50 μm particles produced by typical inhalers can effectively treat certain lung ailments. For example, bronchodilators such as albuterol treat acute asthma by causing the lung passages to open or dilate. Similarly, nebulizers typically vaporize liquid medications to a droplet volume median diameter on the order of 50 μm. However, in addition to direct lung treatments, applicant notes that liquid medicinal drugs could also be delivered directly to the bloodstream through the lungs.
The lungs include groups of tiny air sacs called alveoli. The alveoli have very thin walls or membranes, and small blood vessels called capillaries run through these membranes. Oxygen molecules are small enough to pass through the membranes and into the blood in the capillaries. Other particles having diameters of approximately 1 to 3 μm or smaller may also pass through the alveoli membranes and directly into the blood stream. Nevertheless, there are currently no efficient methods of reducing liquids to particle sizes small enough to pass through the alveoli membranes.
In addition, typical aerosol inhalers produce a wide range of particle droplet sizes, and much of the metered medication tends to simply impinge the mouth or the back of the throat of a user. Consequently, sometimes only a fraction of the medication is deeply inhaled.

Medical liquid processor apparatus and method


Implementations generally relate to communication between a lens assembly and a camera. In some implementations, a method includes establishing electronic communication between a lens assembly and a camera, wherein the lens assembly is removably attached to the camera. The method further includes exchanging capability information between the lens assembly and the camera, wherein the capability information includes one or more functional features. The method further includes matching one or more of the functional features that both the lens assembly has and that the camera has. The method further includes enabling the lens assembly and the camera to cooperate in providing functional features based at least in part on the matching of one or more of the functional features.

Digital cameras capture and record images using digital technology, which enables users to edit photographs and easily share photographs. A digital camera may have an integrated camera lens, which enables the camera to closely control the operations of the lens. Some digital cameras can be used with an interchangeable lens system, which does not have the same degree of control as with an integrated lens.

Wireless communication between a lens assembly and a camera