The disclosure is for a method and apparatus for constructing a concrete wall with a single pouring of concrete. The mold for the pouring of the wall is formed essentially of plastic foam insulation which remains attached to the finished wall to serve as thermal insulation. The wall structure is therefore self jigging and requires no elaborate mold structure or any time or labor to remove the finished wall from the mold.

This invention deals generally with building construction and more specifically with the construction of concrete prefabricated walls.
The traditional methods of constructing building basements are well established. For commercial structures and for high volume residential developments with identical dimensions for each building, poured concrete is used. This involves the construction of forms, either wood or metal, in the exact shape of the vertical basement walls, and then pouring concrete into the forms. After the concrete hardens, the forms are removed and construction continues on the rest of the building.
The cost of forms limits this method to structures where the height requires the strength of reinforced concrete or where the reuse of forms for many identical structures in the same general area permits sharing of the costs of form construction by many buildings.
The more common basement construction technique for individual residential houses is the straight forward construction of the vertical walls by laying many courses of cinder block, one on top of the other. This method is the traditional one used for isolated building sites and small developments, and it is both time consuming and labor intensive. It requires each cinder block to be individually placed and surrounded with mortar. One need only watch a traditional house being built to realize that the cinder block basement may take over a week to construct on a typical site, while the framing and exterior walls go up in just a day or so. Above ground walls of wood and sheathing have been prefabricated for over fifty years, but prefabrication of concrete walls has only started recently.
U.S. Pat. No. 4,605,529, issued Aug. 12, 1986 to Melvin M. Zimmerman, the present inventor, discloses a prefabricated concrete wall structure and the method and assembly jig for the wall""s construction. The method disclosed permits construction of a wall which is no longer linked to the amount of manpower available at the construction site, because the labor at the construction site involves only installation of the previously manufactured wall. Moreover, the cost of the wall is relatively unrelated to the size of the wall.
However, the cost of such a prefabricated wall is greatly influenced by the ease of its off-site manufacture, and to facilitate construction the wall is constructed within a horizontal assembly jig, so that conventional concrete delivery trucks can be used as a source of material.
The assembly jig of the prior art is essentially a set of channel members oriented in a horizontal plane. The channels are arranged in parallel, about eight feet apart, and the channels include precut notches on their innermost walls. These notches are used to support previously manufactured concrete studs which are set in the horizontal plane perpendicular to the parallel channels. A typical spacing for the notches is two feet center to center.
The channel members and frame sides joining the ends of the channel members are constructed so that the peripheral edges of the grid formed by the studs and the channels, that is, the edges forming an outside rectangle, are higher than all the other members by approximately four inches to form a frame around the entire structure. The parallel channel members which form the support for the concrete studs include cavities of considerable volume which are eventually filled with concrete to encase the ends of the concrete studs which are set into the notches in the channels with the ends of the studs extending into the cavities.
Before concrete is poured into the assembly jig, sheet insulation is laid over the concrete studs and impaled upon fasteners cast into and protruding from the concrete studs, and wire reinforcing mesh is laid atop the sheet insulation, but the sheet insulation is sized so that it does not cover the cavities of the channel members.
The wall is then completed by pouring concrete into the jig so that it covers the insulation, the fasteners protruding through the insulation, and the wire mesh, and fills the cavities in the channel members. The concrete is poured to the height of the top of the outer frame members, and once hardened, not only forms an integral exterior surface, but also bonds together the studs, the insulation, and the top and bottom support beams which are formed in the channel members.
The prior art describes the final step of manufacture of the wall as lifting the hardened concrete wall from the assembly jig by jacking one edge of the wall out of the assembly jig, and then attaching lifting aids, such as eyebolts, to holes cast in the upper or lower concrete beams.
However, the task of removing the finished wall from the assembly jig disclosed in the prior art is much more difficult than one might suppose. There is a significant tendency for the wall to adhere to the jig and lock up within it. For example, concrete may leak through the edges of the notches cut in the channel members to support the studs, and such concrete, once hardened, prevents removal of the wall from the assembly jig.
Moreover, even slight irregularities in the sidewalls of the channel members also tend to lock the wall into the assembly jig. For instance, if a dent exists in the sidewall of a channel member, that dent will, depending upon the direction in which it protrudes, either be filled with or surrounded by hardened concrete. Under such circumstances, it is impossible to pull out the concrete beam formed within the channel member without chipping, or at least scoring, the concrete beam. Furthermore, even if the damage to the prefabricated concrete wall can be tolerated, the rigid channel members of the assembly jig of the prior art require much more force, more powerful equipment, and more disassembly time than is desirable to remove the finished wall from the assembly jig.
The present invention completely eliminates the problems associated with casting a prefabricated concrete wall using a reusable assembly jig. Use of the present invention permits the entire wall, including the concrete studs, to be formed with a single pouring of concrete. Moreover, the entire mold for the wall is formed of insulating foam which remains attached to the wall, so that the requirement of breaking the finished wall loose from an assembly jig is completely eliminated. When the concrete hardens, the entire assembly, including the attached foam which will serve as thermal insulation for the finished wall, is simply moved into storage or onto a truck.
A further advantage of the present invention is that, unlike prior art prefabricated concrete walls, the wall of the present invention has insulation completely covering the inside surfaces of the wall, including the surfaces of the concrete studs.
However, the most important advantage of the invention is the simplicity of the construction. No concrete studs need to be separately produced or moved to and set into an assembly jig before the concrete is poured, and top and bottom beams need not be used because reinforcing bars are cast into the face of the concrete wall to furnish strength at the top and bottom of the wall. The entire wall is formed in a single concrete pouring, and the simple, inexpensive insulation foam assembly jig becomes an integral part of the finished wall. This reduces both the time for and cost of producing the wall.
The single use assembly mold is formed on a horizontal surface using simple planar slabs of insulation foam. To create each stud form, a xe2x80x9cUxe2x80x9d shaped metal channel is set upon a flat horizontal surface with the open channel oriented upward. Two vertical slabs of insulation foam are then placed within the metal channel, separated by a beam of insulation foam at the bottom of the channel which holds the vertical slabs against the insides of the legs of the metal channel. In the preferred embodiment, the upper edges of the channel legs are bent slightly inward so that the edges actually dig into the slabs of foam which are forced against them. The foam slabs and foam beam are sized to extend for the entire dimension of what will later be the height of the wall, and the heights of the vertical slabs are chosen to match the dimension of the future depth of the stud. Thus, the bottom foam beam and the two vertical slabs of foam form a cavity which determines the size of the wall stud.
The tops of the vertical slabs of foam insulation are also used to support large sheets of insulation which determine the surface area of the finished wall. The sheets are supported between two stud cavities by forming ridges in the edges of either the sheets or the vertical cavity slabs, so that they interlock. Regardless of which part has a ridge cut into it, the interlocking fit prevents the tops of the stud cavity""s vertical slabs from separating when concrete is poured into the cavity""s insulation mold.
By using two insulating slabs and a insulating bottom beam to form each stud cavity and foam sheets to span the spaces between the stud cavities, an entire wall mold is formed except for the end configurations. The parts of the wall which are at the ends of the stud cavities are closed off by a channel shaped metal sill plate. This plate is held in place by screws driven through the sill plates side legs and into the metal channels on each stud cavity and into the insulation sheets atop the stud cavities. All that is then required is another foam end sheet covering the sections of the wall at the ends of the stud cavities, and such end sheets are easily attached by the use of screws driven through the end sheets into the edges of the insulation sheets and the insulation slabs.
The beauty of the simple insulation foam construction of the wall mold is that the foam is desirable to insulate the concrete wall, and once the concrete is poured and hardened there is no mold from which the concrete wall must be removed. The entire assembly, including the concrete and the insulation, is the finished product, which is a unitized concrete wall with the inside surfaces fully covered with insulation, and the metal channels are xe2x80x9cnailerxe2x80x9d strips which serve as lath to which interior finishing material can be attached to each stud.
Thus the present invention furnishes a prefabricated concrete wall and the process for constructing it which result in faster construction and better insulated walls.

Self jigging concrete wall structure and method of construction


A method and apparatus for generating and displaying points along a centerline curve and right and left offset curves of a freeform stroke, wherein the distances from the centerline curve to the right and left offset curves vary in the same parameter as the horizontal and vertical coordinates of the centerline curve. Preferably, the centerline curve is a spline curve and the points along the centerline curve are generated using a subdivision technique in accordance with predetermined termination criteria.

1. Field of the Invention
The present invention relates to a method and apparatus for generating and displaying freeform strokes and, more specifically, to a method and apparatus for generating and displaying points along a centerline curve and right and left offset curves of a freeform stroke, wherein the width of the centerline curve varies in the same parameter as the horizontal and vertical coordinates of the centerline curve.
2. Description of the Related Art
Freeform curves have useful applications in, for example, computer aided design and manufacturing systems, computer graphics, graphic arts, and typesetting for creating both uniform and variable-width curves. Furthermore, various methods and apparatus exist for presenting graphical representations of such freeform curves. For example, U.S. Pat. No. 4,933,889 issued to Meshkat et al. discloses a method for generating finite elements for representing the shape of an object.
In particular, spline curves have been studied extensively, and are in general use in computer graphics (see generally, Bartels, R. H. et al., An Introduction to Splines for Use in Computer Graphics and Geometric Modeling, Morgan Kauffman Publishers, Los Altos, Calif., 1987; Farin, G., Curves and Surfaces for Computer Aided Geometric Design, Academic Press, San Diego, Calif., 1988).
Spline curves have also been used in computer graphics to generate and display freeform strokes of both constant and varying width in addition to curves, which have no width. For example, Chua, Y. S., Bezier Brushstrokes, Computer-Aided Design, Butterworth-Heinemann, Vol. 22, No. 9 (November 1990), pp. 550-55, 604 ("the Chua article"), discloses a technique for using Bezier curves to mathematically model brushstrokes. The Chua article teaches using Bezier functions to model various attributes of a brushstroke, e.g., variations of shape or outline of the brushstroke, shade or color variation along and across the brushstroke, and some effects due to the variation of moisture content of the brush as well as paper characteristics. The Chua article defines a brushstroke by at least one brush segment, the shape (or outline) of which is modeled with two cubic Bezier curves (called "Bezier segments"). Each Bezier segment is associated with a parameter u, called the "parameter along the brush segment," with u=0 at the beginnings of the segments and u=1 at the ends of the segments. The shape of a general brushstroke can be modeled using one or more brush segments.
As another example, U.S. Pat. No. 4,912,659 issued to Liang et al. discloses a pipeline and parallel processing system for generating surface patches for both wireframe and solid/shaded models in a raster graphics display, wherein the inputs to a transformation processor are the parameters for a rational Bezier surface.
Offset curves have also received considerable attention, primarily in the CAD community (see generally, Farin, G., Curvature Continuity and Offsets for Piecewise Conics, TOG 8, 2 (April 1989), pp. 89-99; Farouki, R., and Neff, C., Algebraic Properties of Plane Offset Curves, CAGD, p. 297-299; Farouki, R., and Neff, C., Analytic Properties of Plane Offset Curves, CAGD, pp 297-299; Hoschek, J., Spline Approximation of Offset Curves, CAGD 5 (1988), pp. 33-40; Klass, R., An Offset Spline Approximation for Plane Curves, CAD 15, 5 (September 1983), pp. 297-299). Various definitions of offset curves exist. The predominant definition, however, is one based on a centerline or "generator" curve with an offset a distance w defined along a unit normal to each point of the centerline curve. In the absence of a sign convention for the unit normal, an offset curve is defined on both sides of the centerline curve. Generally, the term "left offset curve" designates the offset curve based upon a unit normal given by a positive sign, while the term "right offset curve" designates the offset curve based upon a unit normal by the negative sign. Further, the term "offset curve" is used to refer to one or the other of the left and right offset curves, while the term "offset curve pair" indicates both the left and right offset curves.
While the increased generality of offset curves makes them a more powerful means of expressing curves and surfaces as compared to other conventional techniques, their use has generally been restricted to applications for which they are natural. For example, offset surfaces are used to describe tolerance zones (see, e.g., Hoschek, J., Spline Approximation of Offset Curves, CAGD 5 (1988), pp. 33-40), outside surfaces of materials for which the inner surface is the reference (see, e.g., Hoschek, J., Spline Approximation of Offset Curves, CAGD 5 (1988), pp. 33-40; Klass, R., An Offset Spline Approximation for Plane Curves, CAD 15, 5 (September 1983), pp. 297-299), and machine-tool paths (see, e.g., Farouki, R., and Neff, C., Analytic Properties of Plane Offset Curves, CAGD, pp. 297-299).
The majority of applications of offset curves are motivated by physical problems involving constant width offset curves. Because constant width offset curves of spline curves are not spline curves (they are generally non-algebraic), most attention has been given to the efficient approximation of offsets with algebraic (usually rational or non-rational spline) curves. More generally, however, offset curves may have variable widths.
For example, U.S. Pat. No. 4,620,287 issued to Yam ("Yam") discloses a method and apparatus for representing uniform width curves, i.e., strokes having uniform widths. In particular, Yam discloses a technique wherein a curve is approximated by a series of Bezier curves. Each Bezier curve is provided with a predetermined width defined by a corresponding rectangle having the predetermined width. The ends of each of the rectangles are smoothed and rounded so that adjacent rectangles approximate a curve having a constant width.
As another example, Pham, B., Expressive Brushstrokes, CVGIP: Graphical Models and Image Processing, Vol. 53, No. 1 (January 1991), pp. 1-6 ("the Pham article"), discloses a technique for modeling brush strokes based on variable offset approximations of uniform cubic B-splines. An operator specifies a set of points, or knots, on a curve representing a brush stroke. Using an inversion algorithm, control vertices of a cubic B-spline are obtained to construct a cubic B-spline through the knots. Next, given an offset distance for each of the knots of the original curve, corresponding offset knots are obtained. The offset distances are measured from the corresponding knot of the original curve in a direction normal to the curve. Finally, using the inversion algorithm, offset control vertices are obtained from the offset knots to construct an offset cubic B-spline curve through the offset knots.

Method and apparatus for generating and displaying freeform strokes


Methods for detecting IL-16 biological activity, detecting modulation of IL-16 biological activity, and diagnosing the presence of or susceptibility of a subject to an IL-16-related disorder involve measuring and comparing the levels of RANTES proxy produced by eukaryotic cells, such as CD4+ and CD9+ cell lines, peripheral blood mononuclear cells, HuT-78 cells, and/or THP-1 cells.

Interleukin-16 (IL-16; SEQ ID NO: 3) is a pro-inflammatory cytokine that induces positive chemotaxis of T-lymphocytes, monocytes, eosinophils, and dendritic cells (67 J. Leukocyte Biol. 757 (2000)). IL-16 stimulus also increases IL-1b expression, increases IL-6 expression, and increases IL-15 expression in IL-16 responsive eukaryotic cells (67 J. Leukocyte Biol. 757 (2000)).
IL-16 peptide chain monomers are formed by the caspase-3 mediated proteolytic processing of a larger 14 kDa precursor molecule (273 J. Biol. Chem. 1144 (1998)). IL-16 monomers form tetrameric peptide chain complexes. These tetrameric IL-16 complexes are believed to be the bioactive form of IL-16 (67 J. Leukocyte Biol. 757 (2000)). Eukaryotic cells that produce IL-16 include cells that express CD4 or CD8, such as T-cells, mast cells, eosinophils, dendritic cells epithelial cells, fibroblasts, and cells of the cerebellum (67 J. Leukocyte Biol. 757 (2000)). Eukaryotic cells responsive to IL-16 express the CD4 and CD9 peptide chains, but the response to IL-16 may also be independent of these peptide chains (see e.g. 164 J. Immunol. 4429 (2000)).
IL-16 has been reported to play an important role in such diseases as asthma, atopic dermatitis, and rheumatoid arthritis, among others (see e.g. 162 Am. J. Respir. Crit. Care Med. 105 (2000); 109 J. Allergy Clin. Immunol. 681 (2002); 31 J. Rheumatol. 35 (2004). For example, in human patients IL-16 has been shown to be responsible for attracting asthma inducing cells to the lungs and to play a critical role in triggering asthmatic responses in patients (162 Am. J. Respir. Crit. Care Med. 105 (2000)). Clearly, the ability to detect and identify molecules that activate or inhibit IL-16 is critical to the development of effective treatments for IL-16 mediate diseases.
Thus, a need exists for novel methods for detecting IL-16 biological activity, activators of IL-16 biological activity, and inhibitors of IL-16 biological activity.

Method for detecting IL-16 activity and modulation of IL-16 activity based on rantes proxy protein levels


There is provided a MISFET which suppresses a short-channel effect in a deep submicron region and has a low parasitic resistance, a low parasitic capacitance, and a small drain junction leakage current. A shallow concave is formed in a channel forming portion and an extension region forming portion of a MISFET, shallow ion implantation for forming an extension region is performed to a bottom surface of the shallow concave. Deep ion implantation for forming a source/drain region is performed to a silicon substrate adjacent to the concave, and the position of a peak concentration of the shallow ion implantation is caused to coincide with the position of a peak concentration of the deep ion implantation, so that a MISFET which suppresses a short-channel effect and has a low source/drain parasitic resistance, a low source/drain parasitic capacitance, and a small drain junction leakage current generated by SALICIDE steps can be provided. The MISFET according to the invention is preferably used as a means for providing a semiconductor substrate constituted by a high-speed CMOS circuit having a high integration level at a high yield and high reliability.

The present invention relates to the structure of a semiconductor device and a method of manufacturing the same and, more particularly, to an element structure of a Metal Insulator-Semiconductor Field Effect Transistor (to be referred to as a MISFET hereinafter) which is excellent in a high-speed operation and a method of manufacturing the same.
As conventional semiconductor devices using MISFETs, memory devices such as dynamic RAMS or static RAMS formed on silicon substrates, processors using CMOS logic circuits, and the like are mass-produced.
In order to improve the integration density or performance of such a semiconductor device, miniaturization of a MISFET serving as a component is a necessary condition, and development of miniaturization technique and necessity of a short-channel effect and parasitic resistance suppression of the MISFET increase together with transition of generation of a semiconductor device.
As a method of suppressing a short-channel effect, for example, a Lightly Doped Drain structure (to be referred to as an LDD structure hereinafter) shown in FIG. 1 is known. In a MISFET having the LDD structure, a polysilicon gate 4 is formed on a semiconductor substrate through a gate oxide film 3, and ion implantation is performed by using the polysilicon gate 4 as a mask, so that shallow impurity diffusion layers 5 are formed on both the sides of the polysilicon gate 4 to be adjacent to a channel region formed at the gate electrode 4. In addition, gate sidewall spacers 6 are formed on the source/drain sides of the polysilicon gate 4, and ion implantation is performed by using the gate sidewall spacers 6 and the polysilicon gate 4 as masks, so that deep impurity diffusion layers are formed.
Since the impurity diffusion layers are used as source/drain regions 7 for supplying a drive current of a MISFET, voltage drop is increased by the resistances in the impurity diffusion layers. For this reason, the impurity concentration of this portion must be as high as possible. In order to form a diffusion layer having a high impurity concentration by ion implantation, an amount of implanted impurity per unit area (to be referred to a dose amount hereinafter) must be increased, and an acceleration voltage of ion implantation must be increased.
When the acceleration voltage of impurity ions is increased, the depth of ion implantation increased. For this reason, deep impurity diffusion layers are generally formed in the source/drain regions 7. When a gate length decreases with miniaturization of the MISFET, the decrease in distance between the source/drain regions adversely affects the threshold voltage of the MISFET and considerably degrades cut-off characteristics of the MISFET.
In order to activate the ion-implanted impurity, a high-temperature heat treatment must be performed. However, at this time, since the impurity is also laterally diffused, the distance between the source/drain regions in which the impurity is deeply implanted more decreases, and it is difficult to suppress the off-leakage current. The changes in characteristics with miniaturization of the MISFET are generally called a short-channel effect.
In order to reduce the short-channel effect in the LDD structure, shallow diffusion layers are formed to be adjacent to both the sides of the polysilicon gate 4, and the off-leakage current is suppressed such that the distance between the deep diffused layers of the source/drain regions 7 is as large as possible even if the length of the polysilicon gate 4 decreases. Shallow diffusion layers 5 shown in FIG. 1 are called source/drain extension regions.
In order to reduce the resistances of the source/drain regions 7 and the resistance of the polysilicon gate 4, as shown in FIG. 1, a low-resistance layer constituted by a silicide of high melting point metal 8 is formed on the source/drain regions 7 and the polysilicon gate 4. Since the silicide of high melting point metal 8 is formed in a self-aligned manner, the structure of the high-speed MISFET is called as a SALICIDE (abbreviation of self-aligned silicide) structure.
In order to improve the performance of the MISFET in a deep submicron region, a gate length must be decreased, and the dimension of depth must also be scaled down in proportion. Therefore, when the short-channel effect is to be reduced in the LDD structure, the shallow extension regions 5 must be formed, and at the same time, the source/drain regions 7 must be made shallow. However, since in general, high impurity concentration layer can not be made shallow, the shallowness of the ion implantation is limited to a predetermined level.
In the SALICIDE structure, as indicated by a broken-line circle in FIG. 1, the junction of the extension region 5 becomes close to the end portion of the silicide layer 8 on the drain side, and the formation of the silicide layer 8 on the drain region tend to cause increase a leakage current of a drain junction. The increase in leakage current especially poses a problems at the drain junction to which a large voltage is applied in operation of the MISFET. When an integrated circuit having a high integration level is constituted by CMOS circuits of low power dissipation, it is a necessary condition to remove the leakage current of constituent MISFETs.
In order to avoid the problem of the above LDD structure, an elevated source/drain structure shown in FIG. 2 is proposed. In this structure, silicon epitaxial layers 51 are grown on source/drain regions, and ions are implanted into source/drain diffusion layers by using gate sidewall spacers 6 and a polysilicon gate 4 as masks. At this time, since the ion implantation is performed through silicon epitaxial layers 51, the depth of the source/drain regions 7 from the interface of epitaxial layer and silicon substrate 1 is small to suppress a short-channel effect.
However, in the elevated source/drain structure, selective epitaxial growth of silicon at a high temperature of 800° C. or higher is additionally performed, and the number of processing steps increases. At the same time, extra diffusion of impurity implanted in a channel region for threshold voltage control and in the extension regions is advanced. Therefore, this technique cannot always obtain a preferable result as a production technique for a deep submicron region.
Therefore, a means for realizing the structure of a new MISFET having the same advantages as those of an elevated source/drain structure without high-temperature heat treatment processing is strongly demanded.
As shown in FIG. 2, in the elevated source/drain structure, when the silicon epitaxial layers 51 are formed on a silicon substrate leaving (100) surface, (311) facets are easily generated opposite to the polysilicon gate 4, and parasitic capacitance is formed between the silicide layer 8 and the polysilicon gate 4. The gate-drain parasitic capacitance disadvantageously degrades the high frequency performance. Here, the facet indicates a small crystal surface having a special crystal orientation.
As another structure for suppressing a short-channel effect, a UMOS structure (to be described below) is known. That is, as shown in FIG. 3, a U-shaped deep trench is formed in a semiconductor substrate 1, source/drain regions 62 and extension regions 61 are formed on the surface of the silicon substrate.
In this UMOS structure, a channel region and a gate insulating film 3 are formed on the inner surface of a deep trench, and a gate electrode 63 is formed to bury the trench. Since source/drain regions 7 have no surfaces which are opposed to each other inside the semiconductor substrate 1 in the structure, the structure is excellent to avoid a short-channel effect. However, since the gate electrode 63 is adjacent to the source/drain regions 62 through the thin gate insulating film 3, a large gate/drain parasitic capacitance is formed to disadvantageously degrade the high frequency performance of the MISFET.
As described above, in a conventional MISFET in a deep submicron region, when the source/drain regions are to be made shallow to suppress the short-channel effect, a high-concentration impurity diffusion layer required to reduce a series resistance cannot be obtained. In addition, the source/drain regions are to be made effectively shallow by using the elevated source/drain structure, high-temperature heat treatment processing such as a silicon epitaxial processing step is required, and a gate-drain parasitic capacitance is excessively large in the UMOS structure to disadvantageously degrade the high frequency performance.

Semiconductor device and method of manufacturing the same


A pre-equipped shielded harness has at least one end portion formed of a bundle of twisted-together conductors covered by a shielding braid. The harness includes an expander having cross-sectional dimensions substantially identical to those of a rear of a connector to be connected to the end portion. The expander is positioned at the location at which the connector is to be connected, and is covered by the shielding braid by preforming the shielding braid over the expander. The shielded harness has high magnetic protection.

Such a shielded harness has a defined layout, in which it comprises a linear cord of conductors, or a network made up of conductors and having multiple branches, and end connectors for connecting the harness to the various connection points.
For certain applications, it is impossible or not desirable to equip the shielded harnesses with all or some of their connectors before the harnesses are laid. This is particularly true when the harness passes through a wall, through which a passage cannot be provided that is large enough for the connector, since the diameter of the connector is generally larger than the diameter of the cord or of the branch of the network to which it is normally connected. This may also be true when the connectors are relatively fragile and may be damaged by handling while the harness is being transported or laid.
In known manner, a linear cord, and in particular the linear portions of a network may be shielded against electromagnetic interference by means of metal shielding braids. The rear connection portions of the connectors via which the connectors are connected to the cord or to the network must in turn be protected by shielding. Such protection may be obtained by handling the end of the shielding braid of the cord or of the branch of the network roughly so that the shielding braid can be threaded onto the rear portion of the connector.
Such rough handling degrades the shape of the braid. Although such rough handling is acceptable for harnesses subject to low electromagnetic stresses, it is not acceptable for harnesses subject to high electromagnetic stresses.
Also in known manner, the low performance levels obtained by braiding the shielding braid onto the rear portion of the connector can be improved by mounting a heat-shrinkable sheath over the rear portion of the connector and over the end of the braid. The heat-shrinkable sheath is there to provide sealing on top of the shielding braid, but in practice, it is uncommon to obtain a sheath that shrinks enough and that offers almost perfect sealing when there is a large difference between the diameter of the connector and the diameter of the cord or of the branch to which the connector is connected. Furthermore, installing the sheath is not always easy, in particular when the connector is already connected, given that the sheath is installed after the harness has been laid.
An object of the present invention is to connect a connector to one end of a harness that is already shielded, while avoiding the above-mentioned drawbacks, and enabling in particular the connector to be mounted easily and quickly, with high electromagnetic protection at the connector, and without the shielding of the end portion of the harness that is connected to the connector being degraded.
The invention further advantageously enables a faulty connector in place to be replaced by a new connector, under the above-mentioned conditions of mounting and of protection.

Shielded harness pre-equipped so that a connector can be mounted thereon


A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

The present invention relates to a semiconductor IC (Integrated Circuit) device having a memory integrated therein, and more particularly to a technique having the effective application thereof to a semiconductor IC device in which a memory having a plurality of data transmission lines such as data input/output lines (I/O lines) and a logic circuit are integrated on the same semiconductor chip.
In recent years, the progress of LSI's (Large Scale Integrated circuits) to high integration has been made so that it is being possible to integrate a large-capacity memory and a large-scale logic circuit or operation circuit on a semiconductor chip of about 1 cm square. In such chips, a very high speed equal to or higher than 1 G byte/sec can be attained as the rate of data transfer between the memory and the logic circuit or operation circuit by making the number of I/O lines of the memory equal to or greater than several hundreds. Therefore, such chips are expected to, for example, the use thereof for image processing or the like in which high-speed data transfer for a memory is required.
A first prior art applicable to such a purpose of use includes, for example, DRAM (Dynamic Random Access Memory) macros disclosed by Toshio Sunaga, et al., "DRAM Macros for ASIC Chips", IEEE JOURNAL OF S0LID-STATE CIRCUIT, Vol. 30, No. 9, September 1995, pp. 1006-1014. This reference has disclosed an LSI chip which includes the combination of a logic and a DRAM macro of 288 K-bit (32K.times.9 bits) capacity having 9 (nine) I/O lines fabricated by 0.8 .mu.m CMOS technique, and an LSI chip which includes the combination of a logic and a DRAM macro of 1.25 M-bit (64K.times.18 bits) capacity having 18 (eighteen) I/O lines fabricated by 0.5 .mu.m CMOS technique.
As a second relevant prior art, U.S. Pat. No. 5,371,896 (issued Dec. 6, 1994) has showed a system in which a parallel computing system having many processors and memories coupled to each other is integrated on the same semiconductor chip. In this second prior art, a plurality of memories and a plurality of processors are integrated on the same semiconductor chip, and the memories and the processors are coupled by a network including crossbar switches. The second prior art is characterized in that an SIMD (Single Instruction Multi Data Stream) operation and an MIMD (Multi Instruction Multi Data Stream) operation can be performed in a changing-over manner, as required. At the time of SIMD operation, one of the plurality of memories is used as an instruction memory and the remaining memories are used as data memories. An instruction from the instruction memory is given to the processors in common with each other. At the time of MIMD operation, a part of the memories used as the data memories at the time of SIMD operation are used as instruction memories so that instructions from the separate instruction memories are given to the individual processors. Data transfer paths between the individual memories and the processors can be changed over to each other in various ways by the crossbar network.

Semiconductor IC device having a memory and a logic circuit implemented with a single chip


Apparatus, and an associated method, for demonstrating a capability of a mobile station. A demonstration mode is defined at the mobile station. A user of the mobile station selects operation of the mobile station in the demonstration mode and which of the mobile station capabilities to be demonstrated.

Advancements in communication technologies have permitted the development and deployment of many new types of communication devices usable by which to effectuate many different types of communication services.
In general, a communication service is effectuated by, or between, communication devices. The communication devices variously form sending stations that operate to send communication data and receiving stations that operate to receive communication data. Communication data sourced at, or otherwise provided to, a sending station is communicated to a receiving station by way of a communication channel.
Some communication devices operate both to send and to receive communication data, thereby to permit two-way communication of data between a set of communication devices. The communication devices are sometimes constructed to be operable to communicate communication data upon radio channels defined upon portions of the electromagnetic spectrum. A communication system in which the communication devices are interconnected by radio channels, thereby communicate by way of the radio channels, is referred to as a radio communication system.
A radio communication system advantageously provides for communications even when the communication devices operable therein can not be interconnected by way of wirelines upon which communication channels are defined. A wireline communication system, in contrast, requires that the communication devices operable therein be interconnected by way of wireline connections. Free of the need to interconnect the communication devices with such wireline connections, the communication devices of a radio communication system are positionable at locations between which wireline connections are unavailable. Additionally, free of the need to interconnect the communication devices with wireline connections, one, or more, of the communication devices between which data is communicated is permitted mobility, thereby permitting the radio communication system to form a mobile communication system.
A cellular communication system is exemplary of a mobile communication system. Network infrastructures of cellular communication systems of various constructions, i.e., constructed pursuant to various standard operational specifications, have been installed throughout significant portions of the populated areas of the world. Voice and data communication services are effectuable by way of cellular communication systems. Increasingly data-intensive communication services are permitted through use of new-generation cellular communication systems. Users communicate telephonically, typically through the use of portable communication devices that are sometimes referred to as mobile stations. A mobile station is a radio transceiver, capable of communicating with a communication entity of the network infrastructure of a cellular communication system in whose coverage area that the mobile station is positioned. A mobile station includes radio transceiver circuitry, i.e., forms both a receiving station and a sending station to permit two-way communications with the communication entity of the network infrastructure. A mobile station is typically of small dimensions to permit its hand carriage by a user.
In some aspects, a mobile station operable in a cellular communication system corresponds to a conventional telephonic handset and includes microphonic and speaker transducers and a telephonic keypad. A mobile station also typically includes a user display for displaying information in visual, or other human perceptible, form. The user displays of many mobile stations are formed of liquid crystal displays having multiple-color display capabilities and high pixel-density configurations.
Mobile stations are sometimes constructed to incorporate capabilities that provide advancements over earlier-constructed mobile stations and to provide user-interface, and other, capabilities that provide new or unique advantages through their use. The unique capabilities of a mobile station also sometimes provide manufacturers and sellers of the mobile station with marketing advantages. That is to say, selection for purchase or other use of a mobile station is sometimes, if not often times, made as a result of the unique capabilities of the mobile station.
However, particularly when the mobile-station capability is first provided at the start of a production cycle, the capability, although perhaps incorporated into the functionality of the mobile station, is not readily usable as the communication system in which the mobile station is to be operated fails to provide the functionality permitting the mobile-station capability to be evident to a user of the mobile station. Or, particularly with respect to pre-production models, the operability of the feature-providing part of the mobile station associated with the mobile-station capability is not fully working, that is, is not free of defects. The capability of the mobile station might again not be evident to a user or perspective purchaser if the capability-providing feature is not fully operational at the mobile station.
A mechanism by which to demonstrate a capability of a mobile station irrespective of whether the capability-producing feature of the mobile station is fully operational or whether the mobile station is positioned in a communication system that permits the capability to be evidenced would be beneficial.
It is in light of this background information related to mobile stations, or other radio devices, operable in a radio communication system that the significant improvements of the present invention have evolved.

Apparatus, and associated method, for demonstrating an operational capability of a radio device


An integrated mask including a plurality of deposition masks, each deposition mask having an array of deposition apertures formed in accordance with a deposition pattern; and a base plate having a plurality of openings on which the deposition masks are arranged is provided. The deposition mass are retained to the base plate by engaging unit in a disengageable manner, and alignment marks used for positioning the deposition masks on the base plate are formed on the base plate. In addition a method and apparatus for fabricating the integrated mask, a method and apparatus for manufacturing an organic EL device using the integrated mask, and an organic EL device are provided.

1. Technical Field
This disclosure relates to organic EL devices which are able to convert electrical energy into light, and which have various applications in devices such as display devices, flat panel displays, backlights, illuminations, interior decorations, signboards, electronic cameras, timepieces, etc. More specifically, it relates to an integrated mask in which a plurality of deposition masks used for manufacturing the organic EL devices are arranged, and to a method and apparatus for fabricating the integrated mask. In addition, the disclosure also relates to a method and apparatus for manufacturing an organic EL device using the integrated mask.
2. Description of the Related Art
In organic EL devices, light is emitted when electrons supplied from cathodes and holes supplied from anodes are recombined inside an organic layer disposed between the cathodes and the anodes. Organic EL devices are usually used in thin, compact displays because of their simple structure and ability to emit high-intensity, multicolored light at low voltage.
In order to manufacture a full-color display panel using an organic EL device, thin film layers including red, green, and blue (RGB) emitting layers, a first electrode layer (for example, ITO), a second electrode layer (for example, metal), etc., must be regularly formed in a predetermined pattern with a predetermined pitch.
In the above-described thin film layers, in order to form organic thin film layers, for example, emitting layers, in a precise pattern, a mask deposition method is normally applied from the viewpoint of the characteristics of the organic thin film layers. In the mask deposition method, a deposition process is performed in a vacuum using a mask having apertures formed in accordance with a predetermined pattern of the emitting layer.
In order to increase the productivity in manufacturing the organic EL devices, multiple organic EL devices are simultaneously formed on a single, large substrate. This is because a mask deposition used for forming emitting layers is performed in a batch-wise manner, substrate by substrate, and the existing organic EL devices are mainly used in compact apparatuses.
In the case in which multiple organic EL devices are simultaneously formed on a single, large substrate, a deposition mask having a plurality of arrays of apertures, each array corresponding to a single organic EL device, must be prepared. However, in such a case, the size of such a deposition mask is increased, and the deposition mask is greatly deformed in the manufacturing process and the deposition process. Thus, the high dimensional accuracy of the arrays of apertures cannot be maintained sufficiently. Accordingly, an integrated mask in which a plurality of deposition masks, each of which has an array of apertures corresponding to a single organic EL device, are arranged is disclosed in Japanese Unexamined Patent Application Publication No. 2000-113978.
Since three emitting layers corresponding to three colors (RGB) are formed, it is important to accurately adjust the relative positions between the three emitting t layers. Although a method for positioning a single deposition mask relative to a substrate has been suggested (the Japanese Unexamined Patent Application Publication No. 11-158605), a method for positioning an integrated mask relative to a substrate has not been provided. In addition, in an integrated mask, a plurality of deposition masks provided for simultaneously forming multiple organic EL devices must all be accurately positioned.
Accordingly, it could be helpful to have a construction for practically using an integrated mask in which a plurality of deposition masks, each of which has an array of apertures corresponding to an organic EL device, are arranged. In addition, it could be helpful to have a means for fabricating the integrated mask in such a manner that the deposition masks are accurately positioned in the integrated mask. In addition, it could further be helpful to have a method and apparatus for manufacturing an organic EL device by which the integrated mask and a substrate can be accurately positioned, multiple organic EL devices can be formed on a single substrate by a deposition process, and the productivity in manufacturing organic EL devices can be significantly increased. Furthermore, it could be helpful to have a high-quality, inexpensive organic EL device.

Integrated mask and method and apparatus for manufacturing organic EL device using the same


A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

1. Field of the Invention
The field of the invention generally relates to superscalar RISC microprocessors, more specifically, the invention relates to a CISC to RISC microprocessor instruction alignment unit and decode unit for permitting complex instructions to run on RISC-based hardware.
2. Related Art
All complex instruction set computers (CISC computers) which use variable length instructions are faced with the problem of determining the length of each instruction that is encountered in the instruction stream. Instructions are packed into memory as successive bytes of data, so that given the address of an instruction, it is possible to determine the starting address of the next instruction if you know the first instruction's length.
For a conventional processor, this length determination does not have a significant performance impact compared to other stages in the processing of an instruction stream, such as the actual execution of each instruction. As a result, fairly simple circuits are typically used. Superscalar reduced instruction set computers (RISC computers), on the other hand, can process instructions at a much higher rate, requiring instructions to be extracted from memory much more rapidly to keep up with the parallel execution of multiple instructions. This limiting factor imposed by the rate at which instructions can be extracted from memory is referred to as the Flynn Bottleneck.
The task of determining the length of each instruction and extracting that instruction from the instruction stream is performed by a function unit called an Instruction Align Unit (IAU). This block must contain decoder logic to determine the instruction length, and a shifter to align the instruction data with the decoder logic.
For the Intel 80386 microprocessor, the first byte of an instruction can have numerous implications on the overall instruction length, and may require that additional bytes be checked before the final length is known. Furthermore, the additional bytes may specify other additional bytes. It is therefore extremely difficult to quickly determine the length of the X86 instruction because the process is inherently sequential.
Based on the information provided in the i486™ Programmer's Reference Guide, several conclusions can be drawn regarding alignment unit present in the i486™. The i486™'s IAU is designed to look only at the first few bytes of the instruction. In cases where these bytes do not fully specify the length, these initial bytes are extracted and the process is repeated on the remaining bytes. Each iteration of this process requires a full cycle, so it may take several cycles, at worst case, for an instruction to be fully aligned.
Situations that require additional cycles for the i486™ IAU include the presence of prefixed and escaped (2 byte) opcodes. Both of these are common in i486™ programs. In addition, complex instructions may also comprise displacement and immediate data. The i486™ requires additional time to extract this data.
An example format for a CISC processor instruction is shown in FIG. 1. The example depicts the potential bytes of a variable length i486™ CISC instruction. The instructions are stored in memory on byte boundaries. The minimum length of an instruction is 1 byte, and the maximum length of an instruction, including prefixes, is 15 bytes. The total length of the instruction is determined by the Prefixes Opcode, ModR/M and SIB bytes.

This patent is subject to a terminal disclaimer.

System and method for translating non-native instructions to native instructions for processing on a host processor