In power generation control for a vehicle, which is configured to control power generation so as to reduce an amount of fuel consumed by power generation of the internal combustion engine, the vehicle including: a generator configured to be driven by the internal combustion engine to generate electric power; and the battery to be charged by the generated electric power of the generator, the vehicle being configured to stop idling at a predetermined vehicle speed or less, a battery voltage as an inter-terminal voltage of the battery is detected, and the internal combustion engine is controlled to interrupt power generation involving fuel consumption one of when the detected battery voltage reaches a predetermined combustion power generation interruption voltage and when the detected battery voltage exceeds the predetermined combustion power generation interruption voltage.

1. Field of the Invention
The present invention relates to a vehicle power generating device and the like, and more particularly, to reducing an amount of fuel consumed by power generation of an internal combustion engine.
2. Description of the Related Art
Conventionally, a vehicle mounts a generator for supplying electric power to various kinds of electric loads and charging a battery. The generator generates electric power by being driven by an internal combustion engine, and hence, when the internal combustion engine is in operation (excluding when fuel is cut off), the fuel is consumed also by the power generation.
In view of this, vehicle fuel efficiency improvement has been demanded in recent years to deal with environmental matters. There have been proposed a method of actively performing power generation when the internal combustion engine cuts off the fuel, such as when the vehicle is decelerating (hereinafter referred to as power regeneration), to thereby reduce the chance for the internal combustion engine to perform power generation involving fuel consumption (hereinafter referred to as combustion power generation), and a method of setting the operating region of the internal combustion engine as the condition for performing combustion power generation, to thereby reduce the amount of fuel consumed by power generation (see, for example, Japanese Patent No. 4158615). In the conventional technology, based on a fuel consumption map in which incremental power of the internal combustion engine obtained by power generation is added, power generation is performed in an operating region of the internal combustion engine, where fuel consumption is small, to thereby reduce the amount of fuel consumed by power generation.
The conventional technology disclosed in Japanese Patent No. 4158615, however, takes no consideration of a charged state of the battery during power generation. In particular, in the case of a generally-used lead-acid battery, the charge acceptance tends to deteriorate as the state-of-charge (hereinafter referred to as SOC) of the battery becomes higher. Thus, when the SOC of the battery becomes higher than necessary because of excessive combustion power generation, the charge acceptance in power regeneration deteriorates to reduce regenerated energy. The reduced regenerated energy is compensated for by increasing the chance of combustion power generation. As a result, there has been a problem of the increased amount of fuel consumed by power generation.

Vehicle power generating device and power generation control method


A method is provided for defining an antenna with weak sidelobes having at least two sources, in which the sources are regularly distributed and the reflectors have suitable shapes, obtained by the implementation of a specific algorithm, the reflectors being illuminated by sources composed of a single part. The obtained antenna will offer a gain close to 0 in the direction of the array lobes, so these will be as low as possible.

The Ka band is currently being deployed for high-speed satellite communications. It is characterized by a very high frequency, leading to difficulties in technological development, a very large separation of the emission frequencies Tx, about 20 GHz, and the reception frequencies Rx, about 30 GHz, and a large usable bandwidth in the order of 2 GHz. Many companies are developing antenna systems compatible with mobile applications, either ground-based or aeronautical.
The use of satellite dishes in communication systems is not adapted for mobiles because their height is excessive, incurring restrictions on displacement, inability to be used when these systems become outsized, etc. Additionally, in the field of high-speed satellite communications, the standardized environment is important. The power density emitted off-axis is regulated in order to avoid the scrambling of other satellites. This forces the antenna to have a pattern with low sidelobes or array lobes.
Most of the solutions developed by the prior art are imperfect and generally exhibit rises in the sidelobes in certain directions. These solutions are based on dense arrays of sources, but the very high emission frequency in the Ka band of 30 GHz imposes compromises in terms of source density. One of the solutions offered is based on a quincunx array, which is easier to construct but which exhibits wide array lobes.
In the prior art known to the Applicant, the antennas used operate in the Ku band. In the Ku band, two types of solution are used to produce such antennas.
A first type is the type A, as described in patent application US 2011/0267250 in which the dense arrays of elementary sources are of horn or slit type. The second type of solution is the type B in which the arrays are based on sources of large size, for example according to the patent U.S. Pat. No. 6,563,473. To avoid the presence of array lobes, the distance between elementary sources must be shorter than the wavelength, for example 1 cm in the Ka band. This condition is adequate but not necessary. It is also generally necessary for the power density over the whole surface of the antenna aperture to obey precise mathematical laws, and it is for example possible to use a uniform law which will not give rise to array lobes.
Solutions of type A are complicated in terms of application and expensive in the Ka band because:                the array pitch of 1 cm leaves very little space for performing the operations,        the number of sources is very high (1408) for a typical antenna of 22 cm by 64 cm,        the separation of 10 GHz between the TX and RX frequencies as well as the bandwidth of 2 GHz impose solutions (relative band of 30%).
Type B solutions are easier to produce because they include fewer sources. As the separation between sources is greater than the wavelength, the presence of array lobes is generally permitted.
The U.S. Pat. No. 6,563,476 describes an antenna system working in the Ku band, the frequency band of which is twice as low, in which the separation between sources is irregular, for two or more than two sources.
The patent application US 2011/0267250 presents a solution that consists in bringing the sources closer together by asymmetrically shortening the reflectors. This solution works with two sources.
The prior art known to the Applicant does not describe any antenna with weak lobes having more than two sources.

Method for defining the structure of a Ka band antenna


An information handling system, such as a disc drive, includes a controller that communicates with other devices in a loop, and performs distributed or peer-to-peer loop error diagnostics. One example of a loop is a fiber channel arbitrated loop. Distributed or peer-to-peer loop error diagnostics identifies and diagnoses errors in the immediately upstream device and the immediately upstream link by monitoring the error count to determine of the error count is increasing or not. An increasing error count or a changed loop configuration indicates that the source of the error is not the upstream device, while an unchanging error count and an unchanged loop configuration indicates that the source of the error is the upstream link.

The present invention relates to the field of loop diagnostics. More particularly, this invention relates to a peer-to-peer interface diagnostics.
One key component of any computer system is a device to store data. Computer systems have many different places where data can be stored. One common place for storing massive amounts of data in a computer system is on a disc drive. The most basic parts of a disc drive are a disc that is rotated, an actuator that moves a transducer to various locations over the disc, and electrical circuitry that is used to write and read data to and from the disc. The disc drive also includes circuitry for encoding data so that it can be successfully retrieved and written to the disc surface. A microprocessor controls most of the operations of the disc drive as well as passing the data back to the requesting computer and taking data from a requesting computer for storing to the disc.
Information representative of data is stored on the surface of the storage disc. Disc drive systems read and write information stored on tracks on storage discs.
Fibre Channel (FC) is a serial data transfer architecture standardized by ANSI. A prominent FC standard is Fibre Channel Arbitrated Loop (FC-AL). This standard defines a distributed daisy-chained loop. FC provides for peer-to-peer communication on this loop.
FC-AL was designed for new mass storage devices and other peripheral devices that require very high bandwidth. FC-AL supports the Small Computer System Interface (SCSI) command set in addition to other upper level protocols. The mapping of these upper level protocols to FC is referred to as the FC-4 layer.
In a FC-AL, information from an originating device can pass through multiple other devices, and the links between the devices, before arriving at the recipient device. While the passage of information on multiple links adds complexity to isolating marginal and failing links over point to point connections, three conventional techniques of isolating marginal links exist. One technique of isolating marginal FC links uses link status to isolate the problem link. A second approach uses error-reporting features of the FC-4 mapping. A third approach is a combination of the first two.
A primary requirement for the three techniques is knowledge of the topology (i.e. connection order). Knowledge of the topology may be obtained during FC-AL defined loop initialization from the loop position map or by implicit means. An example of an implicit means is an enclosure of disks drives using hard addresses.
A first approach of using link status in the isolation of marginal links requires a management application (MA) in at least one of the devices on the loop. Several MAs may be implemented to cover the failure of any one. An MA may either periodically poll the loop during normal loop operation or request devices detecting link errors to report the incident. In polling mode, the link status accumulated in all the devices is used to locate marginal links. In the report error, identification mode, status accumulated from all devices reporting errors is used to locate marginal links.
The isolation of the source of a single error is possible with this approach but not guaranteed.
The use of link status makes the approach FC-4 independent. This is an advantage in multiple protocol loops. However, the drawback of using link status is the polling or report error mode overhead reduces the efficiency of the loop.
The second approach uses error-reporting features of the FC-4 mapping. Using FC-4 reported errors to isolate the source of errors on loops requires maintaining a log of the errors. The source is located by analyzing the log to determine which devices are reporting errors and which are not.
Using FC-4 reported errors to isolate the source of errors on loops removes the requirement for an MA to maintain link error history and poll the loop. Not polling the loop reduces overhead on the loop. Additionally, errors are only report when they occur.
Using FC-4 reported errors to isolate the source of errors on loops performs best in implementations in which a single master device receives all the reported errors. An example of such an implementation is a single initiator SCSI storage subsystem.
There are at least three drawbacks to relying on just the FC-4 error status. The occurrence of a single error does not provide sufficient information to isolate the source. Furthermore, status must be accumulated to build a history in order to isolate the error source. Lastly, in loops supporting multiple protocols or multiple devices that receive FC-4 status, implementation becomes difficult because the errors are not reported to a common destination device.
The third technique of isolating marginal FC links uses link status and FC-4 error reporting to isolate the problem link. Polling is not used and the isolation of the source of a single error is possible.
As with any use of link status, an MA is needed to keep error counts of all devices. When a FC-4 error is reported or the MA detects a link error, the MA reads the accumulated link status from all devices to determine the possible source of the error.
A disadvantage to implementation on loops with multiple FC-4s is the MA must support all the FC-4s.
Referring to FIG. 1, a diagram of a loop 100 comprised of SCSI Fibre Channel Protocol (FCP) devices, is shown. The loop includes a SCSI initiator device, 110, that serves as the loop master, communicating with SCSI target devices 120, 130, and 140. The link or interconnect 150 between devices 120 and device 130 is marginal and/or failing.
Error detection and reporting provided by a FC-4 may be used for the isolation of marginal links when available.
Due to the marginal link 150, loop master 110 will experience command time-outs and data errors. The command time-outs are the result of errors during command, transfer ready, or response frames. These frames are discarded when they are received in error. Because the time-out could result from discarded frames to the targets, commands, or from the targets, transfer readies and responses, the location of the bad link can not be determined.
On write data operations, device 120 does not experience errors on data from loop master 110. Device 120 and device 130 will, however, detect the errors introduced by the marginal link. Errors on write data are reported in the FCP Response.
On read data operations, loop master 110 does not detect errors on read data from device 130 and device 140.
What is needed are loop error diagnostics that do not require knowledge of the topology of the loop, that reduces loop overhead traffic, and increases the effectiveness of the diagnostics.
In a peer to peer approach to isolation of error source, the management application (MA) function is distributed to all devices on the loop. Link status is used for error source isolation. More specifically, each device maintains the identity and the link error status of the device connected to its input, upstream device. When a device detects a link error on its input, the device initiates a request to the upstream device for link error counts.
When the link status for the upstream device indicates that device is also detecting link errors, the source of the errors is a different link on the loop. If the link status from the upstream devices does not indicate it is detecting errors, the source of the errors is likely the interconnect between the upstream device and the device itself. The device may then initiate diagnostic transfers between the upstream device and itself to verify the interconnect is marginal.
Advantageously, the present invention of loop error diagnostics does not require knowledge of the complete topology of the loop. The present invention also reduces loop overhead traffic because error isolation is distributed to each of the devices in the loop. Furthermore the effectiveness of loop diagnostics is increased because devices closest to the source of the problem perform the diagnostics. In addition, the present invention minimizes degradation of performance of each device on the loop because the diagnostic function in each device is enabled to execute when the device is idle, thereby, preventing the diagnostics from affecting the performance of the device during higher priority tasks.


The throttle control device of this invention for controlling a throttle based on outputs of a position sensor including a first sensor and a second sensor which detect a position of a same object includes: a judgment section for judging whether or not the position sensor is abnormal by comparing a difference between the output of the first sensor and the output of the second sensor with a predetermined threshold value; and a change section for changing the predetermined threshold value depending on at least one of the output of the first sensor and the output of the second sensor.

1. Field of the Invention
The present invention relates to a throttle control device including a double-system sensor, and more particularly, relates to a throttle control device which controls a throttle in consideration of an abnormal state of the double-system sensor.
2. Description of the Related Art
Japanese Publication for Opposition No. 6-94820 discloses an electronic control device which detects an abnormality of a double-system accelerator position sensor including a main sensor and a sub-sensor. This electronic control device displays an error message on a display device when the difference between signals output from the main sensor and the sub-sensor exceeds a predetermined threshold value, thereby indicating that an abnormality has been detected in the accelerator position sensor.
However, the Publication has not considered the case where the variation degree of the output of the double-system sensor changes when the contact resistance between a resistor and a brush of the double-system sensor increases.
More specifically, the variation degree of the output of the double-system sensor changes depending on the detection position of the double-system sensor when the contact resistance increases. This has been found by the inventors of the present invention. Therefore, in the conventional method in which the double-system sensor is judged abnormal when the difference between the signals output from the double-system sensor exceeds a predetermined value, the precision of the abnormality detection is low.
In view of the foregoing, the objective of the present invention is to provide a throttle control device which can detect an abnormality of a double-system sensor with high precision irrespective of a change in the variation degree of the output of the double-system sensor.


A system for a Fischer-Tropsch synthesis using a three-phase reactor in which a primary filter removes coarse catalyst particles from the product and in which catalyst fines are removed in a secondary filter. Some or all portion of the product wax from the secondary filter can be recycled back to the reactor, either as a back flush medium for the primary filter or directly to the slurry in the reactor, whereby removal of catalyst fines is rendered independent of the rate of wax production.

In reactors that generate high molecular weight hydrocarbons (wax), some of the reaction products must be removed from the reactor in liquid form, preferably without losing catalyst, which will be in suspension in a finely divided form.
It is well known that there is a high risk of generating fines in a FT slurry reactor due to attrition/erosion of catalyst, and this can create the danger of catalyst loss and blocking of wax filters by fine catalyst particles.
Several methods have been described in the literature for effecting the separation of the catalyst and/or wax from the reactor slurry, such as internal filtration, external filtration, hydrocyclones, magnetic methods and settling/sedimentation. As the concentration of catalyst fines builds up in the reactor slurry, the flux through the filter will decrease and at a certain point it will be too low to maintain the filtrate capacity needed for a given wax production rate.
There are several known ways of reducing the effect of fines on the filtration, such as using a larger filtration area, more frequent cleaning (for example back-flushing) of filters, higher differential pressure for filtration etc. However all of these methods are either space limited or energy consuming and may shorten the life time of the filters.
The relationship between fines concentration in the slurry and the filtration flux is highly non-linear. This is shown as a very large decrease in flux as a result of increasing the fines concentration at very low or virtually zero fines concentrations, while further increases in fines concentration has a smaller effect. The fines generation rate in the reactor is not particularly sensitive to the wax production rate, but is more sensitive to the fluid dynamics of the reactor, which are for example related to the feed gas rates and of course the mechanical properties of the catalyst. Operating the reactor at conditions that give lower wax production is not a permanent solution; it simply extends the operating time somewhat and gives lower overall production. The concentration of fines in the slurry will increase at a higher rate if the removal of wax is decreased as the only outlet of fines is through the filtered wax.
It is therefore important to have a system for controlling the fines removal rate out of the reactor, both during normal operation and during upset conditions/turn down.

Apparatus and method for conducting a fischer-tropsch synthesis reaction


A logic circuit for generation of data signatures and/or encryption of data packets to be transferred from an industrial controller snoops data as it is written to an output buffer within the industrial controller. The logic circuit generates a secure signature and/or coordinates encryption of the data packet being transferred between the shared memory location and the output buffer. If encryption of the data is required, an encryption module may both encrypt the data and generate a secure signature. If encryption is not required, the logic circuit generates the secure signature. In either case, the logic circuit controls ownership of the memory address in which the secure signature is to be written to coordinate with the MAC transferring the secure signature to the output buffer, providing a uniform interface between the SPP module and the MAC.

The subject matter disclosed herein relates to a method and apparatus for managing transmission of secure data packets on an industrial network. More specifically, an inline logic circuit monitors a data bus to detect the transfer of data packets to a network interface for transmission on the industrial network and to perform high speed generation of secure signatures, encryption, or a combination thereof on the data packet as the data packet is transferred from a shared memory location to a network port for transmission by the device sending the data packet.
Industrial controllers are specialized computer systems used for the control of industrial processes or machinery, for example, in a factory environment. Generally, an industrial controller executes a stored control program that reads inputs from a variety of sensors associated with the controlled process or machine. Sensing the conditions of the process or machine and based on those inputs and the stored control program the industrial controller determines a set of outputs used to control actuators for the process or machine.
Industrial controllers differ from conventional computers in a number of ways. Physically, they are constructed to be substantially more robust against shock and damage and to better resist extreme environmental conditions than conventional computers. The processors and operating systems are optimized for real-time control and are programmed with languages designed to permit rapid development of control programs tailored to a constantly varying set of machine control or process control applications.
Generally, the industrial controllers are embedded systems with a highly modular architecture that allows, for example, different numbers and types of input and output modules to be used to connect the controller to the process or machinery to be controlled. This modularity is facilitated through the use of special "control networks" suitable for highly reliable and available real-time communication. Such control networks (for example, ControlNet, EtherNet/IP, or DeviceNet) differ from standard communication networks (e.g. Ethernet) by guaranteeing maximum communication delays by pre-scheduling the communication capacity of the network and/or providing redundant communication capabilities for high-availability. In addition, packets transmitted on the control network are formatted according to a protocol defined for the particular network, such as the Common Industrial Protocol (CIP) or similar protocols. The control networks allow input and/or output modules to be distributed around a controlled machine or process while guaranteeing that data is received at the processor from an input module or provided to an output module in a timely manner. In some applications, multiple networks may be connected to an industrial controller. One or more networks may be control networks and one or more networks may be standard communication networks. The industrial controller must be configured to manage the network traffic on each network while maintaining the reliability and timing requirements of each control network to which it is connected. Since controllers are constrained embedded systems with tight real-time processing requirements, these designs must be efficient and robust in terms of data movement and CPU software cycles.
As is understood in the art, network communication functions are sometimes described in terms of a seven-layer Open Systems Interconnection (OSI) model. The first (bottom) layer is the physical layer which includes the hardware, such as network cabling, connectors, and other components required to provide the electrical and mechanical interface for transmitting data. The second layer is the data link layer which manages transfer of data frames between devices on the network. A Media Access Controller (MAC) may be part of the data link layer and may be provided at each port of the device connected to the network. Within the device, the MAC provides one of the first layers of data packet management for packets received from the network and one of the last layers of data packet management for packets transmitted on the network.
In an industrial controller, the MAC manages incoming data packets, temporarily storing them in receive buffers and then transmitting the data packets to a shared memory location for further processing by software. The software executing the further processing will be referred to herein as a Software Packet Processing (SPP) module. Similarly, the MAC also manages outgoing data packets. The SPP module is configured to assemble data into a data packet and write the data to shared memory. The MAC then transfers data from the shared memory location and loads data packets into transmit buffers for subsequent transmission on the physical network.
The SPP module also manages additional data handling requirements for each data packet to be transmitted from a device. Some secure data packets may require, for example, authentication of the data packets. Authentication messages can be sent without encryption, but the sending device must generate a secure signature for the data payload and header and append this secure signature to the data packet. The secure signature may be checked by the receiving device in order to verify the received packet arrived from the expected sender and to verify the integrity of the data. Other secure data packets may also require encrypted transmission in addition to authentication. Such incoming data packets may be encrypted and require decryption at the receiver, and outgoing data packets may require encryption prior to transmission. Each of the data handling requirements may require one or more additional reads, writes, or other processing of the data packet to complete, and each read, write, or other processing step introduces latency within the network between receiving the data packet and when the device is able to utilize the data.
In an industrial controller, however, these additional reads, writes, and other processing steps are undesirable overhead. Traditionally, the SPP module utilizes a portion of the processing capacity of the industrial controller to execute these steps. The additional processing overhead along with the latency introduced limits the rate at which the industrial controller may transfer data packets over the network and limits the rate at which other critical control functions may be performed.
Thus, it would be desirable to provide an improved method and apparatus for managing secure transmission of data packets from the industrial controller.

Method and apparatus for managing transmission of secure data packets


A method for driving a plasma display panel. A discharge occurs at a selected discharge cell by scan and address pulses to form wall charges in an address period. A setup pulse is applied to a scan electrode in a sustain period. A discharge occurs between sustain and scan electrodes by a wall voltage of the sustain and scan electrodes and a voltage of the setup pulse when the setup pulse is applied. A self discharge occurs between the sustain and scan electrodes when the setup pulse falls, to form space charges. A sustain pulse is applied to the sustain and scan electrodes, and a sustain occurs by the space charges and the sustain pulse.

(a) Field of the Invention
The present invention relates to a plasma display panel (PDP) and a driving method thereof.
(b) Description of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and PDPs have been actively developed. The PDPs from among the flat panel devices have better luminance and light emission efficiency compared to the other types of flat panel devices, and also have wider view angles. Therefore, the PDPs have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
A PDP is a flat display for showing characters or images using plasma generated by gas discharge, and pixels numbering to more than several million are provided thereon in a matrix format, according to its size. Referring to FIGS. 1 and 2, a PDP structure will now be described.
FIG. 1 shows a partial perspective view of the PDP. FIG. 2 shows an electrode arrangement of the PDP.
As shown in FIG. 1, the PDP includes glass substrates 1 and 6 facing each other with a predetermined gap therebetween. Scan electrodes 4 and sustain electrodes 5 in pairs are formed in parallel on glass substrate 1. Scan electrodes 4 and sustain electrodes 5 are covered with dielectric layer 2 and protection film 3. A plurality of address electrodes 8 is formed on glass substrate 6. Address electrodes 8 are covered with an insulator layer 7. Barrier ribs 9 are formed on insulator layer 7 between address electrodes 8. Phosphors 10 are formed on the surface of insulator layer 7 and between barrier ribs 9. Glass substrates 1 and 6 are provided facing each other with discharge spaces therebetween so that scan electrodes 4 and sustain electrodes 5 may respectively cross address electrodes 8. Discharge space 11 between address electrodes 8 and a crossing part of the paired scan electrode 4 and sustain electrode 5 forms discharge cell 12.
As shown in FIG. 2, the electrodes of the PDP have an (n×m) matrix format. Address electrodes Al through Am are arranged in the column direction, and n scan electrodes Y1 through Yn and n sustain electrodes X1 through Xn are arranged in pairs in the row direction.
Referring to FIGS. 3 and 4A through 4D, a conventional PDP driving method will be described.
FIG. 3 shows a driving waveform diagram of the conventional PDP, and FIGS. 4A through 4D show distributions of wall charges in respective intervals when using the conventional driving method. That is, FIGS. 4A through 4D show charge distributions corresponding to the driving waveform shown in FIG. 3.
In general, a single frame is divided into a plurality of subfields in the PDP, and the gray is represented by combination of the subfields. As shown in FIG. 3, each subfield has a reset period, an address period, and a sustain period. In the reset period, wall charges formed by previous sustaining are erased, and the wall charges are set up so as to stably perform the next addressing. In the address period, cells that are turned on and those that are turned off are selected, and the wall charges are accumulated to the cells that are turned on (i.e., addressed cells). In the sustain period, sustaining is executed so as to display the actual image to the addressed cells.
When a sustain occurs in the sustain period, wall charges are formed and accumulated at the sustain and scan electrodes, and a discharge cell is sustained by a wall voltage formed by the wall charges and a sustain pulse alternately applied in the sustain period. Through the repetition of the above-noted process, a predetermined number of sustains occur in the sustain period. As described, the conventional method uses a memory function of the wall charges generated and stored at the scan and sustain electrodes to generate a sustain.
Referring to FIG. 3, the conventional reset period includes an erase period, a ramp rising period, and a ramp falling period.
(1) Erase Period
When the final sustain is finished, positive charges are accumulated to the sustain X electrode, and negative charges to the scan Y electrode, as shown in FIG. 4A. Since the address voltage is maintained at 0V (volts) during the sustain period, but it tries to maintain a middle voltage of the sustain all the time, a large amount of the positive charges are accumulated to the address A electrodes.
When the sustain is finished, an erase ramp voltage that gradually increases from 0(V) to+Ve(V) is applied to the sustain X electrode, and the wall charges formed on the sustain X and scan Y electrodes are gradually erased, as shown in FIG. 4B.
(2) Y Ramp Rising Period
During this period, the address A electrode and the sustain X electrode are maintained at 0V, and a ramp voltage is applied to the Y electrode, the ramp voltage gradually rising from voltage Vs that is below the discharge firing voltage with respect to the sustain X electrode to voltage Vset that is over the discharge firing voltage. While the ramp voltage rises, first weak resetting is generated to all the discharge cells from the scan Y electrode to the address A electrode and the sustain X electrode. As a result, the negative wall charges are accumulated to the scan Y electrode, and concurrently, the positive wall charges are accumulated to the address electrode and the sustain X electrode, as shown in FIG. 4C.
(3) Y Ramp Falling Period
In the latter part of the reset period, a ramp voltage that gradually falls from voltage Vs below the discharge firing voltage to 0(V) over the discharge firing voltage with respect to the sustain X electrode is applied to the scan Y electrode under the state that the sustain X electrode maintains a constant voltage Ve. While the ramp voltage falls, second weak resetting is generated from all the discharge cells. As a result, the negative wall charges of the scan Y electrode are reduced, and the polarity of the sustain X electrode is inverted to accumulate weak negative charges thereto, as shown in FIG. 4D. Also, the positive wall charges of the address A electrode are adjusted to an appropriate value for the address operation.
As described, the states of the sustain X electrode, the scan Y electrode, and the address A electrode are processed through the reset period so that they may be suitable for addressing in the address period. However, the address period is reduced because each subfield requires a reset period in the conventional driving method. A long address period is needed for scanning of a high-resolution screen, but it is not easy to display the high-resolution screen through the prior art. Also, discharges occur twice in the reset period, and hence, a constant discharge always exists in the discharge cells that are not turned on, and the total contrast of the screen is lowered.

Plasma display panel and driving method thereof


A method for global calibration of a multi-view vision-based touch probe measurement system is provided which encompasses calibrating camera frame distortion errors as well as probe form errors. The only required features in the calibration images are the markers on the touch probe. The camera frame distortion calibration comprises a process that depends on a portable calibration jig and the touch probe, but that process is unaffected by probe form distortion errors in the touch probe and/or tip. The probe tip position calibration depends on applying the results of the camera, frame distortion calibration. When the same probe tip is used throughout the global calibration, the probe tip position calibration uses images from the set of images used by the camera frame distortion calibration. The global calibration method is particularly advantageous for low cost portable versions of multi-view vision-based touch probe measurement systems.

Various types of touch probe coordinate measuring systems are known. In the type of touch probe coordinate measuring system under consideration here, the workpiece is measured by using a multi-camera vision system to determine the location of the touch probe when the touch probe tip is at a desired location on a workpiece surface. A visual marker pattern is located on the body of the touch probe, with the markers being imaged by at least two cameras of the vision system, and the images are used to triangulate the position of each of the markers in three dimensional space. Based on this data the probe tip location coordinates and the adjacent workpiece surface coordinates may be inferred or estimated.
Factors that limit the measurement accuracy of the type of touch probe measurement systems outlined above include errors that are introduced by distortions and/or erroneous assumptions regarding the coordinate frame associated with the multi-camera vision system. Such errors are referred to as camera frame distortion errors herein. Errors are also introduced by distortions and/or erroneous assumptions regarding the relationship between the marker locations in the probe tip location. Such errors are referred to as probe form errors herein.
U.S. Pat. Nos. 5,828,770, 5,805,287, and 6,497,134 each disclose various features related to the type of touch probe coordinate measuring system outlined above, and each is hereby incorporated by reference in its entirety. The '770 patent describes systems and methods related to performing measurements using an object (e.g. a probe) that includes a plurality of activatable markers. However, the '770 patent is generally not directed toward systems and methods for reducing camera frame distortion errors or probe form errors, and includes few, if any, teachings in this regard.
In contrast the '287 patent discloses a method for calibrating and/or correcting certain types of camera frame distortion errors. To briefly summarize that calibration method, the '287 patent teaches that: (i) the positions of permanently mounted light sources or reflectors are registered by their image on each camera, and their positions in the image are given as coordinates related to a camera fixed coordinate system; and (ii) the positions of at least two points for which the mutual separation distances are known are registered by holding a probing tool in contact with the points, and the positions of the points are calculated from the observed images of the light sources or reflectors of the probing tool. Based on the obtained data, the correct length scale in the camera frame may be established, and optical properties of the cameras may be mathematically modeled such that image distortions occurring through the camera lens may be compensated, all of which falls within the scope of calibrating and/or compensating camera frame distortion errors. However, the teachings of the '287 patent with regard to camera frame distortion errors do not encompass potential probe form errors, or their potential deleterious influence on the camera frame distortion calibration methods of the '287 patent.
The '134 patent discloses a method for calibrating and/or correcting a probe form error. In particular, the '134 patent addresses determining a location error for a feature of a surgical probe or instrument (e.g. its tip), relative to a set of energy emitters (e.g. markers) on its body. To briefly summarize the calibration method, the '134 patent teaches that the location error is found by: (i) calculating the position and orientation of the body having the energy emitters disposed thereon, in a plurality of orientations and positions relative to a reference frame, but with the feature (e.g. the tip) in a substantially constant position relative to the reference frame, (ii) calculating the locations of the feature of the object (e.g. the tip) from these calculated positions and orientations, (iii) averaging these calculated locations, (iv) determining the location of the feature by physical measurement thereof in relation to the physical locations of the emitters, and (v) comparing the calculated average location with the physically measured location to arrive at the error. In order to reduce or avoid the effects of camera frame distortion errors when determining probe form error, the teachings of the '134 patent include imaging a local reference frame that comprises an additional plurality of "fixed emitters", at the same time that the "body emitters" are imaged. Calculating the positions and orientations of the "body emitters" relative to the additional "fixed emitters", rather than relative to the overall camera frame, largely circumvents the effects of camera frame distortion errors. Otherwise, the teachings of the '134 patent with regard to calibrating or correcting probe form error do not encompass potential camera frame distortion errors, or their potential deleterious influence on probe form error calibration methods in the absence of additional "fixed emitters" in the calibration images.
As outlined above, a calibration method that efficiently encompasses camera frame distortion errors, as well as probe form errors, is not in evidence. Rather, separate calibration of these errors, using fixed reference emitters, or the like, is the norm. The present invention is directed to providing a system and method that overcomes the foregoing and other disadvantages.

Global calibration for stereo vision probe


The present invention relates to a method and a user equipment for use in a wireless communication system. The method and user equipment allow for transmit power adjustment of the transmit power of a selected of a plurality of antennas of the user equipment. The method comprised a transmit power adjustment phase during which it is test (23) is performed to decrease the transmit power of the selected antenna. A number of TPC commands are then analyzed (24) to determine a result of the decreased transmit power indicating a change in received power at a base station. Based on the determined result it is decided to continue (27) with the decreased transmit power or to resume (26) the previous transmit power of the selected antenna after completion of the transmit power adjustment phase.

In communication systems based on e.g. Code Divisional Multiple Access (CDMA), power control is used to meet the desired quality of service targets. The power control may be implemented both in a user equipment (UE) to meet a downlink quality target and also in a base station (BS) to meet an uplink quality target. In wireless communication networks, the downlink (DL) is the transmission path from the base station to the user equipment, and the uplink (UL) is the transmission path from the user equipment to the base station. It is important that the power control is able to maintain the desired quality of service target despite varying radio conditions, which is often the case in wireless communication systems.
Most CDMA systems, such as cdma 2000, Wideband Code Division Multiple Access (WCDMA), and the extensions of WCDMA called High Speed Packet Access (HSPA) and Evolved HSPA (HSPA+) applies inner loop power control and outer loop power control. The inner loop power control, also called fast power control, runs every time slot, which is typically less than 1 ms (e.g. 0.67 ms in WCDMA). In WCDMA the inner loop power control runs in both uplink and downlink. The fast inner-loop power control adjusts the transmit power of the sender towards a specific Signal to Interference and noise Ratio (SIR) target at the receiver. The aim of the uplink and downlink inner loop power controls is to counter the effect of fast fading, while maintaining the desired SIR target. In the uplink the power control also compensates for the near-far problem, so that a signal received from users far out in a cell are not swamped out by stronger signals from users close to the base stations. During every slot the user equipment estimates the SIR on some known reference or pilot symbols and compares it with some SIR target corresponding to a given service, e.g. Block Error Rate (BLER), certain Bit Error Rate (BER) requirements and spreading factor used etc. In WCDMA, downlink SIR is measured on Dedicated Physical Control Channel (DPCCH), which comprises pilots bits and Transmit Power Control (TPC) bits. The TPC bits, which correspond to TPC commands, are also used for uplink power control and the pilot bits are primarily used for channel estimations. If the estimated SIR is less than the SIR target then the user equipment generates an UP command, otherwise it generates a DOWN command. In response the base station will increase (in case of UP) or decrease (in case of DOWN) its downlink transmit power. TPC commands for uplink power control are carried on Dedicated Physical Channel (DPCH) or Fractional DPCH (F-DPCH) from the base station to the user equipment. The user equipment will increase (in case of UP) or decrease (in case of DOWN) its uplink transmit power in response to the received TPC commands.
The aim of the outer loop power control is to adjust the SIR target value used by the inner loop power control as previously explained, while maintaining a certain link quality. The quality target (e.g. BLER of the data) is set by the network and is expected from the user equipment to consistently maintain this target to ensure the desired quality of service is met throughout the session. Due to the varying radio link conditions e.g. user mobility, fast fading etc, the mapping between the SIR target and BLER changes over time. This is a key point as it requires frequent adjustment of the SIR target to maintain the desired value of BLER. This mechanism of adjusting the SIR target is also referred to as outer loop power control, quality control or outer loop scheme.
The transmission of data over the air in a wireless communication system is performed by using a plurality of different physical channels, for example Dedicated Physical Control CHannel (DPCCH), Dedicated Physical Data CHannel (DPDCH), Enhanced Dedicated Physical Control CHannel (E-DPCCH) and Enhanced Dedicated Physical Data CHannel (E-DPDCH). The power consumptions of these are generally related to each other by power offsets, i.e. beta-values or gain factor relative the power level of the DPCCH.
Currently the Third Generation Partnership Project (3GPP) is evaluating the potential benefits of uplink transmit (Tx) diversity in the context of High-Speed Uplink Packet Access (HSUPA). An aim is to enhance uplink capacity and UE power consumption. With uplink transmit diversity UEs that are equipped with two or more transmit antennas are capable of utilizing all of them for uplink transmissions. This is achieved by multiplying a UE output signal s(t) with a set of complex pre-coding weights wi, where i=1 . . . N with N denoting the number of transmit antennas. The rationale behind uplink transmit diversity is to adapt the pre-coding weights so that user and network performance is maximized. Depending on UE implementation the antenna weights may be associated with different constraints.
Within 3GPP two classes of transmit diversity are considered:                Switched antenna transmit diversity, where the UE at any given time-instance transmits from one of its antennas only. Thus if wi≠0, wj=0 for all j≠i.        Beamforming where the UE at a given time-instance can transmit from more than one antenna simultaneously. By means of beamforming it is possible to shape an overall antenna beam in the direction of a target receiver.
While switched antenna transmit diversity is possible for UE implementations with a single power amplifier (PA) the beam forming solutions may require one PA for each transmit antenna.
Switched antenna transmit diversity can be seen as a special case of beamforming where one of the antenna weights is 1 (i.e. switched on) and the antenna weight of any other antenna of the UE is 0 (i.e. switched off).
A fundamental idea behind uplink transmit diversity is to exploit variations in the effective channel to improve user and network performance. The term effective channel here incorporates effects of transmit antenna(s), transmit antenna weights, receiving antenna(s), as well as the wireless channel between transmitting and receiving antennas.
A commonly considered application scenario of beamforming is a UE with two PAs that typically transmits with equal power on two antennas. Beamforming algorithms proposed in 3GPP use phase differences between the antennas based on a code book, which means that the phase difference is chosen among a set of possible phases. One algorithm to find the best phase difference discussed in 3GPP is to evaluate the effect of changing phase by examining the received TPC bits. For example, if the phase difference is increased and the corresponding TPC bits indicate that power should be increased, this implies that the increased phase difference resulted in worse channel and consequently, the phase should be restored or decreased.
The gain from using beamforming originates from the diversity gain that is obtained by using two or more transmit antennas. The increased gain means that lower transmission power is needed to reach the desired SIR target. In an interference limited system, the lower transmission power results in lower interference between cells (inter-cell interference), which may lead to higher cell throughput. For a power limited UE, the diversity gain is more or less directly shown as a coverage gain.
Channel conditions can differ a lot between different transmit antennas. There are two major reasons for this: fast fading differences between the antennas, and fixed antenna gain imbalance between the antennas. For a high speed user the difference between the antenna channels vary very fast, but for a stationary lap-top the channel differences can be more or less constant (or very slow varying). It is also common that a primary antenna has a better antenna gain than a secondary antenna. In the current 3GPP evaluations of UL Tx diversity, a fixed imbalance between two transmit antennas of 0 or 4 dB and a random (per UE) imbalance with standard deviation of 2.25 dB are being studied. Hence, it is not uncommon or unrealistic that there is a large antenna gain imbalance between the antennas.
From the above description it is apparent that there are many factors that may need to be considered in order to achieve efficient power control both in the downlink and in the uplink.

Method and apparatus for uplink transmit power adjustment


In a pipeline network processor, a multicast echo feature ensures that a copy of a packet is sent to all downstream ports associated with an upstream port that delivers the packet. The pipeline network processor maintains a table of header information that is stripped away upon reception in order to forward the packet to each appropriate downstream port. The pipeline network processor performs direct lookups to identify downstream ports associated with the upstream port over which the packet is received. A direct lookup is also performed to obtain the necessary header with which to forward the packet. A copy of the packet with the correct header is then sent to each identified downstream port.

Pipeline network processors are designed to forward Internet Protocol (IP) packets at an extremely high data rate in excess of two million packets per second. Pipeline network processors typically have a limited number of instruction cycles and memory to perform the applicable task. Implementing features or functions that do not fit the traditional packet forwarding model is a challenging endeavor and may have a negative impact on normal packet forwarding functions such as packet filtering and quality of service processing.
With respect to cable modem routers, one of the required and commonly used features is Multicast Echo. This feature enables cable media to behave like a standard shared media, as in Ethernet, in a local area network environment for Internet Protocol multicast traffic. Cable is a unidirectional media wherein packets are sent from customer premises equipment through a cable modem to an upstream port of a cable modem termination system. Packets are also sent from a downstream port of the cable modem termination system through the cable modem to the customer premises equipment. From a cable standpoint, the configured combination of one or more upstream ports and one or more downstream ports is known as a Media Access Control (MAC) Domain which is a cable media equivalent of a local area network segment.
In a local area network environment, a device is able to receive all multicast packets sent by other devices on the same segment. However in a cable environment, only half of the multicast processing has been completed when a multicast packet is received at an upstream port. The other customer premises equipment connected to the downstream port of the MAC Domain did not receive the multicast packet. Though other devices on the downstream port may be known to be present, normal multicast processing does not add the input interface to the list of output interfaces for multicast traffic and thus no relationship information among ports. This is intentionally done and required by the multicast protocol to avoid multicast traffic loops. The Multicast Echo feature overrides normal multicast processing and permits multicast packets to be forwarded to downstream ports of the MAC Domain.
When a high speed, high end cable modem termination system is developed using a pipeline network processor to forward packets between a large number, several hundred, of cable interfaces and a large number of trunk interfaces, implementing the Multicast Echo feature for the cable interfaces becomes extremely difficult. The cable line cards strip off the Data Over Cable (DOCSIS) header before passing the packet to the pipeline network processor. The pipeline network processor needs to add the original DOCSIS header to the multicast packet in order to forward the packet to one or more downstream ports. There needs to be support for tens of thousands of multicast groups, different service flows, and many MAC Domains. The amount of memory necessary to hold such large data structures and the processing cycles required to search them would preclude the use of a pipeline network processor in terms of cost and performance. A single multicast flow, which is less than 1% of the total traffic, could severely impact the processing of the other 99% of the traffic. Therefore, it is desirable to implement a Multicast Echo feature using a pipeline network processor despite its limited resources.

System and method for sending a packet to multiple destinations using a pipeline network processor


A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the pair of system busses, and enable both of the system memory sections coupled to such pair of system busses to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the pair of system busses.

This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or xe2x80x9cfront endxe2x80x9d, controllers (or directors) and xe2x80x9cback endxe2x80x9d disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled xe2x80x9cSystem and Method for Disk Mapping and Data Retrievalxe2x80x9d, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a system bus made up of a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.
In accordance with the present invention, a data storage system is provided wherein a host computer is coupled to a bank of disk drives through an interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A system bus is coupled to the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus, such directors being configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the system bus, and enable both of the memory sections coupled to such system bus to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the system bus.
In accordance with another feature of the invention, the interface includes a system memory having a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A system bus comprising a pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the pair of system busses, and enable both of the system memory sections coupled to such pair of system busses to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the pair of system busses.
In accordance with another feature of the invention, during the dual-write mode, the directors store therein bursts of the data to be transferred between the host computer and the bank of disk drives. Each burst of data stored in the director is then transferred to one of the pair of system busses coupled to such director during one memory cycle and, during the next memory cycle, the same burst of data is then transferred again, but this time to the other one of the pair system busses coupled to such director. Thus, the same stored burst of data is transferred sequentially to both the pair of system busses coupled to such director. The director sequentially enables both of the memory sections coupled to both such pair of system busses to have written therein, at the same addressable locations, the same data burst which had been sequentiality transferred to each of the pair of system busses coupled to the director. Thus, after the pair of system memory cycles, the burst of data and a copy of such burst of data are stored in the same addressable location of both memory sections. Consequently, redundant data bursts are stored in the system memory.
In accordance with another feature of the invention, a dual-write bus is coupled to the plurality of directors. Each one of the directors includes: (a) a director memory for storing the burst of data fed thereto from the either the host computer or the bank of disk drives; and, (b) a dual-write controller. The dual-write controller is adapted to: (i) provide a dual-write interrupt on the dual-write bus in response to a dual-write mode command fed to the system; (ii) receive a dual-write interrupt produced on the dual-write bus; and (iii) in response to the dual-write interrupt received on the dual-write bus, sequentially place the burst of data stored in the director memory on the pair of system busses for sequential storage in both of the system memory sections at the same one of the addressable locations.
In accordance with still another feature of the invention, the system is adapted to return to a non-dual-write mode when each of the plurality of directors is reset to a non-dual-write mode in response to a reset condition provided to the system. When returned to the non-dual-write mode, each one of the directors is adapted to place the burst of data stored in the director memory on a selected one of the pair of system busses for storage of such stored data in the one of the system memory sections coupled to such selected one of the pair of system busses.
In accordance with yet another feature of the invention, each one of the directors is adapted to detect a fault in the transfer of the data between the director and each one of the pair of system memory sections. In response to a detected fault between the director and one of the pair of system memory sections, each one of the directors is adapted to force subsequent data transfers between the director and the other one of the pair of system memory sections.


A multi-stage pipeline analog-to-digital converter employs an internal digital domain error detection and calibration algorithm to eliminate accumulated digital truncation errors to thereby improve its accuracy and linearity.

The present invention relates generally to analog-to-digital converters, hereinafter referred to as ADCs, and, more particularly, to a pipeline ADC employing internal digital calibration to improve linearity of the ADC.
Multi-stage pipeline ADCs exhibit the distinct advantage of achieving a high sample rate for low power, compared to other architectures such as flash and successive approximation. For this reason, pipeline ADCs have been widely used in many applications, especially those that can tolerate this architecture""s inherent delay between the time the input signal is sampled and the time the digitized output becomes available. Exemplary of these applications are image capture applications such as ultrasound, video cameras, scanners, etc., as well as intermediate frequency demodulation in wireless communications applications and various laboratory instrumentation applications.
Recent advancements in these applications have pushed the resolution requirement for ADCs to 12 bits or higher. In order to meet this level of performance demand, a number of digital domain error calibration techniques have been developed. In the case of multi-stage pipeline ADCs with 1.5 bits per stage, U.S. Pat. No. 5,465,092 to Mayes et al., U.S. Pat. No. 5,499,027 to Karanicolas et al., and U.S. Pat. No. 5,510,789 to Lee describe a means for detecting and correcting errors in reconstruction digital-to-analog converters in each stage. This 1.5 bits per stage architecture is simple to design and also to calibrate because all stages have the same circuit topology. Its disadvantage is that it inherently consumes more power than a multi bits per stage counterpart described in Cline et al., xe2x80x9cA Power Optimized 13-b 5M samples/s Pipelined Analog-to-Digital Converter in 1.2 um CMOS,xe2x80x9d IEEE Journal of Solid State Circuits, March, 1996, pp. 294-303.
Lee et al., xe2x80x9cDigital-Domain Calibration of Multistep Analog-to-Digital Converters,xe2x80x9d IEEE Journal of Solid State Circuits, December, 1992, pp. 1679-1688, proposes a means of digitally calibrating a multi bits per stage pipeline ADC. This reference teaches a means for detecting an error between two adjacent codes of a multiplying DAC (MDAC) composed of a capacitor array and an operational transconductance amplifier (OTA), by the subsequent stages of the ADC. As each code transition error or differential linearity error (DLE) is measured, it is digitally accumulated to derive the linearity error of all codes or integral linearity error (ILE). As acknowledged by the authors in this reference, this digital accumulation technique inherently suffers from digital truncation errors, which increase as the resolution of each stage increases.
The prior art circuits of FIGS. 1A and 1B serve to measure an MDAC""s segment error for code transition from j to j+1. The MDAC is composed of the operational transconductance amplifier (OTA), feed back capacitor Cf, the binary weighted capacitor array, the sampling switch SW, and other switches that selectively connect bottom plates of the capacitor array to terminals Vref or AGND, or to an output from the previous stage. The latter switches are not shown in FIGS. 1A and 1B for clarity. The non-overlapping clock signals in FIG. 1C control this two phase operation. During the first clock phase, Phase 1, the clock signal qs is high. The clock signal qg is high in the second clock phase, Phase 2. The clock signal qsp controls the sampling switch SW, and is identical to clock signal qs except that it has a preceding falling edge. In Phase 1, the bottom plates of the capacitor array are driven to the voltages at either of terminals Vref or AGND in accordance to the digital input j. At the same time, OTA is configured to be a unity gain buffer, and the bottom plate of capacitor Cf connects to terminal AGND. At the end of Phase 1, the sampling switch SW opens and traps the charge on the common top plate of all the capacitors. In Phase 2, the bottom plates of the capacitor array are driven according to the digital input j+1. The feedback capacitor Cf is connected between the output and the negative input of the OTA, thereby closing the loop. The output of OTA at the end of Phase 2 would ideally be equal to Vref/2. Any deviation from this ideal voltage is an error voltage, or DLE, associated with the code transition between code j and j+1. The error voltage is digitized by the subsequent stages of the ADC. This sequence is repeated for every code increment, and the results are incrementally accumulated in digital domain to derive the digital representation of ILE for all codes of the MDAC. The accumulation of code transition errors in digital domain by definition accumulates the digital truncation errors of all code transition errors.
U.S. Pat. No. 5,870,041 to Lee et al. recognizes this digital truncation error problem and attempts to reduce the truncation error just by increasing resolution of the over-all ADC used during error detection. This approach is common to minimizing truncation errors in general, but it does not solve the fundamental problem of truncation error limitations that stem from the error detection algorithm originally proposed in the above-cited paper authored by Lee et al. It also requires that all analog signals must settle to a higher resolution level with a small lsb size, which limits the maximum speed attainable for a given technology and power consumption.
Another practical limitation of the prior art circuits of FIGS. 1A and 1B is that the voltage reference, Vref changes between the two clock phases, due to its finite output impedance, thus limiting its capability to absorb switching transients and maintain the output voltage. This limitation becomes more pronounced for higher resolution, higher speed ADCs.
It would therefore be advantageous to provide a digital domain error detection and calibration algorithm for a multi stage pipeline ADC that is free from accumulation of digital truncation errors to thereby provide a multi stage pipeline ADC of inherently higher accuracy.
It would also be advantageous to provide a digital domain error detection method which exhibits greatly reduced sensitivity to changes in the reference voltage from one phase of operation to the other.
It would be further advantageous to provide a multi-stage pipeline ADC architecture that incorporates digital circuitry to perform the aforementioned digital domain error detection and calibration algorithm.
It would be further advantageous to provide a high speed, high resolution multi-stage pipeline ADC which offers superior performance with respect to accuracy, linearity, offset, gain error, total harmonic distortion (THD), spurious free dynamic range (SFDR), signal to noise ratio (SNR), and effective number of bits (ENOBs).
It would also be advantageous to provide a complementary metal oxide semiconductor process for implementing a multi stage pipeline ADC.

Pipeline analog-to-digital converter with on-chip digital calibration


A cure catalyst is provided. The cure catalyst may include a Lewis acid and one or both of a nitrogen-containing molecule or a non-tertiary phosphine. The nitrogen-containing molecule may include a mono amine or a heterocyclic aromatic organic compound. A curable composition may include the cure catalyst. An electronic device may include the curable composition. Methods associated with the foregoing are provided also.

The invention includes embodiments that relate to a curable composition and an associated method. The invention includes embodiments that relate to a device incorporating the composition.
Some electronic components may be connected by eutectic tin/lead (Sn/Pb) solder, which has a melting point at about 183 degrees Celsius (° C.). It may be desirable to use a lead-free solder rather than the eutectic solder. But, lead-free solder may have a different melting point than the eutectic solder. A possible replacement solder may have a melting point in range of from about 218 degrees Celsius to about 230 degrees Celsius. A higher melting point of the solder may shift peak temperature during a reflow from about 220 degrees Celsius to a new peak in a range of from about 240 degrees Celsius to about 260 degrees Celsius. Commercially available no-flow underfills (NUF) may respond to the higher temperature by initiating an overly fast cure that may restrict solder ball and prevent formation of good electrical connections.
Attempts to produce a catalytic material for an NUF for use with a lead-free solder have been problematic. Problems encountered may include an unacceptable electrical yield. It may be desirable to have a curable composition usable as an underfill material with lead-free solder having improved or different properties.

Cure catalyst, composition, electronic device and associated method


The invention relates to a compound comprising a labeled nickel complex (FIG. 1) that is used to detect and purify nucleic acid sequences by forming an adduct between a specific nucleic acid base and the labeled nickel complex. The adduct can also be purified through a separation process, such as affinity chromatography

The present invention relates to a nickel-based reagent that covalently binds to a specific nucleotide. The present invention also relates to a nickel-based salicylimine complexed to a histidine containing organic compound, as well as a nickel-based complex comprising a detectable label.
There are a variety of methods for detecting DNA/RNA-protein interactions and some depend on cross-linking. However, to the inventors' knowledge, there is no current technology that uses a nickel-based complex to covalently bind to a specific nucleotide and detect such binding and optionally isolating the DNA regions through use of a labeled complex.
A salicylimine containing nickel complex or any square planar, 4-coordinate nickel complex system linked with any detectable label is sufficient to practice the present invention. Moreover, the salicylimine containing nickel group complexed with the N-terminus of a polypeptide where the terminal amino acid is followed by a histidine or histidinyl residue results in a nickel based reagent that has additional desirable functional capabilities. If this terminal amino acid sequence is not naturally derived, then genetic manipulation may be used to append such a terminus on to any polypeptide of interest. For non-natural amino acids, chemical synthesis is preferred. Further, a semi-synthesis approach can be taken. Combining genetic and chemical means to obtain an amino acid sequence complexed with the salicylimine containing nickel complex is encompassed by the present invention. In addition, this complex may be used to add an aromatic aldehyde selectively to a nucleotide sequence which can be used as a handle for further modification or identification. Furthermore, whereas single-stranded regions of nucleic acids typically react more readily with various chemical and biochemical reagents, their detection and characterization method require prior knowledge of the target sequence. A nickel complex-identifier (such as biotin) of the invention will allow for purification and identification of the nucleic acid sequence without prior knowledge of the reactive sequence. Whereas there is no current reagent that selectively couples to and stays attached to the bound nucleotide, the nickel reagent of the invention allows for the detection of the bound sequence as well as isolation of the nucleotide region.
Shearer, J. M. and Rokita, S. E., Bioorg. Med. Chem. Lett. 9, 501-504, (1999), discloses the preparation of diamine compound for synthesis of a water-soluble Ni (II)-salen (salicylaldehyde) complex. This reference discloses a synthesis method for a simple, unconjugated Ni (Salen) called TMAPES. However, this reference does not disclose the attachment of a label or an adduct to this complex so that the complex can be detected biochemically.
Liang et al., J. Am. Chem. Soc., 120, 248-257 (1998), discloses a Ni (II) linked metallopeptide that is used to selectively degrade DNA through a minor groove binding interaction. However, this reference does not disclose or suggest the covalent linkage between a nickel containing complex and a specific nucleotide.
Routier et al., Bioconjugate Chem., 8, 789-792 (1997), discloses a conjugate between a salen and any biologically active molecule. The complex uses copper. However, such a copper conjugate cleaves nucleic acids non-specifically while non-covalently binding to the backbone of the nucleic acid. This is contrary to the present invention, which is directed to specific coupling of the nickel-containing complex to a nucleotide base.
Routier et al., Biooragnic & Medicinal Chemistry Letters, Vol. 7, No. 1, pp. 63-66 (1997), discloses a Ni-Salen complex. However, in this reference, coupling the Ni-Salen complex with the terminal N group would typically create a neutral compound that would be insoluble and not useful in coupling to nucleic acid bases.
Bhattacharya and Mandal, J. Chem. Soc., Chem. Common., 1995, pp. 2489-2490, discloses a Co-Salen chemistry. Again, this reference does not disclose formation of an adduct with nucleic acid.
Tanaka et al., Bull. Chem. Soc., Jpn. 70, 615-629 (1997), discloses the synthesis of a Cu-Salen molecule. This reference does not disclose or suggest formation of an adduct with nucleic acids.
Gravert and Griffin, J. Org. Chem., 58, 820-822 (1993), discloses a Mn-Salen complex. This reference does not disclose the formation of an adduct with nucleic acids.
Chen and Lu, Journal of the Chinese Chemical Society, 45, 611-617 (1998), discloses a Ru-Salen complex. This reference does not disclose or suggest the formation of an adduct with nucleic acids.
Jacquet et al., J. Am. Chem. Soc. 119, 11763-11768, (1997), discloses a Ru metal-Salen complex which requires photo-activation.
Gravert and Griffin, Inorg. Chem., 35, 4837-4847 (1996), discloses a Mn-Salen complex. However, this reference does not disclose the formation of an adduct with nucleic acids.
Brown et al., Biochemistry, 34, 4733-4739 (1995), discloses a nickel-His-tag and a nickel-glycylglycylhistidine for protein-protein cross-linking. However, the reference does not disclose nickel-dependent protein-nucleic acids or nucleic acid-biotin cross-linking.
U.S. Pat. Nos. 5,272,056 and 5,504,075 disclose a Ni(TMAPES) complex but fails to disclose attaching a detectable label to this complex. These two patents are incorporated herein by reference in their entirety.
As the literature described above shows, no salicylimine containing nickel complex is known in the prior art for the application of directly detecting or isolating nucleic acids. There is a need in the art for more effective method of studying chromosome structure, detecting specific nucleotide bases, and studying protein-DNA interactions.
The invention provides a salicylimine containing nickel complex for detecting protein-nucleic acid interactions and the presence of single-stranded regions of nucleic acids formed during gene expression, macromolecular assembly and chromatin reorganization.

Nickel-based reagents for detecting DNA and DNA-protein contacts


Playlist bookmarking may be provided. First, a content program from a playlist may be displayed on a first user device. The content program may then be paused and a time stamp may be placed in the playlist at a point where the content program was paused. Next, the time stamped playlist may be transmitted to a server. At a second user device, the time stamped playlist may be received from the server and the content program may be displayed from the playlist from the point in the content program corresponding to the time stamp.

As music storage and playback using personal computers became common, the term "playlist" has been adopted by various media player software programs intended to organize and control music or video on a computer. Such playlists may be defined, stored, and selected to run either in sequence or, if a random playlist function is selected, in a random order. Playlists' uses include allowing a particular desired musical or video atmosphere to be created and maintained without constant user interaction, or to allow a variety of different styles of music and video to be played without maintenance.


An overlay protocol and system for allowing multicast routing in the Internet to be performed at the application level. The overlay protocol uses “native” Internet multicast and multicast routing protocols to route information, according to overlay routing tables. Overlay groups are mapped to native multicast groups to exploit native multicasting in regional or local forwarding domains. Use of the overlay protocol allows overlay distribution to be handled in a more intelligent and bandwidth-managed fashion. Overlay routers are placed at each of several local area networks, Internet service provider's point of presence, enterprise, or other cohesively-managed locations. The overlay computers are configured according to bandwidth and security policies, and perform application-level multicast distribution across the otherwise disjoint multicast networks by using the overlay routing. The result is an overlay multicast network that is effectively managed according to local network management policies. Application-level control can be applied to the transferred data at the overlay routers.

As the Internet gains in popularity it is desirable to allow broadcasts of live media, such as a television program or radio program, over the Internet. However, a problem with such "streaming media" broadcasts is that they require very high data transfer rates across many servers, routers and local area networks that form the Internet. Because of this, high-quality, scalable broadcasts, or "multicasts," of streaming media information to massive numbers of end-users at once over the Internet have not been achieved to date.
Examples of attempts to design and deploy multicast systems for the Internet include systems by RealNetworks and Broadcast.com. RealNetworks has built an Internet broadcast infrastructure called the Real Broadcast Network (RBN) while Broadcast.com has partnered with Internet Service Providers (ISPs) and content providers to build a broadcast system based on native Internet multicast routing. A typical streaming broadcast consists of a server that unicasts a User Datagram Protocol (UDP) flow to each requesting client. Bandwidth is managed very crudely by simply limiting the number of simultaneous active flows via some simple configuration hook at the server. While this approach works for today's demands, it wastes network bandwidth and cannot scale to very large audiences anticipated in the future.
Although some existing products (like NetShow and Cisco's IP/TV) support multicast, Internet Service Providers (ISPs) and enterprise network managers have been slow to adopt multicast because it is difficult to configure, manage, and debug. For some companies, these deployment problems are crucial barriers because they view multicast as critical for their long-term viability and feel that failure to successfully integrate multicast could compromise their mission.
A successful Internet broadcast system depends on its ability to broadcast audio and video programming to a large number of simultaneous users. Two approaches for broadcasting streaming media are replicated unicast (one user per stream) and multicasting (multiple users per stream).
While unicast delivery has enjoyed tremendous success as the-fundamental building block of the Internet, multicast has proven far more complex and many technical barriers remain that prevent multicast from being deployed across the wide area. Despite a decade of research and development, interdomain multicast routing has yet to be successfully realized and there are many reasons to believe that multicast, in its present form, may never be universally deployed throughout the Internet. In this case, applications that assume ubiquitous multicast connectivity to attain scalable performance will never become feasible. On the other hand, multicast, when restricted to a singly administered network domain, has been much easier to configure and manage, and for this reason, has been a resounding success in isolated deployments. That is, it's easy to build an isolated multicast "cloud" as long as it doesn't span multiple administrative domains and involve highly heterogeneous equipment with different multicast implementations.
While uniform and homogeneous multicast clouds can effectively carry multicast traffic that is isolated to LANs or autonomous corporate networks, a wide range of compelling applications, such as streaming media broadcasts, are potentially enabled by interconnecting the isolated multicast clouds into a very large-scale distribution network. However, attempts to use wide area multicast routing protocols to solve this problem have failed. Another problem with interconnecting multicast clouds has been lack of control over the multicast traffic from domain to domain. This implicates not only bandwidth considerations, but security issues as well.
Thus it is desirable to complement and enhance the vast array of existing servers and end-clients with a state-of-the-art system that provides an improved network infrastructure for achieving multicasting of information. Such a system should enhance existing digital audio/video/media applications and enable them to work more effectively at large scale and across heterogeneous environments. The system should provide flexible bandwidth management and diagnostic tools to network managers such as by providing localized control over traffic and content of multicast data. The system should make use of existing, widely deployed communication protocols and procedures to achieve efficient transfer of information.

Performing multicast communication in computer networks by using overlay routing


A light-emitting device, comprising: a multi-layer stack of materials supported on an optically transparent support member, a first spatial filter, and a second spatial filter spaced from the first spatial filter. The multi-layer stack including at least one organic light-emitting layers, an anode layer, and a cathode layer. The first spatial filter is disposed intermediate the multi-layer stack of materials and the second spatial filter.

Organic electro-luminescent devices are well known. Organic electroluminescent (EL) devices are electronic devices that emit light in response to an applied potential. In simplest form, an organic EL device is comprised of an anode for hole injection, a cathode for electron injection, and an organic medium sandwiched between these electrodes to support charge recombination that yields emission of light. These devices are also commonly referred to as organic light-emitting diodes, or OLEDs.
Organic light-emitting diode (OLED) technology incorporates organic luminescent materials that, when sandwiched between electrodes and subjected to an electric current (AC or DC), produce intense light of a variety of colors. These OLED structures can be combined into the picture elements or pixels that comprise a display, such as flat-panel displays in watches, telephones, laptop computers, pagers, cellular phones, calculators, and the like. OLEDs are also useful in a variety of applications as discrete light-emitting devices.
Optically excited organic dye lasers, in the liquid state, are well-known sources of powerful and highly coherent tunable laser emission. Two references which describe such lasers are: (1) F. P. Schäfer (ed.), Dye Lasers (Springer, Berlin, 1990), and (2) F. J. Duarte (ed.), High Power Dye Lasers (Springer, Berlin, 1991).
While such lasers can be powerful, these lasers can be rather large and complex and their attractiveness diminishes for many low power applications.
Recently, organic dye lasers have made a successful transition into the solid-state using highly homogeneous gain media comprised of dye-doped polymers. References which describe these developments include: F. J. Duarte, Appl. Opt. 33, 3857 (1994).; A. Maslyukov, S. Solokov, M. Kaivola, K. Nyholm, and S. Popov, Appl. Opt. 34, 1516 (1995); and A. Costela, I. Garcia-Moreno, and R. Sastre, Phys. Chem., Chem. Phys. 5, 4745 (2003).
Multiple-prism grating tunable laser oscillators, using dye-doped organic matrices, have been reported to yield nearly diffraction limited laser beams and single-longitudinal-mode emission at power levels in the kW regime. Refer to F. J. Duarte, Appl. Opt. 38, 6347 (1999).
Although these may be attractive for some applications, these lasers still require another laser as source of excitation. In this regard, it would be technologically advantageous to have semiconductor organic sources of coherent radiation excited directly by electrical means. Optically excited organic semiconductor films have been reported to lase by several authors. See, for example, S. Riechel, U. Lemmer, J. Feldman, S. Berleb, A. G. Mückl, W. Brütting, A. Gombert and W. Wittwer, Opt. Lett. 26, 593 (2001); and W. Holzer, A. Penzkofer, T. Pertsch, N. Danz, Abräuer, E. B. Kley, H. Tillmann, C. Bader, and H. H. Hörhold, Appl. Phys. B. 74, 333 (2002). See also Heeger and Bradley R. Xia, G. Heloitis, D. D. C. Bradley, Applied Physics Letters, 82 3599 (2003); and G. Heliotis, D. D. C. Bradley, G. A. Turnbull and I. D. W. Samuel, Applied Physics Letters, 81 415 (2002). A further reference is M. D. McGehee, M. A. Díaz-García, F. Hide, R. Gupta, E. K. Miller, D. Moses, and A. J. Heeger, Applied Physics Letters, 72, 13 1536 (1998).
As such, the subject of direct electrical excitation of organic lasers has been an issue discussed, for some time, in the open literature. For example, see: G. Kranzelbinder and G. Leising, Rep. Prog. Phys. 63, 729 (2000); V. G. Kozlov, P. E. Burrows, G. Parthasarity, and S. R. Forrest, Appl. Phys. Lett., 74, 1057 (1999); and M. A. Baldo, R. J. Holmes, and S. R. Forrest, Phys. Rev. B., 66, 35321 (2002).
It has been recognized that two of features of laser radiation are directionality of the emission, that is, low beam divergence, and spectral coherence, also known as narrow-linewidth emission. Therefore, any incipient study of a potential electrically excited organic laser must include these two basic parameters.
Accordingly, there exists a need for a direct electrical excitation of an electrically driven organic laser which provides for low beam divergence and spectral coherence.
The present invention provides an electrically driven organic laser which provides for low beam divergence and spectral coherence.

Electrically excited organic light-emitting diodes with spatial and spectral coherence


A method is disclosed for thermal management of an engine comprising a continuously variable transmission. The method includes an engine capability module storing a torque-speed map comprising a first region where the engine inefficiently regenerates an aftertreatment device, a second region where the engine efficiently regenerates the aftertreatment device, and a third region where the engine is not capable of regenerating the aftertreatment device. The method further includes an aftertreatment determination module determining a regeneration index, an operating conditions module determining an engine speed and an engine load, and a speed-load adjustment module adjusting a speed-load target. The method further includes the speed-load adjustment module adjusting the speed-load target to a preferred region along equal power curves of the torque-speed map based on the regeneration index.

1. Field of the Invention
This invention relates to a thermal management of a combustion engine and more particularly relates to supporting the efficient regeneration of an aftertreatment device such that an optimal fuel efficiency is achieved.
2. Description of the Related Art
Consumer demand for the benefits provided by the internal combustion engine, environmental concerns, and falling reserves of fossil fuel continue to spur improvements in the durability, fuel efficiency, and the emission's quality of the combustion engine. Competing performance demands, such as increasing fuel efficiency while reducing harmful emissions, provide ongoing engine development challenges. Many techniques of reducing emissions are well known in the art and substantially all of them adversely affect fuel efficiency. For example, a common catalytic converter must periodically achieve certain temperature thresholds, as a maintenance step, to oxidize particulates within the device (i.e. regenerate). In an alternate example, a diesel particulate filter collects soot that must be continually, or periodically, burned off by temperature increases in the exhaust stream passing through the device.
The preceding aftertreatment device examples illustrate the need of most aftertreatment devices for requisite heat that typically must be provided via the exhaust stream passing through the aftertreatment system. One common method to increase the temperature of the exhaust stream consists of adding extra fuel in-cylinder and/or down stream of an exhaust manifold during a portion of the combustion cycle (i.e. fuel dosing). Depending on the timing and the location where additional fuel is introduced efficiency may be reduced by a phase disturbance of the combustion cycle, unburned fuel lingering in the exhaust stream, and/or by decreasing the air to fuel ratio.
Another common approach to raise the temperature in the exhaust stream includes restricting the amount of air available for combustion, once again effectively reducing the air to fuel ratio. One example of how this may be accomplished includes creating a restriction in the exhaust stream, such as by choking the exhaust flow through a variable geometry turbocharger. Once again, however, this method generates a backpressure on the engine, which reduces the work efficiency of the engine. Temperature increases may need to be either periodic and/or fall within specific ranges to limit the amount of nitrous oxides that may be generated in the high heat environment. Many present applications of the internal combustion engine face thermal control challenges that may impede the optimization of fuel efficiency, degrade the power output, generate thermal stress on aftertreatment components, and reduce the overall effectiveness of the aftertreatment system.

Apparatus, system, and method for thermal management of an engine comprising a continuously variable transmission