The present invention relates to overdrive circuits for generating an operational potential of a sense amplifier. For example, a switch circuit is used to connect a drive node of the sense amplifier with a overdrive potential generation circuit for generating an overdrive potential to be applied to bit lines. A restoration potential generation circuit comprises a push-pull regulator circuit for generating a restoration potential to be applied to bit lines. Consequently, the restoration potential generation circuit can directly connect with the sense amplifier""s drive node.

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-204104, filed Jul. 5, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device. More specifically, the invention relates to an overdrive power supply circuit used as a power supply circuit of a sense amplifier.
Conventionally, DRAM uses an overdrive power supply circuit (hereafter referred to as the overdrive circuit) for highly sensitive and fast sense operations. For a sense operation on a bit line, a sense amplifier""s positive electrode is supplied with an electric potential (so-called overdrive potential) which is higher than a restoration potential for the bit line.
FIG. 12 shows a configuration example of a conventional overdrive circuit. In this figure, one external power supply (VCC) 101 connects with an overdrive potential generation circuit (VIIAG) 102. The other external power supply (VCC) 103 connects with a restoration potential generation circuit (VAAG) 104. The overdrive potential generation circuit 102 and the restoration potential generation circuit 104 connect with a switch circuit 105. The switch circuit 105 connects with a sense amplifier driver (PSAD) 106. The sense amplifier driver 106 connects with a sense amplifier (S/A) 107. The sense amplifier 107 connects with a sense amplifier driver (NSAD) 108. The sense amplifier driver 108 connects with an external power supply (GND) 109.
The overdrive potential generation circuit 102 generates an overdrive potential (VIIA) for overdriving (amplifying) an electric potential of the bit line during a sense operation. This overdrive potential is also used as a power for peripheral circuits. The restoration potential generation circuit 104 generates a restoration potential (VAA) for restoring an electric potential of the bit line after the overdrive. The switch circuit 105 selects one of the overdrive potential and the restoration potential, and supplies it to the sense amplifier driver 106.
FIG. 13 shows a configuration of the above overdrive circuit in more detail. The overdrive circuit needs to suppress output impedance. To configure the overdrive circuit using a MOS (Metal Oxide Semiconductor) transistor, a source follower (common drain amplifier) is used.
Normally, the overdrive potential generation circuit 102 and the restoration potential generation circuit 104 both generate a positive potential. Namely, the overdrive potential generation circuit 102 is configured by using an n-type MOS transistor 102a as a source follower. Namely, the restoration potential generation circuit 104 is configured by using an n-type MOS transistor 104a as a source follower.
The switch circuit 105 comprises p-type MOS transistors 105a and 105b. In this example, the p-type MOS transistors 105a and 105b also work as the sense amplifier driver 106.
The sense amplifier 107 comprises p-type MOS transistors 107a and 107b and n-type MOS transistors 107c and 107d. The p-type MOS transistor 107a and the n-type MOS transistor 107c share the drain and are connected serially. The p-type MOS transistor 107b and the n-type MOS transistor 107d share the drain and are connected serially. A bit line BLt is connected to a connection point between the p-type MOS transistor 107a and the n-type MOS transistor 107c and gates of the p-type MOS transistor 107b and the n-type MOS transistor 107d. A bit line BLc is connected to a connection point between the p-type MOS transistor 107b and the n-type MOS transistor 107d and gates of the p-type MOS transistor 107a and the n-type MOS transistor 107c. The bit line BLc is complementary to the bit line BLt.
The power supply line 110 connects the sense amplifier 107""s positive electrode (connection point between sources of the p-type MOS transistors 107a and 107b) with the switch circuit 105 (connection point between drains of the p-type MOS transistors 105a and 105b). The sense amplifier driver 108 is connected to the sense amplifier 107""s negative electrode (connection point between sources of the n-type MOS transistors 107c and 107d). The sense amplifier driver 108 comprises an n-type MOS transistor 108a.
FIG. 14 shows a layout structure of a DRAM memory core using the above overdrive circuit. Especially, the figure shows an arrangement of the overdrive circuit and its power supply wiring. AS shown in this figure, a plurality of cell arrays (cells) 111 is arranged in a matrix. The sense amplifiers 107 are placed on and under each cell array 111 along a row direction. The segment row decoders (SRD) 112 are placed to the right and left sides of each cell array 111 along a column direction. A circuit area (SSC1) 113 is provided at each intersection point between the sense amplifier 107 and the segment row decoder 112.
A memory core periphery (one end of the column direction) is provided with a main row decoder (MRD) 114 corresponding to each column for the cell array 111. A circuit area (SSC2) 115 is provided on and under each main row decoder 114 (row direction) corresponding to the circuit area 113.
A memory core periphery (one end of the row direction) is provided with a plurality of overdrive potential generation circuit blocks 116 and a plurality of restoration potential generation circuit blocks 117. In this example, each circuit block 116 comprises the overdrive potential generation circuit 102 (the n-type MOS transistor 102a) and the switch circuit 105 (the p-type MOS transistor 105a). Likewise, each circuit block 117 comprises the restoration potential generation circuit 104 (the n-type MOS transistor 104a) and the switch circuit 105 (the p-type MOS transistor 105b).
The circuit blocks 116 and 117 are connected to the sense amplifier 107 via the power supply line 110. The power supply line 110 comprises, say, a first-level metal wire 110a and a second-level metal wire 110b. The metal wire 110a connects with the sense amplifier 107""s positive electrode. The metal wire 110b connects with the circuit blocks 116 and 117. The metal wire 110a and the metal wire 110b are connected with each other in the circuit area 115 and the sense amplifier 107.
However, the above configured overdrive circuit has the following problems.
1. An operation in a long RAS cycle requires a long restoration time. At this time, the potential level creeps, causing an excessively high restoration potential.
2. In the event of an excessive overdrive, there is a limited capability of decreasing an overdrive potential.
3. The overdrive potential generation circuit 102 is also used as the power supply circuit for the peripheral circuit. Because of this, a power supply noise during a sense operation propagates to the peripheral circuit.
4. There is a long distance between the restoration potential generation circuit 104 and the sense amplifier 107. It takes time to supply a restoration potential.
As mentioned above, the prior art can provide highly sensitive and fast sense operations. When a bit line potential after the overdrive becomes too low or high with reference to the restoration potential, however, it is difficult to control this potential to a desired potential.
It is an object of the present invention to provide a semiconductor device which can stabilize a restoration potential level when the overdrive technique amplifies a bit line potential and the amplified bit line potential becomes too higher or lower than the restoration potential. It is also an object to provide a semiconductor apparatus which can easily control the overdriven bit line potential to a desired potential.
In order to attain the above objects, according to a first aspect of the present invention, there is provided a semiconductor device comprising: a sense amplifier for amplifying a bit line potential; a first generation circuit for generating an overdrive potential needed for a sense operation of the bit line according to the sense amplifier; a switch circuit for controlling supply of the overdrive potential to a positive electrode of the sense amplifier; and a second generation circuit comprising a push-pull regulator circuit connected to the positive electrode of the sense amplifier, wherein the second generation circuit generates a restoration potential of the overdriven bit line.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: a plurality of memory cell blocks arranged in a matrix; a plurality of sense amplifiers for amplifying a bit line potential; a plurality of main row decoders for controlling drive of one main word line for controlling selection of a plurality of word lines; a plurality of segment row decoders driven by selecting a specific word line from the plurality of word lines corresponding to the one main word line; a plurality of first generation circuits for generating an overdrive potential needed for a sense operation of the bit line according to the plurality of sense amplifiers; a plurality of switch circuits for controlling supply of the overdrive potential to respective positive electrodes of the plurality of sense amplifiers; and a plurality of second generation circuits comprising push-pull regulator circuits respectively connected to positive electrodes of the plurality of sense amplifiers, wherein the plurality of second generation circuits generate a restoration potential for the bit line after overdrive, wherein the plurality of memory cell blocks and the plurality of sense amplifiers are alternately arranged in a first direction; the plurality of segment row decoders are arranged respectively adjacent to the plurality of memory cell blocks in a second direction orthogonal to the first direction; the plurality of main row decoders are arranged at one end of the second direction; the plurality of switch circuits are arranged in a plurality of first regions adjacent to the plurality of sense amplifiers; the plurality of first generation circuits are arranged at one end of the first direction; and the plurality of second generation circuits are arranged in a plurality of second regions adjacent to the plurality of main row decoders.
According to the semiconductor device of the present invention, the restoration potential can be driven to be positive or negative. This can suppress potential level inconsistency of the restoration potential due to overdrive timing inconsistency.
Especially, the second generation circuit can be directly connected to the sense amplifier""s positive electrode. This can decrease resistance between the sense amplifier and the regulator circuit. It is possible to speed up a supply of the restoration potential to the bit line.
The first generation circuit can be configured through the use of a dedicated power supply circuit which is independent of a power supply circuit for driving a peripheral circuit. In this case, it is possible to prevent a power supply noise from being propagated to the peripheral circuit during a sense operation.
Since the regulator circuit is provided near the sense amplifier, it is possible to further decrease resistance between the sense amplifier and the regulator circuit. Therefore, it is possible to further speed up a supply of the restoration potential to the bit line.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


An image processing apparatus functions as a server. When a reference request is received from a client or a user's instruction for transmitting such address data to a client is received, and the address data to be transmitted has no domain name described therein, the apparatus complements the address data with a domain name, and then sends the complemented address data to the client. This makes it possible to export address data correctly to a designated destination, and to reduce failure of authentication.

1. Field of the Invention
The present invention relates to an image processing apparatus which functions as a server communicable with a client image processing apparatus via a network, and a method of controlling the image processing apparatus.
2. Description of the Related Art
Conventionally, there has been disclosed a technique in which e.g. two MFPs (Multiple Function Peripherals) are assigned functions of a server and functions of a client, respectively, and the client MFP acquires and utilizes address data acquirable from or stored in the server MFP. This kind of technique enables a client to perform transmission using address data (data storing the address of a transmission destination to which the client intends to perform transmission) acquired from a server (see e.g. Japanese Patent Laid-Open Publication No. 2005-94676).
On the other hand, there has been disclosed a technique related to name resolution (method of looking up the IP address of a host based on the associated host name). A description will be given of a system for performing name resolution, by taking a DNS (Domain Name System) as an example. The DNS is a system which associates host names with IP addresses on the Internet. In the DNS, it is possible to look up a host name based on an associated IP address, and vice versa.
For example, a name resolution unit (e.g. a DNS server) is set in each of a server MFP and a client MFP, and the name resolution is performed using the set name resolution units. In this method, when a domain name is not described in address data designating a transmission destination, the name resolution is generally performed after the address data is automatically complemented with a domain name by one of the name resolution units. Further, a method is also proposed in which the address data is configured to store not only a destination address, but also a user account and a password, and authentication is performed based on the user account and the password at a transmission destination (receiving end).
FIG. 18 shows parts of a system which uses "reverse DNS" to obtain a host name based on an IP address. The system 100 comprises an MFP 101, a DNS server 102 and first and second file servers 103 and 104. The MFP 101, DNS server 102 and the file servers 103 and 104 are interconnected via a network 105 such as a Local Area Network (LAN).
The MFP 101 stores an address book having a plurality of entries corresponding to different respective users of the system. Each entry has a host name, user name and password. For example, the first entry in the address book, "address data 1", has "fileserver1" as the host name, "tanaka" as the user name and "1234" as the password.
The host name identifies the name of a host assigned to the first file server 103. The full host name for the first file server 103 is "fileserver1.aaa.bbb.co.jp" but, as shown in FIG. 18, the address data 1 only specifies "fileserver1", i.e. the domain name "aaa.bbb.co.jp" is omitted. Similarly, the full user name for the user "tanaka" is "tanaka.aaa.bbb.co.jp" but the address data 1 only specifies "tanaka". It is possible to omit the domain name in this case because the MFP 101 and the file servers 103 and 104 belong to the same network, i.e. they share the same domain name.
A user who wishes to transmit image data from the MFP 101 to another user or to himself, selects the relevant address-book entry, for example the address data 1 for the user "tanaka". In this case, the image data should be transmitted to a directory corresponding to "tanaka" of the file server 103 having the address "fileserver1.aaa.bbb.co.jp". To obtain this address the MFP 101 obtains the domain name "aaa.bbb.co.jp" from the DNS server 102 based on the IP address of MFP 101 which is "172.24.10.10" and adds this domain name to "fileserver1" and "tanaka". As a result, the complemented address data "fileserver1.aaa.bbb.co.jp" and "tanaka.aaa.bbb.co.jp" can be used as the destination of the image data.
FIG. 19 shows another system having, in addition to the MFP 101 and DNS server 102 of FIG. 18, a further MFP 201 and a further DNS server 202. The MFP 101 uses the DNS server 102 to obtain a domain name based on an IP address, whereas the further MFP 201 uses the further DNS server 202 to obtain a domain name based on an IP address. The MFP 101 and DNS server 102 are connected to the MFP 201 and DNS server 202 via the Internet. The domain name of the MFP 201 is "ccc.ddd.co.jp", which is different from the domain name "aaa.bbb.co.jp" of the MFP 101.
In the system of FIG. 19, a problem occurs when the address book of the MFP 101 is exported to the MFP 201 which uses the DNS server 202 different from the DNS server 102 used by the MFP 101. This problem arises because the address book of the MFP 101 does not include domain names. If a user of MFP 102 selects the exported address data 1, in order to transmit image data from the MFP 102 to the user "tanaka", the domain name "ccc.ddd.co.jp" is added to the host name and the user name for "tanaka". As a result, an incorrect host name "fileserver1.ccc.ddd.co.jp" and an incorrect user name "tanaka.ccc.ddd.co.jp" are used to transmit the image data, and a transmission error (destination unknown) occurs.
Thus, according to the above-described conventional technique, in the system comprised of the server MFP (MFP 101) that makes address data acquirable or stores the same and the client MFP (MFP 201) that performs transmission using the address data, if the server MFP and the client MFP have different name resolution units (e.g. DNS servers 102 and 202) set therefor, the following problems occur: When address data is exchanged in a state where an associated domain name is not described, there is a possibility that authentication or transmission might fail due to complementary addition of a wrong domain name. Further, it is difficult for a user who intends to perform transmission using address data to check whether or not a domain name is described in the address data.

Image processing apparatus, control method, and storage medium that complement a domain to an address data item with no domain name


A high-strength ratchet structure for ratchet wrench is disclosed to include a driving block with two transverse sliding grooves, two pairs of directional block members respectively movably mounted in the sliding grooves of the driving block, two spring members respectively mounted in the sliding grooves and supported between the associating directional block members, a ratchet member coupled to the driving block, and a direction control ring selectively set in a first position where the ratchet member is locked to the driving block, a second position where the ratchet member is prohibited from clockwise rotation relative to the driving block and allowed for counter-clockwise rotation relative to the driving block, or a third position where the ratchet member is prohibited from counter-clockwise rotation relative to the driving block and allowed for clockwise rotation relative to the driving block.

1. Field of the Invention
The present invention relates to ratchet wrench and more specifically, to a high-strength ratchet structure for ratchet wrench.
2. Description of the Related Art
Many reversible ratchet wrenches are commercially available. These reversible ratchet wrenches commonly comprise a wrench body, a ratchet member coupled to the wrench body, a directional block member for engaging the ratchet member to control the direction of rotation of the ratchet member relative to the wrench body, prohibiting the ratchet member from clockwise rotation and allowing the ratchet member for counter-clockwise rotation, or prohibiting the ratchet member from counter-clockwise rotation and allowing the ratchet member for clockwise rotation. This single-sided stop control design is not applicable for high torque application. The ratchet member may slip when encountering a high resistance, resulting in a failure.

High-strength ratchet structure for ratchet wrench


A power converter for converting three phase input power to DC output power and a method of effecting such conversion. The power converter includes: (1) three single phase DC converters, each having outputs, that receive the three phase input power, (2) a DC/DC converter coupled to the outputs of the three single phase DC converters and (3) a converter selection circuit, associated with the three single phase DC converters, that selects a selected subset of the three single phase DC converters as a function of an electrical characteristic of each phase of the three phase input power to conduct a portion of the three phase input power to the DC/DC converter, the converter selection circuit permitting the power converter to operate on the three phase power with less than three DC/DC converters.

Power converters that use pulse-width modulation techniques to convert three-phase AC input power to one or more DC power levels are widely known. These converters typically comprise three individual converter stages that may be connected in either a delta or a wye configuration. In a delta configuration, each converter stage is coupled between two of the three phases, .phi.A, .phi.B and .phi.C. In a wye configuration, each single phase stage is coupled between a single phase and neutral. In each stage, a switch is closed to generate an increasing current in an inductor that is coupled to one of the phase inputs. When the switch is opened, the current in the inductor is diverted to a large storage capacitor. The current that is pumped onto the storage capacitor when the switch is open creates a DC voltage on the capacitor.
Since the voltage on the storage capacitor in each single phase stage is not at the same level as the voltages on the storage capacitors in the other stages, the stage outputs cannot be coupled in parallel. Therefore, each large storage capacitor is coupled to a separate DC/DC converter. The outputs of the three isolated DC/DC converters may then be coupled together to form a single DC supply, where each stage provides one third of the total output power.
The above-described power device thus converts a three-phase AC input to a DC level using three single-phase boosts and three DC/DC converters. This architecture contains a considerable number of redundant components. This adds to the cost of the power device, increases the amount of circuit board area required by the power device, and adds additional weight to any system in which the power device is installed.
Accordingly, what is needed in the art is an improved power supply converter that minimizes the number of components needed to convert three phase power to a DC level. In particular, there is a need in the art for an improved power supply converter that utilizes only a single DC/DC converter to convert DC outputs received from three separate converter stages.

Three phase rectifier using three single phase converters and a single DC/DC converter


A first processor may receive a first request, from a first user, to initiate a first application. The first processor may initiate a first recording device. Initiating the first recording may include executing firmware embedded in the first recording device. The first processor may validate the identity of the first user using the first recording device. The first processor may initiate the first application. Initiating the first application may include loading and executing a first operating system associated with the first application.

The present disclosure relates generally to the field of digital security, and more specifically to identity authentication during two-way communication.
Built into many tablets, cellphones, and computer systems are webcams. Webcams provide the ability for a user to perform many functions, such as, web conferencing or video messaging. There are many warnings about turning off webcams unless needed at a specific time or for a specific use.

This patent is subject to a terminal disclaimer.

Enabling/disabling applications using face authentication

International Business Machines Corporation


An apparatus, method, and computer program product are described that can detect the presence of a tangible object without using computer vision. The apparatus receives a signal from a device proximate the apparatus, where the signal includes at least one of a proximity component and an orientation component, and also receives a touch input from the associated display. The apparatus then determines whether there is an association between the signal and the touch input based on the proximity component and/or the orientation component. If the signal and the touch input are associated, it is an indication that the device is disposed on the display, operations may be executed, such as to facilitate interaction between the apparatus and the device. As a result, any object capable of providing a signal having a proximity component or an orientation component can be detected (e.g., without the use of cameras or fiducial markers).

As digital information becomes more prevalent in society, the need to access and share such information is constantly growing. Devices for capturing, creating, manipulating, and/or storing such information abound, from digital cameras to cellular phones to laptop computers and other personal mobile devices.
In addition to being able to access information from such devices, users also desire to share information between devices. For example, a user may want to display pictures taken using a digital camera on a portable device with a larger display to make the images easier to see and manipulate. Similarly, a user may wish to view a movie downloaded on the user's cellular phone on a mobile device with a larger display.
Accordingly, it may be desirable to provide an improved mechanism for detecting and establishing a connection with a device for the purpose of receiving and interacting with data from the device.

Method and apparatus for determining the presence of a device for executing operations


Some demonstrative embodiments include devices, systems and methods of multi-channel processing. For example, a multi-channel data processor may process data of a plurality of channels, the multi-channel data processor is to switch from processing a first channel to processing a second channel of the plurality of channels by performing a context switch during a single clock cycle, the context switch including storing first state context corresponding to a processing state of the first channel and loading previously stored second state context corresponding to a processing state of the second channel.

Some communication networks, may communicate data over a plurality of communication channels.
For example, a cable network may include a cable modulator-demodulator (modem) capable of transferring downstream data, which is modulated over a plurality of downstream channels, from a Cable-Modem-Termination-System (CMTS) to one or more devices (subscriber devices), and transferring upstream data, which is modulated over a plurality of upstream channels, from the devices to the CMTS.

Device, system and method of multi-channel processing


Methods, software and systems of dynamically controlling push cache operations are presented. One method, which may also be implemented in software and/or hardware, monitors performance parameters and enables or disables push cache operations depending on whether the performance parameters are within a predetermined range. Another method, which may also be implemented in software and/or hardware, monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.

A computer system typically includes one or more central processor units (CPUs), also referred to simply as processors. Processors are well known to those of ordinary skill in the art. One known technique used to improve CPU performance involves the use of caches. Two types of caches are typically used. The first type of cache is known as an L1 (Level-1) cache which typically resides in the processor core and improves performance by providing speedy access to data and instructions resident in the L1 cache(s). This saves the processor core from having to access main memory to obtain the desired data. L1 caches are typically small in order to achieve the desired speed. The second type of cache is known as an L2 (Level-2) cache. The L2 cache is larger, slower and requires larger access time than L1 cache, while still being smaller, faster and requiring less access time than main memory. Since the L2 cache is faster than memory, the L2 cache saves the processor from having to access main memory if the desired data is not in the L1 cache but is resident in the L2 cache. It is clear that such cache hierarchies are not limited to two levels but can be extended with larger and slower Level 3 caches, Level 4 caches and so on.
Another known technique for improving CPU performance involves a mechanism referred to as a push cache. Push cache is an architectural feature that allows devices or other processors to utilize cache push operations to push or write data directly into one or more of the CPU's caches while maintaining coherency with the main memory. The processor utilizes the cache data and avoids costly memory accesses thereby increasing the overall performance of the system. Devices designed to push selected data into a processor's cache(s) perform the push operation irrespective of the effect of the operation on the overall performance of the system. Thus, in certain scenarios, use of the cache push mechanism may significantly degrade system performance, for example by displacing from the cache previously pushed data that a program running on the CPU has not yet consumed; if for example the data is stored in a data structure that is accessed in First In/First Out (FIFO) order then the displaced data will again be moved back into the cache and accessed before the most recently pushed data is accessed, thus causing extra unnecessary delays and memory traffic.
Referring now to FIG. 1, a prior art system 10 supporting cache push operations is shown. A device 60 issues a write to memory 40 with control bits set to indicate that it is a cache push write operation. The bridge 50 updates the L2 cache 30. The L2 cache 30 updates the memory 40 later in order to maintain coherency between the memory and the L2 cache. Any data displaced or victimized from the L2 cache 30 as a result of the push operation is discarded or written by the L2 cache 30 to memory 40 as necessary in order to maintain coherency in the memory image. Any processor 20 accesses to the updated data would find the data available in the L2 cache 30, thereby avoiding a cache miss by the processor core in L2 cache 30. Alternately, the push operation updates both the L2 cache and main memory together. As should be clear to one skilled in the art the memory 40 might be a next-level cache accessed in common between the CPU and the device.
While the cache push mechanism offers significant performance gains, the efficiency of the cache push mechanism is dependent on two factors. A first factor is the timeliness of the data pushed. A second factor is the cost of victimizing other L2 cache entries as a result of a cache push operation.
The timeliness of the data pushed comes into effect in certain scenarios. In a cache push mechanism system, cache misses are reduced by proactively placing data into the L2 cache 30 thereby avoiding main memory accesses. However, if pushed cache data does not get accessed soon enough, the pushed cache data could end up being a victim of cache replacement, thereby nullifying any gain achieved by the cache push operation and instead incurring additional bus traffic due to the displacement of the pushed cache data and potentially also due to an update to memory with the cache data that was initially displaced by the push operation. Such cache replacement may occur due to processor demand wherein the CPU requests data which is not currently in the cache and the line containing the pushed cache data is displaced by it, or can also occur when another cache push operation occurs and previously pushed cache data is displaced by that act.
In prior art system 10 the peripheral device 60 might be configured to deliver received network packets into buffers in memory 40 along with packet metadata into descriptors also in memory 40, with both the packet data and the associated descriptors to be accessed by a network device driver running on the processor 20. A typical communications mechanism between a network interface such as gigabit Ethernet engine 60 and a processor 20 is one or more FIFOs implemented as data structures in memory 40, where the network interface writes to the tail of the FIFO and the processor 20 reads from the head of the FIFO. In a system implementing cache push capability the network interface might further be configured to push packet descriptors and some or all of the contents of the packet buffer to the cache(s) on one or more CPUs.
The peripheral device 60 may be provided as a gigabit Ethernet engine and the processor 20 may be a network processor. A gigabit Ethernet engine used with a network processor 20 typically implements an interrupt moderation scheme to ensure efficient packet processing at high packet rates. The interrupt moderation scheme ensures that the inter-interrupt interval increases as the packet rate increases. These schemes, while reducing the interrupt rate, also increases the number of packets and descriptors accumulated per interrupt. In turn, the potential of a pushed descriptor being victimized increases as the number of descriptors pushed between interrupts is concomitantly higher.
In normal operation of such a network interface and related device driver, the queue in memory provides for elasticity, or "smoothing" of the arrival rate of packets; the device driver does not have to keep up with the arrival of packets on a packet-by-packet basis but rather only needs to budget such that the processing time on average does not exceed the inter-arrival time on average of packets. Victimization of pushed but unaccessed packets and descriptors from the head of a queue due to subsequent cache push operations to the tail of that queue occurs when the cache is not dynamically able to contain the required depth of elasticity at a particular point in a bursty arrival of packets.
The cost of cache victimization due to cache push operations also comes into effect in certain scenarios. The cache unit treats a cache push operation similar to a cache line replacement operation from the processor core. A cache push operation could result in a cache line being victimized, the cache victim selected by the cache's particular replacement algorithm. If the location represented by the victimized cache line is of current or future interest to the code running on the processor 20, then the victimized cache line would subsequently be brought back into the cache as a result of an access by the processor 20 from memory 40. Thus, in this scenario, the push operation could result in a net increase rather than decrease in cache misses, thereby negatively impacting the overall system performance.
Thus, in systems that implement cache push operations, the use of cache push operations could be counterproductive, especially under high packet rate and high core processor load conditions. Using cache push operations under both these conditions could result in additional cache misses and associated main memory accesses. As the processor continues to receive data on its I/O interfaces, more data gets pushed, with the push operation increasingly victimizing the current working set resulting in more cache misses and more memory accesses. This cycle could continue eventually bringing the system to a halt under heavy load and I/O or causing packet loss due to increased processor stalls.


A ceramic electronic device includes a multilayer chip in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to a first end face and a second end face of the multilayer structure. A bent portion, in which the plurality of dielectric layers in a substantially same position along a stacking direction project along the stacking direction, is formed in the multilayer chip. In the bent portion, a through-hole is formed in two or more of the plurality of internal electrode layers. The through-hole is a defect portion in a first direction in which the first end face faces with the second end face and in a second direction that is vertical to the first direction in a plane of the plurality of internal electrode layers.

Ceramic electronic devices such as multilayer ceramic capacitors are being used, in order to downsize electronic devices such as smart phones. Downsizing of the electronic devices is requested. Therefore, downsizing and capacity enlargement of the ceramic electronic devices are requested. In order to downsize the ceramic electronic devices and enlarge capacity of the ceramic electronic devices, it is thought that the thickness of dielectric layers and the thickness of interna electrode layers are reduced. However, the thicknesses are reduced, delamination may occur. And so, there is disclosed technology in which an opening is formed in the internal electrode layers (for example, see Japanese Patent Application Publication No. 2018-121025, Japanese Patent Application Publication No. 2005-85823, and Japanese Patent Application Publication No. 2001-217137).

Ceramic electronic device and manufacturing method of the same


A novel system by which the utilization of a central processing unit (CPU) in performing filtering operations can be reduced by shortening the filter's length thus degrading the performance of the system down to a predetermined level or threshold. The present invention is applicable to such systems that incorporate filters whereby shortening their length decreases the performance of the system and to such systems where a reliable quality criteria exists that can be measured during run time. A method iteratively minimizes the filter's length so that the quality criteria does not fall below a predetemined threshold level. In addition, a signal to noise ratio (SN) criteria is suggested for estimating the quality of the reception of communication signals. An implementation is suggested for the method in the particular case of an echo cancellation adaptive filter. In addition, a method for determining an immediate approximation of the echo canceler filter's length as opposed to finding it iteratively.

Traditional fall duplex communications systems are typically implemented using dedicated DSP-based hardware. Such modem implementation schemes are usually quite expensive due to the dedicated DSP hardware utilized. Therefore, the recent trend in the personal computer (PC) industry is to implement modems by exploiting the general purpose CPU built into each PC without the need for additional processing hardware. Such implementation schemes are termed Native Signal Processing (NSP).
Implicit in any NSP based modem design is the requirement that the modem share CPU time with other tasks executed in the PC system on the same processing unit. Hence, the great importance in minimizing CPU utilization of the NSP software functions using both novel DSP algorithms and hand coded assembly language optimizations.
Most modem implementations, whether NSP or DSP based, utilize one or more finite impulse response (FIR) adaptive filters to perform various filtering functions. Examples of applications of FIR adaptive filters include the far-end (FE) echo canceler FIR filter, the near-end echo (NE) echo canceler FIR filter and the equalizer (EQU) FIR filter. Each filter is constructed to have a particular number of taps or delay units. Generally, the larger the number of taps the better the filter performs its filtering function. However, the price is increased processing time.
In addition, the communication systems the modems are employed in are usually required to cope with a vast number of diverse channel and echo impairments. The length of a communications filter needed to retain a given performance curve depends on the amount of signal distortion introduced by the channel and the echo impairments. Usually, the greater the distortion that is present in the channel, the longer the filter that is needed to cancel it. Since the communication system must be able to cope with the worst case impairment conditions, and since the distortion characteristics are not known a priori, prior art modems which use fixed length filters must employ a long filter length to meet the worst case requirements regardless of the actual signal distortion. However, since worst case distortion conditions are quite rare, a fixed length filter implementation usually results in wasted consumption of CPU resources.
Modifying the length of a digital filter for producing optimal acoustic echo cancellation is known in the art. U.S. Pat. No. 5,473,686 issued to Virdee teaches modifying the number of taps of an adaptive finite impulse response (AFIR) to achieve optimal echo cancellation. The taps at the end of the filter are examined as to whether they contribute a first threshold amount to the echo estimate. If not, the number of samples is reduced and the taps at the end of the filter are checked again. If the taps at the end of the filter contribute more than a second threshold amount, the number of samples is increased and the process is repeated.

System for dynamically adapting the length of a filter


A vehicle steering system is configured to avoid contact between wheels and wheel housings when the wheels are steered and to enlarge the maximum steering angle. The vehicle steering system has a steering knuckle that supports a wheel for rotation about a wheel axis and a pivotal movement about a steering axis. The steering knuckle is coupled to a first end part of an extension link. A second end part of the extension link is connected to an arm through a control rod. The extension link is pivotally sustained around a steering axis. The arm is connected to a front end of a knuckle arm through a tie rod. When the arm turns, the second end part of the extension link is pulled inside through the control rod, and the steering knuckle situated on rear end of the control rod is pushed outwardly. At the same time, the arm steers the steering knuckle through the tie rod.

1. Field of the Invention
The present invention generally relates to a vehicle steering system for steering wheels of a vehicle. More specifically, the present invention relates to a steering system that provides for widening the maximum steering angle without enlarging the wheel housings of the vehicle.
2. Background Information
Generally, there are two basic types of steering systems used on passenger cars: manual and power. In a manual steering system, the driver's effort to turn the steering wheel is the primary force that causes the front steerable wheels to turn to the left or right on steering knuckles. With power steering, the driver's turning efforts are multiplied by a hydraulic or in electro hydraulic assist. Whether the steering system is a manual steering system or a power steering system, one of the most common types of steering system is a rack-and-pinion type steering system. A typical rack-and-pinion steering system basically includes a pinion shaft, a rack gear, a gear housing, two tie rod assemblies and two steering knuckles.
When a wheel turns around a kingpin or steering axis, generally one part of the wheel shifts its position inward in the widthwise direction of a vehicle. In the meantime, the other part of the wheel shifts outward of the vehicle. Therefore, if the steering angle becomes larger, the wheel contacts the wheel housing.
The wheel housing can be widened in the widthwise direction in order to avoid the contact and therefore the maximum steering angle can be larger. However, it will be impossible to mount a large engine or a large transmission by sacrificing the space for the wheel housing. On example of a vehicle steering system that attempts to widen the maximum angle of the steerable wheels without enlarging wheel housings is disclosed in Japanese Laid-Open Publication No. 6-219314. The vehicle steering system disclosed in this Japanese publication is designed to widen the maximum steering angle of the steerable wheel disposed on the outside of the vehicle's turn radius, even when the steerable wheel disposed on the inside of the vehicle's turn radius reaches its maximum angle, by installing an expansion and contraction mechanism in each of the links that are attached to the knuckle arms.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved vehicle steering system. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.


A prosthesis for large blood vessels includes a main conduit. At least one tract of the main conduit is subdivided into a plurality of smaller conduits located parallel to one another.

The thoracic-abdominal aneurysm is largely a progressive yielding, fatal upon breaking, of the walls of the thoracic and abdominal aorta. As there is no possible medical therapy available, the pathology can only be treated by surgical intervention, which involves a large-scale thoracic laparotomy and substitution of the dilated tract with a straight tubular prosthesis. The visceral blood vessels and sometimes the intercostal arteries are connected to the prosthesis.
The surgical operation is carried out usually according to two main techniques, often used in combination.
The first of these techniques, also known as the De Bakey method, involves clamping (hemostasis) of the tract of aorta downstream of the aneurysm, a first sectioning of the aorta itself and the suturing of the prosthesis to the first section, and the clamping of the tract of aorta upstream of the aneurysm, a second sectioning of the aorta and the suturing (anastomosis) of the prosthesis to the second section. Then the visceral branches are sutured to the prosthesis with or without interpositioning of prosthetic segments. This technique exposes the patient to quite long operations with relevant haemorrhaging, but guarantees good blood circulation downstream of the aneurysm.
The second technique, also known as the Crawford method, is based on the speed of performance of the operation. The aorta is clamped upstream and downstream of the aneurysm. The aorta is sectioned upstream and downstream of the aneurysm, hemostasis is performed on any arteries connected to the sectioned tract of aorta, and the prosthesis is applied with rapid suturing to the two sections.
The visceral and intercostal arteries from the sectioned tract of aorta are then sutured to the prosthesis, preferably without interpositioning of prosthetic segments in order not excessively to extend operation time. The technique implies that during the operation the circulation downstream of the thorax is practically stopped. If possible, in anastomosis of the visceral and intercostal arteries, patches of aortic sections surrounding the original connection points of the arteries are re-used.
Although the results obtained using the techniques are satisfactory in a majority of the cases, with the patients' progressing to full recovery, there are however not inconsiderable risks connected to the importance of the surgical operation itself. The rate of mortality during or immediately following surgery, together with post-operational respiratory difficulties and kidney failure, can reach up to 20%. There is also a risk of about 20% of paraplegia, leading many patients to refuse to undertake the operation.
Paraplegia, as well as the other complications, is essentially due to a blockage in arterial circulation to the lower parts of the body. This blockage, which is of a length correlated to the difficulty of performance of the operation, can obviously lead to medullar ischemia and therefore to paralysis of the lower limbs.
To limit the risk of paraplegia temporary aortic by-passes are used, with extracorporeal circulation tubing taking blood from upstream of the aneurysm and sending it to the lumbar and hypogastric arteries. The inflow of blood to these arteries guarantees a sufficient vascularization of the medulla and the abdominal organs, very considerably reducing risks of ischemia. The use of extracorporeal circulation, however, involves considerable use of anticoagulants, especially if a pump is used, as is sometimes the case; in all cases, however, long operation times are needed.


An electroluminescent (EL) device having an LED formed on a substrate with at least two electrodes formed over the substrate, and an EL unit formed between the electrodes. At least one of the electrodes is transparent. At least one of the electrodes is patterned to define independently controllable light-emitting areas. A cover is formed over the LED. The cover or substrate is transparent. A light-scattering layer is formed between the cover and substrate for scattering light. A low-index element, having an optical index lower than other optical indices, is formed between the scattering layer and the transparent cover or substrate. Additionally, a contrast-enhancement layer includes alternating light-absorbing portions and light-transmissive portions formed in the layer located between the light-scattering layer and the transparent substrate or cover through which light is emitted, wherein the light-absorbing portions and light-transmissive portions are located in each light-emitting area.

Electroluminescent devices are a promising technology for flat-panel displays and area illumination lamps. These devices rely upon thin-film layers of materials coated upon a substrate, and include organic, inorganic and hybrid inorganic-organic light-emitting diodes. The thin-film layers of materials can include, for example, organic materials, quantum dots, fused inorganic nano-particles, electrodes, conductors, and silicon electronic components as are known and taught in the LED art.
Irrespective of the particular electroluminescent device configuration tailored to these broad fields of applications, all electroluminescent devices function on the same general principles. An electroluminescent (EL) unit is sandwiched between two electrodes. At least one of the electrodes is at least partially light transmissive. These electrodes are commonly referred to as an anode and a cathode in analogy to the terminals of a conventional diode. When an electrical potential is applied between the electrodes so that the anode is connected to the positive terminal of a voltage source and the cathode is connected to the negative terminal, the LED is said to be forward-biased. Positive charge carriers (holes) are injected from the anode into the EL unit, and negative charge carriers (electrons) are injected from the cathode. Such charge carrier injection causes current flow from the electrodes through the EL unit. Recombination of holes and electrons occurs within the light emitting layer and results in emission of light. For example, electroluminescent devices containing quantum dot light-emitting diode (LED) structures can be either inorganic or hybrid inorganic-organic, and the recombination of the holes and electrons occurs within the core of a quantum dot in the light-emitting layer. A hybrid inorganic-organic EL unit can be formed of a stack of sublayers that can include small-molecule layers or polymer layers.
In the late 1990's LED devices containing mixed emitters of organics and quantum dots were introduced (Mattoussi et al., Journal of Applied Physics 83, 7965 (1998)). Quantum dots are light-emitting, nano-sized semiconductor crystals. Adding quantum dots to the emitter layers could enhance the color gamut of the device; red, green, and blue emission could be obtained by simply varying the quantum-dot particle size; and the manufacturing cost could be reduced. Because of problems such as aggregation of the quantum dots in the emitter layer, the efficiency of these devices was rather low in comparison with typical OLED devices. The efficiency was even poorer when a neat film of quantum dots was used as the emitter layer (Hikmet et al., Journal of Applied Physics 93, 3509 (2003)). The poor efficiency was attributed to the insulating nature of the quantum-dot layer. Later the efficiency was boosted (to ˜1.5 cd/A) upon depositing a mono-layer film of quantum dots between organic hole and electron transport layers (Coe et al., Nature 420, 800 (2002)). It was stated that luminescence from the quantum dots occurred mainly as a result of Forster energy transfer from excitons on the organic molecules (electron-hole recombination occurs on the organic molecules). Regardless of improvements in efficiency, these hybrid devices still suffer from all of the drawbacks associated with pure OLED devices.
Recently, a mainly all-inorganic LED was constructed (Mueller et al., Nano Letters 5, 1039 (2005)) by sandwiching a monolayer thick core/shell CdSe/ZnS quantum-dot layer between vacuum deposited inorganic n- and p-GaN layers. The resulting device had a poor external quantum efficiency of 0.001 to 0.01%. Part of that problem could be associated with the organic ligands of trioctylphosphine oxide (TOPO) and trioctylphosphine (TOP) that were reported to be present post growth. These organic ligands are insulators and would result in poor electron and hole injection into the quantum dots. In addition, the remainder of the structure is costly to manufacture, due to the usage of electron and hole semiconducting layers grown by high-vacuum techniques, and the usage of sapphire substrates.
As described in co-pending, commonly assigned U.S. Ser. No. 11/226,622 by Kahen, which is hereby incorporated by reference in its entirety, additional semiconductor nanoparticles may be provided with the quantum dots in a layer to enhance the conductivity of the light-emitting layer.
OLED devices generally can have two formats known as small molecule devices such as disclosed in U.S. Pat. No. 4,476,292 and polymer OLED devices such as disclosed in U.S. Pat. No. 5,247,190. Either type of OLED device may include, in sequence, an anode, an organic EL element, and a cathode. In most designs, one of the electrodes is reflective and the other transparent. The organic EL element disposed between the anode and the cathode commonly includes an organic hole-transporting layer (HTL), a light-emissive layer (LEL), and an organic electron-transporting layer (ETL). Holes and electrons recombine and emit light in the LEL layer. Tang et al. (Applied Physics Letters, 51, 913 (1987), Journal of Applied Physics, 65, 3610 (1989), and U.S. Pat. No. 4,769,292) demonstrated highly efficient OLEDs using such a layer structure. Since then, numerous OLEDs with alternative layer structures, including polymeric materials, have been disclosed and device performance has been improved.
Light is generated in an LED device when electrons and holes that are injected from the cathode and anode, respectively, flow through the respective charge-transport layers and recombine in the emissive layer. Many factors determine the efficiency of this light generating process. For example, the selection of anode and cathode materials can determine how efficiently the electrons and holes are injected into the device; the selection of ETL and HTL can determine how efficiently the electrons and holes are transported in the device, and the selection of LEL can determine how efficiently the electrons and holes be recombined and result in the emission of light, etc.
However, electroluminescent devices generally suffer from poor ambient contrast because of the reflectivity of the reflective electrode. Such a reflector tends to reflect ambient light thus reducing the contrast between the emitted light and the ambient light and decreasing the image quality of the LED device. One approach to addressing this problem is to use circular polarizers. For example, the Eastman Kodak LS633 digital camera employed such means to improve ambient contrast in an active-matrix OLED display. However, such polarizers are expensive and also absorb as much as 40% of the emitted light.
The use of louver films comprising alternating light-transmissive and light-absorbing portions as privacy securing and contrast improving films for display devices has been suggested, e.g., as described in US Patent 2004/0191548 and in WO 2005/092544 A1. Such louver films are typically employed on the top surface of a display device, and while effective at reducing viewing angles, typically have not been suggested for use in displays with improved light output and sharpness of display images.
It has also been found, that one of the key factors that limits the efficiency of LED devices is the inefficiency in extracting the photons generated by the electron-hole recombination out of the LED devices. Due to the high optical indices of the materials used, most of the photons generated by the recombination process are actually trapped in the devices due to total internal reflection. These trapped photons never leave the LED devices and make no contribution to the light output from these devices. Because light is emitted in all directions from the internal layers of the LED, some of the light is emitted directly from the device, and some is emitted into the device and is either reflected back out or is absorbed, and some of the light is emitted laterally and trapped and absorbed by the various layers comprising the device. In general, up to 80% of the light may be lost in this manner.
A typical OLED device uses a glass substrate, a transparent conducting anode such as indium-tin-oxide (ITO), a stack of organic layers, and a reflective cathode layer. Light generated from the device is emitted through the glass substrate. This is commonly referred to as a bottom-emitting device. Alternatively, a device can include a substrate, a reflective anode, a stack of organic layers, and a top transparent cathode layer and transparent cover. Light generated from the device is emitted through the top transparent electrode and transparent cover. This is commonly referred to as a top-emitting device. In these typical devices, the index of the ITO layer, the organic layers, and the glass is about 2.0, 1.7, and 1.5 respectively. It has been estimated that nearly 60% of the generated light is trapped by internal reflection in the ITO/organic EL element, 20% is trapped in the glass substrate, and only about 20% of the generated light is actually emitted from the device and performs useful functions.
In any of these LED structures, the problem of trapped emitted light and reflected ambient light remains. Referring to FIG. 9, a bottom-emitting LED device as known in the prior art is illustrated having a transparent substrate 10, a transparent first electrode 12, an EL unit 14 which contains a light-emitting layer, a reflective second electrode 16, a gap 19 and a cover 20. The gap 19 is typically filled with desiccating material. Light emitted from one of the EL unit 14 can be emitted directly out of the device, through the transparent substrate 10, as illustrated with light ray 1. Light may also be emitted and internally guided in the transparent substrate 10 and EL unit 14, as illustrated with light ray 2. Additionally, light may be emitted and internally guided in the EL unit 14, as illustrated with light ray 3. Light rays 4 emitted toward the reflective electrode 16 are reflected back toward the substrate 10 and follow one of the light ray paths 1, 2, or 3. Ambient light 6 incident on the LED may be reflected from the reflective electrode 16, thereby reducing the ambient contrast of the LED device. In some prior-art embodiments, the electrode 16 may be opaque and/or light absorbing. Such an arrangement will increase the contrast by absorbing ambient light, but also absorbs the light 4 emitted toward the electrode 16. The bottom-emitter embodiment shown may also be implemented in a top-emitter configuration with a transparent cover and top electrode 16.
Scattering techniques are known to assist in extracting light from LED devices. Chou (International Publication Number WO 02/37580 A1) and Liu et al. (U.S. Patent Application Publication No. 2001/0026124 A1) taught the use of a volume or surface scattering layer to improve light extraction. The scattering layer is applied next to the organic layers or on the outside surface of the glass substrate and has optical index that matches these layers. Light emitted from the OLED device at higher than critical angle that would have otherwise been trapped can penetrate into the scattering layer and be scattered out of the device. The efficiency of the OLED device is thereby improved, but still has deficiencies as explained below. Moreover, the contrast of the device is not improved under diffuse illumination.
U.S. Pat. No. 6,787,796 entitled "Organic electroluminescent display device and method of manufacturing the same" by Do et al issued 20040907 describes an organic electroluminescent (EL) display device and a method of manufacturing the same. The organic EL device includes a substrate layer, a first electrode layer formed on the substrate layer, an organic layer formed on the first electrode layer, and a second electrode layer formed on the organic layer, wherein a light-loss preventing layer having different refractive index areas is formed between layers of the organic EL device having a large difference in refractive index among the respective layers. U.S. Patent Application Publication No. 2004/0217702 entitled "Light extracting designs for organic light emitting diodes" by Garner et al., similarly discloses use of microstructures to provide internal refractive index variations or internal or surface physical variations that function to perturb the propagation of internal waveguide modes within an OLED. When employed in a top-emitter embodiment, the use of an index-matched polymer adjacent the cover is disclosed.
Light-scattering layers used externally to an OLED device are described in U.S. Patent Application Publication No. 2005/0018431 entitled "Organic electroluminescent devices having improved light extraction" by Shiang and U.S. Pat. No. 5,955,837 entitled "System with an active layer of a medium having light-scattering properties for flat-panel display devices" by Horikx, et al. These disclosures describe and define properties of scattering layers located on a substrate in detail. Likewise, U.S. Pat. No. 6,777,871 entitled "Organic ElectroLuminescent Devices with Enhanced Light Extraction" by Duggal et al., describes the use of an output coupler comprising a composite layer having specific refractive indices and scattering properties. While useful for extracting light, this approach will only extract light that propagates in the substrate (illustrated with light ray 2) and will not extract light that propagates through the organic layers and electrodes (illustrated with light ray 3).
In any case, scattering techniques, by themselves, cause light to pass through the light-absorbing material layers multiple times where they are absorbed and converted to heat. Moreover, trapped light may propagate a considerable distance horizontally through the cover, substrate, or organic layers before being scattered out of the device, thereby reducing the sharpness of the device in pixellated applications such as displays. For example, as illustrated in FIG. 10, a prior-art pixellated bottom-emitting LED device may include a plurality of independently controlled sub-pixels 50, 52, 54, 56, and 58 and a scattering layer 22 located between the transparent first electrode 12 and the substrate 10. A light ray 5 emitted from the light-emitting layer may be scattered multiple times by scattering layer 22, while traveling through the substrate 10, EL unit(s) 14, and transparent first electrode 12 before it is emitted from the device. When the light ray 5 is finally emitted from the device, the light ray 5 has traveled a considerable distance through the various device layers from the original sub-pixel 50 location where it originated to a remote sub-pixel 58 where it is emitted, thus reducing sharpness. Most of the lateral travel occurs in the substrate 10, because that is by far the thickest layer in the package. Also, the amount of light emitted is reduced due to absorption of light in the various layers.
U.S. Patent Application Publication No. 2004/0061136 entitled, "Organic light emitting device having enhanced light extraction efficiency" by Tyan et al., describes an enhanced light-extraction OLED device that includes a light-scattering layer. In certain embodiments, a low-index isolation layer (having an optical index substantially lower than that of the organic electroluminescent element) is employed adjacent to a reflective layer in combination with the light-scattering layer to prevent low-angle light from striking the reflective layer, and thereby minimize absorption losses due to multiple reflections from the reflective layer. The particular arrangements, however, may still result in reduced sharpness of the device and does not improve contrast.
Co-pending, commonly assigned U.S. Ser. No. 11/065,082, filed Feb. 24, 2005, describes the use of a transparent low-index layer having a refractive index lower than the refractive index of the cover or substrate through which light is emitted and lower than the organic layers to enhance the sharpness of a LED device having a scattering element. US 20050194896 describes a nano-structure layer for extracting radiated light from a light-emitting device together with a gap having a refractive index lower than an average refractive index of the emissive layer and nano-structure layer. Such disclosed designs, however, do not improve the contrast of the device.
It is known to improve the contrast of a LED device by employing, for example, black-matrix materials between the light-emitting areas or by using color filters. While such methods are useful, the presence of a reflective electrode still decreases the ambient contrast significantly. As noted above, circular polarizers may be employed, but applicants have determined that light-extraction techniques such as scattering layers tend to be incompatible with such polarizers.
There is a need therefore for an improved light-emitting diode device structure that avoids the problems noted above and improves the efficiency and sharpness of the device.

LED device having improved output and contrast


A self-contained training device for simulated personnel entry, exit and rescue in confined space scenarios. The device features an enclosed tank mounted on a truck trailer. The tank has at least one top portal and at least one side portal for entry and exit. An enclosed pipe is situated within the tank and has separate points of entry and exit. The top of the tank features a walkway and handrail.

1. Field of the Invention
The present invention is directed to a self-contained, mobile, confined or enclosed space training device to train for personnel entry, exit and rescue procedures. In particular, the present invention relates to a self-contained vehicle mounted device for training personnel who work with, in, and around confined or enclosed space work areas.
2. Prior Art
Certain work places are defined by the U.S. Department of Labor Occupational Safety and Health Administration ("OSHA") as "confined spaces" because their configurations hinder the activities of personnel who must enter, work in, and exit them. For instance, the U.S. Department of Labor has set forth the following:                . . . employees who work in process vessels generally must squeeze in and out through narrow openings and perform their tasks while cramped or contorted. OSHA uses the term "confined space" to describe such spaces. In addition, there are many instances where employees who work in confined spaces face increased risk of exposure to serious hazards. In some cases, confinement itself poses entrapment hazards. In other cases, confined space work keeps employees closer to hazards, such as asphyxiating atmospheres or the moving parts of machinery. OSHA uses the term "permit-required confined space" (permit space) to describe those spaces that both meet the definition of "confined space" and pose health or safety hazards. The following questions link to resources that provide safety and health information relevant to confined spaces in the workplace. (www.osha.gov/SLTC/confinedspaces)
There are various hazards that may be encountered when entering, exiting and working in confined space work places.
Confined spaces are categorized as those with open tops having a depth that will restrict natural movement of air, and enclosed spaces with very limited openings for entry. Those with limited access pose additional problems. Even when the containers or tanks are opened, gases which are heavier than air, such as carbon dioxide or propane, may lie in a tank for hours or days after the containers have been opened.
Entry into confined or enclosed spaces by personnel may be done for various reasons. These include inspection, repair, maintenance such as cleaning or painting, and similar operations. Additionally, unauthorized entry may be involved where various workers and trades are involved.
Finally, emergency rescue may be a reason for entry by personnel into confined or enclosed spaces.
Because of these conditions, the U.S. Department of Labor and other jurisdictions require that any employee required or permitted to enter a permit-required confined space must have successfully completed, as a minimum, certain training. A permit verifies completion of surveillance, testing, space ventilation and entry procedures. For example, 29 CFR Part No. 1910.146 Appendix C provides:                Entry Procedures. The following procedure shall be observed under any of the following conditions: 1.) Testing demonstrates the existence of dangerous or deficient conditions and additional ventilation cannot reduce concentrations to safe levels; 2.) The atmosphere tests as safe but unsafe conditions can reasonably be expected to develop; 3.) It is not feasible to provide for ready exit from spaces equipped with automatic fire suppression systems and it is not practical or safe to deactivate such systems; 4.) An emergency exists and it is not feasible to wait for pre-entry procedures to take effect.        All personnel must be trained. A self contained breathing apparatus shall be worn by any person entering the space. At least one worker shall stand by the outside of the space ready to give assistance in case of emergency. The standby worker shall have a self contained breathing apparatus available for immediate use. There shall be at least one additional worker within sight or call of the standby worker. Continuous powered communications shall be maintained between the worker within the confined space and standby personnel.        If at any time there is any questionable action or non-movement by the worker inside, a verbal check will be made. If there is no response, the worker will be moved immediately. Exception: If the worker is disabled due to falling or impact, he/she shall not be removed from the confined space unless there is immediate danger to his/her life. Local fire department rescue personnel shall be notified immediately. The standby worker may only enter the confined space in case of an emergency (wearing the self contained breathing apparatus) and only after being relieved by another worker. Safety belt or harness with attached lifeline shall be used by all workers entering the space with the free end of the line secured outside the entry opening. The standby worker shall attempt to remove a disabled worker via his lifeline before entering the space.        When practical, these spaces shall be entered through side openings—those within 3½ feet (1.07 m) of the bottom. When entry must be through a top opening, the safety belt shall be of the harness type that suspends a person upright and a hoisting device or similar apparatus shall be available for lifting workers out of the space.        In any situation where their use may endanger the worker, use of a hoisting device or safety belt and attached lifeline may be discontinued.
Entry and exit with hoisting harnesses and breathing equipment requires considerable personnel training.
In addition, 29 CFR Part No. 1910.146(k)(2)(iv) requires personnel to practice making confined space rescues at least once every twelve (12) months.
Where valves, motors and other mechanical devices operate in conjunction with confined space tanks or containers, prescribed lock-out, tag out procedures must be employed. For example, where a motor and valve are involved, the power switch or switches must be turned off at a power panel. Thereafter, a tag is affixed to a lock in order to inform and advise others that a permit, confined space entry is in progress. Additionally, any and all valves will be closed. Each valve will be set to the closed position and a chain and lock secure the valve in that position. A tag will be attached to the valve warning that a confined space entry is in progress.
Of course, it is possible to utilize existing confined space tanks or containers to train personnel in entry, exit and rescue procedures. This will often times require disabling or taking the container tank out of service during these training sessions. Smetanick (U.S. Pat. No. 4,346,905) illustrates an example of a tank trailer to transport fluid products but is otherwise dissimilar.
Accordingly, it would be advantageous to provide a training device for personnel entry, exit and rescue procedures to simulate confined spaces without having to interrupt or interfere with operation of actual tanks or containers.
Additionally, it would be advantageous to provide a training tank device which would provide opportunities for training in multiple procedures and situations that might be encountered in confined space operations.
It would also be advantageous to provide a confined space training device to demonstrate proper entrance, exit and rescue procedures.
It would also be advantageous to provide a self-contained, integrated, mobile confined space training device which could be brought to a work site for periodic training of personnel.

Training tank for personnel entry, exit and rescue


A voltage division circuit for a photomultiplier tube in which an electron multiplication factor of the photomultiplier tube is readily changeable in a wide range with a low power consumption and without degrading a dynode's collection efficiency and an output linearity. The voltage division portion 100 divides a high voltage (-HV) at a fixed voltage division ratio determined by the resistance values of resistors 111 to 116, 121 and 122, and 131 to 134 to thereby generate voltages applied to a focusing electrode 820, dynodes 831, 832 and 836 to 838. Another voltage division portion 300 includes a variable resistor 332 and generates voltages applied to the dynodes 833 to 835 by dividing the high voltage at a variable voltage division ratio upon operating the variable resistor.

1. Field of the Invention
The present invention relates to a voltage division circuit for supplying high voltages to a photomultiplier tube.
2. Description of the Related Art
A photomultiplier tube is a photodetector with a large electron multiplication factor, wherein photoelectrons generated when light is incident on a photocathode are multiplied by multistage dynodes and the resultant electrons are extracted from an anode as a photo detection signal. Due to the large electron multiplication factor, the photomultiplier tubes have been extensively used in various fields such as a light measurement field to measure minute light.
In the light measurement,
(i) a single photomultiplier tube is used to detect whether or not light is received or to detect an amount of light received, and
(ii) a number of photomultipliers are used in conjunction with position CTs (Computer Tomography), gamma cameras, TOFs (Time Of Flight) and the like.
A voltage is applied between the photocathode and the first-stage dynode and also between the succeeding dynodes to activate the photomultiplier tubes. To this effect, a voltage division circuit is employed in which a high voltage applied thereto is subjected to a voltage division to generate voltages to be applied to the photocathode and the respective dynodes.
FIG. 4 is a circuit diagram showing a conventional, very basic voltage division circuit. As shown therein, the voltage division circuit includes a serially-connected resistor array 910 in which a plurality of resistor elements 910.sub.1 through 910.sub.N+2 are connected in series. A high voltage applied between both terminals of the resistor array 910 is divided by the respective resistor values. Divided voltages are applied to the photocathode 991, focusing electrode 992, and dynodes 993.sub.1 through 993.sub.N of the photomultiplier tube 990.
The electron multiplication factor in the photomultiplier tube changes depending on the voltages applied thereto. Further, the electron multiplication factors change for different photomultiplier tubes even if the same voltages were applied between the photocathode and the first-stage dynode and between the succeeding dynodes.
When a single photomultiplier tube is used as described in (i) mentioned above, it is required that the electron multiplication factor be controlled depending on a predicted amount of incident light from the subject to be measured so that the output from the photomultiplier tube may not be saturated. When a number of photomultiplier tubes are used at a time as described in (ii) mentioned above, it is desirable that the electron multiplication factors of all the photomultiplier tubes be approximately equal to one another. Equal electron multiplication factors facilitate configuration of amplifiers to be provided following the photomultiplier tubes in terms of processing photo detection signals output from the photomultiplier tubes.
It has conventionally been proposed to change the level of the high voltage applied to the voltage division circuit or to change the voltage division ratio in the voltage division circuit to change the electron multiplication factor in an individual photomultiplier tube. When changing the electron multiplication factor by such a method, attention should be drawn to the fact that a dynode's collection efficiency, which is a probability in which the photoelectrons emitted from the photocathode enter the first stage dynode, relies upon the voltage applied between the photocathode and the first dynode. FIG. 5 is a graphical representation showing that the dynode's collection efficiency relies upon the voltage applied between the photocathode and the first-stage dynode. As is apparent from FIG. 5, it is required that the voltage applied between the photocathode and the first-stage dynode be maintained at a level higher than a predetermined value in order to maintain the dynode's collection efficiency at a high level.
In view of the foregoing, there have been proposed the following voltage division circuits. One type of the voltage division circuit maintains the voltage applied between the photocathode and the first-stage dynode at a constant level and changes the high voltage applied to the voltage division circuit. Another type of the voltage division circuit changes the voltage division ratio to thus change the electron multiplication factor of the individual photomultiplier tubes.
FIG. 6 shows a conventional voltage division circuit disclosed in Japanese Laid-Open Patent Publication (Kokai) No. HEI-7-142024. The circuit shown therein includes Zener diodes which are used to maintain the voltage applied between the photocathode and the first-stage dynode at constant. In this circuit, a variable resistor 921, Zener diodes 922, 923 and resistor elements 924.sub.1 through 924.sub.N are connected in series. The Zener diodes 922 and 923 maintain the voltages between the photocathode 991 and a focusing electrode 992 and between the focusing electrode 992 and the first-stage dynode 993.sub.1, respectively. As such, the voltage between the photocathode 991 and the first-stage dynode 993.sub.1 is maintained at constant by virtue of the Zener diodes 922 and 923, thereby remaining the dynode's collection efficiency unchanged. To change the electron multiplication factor of the photomultiplier tube, the resistance value of the variable resistor 921 is changed to change the voltage applied between the adjacent two electrodes of the photocathode 991 and the dynodes 993.sub.1 through 993.sub.N.
FIG. 7 shows another conventional voltage division circuit disclosed in Japanese Laid-Open Patent Publication (Kokai) No. HEI-7-142024. This circuit uses a constant voltage source to maintain the voltage between the photocathode and the first-stage dynode at constant. This circuit includes a first serially-connected circuit consisting of a first constant voltage source 931, a second constant voltage source 932, and resistor elements 993.sub.1 through 993.sub.N, and a second serially-connected circuit consisting of resistor elements 934.sub.1 through 934.sub.N, wherein the first and second serially-connected circuits are connected in parallel to each other. The resistor elements 993.sub.1 through 993.sub.N are provided in one-to-one correspondence to the resistor elements 934.sub.1 through 934.sub.N so that the resistor element 993.sub.1 correspond to the resistor element 994.sub.1. Switches 935.sub.1 through 935.sub.N+1 are connected between terminals of the corresponding resistors. A high voltage is applied between the two terminals of the resistor array 993.sub.1 through 993.sub.N.
In the voltage division circuit shown in FIG. 7, the constant voltage sources 931 and 932 maintain the voltages between the photocathode 991 and the focusing electrode 992 and between the focusing electrode 992 and the first-stage dynode 993.sub.1, respectively. That is, the voltage between the photocathode 991 and the first-stage dynode 993.sub.1 is maintained at constant to thereby maintain the dynode's collection efficiency. By individually performing on-off actions of the switches 935.sub.1 through 935.sub.N+1, the electron multiplication factor of the photomultiplier tube 990 is changed.
The conventional voltage division circuits as described above contain the following disadvantages.
In the voltage division circuit disclosed in Japanese Laid-Open Publication No. HEI-7-142024, the Zener diode generates non-negligible noises when the current flowing therein is less than several hundreds microamperes. In order to operate the circuit without introducing unwanted Zener noises, it is required that a current more than several hundreds microamperes be flowed in the Zener diode at all times. This results in a large consumption power in the photomultiplier tube.
In the prior art described above, the voltage between the photocathode and the N-th dynode, that is, the voltage between the photocathode and the anode is changed to change the electron multiplication factor. However, a range of linearity of the anode current relative to the amount of incident light becomes narrow when the voltage between the photocathode and the anode is lowered. Therefore, the output linearity is degraded when the electron multiplication factor is lowered.
Japanese Laid-Open Patent Publication No. HEI-7-142024 is not involved with the above-described problems. Instead, a complicated operation is required to change the electron multiplication factor due to the provision of a large number of switches.

Voltage division circuit for a photomultiplier tube


An image recording device may include first and second housings, where the second housing is movable relative to the first housing. For example, the second housing may move from a first position to a second position in a first direction away from one end portion of the first housing and from the second position to the first position in a second direction toward the one end portion. In the first position, the second housing may contact the first housing with a surface of the second housing facing an accommodating area. A portion of the second housing may be located behind the other end portion of the first housing in the second direction, when the second housing is in the first position. In the second position, the surface of the second housing may cover the other end portion of the first housing in a direction perpendicular to the second direction.

1. Field of the Invention
The present invention relates to an image recording device comprising a first housing and a second housing disposed above the first housing which accommodates a printer therein.
2. Description of Related Art
A known image recording device, e.g., a multi-function device (MFD), has a scanning function and a printing function. A housing of a scanner is disposed on a housing of a printer. In the printer, a path for a user to access a recording unit is required for removal of paper jam and maintenance. The housing of the scanner is configured to pivot or slide relative to the housing of the printer.
It may be beneficial for an image recording device to be configured to provide an adequate access path to a recording unit while reducing restrictions in layout of components of the image recording device.

Movable housing configuration for an image recording device


Provided is a droplet discharging device (1) enabling the manufacture and discharge of microcapsules. A solution (16) containing the core material and shell material of the microcapsule is temporarily stored within a discharge tank (11) to which is disposed the oscillating body (12) of the droplet discharging device(1), and microcapsules are formed within the solution by oscillating the oscillating body (12) at a high frequency f1 and levigating the core material. Thereafter, the oscillating body (12) is operated at a relatively low frequency f2 in which the solution is able to respond, the solution is pushed outside from the tank (11), small amounts of the solution containing the microcapsule are discharged from the discharge nozzle (13), and microcapsules are applied to the target body.

1. Field of the Invention
The present invention generally relates to droplet discharging technology for discharging minute amounts of droplets, and in particular to a droplet discharging device capable of microencapsulating and discharging the object to be discharged (droplet), and to a manufacturing method of microcapsules.
2. Description of the Related Art
A microcapsule is generally composed of a content referred to as the core material, and a shell material which is a minute container for encapsulating this core material. Since a microcapsule possesses a function of protecting the core material from external environment and a function of adjusting the timing of being discharged to the outside, it is being used in a variety of fields such as pharmaceutical products, impact paper, aromatic substances, electrophoresis and so on.
This microcapsule is generally manufactured via the step of dispersing the core material into particulates in a suitable medium, and the step of coating such particles with the shell material. The ultrasonic wave method, homogenizer method, spray drying method or the like is employed for the levigation and micro-encapsulation of the core material.
For example, Japanese Patent Laid-Open Publication No. H05-285375 discloses an example of an ultrasonic wave method. In this example, employed is a probe device for generating ultrasonic waves from the tip of a metal probe composed of titanium or the like. The probe is dipped in a liquid containing keratin S-sulfur salt solution, organic solvent, core material and so on, and then subject to vibrational energy, whereby obtained is a microcapsule.
Further, for instance, Japanese Patent Laid-Open Publication No. H07-96167 discloses an example of the homogenizer method. In this example, while supplying an aqueous substance and hydrophobic substance, these are emulsified and dispersed with the high-speed rotation of a rotor, and the hydrophobic substance is thereby microencapsulated.
Nevertheless, the manufacture and use of microcapsules are estranged either in terms of time or space. A typical example of this would be when the place of manufacture and the place of use of such microcapsules differ, and this estrangement in terms of time or space leads to the deterioration in quality of the microcapsules. Appropriate storage and transport of the microcapsules will also become necessary.
Moreover, since a conventional manufacturing device of microcapsules adjusts the particle size of microcapsules via stirring, it is necessary to fill the microcapsule materials in the stirring container in an amount in which the stirring bar of the stirring mechanism will become buried to a certain degree. Thus, this is not suitable for production of microcapsules in slight or minute amounts. For example, since DNA fragment samples for forming a so-called DNA sensor (or DNA chip), medical drugs for testing and so on are extremely costly, problems will arise when these are to be microencapsulated.
In addition, a conventional manufacturing device of microcapsules is for producing one type in large amounts, and, when various microcapsules in which the particle size and core material selected arbitrarily are to be produced in minute amounts, the production efficiency is low.
Further, with a conventional manufacturing device of microcapsules, it is difficult to stir the material evenly, and distribution of the particle size of the manufactured microcapsules is broad. As a result, the nozzle hole of the droplet discharging device may clog up when applying the microcapsules with the droplet discharging method.

Droplet discharging device and manufacturing method of microcapsule


A method and system for circulating combined cooling, heating and power with a jet cooling device. An outlet of a working medium pump which is used to pressurize liquid working medium is connected to an inlet of a heater. An outlet of the heater is connected to an inlet of an expansion component. An outlet of the expansion component is connected to an inlet of a cooler. An outlet of the cooler is connected to a primary inlet of a jetting device. Primary outlets of the jetting device are respectively connected to an inlet of the working medium pump and an inlet of a throttle valve. An outlet of the throttle valve is connected to an inlet of an evaporator. An outlet of the evaporator and a gaseous outlet of the jetting device are both connected to an inlet of a pressurization component.

Energy is an important material base for the continuous progress of human society and plays a crucial role in national security and economic development. At present, fossil energy is still dominant in the energy structure, and the energy shortage is becoming increasingly severe with the gradual depletion of fossil energy.
A distributed energy technique and a principle of energy cascade utilization contribute to the improvement of the utilization ratio of overall energy, and can alleviate the problem of energy shortage. The combined cooling, heating and power belongs to the category of the distributed energy technique, and can simultaneously provide the energy in three forms, including cooling, heating and electricity, to satisfy people's demand for different forms of energy.
Based on the principle of cascade utilization, energy should be used according to its grade, high grade for high use, low grade for low use, in the technology of combined cooling, heating and power, which optimizes the energy supply, contributes to the reduction in irreversible losses in the energy conversion process, and has the characteristics of high comprehensive energy efficiency.
The technology of combined cooling, heating and power may use the combustion heat of the natural gas as a heat source, and achieves the supply of three different forms of energy with a system provided with three functional techniques, which can improve the overall energy efficiency of the system to a certain extent. However, three functional technique modules built in such a system work independently, such as using a gas turbine to generate electricity, using waste heat from the flue gas to drive an absorption refrigeration system, and using a flue gas heat exchanger to collect heat for heat supply, and therefore, problems occur such as complicated intermediate conversion processes of heat energy and relatively large overall irreversible loss; and further, since the modules are relatively scattered and occupy a large space, high initial investment for the system is required.

Method and system for circulating combined cooling, heating and power with jet cooling device

INSTITUTE OF MECHANICS, CHINESE ACADEMY OF SCIENCES