Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.

FPGA technology provides a flexible means to quickly transform a logic design into a working microelectronic chip by allowing a pre-fabricated chip to be programmed according to the specific design. An FPGA device (chip) comprises logic blocks, interconnects and input/output (I/O) blocks. These are pre-fabricated logic resources on an FPGA device with fixed locations, but many, and desirably most, of the resources on an FPGA device can be programmed to realize different logic functions and generate different signal paths to realize different logic designs.
There are usually two types of logic blocks on an FPGA device. The generic or generic logic block type can be programmed to realize any of many different logic functions. The dedicated type of logic block can only be programmed to realize a specific type of logic function (but in different sizes and configurations). One example of a function of a dedicated logic is as a memory module. In such a case, the dedicated logic block when programmed is a dedicated memory module. Most of the logic blocks on an FPGA device are of the generic type. Generic logic blocks are typically evenly distributed on an FPGA device. The logic blocks of the dedicated type are available only for limited types of logic functions and typically are only available in small quantities. Dedicated logic blocks are sparsely located on an FPGA device.
Memory modules or memory elements are important components of modern logic circuit designs. A simplified view of a memory module is as a collection of memory cells, each of which can store a single bit of information and can be read from and/or written into. The input/output signals pertaining to reading the information form a read port. The signals pertaining to writing the information form a write port. A port, in one alternative form, can also serve as both a read port and a write port.
A port in one exemplary form comprises an address bus, which is desirably a collection of input signals that select the memory cells to be accessed. A read port in one form has an output data bus, which is desirably a collection of signals that carries the information from selected memory cells. A write port in one form has an input data bus, which is desirably a collection of signals that carry information that is to be written to the selected memory cells. Each port also desirably has a number of control signals, such as clock signals that synchronize the operations of the memory module, enable signals that enable and disable the operations, and set/rest signals that apply special content to the memory cells and/or the output buses.
In one form of design implementation using an FPGA device, a memory module may be realized using generic logic blocks. This form of memory module implementation is referred to as a distributed memory implementation. Alternatively, in another form of design implementation using an FPGA device, a memory module may be realized using dedicated logic blocks for memories. This latter form of memory module implementation is referred to as a block memory implementation. If the size of the memory module exceeds the capacity of a single logic block of the chosen type, multiple blocks can be used, including blocks realizing the memory cells, and blocks realizing auxiliary logic that combine the blocks realizing the memory cells together.
It is rare that a memory module will fit into a single generic block. Memory implementation using dedicated memory blocks is often more efficient for large memory modules and is therefore often preferred by those skilled in the art of FPGA design. On the other hand, dedicated memory blocks on a FPGA are of limited quantity. When the total need for memory modules in a circuit design being implemented on an FPGA exceeds the available supply of dedicated memory blocks, or when other concerns arise, some memory modules may have to be implemented using distributed generic logic blocks. Determining which realization strategy to use for a memory module, or a portion of a module, is an important decision in the art of FPGA design.
Known approaches for implementing memory in a circuit design on an FPGA determine which blocks to be used to implement memory module(s) prior to the logic functions of the design being arranged and connected on the FPGA device. This is necessary in these known approaches because the arrangement and connection (placement and routing) requires that the logic functions be generated first. However, this also limits the ability to determine the optimal strategy for memory realization.
Because dedicated blocks are few and sparsely positioned, a memory module which is implemented using a dedicated block may have to be placed far away from its signal sources and/or destinations, yielding large signal propagation delays from and/or to the memory module. This adverse impact is difficult to foresee prior to placement and routing. Similarly, the implementation of memory using a combination of distributed blocks may also result in exceedingly large signal propagation delays at their inputs and/or outputs. In addition, large delays may be present in block-to-block interconnects, such as when there are so many logic blocks in the memory that they cannot readily be placed in a close proximity with their signal sources and/or destinations. Again, such impacts may only become clear after placement and routing is completed. In either case, any larger than anticipated signal delays will cause the design to operate at a slower speed.
Accordingly, a need exists for improvements in memory implementation on FPGAs which desirably takes into consideration the resource availability and distribution.

Memory re-implementation for field programmable gate arrays


A method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Also, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.

The present invention relates to a nonvolatile semiconductor memory and particularly relates to an electrically rewritable nonvolatile semiconductor memory (EEPROM, flash memory) employing memory cells each having a stack of a floating gate (charge accumulation layer) and a control gate.
The present invention also relates to a nonvolatile semiconductor memory utilizing a multilevel storage technique.
There is conventionally known, as a nonvolatile semiconductor memory which is electrically rewritable and capable of realizing high integration, an NAND type EEPROM having a plurality of memory cells mutually connected in series.
FIG. 1A is a plan view showing one NAND cell formed on a memory cell array on an EEPROM chip and FIG. 1B is an equivalent circuit thereof. FIG. 2A is a cross-sectional view taken along the line 2Axe2x80x942A of FIG. 1A.
FIG. 2B is a cross-sectional view showing one example of a cross section taken along the line 2Bxe2x80x942B of FIG. 1A and particularly shows a case of employing an LOCOS element isolation film (312).
FIG. 3 is a cross-sectional view showing another example of a cross section taken along the line 2Bxe2x80x942B of FIG. 1A and particularly shows a case of employing a trench element isolation insulating film (322). It is noted that a portion surrounded by a dashed line corresponds to the portion shown in FIG. 2B.
As shown in FIGS. 1A, 2A, 2B and 3, a memory cell array consisting of a plurality of NAND cells are formed on a P type silicon substrate (or P type well which will be referred to as herein) 311 surrounded by the element isolation oxide film 312. One NAND cell includes, for example, eight memory cells MC (MC1 to MC8) mutually connected in series.
Each memory cell MC has a stacked gate structure. The stacked gate structure consists of an insulating film 313 formed on the P type well 311, a floating gate 314 (3141 to 3148) formed on the insulating film 313, an insulating film 315 formed on the floating gate 314 and a control gate (CG) 316 (3161 to 3168 or CG1 to CG8) formed on the insulating film 315.
An N+ diffused layer (source/drain region) 319 of one memory cell MC is shared with its adjacent memory cell MC, whereby, for example, eight memory cells MC are connected to one another in series and one NAND cell is formed.
One end of a current path of the NAND cell is connected to a bit line BL (318) through a drain-side select gate transistor ST1 and the other end thereof is connected to a source line SL through a source-side select gate transistor ST2.
The gate electrode of each of the select gate transistors ST1 and ST2 has a structure in which the floating gate 314 (3149, 31410) and the control gate 316 (3169, 31610), for example, are electrically connected with each other at a portion which is not shown.
The P type well 311, on which memory cells MC, the select gate transistors ST1, ST2 and the like are formed, is covered with a CVD oxide film 317 or the like. The bit line (BL) 318 is arranged on the CVD oxide film 317. The bit line (BL) 318 extends in column direction.
The control gate CG (CG1 to CG8) of each memory cell MC is shared among NAND cells arranged in row direction and functions as a word line WL (WL1 to WL8). The row direction is a direction orthogonal to the column direction.
The gate electrode (3149, 3169) of the drain-side select gate transistor ST1 is shared among drain-side select gate transistors ST1 arranged in row direction and functions as a drain-side select gate line SGD.
The gate electrode (31410, 31610) of the source-side select gate transistor ST2 is shared among source-side gate transistors ST2 arranged in row direction and functions as a source-side select gate line SGS.
The data stored by one memory cell MC in the NAND cell is multilevel, i.e., binary or more.
In case of storing binary data, the range of the possible threshold voltages of the memory cells MC is divided into two types which are assigned data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively. In case of the NAND type memory, the threshold voltages after data erase are normally xe2x80x9cnegativexe2x80x9d and defined as, for example, xe2x80x9c1xe2x80x9d. The threshold voltages after data write are normally xe2x80x9cpositivexe2x80x9d and defined as xe2x80x9c0xe2x80x9d.
In case of storing multilevel data, e.g., four-level data, the range of the possible threshold voltages of the memory cells MC is divided into four types, which are assigned data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d, respectively. In case the NAND type memory, the threshold voltages after data erase are normally xe2x80x9cnegativexe2x80x9d and defined as xe2x80x9c11xe2x80x9d. The threshold voltages after data write are normally xe2x80x9cpositivexe2x80x9d and defined as xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d in the order in which threshold voltages are higher.
It is not always necessary that only the data after data erase have xe2x80x9cnegativexe2x80x9d threshold voltages. It suffices that the range of the possible threshold voltages of memory cells MC is divided into a plurality of types. It also suffices that the polarity of a threshold voltage, i.e., whether the threshold voltage is xe2x80x9cnegativexe2x80x9d or xe2x80x9cpositivexe2x80x9d, is opposite to that described above.
In the data write operation technique of such an NAND type EEPROM, a local self boost technique (LSB technique) is recently regarded as a favorable one. The operation of the NAND type EEPROM adopting the LSB technique will be described hereinafter with reference to FIG. 1B.
Data erase is roughly divided into two ways, i.e., batch erase and block erase.
In batch erase, the data of all the memory cells MC existing on the memory cell array are simultaneously erased. In this case, the potentials of all the control gates CG (word lines WL) on the memory cell array are set at 0V, the bit lines BL and the source lines SL are turned into a floating state, respectively and then a high voltage (e.g., 20V) is applied to the P type well 311. By doing so, electrons are discharged into the P type well 311 from the floating gates 314 of all the memory cells MC existing in the memory cell array and the threshold voltages of all the memory cells MC are shifted in negative direction.
In block erase, the data of the memory cells MC existing on the memory cell array are erased in units of blocks. Normally, one block consists of a group of NAND cells which are arranged in row direction and which share control gates CG (word lines WL). In this case, the potentials of the control gates CG (word lines WL) in a select block are set at 0V, a high voltage (e.g., 20V) is applied to control gates CG (word lines WL) in non-select blocks, the bit lines BL and the source lines SL are turned into a floating state, respectively and a high voltage (e.g., 20V) is applied to the P type well 311. By doing so, electrons are discharged from the floating gates 314 of the memory cells MC existing in the select block into the P type well 31 and the threshold voltages of the memory cells MC in the select block are shifted in negative direction.
The above-stated data erase operation is executed prior to the data write operation to be conducted to the entire memory cell array or the data write operation to be conducted in block units.
Before starting the description of the data write operation, it is assumed that a select control gate CG in the select block is xe2x80x9cCG2 (word line WL2)xe2x80x9d.
In the data write operation, a predetermined positive voltage Vsgd is applied to a select gate line SGD in a select block and 0V is applied to a select gate line SGS. Also, 0V is applied to all word lines WL and all select gate lines SGD and SGS in non-select blocks.
In this state, if data write is carried out by means of the LSB technique, the select word line WL2 is applied with a high voltage Vpp for data write, non-select word lines WL1 and WL3 adjacent to the select word line WL2 are applied with 0V, respectively, and non-select word lines WL4 to WL8 other than the non-select word lines WL1 and WL3 are applied with a voltage Vpass, respectively. The voltage vpass is almost in the middle of 0V and the data write high voltage Vpp. Although 0V is applied to the non-select word lines WL1 and WL3 in the above example, a positive voltage lower than Vpass may be applied thereto.
Data write is normally carried out sequentially from the memory cell MC8 farthest from the bit line BL toward the memory cell MC1 closest thereto.
When data xe2x80x9c0xe2x80x9d (or data having a xe2x80x9cpositivexe2x80x9d threshold voltage in this example) is written, 0V (write select voltage) is applied to a select bit line BL.
The data of the memory cell MC1 closer to the bit line BL than the select memory cell MC2 is always in an erase state (which data has a xe2x80x9cnegativexe2x80x9d threshold voltage in this example). Due to this, even if the voltage of the word line WL1 is set at 0V, the voltage of 0V applied to the bit line BL is transferred to the channel of the select memory cell MC2 and to an N+ type diffused layer 319 thereof. As a result, in the select memory cell MC2, electrons move from the P type well 311 to the floating gate 314 and the threshold voltage of the select memory cell MC2 is shifted in the positive direction.
When data xe2x80x9c1xe2x80x9d (or data having a xe2x80x9cnegativexe2x80x9d threshold voltage in this example) is written, a voltage (write non-select voltage) equal to or higher than the voltage Vsgd is applied to the select bit line BL.
Here, the select gate SGD is applied with the voltage Vsgd. Due to this, the select gate transistor ST1 becomes non-conductive and the channels and N+ type diffused layers 319 of the memory cells MC1 to MC8 are turned into a xe2x80x9cfloating statexe2x80x9d, respectively. In this state, if the write high voltage Vpp and the voltage Vpass are applied to the select word line WL2 and to the non-select word lines WL4 to WL8 other than the non-select word lines WL1 and WL3, respectively, then the channel potential of the select memory cell MC2 and those of the non-select memory cells MC4 to MC8 as well as the potentials of the N+ type diffused layers 319 are increased.
The memory cells MC1 and MC3 adjacent to the select memory cell MC2 are cut off by the back-bias effect caused by the increased channel potentials. At this moment, the high voltage Vpp is applied to the control gate CG2 (word line WL2) of the select memory cell MC2. Thus, the channel potential of the select memory cell MC2 is increased further. The channel potential of the select-memory cell MC2 rises to about 8 to 9V if the high voltage Vpp is, for example, 18V and a channel boost ratio is 0.5. Namely, the potential difference between the word line WL2 and the channel of the select memory cell MC2 is decreased to a value sufficient to provide a write inhibit voltage. As a result, in the select memory cell MC2, there is little movement of electrons from the P type well 311 to the floating gate 314 and the threshold voltage of the select memory cell MC2 is kept xe2x80x9cnegativexe2x80x9d.
In data read operation, a voltage (e.g., 3.5V) for continuity is applied to the select gate lines SGD and SGS in the select block and to the control gates CG (word lines WL) of the non-select memory cells. By doing so, the select gate transistors ST1 and ST2 in the select block and the non-select memory cells are turned xe2x80x9conxe2x80x9d. In this state, a read voltage of 0V or the like is applied to the control gate CG (word line WL) of the select memory cell in the select block. At this moment, the potential of the bit line BL is changed according to a current flowing thereto through the select memory cell. Whether data is data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is determined by detecting the changed bit line potential. In case of storing four-level data, it is determined whether the data is data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d or xe2x80x9c00xe2x80x9d.
As described above, in data write operation employing the LSB technique, a voltage not less than 0V and less than Vpass is applied to non-select word lines adjacent to a select word line which is applied with a high voltage, and the voltage Vpass is applied to the remaining non-select word lines.
With such an LSB technique, it is possible to increase the channel potential of the select memory cell, thus occurrences for writing errors at the time of particularly writing data xe2x80x9c1xe2x80x9d can be suppressed. Besides, since the variation of the threshold voltages of cells becomes quite small, the LSB technique is regarded as a favorable one particularly for writing data to a multilevel memory.
Nevertheless, problems are rising in the LSB technique as cells are made smaller in size and higher integration progresses.
The greatest feature of the LSB technique is that non-select memory cells adjacent to a select memory cell must be turned into a cutoff state irrespectively of the data stored in these non-select memory cells. The non-select memory cells adjacent to the select memory cell have arbitrary threshold voltages. Owing to this, there are cases where one of the adjacent non-select memory cells has a xe2x80x9cpositivexe2x80x9d threshold voltage or both of them have xe2x80x9cnegativexe2x80x9d threshold voltages (erase state).
To cut off these adjacent non-select memory cells by means of the back-bias effect caused by the channel potential, it is necessary to sufficiently increase the voltage Vpass or to control threshold voltage distribution after data erase to thereby sufficiently increase the lowest threshold voltage.
As regard the former case, to suppress the voltage Vpass-induced variation of the threshold voltages of the non-select memory cells connected to the non-select word lines and to the selected bit line, the voltage vpass cannot be set so high. To the contrary, the lower the voltage Vpass, the more effectively the threshold voltage variation of the non-select memory cells can be suppressed and writing error can be prevented. Considering this, therefore, it is essential to set the threshold voltage distribution after data erase to be higher within the range in which the erase state can be read and to sufficiently narrow the distribution width.
It is necessary that the distribution width of the threshold voltage after erase is limited within the range of, for example, xe2x80x9cxe2x88x923V to xe2x88x920.5Vxe2x80x9d.
In these circumstances, the present applicant proposed a soft write technique. The soft write technique is to gradually write data on a memory cell after erasing data and to gradually move the threshold voltage of the memory cell in positive direction. To be specific, after data is erased, using a sufficiently low voltage as a start voltage, a write pulse is applied to word lines for each block while repeatedly stepping up the start voltage and conducting verification for each block. This makes it possible to greatly narrow the distribution width of the threshold voltages after data erase.
The write operation in an NAND type EEPROM by means of the LSB technique and a technique for controlling a threshold voltage distribution after data erase by means of the soft write technique are mentioned in detail in the following references.
Japanese Patent Application No. 10-104652 (priority application of Japanese Patent Application No. 9-124493) discloses a technique for turning a memory cell in an over-erase state to a normal state by soft write (as well as for making erase verification).
Japanese Patent Application No. 9-340971 discloses a technique for conducting soft write and erase verification after erasing data from an NAND cell, determining that there are predetermined number of memory cells which threshold voltages reach a predetermined threshold voltage to finish the soft write and turning memory cells in an over-erase state into a normal state.
Japanese Patent Application No. 9-224922 discloses a technique for conducting erase verification and over-erase detection read while erasing data from an NAND cell and conducting data erase and soft write so that the threshold voltages in an erase state can be set between a desired upper limit and a desired lower limit while monitoring the threshold voltages of the memory cells.
FIGS. 4A and 4B show the concept of the soft write technique.
As indicated by xe2x80x9cINITIALxe2x80x9d in solid line in FIG. 4B, the distribution of threshold voltages Vth after block erase or batch erase is very wide.
As indicated by xe2x80x9cTbxe2x80x9d which is gradient shown in FIG. 4A, however, a memory cell easy to erase is also easy to write.
Accordingly, by optimizing a voltage for block erase or batch erase, a start voltage for later soft write as well as a step-up width to conduct erase verification for each block, it is possible to narrow the distribution width of threshold voltages Vth after data erase as indicated by xe2x80x9cSOFTWxe2x80x9d in dotted line shown in FIG. 4B. The reason for conducting verification for each block is that it requires shorter time to complete verification than the time required for conducting verification for each bit. As a result, it is possible to narrow the distribution width of the threshold voltages Vth compared with that after block erase or batch erase. Naturally, however, the distribution width narrowed by the soft write is greatly influenced by the irregularity of the write characteristic of memory cells within the respective blocks. For that reason, there is fear that the following problems may occur to the controlling of the distribution width by means of the soft write technique as miniaturization progresses in the future.
FIG. 5A shows the dependency of write characteristic on gate length. It is noted that the dependency is obtained under constant conditions for a voltage applied during data write and for a write pulse width.
As shown in FIG. 5A, the dependency of write characteristic on gate length is particularly great when a gate length L is within the range of 0.25 xcexcm or less. This is due to the influence of process irregularity, the short channel effect and the like. The great dependency of write characteristic on gate length means that write characteristic varies according to wafers, chips and blocks as the gate length L is shorter. It is not favorable to conduct verification at the time of soft write for each bit due to the limited erase time. Verification is, therefore, conducted on a block-by-block basis.
Thus, the irregularity of write characteristic has great influence on the distribution of threshold voltages after soft write. Consequently, writing errors and the variation of the threshold voltage increase particularly in a memory cell having a gate length L decreased to not more than 0.25 xcexcm.
AS can be seen from the above, the LSB technique is a promising technique among NAND cell write techniques, for preventing writing error or threshold voltage variation which may occur during write operation.
Nevertheless, as the miniaturization of memory cells progresses, it becomes more difficult to control the distribution of threshold voltages after data erase. Such controlling is quite significant for the LSB technique. If the distribution width of threshold voltages after data erase increases, writing errors or the like occur to the write operation after erase operation, resulting in the deterioration of reliability.
In one aspect of the present invention, a method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Also, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
In another aspect of the invention, a method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. The method also includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition, the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Furthermore, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a third read-out potential that is different from the first or second read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d and the bit data of the second digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Also, the method includes setting the source potential of the memory cell to a third source potential that is an in-between potential of the first and second source potentials and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d and the bit data of the second digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition, the method includes setting the source potential of the memory cell to the second source potential and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d and the bit data of the second digit is xe2x80x9c0xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Furthermore, the method includes setting the source potential of the memory cell to a fourth source potential that is obtained by adding the third source potential to the second source potential and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d and the bit data of the second digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
Objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.xe2x80x9d


A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to represent the functionality of the IP blocks. The implementations of these IP blocks exchanges messages through complex signaling protocols. In conventional systems, interfacing between IP blocks that use different signaling protocols is a tedious and error prone design task. The present invention uses regular expression based protocol descriptions to show how to map the message onto a signaling protocol. Given two protocols, the present invention builds an interface machine that automatically labels data referenced by all protocols. The present invention is capable of generating the interface even when the data sequencing of the two protocols differs.

1. Field of the Invention
The present invention is related to the field of electronic design automation (EDA) and more particularly to the field of interface synthesis for intellectual property (IP) blocks.
2. Description of Background Art
As time to market pressures and product complexities climb, the pressure to reuse complex building blocks (also known as Intellectual Property, or IP) also increases. Today, most IP is available only at the register transfer level (RTL). This is problematic because of verification speeds and the variety of signaling conventions used for interfacing between IP blocks.
The present invention addresses the problem of synthesizing interfaces between communicating IPs that use different signaling conventions. For this problem, a description of the entire behavior of the IP is not only cumbersome, but introduces unnecessary details that may hamper the design process. An interface-based design process that attempts to separate the communication from the behavior for IP is described in J. A. Rowson and A. L. Sangiovanni-Vincentelli, Interface Based Design, Proceedings of the 34th Design Automaton Conference, 178–183 (Jun. 9–13, 1997) which is incorporated by reference herein in its entirety. To separate the communication aspect of the IP blocks from their behavior, the blocks must be abstracted to a transaction or messaging level. With abstracted communication, improvement in simulation performance was shown with a simulator named Cheetah. However, the abstraction level that is appropriate for fast simulation is not efficient for implementation.
One problem is that given two communicating design actors exchanging data, e.g., IP blocks, and a description of the two protocols that each one of the IP blocks uses to transfer the data, an interface needs to be generated that ensures that data transfers are consistent between the two protocols.
Some conventional systems have attempted to address the problem of interface synthesis. One such conventional system is described in G. Borriello, A New Interface Specification Methodology and its Applications to Transducer Synthesis, Ph.D. Thesis, University of California at Berkeley, Berkeley Calif. (1988) and G. Borriello and R. H. Katz, Synthesis and Optimization of Interface Transducer Logic, Proceeding of the International Conference on Computer Aided Design (November 1987), which are both incorporated by reference herein in their entirety (together referred to as "Borriello". Borriello introduces an "event graph" to establish synchronization between the two protocols and data sequencing. One limitation of this approach is that before attempting to make the two protocols compatible, a user must manually assign labels to the data referenced by each protocol, because the specification of the protocols is given at a very low level of abstraction using waveforms.
A second conventional system is described in J. S. Sun and R. W. Brodersen, Design of System Interface Modules, Proceeding of International Conference on Computer Aided Design, 478–481 (1992) which is incorporated by reference herein in its entirety. This second system extends the Borriello approach by providing a library of components. Each component in the library must still be manually entered into the library. Accordingly, even in this second system the user must still consider lower level details.
A third approach is described in S. Narayan and D. D. Gajski, Interfacing Incompatible Protocols Using Interface Process Generation, Proceedings of the 32nd Design Automation Conference, 448–473 (Jun. 12–16, 1995) which is incorporated by reference herein in its entirety. In this approach the protocol specification is first reduced to the combination of five basic operations (data read, data write, control read, control write, and time delay). Then the protocol description is broken into blocks (called relations) whose execution is guarded by a condition on one of the control wires or by a time delay. Next, the relations of the two protocols are matched into sets that transfer the same amount of data. Although this approach is able to account for data width mismatch between the two modules, the procedural specification of the protocols makes it difficult to adapt different data sequencing.
Another conventional approach is described in J. Akella and K. McMillan, Synthesizing Converters Between Finite State Protocols, Proceedings of the International Conference on Computer Design, 410–413 (Oct. 14–15, 1991) which is incorporated by reference herein in its entirety. In this approach the protocols are described as two finite state machines (FSMs), while a third FSM represents the valid transfer of data. The product machine is taken and pruned of the invalid/useless states. One limitation in this conventional approach is that data width mismatch cannot be handled and that the designer must manually enter the intended behavior of the interface in the form of the third FSM (referred to as the C-machine).
What is needed is a system and method that overcomes the above identified limitations and: (1) automatically resolves the correspondence between data referenced by multiple protocols; and (2) generates an interface that can translate between different sequences of data without having to manually introduce the intended behavior of the interface process.

System and method for automatically synthesizing interfaces between incompatible protocols


A duty cycle correction circuit comprises a tuned circuit, a delay circuit and a phase-locked loop; wherein the tuned circuit receives an input clock, generates a periodic pulse according to the input clock, tunes the periodic pulse depending on a reference voltage, and outputs an output clock; a delay circuit receives the output clock, and generates a complementary signal; a phase lock loop receives the complementary signal, measures the periods of time of the high level state and the low level state of the complementary signal, generates the reference voltage and feeds back to the tuned circuit. By using the technique of the present invention, it is able to track the delay time between the input clock and the output clock, and the drift of the output clock is reduced.

A problem in current semiconductor memory system is that the duty cycle of the input clock isn't always unchanged. The rising edge and the falling edge of the input clock may drift back and forth in time domain when memory system is read or written data, which causes data indefinite.
Referring to FIG. 1, shows a duty cycle correction circuit of prior art. The circuit comprises a duty cycle corrector 11 and a delay locked loop 15. Wherein the duty cycle corrector 11 receives an input clock (Clk_in), corrects the duty cycle of the input clock (Clk_in), and generates a correction clock (Clk_dcc). The delay locked loop 15 connected to the duty cycle corrector 11 receives the correction clock (Clk_dcc), and generates an output clock (Clk_out).
The delay locked loop 15 requires a first locking times of making the phase of the received correction clock (Clk_dcc) the same as the output clock (Clk_out).
The duty cycle corrector 11 requires a second locking times of making the phase of the received input clock (Clk_in) the same as the correction clock (Clk_dcc).
In accordance with the above prior art skill, which could be improved the drifting condition of the duty cycle. But the duty cycle correction circuit shows by FIG. 1 without the function of feed backing, therefore the delay time between the input clock and the output clock can't be tracked and reproduced.
Besides, the duty cycle correction circuit of the prior art for making the phase of the input clock (Clk_in) can equal the output clock (Clk_out). Whole circuit locking time is the sum of the first and second locking times in the case where the duty cycle corrector 11 and the delay locked loop 15 are serially connected.
The locking time is too long which is causing circuit unsteady. Drifting and phase noise still exist in the correction clock (Clk_dcc) and the output clock (Clk_out) from the duty cycle correction.


A flow sensor for compressible fluid comprising a central hub having a total pressure chamber and a static pressure chamber disposed therein. A pair of wings extend radially outward from opposing sides of the total pressure chamber. The wings include a plurality of radially spaced holes oriented to generally face an upstream direction and an internal wing passageway connecting the spaced holes to the total pressure chamber. The sensor also includes a static tube having a tube wall extending outward from the static pressure chamber from a first attached end to a second distal closed end. A generally upstream facing hole and a generally downstream facing hole are disposed on opposing sides of the tube wall intermediate the first and second ends to define a fluid flow passage therethrough. An internal tube passageway connects the flow passage to the static pressure chamber.

The present invention relates to air control and distribution devices used in commercial air distribution systems. More specifically, the present invention relates to a flow sensor for a compressible fluid, such as air, having a fluid flow, wherein the flow sensor samples and averages the total pressure profile over the cross section of a duct.
Airflow sensors are used to measure the quantity of air flowing in the ducting of air-conditioning systems to provide control signals to an air terminal. Air terminals are devices of an air-conditioning system that modulate the volume of air delivered to a conditioned space, e.g., of a building, in response to a given thermal load. Examples of various types of air terminals include: variable air volume (VAV) units, bypass terminals, integral diffuser terminals and dual duct terminals.
As the air to be measured flows through the ducting from an upstream direction toward a downstream direction, pressure is generated in all directions in the form of a static pressure. Moreover, on the duct walls perpendicular to the direction of flow, the static pressure is the primary component of pressure. In addition, there is an impact pressure (velocity pressure) on anything that is facing upstream of the direction of flow. The combination of these two forces is called total pressure. Thus, the force on any object in the airflow path that faces the upstream direction has this total pressure acting on it. To derive airflow as a quantity over rate of time, e.g., cubic feet per minute (CFM), from the pressures measured in a duct system, one must subtract the measured static pressure from the measured total pressure to obtain the velocity pressure.
Prior art pitot tube type instruments have been used to perform this task. However, the use of a single pitot tube in the air stream does not provide accurate results. This is because the total pressure varies at different points along the cross section of a duct system, due primarily to frictional drag forces of the air against the duct walls.
Problematically, the traditional pitot tube design provides no amplification of the differential between the static pressure and the total pressure, which is often very small. This is especially problematic in cases of low velocity pressures that are inherent to low CFM, such as when a VAV unit is operating at its minimum rated flow. Consequently, many industrial pressure transducers have difficulty reacting to changes in velocity under low flow conditions when used with such prior art flow meters utilizing a traditional pitot tube design.
Other prior art airflow sensors have been developed which require the averaging of multiple measurements over the cross section of the duct to determine total pressure. One such prior art airflow sensor is disclosed in U.S. Pat. No. 5,481,925 to Woodbury, filed on Sep. 9, 1994 (hereinafter xe2x80x9cWoodburyxe2x80x9d).
Woodbury describes an airflow sensor adapted to be mounted within a flow conduit. The airflow sensor includes a streamlined central hub, at least two pair of upstream airflow sensing tubes and a corresponding number of downstream airflow sensing tubes. The central hub is of air foil shape having an upstream region smoothly transitioning to a downstream region. The upstream airflow sensing tubes are diametrically opposed and extend radially outwardly from the central hub. Each of the upstream airflow sensing tubes including a plurality of radially spaced holes. The holes fluidly connect regions exterior to the tube to an internal flow passage thereof. The holes are spaced from one another such that each hole receives airflow from an equal concentric cross-sectional area of a flow conduit and face upstream to sample the varying total pressure profile along the conduit. The upstream tubes also include a streamlined attachment member for attaching the tubes to an inner wall of the flow conduit. The downstream airflow sensing tubes extend radially outwardly from the central hub a distance shorter than a distance of radial extension of the upstream airflow sensing tubes. Each downstream airflow sensing tube has a single inlet at an end thereof and is circumferentially spaced from a respective adjacent upstream airflow sensing tube in order to measure static pressure within the duct.
However the plurality of upstream facing holes of Woodbury are spaced such that each hole receives airflow from an equal concentric cross sectional area of flow in the duct. This spacing pattern fails to account for the frictional losses at the duct wall. This error can be especially problematic in rectangular ducts.
Moreover, noise is often a problem in prior art flow sensors. Excessive noise levels generated by a flow sensor under normal operating conditions can be a critical factor in a potential customer""s decision to buy. The noise generation issue is of such importance that the Air-Conditioning and Refrigeration Institute (ARI), one of the primary standard making bodies of the refrigeration industry, has developed Standard 880 (herein incorporated by reference). Standard 880 measures and publishes noise levels for air terminals, of which airflow sensors are very often used therein. In order to enhance performance ratings during the standardized test conditions imposed by ARI 880, many airflow sensors, e.g., Woodbury, have a streamlined shape. However, certain streamlined shapes perform better than others for different types of equipment. It is therefore important for a manufacturer to determine the best streamline shape required to optimize noise level performance of its equipment.
Accordingly, there is a need for an improved flow sensor for measuring the flow of a compressible fluid, such as air, in a duct.
The present invention offers advantages and alternatives over the prior art by providing a flow sensor for a compressible fluid, which utilizes radially spaced holes to average the total pressure profile of the fluid flow in a duct. Additionally, the flow sensor utilizes a static tube having a closed distal end and a flow passage therethrough to amplify the differential between the static pressure and the total pressure. Moreover, the flow sensor has a streamlined shape to reduce operating noise levels and minimize pressure drop across the flow sensor.
These and other advantages are accomplished in an exemplary embodiment of the invention by providing a flow sensor for compressible fluid having a fluid flow from an upstream direction toward a downstream direction. The flow sensor comprises a smoothly contoured central hub having a total pressure chamber and a static pressure chamber disposed therein. A pair of wings extends radially outward from opposing sides of the total pressure chamber of the hub. The wings include a plurality of radially spaced holes oriented to generally face the upstream direction and an internal wing passageway connecting the spaced holes to the total pressure chamber. The flow sensor also includes a static tube having a tube wall extending radially outward from the static pressure chamber of the hub from a first attached end to a second distal closed end. A generally upstream facing hole and a generally downstream facing hole are disposed on opposing sides of the tube wall intermediate the first and second ends to define a fluid flow passage therethrough. An internal tube passageway connects the flow passage to the static pressure chamber.
In an alternative embodiment of the invention, the flow passage of the static tube of the flow sensor is shaped to provide a vortex effect which reduces static pressure of the fluid within the static pressure chamber relative to static pressure of the fluid external to the static chamber. By reducing the static pressure, the differential between the static pressure and total pressure is effectively amplified.
In another embodiment of the invention the radially spaced holes on the wings of the flow sensor are substantially spaced per the Log-Tchebycheff rule. By spacing the holes as such, losses due to frictional forces between the walls of a duct and the fluid flow are taken into account.
In another alternative embodiment of the invention the wings and hub of the flow sensor have a substantially elliptical shape to reduce noise levels generated by the flow sensor and minimize pressure drop across the flow sensor.

Airflow sensor for averaging total pressure


Pavement markers are provided that are equipped with installation tabs which permit marker storage vertically and which permit hand holding of the individual markers during installation. After a marker is installed, each tab is breakable adjacent to the marker upper surface in response to an applied small bending force. The tabs overcome the problem of installing pavement markers upon hot tar.

Pavement markers which have convexly rounded upper surface portions and convexly extending perimeters have come into general usage particularly for use in vehicular lane marking. For example, by placing a series of markers upon the center line of a two-lane paved road with the markers being longitudinally spaced from one another, improved ability is provided for a vehicle driver to stay in his assigned proper lane is provided. A vehicle driver traveling in either direction either sees the markers or senses the vibration when tires of his vehicle strike individual markers successively. At least some of the pavement markers of a center line located series can each be associated with retro-reflective reflector means for viewability by approaching vehicle drivers during nighttime.
At the present time, pavement markers are installed manually. Each individual pavement marker of a series is positioned by hand and is conveniently adhered to a paved road surface at a desired location and oriented position by means of an adhesive. A presently commonly used adhesive is hot tar during installation.
The convexly rounded upper surface portions of a pavement marker cannot be held by an installer's hand since no gripping surface exists. For an installer to hand hold a pavement marker along opposed portions of its opposite edges is dangerous because of the potential for finger and/or thumb burns from exposure to the hot tar during final positioning and contacting of an individual pavement marker with freshly deposited hot tar during installation.
There is a substantial need in the art of pavement markers for a system or means for manually holding an individual pavement marker in such a way that the chance of injury to an installer's hand is substantially eliminated.

Pavement markers with frangible installation tabs


According to one embodiment, a three-dimensional image display apparatus displays, when an event of requesting a check of a viewing position occurs, a three-dimensional image for testing, by displaying on the display a three-dimensional display image which is obtained by using a left-eye image and a right-eye image included in the three-dimensional still image data for testing in a storage device. The three-dimensional image for testing includes such a first image that when the three-dimensional image for testing is viewed from a predetermined viewing area, stereoscopic images of a plurality of vertical rods disposed at different depth positions are perceived.

In recent years, various types of three-dimensional (3D) image display apparatuses for viewing three-dimensional (3D) images, for instance, a three-dimensional (3D) TV, have been provided. In such 3D image display apparatuses, for example, a user is enabled to perceive 3D images (stereoscopic images) by using left-eye images and right-eye images based on binocular disparity.
Methods of displaying 3D images are classified into a glasses method using 3D glasses and a naked-eye stereopsis method (glasses-less 3D method). The methods of using 3D glasses include a shutter method (active method) and a polarization method (passive method). As the naked-eye stereopsis method (glasses-less 3D method), there are known, for instance, a lenticular method, a barrier method and an integral imaging method.
In these 3D image display apparatuses, an observer (user) can perceive normal stereoscopic images, that is, real stereoscopic images ("3D viewing") when viewing the display screen from a correct position. However, if the viewing position deviates from the correct position, stereopsis is no longer effected, and a phenomenon, such as crosstalk (3D crosstalk) or pseudoscopy, will occur. If 3D crosstalk occurs, a decrease in stereoscopic effect of the images, a decrease in depth effect of the images or appearance of double images (ghost images) will occur. Pseudoscopy is a phenomenon in which a left-eye image is incident on the right eye and a right-eye image is incident on the left eye. The crosstalk and pseudoscopy may possibly become factors which cause eyestrain of the user.
However, even when the user views an ordinary 3D moving picture such as a 3D movie or 3D TV broadcast program, the user cannot always confirm whether the user is actually enjoying 3D viewing. The reason for this is that picture patterns vary one after another in an ordinary 3D moving picture, and the picture patterns are complex. Thus, the user is unable to discriminate whether stereoscopic images, which the user currently perceives, are real stereoscopic images, and it is difficult for the user to confirm whether the present viewing position is within a correct viewing area (3D viewing area).

Three-dimensional image display apparatus and viewing position check method


A system for controlling the excitation of an alternator field coil. The system comprises a capacitor forming a charge reservoir, a first and a second selectively operable switch connected to opposing ends of a field coil of the alternator, a first catch diode, and a second catch diode. At least one of the first and second switches are operated at a variable duty cycle and the capacitor both absorbs energy from the field coil and supplies energy to the field coil to regulate the magnetic field of the field coil, effective to regulate the output voltage of the alternator and rapidly compensate for changes in at least one load connected to the alternator.

There is a desire on the part of vehicle manufacturers to increase the electrification of vehicle auxiliary loads by reducing the number of engine accessories that depend directly on the fueled-engine as a prime mover. Examples include the vehicle's power steering pump, hydraulic drives, engine cooling fan, air conditioning compressor, oil and coolant pumps, and air compressors. An advantage of accessory electrification is reduced engine loading, which facilitates greater engine performance, increased flexibility in locating the accessories, reduced fuel consumption, more efficient accessory operation, and reduced vehicle emissions.
In addition to engine accessories, many vehicles include ancillary electrical accessories directed to the mission of the vehicle and/or comfort of the vehicle's occupants. For example, an emergency vehicle includes exterior emergency lighting, heating, ventilation and air conditioning ("HVAC"), interior lights, radios and medical equipment. Many trucks, such as long-haul transport tractor-trailer semis, include radios, exterior and interior lights, and a sleeper compartment having a variety of household appliances such as televisions and microwaves that are operable from AC power supplied by a DC-to-AC inverter.
Vehicle electrical systems typically include one or more batteries comprising an electrical power supply, with an engine-driven alternator being employed to augment and charge the battery. A particular problem of such systems is that the loading of the system and, consequently, the alternator output constantly changes as various engine and ancillary accessories are switched on and off. The output of the alternator, which varies in proportion to the load on the electrical system and the discharge of the battery, responds relatively slowly to the changes in loading due to the inductive time constant of the field and stator coils of the alternator. This can adversely affect the voltage regulation of the vehicle's electrical system. For example, if a high-power exterior light is switched on, the increased loading of the electrical system causes the electrical system voltage to decrease until the alternator eventually responds by increasing its output voltage. Conversely, when a load is switched off, the electrical system voltage may surge to a higher level than is desirable until the alternator output is reduced. The slow response of the alternator to changing load conditions thus results in relatively poor electrical system voltage regulation. This problem is exacerbated when a number of accessories are randomly switched on and off at any given time. There is a need to improve an alternator's response to varying load conditions within a vehicle's electrical system.


A metal film 4 is disposed between a permanent magnet 3 and a rotor yoke 1, and the permanent magnet 3 and the rotor yoke 1 are subjected to beam welding. Since the metal film 4 is disposed between the permanent magnet 3 and rotor yoke 1, and the metal film 4 as a laser beam irradiated portion is melted by vacuum beam or laser beam, the metal film 4 has brazing metal function in welding, so that the connection between the permanent magnet 3 and the rotor yoke 1 is strong. Since there is no need of embedding the permanent magnet 3 in the rotor yoke 1 and there is no need to use polymer adhesives, the cost can be reduced.

In rotors used in permanent magnet type motors used as power sources for automobiles, various kinds of techniques have been proposed in order to improve characteristics relating to durability, cost, magnetic efficiency, heat dissipation, and connection strength between a rotor yoke and a permanent magnet, etc., in accordance with intended use.
In the above rotors for permanent magnet type motors, for example, a technique has been proposed, in which a permanent magnet is embedded in a rotor yoke so as to improve durability (for example, see Japanese Unexamined Patent Application Publication No. Hei 6-38415). A technique has been proposed, in which a rotor yoke and a permanent magnet are connected to each other by sintering so as to improve magnetic efficiency and heat dissipation (for example, see Japanese Unexamined Patent Application Publication No. Hei 7-177712). A technique is proposed, in which a rotor yoke and a permanent magnet are connected by using an adhering technique by polymer material so as to reduce the cost and improve the connection strength therebetween (for example, see Japanese Unexamined Patent Application Publication No. 2002-272033).
However, in the rotor disclosed in the above Japanese Unexamined Patent Application Publication No. Hei 6-38415, a rotor is relatively high in cost since the rotor yoke is disposed between permanent magnets so that the rotor is double in radius, and magnetic efficiency based on air gap between the rotor and a stator is low since the permanent magnet is not exposed on a surface of the rotor. In the rotor disclosed in the above Japanese Unexamined Patent Application Publication No. Hei 7-177712, the rotor is relatively high in cost due to manufacturing equipment used in a powder metallurgy method, the connection strength at high temperature and at high speed rotation and the durability including thermal shock are low since sintering connection without an adhering medium is adopted, and manufacturing cannot be performed when the yoke has a stacked structure since a powder metallurgy method cannot be applied thereto. In the rotor disclosed in the above Japanese Unexamined Patent Application Publication No. 2002-272033, the durability of the rotor is lowered since adhesives composed of a polymer are softened at temperatures during the use of the rotor, and heat dissipation from the permanent magnet to the rotor yoke is low since adhesives for permanent magnet have thermal conductivity lower than metal films, so that heat does not dissipate to a side of the rotor. In the rotor disclosed in the above Japanese Unexamined Patent Application Publication No. 2002-272033, when the adhesives composed of the polymer material are used, magnetic efficiency based on air gap between the rotor and a stator and magnetic efficiency based on the included gap between the permanent magnet and the rotor yoke are low.
Therefore, in recent years, techniques have been required such that all characteristics regarding the durability, the cost, the magnetic efficiency based on the air gap between the rotor and the stator, the magnetic efficiency based on the included gap between the permanent magnet and the rotor yoke, the heat dissipation, and the connection strength between the rotor yoke and the permanent magnet favorably reach high levels.


A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.

Individual electrical components of a semiconductor device were originally integrated on a silicon wafer by forming a vertical back to back diode between the components. This was done by forming a lightly doped epitaxial layer ("epi" layer) over a substrate of the opposite doping type. Then a deep junction of the same type as the substrate was diffused down from the top of the epi layer to the substrate.
In this way two back to back diodes were formed from the epi layer on one side of the deep junction to the epi layer on the other side. Because the junction had to be driven all the way down through the epi layer to the substrate, and because the diffusion process proceeds in all directions, this method required a great deal of space to implement. Because the electrical components must be spaced away from the heavily doped junctions there had to be sufficient space provided for the lateral diffusion of the junction as the junction was driven down to the substrate. The back to back diode method did, however, provide a way to connect the front of the wafer to the substrate.
The local oxidation of silicon (LOCOS) method was also later used to isolate the individual electrical components in a semiconductor wafer. The LOCOS method, however, only provides surface isolation. Therefore, electrical components that require deep isolation are not isolated using the LOCOS method.
Shallow trench isolation has been used to replace the LOCOS method of isolation. Shallow trench isolation provides isolation in a more space efficient manner than LOCOS isolation. But because LOCOS isolation only provides surface isolation an additional method is required to provide deep isolation. Typically, when deep isolation is required, a deep trench is used in conjunction with a shallow trench. The combination of the deep trench and the shallow trench does not provide a method of connecting to the substrate.
Therefore, there is a need in the art for a system and method for providing a deep connection to a substrate or buried layer of semiconductor device. There is also a need in the art for a system and method for combining shallow trench isolation with partial deep diffusion to provide a deep connection to a substrate or buried layer of a semiconductor device.

Method for providing a deep connection to a substrate or buried layer in a semiconductor device


A display that can be expanded from a collapsed position for storage and transport to an expanded position for free-standing operation and use. A spinal member is disposed between front and back panels such that in the collapsed position, the spinal member maintains the two panels substantially adjacent one another in a generally two-dimensional shape. Upon movement of at least a portion of the spinal member relative to the panels, parts of the spinal member bias the panels apart from one another to form an expanded, three-dimensional shape. This shape provides a sufficient footprint of the display relative to its height that the display can be free-standing. The cooperative relationship between the spinal member and the panels is such that no rubber bands or related elastic devices are required to maintain the display in the expanded position.

This invention relates generally to a stand-up display used for advertising and related retail functions, and more particularly to such a display that expands (i.e., pops out) from a generally planar two-dimensional shape into a three-dimensional shape with a minimal amount of human intervention.
The use of stand-up displays is commonplace in the modern retail environment. In such devices, a generally portable, lightweight display is placed to attract consumer attention to a particular good or service. Visual attributes, such as life-size pictures of a celebrity endorser or the like, entice a would-be consumer to consider purchasing the good or service advertised thereon. Similarly, such displays may also be used for public service or related non-commercial information. While such displays are effective vehicles for conveying a desired message, their physical dimensions (often measuring over two feet wide by more than five feet tall) make them unwieldy and expensive to transport. To that end, folding displays have been developed that can be stored and shinned in a compact, generally two-dimensional shape and that, upon expansion, assume a three-dimensional shape when in use. In such configurations, articulating flaps, expandable box-like members, elastic bands or combinations of the above can be used such that when the display reaches its destination, one or more people can assemble the display to ready it for its intended use.
The foldable displays have certain drawbacks, despite offering additional flexibility over their nonfoldable counterparts. The complex construction of the articulating parts of some displays are such that skilled assemblers are required, sometimes in teams of two or more. In either case, such complexity increases the cost associated with the display. Accordingly, there is a need to provide foldable, stand-up displays with simple construction so that a single unskilled installer can set up the displays quickly. In addition, many such displays employ numerous discrete parts that can become separated from the displays, making effective display construction more complicated. Accordingly, there is also a need to provide stand-up displays that reduce or eliminate the number of separable parts required for assembly of the displays. Moreover, the support structure used to give rigidity to present foldable displays is often located on the rear surface of the display. Such structure can detract from the appearance of the display, especially where the display is situated such that people can see both the front and rear surfaces. Furthermore, such structure takes up additional floor space. Accordingly, there is a need for a stand-up display that also keeps much, if not all, of the articulating componentry hidden from view.


A LCD substrate having a supporting buffer film formed around it outer edges and method for making same.

The present invention relates to a substrate for a liquid crystal display (LCD) and method for manufacturing same. More particularly, the invention relates to an LCD substrate formed with a bordering buffer film which reduces substrate warping. The present invention also relates to a method for manufacturing the foregoing LCD substrate.
The conventional manufacturing process for LCDs begins with a glass substrate. The glass substrate is cleaned, or "washed," and a matrix of thin film transistors (TFTs) and related pixel elements are formed on the glass substrate by known techniques. A liquid crystal is then injected into a space between the thus fabricated glass substrate structure and an opposing color filter substrate, or similar opposing surface.
of particular note, the conventional glass substrate is flexible to a certain degree. For example, a conventional glass substrate 1 will bow or curve in the middle when carried on edge supports 6, as shown in FIG. 1. The bow shown in FIG. 1 is exaggerated to illustrate the difficulty arising when even slight bowing occurs in the glass substrate. That is, bowing may cause lifting or shifting of the semiconductor layers subsequently formed on the conventional glass substrate. For example, the aluminum film forming the gate electrodes of the TFTs may separate from the substrate and actually create shorts and opens in the electrode paths. Bowing, warping in any direction, may become particularly pronounced in high temperatures applied to the glass substrate during heat treatment steps common to the manufacture of the LCD. As LCDs increase in size, the tendency of the underlying glass substrate to warp under its own weight only increases. The resulting effects of glass substrate warping can be disastrous.

Substrate for a liquid crystal display and method for manufacturing same


Provided herein are methods for making an alpha-tocotrienol enriched tocol mixture, such as from a plant or plant-derived material. Also provided herein are simulated moving bed purification methods for tocotrienol compounds such as alpha tocotrienol.

Certain plants contain mixtures of tocol compounds, such as tocopherol (alpha, beta, gamma and/or delta tocopherols) and/or tocotrienol (alpha, beta, gamma and/or delta tocotrienols) compounds. Previous methods have been used to obtain alpha-tocotrienol containing compositions from natural plant sources, such as palm oils and refined palm oils. Some processes for producing alpha-tocotrienol from plant sources produce alpha-tocotrienol by alkylating beta-, gamma-, and delta-tocotrienols; however, those processes result in a lower amount of alpha-tocotrienol than might otherwise be obtained. In particular, it has been difficult to obtain desirable amounts of alpha-tocotrienol from plant sources containing more than about 5% phytosterol content.
What is needed are improved methods for enriching alpha-tocotrienol from natural plant sources. Furthermore, what is needed are methods for enriching alpha-tocotrienol from natural plant sources, wherein higher amounts of alpha-tocotrienol may be obtained by converting the beta-, gamma-, and delta-tocotrienols to alpha-tocotrienol. The methods provided herein are capable of solving this and other problems.

This patent is subject to a terminal disclaimer.

Methods for enriching alpha-tocotrienol from mixed tocol compositions


A cleaning device, cleaning system and method relating thereto are provide. The cleaning device comprises (a) a handle unit having a (i) a handle section and (ii) a support section, (b) a body comprising (i) a deformable foundation supported by the support section (ii) a lofted fibrous material overlaying the foundation (iii) water proof plastic layer covering the fibrous material to prevent water contact of the fibrous material and foundation; (c) a cleaning skirt optionally having (i) a cloth cleaning section for enveloping the body and (ii) an elastic section for selectively retaining the skirt on the body. The cleaning system comprises (a) the cleaning device and (b) a plurality of cleaning skirts. The cleaning method comprises (a) providing a cleaning device as set out above, (b) cleaning a first household item with the device, (c) replacing the used skirt with a second skirt, and (d) cleaning a second household item with the device. The cleaning device, system and method are useful for cleaning of a plurality of household items.

1. Field of the Invention
The present invention relates to cleaning tools and methods related thereto, and more particularly relates to handled cleaning tools and methods related thereto.
2. Description of the Related Art
Conventional cleaning techniques for cleaning of household structures such as windows, tables and dishes have typically involved the need to utilize separate cleaning tools and cleaning solutions. For example, cleaning of windows often utilizes a cloth rag, a bucket of water-based cleaning composition and a squeegee-type water remover; cleaning of tables has typically involved the use of a duster, cloth rag, and a furniture polish composition; and cleaning of dishes has often used a cleaning brush, a cleaning rag, soap and water.
Consequently, cleaning of multiple household items has typically required plurality of tools to clean the multiple household items.

Cleaning device cleaning system and method related thereto


An electrical device having carbonized conductors and a method and a device for the production thereof is disclosed. The electrical device has electrical components having connections. Furthermore, there are situated between the electrical components regions made of plastic with conductors having carbonized plastic and/or agglomerated nanoparticles. The conductors are connected to the connections of the components and/or to external connections of the electronic device.

The wiring and packaging of electrical components and/or semiconductor chips to form compact electrical devices is extremely complex and costly. Thus, it is necessary to provide external contacts which are to be connected to electrodes of the electrical components and/or to contact areas of semiconductor chips via a plurality of wiring layers or multilayer substrates. Through contacts have to be provided between the wiring layers or in the multilayer substrates in order that the conductor tracks of the different layers are electrically connected to one another via said through contacts. The production of electrical devices constructed in this way is thus complicated and cost-intensive.

Electrical device comprising conductors made of carbonized plastic, and method and apparatus for the production thereof


The present invention relates to a method for treating conditions associated with elevated levels of Tac-positive cells, including malignancy and autoimmune disorders and for preventing allograft rejection. 90Y-Conjugated anti-Tac or Ricin A conjugated anti-Tac and optionally unconjugated anti-Tac antibodies are employed to treat the above conditions. Clinical therapies have been designed to treat immune diseases and lymphomas in patients using conjugated anti-Tac antibodies.

1. Technical Field
The present invention is related to a method for treating malignancy and autoimmune disorders and for preventing allograft rejection. More particularly, the present invention is directed to treating any human condition or disorder related to the expression of Tac antigen or involving abnormal IL-2- receptor expression, by reacting Tac antigen or IL-2 receptor expressing cells with anti-Tac antibody or a preparation thereof.
2. State of the Art
The normal resting cells of the body, including T cells, do not express IL-2 receptors and thus do not react with a monoclonal antibody anti-Tac that recognizes the human IL-2 receptor. However, in certain conditions, such as in leukemic T cells of patients infected with human T-cell lymphotrophic virus I (HTLV-I-associated Adult T Cell Leukemia), large numbers of IL-2 receptors are constitutively expressed.
The Tac antigen (also referred to herein as "IL-2Rα") is also expressed in other malignant conditions including the malignant B lymphocytes of Hairy cell leukemia, follicular lymphoma and the Reed-Sternberg cells of Hodgkin's disease. Furthermore, activated T cells expressing the Tac antigen also appear to play a pathogenic role in certain forms of autoimmune disorders, such as type I diabetes and a subset of patients with aplastic anemia. In addition, when cells responding to foreign histocompatibility antigens become activated, they express the Tac antigen and participate in allograft rejection such as in patients receiving vascularized organ allografts and in graft-versus-host disease in patients receiving marrow allografts. Thus, there are a number of clinical circumstances where the expression of Tac-antigen is involved. Clearly, therefore, the elimination of Tac-positive cells using the anti-Tac monoclonal antibodies would be of value in treating or controlling such pathological states.
The use of chemotherapeutic agents has cured some types of cancer. However, many types of cancer either are initially unresponsive or subsequently acquire resistance to chemotherapy. The development of monoclonal antibody technology by Kohler and Milstein (1975 Nature, 256:495) rekindled interest in the use of antibodies targeted to cell surface antigens to treat cancer patients. However, monoclonal antibodies are just beginning to fulfill the promise for immunotherapy inherent in their great specificity for recognizing and selectively binding to abnormal cells. A number of factors underlie the low therapeutic efficacy observed initially. Unmodified murine monoclonal antibodies are immunogenic and elicit a human immune response. Moreover, most of the mouse monoclonal antibodies used were not cytocidal against neoplastic cells in humans. Finally, in most cases the antibodies used were not directed against a vital cell surface structure such as a receptor for a growth factor that is required for both tumor cell proliferation and the prevention of apoptotic cell death induced by factor deprivation.
Adult T-cell leukemia is a malignancy of T lymphocytes with a median survival time of 9 months in the acute and 24 months in the chronic form of the disease. Various combination chemotherapies have not significantly increased the survival of patients with ATL. In light of the disappointing results using conventional combination chemotherapy, IL-2R-directed therapy was developed to exploit the observation that normal resting cells, including the unaffected normal T cells of patients with ATL, do not display IL-2Rα, whereas the leukemic cells express this interleukin receptor subunit.
Hodgkin's disease currently has an annual incidence of 4/100,000 in the United States. Tumors in the lymph nodes of affected patients are composed of nonmalignant lymphocytes far outnumbering the malignant Reed-Sternberg cells, which may express T or B cell markers. 40% of patients will have stage I or II disease, which is curable in >90% of cases with radiation and/or chemotherapy.
Non-Hodgkin's lymphoma is becoming more common in the U.S. The annual incidence, which does not include HIV-related cases, is about 15/100,000, over 30-60% higher than 12 years earlier. It is the most rapidly increasing cause of cancer death in white men and in white women is second only to lung cancer. T-cell varieties include cutaneous and peripheral T-cell lymphomas and lymphoblastic lymphoma. B-cell varieties are more common, and are divided into low, intermediate and high grades.
Peripheral T-cell leukemia/lymphomas including T-cell chronic lymphocytic leukemia (CLL) as well as Ki-1 lymphoma, also known as anaplastic large cell lymphoma, frequently expresses IL-2Rα on the surface of a significant proportion of the malignant cells. The malignant cells of between 21 and 47% of patients with HTLV-I negative peripheral T-cell lymphomas express IL-2Rα on the surface of the malignant cells. Furthermore, the malignant T cells in the skin and lymph nodes of patients with cutaneous T-cell lymphoma (mycosis fungoides and the Sézary syndrome) express the Tac antigen (or IL-2Rα). In addition, virtually all (>95%) of the malignant cells of patients with the hairy cell B-cell leukemia express the Tac antigen, and a proportion of other B-cell lymphomas are also Tac-positive. Finally, true histiocytic leukemias and the Reed-Sternberg cell of Hodgkin's disease also manifest the 55-kD Tac peptide. In addition to the expression of the Tac peptide on the surface of the malignant cells, a released soluble 45-kD form of the Tac peptide (referred to herein as "sIL-2Rα") appears in the circulation. Elevated concentrations of this soluble form of the IL-2 receptor are present in the circulation of patients with the Tac-expressing malignancies discussed above.
All of these diseases are treatable with the method of the present invention.

Method for treating malignancy and autoimmune disorders in humans using tac antibodies

The United States of America as represented by the Department of Health and Human Services


System and method for allocating and managing a shared Internet access channel on an Internet access device. The system and method prioritize data flow in a multi-user, limited bandwidth networking environment by differentiating data types for disparate processing thereof by which a plurality of aggregation classes are hierarchically ordered to include at least one favored class (bandwidth guaranteed) and at least one disfavored class (best effort). Network sessions are aggregated into these classes according to an aggregation policy and bandwidth is asymmetrically allocated to the sessions according to a plurality of algorithms operating in conjunction with the hierarchy.

1. Field of the Invention
The present invention relates generally to networking environments in which one or more Network Access Devices compete for limited Network Access Channels; more specifically, it relates to allocating and managing bandwidth, for example, for shared Network Access Channels on a local area network ("LAN").
2. Description of Related Art
Referring now to the drawings, FIG. 1 depicts a simplified networking environment 10 which illustrates in a preferred embodiment of the present invention. More specifically, one or more computers 12, 14, 16, 18, . . . initiate one or more respective network sessions 20, 22, 24, 26, . . . with a communications network such as the Internet 28. Representative network sessions 20, 22, 24, 26, . . . include web browsing sessions, electronic mail ("e-mail") sessions, file transfer protocol ("FTP") sessions, and video streaming ("VS") sessions, among others. Each session involves sending and receiving one or more data packets as part of the network session 20, 22, 24, 26, . . . with one or more other computers (not shown) similarly connected to the networking environment 10.
While the Internet 28 spans the globe, its network of networks connect to one another via electronic pathways that facilitate exchanges of information, files, and other types of data that are transferred through the network sessions 20, 22, 24, 26, . . . . To be "connected" to the Internet 28 means that a computer 12, 14, 16, 18, . . . has access to these electronic pathways. In nearly every networking environment 10, the computers 12, 14, 16, 18, . . . share one or more common Network Access Channels ("NAC") 30 at a shared Network Access Device ("NAD") 32 or other network gateway. Known NACs include, for example, a T-1 or digital subscriber line ("DSL"). Known NADs include, for example, cable modes, wireless devices, and other similar devices.
Data packets flow along the electronic pathways according to various well-known protocols, such as the Transmission Control Protocol ("TCP") and Internet Protocol ("IP"). While the IP functions route the data packets to specified destinations, the TCP functions to break down and reassembles them at respective senders and receivers. Most data transfers over the Internet 28 employ TCP/IP because the Internet 28 is a packet-switched communications network, meaning there are no single, unbroken connections between senders and receivers. Instead, when information is broken down into small data packets for transmission, each individual packet is commonly sent over a different pathway, all at approximately the same time. Because the packets traverse different paths, they commonly arrive out of order. In circuit-switched networks, on the other hand, such as traditional phone lines, a specific part of the network is dedicated in its entirety to a particular sender and receiver as long as a connection therebetween is maintained; in these circuit-switched networks, individual data packets are sent and received sequentially.
A common networking environment 10 can be connected in numerous ways. For example, LANs often join regional networks (e.g., a wide area network ("WAN")) in order to provide better service and maximize efficiencies. A variety of leased lines commonly connect LANs to WANs and WANs to the World Wide Web ("WWW"). These leased lines may include a single telephone line or a complex fiber-optic cable having microwave linking and satellite transmission capabilities. High-speed "backbones" and other high-capacity lines carry enormous amounts of traffic across the network 10, such as the very high-speed backbone network service ("vBNS").
When information is broken into data packets according to the TCP for transmission, the packets commonly travel from a LAN through the many levels of the network 10. Various hardware and software components, including hubs, bridges, gateways, repeaters, and routers, process the packets and ensure their delivery at specified destinations. Hereinafter, such components will be referred to as head-end devices ("HED") 34, although they are not intended to be limited to such. Like NADs 32, HEDs 34 commonly share one or more NACs such as, for example, a DSL Access Multiplexer (DSLAM) or Asynchronous Transfer Mode ("ATM") Data Switch.
It is often difficult for NADs 32, which allocate and manage upstream traffic, to predict or control the download/arrival rate of data packets from the Internet 28. As a result, the NAD 32 is commonly unable to allocate an efficient amount of bandwidth from the total amount of bandwidth available across its NAC 30. This problem arises because WAN links between NADs 32 and HEDs 34 have limited bandwidth. Thus, for upward traffic sent from a LAN to the Internet 28, congestion traffic traditionally occurs at the NAD 32 whenever the bandwidth required for the data packet's transmission exceeds the available WAN link bandwidth.
Similarly, it is often difficult for HEDs 34, which allocate and manage downstream traffic, to predict or control the upload/serving rate of data packets from a LAN. As a result, the HED 34 is commonly unable to allocate an efficient amount of bandwidth from the total amount of bandwidth available across its NAC 36. This problem arises because WAN links between NADs 32 and HEDs 34 have limited bandwidth. Thus, for downward traffic sent from the Internet 28 to a LAN, congestion traffic traditionally occurs at the HED 34 whenever the bandwidth required for the data packet's transmission exceeds the available WAN link bandwidth.
For example, if a network session 20, 22, 24, 26, . . . requires a certain amount of bandwidth for successful transmission, the traditional NAD 32 has no mechanisms with which to control the HED 34 or monitor congestion at the network 10. As a result, overburdened HEDs 34 commonly drop data packets before transmitting them to NADs 32. More specifically, if a specific NAD 32 is configured for a 512 Kb/sec SV transfer at the same time another user downloads one or more large files in a FTP network session, the HED 34 could be forced to compromise both data transmissions to the NAD 32. Even if the NAD 32 confined the FTP session to ensure sufficient local bandwidth for the SV network session, present-day NADs 32 lack the power to effectively control and monitor traffic congestion at the HED 34.
In addition, most NADs 32 and HEDs 34 regard each data packet as equally important regardless of the host that sent the packet or the network session 20, 22, 24, 26, . . . to which the packet belongs. These devices traditionally have only one input queue and only one output queue for both directions. When a data packet comes in, for example, the NAD 32 appends it at the end of its input queue where it waits to be forwarded with other data packets. While this traditional algorithm sufficed when there were only a few best-effort protocols in use, such as FTP and SMTP, it is less sufficient as increased digital content is shared within the networking environment 10 and delivered via the many different multimedia-streaming protocols that are available today. These multimedia-streaming protocols, such as Video Conferencing and Voice-over-IP applications, commonly require consistent downloading rates, delays, and delay jitters. Furthermore, even for best-effort protocols, more and more business users demand differentiation and prioritization between different types of network traffic. For example, on-line transactions may require preferential treatment over regular web-browsing sessions.
As a result of the problems and shortcoming typified by the foregoing, even small outgoing traffic bursts can abuse bandwidth allocations at the NAD 32 and HED 34. Moreover, most traditional NADs 32 and HEDs 34 employ identical algorithms to predict respective download/arrival rates and upload/serving rates.
While numerous efforts have been aimed at solving these problems and shortcomings, most have focused exclusively on Internet-wide solutions, such as Qualify of Service ("QoS"), Differentiated Service ("DiffServ"), different kinds of feedback mechanisms, Admission Control, Resource Reservation, and other scheduling algorithms. Implementation of an Internet-wide solution, however, would require worldwide adoption of the new algorithm or implementation. Even still, such Internet-wide solutions generally fail to differentiate between network sessions that originate from a common host. While several data flows have been prioritized on selective core routers, these solutions still fail to control and allocate the NAC 30.
What is required, then, is a bandwidth management and allocation mechanism that operates on a NAD 32, independently of a HEDs 34. And since NADs 32 and HEDs 34 are usually controlled by different parities, it is also highly desirable to control both the upstream and downstream data flows at a single device. In this way, the bandwidth management and allocation mechanism can be deployed immediately, and it is easier to maintain and upgrade such a mechanism subsequently. Furthermore, business and other entities can decrease independent serviced providers ("ISP") service fees and avoid risking disclosing confidential secerets by implementing bandwidth management solely at their own NAD 32. What is needed therefore, is an accurate system and method for predicting download/arrival rates and upload/serving rates so that bandwidth can be allocated efficiently in limited bandwidth networking environments 10. It is also desirable to reduce or eliminate bursty network traffic and provide prioritized traffic routing according to a port or other number, e.g. a TCP port number. It also remains desirable to allocate available bandwidth among network capable devices based on individualized and customized user requirements.
The foregoing and other objects, advantages, and aspects of the present invention will become apparent from the following description. In the description, reference is made to the accompanying drawings which form a part hereof, and in which there is shown, by way of illustration, a preferred embodiment of the present invention. Such embodiment does not represent the full spirit or scope of the invention, however, and reference must also be made to the claims herein for properly interpreting the spirit and scope of this invention.

System and method for asymmetrical bandwidth management