A method for implementing mobile device-initiated inter-radio access technology (I-RAT) handovers between networks includes a wireless device communicating with a first network using an internet protocol (IP) address that was received from the first network during an initial attachment procedure. The wireless device may initiate an I-RAT handover procedure to connect to a second wireless network using a configuration message that includes a handover attach type. Once the connection with the second network is established, the wireless device may receive the information from the second wireless network using the same IP address. The wireless device may force the wireless device into dormancy and prevent data transfer, and initiate another I-RAT handover procedure to upgrade and connect to the first network, by sending an attach request message that includes a handover attach type.

1. Technical Field
This disclosure relates to wireless communication devices, and more particularly to wireless devices initiating inter-radio access technology handovers.
2. Description of the Related Art
Wireless networks continue to evolve as new communication technologies develop and standardize. Wireless network operators can deploy new communication technologies in parallel with earlier generation communication technologies, and wireless networks can support multiple communication technologies simultaneously to provide smooth transitions through multiple generations of mobile wireless devices. A representative wireless network may include simultaneous support for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) wireless communication standard (which may be referred to as a 4th generation (4G) network) as well as other 3GPP, and 3GPP2 wireless communication standards such as the Enhanced High Rate Packet Data (eHRPD), for example. This representative "simultaneous" wireless network may support circuit switched voice connections through a first wireless network that may use, for example, the CDMA2000 1x wireless communication protocol and packet switched connections (voice or data) through a second wireless network that uses, for example, the LIT wireless communication protocol. The 3GPP wireless communications standards organization develops mobile communication standards that include releases for Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), LTE and LTE Advanced standards. The 3GPP2 wireless communications standards organization develops mobile communication standards that include CDMA2000 1xRTT and 1xEV-DO, and eHRPD standards.
Some mobile wireless, or user equipment (UE) devices may include functionality to seamlessly transition from one radio access technology to another using various cell selection or handover procedures. When that transition is between RATs from different technologies, it is referred to as an Inter-RAT (I-RAT) handover. Conventionally, I-RAT handovers may be initiated by the network or base station to which the UE is communicating. In many cases, the base station may make a determination based upon information and measurements received from the mobile device, and the base station initiates the handover.
However, there may be issues that arise when the UE is transitioned to a given RAT. For example, although a 4G network may be available to the UE, it may not be preferable for reasons such as power consumption, for the UE to transition or upgrade to the 4G network. Similarly, it may not be preferable to stay idly connected in a 4G network, when a suitable 3G network is available.

Mobile device-initiated inter-radio access technology handovers between networks


The present invention relates to subterranean cementing operations, and more particularly to an apparatus useful in loading cementing plugs and darts into tubulars, and methods of using such apparatus in subterranean cementing operations. An example of a method of the present invention is a method of placing a compressible object having a cross-section within a tubular, including the steps of: reducing the cross-section of the compressible object; placing the compressible object with the reduced cross-section in a tubular; and releasing the compressible object within the tubular. Another example of a method of the present invention is a method of reducing the radial cross-section of a compressible object. Other examples of apparatus of the present invention include apparatus for placing a compressible object into a tubular.

The present invention relates to subterranean cementing operations, and more particularly to an apparatus useful in loading cementing plugs and darts into tubulars, and methods of using such apparatus in subterranean cementing operations.
Cementing operations may be conducted in a subterranean formation for many reasons. For instance, after (or, in some cases, during) the drilling of a well bore within a subterranean formation, pipe strings such as casings and liners are often cemented in the well bore. This usually occurs by pumping a cement composition into an annular space between the walls of the well bore and the exterior surface of the pipe string disposed therein. Generally, the cement composition is pumped down into the well bore through the pipe string, and up into the annular space. Prior to the placement of the cement composition into the well bore, the well bore is usually full of fluid, e.g., a drilling or circulation fluid. Oftentimes, an apparatus known as a cementing plug may be employed and placed in the fluid ahead of the cement composition to separate the cement composition from the well fluid as the cement slurry is placed in the well bore, and to wipe fluid from the inner surface of the pipe string while the cementing plug travels through it. An apparatus known as a dart also may be used, inter alia, to facilitate deployment of cementing plugs within the well bore, e.g., by contacting a cementing plug in a manner that separates (e.g., shears) a frangible connection holding the cementing plug in place, thereby freeing the cementing plug to travel along the well bore. Other objects (e.g., a ball) also may be used for these and similar purposes. Once placed in the annular space, the cement composition is permitted to set therein, thereby forming an annular sheath of hardened substantially impermeable cement that substantially supports and positions the pipe string in the well bore and bonds the exterior surface of the pipe string to the walls of the well bore.
Conventional methods of placing a cementing plug or dart in a well bore typically involve loading the cementing plug or dart into a tubular, such as the pipe string or a cementing head, either of which may have a cross-sectional area that is smaller than the maximum cross-sectional area of the cementing plug or dart. Commonly, the cementing plug or dart is forced into the tubular by hand until the cementing plug or dart can no longer be moved by hand. Subsequently, an operator may use, e.g., a sledge hammer and rod to further load the cementing plug or dart into the desired position. This may be problematic because it may create safety concerns for the operator, delay the placement in the well bore of the cementing plug or dart (and, consequently, the cement composition), and damage the cementing plug or dart itself.

Methods and apparatus for use in subterranean cementing operations


In accordance with a specific deposition/etching sequence, a multi-layer metallization system is formed on the non-planar top surface of a semiconductor wafer. In an electrophoretic deposition step, a conformal uniform-thickness layer of a resist material is then formed on the top surface of the metallization system. In turn, the layer of resist material is lithographically patterned to provide an etch-mask for defining features in the underlying metallization system.

This invention relates to the fabrication of semiconductor devices and, more particularly, to a method for patterning the non-planar surface of a semiconductor wafer on which devices are to be made.
For a variety of applications of practical importance, it is necessary that a substrate having a non-planar surface topology be lithographically processed to define patterns on the surface of the wafer. Thus, for example, for making devices for use in an optical communication system, it may be necessary to define patterns on a semiconductor wafer having v-shaped grooves formed in its surface. In particular, patterns may have to be defined simultaneously both in the v-grooves and on adjacent planar portions of the wafer surface.
It is well known that considerable difficulties are associated with utilizing conventionally spun-on resists for patterning non-planar wafer surfaces. In particular, the presence of v-grooves in such a surface presents an overall wafer topology that cannot be uniformly coated with standard spin-on resist technology. In practice, a spun-on resist tends to form a coating along the edges of such grooves that is thin relative to some prescribed nominal coating thickness, while forming a considerably thicker-than-prescribed coating in low-lying areas of the grooves.
The aforedescribed non-uniform distribution of spun-on resist over the surface of a wafer containing v-grooves is clearly undesireable. The inevitable result of such non-uniform distribution is that it is difficult, if not impossible, in a wafer processing sequence to lithographically achieve well-defined and consistent resist patterns simultaneously both in the grooves and on adjacent planar surface portions of the wafer.
Accordingly, considerable efforts have been directed by workers skilled in the art aimed at trying to devise semiconductor device fabrication sequences, including resist-based lithographic steps, suitable for forming small-feature-size patterns on the non-planar surfaces of semiconductor wafers. It was recognized that these efforts, if successful, could improve the yield, lower the cost, and improve the performance and reliability of semiconductor devices whose manufacture on non-planar wafer surfaces has heretofore been considered exceedingly difficult and complicated.

Method of making semiconductor devices by patterning a wafer having a non-planar surface


Provided are personal care compositions comprising a first surfactant comprising sodium lauryl sulfate and a second surfactant having a structure represented by

Sodium lauryl sulfate (SLS) is a very commonly used foaming agent in oral care products, in particular, toothpaste. SLS offers certain properties over other surfactants that make it desirable for the use in oral applications. These properties include high foaming properties, low oral toxicity, and low cost. However, SLS has several disadvantages that can greatly limit its use in oral care applications. These disadvantages include foam suppression by divalent cations such as Ca2+, and the tendency to denature proteins. Protein denaturation is a particular problem that can lead to skin irritation and incompatibility with proteinacious materials. This means that SLS may not be favorably combined with proteinacious additives, which may be desirable, including enzymes and beneficial bacteria.
There have been several attempts to address these problems, including use of alkyl polyglucosides. Alkyl polyglucosides (APGs) are high foaming surfactants employed in a number of personal care applications, including oral care. APGs are very mild to proteinacious surfaces and are known to improve the foaming properties of SLS in the presence of hard water cations. However, APGs have a bitter aftertaste which can limit their use in oral care application.
Therefore, there exists a need to develop surface active materials that can mitigate the effect of SLS on protein without negatively impacting foam. In particular, for oral care applications, there also exists a need for surfactants which solve the above problems but also do not negatively impact taste.

Personal care compositions comprising sulfated poloxamers and methods of making and using same

Abstract: wherein each a has a value of about 1 to about 110, b has a value of about 16 to about 70, and at least one R group is SO3, and the other R group is SO3 or hydrogen. Also provided are methods of producing personal care compositions and methods of ameliorating skin or mucosal membrane irritation due to sodium lauryl sulfate.


A battery charger and method of charging a rechargeable battery which comprises charging the battery with an initial charging current and measuring and comparing the charging temperature to an initial temperature to identify a temperature factor which either identifies a need to lower the current or terminate the charging current. The temperature factor may be a temperature gradient .DELTA.T. The open circuit voltage may be monitored from the beginning or may begin when .DELTA.T is identified. V.sub.OCV is plotted with respect to time t elapsed to identify a point or points on the V.sub.OCV (t) curve, such as an inflection point in the dV.sub.OCV /dt data or a transition point in the d.sup.2 V.sub.OCV /dt.sup.2 which indicate the onset of overcharge. If the open circuit voltage V.sub.OCV of the battery is sampled from the beginning of charging the second order differential information should be ignored until a predetermined temperature gradient is realized. If a point indicating onset of overcharge is not recognized then charging is continued and the steps above are repeated until a point or points indicating onset of overcharge are identified. As a safeguard against overcharge, the inflection point on dV.sub.OCV /dt curve is utilized to indicate onset of overcharge even if the inflection point on the d.sup.2 V.sub.OCV /dt.sup.2 curve is not identified and the negative slope--dV.sub.OCV /dt is utilized to indicate onset of overcharge if the inflection point on the dV.sub.OCV /dt data is not identified.

1. Field of the Invention
The invention relates generally to a battery charger and a method of charging a rechargeable battery, specifically alkaline secondary battery, Ni--Cd (Nickel-Cadmium), Ni--H (Nickel-Hydrogen) and Ni--MeH (Nickel Metal-Hydride) batteries.
2. Description of Related Art
In recent years, a large number of portable electronic devices, i.e. cellular phones, two-way radios, laptop computers and camcorders have become available. Accordingly, it has become necessary to provide a battery that is in a continuous state of operational readiness. In this regard, it is preferable to utilize a rechargeable battery and a method of recharging the battery which avoids both under and overcharging.
The charging of batteries involves forcing electrical current through the battery, usually under some control of the current (e.g. constant current) and often with some voltage control as well (e.g. maximum voltage). While there is some need for controlling the rate of the charging process itself, the most important need for control is when the battery becomes fully charged. After this point, continued charging of the battery leads to undesirable and wasteful overcharge reactions. Overcharge reactions in vented cells result in electrolysis and loss of water that has to be replaced, while in sealed cells it creates pressure and heat since the recombination reactions of gases produced during overcharge are exothermic.
Ideally, the overcharge reactions that require higher voltage can be prevented simply by limiting the charging voltage to a certain value. This simple approach is, unfortunately, only partially successful with certain cell types, e.g. lead acid cells, vented NiCd cells, and sealed lithium ion cells.
Sealed cells capable of recombining the overcharge reaction products are able to tolerate overcharge at low rates because the pressures of by-product gases are low and the heat generation is slow enough for the heat to be easily dissipated and lost. As long as no electrolyte constituent is being lost, it is not critical to terminate charging. However, continuous overcharge even at a low rate reduces the cycle life of the cells.
Rapid charging, i.e. charging in less than one hour, presents much more of a challenge with both vented and sealed cells. The first problem results from the limited rate of charge distribution or equilibration within the electrode plates. Also, at higher charge rates, the overcharge reactions begin to appear at a lower fraction of full charge. When overcharge reactions appear, the current efficiency of the charge reactions decline and most of the columbic energy is wasted on the overcharge reactions. To complete the charging process under these conditions overcharge reactions are tolerated for a sufficiently long time. This process causes damage to the battery. The rapid heating of a battery during high rate overcharge cannot be avoided and may cause safe pressure to be exceeded, as well as cell venting.
U.S. Pat. No. 5,352,967 details some of the known methods of charging storage batteries. The methods disclosed therein focus on various techniques of determining proper charged termination and include: constant current mode; delta temperature/delta time mode (dT/dt); negative delta voltage charge mode (-.DELTA.V); positive delta voltage or delta voltage/delta time mode (dV/dt); pulse charge mode; and reflex mode. In the constant current charge mode, the battery is continuously overcharged with a low current. Although the expenditure for a constant current source is relatively low, the long charging time causes damage to the cell. In the constant charge mode, it is customary to restrict the charging time. Therefore, as soon as a predefined time has elapsed, the charging operation is terminated. Accordingly, since the constant current charge mode does not take into account the charge condition or chemical makeup of the cell under or overcharging of the cell can result.
In delta temperature/delta time charging (dT/dt), the charging current is switched off once a predetermined slope in the temperature versus time curve has been reached. This method can generate false termination signals. The charging process may be terminated prior to the battery being fully charged if preset value of dT/dt is too low, or conversely, if dT/dt is too large, the charging process may be terminated too late.
In the negative delta voltage charge mode, a negative slope in the charge curve (dV/dt<0) which appears after complete charging of the battery is used to terminate charging. The batteries are charged from a constant current source, and the charging voltage rises steadily for as long as the cell is capable of converting the supplied energy into chemical energy. When the batteries are no longer capable of storing the supplied energy, the supplied energy is converted into heat, and the cell voltage drops. The drop in the cell voltage is used as an indicator to terminate charge. However, this method can only be used for those type of batteries permitting high-current charging. The charging method itself suffers from the fact that during the charge operation, surface effects may result in fluctuations in the battery voltage. These fluctuations may be erroneously interpreted as a signal to terminate charge. Therefore, premature break off of the charging operation is often seen when utilizing the negative delta voltage charge mode. Additionally, nickel-metal hydride batteries do not have the pronounced charging voltage curves seen in nicad batteries, and as a result, are often overcharged using the negative delta voltage charge mode.
In the positive delta voltage or delta voltage/delta time mode (dV/dt), the slope of the voltage charging curve is evaluated to determine when to terminate charging of the battery. Theoretically, the rise in the charging voltage decreases when the battery is near full charge. Utilizing the mathematical differential of the charge curve, the reduction in this rise in the charging voltage can be evaluated as the criteria for terminating charging. This method suffers from the fact that the difference in the rise may not be dramatic enough to cause termination of the charging at a proper time with ensuing overcharge of the battery. Additionally, due to fluctuation in the charging curve, this first order derivative charging method may terminate charging prematurely.
Pulse charging utilizes a high current charge followed by an interruption period. The interruption period allows the voltage of the battery to be determined during a currentless phase or under open circuit voltage conditions (OCV) in order to determine the open circuit voltage of the battery (V.sub.OCV). Charging is terminated when V.sub.OCV has reached a preset reference voltage (V.sub.REF). However, as discussed herein, the reference voltage has a degree of uncertainty, and the value often depends on the rate of charge and the battery's design criteria. This method does not take these factors in to consideration when determining termination of charging.
Reflex mode charging also monitors the V.sub.OCV, but follows the charging mode with a discharge period and determines and stores V.sub.MAX. This V.sub.MAX is used as a reference wherein charging is terminated when V.sub.OCV is equal to or greater than V.sub.MAX. Reflex mode charging necessitates discharge of the battery.
Each of the methods discussed above suffer from potential under or overuse charge of the battery or cell. As discussed herein, overcharging a battery is very dangerous. A more accurate determination of charge termination which has been described in the related art in a limited manner is the use of a second order derivative of the charge versus time curve (d.sup.2 V/dt.sup.2) to signal charge termination.
U.S. Pat. No. 5,477,125 proposes a method of recharging a battery which comprises the steps of periodically interrupting the charge current, sampling the resistance free voltage (V.sub.O) after a delay period, and determining point or points on the V.sub.O (t), dV.sub.O /dt and d.sup.2 V.sub.O /dt.sup.2 curve which indicate onset of overcharge to signal charge termination. The current measuring periods are repeated every 10 seconds, and a delay period after current interruption is used to allow the battery to reach an equilibrium.
According to U.S. Pat. No. 5,477,125, after identifying the onset of overcharge, a suitable V.sub.REF is chosen as a function of either one or a weighted average of two or more characteristic points of overcharge. V.sub.REF is chosen for example by increasing V.sub.O by a certain percentage point (minimum on dV.sub.O /dt curve) or by decreasing V.sub.O by a certain percentage (V.sub.O corresponding to either the maximum on d.sup.2 V.sub.O /dt.sup.2 curve). An educated guess as to the percentage of V.sub.REF (i.e. 98% of V.sub.O corresponding to maximum on d.sup.2 V.sub.O /dt curve or 95% of V.sub.O corresponding to maximum on dV.sub.O /dt curve) is used as the termination point. This guesswork can result in accidental overcharging or under charging of the battery and ultimately leads to poorer performance and cell cycle life of the battery. U.S. Pat. No. 5,477,125 states that the V.sub.REF is independent of rate of charge. However, the present disclosure indicates that this appears to be an overbroad or erroneous statement. Establishing V.sub.REF independent of the rate of charge will cause V.sub.REF to have a large degree of error. The type of crystal that forms on the nickel oxide electrode is sensitive to the rate of charge being applied to the battery. A high rate of charge results in .gamma.-NiOOH while a low rate of charge results in .beta.-NiOOH crystal formation. The difference between these two is 30-40 mv under open circuit voltage conditions. Additionally, the interval after charge interruption at which the voltage of the battery is measured is important due to the fact that the open circuit voltage is unsteady for some time after charge interruption. The fluctuation at different time intervals depends on the rate of charge, the battery design and charging temperature. The rate of charge, for example, may increase the potential of the nickel-oxide electrode by 60-80 mv due to the appearance of high valence NiO.sub.2 at the end of charge. Considering only those factors enumerated above, an error in determining V.sub.REF on the order of at least 90-120 mV can be made if V.sub.REF is determined independent of the rate of charge.

Battery charger and method of charging batteries


A microscopy method is for producing an electronic image of an object, wherein the object is imaged with an adjustable optical imaging scale on an image detector. The method includes: selecting a parameter for the electronic image, wherein the parameter can be influenced by the optical imaging scale and differs from the image field dimensions, and setting a setpoint value range for the parameter, setting a total imaging scale for the electronic image, wherein adjusting or controlling the parameter of the electronic image is implemented such that, at the same time, the parameter of the electronic image lies in the specified setpoint value range with a tolerance and the set total imaging scale is obtained, wherein the optical imaging scale forms a basis for a manipulated variable of the adjustment or closed-loop control and a digital image magnification is carried out on the basis of the set total imaging scale.

Surgical microscopes are known from US 2008/0266657 A1 or US 2005/0063047 A1. Further, digital surgical microscopes which include a digital magnification (often called zoom) combined with optical image magnification are known, by way of example, from US 2006/0092505 A1, US 2012/0002274 A1, U.S. Pat. No. 10,139,613 B2 or US 2008/0198448 A1.
In microscopes which generate electronic images at adjustable optical magnification, usually the maximum optical magnification is utilized and additional zooming is performed with the aid of a digital magnification. The total magnification is the product of the optical magnification scale multiplied by the digital zoom factor. However, all image information is contained in the optical image and digital magnification does not provide additional image information. In particular, no increased light sensitivity is achieved by digital zooming.
US 2019/0339506 A1 discloses a digital surgical microscope which is adjusted such that no details for which image information would be available but which cannot be recognized due to his eyesight and due to the distance at which he is standing are displayed on a display device.

Microscopy method and microscope for producing an image of an object


The purpose of the present invention is to provide an image processing apparatus and a computer program such that correspondence points between design data and an edge line or between edge lines can be accurately identified for their matching. In an embodiment for achieving the purpose, when positioning between a first pattern formed by a first line segment and a second pattern formed by a second line segment is performed, a first correspondence point and a second correspondence point are set on the first line segment and the second line segment, respectively; a degree of alignment for performing the positioning of the first pattern and the second pattern is calculated on the basis of the distance between the first correspondence point and the second correspondence point; and the position of the first correspondence point and/or the second correspondence point is changed in accordance with a shape difference between the first line segment and the second line segment (see FIG. 2).

With the recent progress in miniaturization technology for semiconductor device manufacturing, the patterns formed on a semiconductor wafer have been miniaturized, and increasingly higher accuracy is required for apparatuses that evaluate the miniaturized patterns. Particularly, the advance in OPC (Optical Proximity Correction) technology has created increasing demand for evaluating the two-dimensional shape of a pattern. In order to accurately measure or inspect a fine pattern, a charged particle beam apparatus represented by the scanning electron microscope (SEM) is used. In an image acquired by a SEM and the like, a pattern edge portion is represented with a certain width. As a method for accurately ascertaining the edge shape of a pattern, an edge line determination technology is known. Patent Literatures 1 and 2 disclose methods for performing pattern matching between an edge line and design data so as to accurately measure a shape difference between design data and edge line.

Image processing device and computer program


Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, in which active and inactive regions are separated by a field oxidation film; source/drain junctions contacting the field oxidation film and formed in the active regions of the semiconductor substrates; a buffer oxidation film formed at designated portions of the source/drain junctions, and a gate electrode formed on the semiconductor substrate adjacent to the buffer oxidation film; and a silicide film formed at designated portions of the source/drain junctions and the upper surface of the gate electrode.

1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a salicide process in which silicide is formed simultaneously on a gate and source/drain regions.
2. Description of the Related Art
In a conventional method for manufacturing a semiconductor device having a size of less than 1.2 μm, silicide is formed on a polysilicon substrate using tungsten, and is used as a gate electrode of a metal oxide semiconductor field effect transistor (MOSFET). However, as semiconductor devices become increasingly high-integrated to have a size less then 0.35 μm, various methods for forming electrodes using titanium in MOS transistors are widely used.
FIGS. 1A to 1D are sectional views illustrating a conventional method for manufacturing a semiconductor device.
As shown in FIG. 1A, a field oxidation film 110 for insulating unit complementary metal oxide semiconductor field effect transistors (CMOSFETs) from each other is formed on a silicon substrate 100.
Thereafter, as shown in FIG. 1B, a gate oxidation film 140 for forming a gate is grown on the silicon substrate 100. Then, a polysilicon gate is formed by stacking a polysilicon film 150 doped with impurities serving as an electrode of the gate on the gate oxidation film 140 and forming a pattern using a mask.
As shown in FIG. 1C, source/drain junctions 170 are formed by injecting impurities two to four times into regions used as source and drains of a transistor using a spacer oxidation films 160 interposed between.
Thereafter, a blank oxidation film 180 is formed on the field oxidation film 110, and is removed from places other than regions, in which silicide is not formed, by etching.
Then, a silicide film 190 is formed by a salicide process.
In the conventional method for forming silicide using the conventional technique, since a process margin does not exist when the etching of the spacer oxidation film or the blank oxidation film is performed during the formation of the source and drains, the silicide film is formed or remains through the side wall of the transistor even by a small error in the process, thereby generating short between a gate and the drains or between the gate and the source, or increasing parasitic capacitor, thus exerting a negative influence upon yield and characteristics of products.
Accordingly, a method for manufacturing a semiconductor device, in which a process margin for etching is assured to solve various problems generated from the formation of silicide, has been increasingly required.

Semiconductor device manufacturing method


A lens apparatus includes an imaging optical system including a movable lens unit, a drive unit configured to drive the movable lens unit, and a control unit configured to cause the movable lens unit to perform a wobbling motion in an optical axis direction by alternatively outputting to the drive unit a first drive command for driving the movable lens unit at a first driving speed and a stop command for stopping driving of the movable lens unit, and to move the movable lens unit based on contrast information obtained from an image pickup unit during the wobbling motion of the movable lens unit, wherein, at least one of before and after outputting the first drive command to the drive unit, the control unit outputs to the drive unit a second drive command for driving the movable lens unit at a second driving speed lower than the first driving speed.

1. Field of the Invention
The present invention relates to a lens apparatus that performs a wobbling motion of a focus lens in order to determine a driving direction of the focus lens in which an object image comes closer to an in-focus state, and also relates to an imaging apparatus including the same.
2. Description of the Related Art
In a conventional still image capturing imaging apparatus or a conventional moving image capturing imaging apparatus, in order to determine a driving direction of a focus lens in which an object image formed by an imaging optical system comes to be in focus, the focus lens is minutely moved back and forth (i.e., a wobbling motion) in an optical axis direction of the imaging optical system.
For example, as discussed in Japanese Patent Application Laid-Open No. 2010-63162, the wobbling motion of a focus lens is performed in a plurality of follow-up modes independent from a frequency of an exposure synchronization while taking the exposure synchronization between a camera apparatus and a lens apparatus. Discussed therein is that the focus lens can be controlled at an appropriate frequency for the wobbling motion of the focus lens.
However, in the conventional art discussed in the above-described Japanese Patent Application Laid-Open No. 2010-63162, each follow-up mode has only one driving frequency (i.e., driving speed) during the wobbling motion. Further, as a mechanism design for causing the focus lens to operate in an optical axis direction, it is difficult to eliminate a back-lash of a connection unit in view of operation guarantee and part accuracy under various temperatures. As a result thereof, a mechanical collision noise cannot be prevented from being generated during the wobbling motion.
Therefore, in a case where the driving frequency is increased in order to improve controllability, the mechanical collision noise increases and thus such an inconvenience occurs that the noise tends to be recorded by a camera microphone as an operation noise of the focus lens. In the wobbling motion, an automatic focus operation is realized by causing the focus lens to move back and forth in an optical axis direction at a minute drive amplitude value to the extent that humans cannot visually confirm it in an captured moving image and a through-image.
The mechanical collision noise generated during the wobbling motion is a periodic sound generated in a short period such as an imaging period (i.e., a frame rate), so that the noise tends to be recognized as a grating sound in an audibility of human. Therefore, when capturing a moving image, recording of the mechanical collision noise generated during the wobbling motion is recognized as an unpleasant sound for a viewer of the moving image, resulting in inviting degradation of video quality (including sound).
A conventional camera has a through-image display function for causing a liquid crystal display provided on the rear surface of a camera body to display an image captured by an image sensor. The through-image is an image which is not to be recorded on a recording medium, such as a memory card, after the image capturing. An operator visually confirms the through-image, thereby being able to determine the composition of an object when capturing a still image thereof.
The mechanical collision noise generated during the wobbling motion does not involve a change of the captured moving image or through-image, so that the noise tends to be recognized as the grating sound in the audibility of human. Therefore, when capturing a moving image, recording of the mechanical collision noise during the wobbling motion and generation of the mechanical collision noise when capturing a still image or a moving mage are recognized as the unpleasant sound for the operator and a viewer of the moving image, resulting in inviting the degradation of the video quality (including sound).

Lens apparatus and imaging apparatus including the same


A device in fluid-conducting unit for use in a supply line for carrying fluid with pressure from a source of the fluid to a tool comprises a coupling member having first and second open ends and a fluid passageway extending between the open ends. The fluid passageway has inner walls defining first and second sections with the second section having a larger diameter than the first section. A sloped surface connects the walls of the first section with the walls of the second section and a convergingly-shaped hub body is mounted within the second section for longitudinal movement therein between a first position of the hub body at the second end for providing a large fluid exhaust area and a second position at the first end for providing a reduced exhaust area, the convergingly shaped hub body being provided with a first end adjacent to engage the sloped surface and a plurality of spaced-apart wings projecting from the hub body to the inner walls of the second section, the wings interacting with the sloped surface at their front edges and having a longitudinally extending elongate outer surface for engaging the inner wall of the second section.

Quick couplings with displaceable inner parts are already well known. However, the present unit is to be used in connection with a pressure source, preferably for air, with the aid of which tools, elements and the like, are to be operated. The unit supplies the medium in question, conducted via a hose from the unit to the tool in question or the like. The unit can also include a nozzle, for example a nozzle for air blasting. The nozzle can be connected to a suitable pressure source via a hose or another line.


A mandrel used to cure a composite part layup has an elastic body and at least one internal open space therein. The internal open space is configured to allow substantially uniform thermal expansion of the body during curing.

When composite materials are molded into structures having cavities, such as hat stringers, for example and without limitation, there may be a need for tooling that applies outward pressure from within the cavity during curing, and which can be removed from the cavity after curing. Existing tooling used for this purpose may include, without limitation, inflatable rubber mandrels; solid mandrels such as metal, rubber or composite mandrels; or dissolvable mandrels. Solid rubber or composite mandrel are sometimes preferred for certain applications, however when subjected to heat and pressure, this type of mandrel may produce a cavity having a distorted cross-sectional shape and/or may exert uneven pressure on the composite laminate.
Accordingly, there is a need for a removable mandrel that reduces or eliminates distortion of the cavity shape, and exerts substantially uniform pressure over the composite laminate during curing at elevated temperatures.

Mandrel for autoclave curing applications


Embodiments directed to an apparatus and system of monitoring an instrument with a working tool engaged thereby. In one aspect, an embodiment including a working tool with a machine readable indicium indicative of a working tool attribute. The working tool may be receivable by an instrument such that a corresponding machine readable indicia reader receives an identifier of the working tool. Various attributes and conditions in relation to the instrument and working tool received thereby may be identified to facilitate the provisioning of a response to prompt various corrective actions. In this regard, a controller may provide an output in response to a received identifier of a working tool and an identified instrument operating condition.

Various powered surgical instruments (e.g., drills, saws, grinders, etc.) may be associable with a plurality of corresponding working tools (e.g., drills bits, saw blades, grinding burrs, etc.) to facilitate certain operations using the powered surgical instruments. For example, a handheld drill may engage any one of a plurality of drill bits in order to bore a hole through a medium of interest such as an anatomical structure of a patient. Further, in such settings, each of the plurality of working tools may embody certain attributes including but not limited to a certain size, serial number, material composition, manufacturer, temperature tolerance, and the like. For example, a first respective drill bit may constitute a first bore diameter and a first material made by a first manufacturer, while a second respective drill bit may constitute a second bore diameter and a second material made by a second manufacturer. In this regard, the operation of the instrument including the functionality, specifications, and limitations related thereto may be at least partially based on the particular respective working tool engaged by the powered surgical instrument. That is, the specific attributes of the engaged working tool may at least partially inform or otherwise impact the functionality of the instrument, for example, by defining the operational limitations of the instrument in relation to the engaged working tool. In this regard, the first respective drill bit with the first bore diameter and first material may limit the rotational speed, for example, at which the instrument may be used to bore a hole, etc.
Further, some electro-mechanical instruments may include one or more sensors integrated therein to measure various conditions of the instrument and/or of the operational environment thereof such as the density of a medium through which a working tool is advanced during use. In this regard, in such circumstances, the values measured by the one or more sensors of the instrument and any outputs related thereto may be at least partially based on the particular engaged working tool and its associated attributes. As such, with regards to the foregoing, it may be desirable to identify the particular engaged working tool and the attributes related thereto.

Drill bit data management for penetration-monitoring drill


An acceleration sensor includes a housing member, a spring member attached to the housing member, a magnetic field generation member fixed to the housing member, and at least one magnetic field detection sensor and a weight member, fixed to the spring member so that the at least one magnetic field detection sensor faces the magnetic field generation member. The spring member has freedom in at least one direction of acceleration to be detected. The at least one magnetic field detection sensor is provided with at least one multi-layered MR element including a magnetization fixed layer and a magnetization free layer. A magnetic field is applied to the at least one multi-layered MR element from the magnetic field generation member in a direction substantially perpendicular to a lamination plane of the at least one multi-layered MR element when no acceleration is applied. When an acceleration is applied, the magnetic field is applied to the at least one multi-layered MR element from the magnetic field generation member in a direction changed by an angle corresponding to the applied acceleration from the substantially perpendicular direction.

1. Field of the Invention
The present invention relates to an acceleration sensor with at least one magnetoresistive effect (MR) element and to a magnetic disk drive apparatus with the acceleration sensor.
2. Description of the Related Art
In a magnetic disk drive apparatus or a hard disk drive (HDD) apparatus assembled in a mobile equipment such as for example a walkabout personal computer, a mobile phone, a digital audio player and other mobile gear, an HDD apparatus used as a mobile storage itself or a removable HDD apparatus, in order to prevent a collision of a magnetic head with a hard disk surface due to drop impact, it is necessary to detect the instant at which the HDD apparatus falls before occurrence of the drop impact and to retract the magnetic head from the hard disk surface. Such instant of the falling can be detected from a slight change in the acceleration of gravity.
U.S. Pat. No. 6,131,457 (Japanese patent publication No. 11-352134A) discloses an acceleration sensor for detecting a small change in the acceleration of gravity. This acceleration sensor has a magnetic body including a mass point on an axis along a Z-axis, mounted to a vibrator having three-dimensional freedom, and four or more magnetoresistive effect (MR) detector elements positioned on an X-axis and a Y-axis with their centers located along a perimeter of a concentric circle around the origin point of the orthogonal coordinate axes. The sensor is thus capable of detecting each of acceleration in the direction of X-axis through a relative difference in output voltage between the two detector elements on the X-axis due to a vibration of the magnetic field, acceleration in the direction of Y-axis through a relative difference in output voltage between the two detector elements on the Y-axis due to a vibration of the magnetic field, and acceleration in the direction of the Z-axis through a sum total of the output voltages of all the detector elements.
However, because this known acceleration sensor disclosed in U.S. patent No. 6,131,457 has a structure with the permanent magnet mounted on the vibrator having three-dimensional freedom, this permanent magnet may be moved due to a force produced by an externally applied magnetic field. This movement of the permanent magnet will induce noises or detection errors of acceleration when precise detection of acceleration is performed. Such influence of the externally applied magnetic field will increase in case the acceleration sensor is downsized and thus the size of the permanent magnet decreases.
Also, because the known acceleration sensor uses an anisotropic MR (AMR) element with a single layer structure for each magnetic field detector element causing lower sensitivity of the magnetic field, it is difficult to detect acceleration with high sensitivity.

This patent is subject to a terminal disclaimer.

Acceleration sensor and magnetic disk drive apparatus


A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.

Over the last few decades, the capability of digital systems has dramatically increased, also with a significant reduction in size, weight, power, and cost (SWAP-C). Digital systems and signals differ from their analog counterparts primarily because they are quantized (discrete in value) and sampled (discrete in time). Analog-to-digital converters (ADCs) sample and quantize an analog signal to create a digital signal, a process known as digitization. Conversely, digital-to-analog converters (DACs) generate analog signals from digital signals. ADCs and DACs are often at the boundary of a digital system, determining much of the system's performance in its interaction with the environment.
Both ADCs and DACs are governed by the Nyquist Sampling Criterion, which specifies the bandwidth of a digital signal to be no greater than the Nyquist bandwidth, which is half the sampling rate for a real signal with uniform sampling. If the Nyquist Criterion is satisfied, an analog signal can be digitized and then perfectly reconstructed using the digital samples. If the Nyquist criterion is violated, irreversible corruption may occur due to aliasing. In practice, signal bandwidths are typically noticeably less than the Nyquist bandwidth.
For an ADC to satisfy the Nyquist Sampling Criterion, the analog signal must be filtered to a bandwidth less than the Nyquist bandwidth of the converter before digitization. For a DAC, analog filtering is generally performed to reduce spectral artifacts outside the Nyquist bandwidth of the represented signal. Examples of ADC applications include the receive path of digital coherent radar, communications, networking, electronic warfare, and control circuitry. DACs might be used on the transmit side for each of those applications.
Nyquist-rate ADCs and DACs are a class of converters whose converted signal typically has a bandwidth comparable to the Nyquist bandwidth. These converters generally have more bits and therefore more levels of quantization compared to alternative classes of converters.
Delta-sigma converters are in a separate class of converters. In contrast to Nyquist-rate converters, delta-sigma converters are oversampled converters, meaning their Nyquist bandwidth is much greater than the signal bandwidth. The specific ratio at which a delta-sigma DAC samples compared to the Nyquist rate is specified as the converter's oversampling ratio (OSR).
Specific instances of delta-sigma converters may have comparable performance to Nyquist-sampled converters, with reduced size, weight, power, and/or cost. In some instances, Delta-sigma converters are implemented as part of a digital integrated circuit (IC) or field-programmable gate array (FPGA), eliminating the need for an external converter chip and thereby reducing circuit complexity, cost, power consumption, and latency. Delta-sigma converters typically are highly quantized (fewer bits), but can retain the signal quality over the signal bandwidth through oversampling and spectral shaping of the quantization noise away from the signal. This shaping occurs through a feedback loop. The quantization error of previous samples are used to adjust the value of subsequent pre-quantization samples. Higher OSRs improve the noise shaping (OSR is often more than 10). Delta-sigma ADCs differ fundamentally from delta-sigma DACs in that the delta-sigma ADC's feedback loop is mixed signal (analog and digital), whereas the delta-sigma DAC feedback is purely digital.
Typically, a delta-sigma DAC comprises an input, a quantizer, an output, and a feedback path. The feedback path uses the difference (a.k.a. residue or error) between the pre-quantized signal and its quantized approximation. The specific feedback logic determines the characteristics of the noise shaping. Note that the quantized approximation may be represented in the output signal as binary (e.g. a binary 1 or binary 0 for a 1-bit output), the representation of which is scaled (e.g. multiplied by some gain) and offset (e.g. to a set 0-mean) before differencing.
Output sample rate directly impacts delta-sigma DAC performance; increasing the output sample rate increases either the operational signal bandwidth or the output's dynamic range. An increase in output sample rate with a constant signal bandwidth increases the OSR and thereby the SNR. An increase in output sample rate with constant OSR increases the operable bandwidth. The theoretical dynamic range performance of the first-order delta-sigma DAC is limited by the signal-to-noise ratio (SNR, in dB):SNR<9.03 log2(OSR)−12.12  (1)
The spectral shaping of delta-sigma DACs produces a frequency band around which the output signal exhibits the highest dynamic range. The location of this band depends on the configuration and structure of the delta-sigma modulator and the output sample rate. For a low-pass delta-sigma DAC the output band is centered around 0 Hertz. For a band-pass delta-sigma DAC, the output band is centered around some frequency relative to the output sampling rate.
Delta-sigma DACs are typically modeled and implemented recursively, A system or processes is recursive when the current state is determined using a previous state.
FIG. 1 is a simplified block diagram of a conventional fully recursive 1-bit low-pass delta-sigma DAC 100, As shown, a multi-bit oversampled signal 102 is input to the delta-sigma DAC 100. The input signal 102 is combined with a residue (error) signal 122 by an addition circuit 104 to produce an error-compensated signal 105. Signal 105 is quantized to 1 bit using a compare-to-zero comparator 106 to generate a modulated output signal 108, Signal 108 is then output from the delta-sigma DAC 100. Signal 108 is also fed back to a switch 116, The switch 116 interprets the encoding of the output signal 108 to the appropriate scale and offset relative to the error-compensated signal 105, Switch 116 takes a gain of the DSM (g) as its input and outputs the value of g 112 (same as its input) when signal 108 has a value of "1," and a value of negative g when signal 108 has a value of "0", The output of the switch 116 is combined with the error-compensated signal 105 by a subtraction circuit 118 to produce a 0-delay residue 119, The residue 122 is delayed by one clock cycle relative to the 0-delay residue 119 by a delay block 120.
The low-pass delta-sigma modulator in FIG. 1 can be modeled mathematically as
                              y                                [            n            ]                          =                                            x              int                                                  [              n              ]                                +                      ɛ                                      [                              n                -                1                            ]                                                          (        2        )                                                      x            b                                          [            n            ]                          =                  {                                                                      1                  ,                                                                                y                                                              [                      n                      ]                                                        >                  0                                                                                0                  ,                                                            otherwise                                                                        (        3        )                                                                                ɛ                                      [              n              ]                                =                                    y                                            [                n                ]                                      +                          {                                                                                -                        g                                            ,                                                                                y                                                                          [                          n                          ]                                                                    >                      0                                                                                g                      ,                                                                            otherwise                                                                                (                  4                    a                )                                                                            =                                    y                                            [                n                ]                                      +                          {                                                                                -                        g                                            ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      1                                                                                g                      ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      0                                                                                (                  4                    b                )                                                                            =                                    y                                            [                n                ]                                      +            g            +                          {                                                                                -                          2                                                                        g                                            ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      1                                                                                0                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      0                                                                                (                  4                    c                )                                                                            =                                    y                                            [                n                ]                                      +            g            -                          2                                                              gx                  b                                                                  [                  n                  ]                                                                                (                  4                    d                )            where
nis time indexxint [n]is oversampled signal102y [n]is error-compensated signal105xb [n]is output signal108ε [n]is 0-delay residue119ε [n −1]is residue122gis value for feedback gain112
This conventional delta-sigma DAC 100 is fully recursive since each signal (excluding the input signal 102) is expressed in terms that are dependent on some value of a previous clock cycle.
A recursive implementation's output data rate is limited to the rate at which the (loop) computation can be completed. In other words, a fully-recursive delta-sigma DAC has a maximum output data rate equal to the logic clock. This, in turn, limits the delta-sigma DAC's performance. Prior art approaches attempt to parallelize and pipeline the delta-sigma DAC to achieve higher performance, but all introduce non-idealities which produce spectral artifacts or other degradation in the quality of the output signal.
A higher delta-sigma DAC output rate may be achieved while preserving signal quality by pre-computing the output waveform. The computation is performed at slower rate than the rate of the output transmission. The a-priori waveform is stored in memory, and recalled when transmission is desired, potentially at a much higher rate than the logic which generated it. The use of this approach is greatly limited and impractical for many applications, because it assumes a priori knowledge of the desired waveform. Accordingly, there is a need for a high-performance real-time delta-sigma DAC which overcomes these limitations. Existing fully-recursive band-pass delta-sigma DACs have the same limitation described for low-pass delta-sigma DACs.
FIG. 2 is a simplified block diagram of a typical fully recursive generalized 1-bit second-order delta-sigma DAC 200, As shown, a multi-bit oversampled signal 202 is input to the delta-sigma DAC 200. The input signal 202 is combined with a first compensation signal 238 by an addition circuit 204 to produce first compensated signal 206. Signal 206 is combined with a second compensation signal 230 by an addition circuit 208 to produce a second compensated signal 210. The signal 210 is quantized to 1 bit using a compare-to-zero comparator 212 to generate a modulated output signal 214. Signal 214 is then output from the delta-sigma DAC 200. Signal 214 is also fed back to a switch 220. The switch 220 interprets the encoding of the output signal 214 to the appropriate scale and offset relative to the error-compensated signal 210. For the 1-bit low-pass DSM shown, switch 220 takes a gain of the DSM (g) as its input and outputs the value of g 216 (same as its input) when signal 214 has a value of "1" and a value of negative g when signal 214 has a value of "0", The output of the switch 330 is combined with the second error-compensated signal 210 by a subtraction circuit 220 to produce a 0-delay residue 223. The residue 223 is delayed by one clock cycle relative to the 0-delay residue 223 by a delay block 224 to produce a 1-delay residue 226. The 1-delay residue 226 is multiplied by a first constant multiplier 228 to produce the second compensation signal 230. The 1-delay residue 226 is also delayed by one clock cycle relative to the 1-delay residue 226 by delay block 232 to produce a 2-delay residue 234. The 2-delay residue 234 is multiplied by a second constant multiplier 236 to produce the first compensation signal 238. The output noise shaping depends on the values of the constant multipliers 228 and 236. For example, if the first multiplier 228 uses a value of 1 and the second constant multiplier 236 uses a value of 0, the model is equivalent to the low-pass delta sigma DAC of FIG. 1.
The delta-sigma modulator in FIG. 2 can be modeled mathematically as
                                                                            y                                      [              n              ]                                =                                                    x                int                                                          [                n                ]                                      +                                          a                1                                                          ɛ                                                  [                                      n                    -                    1                                    ]                                                      +                                          a                2                                                          ɛ                                                  [                                      n                    -                    2                                    ]                                                                                (        5        )                                                      x            b                                          [            n            ]                          =                  {                                                                      1                  ,                                                                                y                                                              [                      n                      ]                                                        >                  0                                                                                0                  ,                                                            otherwise                                                                        (        6        )                                                                                ɛ                                      [              n              ]                                =                                    y                                            [                n                ]                                      +                          {                                                                                -                        g                                            ,                                                                                y                                                                          [                          n                          ]                                                                    >                      0                                                                                g                      ,                                                                            otherwise                                                                                (                  7                    a                )                                                                            =                                    y                                            [                n                ]                                      +                          {                                                                                -                        g                                            ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      1                                                                                g                      ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      0                                                                                (                  7                    b                )                                                                            =                                    y                                            [                n                ]                                      +            g            +                          {                                                                                -                          2                                                                        g                                            ,                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      1                                                                                0                                                                                x                          b                                                                                [                          n                          ]                                                                    =                      0                                                                                (                  7                    c                )                                                                            =                                    y                                            [                n                ]                                      +            g            -                          2                                                              gx                  b                                                                  [                  n                  ]                                                                                (                  7                    d                )
where
nis time indexxint [n]is oversampled signal202y [n]is 2nd compensated signal210xb [n]is output signal214ε [n]is 0-delay residue223ε [n −1]is 1-delay residue226ε [n −2]is 2-delay residue234gis value for feedback gain216
The output sampling rate and the values a1 and a2 used for multipliers 228 and 236, respectively, are typically static. However, a fully-recursive delta-sigma DAC experiences the associated limitations discussed earlier, whether dynamic or static multiplier values and output sampling rate are used.

Digital delta-sigma modulator with dynamically adjustable output frequency band


A display method and apparatus for a navigation system which is capable of easily and quickly specifying a destination in the navigation system when using a “Point of Interest (POI)” method by preventing unwanted POI names or types from appearing on the navigation system. The method includes the steps of displaying a POI name list based on an instruction specified by a user, selecting an unwanted POI name in the POI name list, removing all POIs having the unwanted POI name or having the unwanted POI type from the POI name list, and selecting a destination in the POI name list from which the unwanted POI name is removed for route guidance by the navigation system. If necessary, the above steps of selecting the unwanted POI name and removing the unwanted POI names from the POI name list are repeated.

A navigation system performs travel guidance for enabling a user to easily and quickly reach the selected destination. A typical example is a vehicle navigation system where a user drives a car having a vehicle navigation system. Such a navigation system detects the position of the user or user's vehicle, reads out map data pertaining to an area at the current vehicle position from a data storage medium, for example, a CD-ROM (compact disc read-only memory), a DVD (digital versatile disc), or a hard disc. Alternatively, such map data can be provided to the user from a remote server through a communication network such as Internet. The navigation system displays a map image on a monitor screen while superimposing a mark representing the current location of the user on the map image.
When a destination is set, the navigation system starts a route guidance function for setting a guided route from the start point to the destination. To determine the guided route to the destination, the navigation system calculates and determines an optimum route to the destination based on various parameters. For example, the guided route is determined based on the shortest way to reach the destination, the route preferring freeways to surface roads, the least expensive way to the destination, or the route without using toll road, and the like.
During the route guidance, the navigation system reads the nodes data from the data storage medium such as DVD and successively stores the nodes data of road segments (expressed in longitude and latitude) constituting the guided route in a memory. In the actual traveling, the node series stored in the memory is searched for a portion of the guided route to be displayed in a map display area of the monitor screen, and the portion of the guided route is highlighted so as to be discriminable from other routes. When the vehicle is within a predetermined distance of an intersection it is approaching, an intersection guidance diagram (an enlarged or highlighted intersection diagram with an arrow indicating the direction in which the vehicle is to turn at the intersection) is displayed to inform a user of the desired one of roads or directions selectable at the intersection. Such route guidance by the navigation system is also given by voice instruction.
FIGS. 1A-1H show an example of overall procedure and screen display involved in the navigation system. FIG. 1A shows an example of locator map screen of the navigation system when the destination is not specified. Typically, the navigation system displays a street on which the vehicle (current vehicle position VP) is running on a map image and a name of the street. Other information such as a north pointer NP, a map scale and a current time may also be illustrated on the display screen. However, in this situation, the navigation system does not perform the route guidance function because the destination is not specified.
FIGS. 1B-1D show an example of process for specifying a destination in the navigation system. A main menu screen such as shown in FIG. 1B displays menu items including a "Destination" menu for entering the destination. When selecting "Destination", the navigation system displays an "Find Destination by" screen as shown in FIG. 1C for specifying an input method for selecting the destination. The "Find Destination By" screen lists various methods for selecting the destination including "Address" for specifying the city and address of the destination, "Intersection" for specifying the names of two streets which intersect with one another, and "Point of Interest" (POI) for selecting the programmed destination based on the name, category or telephone number. Other methods in the "Find Destination by" screen include "Recent Route" for specifying the destination based on the recent history of destinations saved in the navigation system, and "Address Book" for selecting the address of the destination out of the prescribed address list stored in the system.
When selecting, for example, the "Point of Interest" method in FIG. 1C, the navigation system displays selection methods of point of interest (POI) either by "Place Name" or "Place Type" in FIG. 1D. The "Place Name" is to specify a name of POI, and the "Place Type" is to specify a category of POI. If the "Place Name" is selected in FIG. 1D, the navigation system shows an "Enter Place Name" screen such as shown in FIG. 1E. The screen of FIG. 1E is basically a keyboard for inputting the name in an input box on the monitor screen. The user inputs the name of the desired POI in the input box through the keyboard.
FIG. 1F shows a "Confirm Route" screen of the navigation system for confirming the destination. In this example, the "Confirm Route" screen lists the name, address and phone number of the destination (i.e., the POI specified by the user). If this is the correct destination, the user enters an "OK to Proceed" key to proceed to the next procedure.
In FIG. 1G, the navigation system calculates and determines a guided route to the destination, i.e., the selected POI. The navigation system determines a route to the destination based on, for example, the shortest way to reach the destination, the route using as much freeway as practical or the route without using toll road, and the like. In this example, the navigation system displays a progress scale of the calculation of the route.
After determining the guided route, the navigation system starts the route guidance as shown in FIG. 1H. Typically, the navigation system shows the intersection which is highlighted to show the next turn and a direction of the turn. Such route guidance by the navigation system is also given by voice instruction.
In the process of specifying the destination by the "Point of Interest (POI)" method described above, because the recent storage medium provides a large volume of data involved in this input method, it requires relatively many steps until finally selecting the destination. Further, when there are a large number of POIs in a relatively small area, too many POIs will be displayed, which makes it difficult for the user to find the desired one.
For example, when finding a POI through a category such as "restaurant" in a downtown area, many POI names will appear on the navigation display, requiring the user to scroll many pages of the screen and to see many POI names. In another example, when the user does not know the exact name of the POI, thus, only a portion of the name is input through the keyboard, the navigation system will detect a large number of POIs including the portion of that name. Thus, it takes a long time to find a correct POI name by scrolling many pages of the list, which may adversely affect the safe driving. Therefore, there is a need for a navigation system which can easily and quickly specify the destination through the "Point of Interest" method.

Display method and apparatus for navigation system


This invention provides a novel acid DNase (DLAD) which is an endonuclease capable of cleaving DNA independently from divalent cations, under acidic conditions, which retains its activity in acidic to even neutral pH range, and which is not inhibited by G-actin. This invention also provides a DNA encoding the enzyme, an expression vector containing the DNA, and a host cell transformed with the expression vector. Furthermore, a pharmaceutical composition containing DLAD, DLAD expression vector or a host cell transformed with the expression vector as an active ingredient is provided. The pharmaceutical composition is useful as a therapeutic agent replacing DNase I for cystic fibrosis, and can provide a new approach for the prophylaxis and treatment of infectious diseases.

The presence of various deoxyribonucleases (hereinafter referred to as DNase) in mammalian cells has been known. DNase II is one of the DNases studied most and catalyzes DNA hydrolysis reaction in the absence of divalent cations at acidic pH [in The Enzymes (Boyer, P. D., ed) 3rd Ed., Vol. 4, pp. 271-287 (1971), Academic Press, New York; Arch. Biochem. Biophys., 300: 440-450 (1993)]. While the acid DNase activities are widely found in various animal tissues [Biochim. Biophys. Acta, 1119: 185-193 (1992); J. Biol. Chem., 273: 2610-2616 (1998)], DNase II has been considered to be the sole enzyme responsible for the acid DNase activities. Because DNase II shows low organ specificity and is distributed ubiquitously, a possibility of DNase II playing an important biological role in the fundamental biological phenomena, such as DNA catabolism and apoptosis, has been suggested [The Enzymes (1971), supra; Arch. Biochem. Biophys., 300: 440-450 (1993)].
Even though the enzymological properties of the DNase II isolated from different organisms are very similar, their physicochemical properties and molecular structures are strikingly different. For example, it is known that porcine DNase II is a complex protein consisting of unidentical subunits derived from its precursor protein, but DNase II derived from other animals are mostly single polypeptides [J. Biol. Chem., 260: 10708-10713 (1985); Biochem. Biophys. Res. Commun., 247: 864-869 (1998); J. Biol. Chem., 251: 116-123 (1976); Gene, 215: 281-289 (1998)]. Furthermore, the apparent molecular weights of DNase II vary from 26.5 kDa to 45 kDa [J. Biol. Chem. (1976), supra; Gene, (1998), supra; J. Biol. Chem., 247: 1424-1432 (1972); Eur. J. Biochem., 202: 479-484 (1991)].
The diversity of acid DNases can be also appreciated from the subcellular localization. DNase II is considered to be localized in lysosomes [J. Biol. Chem. (1972), supra; Biochim. Biophys. Acta, 1007: 15-22 (1989)], but acid DNase activity is also found in nuclear fraction [Arch. Biochem. Biophys. (1993), supra; Biochem. J., 136: 83-87 (1973)].
The reason for such molecular diversity of DNase II still remains unclear, but the aforementioned findings suggest the existence of a different acid DNase distinguishable from DNase II. In fact, the present inventors have identified and partially purified novel acid DNases (DNase α and DNase β) from the nuclear fraction of rat thymus (JP 8-187079 A). In view of the foregoing situation it is considered to be critical for the elucidation of the diversity of acid DNases to search other novel acid DNases and determine their characteristics.
In addition, DNase has been actively studied with the aim of applying same for the prophylaxis and treatment of various diseases. One of the clinical applications of DNase, which has been drawing particular attention in recent years, is an application to the treatment of cystic fibrosis (hereinafter sometimes to be also referred to as CF) [Annu. Rev. Pharmacol. Toxicol., 35: 257-276 (1995); Chest, 107: 65-70 (1995)]. CF is a lethal hereditary disease caused by abnormal chloride ion channel of exocrine glands. In the Caucasian population, one in 2500 newborns suffers from this disease and one in 25 Caucasians is a carrier. About 90% of the CF patients die of respiratory insufficiency caused by intractable infection with Pseudomonas aeruginosa in the inferior airway in their 20's and 30's [Curr. Opin. Pulm. Med., 6: 425-434 (1995)]. Phlegm that is accumulated in the airway to impair the respiratory function is caused by high concentration DNA released from the disrupted leukocytes infiltrating into the inflammatory site. Genentech, Inc. U.S. is selling a recombinant DNase I as a therapeutic agent for CF in Europe and America, which aims at removing the high molecular weight DNA accumulated in the lung, recovering the respiratory function and preventing infectious diseases [Annu. Rev. Pharmacol. Toxicol. (1995), supra; Chest (1995), supra]. DNase I not only degrades DNA, but also depolymerizes F-actin which is abundant in the sputum of CF patients. However, since the resulting monomeric G-actin strongly inhibits DNase I, DNase I is immediately inactivated. Actually, DNase I hardly shows any therapeutic effect. Some attempts have been made to produce a G-actin nonsensitive DNase I by genetic recombination, but satisfactory DNase has not been obtained yet [Proc. Natl. Acad. Sci. USA, 93: 8225-8229 (1996); J. Biol. Chem., 273: 18374-18381 (1998)]. Thus, there is a demand on the identification of a novel G-actin nonsensitive DNase effective for the treatment of CF.
A second interest in the clinical application of DNase is that for the prophylaxis and treatment of infectious diseases. Some DNases are considered to play an important role in the biological defense mechanisms against infection with bacteria and viruses, based on degradation of foreign genomic DNAs. Accordingly, identification of the DNase involved in the prevention of infection in mammals, such as human, and utilization thereof as a medicament are expected to open a new possibility in the prophylaxis and treatment of infectious diseases.
It is therefore an object of the present invention to provide a novel acid DNase and clarify the characteristics of the enzyme, thereby providing critical information for the study of the molecular diversity of acid DNases. It is another object of the present invention to provide a novel G-actin nonsensitive DNase that can be effectively used as a therapeutic agent of CF. It is yet another object of the present invention to provide a novel DNase useful for the prophylaxis and treatment of infectious diseases.

Deoxyribonuclease, gene encoding same and use thereof


A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

Field of the Invention
The present invention relates to a laminated chip electronic component for reducing acoustic noise generated by the laminated chip electronic component, a board for mounting the same, and a packing unit thereof.
Description of the Related Art
A multilayer capacitor, a laminated chip electronic component, includes internal electrodes formed between a plurality of dielectric layers.
When DC or AC voltages are applied to the multilayer capacitor having internal electrodes overlapping with dielectric layers interposed therebetween, a piezoelectric effect takes place between the internal electrodes, generating vibrations.
As permittivity of a dielectric layer becomes higher and the size of a chip is larger based on the same capacitance, generated vibrations become more intense. The generated vibrations are transferred from external electrodes of the multilayer capacitor to a printed circuit board (PCB) on which the multilayer capacitor is mounted. Here, the PCB vibrates to produce a noise.
When the noise produced due to the vibrations of the PCB is included in an audio frequency, a corresponding vibrating sound may make users uncomfortable, and such a sound is known as acoustic noise.
In order to reduce acoustic noise, the inventors of the present invention has conducted research on a mounting direction of internal electrodes within a multilayer capacitor, in relation to a PCB. As a result of the research, it has been recognized that mounting a multilayer capacitor on a PCB to have directionality such that internal electrodes of the multilayer capacitor are horizontal with the PCB, may reduce acoustic noise in comparison to a case in which a multilayer capacitor is mounted on the PCB such that internal electrodes thereof are perpendicular to the PCB.
However, even in the case that the multilayer capacitor is mounted on the PCB such that internal electrodes thereof are horizontal with the PCB, acoustic noise may be measured and determined to still be at a certain level or higher, so a further reduction in acoustic noise remains an issue to be studied.

Laminated chip electronic component, board for mounting the same, and packing unit thereof


Coating compositions are disclosed comprising a polyester comprising at least two reactive hydroxyl groups, a material comprising at least two functional groups reactive with the hydroxyl groups of the polyester, and a free acid. Methods of using the coatings, methods for refinishing an article with the coatings, and the substrates coated therewith, are also disclosed.

In the automotive industry, it is desirable to extend the life of vehicle bodies by protecting them from, for example, the abrasive chipping action of road dirt and debris, such as sand and gravel, that may cause an aesthetically unpleasing chipping of the vehicle body surface, which may also lead to rusting. Often, coating compositions designed to aid in various properties, such as corrosion resistance and chip resistance are employed to protect against such damage. Thus, coating compositions, such as primer compositions, have been developed that have desirable chip resistance and/or corrosion resistance properties. Such chip resistant primer compositions may be placed directly upon a metal substrate or between an electrodeposited primer layer, which is directly upon the metal substrate, and an outer topcoat layer.
In the automotive refinish industry, several steps are often involved in repairing defects in the original coating. For example, such a repair can involve sanding or grinding out the defect by mechanical means, or completely stripping the whole part or vehicle of its original coating layers, often resulting in exposure of the bare metal substrate. The sanded area of exposed bare metal is then covered with a corrosion inhibitive primer composition, that is, a primer composition formulated with corrosion inhibitive pigments, such as strontium chromate, zinc phosphate, and derivatives of zinc phosphate, and which also adheres to both bare metal substrate and subsequently applied organic coatings. Next, a sandable primer-surfacer composition is often applied. Then, a primer, often referred to as a sealer, is applied, which improves adhesion of topcoats to the undercoated area, and also often improves the surface properties, such as chip resistance, of the entire coating system.
As is apparent, such a refinish undercoat application process can be time consuming and expensive due to labor, volatile organic abatement engineering requirements, and time required for drying of each of the applied undercoatings. As a result, it would be desirable to provide a coating composition that can exhibit favorable chip resistance and intercoat adhesion and which may allow for simplified methods of refinishing the surface of an article, such as an automobile body.

Coating compositions that include a polyester polyol, related coated substrates, multi-layer coating and methods


In one embodiment, a method for cooling an engine damper, including converting a gas to a liquid, and cooling an engine damper by passing the liquid through a tube portion located between fan air flow and the engine damper.

Dampers, including torsional vibration dampers, are used on many engines to reduce vibrations by converting energy to heat. Dampers often are constructed using an inertia ring in a viscous fluid (e.g., oils, grease, liquids with high silica content, etc., or an inertia ring cooperating with an elastomeric material), where torsional vibration (e.g., imposed by crankshaft forces) forces the fluid through narrow passages that dissipate the vibration as heat. This heat should be dissipated to keep the damper fluid functioning. Typically, engines are mounted behind a cooling packages that expend a considerable amount of heat, making it difficult to keep the engine damper cool. Efforts have focused on damper designs to alleviate high temperature effects, but sometimes conditions arise that present challenges in dissipating heat.

Engine damper cooling utilizing cab A/C circuit


A pre-mix insecticidal composition is disclosed that contains (a) 0.1-10% by weight of 2,4-dioxo-1-(2-propynyl)imidazolidin-3-ylmethyl chrysanthemate, (b) 2.5-50% by weight of a fatty acid ester of 16-19 carbon atoms; (c) 2.5-30% by weight of a sorbitan fatty acid ester; (d) 0.5-1% by weight of at least one alcohol selected from the group consisting of ethanol, 1-propanol, 2-propanol, ethylene glycol, diethylene glycol, triethylene glycol, propylene glycol, dipropylene glycol, butylene glycol and glycerin; and (e) 40-93.5% by weight of a saturated hydrocarbon of 8-18 carbon atoms. This pre-mix insecticidal composition exhibits little, if any, precipitation when left to stand. It is sufficiently stable to be transported and is storage stable prior to formulating an insecticidal aerosol composition. A useful insecticidal aerosol composition contains 5-30% by weight of this pre-mix insecticidal composition, 40-85% by weight of water and 10-50% by weight of a propellant. The aerosol composition is stable, i.e. the separation into aqueous phase and organic phase occurs at a very low rate after shaking. A method for controlling harmful insects is also disclosed.

The present invention relates to an insecticidal aerosol composition and an insecticidal composition used for the preparation of the aerosol composition.
2,4-Dioxo-1-(2-propynyl)imidazolidin-3-ylmethyl chrysanthemate is an insecticidal compound disclosed in U.S. Pat. No. 4,176,189, and it is known in GB2,243,297B that the insecticidal activity of the compound, especially against cockroaches, is enhanced by the addition of some ester compounds.
However, there have been known no insecticidal water based aerosol compositions containing 2,4-dioxo-1-(2-propynyl)imidazolidin-3-ylmethyl chrysanthemate as an active ingredient which are enhanced in control effect against cockroaches and excellent in stability. Especially, in the case of water based aerosols, since they readily separate into an aqueous phase (emulsion) and an organic phase, even if they are shaken before spraying, separation into aqueous phase and organic phase occurs during spraying and as a result the insecticidal activity often becomes changeable.

Insecticidal aerosol composition and insecticidal composition for preparation of same