An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix, a plurality of neuron representing units, a plurality of educator signal control circuits, and a plurality of buffer circuits. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines. Each synapse representing unit includes a learning control circuit which derives synapse load change value data in accordance with predetermined learning rules in response to a first axon signal Si and a second axon signal Sj, a synapse load representing circuit which corrects a synapse load in response to the synapse load change valued data and holds the corrected synapse load value Wij, a first synapse coupling operating circuit which derives a current signal indicating a product Wij.multidot.Si from the synapse load Wij and the first axon signal Si and transfers the same to a first dendrite signal line, and a second product signal indicating a product Wij.multidot.Sj from the synapse load Wij and the second axon signal Sj and transfers the same onto a second dendrite signal line.

1. Field of the Invention
The present invention relates to a neural network, and more particularly, it relates to an integrated circuit device for implementing a Boltzmann machine which has a learning function (self-organizability).
2. Description of the Background Art
In recent years, various calculation processing techniques have been proposed on the models of vital cells (neurons). One of such processing techniques is a parallel information processing machine called a Boltzmann machine. The Boltzmann machine is a sort of a mathematical model representing a neural network, which was proposed in 1985 by D. H. Ackley, G. E. Hinton and T. J. Sejnowsky. The feature of the Boltzmann machine resides in stochastic state transition of neurons. The source of this naming is as follows: When a connection strength (hereinafter referred to as a synapse load) Wij between neurons is symmetrical (Wij=Wji) with no self coupling (Wii=0), a state distribution p(z) of the system (neural network) is in the following Boltzmann distribution with a finite temperature representation parameter T of the system: EQU p(z)=C.multidot.exp(-U(z)/T)
where U(z) represents the potential function of the system, z represents the state of the system of the neurons, and C represents a normalization coefficient.
Through introduction of the above probability with respect to state determination of each neuron, it is expected that the neural network system converges to a global minimum value without being captured by a local minimum value of state energy. In other words, it is expected that a more probable solution can be found. Such a Boltzmann machine is suitable for solution of a complicated cost problem, non-algorithmic problems in pattern recognition, associative storage and the like, in contrast to a Turing machine which requires algorithms for solving problems. Therefore, the Boltzmann machine requires no programs, which have been indispensable to a von Neumann computer. The Boltzmann machine shows behavior similar to sensible judgement of a man, such that it solves a problem simply through data. Thus, the Boltzmann machine is expected to greatly contribute to development of industry.
In general, the Boltzmann machine has been simulated through a von Neumann computer in accordance with programs. In such a case, probabilities have been expressed in pseudo-random numbers, and states of neurons have generally been provided in discrete time expression. This is because the von Neumann computer is restricted to a serial processing system, and it is necessary to repeat a number of operations until respective neurons reach thermal equilibrium states. Further, it is generally predicted in principle that a state convergence time of the overall system is increased in proportion to the square of the number of neurons when the system is in full connection. Thus, a neural network of a practical scale, including at least 1000 neurons, requires an impractical computation time, to cause difficulty in practical application.
To this end, there has been developed a relatively high-speed simulator by connecting a general computer with dedicated hardware, which can operate state transition of neurons at a high speed. However, it is inefficient in principle to apply a serial processing computer to simulation of a neural network, which originally operates in parallel. Hence, it is still difficult to implement a practically applicable simulator.
Thus, awaited is implementation of a device which can efficiently represent a Boltzmann machine of a practically applicable scale at a high speed. If such a device can represent a strong parallel processing system which simulates the operation of a neural network, it is expected that its miraculous convergence time enables practical application to a number of new fields such as that of a real time controller (substitute for a skilled pilot), for example, while its useful feature of structural stability is exhibited in a unit system including the parallel processing system, thereby providing a highly reliable unit.
In order to implement the Boltzmann machine of such a practical level, it is requisite to implement a strong parallel processing system. To this end, it is necessary to build a neural network by preparing and interconnecting/arranging a plurality of functional units representing neurons whose states are stochastically transitive, a plurality of functional units representing synapse loads between the neurons, and a plurality of functional units deciding or correcting the synapse loads arbitrarily or in accordance with learning rules as those of portions to operate in parallel, while setting an input/output unit in response to information to be processed with respect to the neural network.
Some attempts have been made to implement such types of Boltzmann machines by semiconductor integrated circuits. Before explaining the structures and operations of conventional integrated semiconductor neural networks, the principle of operation of the Boltzmann machine is now described in more detail.
FIG. 1 shows the structure and the principle of operation of a general neuron model. Referring to FIG. 1, a neuron unit i includes an input part A which receives output signals S.sub.k, S.sub.j and S.sub.l from other units k, j and, a conversion part B which converts signals from the input part A in accordance with predetermined rules, and an output part C which outputs signals from the conversion part B. The input part A has weights (hereinafter referred to as synapse loads) indicating connection strengths with respect to the units k, j and l. For example, an output signal Sk from the unit k is converted with Wik.multidot.Sk with a synapse load Wij in the input part A, and transferred to the conversion part B. When the total of input signals received from the input part A satisfies certain condition, the conversion part B is fired to output a signal. The input part A of this neuron unit model corresponds to a dendrite of a vital cell, while the conversion part B corresponds to the body of the nerve cell and the output part C corresponds to an axon.
In this neuron model, it is assumed that each neuron takes two states of Si=0 (non-fired state) and Si=1 (fired state). Each neuron unit updates its state in response to the total input thereof. The total input of the unit i is defined as follows: ##EQU1## Symmetrical synapse coupling of Wij=Wji is assumed here while Wii corresponds to the threshold value of the unit i.
The state of the neuron unit is asynchronously and stochastically updated between the units. When the unit i updates its state, the new state is "1" in the following probability: EQU p(Si=1)=1/(1+exp(-Ui/T))
where T represents a parameter which serves as a temperature in a physical system. This parameter takes a positive value, and is generally called a "temperature".
FIG. 2 shows the relation between the total input Ui with respect to each temperature T and the probability p(Si=1). Each unit i takes the value of either "0" or "1" in a probability of 1/2 substantially at random when the temperature T is high, while it substantially decision-theoretically complies with such threshold logic that the state of the total input goes to "1" when the total input exceeds a certain threshold value if the temperature T approximates zero.
The state of the Boltzmann machine at a certain time instant is represented in combination of ONs (S=1) and OFFs (S=0) of all units. With respect to a certain state .alpha. energy E is defined as follows: ##EQU2## In the above equation, it is assumed that the threshold value of each neuron unit is zero. This state can be realized by preparing each unit from that which is regularly in an ON state (S=1) and setting the same so that its connection strength is equal to its threshold value while its sign is reverse thereto.
When each neuron unit starts from an arbitrary initial state and continues its operation, the Boltzmann machine approaches a stochastic equilibrium state which is determined by the synapse loads W (hereinafter the synapse loads are simply denoted by W) of the respective units. In this case, as hereinabove described, the Boltzmann machine takes the state .alpha. in the following probability: EQU P(.alpha.)=C.multidot.exp(-E.alpha./T)
The Boltzmann machine uses a technique called simulated annealing, in order to reach a global minimum energy value. A relative probability of two global states .alpha. and .beta. is expressed as follows: EQU P(.alpha.)/P(.beta.)=exp(-E(.alpha.-E.beta.)/T)
The minimum energy state regularly has the highest probability at an arbitrary temperature. In general, it takes a long time to reach the thermal equilibrium state, and hence it is considered preferable to start the annealing from a high temperature and gradually reduce the annealing temperature. This state transition is similar to such a state that each crystal atom is transferred to a position for taking the minimum energy state at a given temperature in a crystal lattice.
A subject in the Boltzmann machine is to find such weights that the network itself can realize its distribution as correct as possible with no external supply of probability distribution of input/output data. Consider that units of a network K are divided into a set A of input/output units (hereinafter referred to as visible units) and a set B of other units (hereinafter referred to as hidden units).
It is assumed that the set A of the visible units enters a state .alpha. in a probability distribution P.sup.- (.alpha.) when the network K is externally supplied with no probability distribution. Further, the state of the overall set (network) K is expressed as .alpha.+.beta. when the set A is in the state .alpha. and the set B of the hidden units is in the state .beta.. In this case, the following equation holds: ##EQU3## where E.alpha..beta. represents the energy of the network K in the state .alpha.+.beta.. Assuming that Si(.alpha..beta.) represents the state of a unit i in the state .alpha.+.beta. of the network K, the energy of the network K is expressed as follows: ##EQU4## In the aforementioned network model, probability distributions of input units are not separated from those of output units. Such a network is called a self-associative Boltzmann machine. In a network called an inter-associative Boltzmann machine, on the other hand, it is necessary to separate the probability distributions of states of input units from those of states of output units originally supplying inputs.
When the network K is externally supplied with inputs/outputs, the set A of the visible units enters the state .alpha. in a probability distribution P.sup.+ (.alpha.). This probability distribution P.sup.+ (.alpha.) is independent of the synapse load Wij. The subject is to evaluate such a synapse load Wij that minimizes the difference between the probability distributions P.sup.+ (.alpha.) and P.sup.- (.alpha.). That is, evaluated is such a synapse load Wij that minimizes the following Kullback information measure: ##EQU5## with respect to the probability distributions P.sup.+ (.alpha.) and P.sup.- (.alpha.). The following equation results from the equation (3), to be used as a basic equation of the learning rules: EQU .alpha..beta./.alpha.Wij=-(1/T)(p.sup.+ ij-p.sup.- ij)
The above equation is generally provided in the following form: EQU .DELTA.Wij=.eta..multidot.(p.sup.+ ij-p.sup.- ij) (4)
where p.sup.+ ij represents such an expected value that both of the neuron units i and j enter states "1" when the network K is externally supplied with educator information and enter equilibrium states. On the other hands, p.sup.- ij corresponds to an expected value in such case that no educator information is externally supplied. In the above equation (4), the term p.sup.+ ij means that the connection strength Wij between the adjacent units i and j is increased when both of the units are activated. This corresponds to a learning mechanism, called a Hebb's learning rule, for strengthening synapse coupling.
On the other hand, the term p.sup.- ij means that the connection strength Wij between the adjacent units i and j is reduced when both of the units are activated with no external supply of input/output. This is generally called Hebb's anti-learning.
A learning algorithm in the Boltzmann machine will now be briefly described.
The learning algorithm in the Boltzmann machine includes an operation 1 (plus (+) phase), ah operation 2 (minus (-) phase) and an operation 3.
Operation 1 (plus (+) phase):
States of input units and output units (visible units) are clamped at specific patterns shown by input data and output data (educator data) in accordance with appearance probabilities of respective patterns. The operation 1 (plus phase) includes (1) an annealing process, (2) a data collecting process and (3) a process of evaluating p.sup.+ ij. In the annealing process (1), the state of each unit is changed for each temperature T in accordance with the following equations (5) and (6): ##EQU6## EQU Pi=1/(1+exp(-.DELTA.Ei/T) (6)
The equation (5) expresses an energy gap between a state Si of "0" and a state Si of "1" of the unit i with respect to the energy E of the overall neural network. The equation (6) expresses such a probability that a new state Si of the unit i takes the value "1" when such an energy gap takes place. In the annealing process (1), the temperature T is successively converted from a high level to a low level. It is assumed that the network is relaxed to the minimum energy state and reaches a thermal equilibrium state when the temperature T is converted to a low level and a prescribed annealing procedure is terminated.
In the data collecting process (2), evaluated is such a number of times that both of respective states S of coupled units are "1" after the annealing process (1) is repeated by a prescribed number of times.
In the process (3) of evaluating p.sup.+ ij, an average value of data obtained in the process (2) is evaluated after the annealing process (1) and the data collecting process (2) are repeated by prescribed numbers of times in correspondence to received educator information, and this average value is assumed to be p.sup.+ ij.
The operation 2 (minus phase) similarly includes an annealing process (1), a data collecting process (2) and a process (3) of evaluating p.sup.- ij. The processes (1), (2) and (3) are similar to those in the operation 1 (plus phase). In the operation 2 (minus phase), however, only the states of units corresponding to input data are clamped in accordance with the appearance probability of the educator data. In this operation 2, an average value evaluated in the process (3) after the processes (1) and (2) are repeated is assumed to be p.sup.- ij, similarly to the operation 1.
In the operation 3, the synapse load Wij is varied in accordance with the following relational expression: EQU Wij=.eta..multidot.(p.sup.+ ij-p.sup.- ij)
from the evaluated values p.sup.+ ij and p.sup.- ij. Symbol .eta. represents a positive constant which determines the degree of a single variation of the synapse load Wij. The variation process of the synapse load Wij is determined by only the states of the two units i and j which are coupled with each other, as clearly understood from the above equation. The final object of the learning is minimization of the value G in the equation (3), i.e., minimization of the above value .DELTA.Wij such that the same ideally converges to zero.
As to the aforementioned variation of the synapse load Wij, the following relational expression may be employed in an electronic circuit, in order to simplify its structure: ##EQU7##
"A Neuromorphic VLSI Learning System" by J. Alspector et al., "Advanced Research in VLSI 1987" issued by MIT Press, p. 313 to 327, discloses an exemplary device which implements the aforementioned Boltzmann machine by an integrated circuit. The structure and operation of such a conventional semiconductor neural network device implementing the Boltzmann machine will now be described.
FIG. 3 shows an exemplary structure of the neural network. Referring to FIG. 3, the neural network includes complementary input data line pairs IN1 and IN1 to INj and INj, which are arrayed in the row direction, and complementary data output line pairs S1 and S1 to Sj and Sj, which are arrayed in the column direction. The neural network is further provided with differential amplifiers Z1 to Zj, which detect and amplify potential differences on the input line pairs INk and INk (k=1 to j) and transfer the same to the data output lines Sk and Sk. The respective differential amplifiers Zk correspond to neurons, while the data input lines IN and IN correspond to dendrites and the data output lines S and S correspond to axons. Synapse loads W are supplied by resistive elements R, which are arranged on crosspoints between the data input lines IN and IN and the data output lines S and S.
In the Boltzmann machine model, the synapse loads W have such a symmetric property that Wij=Wji. Thus, the differential amplifiers Zk are arranged on a diagonal line of a connection matrix formed by the data input lines, the data output lines and the resistive elements.
The differential amplifiers Zk have complementary outputs S and S. When the neurons are in ON states, the S outputs of the differential amplifiers Zk are "1" (5 V). When the neurons are in OFF states, on the other hand, the S outputs are "0" (0 V). The outputs of the differential amplifiers Zk are fed back to the data input lines IN and IN through the resistive elements R, indicating the synapse loads, which are arrayed in the matrix. A resistive element R, which is arranged on the i-th row and j-th column in the connection matrix, connects the output of the differential amplifier (neuron) Zj to the input of the differential amplifier (neuron) Zi. When the synapse load Wij is positive, therefore, the data output line Sj is connected to the data input line INi, and the data output line Sj is connected t the data input line INi. When the synapse load Wij is negative, on the other hand, the data output line Sj is connected to the data input line INi, and the data output line Sj is connected to the data input line INi.
A differential amplifier Zt, which is provided in a region V of the connection matrix, is regularly in an ON state, while an output line Sv is regularly supplied with "1" and an output line Sv is regularly supplied with "0". Such a structure eliminates influence by a threshold value in each neuron unit, and each threshold value is equivalently set at zero.
This network is initialized by setting the weight (resistance value) of each resistive element R. Data of the synapse load Wij is transferable along arrows shown in FIG. 3 through a weight processing circuit which is provided in correspondence to each resistive element R, as hereinafter described.
FIG. 4 shows the structure of each synapse load part (resistive element). The synapse load part includes four transistor groups TR1, TR2, TR3 and TR4, in order to provide positive coupling (excitatory coupling) and negative coupling (inhibitory coupling). Each of the transistor groups TR1 to TR4, which are identical in structure to each other, includes n MOS (metal oxide-semiconductor) transistors T.sub.0 to T.sub.n-1 and one pass transistor TG. ON resistances of the MOS transistors T.sub.0 to T.sub.n-1 are set as 1:2: . . . :2.sup.n-1, in order to provide different resistance values. The pass transistors TG1 and TG4 receive a signal TSGN indicating the sign of the synapse load, while the pass transistors TG2 and TG3 receive a complementary signal TSGN. The signals TSGN and TSGN are complementary signals, which determine whether the sign of the synapse load is positive or negative. When the synapse load Wij is positive, the signal TSGN is "1", and the transistor groups TR1 and TR2 provide the synapse load Wij. When the synapse load Wij is negative, on the other hand, the complementary signal TSGN is "1", and the transistor groups TR2 and TR3 provide the synapse load Wij. The synapse load is set by turning one or more MOS transistors in each transistor group TR on through an output from a weight processing circuit, as hereinafter described.
FIG. 5 shows the structure of each differential amplifier Z forming a neuron. The differential amplifier Z includes p-channel MOS transistors PT1 and PT2, and n-channel MOS transistors NT1, NT2, NT3 and NT4. The p-channel MOS transistors PT1 and PT2 provide a pair of differential outputs, and transfer complementary data to data output lines S and S. The n-channel MOS transistors NT1 and NT2 provide a first differential input pair, while the n-channel MOS transistors NT3 and NT4 provide a second differential input pair. The first differential input pair differentially amplifies the potential difference on data input lines IN and IN to provide an energy gap ##EQU8## while the second differential input pair generates an annealing temperature T in the form of a noise. The second differential input pair receives a complementary output from an amplifier AZ, which receives a noise from a noise source NS. The level of a noise signal from the amplifier AZ is reduced with progress of a certain phase. Hence, such a process is realized that annealing is started at a high temperature and the annealing temperature is successively reduced so that the neural network is not captured by a pseudo optimum solution (local minima) but stabilized to a global minimum value. In general, the amplifier AZ is formed by an operational amplifier, whose gain is externally adjusted to set the annealing temperature.
In order to adjust input/output characteristics of the neuron (differential amplifier), a further n-channel MOS transistor NT5 is provided for receiving a prescribed bias potential V.sub.bias at its gate.
FIG. 6 shows an exemplary structure of the weight processing circuit. Referring to FIG. 6, the weight processing circuit includes a correlation logic CL, an up/down logic UDL, and flip-flops FF0 to FFn. In the Boltzmann model, the synapse loads have such a symmetrical property that Wij=Wji. Therefore, the weight processing circuit is commonly provided for the symmetrical synapse loads Wij and Wji. The flip-flops FF0 to FFn control ON and OFF states of the MOS transistors representing the synapse loads. The flip-flop FF0 stores information indicating the sign of the synapse loads, and controls on-off operations of the pass transistors TG. The flip-flops FF1 to FFn control on-off operations of the MOS transistors T.sub.0 to T.sub.n-1.
The correlation logic CL counts the numbers of a signal indicating the phase in operation and a signal COOC indicating such time when both of the outputs Si and Sj of the neuron units (differential amplifiers) Zi and Zj are "1", and evaluates a probability distribution Pij. When a weight adjusting signal ADW is received, the correlation logic CL supplies a signal indicating an increment, a decrement or holding (silent state) to the up/down logic UDL through the evaluated probability distribution Pij in accordance with the equation (4).
In response to the increment/decrement indication signal from the correlation logic CL, the up/down counter UDL increments, decrements or leaves intact the count value, and transfers the same to the flip-flops FF0 to FFn. The up/down logic UDL has the structure of a shift register, which can receive synapse load data W from an up/down logic included in an adjacent weight processing circuit in initialization, and can transfer the data to another up/down logic included in another adjacent weight processing circuit.
FIG. 7 shows an exemplary structure of the up/down logic UDL. In the structure shown in FIG. 7, a synapse load W is expressed in four bits (including one sign bit). FIG. 7 shows no path for setting weight data from the adjacent weight processing circuit as shown in FIG. 6. The up/down logic UDL is formed by an updown counter 100'. This updown counter 100' comprises a terminal U/D which receives a signal indicating incrementation/decrementation of the count value, a terminal T which receives a signal providing variation timing for the count value, a reset terminal R, and data output terminals Q0 to Q3. Outputs of the output terminals Q0 to Q2 provide the level of the synapse load W, and the output terminal Q3 outputs data defining the sign of the synapse load W. The output data from the output terminal Q3 is transferred through an inverter I1. Signal lines 103' to 106' are coupled to the flip-flops FF0 to FFn (n=3) respectively. In accordance with the incrementation/decrementation indication signal transferred through the signal line 102', the updown counter 100' increments, decrements or holds its count value when a timing signal is received through the signal line 101'. The synapse load is learned by this operation. A signal on a signal line 107' resets the updown counter 100'.
A threshold value processing operation of one neuron (differential amplifier) Zi is now described with reference to FIG. 8. Referring to FIG. 8, one transistor TC typically shows a conductance representing each synapse load W. When the synapse loads W are positive and the neurons are in ON states (differential amplifier outputs S are "1") or the synapse loads W are negative and the neurons are in OFF states, voltages V.sub.on and V.sub.off are transferred to the data input lines IN and IN through conductances on Ist and IVth rows. Conductances on IInd and IIIrd rows are those developed when the synapse loads W are negative and the neurons are in ON states or the synapse loads W are positive and the neurons are in OFF states (differential amplifier outputs S are "0").
The voltage V.sub.off is transferred to the data input line IN, and the voltage V.sub.on is transferred to the data input line IN. The positive input of the differential amplifier Zi is coupled with a conductance which is pulled up to the voltage V.sub.on and a conductance which is pulled down to the voltage V.sub.off. The conductance which is pulled up to the voltage V.sub.on is provided by the absolute value of the sum of positive synapse loads W from neurons which are in ON states. A conductance, which is provided by the absolute value of the total sum of positive synapse loads W from OFF-state neurons, pulls down the potential at the positive input of the differential amplifier Zi to V.sub.off. The relation between conductances in a negative input (-) of the differential amplifier Zi is evaluated from the relation, which is reverse to the same, in a positive input of the differential amplifier Zi. Considering the aforementioned relations with the fact that the synapse loads in the region V of FIG. 3 are provided as -.theta.i, the differential amplifier Zi simply performs the following comparison: ##EQU9## The differential amplifier Zi performs threshold value processing in accordance with the above expressions, and outputs the data to the data output lines S and S.
In the aforementioned structure, it is also possible to obtain desired output data by simply comparing the value of the positive input (+) of the differential amplifier Zi with a prescribed threshold value (V.sub.on +V.sub.off)/2. FIG. 9 shows another structure.
The structure shown in FIG. 9 is described in "Electronic Implementation of Neuromorphic System" by Jack I. Ruffel, IEEE 1988 Custom Integrated Circuit Conference, pp. 10.1.1. to 10.1.7.
Referring to FIG. 9, a circuit part (hereinafter referred to as a synapse polarity converting circuit) for outputting the product of a load and Sj of a data output line includes a synapse load representing part representing a synapse load Wij in accordance with data stored in a register 200', and a constant current circuit 210'. The register 200' has unit registers B0 to B2 which determine the value of the synapse load Wij, and a unit register B3 which outputs data for setting the sign of the synapse load Wij. The register 200' corresponds in structure to the flip-flops FF0 to FFn shown in FIG. 6.
The synapse load representing part has n-channel MOS transistors 201'a to 201'd, 202'a to 202'd and 203'a to 203'd. Data of the registers B0 to B2 are transferred to the gates of the MOS transistors 201'a, 202'a and 203'a through signal lines 200'a to 200'c respectively. An output signal of the data output line (axon signal line) Sj is transferred to the gates of the MOS transistors 201'b, 202'b, 203'b, 201'c, 202'c and 203'c. Output data from the register B3 is transferred to the gates of the MOS transistors 201'd, 202'd and 203'd through a signal line 200'd. The MOS transistors 201', 202' and 203' are set in the transistor width (gate width) ratio 1:2:4, whereby the MOS transistors 201', 202' and 203' are set in the conductance ratio 1:2:4. The transistor 201' is the generic name for the MOS transistors 201'a to 201'd. This also applies to the transistors 202' and 203'.
The constant current circuit 210' includes n-channel MOS transistors NT10 and NT11 and p-channel MOS transistors PT11 and PT12. The MOS transistor NT10 includes a diode-connected n-channel MOS transistor NT10b, and an n-channel MOS transistor NT10a whose gate is connected to the gate of the MOS transistor NT10b. Similarly, the n-channel MOS transistor NT11 has a diode-connected MOS transistor NT11b, and a MOS transistor NT11a. The p-channel MOS transistor PT11 has a diode-connected p-channel MOS transistor PT11a, and a MOS transistor PT11b. The MOS transistor PT12 includes a diode-connected p-channel MOS transistor PT12a, and a p-channel MOS transistor PT12b. The MOS transistor pairs NT10, NT11, PT11 and PT12 form a current mirror type constant current circuit. Therefore, a current I.sub.0 on a signal line 211'a, which is outputted from the constant current circuit 210', is equal to the sum of a current flowing on a signal line 211'b and that flowing on a signal line 212' (data input line IN). The signal line 211'a is connected to first conducting terminals of the MOS transistors 201'a, 202'a and 203'a, while the signal line 211'b is connected to first conducting terminals of the MOS transistors 201'd, 202'd and 203'd. The operation is now briefly described.
First, it is assumed that the potential signal Sj on the data output line is at a high level and the corresponding neuron is in an ON state.
When the synapse load Wij is positive, a low-level signal potential is transferred form the register B3 onto the signal line 200'd. Thus, all of the MOS transistors 201'd, 202'd and 203'd are in OFF states. In response to synapse load data from the registers B0 to B2, one of the MOS transistors 201'a, 202'a and 203'a enters an ON state. Thus, the current flowing on the signal line 211'a flows to the ground potential through the MOS transistor which is in an ON state. Consequently, the current I.sub.0 flowing on the signal line 211'a is increased, while the current I.sub.i flowing on the signal line 211'b remains unchanged. Thus, a current (I.sub.0 -I.sub.i) appearing on the signal line 212' is increased in correspondence to the increase in the current flowing on the signal line 211'a, to indicate the degree Wij.multidot.Sj of coupling between neurons j and i.
When the synapse load Wij is negative, on the other hand, the register B3 outputs a high level and all of the MOS transistors 201'd, 202'd and 203'd enter ON states, thereby opening a path for receiving the current from the signal line 211'b. In this state, the current is extracted from the signal line 211'b to the ground potential in an amount identical to that extracted when all of the MOS transistors 201'a, 202'a and 203'a are in ON states. The current (I.sub.0 -I.sub.i) on the signal line 212' is reduced by such increase of the current I.sub.i flowing on the signal line 211'. In this state, the synapse load is subjected to an offset in the negative direction by the absolute value of the maximum value of a state provided by the product of the load Wij and the output Sj of the neuron j. Thus, negative Wij can be represented.
When the output Sj of the neuron j is at a low level and the neuron j is in an OFF state, all of the MOS transistors 201'b, 201'c, 202'b, 202'c, 203'b and 203'c enter OFF states, and hence no path is opened to extract the currents from the signal lines 211'a and 211'b. Therefore, the currents I.sub.0 and I.sub.i flowing on the signal lines 211'a and 211'b are equal to each other, and the current value (I.sub.0 -I.sub.i) appearing on the signal line 212' is zeroed to represent a state of Wij.multidot.Sj=0.
Thus, the output state of the neuron unit i is determined by connecting a plurality of synapse representing circuits in parallel with the signal lines 211a and 211b and comparing the current flowing on the signal line 212' with the threshold value .theta..sub.i.
In the aforementioned structure of the integrated semiconductor neural network, the number of neuron units is still extremely small, and the respective functional blocks are formed in single chips, which are interconnected to provide one neural network.
In order to arbitrarily represent both of excitatory and inhibitory coupling states in representation of synapse loads, the conventional Boltzmann machine provided with a learning function requires four signal lines S, S, IN and IN as shown in FIG. 3, for each neuron as signal lines (axons) showing the state of the neuron and input lines (dendrites) transferring the data supplied to the neuron. Thus, the number of wires is so increased that interconnection in the neural network is complicated with difficulty and the area of interconnection is increased to cause difficulty in high integration.
In order to implement learning (self organization) of the neural network at a high speed, it is effective to correct the respective synapse loads in parallel in accordance with the aforementioned conversion expression (4): EQU .DELTA.Wij=.eta..multidot.(p.sup.+ ij-p.sup.- ij)
Thus, it is necessary to provide a circuit for calculating .DELTA.Wij and a synapse load control circuit for correcting synapse load information on the basis of the supplied .DELTA.Wij in correspondence to a circuit for representing each synapse load (see FIG. 6), and hence the circuit scale is increased to cause difficulty in high integration. In the structure shown in FIG. 6, the synapse load Wij is symmetrical and the Wij calculating circuit and the synapse load control circuit are used in common. In a practical scale, however, at least 1000 to 1500 neuron units are required. Therefore, it is necessary to extend the neural network by interconnecting a plurality of semiconductor neural network chips. However, a single chip providing synapse load representation may be in a state not satisfying the relation Wij=Wji. In this case, it is impossible to simply use a Wij calculating circuit and a synapse load control circuit for representing two synapse loads in common, dissimilarly to the above. Thus, the semiconductor neural network cannot be easily extended.
Further, only six neuron units have been illustrated in relation to the conventional semiconductor neural network, and no consideration has been made on a structure for extending the semiconductor neural network.
In the learning algorithm, on the other hand, it is necessary to implement stochastic state transitions of neurons while implementing controlled simulated annealing. However, it has been difficult to freely electrically control representation of such stochastic state transitions of the neurons and simulated annealing from the exterior, due to a number of restrictions. In the conventional Boltzmann machine, stochastic state transitions of neurons are generally represented with pseudo-random numbers in simulation in a von Neumann computer. In an electronic circuit device employing operational amplifiers such as those shown in FIGS. 3 and 5, each operational amplifier is used as a comparator, whose first input terminal is connected with a load sum input signal (dendrite signal line) IN while its input terminal is connected with a noise signal from a noise source (NS, AZ). This structure exhibits such a tendency that a high voltage appears at the output terminal of the operational amplifier when the voltage value of the load sum input signal exceeds a time average of noise voltages while a low voltage appears in other case. When a noise potential supplied from the noise source deviates in terms of the time average at a speed of change which is sufficiently faster than the change of the total load input signals and the comparator can follow the said speed of the change, the variation of a threshold value on a time base can be expected in a range corresponding to the width of the noise. In this case, the output of the comparator (operational amplifier) represents a stochastic transition state.
However, this structure requires control for reducing the noise width as a function of time in order to implement efficient simulated annealing. Although such control is generally achieved by controlling the gain of the operational amplifier AZ, it is difficult to derive a desired attenuating noise signal by such gain control. Further, it is difficult to achieve such gain control by high and low voltage signals of binary levels from an exterior to the device, while it is also difficult to generate a noise signal having desired time-dependent attenuation through such logical binary voltages.
When a noise generation source generating a thermal noise is employed, it is necessary to selectively extract a component in a frequency domain providing a variation speed which meets the object. Thus, an additional circuit is required for this and hence the circuit scale for generating simulated annealing is increased to increase the scale of the neural network.
In learning (self organization) of the Boltzmann machine, it is necessary to increase or decrease synapse loads. The up/down counter shown in FIGS. 6 and 7 is employed for increasing or decreasing the synapse loads. However, since it is necessary to repeat learning by tens of times in such a simple up/down counter, the contents of the up/down counter may overflow in learning. When such an overflow occurs in the up/down counter for setting the synapse loads, erroneous learning is made since the counter outputs a signal which is absolutely different from the learning value. Thus, it is impossible to correctly set the synapse loads.
On the other hand, the synapse polarity converting circuit for calculating a degree W.multidot.S of coupling between neurons requires four pairs of MOS transistors for providing excitatory coupling and inhibitory coupling in the structure shown in FIG. 4. Thus, the structure of the synapse load representing part is complicated and the circuit scale thereof is increased. Further, the data input lines IN and IN and the data output lines S and S are required for operating the products/sums, and hence the semiconductor neural network is prevented from high integration, as a matter of course.
Further, the current mirror type constant current circuit shown in FIG. 9 requires two current output signal lines, and hence the neural network is prevented from high integration.
When the current mirror type constant current circuit is employed, further, the amount of its driving current or an output current derived from the constant current circuit is determined depending on the sizes of transistors forming the constant current circuit. Thus, it is impossible to achieve extended connection for a number of synapse load representing parts (circuits for calculating Wij.multidot.Sj) which are connected to a single constant current circuit. In other words, it is impossible to drive a number of synapse load representing circuit parts by one constant current circuit. Thus, the neural network is increased in scale, while it is impossible to easily extend the neural network.
In the conventional Boltzmann machine, the learning rules are achieved in accordance with: EQU .DELTA.Wij=.eta..multidot.(P.sup.+ ij-P.sup.- ij)
It is necessary to calculate P.sup.+ ij and P.sup.- ij in this case, and such calculation is made in the correlation logic shown in FIG. 6. The correlation logic shown in FIG. 6 is required in order to calculate such P.sup.+ ij and P.sup.- ij as well as to output the variation Wij. In this correlation logic, it may be necessary to count numbers at which both of the signals Sj and Si are "1" and to obtain an average value of the numbers over a number of repeated times of actually performed simulated annealing In order to form the correlation logic, therefore, the amount of hardware is increased and the calculation time is also increased.
Further, multibit operation is required for evaluating P.sup.+ ij-P.sup.- ij, and this multibit operation is performed through an up/down logic. Thus, the bit number of the counter circuit is increased and the circuit structure for calculating .DELTA.Wij is increased, to cause difficulty in high integration of th neural network.
In the conventional Boltzmann machine, it is necessary to perform the plus and minus phase operations respectively, in order to obtain the synapse load variation .DELTA.Wij. In the plus phase operation, an educator signal is supplied also to an output neuron, which is clamped in correspondence to the educator data. In the minus phase operation, on the other hand, the output neuron receives no educator data but remains in a free state. In learning of the neural network, therefore, it is necessary to make the educator signal valid/invalid in response to each phase, while definition of the attribute of each neuron (hidden neuron or visible (input/output) neuron) must be easily variable in extension of the neural network. Thus, the attribute of each neuron must be arbitrarily settable in the neural network, while a structure for easily transferring an educator signal to a set visible neuron is required in order to implement extended arrangement of the neural network.

Neural network integrated circuit device having self-organizing function


A new and distinct variety of peach tree, Prunus persica, cv. ‘Supechtwentysix’ is characterized by early ripening, large-size fruit, having medium brix, melting flesh, medium adherence of the stone to the flesh, and a large percentage of over-color.

This invention relates to the discovery and asexual propagation of a new and distinct variety of peach, Prunus persica cv. 'Supechtwentysix'. The variety 'Supechtwentysix' was originated by hybridization and was first selected in May 2012 by Terry Bacon as breeder number: 'PE1479'. The new variety was first evaluated by Terry Bacon near Wasco, Calif. in Kern County.
The new variety 'Supechtwentysix' is characterized by having early ripening, large-size fruit, with medium brix, melting flesh, medium adherence of the stone to the flesh, and a large percentage of over-color.
The seed parent is 'PE226' (unpatented breeding selection), and the pollen parent is unknown (open pollination). The parent varieties were first crossed in February 2008, with the date of sowing being February 2009, and the date of first flowering being February 2011. The new peach variety 'Supechtwentysix' was first asexually propagated by Terry Bacon near Wasco, Kern County, Calif. in February 2014 by dormant grafting.
The new variety 'Supechtwentysix' is distinguished from its seed parent, 'PE226', in that harvest of the fruit of the new variety starts about twenty days later than for 'PE226' and the fruit diameter of the new variety 'Supechtwentysix' is larger at 82 mm compared to 69 mm for 'PE226'.
The fruit of the new variety 'Supechtwentysix' ripens about the same time as 'Brittney Lane' (U.S. Plant Pat. No. 10,286). However, the fruit of the new variety 'Supechtwentysix' has a diameter of 82 mm compared to the diameter of the fruit of 'Brittney Lane' of 78 mm. Further, the new variety 'Supechtwentysix' has a larger fruit weight at 270 g compared to 230 g for 'Brittney Lane'.
The fruit of the new variety 'Supechtwentysix' ripens about 17 days later than 'Supechtwentyone' (U.S. Plant Pat. No. 26,773). Additionally, the fruit of the new variety 'Supechtwentysix' has a diameter of 82 mm compared to a diameter of 74 mm for the fruit of 'Supechtwentyone'. Further, the new variety 'Supechtwentysix' has a larger fruit weight at 270 g compared to 198 g for the fruit of 'Supechtwentyone'.
The new variety 'Supechtwentysix' ripens about 34 days later than 'Supechfifteen' (U.S. Plant Pat. No. 13,177). Additionally, the fruit of the new variety 'Supechtwentysix' has a larger fruit weight at 270 g compared to 200 g for 'Supechfifteen'. The new variety 'Supechtwentysix' has a higher degree of over-color at 95+% compared to 80% for the fruit of 'Supechfifteen'
The new variety 'Supechtwentysix' has been shown to maintain its distinguishing characteristics through successive asexual propagations by, for example, cuttings and grafting.


A screen printing machine has a drive mechanism for moving printing platens along an endless horizontal path through successive printing stations and a printing screen carried by a printing head above the endless path at each printing station. A platen alignment mechanism at each printing station has locating members movable vertically into and out of engagement with freely rotatable rollers on the platen supports. A screen positioning mechanism at each printing station has screen holders engageable with opposite sides of screens, and the screen holders each comprise a screen support mounted for pivotation to and fro between a position beneath one of the screens. A lifting system at each printing station has supports positioned to support opposite ends of one of the printing heads and a support drive mechanism operable to simultaneously raise the supports. A squeegee support bar is provided which has a recess extending longitudinally of the bar at an underside thereof, and an elongate retainer extending longitudinally of the bar and having a projecting portion. The elongate retainer is movable between an operative position, in which the projecting portion releasibly engages and retains a squeegee relative to the squeegee support bar, and a released position, in which the projecting portion releases the squeegee from the bar.

1. Field of the Invention
The present invention relates to screen printing machines and, more particularly, to screen printing machines in which printing platens are moved around an endless path through successive printing stations.
2. Description of the Related Art
Screen printing machines of this type are known, for example, for printing T-shirts, and such machines usually comprise a plurality of printing stations, each provided with a printing screen, an inking and squeegee system for applying ink to the screen and a platen alignment system for locating the platens in position as the platens arrive, in succession, at each printing station.
In such machines, the platens are driven by means of an endless chain drive mechanism around their endless path on a machine bed. The alignment of each platen at each printing station has been effected by means of an alignment mechanism applying force to the platens in a direction extending transversely of the path of travel of the platens. This has the disadvantage that the force exerted by this alignment mechanism tends to force components of the machine frame at opposite sides of the path of travel apart from one another, thus adversely affecting the accurate positioning of the platens at the printing station during printing operations.
More particularly, the frames of screen printing machines are normally constructed of frame components which are bolted together and which, consequently, tend to flex out of shape when subjected to forces tending to urge the frame components apart from one another. However, for accurate printing at successive printing stations, it is necessary to ensure that each platen is accurately located in position during each printing operation.
In prior art printing machines, as each platen arrives at a printing station, it is pushed so as to slide horizontally, in a direction transverse to the path of travel of the platen, to urge a drive chain, provided for displacing the platen around the path, into abutment with a rail in order to register the platen for printing.
Since each of the platens is simultaneously forced so as to slide against friction into abutment this way, and since the forces acting on the platens are exerted transversely of the path of travel of the platens, the machine frame is thus subjected to these forces, at various positions, and consequently the components of the machine frame are deflected, thus adversely affecting the accuracy of the registration of the platens.


An improved ultrasound transceiver array for permitting improved imaging is taught. The array may be either a two dimensional array for volumetric imaging or a one dimensional array of elements shaped to permit a more precise beam focus for finer resolution imaging. An Nd:YAG laser is used to machine a workpiece from both ends to produce kerfs which taper inwardly from the transceiving side of the array thereby permitting a stronger ultrasound signal and clearer imaging.

Ultrasound imaging devices have become an important part of medical technology. The most commonly familiar applications for these devices are fetal imaging and cardiac imaging. The transceiver of an ultrasound imaging system is typically housed in a probe that is placed over a portion of the imaging subject's body.
An ultrasound transceiver is generally an array of piezoelectric elements. A pulse of electricity applied to ultrasound material will physically perturb it, producing a sound wave. In reverse, a sound wave striking ultrasound material will create a pulse of electricity. In an ultrasound imaging system, electrical driver circuitry perturbs the ultrasound elements with pulses of electricity. The ultrasound beam thus created reflects from the tissue of the imaging subject and returns to the transceiver, creating an "echo" signal. This signal is sampled to produce a time stream of data. The time at which any particular sample is collected is proportional to the distance (i.e. range) from the transceiver to the tissue represented by the sample.
Typically, an ultrasound array is electronically focused and steered. This means that the beam direction is determined by setting the amplification and relative phase relationship of each piezoelectric element. Because a present day ultrasound transceiver is typically a one dimensional, linear array of elements, the beam can only be steered in one angular dimension, thereby defining a single scan plane and constraining the data collection to a 2-dimensional cut as described above. If the beam could be steered in two angular dimensions, it would be possible to gather data in two angular dimensions and in range, thereby describing a volumetric portion of the imaging subject rather than a cut. This data could be displayed holographically, as a false color map or as a two dimensional image that would be rotatable in three dimensions.
A transceiver that is electronically steerable in two dimensions must include a two dimensional array of individually controllable elements. A number of problems present themselves in the construction of such an array. First, there is the problem of constructing the elements themselves. One dimensional arrays have traditionally been produced by starting with a solid piece of polarized piezoelectric material and forming individual linear elements by sawing cuts (referred to as "kerfs" in the micromachining field) into this material with a dicing saw. This process generally is too destructive for the production of a two dimensional array. Production using an excimer laser has been tried, but the problems of focusing and time-controlling this type of laser proved so great that only a limited success was achieved.
In addition, to operate correctly, the piezoelectric material of each element must be polarized. It is far more economical and more effective to begin with a solid piece of polarized dielectric material and then machine it without disturbing the polarization. The heat produced by machining with an excimer laser tends to destroy the polarization of the piezoelectric material.
A problem shared by efforts to construct such an array with virtually any sort of energy beam is that the kerfs tend to have a v-shaped cross section. Because the elements are optimally spaced .lambda./2 apart, where .lambda. is the wavelength of the transmitted ultrasound, the v-shaped kerfs deprive the user of part of the potential maximum .lambda..sup.2 /4 surface area of each element. This forces the use of a larger transmit voltage pulse for the production of the same volume of ultrasound per element and reduces the receive sensitivity of each element.
The problem of connecting each piezoelectric element of an array to driver and amplifier circuitry is also a challenge. A typical ultrasound frequency is 5 MHz, which is equivalent to a wavelength of 300 .mu.m and necessitates a two dimensional element with a transceiving surface of 150 .mu.m square. Because of this small element cross section, each element presents a high impedance to the electrodes that are placed across it. The longer the electrical leads, the more transmission line problems, such as reflection and cross-talk, will be encountered. In addition, it is a challenge to simply extend a lead to each element because in a sizable two dimensional array, the path of many leads must intersect.

Method of producing an ultrasound transducer


End faces of copper alloys to be used for electrical conductors are placed in contacting relationship under a compressive force below the yield strength of the copper alloy conductor in the room temperature condition. The contacting end faces are heated under continuous compression at a temperature of at least 300.degree. C. but below the solvus temperature of the copper alloy in at least one heating cycle.

The present invention provides a process for joining dilute copper based alloys to be used for electrical conductors, such as wire and cable, to produce long coils of wire and shaped wire products. The process achieves high strength welds close to parent properties and characteristics without the need for heat or mechanical treatment to restore properties to the weld and its adjacent zone typical of current welding practices.
Electrical connector and conductor applications which are not satisfied by commercially pure copper are increasingly being replaced by dilute alloys of copper. These alloys have less than 20% alloying content (80% copper based) and usually have less than 5.0% alloying content. The alloying addition is designed to strengthen the structure by precipitation and/or particle or work hardening, thereby only minimally impacting conductivity.
The process involved in making or maintaining long coils of these alloys requires coil butt welding. Due to the nature of the drawn and shaped wire forming processes or cabling procedures and to assure economics, these end butt welds should desirably be done so as not to degrade the metal properties in the weld region. Naturally, also, the weld structure should be as close to the parent structure in mechanical and electrical properties as possible. Specifically, a weld zone of heat affected metal resulting from a fusion bonding process would adversely affect mechanical properties and especially electrical conductivity. Cold pressure welding, which is significantly more difficult to do in large or non-round configurations, also yields significant increases in strain hardening with concomitant loss in ductility in the weld zone.
One can overcome the above deficiencies by subsequent heat treating procedures or cold work on the entire coil, but this is expensive and time consuming and can create other problems.
Accordingly, it is a principal object of the present invention to provide a process for joining copper alloy electrical conductors in strip, rod or wire form.
It is a particular object of the present invention to provide a process as aforesaid which provides a joined copper alloy conductor having good strength and conductivity properties.
It is a still further object of the present invention to produce coils of joined copper alloy conductor.
It is also an object of the present invention to provide a process as aforesaid which is convenient and expeditious to practice.
Further objects and advantages of the present invention will appear hereinbelow.


A method of manufacturing a metal separator for a fuel cell includes providing an opening in a metal plate which is to be a part of the metal separator for the fuel cell, integrally molding a sealing member on both sides of an outer peripheral edge of the metal plate to cover the opening, and trimming the sealing member to remove a covering portion of the sealing member that covers the opening and to provide a fluid communication hole, at least one of a fuel gas, an oxidant gas, and a cooling medium being to pass through the fluid communication hole in the fuel cell.

Field of the Invention
The present disclosure relates to a method of manufacturing a metal separator for a fuel cell.
Discussion of the Background
For example, a solid polymer electrolyte membrane formed of a polymer ion exchange membrane is used for a solid polymer electrolyte fuel cell. The fuel cell has a power generation cell in which a membrane electrode assembly (MEA) is sandwiched between separators (bipolar plates), the membrane electrode assembly being formed by disposing an anode-side electrode and a cathode-side electrode including an electrode catalyst and a porous carbon on both sides of the solid polymer electrolyte membrane, respectively. A fuel cell including stacked layers of a plurality of power generation cells is used, for example, as an in-vehicle fuel cell stack.
In the fuel cell, a passage for passing a fuel gas (hereinafter also referred to as a reactant gas) is formed in the surface of the separator that faces the anode-side electrode, while a passage for passing an oxidant gas (hereinafter also referred to as a reactant gas) is formed in the surface of the separator that faces the cathode-side electrode. In addition, a passage for passing a cooling medium between separators is formed for each power generation cell or for a predetermined number of power generation cells.
Thus, it is necessary to securely seal between the passages so that a fuel gas, an oxidant gas, and a cooling medium are not mixed with each other, and also necessary to prevent intrusion of a foreign substance into the passages and a short circuit between the separators. For this reason, a metal separator in which a sealing member is integrally molded on both sides of the outer peripheral edge of a metal plate is used, for example.
For example, as disclosed in Japanese Unexamined Patent Application Publication No. 2002-305006, there is known a fuel cell in which the above type of metal separator is used, and an insulating member is provided around the periphery of each communication hole formed in the separator. Specifically, as illustrated in FIG. 10, a separator 1 and a membrane electrode assembly (not shown) are stacked alternately, and a communication hole 2 is formed in the separator 1 through in the stacking direction, for passing a reactant gas and a cooling medium.
The separator 1 is provided with a metal plate 3 composed of a stainless steel plate material or the like, and a seal member 4 is integrally molded with the metal plate 3. The separator 1 is provided with a circular insulating member 5 which surrounds the communication hole 2.

Method of manufacturing metal separator for fuel cell


Techniques are described for determining that a property is vacant based on monitoring data collected by connected sensors and appliances near or within the property. In response to determining that a property is vacant, the condition of the vacant property can be monitored for various risks such as fire safety and security breaches. Monitoring techniques may also be used to determine when a new customer (e.g., a new tenant or property owner) has moved into the property. In response to detecting a move-in, one or more notifications may be transmitted to assist the new customer to customize a security system associated with the property. In this regard, techniques described herein may be used by service providers to improve the transition associated with move-in and move-out processes, which may also improve retention of monitoring services.

Monitoring service providers offer customers options to provide notifications of move-out dates. For example, a home monitoring service customer may call a monitoring service company to let them know they are moving out of their home in two months and to discontinue billing and services when the customer moves out.

Detection and handling of home owner moving by a home monitoring system


A multilayer wiring base plate includes an insulating plate including a plurality of synthetic resin layers made of an insulating material, a wiring circuit provided in the insulating plate, a thin-film resistor formed along at least one of the synthetic resin layers to be buried in the synthetic resin layer and inserted in the wiring circuit, and a heat expansion and contraction restricting layer formed to be buried in the synthetic resin layer adjacent to the synthetic resin layer in which the thin-film resistor is formed to be buried, arranged along the thin-film resistor, and having a smaller linear expansion coefficient than a linear expansion coefficient of the adjacent synthetic resin layers.

Semiconductor ICs such as semiconductor chips are collectively formed on a semiconductor wafer and undergo an electrical test before being separated into respective chips. For this electrical test, a probe card to be connected to electrode pads of each semiconductor IC as a device under test is used in general. Respective probes of the probe card contact the corresponding electrode pads of the device under test to cause the device under test to be connected to a tester for the electrical test (for example, refer to Patent Literature 1).
In such a probe card, a multilayer wiring base plate is used as a probe base plate, and multiple probes are arranged on one surface of the probe base plate. Also, in a wiring circuit incorporated in this probe base plate or multilayer wiring base plate, an electrical resistor is incorporated for the purpose of electrical matching such as impedance matching or for the purpose of control of supply power to the respective probes (for example, refer to Patent Literature 2).
To incorporate a resistor in such a multilayer wiring base plate, a thin-film resistor is buried and formed in a synthetic resin layer made of an electrical insulating material as a base material for the wiring base plate. This thin-film resistor is made of a metal material having a smaller linear expansion coefficient than a linear expansion coefficient of the aforementioned synthetic resin layer as a base material for the wiring base plate.
Thus, when the aforementioned electrical test of the device under test is performed under heat cycle test conditions, the aforementioned thin-film resistor of the probe card results in receiving relatively large stresses repeatedly at a border with the synthetic resin layer in accordance with a difference in the linear expansion coefficient between the thin-film resistor and the synthetic resin layer to which the thin-film resistor is fixed. Such repeated stresses by the temperature shock promote deterioration of the thin-film resistor and cause breakage.
Citation List
Patent Literature 1: Japanese Patent Appln. Public Disclosure No. 2010-151497
Patent Literature 2: Japanese Patent Appln. Public Disclosure No. 2008-283131

Multilayer wiring base plate and probe card using the same


This invention relates to a self-activated automatic candle snuffer. The device generally comprises a back plate connected to a base and to a spoon having a hole so that the back plate supports the spoon for spring movement with respect to the base. A candle mounted to the base so that the candle passes through the hole in the spoon. A set pin movably affixed to the spoon proximate the hole, operatively arranged to pierce and enter the candle so as to maintain tension in the spoon. A ball balanced on the spoon and a means for release of tension in the spoon which causes release of potential energy that allows the spoon to elevate to an inclined plane to cause the ball to roll down the spoon to settle on the hole and the wick and extinguish a flame.

1. Field of the Invention
This invention relates to candle extinguishing device. More particularly, the invention relates to an non-electric self activated automatic candle extinguishing device which allows a candle to burn for a predetermined amount of time before being snuffed out.
2. Background
Several devices have been invented to automatically extinguish a candle. For example U.S. Pat. No. 4,138,211 issued to Kampfer et al, discloses a thermomechanical candle snuffer utilizing metals with mechanical memory properties. Mechanical memory metals can be deformed into bent shapes which recover their unbent state upon heating above the metals recovery temperature. In this invention, as a candle burns down, it will heat the metal and cause it to return to its unbent state. Utilizing this phenomenon, the invention comprises a clip for securing a snuffing cone to a candle. The length of metal between the clip and the cone is made of the thermomechanical metal with the cone being held away from the burning candle. With recovery of the metal to its unbent state, the snuffing cone is brought over the burning wick causing the flame to be extinguished. This design depends on the clip holding the snuffing cone in the desired position for proper functioning. Thus, the clip must apply sufficient force to the candle so that the clip and snuffer do not slide down the length of the candle negating the desired automatic extinguishing of the flame. The problem with this configuration is that if the clip applies too much force, the candle may be crushed or even broken. Therefore, each candle diameter requires its own clip to function properly. Additionally, another problem is that the melting wax may interfere with the thermomechanical metal causing the metal's recovery to fail or be hindered.
U.S. Pat. No. 5,944,505 issued to Kroecher describes a candle snuffing device having two candles attached at opposite ends of a pivoting balancing arm. Above each candle is a snuffing cone for extinguishing the candle. One candle is lit at a time, and as the wax melts, the burning candle reduces its mass. The counterbalance of the opposite, non-burning candle pivots the balancing arm causing the burning candle to rise toward the snuffing cone. Once enough wax is consumed the candle reaches the snuffing cone and is extinguished automatically. This design, however, requires careful balancing of the arm to function properly. Although the candle is extinguished automatically, there is uncertainty in the burning time of the lit candle due to various sizes and densities of candles. Depending on the candle's burn rate and the mass of the counterbalance, the burning of the candle may be too long or too short for the user's desired timeframe. Also, this design limits the types of candles that can be used—namely tealight or votive, and not tapered, candles.
Byxbe discloses an automatic candle snuffer in U.S. Pat. No. 6,572,365. This device places a candle within a sealed container having an automated closeable lid. The lid is held open with a magnetized hinge mechanism. A user inputs a predetermined time into a timer which is partially attached to the container and partially attached to the lid. When this time is reached, the timer demagnetizes the hinge allowing the lid to close the container. As the oxygen in the container is consumed by the flame, the candle is automatically extinguished. This design suffers various drawbacks, including obstruction of the candle and difficulty in lighting the candle. By placing a box around the candle, the candle and/or candle flame is obstructed by the box, limiting the types of materials which can be used to construct the box. Depending on the height of the box and height of the candle, it may be onerous or even dangerous to try to light the candle using a match or cigarette lighter because a user has to reach into the box to set the wick alight. This reaching may cause the user to be burned by either the match or the candle once lit. Alternatively, the user may light the candle and then place the box over the lit candle. However, if the box does not sit correctly, air will leak into the box and provide sufficient oxygen for the candle to continue burning after the selected extinguishing time. Manipulating the box to ensure a good seal could lead to the lit candle tipping over and becoming extinguished, or increase risk of burning the user or setting something external from the device on fire.
Thus it is readily apparent that there is a need for an automatic candle extinguisher capable of snuffing a candle after a predetermined amount of time. There is a particular need for a candle extinguisher that is decorative and interesting to watch.

Self-activated candle extinguishing device


A non-destructive test system includes a plurality of impact devices including a knob configured to generate at least one flexural mode in a material when a surface of the material is impacted by the knob, a controller configured to independently control each of the plurality of impact devices, the controller having a communications channel for each of the plurality of impact devices, and a microphone configured to detect an acoustic response generated upon impact of the knob on the surface of the material, the acoustic response being based on the at least one flexural modes generated in the material.

Concrete can be used in construction (e.g., roadways, bridges, and buildings) and has other uses in society. Over time, concrete can undergo reductions in strength and/or stiffness and can develop cracks and structural flaws, including but not limited to delaminations. This deterioration can be caused by age, weather, stress, etc. of the concrete. Methods for rapid scanning and identification of some forms of deterioration, including delaminations, are limited, and existing technology may not identify flaws or non-uniformities in concrete in a timely manner.

Multichannel impact response for material characterization


In a semiconductor device and, in particular, a semiconductor memory device in which a channel region formed in a polycrystalline film of a first channel conductivity type insulated gate field effect transistor is divided into a first channel region, which is in contact with a drain region, and a second channel region and the second channel region contains a second conductivity type impurity or a first conductivity type impurity whose density is higher than the impurity density of the first channel region, the threshold voltage can be controlled and the leakage current can be made small.

The present invention relates to a semiconductor device and, in particular, a semiconductor memory device having field effect transistors formed by polycrystalline silicon films.
A MIS transistor (e.g., a metal insulator semiconductor transistor or an insulated gate field effect transistor) using a polycrystalline silicon film which is formed above the surface of the semiconductor substrate is a transistor most suited to a high density integrated circuit device. FIG. 7 shows the sectional view of such a conventional transistor. The MIS transistor is composed of: a first polycrystalline silicon film for forming a source region 3a on a silicon oxide film (SiO.sub.2 film) 2 which, in turn, is on a silicon substrate 1, a channel region 3', and a drain region 3b; a gate insulating film 4 formed on the above referred-to polycrystalline silicon film; and a gate electrode 5 comprising a second polycrystalline silicon film formed on the gate insulating film 4.
In a device of this type, the gate electrode 5 is used as an ion implantation mask, i.e. ions of impurity atoms, such as boron or others, are implanted in the source region 3a and the drain region 3b, and the channel region 3' of the MIS transistor is formed in a self-alignment manner. When the source region, drain region, and channel region are not formed in the self-alignment manner with the gate electrode, the source region, the drain region, and the channel region are formed by limiting the impurity atom ion implantation region using a photoresist or other scheme as an ion implantation mask. The gate electrode is placed above or under the channel region.
A device of this type is described in IEDM. Tech. Dig., December 1983, pp. 202-205.
A semiconductor device having a conventional static random access memory cell has been implemented using the above field effect transistor, which is formed by a polycrystalline silicon film to form a driver transistor, a load transistor, or a transfer transistor. An example of such a semiconductor memory device is disclosed in Japanese Patent Laid-Open 2-14564.
In the above conventional MIS transistor using polycrystalline silicon, the trap level is formed on the grain boundary of the polycrystalline silicon, carriers are trapped on this trap level, and potential barriers are formed. Therefore, it is difficult to control the threshold voltage of the MIS transistor. It is determined that a leakage current flowing between the source and drain regions when the MIS transistor is cut off is caused by a recombination current in a depletion layer which is formed on the above trap level by trapped carriers. This leakage current causes a problem that when the MIS transistor using a polycrystalline silicon film is applied to, for example, a static random access memory cell, the standby power consumption increase extremely.
Furthermore, the experimental study of the inventors of the present invention shows that when ions are implanted in the channel region by the same means as that of the well-known MOS (metal oxide semiconductor) formed on the substrate so as to control the threshold voltage of a MIS transistor having a large amount of such a trap level, there is a phenomenon found that the leakage current between the source and drain regions, which is caused by the electric field at the end of the channel region on the drain region side, increases. This trend grows as the implantation dose in the channel region increases as shown in FIG. 3.
Japanese Patent Laid-Open 62-98665 indicates that an impurity is used as a high resistance load element so as to increase the threshold voltage of a parasitic MISFET.

Semiconductor memory device having a field effect transistor with a channel formed from a polycrystalline silicon film


An epitaxial structure includes a substrate having an epitaxial growth surface, a first epitaxial layer, a graphene layer and a second epitaxial layer. The first epitaxial layer is stacked on the epitaxial growth surface. The graphene layer is coated on the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer and covers the graphene layer.

1. Technical Field
The present disclosure relates to an epitaxial structure and a method for making the same.
2. Description of Related Art
Light emitting devices such as light emitting diodes (LEDs) use group III-V nitride semiconductors, such as gallium nitride (GaN), have been put into practice.
Since wide GaN substrate cannot be produced, the LEDs have been produced upon a heteroepitaxial substrate such as sapphire. The use of sapphire substrate is problematic due to lattice mismatch and thermal expansion mismatch between GaN and the sapphire substrate. One consequence of thermal expansion mismatch is bowing of the GaN/sapphire substrate structure, which leads in turn to cracking and difficulty in fabricating devices with small feature sizes. A method for solving the problem is forming a plurality of grooves on surface of the sapphire substrate by lithography or etching. However, the process of lithography and etching are complex, high cost, and may pollute the sapphire substrate.
What is needed, therefore, is to provide an epitaxial method for solving the problem discussed above.


An air conditioner condensate sump pump controller comprising a self heated PTC resistor located in the sump including an ambient compensation circuit. When the condensate reaches the resistor level due to decreased resistance the sump pump is energized reduce the condensate level.

As is well-known, air conditioners may serve to cool room air, for the purpose of which the air is drawn into the conditioner wherein it passes over a heat exchanger cooled by a refrigerant. Condensation thus forms on the surface of the heat exchanger and drips into a sump. In some arrangements, the condensate simply drains out of the sump, under the influence of gravity, through a pipe but in many cases it is essential or aesthetically desirable to lift the condensate, sometimes several meters, before discharging it to the desired location and it is common practice to use an electric pump for that purpose. Usually, the pump is of the reciprocating type and they are often noisy if air is drawn in. For this reason, it is important that the pump, when of such a type, operates only when the level of water in the sump is between pre-determined levels and so it is necessary to use a water level detection device.
The use of several alternative level detection devices has been proposed including mechanical devices such as magnetic float switches and devices which respond to changes in electrical conductivity. The former suffer from the disadvantage that they can readily become jammed by foreign matter such as metal or other particles or by the growth of biological matter on the moving parts. The latter often malfunction because the electrodes tend to become coated with electrically insulative material such as oil or fat or become permanently bridged by electrically conductive contaminants.
It is an object of the present invention to solve or mitigate the problems by proposing the use of an alternative form of level detection device.


Apparatus for electrostatic clamping of a workpiece, such as a semiconductor wafer, includes a platen assembly defining an electrically-insulating clamping surface for receiving the workpiece. The platen assembly includes electrodes underlying and electrically isolated from the clamping surface and a dielectric layer between the electrodes and the clamping surface. The dielectric layer may have a periphery which is beveled to define a blunt first edge that forms a boundary of the clamping surface and a second edge that is spaced from the workpiece. A thin, low friction, high hardness dielectric coating may be provided over the dielectric layer. The electrodes may be fabricated of niobium. The disclosed electrostatic wafer clamp provides excellent performance with respect to particulate contamination of the workpiece.

In the fabrication of integrated circuits, a number of well-established processes involve the application of ion beams to semiconductor wafers in vacuum. These processes include, for example, ion implantation, ion beam milling and reactive ion etching. In each instance, a beam of ions is generated in a source and is directed with varying degrees of acceleration toward a target wafer. Ion implantation has become a standard technique for introducing conductivity-altering impurities into semiconductor wafers. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded in the crystalline lattice of the semiconductor material to form a region of desired conductivity.
The target mounting site is a critical part of an ion implantation system. The target mounting site is required to firmly clamp a semiconductor wafer in a fixed position for ion implantation and, in most cases, to provide cooling of the wafer. In addition, means must be provided for exchanging wafers after completion of ion implantation. Cooling of wafers is particularly important in commercial semiconductor processing wherein a major objective is to achieve a high throughput in terms of wafers processed per unit time. One way to achieve high throughput is to use a high current ion beam so that the implantation process is completed in a shorter time. However, large amounts of heat are likely to be generated by the high current ion beam. The heat can result in uncontrolled diffusion of impurities beyond prescribed limits in the wafer and in degradation of patterned photoresist layers. It is usually necessary to provide wafer cooling in order to limit the maximum wafer temperature to about 100.degree. C.
A number of techniques for clamping a semiconductor wafer at the target mounting site are known in the art. One known technique involves the use of electrostatic forces. A dielectric layer is positioned between a semiconductor wafer and a conductive support plate. A voltage is applied between the semiconductor wafer and the support plate, and the wafer is clamped against the dielectric layer by electrostatic forces. An electrostatic wafer clamp is disclosed by G. A. Wardly in "Electrostatic Wafer Chuck for Electron Beam Microfabrication", Rev. Sci. Instrum., Vol. 44, No. 10, Oct. 1972, pp. 1506-1509 and in U.S. Pat. No. 3,993,509 issued Nov. 23, 1976 to McGinty. Electrostatic wafer clamp arrangements which utilize a thermally-conductive material to remove heat from the wafer are disclosed in U.S. Pat. No. 4,502,094, issued Feb. 26, 1985 to Lewin et al., U.S. Pat. No. 4,665,463, issued May 12, 1987 to Ward et al., and U.S. Pat. No. 4,184,188, issued Jan. 15, 1980 to Briglia. The Briglia patent discloses a support plate having layers of thermally-conductive, electrically-insulative RTV silicone. Electrostatic wafer clamps are also disclosed in U.S. Pat. No. 4,480,284, issued Oct. 30, 1984 to Tojo et al., U.S. Pat. No. 4,554,611, issued Nov. 19, 1985 to Lewin, U.S. Pat. No. 4,724,510, issued Feb. 9, 1988 to Wicker et al. and U.S. Pat. No. 4,412,133, issued Oct. 25, 1983 to Eckes et al.
U.S. Pat. No. 4,520,421, issued May 28, 1985 to Sakitani et al., discloses a specimen supporting device including a pair of specimen attracting portions each having an electrode on the lower surface of an insulating member. When a voltage is applied between the pair of specimen attracting portions, the specimen is electrostatically attracted to the upper surface. The voltage can be AC or DC. An embodiment having eight arcuate specimen attracting portions with voltages of alternately opposite polarities is disclosed.
U.S. Pat. No. 5,103,367, issued Apr. 7, 1972 to Horowitz et al., discloses an electrostatic chuck for semiconductor wafers having at least three electrodes. Two of the electrodes embedded in a dielectric film are energized by an AC supply to provide sine wave fields of controlled amplitude and phase. The relative phases and amplitudes of the electrode voltages are adjusted to null the voltage induced on the surface of the wafer. In one embodiment, the substrate support surface comprises a thin ceramic layer such as sapphire (Al.sub.2 O.sub.3).
U.S. Pat. No. 5,166,856, issued Nov. 24, 1992 to Liporace et al., discloses an electrostatic chuck including a body of refractory metal sized to support a semiconductor wafer. A first layer of diamond coats the refractory metal body. A pair of generally planar electrodes is disposed on the first layer of diamond. A second layer of diamond conformally coats the electrodes. A DC voltage applied between the electrodes develops an electrostatic force to hold the wafer against the second diamond layer.
Problems associated with prior art electrostatic wafer clamping arrangements include inadequate clamping force, damage to devices on the wafer by charging currents, difficulty in making electrical contact to the semiconductor wafer, and wafer sticking to the platen after the clamping voltage has been removed. In addition, thermal transfer characteristics have usually been inadequate for high current ion implantation applications, since a significant portion of the platen surface area is devoted to making electrical contact with the semiconductor wafer. See, for example, the aforementioned U.S. Pat. No. 4,502,094.
An electrostatic wafer clamp that provides highly satisfactory performance is disclosed in U.S. Pat. No. 4,452,177, issued Sep. 19, 1995 to Frutiger. A six-phase electrostatic wafer clamp includes a platen having six symmetrically located electrodes. Voltages with six different phases are applied to the electrodes, with the voltages applied to electrodes on opposite sides of the platen being one-half cycle out of phase. The applied voltages are preferably bipolar square waves.
As semiconductor device geometries become progressively smaller and wafer sizes become progressively larger, the allowable particulate contamination specifications become more restrictive. The particulate performance of electrostatic wafer clamps is of particular concern because the wafers physically contact the surface of the wafer clamp and because the electrostatic forces which are employed to clamp wafers also attract particles. Accordingly, it is desirable to provide electrostatic wafer clamp configurations wherein particle generation and particulate contamination of wafers are extremely low.

Electrostatic wafer clamp having low particulate contamination of wafers

Varian Semiconductor Equipment Associats, Inc.


An elevation measurement instrument including a support ruler, an optical instrument and a bracket pivotally coupling the optical instrument to the support ruler. The optical instrument includes a first ocular mount having a telescope with a horizontal crosshair and a second ocular mount having a horizontal alignment level device. The bracket couples the optical instrument to the ruler along a horizontally balanced axis. The bracket includes a position indicator colinearly aligned with the horizontal crosshair.

In the field of construction, it is often necessary to ascertain the elevation of a site or of a feature of a building, bridge or any other structure being constructed. When designing a construction project, engineers and architects prepare blueprints indicating the relative elevation of various features, including the elevation of the sub grade, that is, the surface of earth or rock leveled-off to receive a foundation. Accurate elevation measurements are critical to ensure the proper completion of a project.
A common instrument used to measure elevations comprises a single telescopic lens mounted on a tripod base. To measure elevations, the instrument is first placed on a fixed and unalterable position somewhere in the construction site. By adjusting each of the tripod legs, the instrument is calibrated to assure that it is perfectly level with a horizontal plane. One operator then places a reference ruler having spaced measurement marks on top of a reference point of known elevation. The reference ruler may include an adjustable marker. A second operator points the telescope at the measurement ruler and notes or marks the measurement of the ruler, determining the elevation of the horizontal plane of sight of the telescope. Once this horizontal plane of sight is determined, the instrument is swiveled to intersect a vertical axis aligned at a second location of unknown elevation. By having the first operator place the measurement ruler at this second location, the second operator can then note the ruler's measurement and calculate the elevation difference of the second location with respect to the reference point.
Two operators are necessary to operate the tripod telescope instrument, one to operate the tripod-mounted telescope and one to move the measurement ruler along the construction site. If at any time the adjustment on the tripod-mounted telescope is disturbed, either in its alignment to the horizontal plane or on its elevation, an error will occur that will be transferred to all other points in the construction site. Furthermore, the ability of the tripod telescope to measure height differences is limited to the ability to position the ruler within the line of sight of the instrument. Points having heights that differ more than a length of the measurement ruler or are hidden from the line of sight cannot be measured directly.
Other known methods and apparatus for measuring elevations include the use of a laser to triangulate the desired elevation of the site. However, the laser equipment is generally more costly than the traditional telescope. Laser equipment is fragile and complex and may prove to be too expensive for smaller operations. A need remains for a cost-effective apparatus and method for measuring elevations. The desired apparatus would preferably minimize measurement error and allow use by a single operator.