In a method for removing tin from a surface and/or from a region close to the surface of a component part, the component part has a concentrated aqueous sodium hydroxide or concentrated hydrochloric acid flowing in contact with it at a temperature which is distinctly higher than room temperature. Preferably, the temperature is approximately 220.degree. C., and the component part is moreover subjected to a positive pressure of 5.5 bar. The method is suitable for a component part fabricated through the use of unidirectional solidification and liquid-metal cooling, in particular a turbine blade.

Field of the Invention
The invention relates to a method for removing tin from the surface and/or from a region close to the surface of the component part. Furthermore, the invention relates to an application of the method to a component part, in particular a turbine blade.
European Patent Application 0 631 832 A1 describes the fabrication of a component part by unidirectional solidification of a metal melt. That involves filling a mold with an alloy melt which forms the component part, wherein the mold is maintained in a heating chamber at a temperature above the melting temperature of the alloy. The mold containing the molten alloy is introduced continuously into a bath having a cooling fluid, with unidirectional solidification thus being induced. In order to avoid heat currents and to establish a high temperature gradient, the cooling fluid is covered with a thermally insulating layer that is made of free-flowing material, through which the mold is lowered into the cooling fluid.
A possible cooling fluid is molten tin having a temperature of about 260.degree. C., as described in German Published, Non-Prosecuted Patent Application DE 22 42 111 A1. If the mold is cooled through the use of a liquid metal (liquid metal cooling or LMC), there is the possibility that the liquid metal, for example liquid tin, may come into direct contact with the solidified alloy through cracks in the mold. In that case, the tin may adhere to the surface (tin accretion) or form a compound with the alloy in a region close to the surface (tin enrichment). In the course of a heat treatment of the cast component part, which may follow the casting process, there is the possibility of more tin diffusing into the component part. There is a consequent risk of the mechanical properties and the corrosion characteristic of the component part being impaired.
German Published, Non-Prosecuted Patent Application DE 36 04 792 A1 describes a method for the fabrication of tin-free articles by deep-drawing or ironing tin-plated sheet iron. A tin coating on a latten, for example for making tin cans, is removed through the use of a strong alkali such as sodium hydroxide.


A user application is generated in response to user input, wherein the user application is described in a user application description. Processing device code is generated for a targeted processing device based at least in part on the user application description without user intervention, wherein the processing device code includes a system layer, wherein functionality of the system layer is independent of the targeted processing device.

1. Field
Embodiments of the invention relate to the field of processing devices and more specifically, but not exclusively, to providing hardware independence to automate generation of processing device firmware.
2. Background Information
Processing devices, such as microcontrollers, are widely used in the industry as control elements in many solutions. Most microcontrollers are general in purpose, and are designed for use in a wide variety of problem solutions. As microcontrollers become more programmable and more widely applicable, a designer needs more specific device knowledge to use the microcontroller to solve a problem.
In a conventional solution, hardware and software are usually created for a specific microcontroller, and may be redesigned (sometimes completely) following a change in requirements. A common sequence of events is to first determine the system requirements (often incompletely when time is short) to address a problem, then second to determine hardware and software requirements, then third to determine microcontroller and interfacing circuitry requirements, and fourth to find a suitable microcontroller and design suitable interfaces. Finally, the user must manually configure the microcontroller and write device specific firmware, and the user may have to re-write firmware, redesign circuitry, or choose another microcontroller based upon new/changing requirements.
Design changes during this conventional approach may result in costly and inefficient code changes, may cause software and hardware architecture changes and may even require a change in microcontroller and a significant redesign. Such a redesign may be costly and may delay design and production schedules. Also, designing and redesigning conventional microcontrollers may require specialists in a variety of areas including hardware engineering, firmware coding, and system design.

Providing hardware independence to automate code generation of processing device firmware


A hydraulically damped sleeve bearing having two supporting structures which are arranged essentially parallel to a common axis and are connected by a spring member made of a rubber-elastic material. The spring member has at least one liquid-filled chamber pair that is connected through a damping opening and whose chambers are configured at right angles to the axis so that they are opposite to each other. The spring member is furnished with recesses, which are molded during production and are open in the direction of an axial front end, and the recesses are sealed by a subsequently installed lid-locking device. The lid-locking device is connected to one of the supporting structures and is movable relative to the other supporting structure.

FIELD OF THE INVENTION
The present invention relates to a hydraulically damped sleeve bearing having two supporting structures which surround each other and are arranged parallel to a rotation axis. The supporting structures are braced flexibly against each other by means of a spring member made of a rubber-elastic material. The spring member has at least one liquid-filled chamber pair that is connected through a damping opening. The chambers are configured at right angles to the axis so that they are opposite to one another.


Disclosed is a single reel tape cartridge having a supply reel positioned within a central cavity of a shell. The supply reel is coupled to the attachment end of a length of recording tape which is wound in a sequence of wraps from an inner circumference to a maximum outer circumference when the length of recording tape is fully wound on the supply reel. A tape guide and bearing assembly positioned within the central cavity closely adjacent the maximum outer circumference, faces towards an aperture in the shell and away from the supply reel. The tape guide and bearing assembly defines a tape path for the outermost wrap from the supply reel to the tape guide and bearing assembly, across an aperture in the shell for interfacing the outermost wrap with the tape head of the tape drive at the aperture. The tape path then extends to an isolator, e.g. the supply reel, for isolating the tape path at the tape guide and bearing assembly from the free end of the length of recording tape as the free end is wound at a take up reel in the drive. A stable head to tape interface is thus provided at the cartridge tape guide and bearing assembly, which allows a small form factor tape drive having a short tape path to the take up reel.

Conventional single reel cartridges for recording tape comprise a flattened, generally square box-like shell with a single supply reel of recording tape centrally located in the shell. The length of recording tape is attached at one end to the supply reel and the other end is a free end which is attached to a leader block. The leader block is drawn from the cartridge by a tape drive threader which moves the tape through an elongated tape path in the drive, past tape bearings and guides, a tape read/write head, more tape bearings and guides, and to a take up reel.
Typically, the tape winds onto reels in a non-uniform profile which results in lateral tape motion at the head and tape guides when the tape is unwound at typical tape speeds. Thus, tape bearings and guides are required to insure that the tape is stable when it passes the head in order to meet design requirements for data density and performance.
It is desirable to provide high capacity and high performance tape drives. One means of increasing capacity is to reduce the thickness of the recording tape to permit a greater length of tape to be stored in a tape cartridge, but this leads to increased susceptibility to vibration and decreased stability of the tape, and requires a more stable tape path. As described in U.S. Pat. No. 5,155,639, Platter et al., care must be taken to develop a proper tape path between the supply and take up reels, and across the tape read/write head, to assure proper registration of the tape with the tape head. As the result, conventional tape paths are long and cumbersome and expensive. It is also desirable to reduce the size of the tape drive while retaining stability of the tape. The '639 patent reduced the size of the tape drive to an 8 inch form factor by employing an improved tape threading mechanism and an improved take up reel in the drive.
It is also desirable to provide such tape drives in even smaller form factors. To do so, requires a smaller tape path.

Single reel tape cartridge with integral tape guide

International Business Machines Corporation


An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

1. Field of the Invention
The present invention is related to a field programmable gate array (FPGA) having embedded static random access memory for the embedded SRAM, and the connection of the SRAM bus architecture to the general interconnect architecture of the FPGA.
2. The Prior Art
As integrated circuit technology advances, geometries shrink, performance improves, and densities increase. This trend makes the design of systems of ever increasing complexity at ever decreasing cost feasible. This is especially true in logic products such as Application Specific Integrated Circuits (ASICs), Complex Programmable Logic Devices (CPLDs), and Field Programmable Gate Arrays (FPGAs).
The need for integrating fast, flexible, inexpensive memory into these logic products to provide memory for a variety of purposes such as register files, FIFOs, scratch pads, look-up tables, etc. has become more apparent, because there are significant cost and performance savings to be obtained by integrating this functionality directly into, for example, an FPGA. However, providing this memory by having other than explicitly dedicated SRAM blocks included in the FPGA has not proved satisfactory. Typically, the implementation of memory without dedicated SRAM blocks in an FPGA has been done by either providing external SRAM to the FPGA or by using the logic modules, flip-flops and interconnect of the FPGA. Both of these solutions are less than satisfactory.
Using external SRAMs with FPGA designs is undesirable for several reasons. Separate memory chips are expensive, require additional printed circuit board space, and consume I/O pins on the FPGA itself. Also, a separate memory chip is required to implement each memory function, thereby further increasing the cost.
When SRAM is implemented with the logic modules in the FPGA, it requires a substantial amount of the routing and logic resources of the FPGA, because the available logic blocks are implemented as gates and latches and the programmable interconnect is employed to connect them. This substantially degrades both the performance and flexibility of the FPGA by consuming a considerable amount of logic array resources, and imposes critical paths that are quite long for even a small memory block.
Xilinx offers the capability of using the configurable logic blocks on their 4000 Series of parts as 16xc3x971 SRAM blocks, but requires the use of normal interconnect to combine the blocks into larger memory configurations. While this distributed SRAM approach is an improvement in density and is flexible for building larger memories, it is still slow and consumes logic array resources. The necessary overhead circuitry was sufficiently large that Xilinx actually removed it when they developed their low cost 4000-D parts. On their 4000-E Series parts, they offer the ability to configure two configurable logic blocks to emulate a dual ported 16xc3x971 SRAM block, however, this design still carries with it performance and flexibility degradation.
Altera has also attempted to improve on the connection of the SRAM blocks in their embedded array blocks for their 10K FLEX parts. They include one or more columns on their larger parts of embedded array blocks which are size matched to their logic array blocks. The embedded array blocks contain 2K bits of single ported SRAM configurable as 256xc3x978, 512xc3x974, 1024xc3x972, or 2048xc3x971. This approach builds the flexibility of different widths and depths into the SRAM block, but at a significant performance cost since the access time of an embedded array block is very slow for a memory of the size and the technology in which it is built. Further, array routing resources are required for memory configurations other than those indicated.
Another approach to SRAM memory in FPGA applications is found in xe2x80x9cArchitecture of Centralized Field-Configurable Memoryxe2x80x9d, Steven J. E. Wilton, et. al., from the minutes of the 1995 FPGA Symposium, p. 97. This approach involves a large centralized memory which can be incorporated into an FPGA. The centralized memory comprises several SRAM arrays which have programmable local routing interconnect which are used exclusively by the centralized memory block. The local routing interconnects are used to make efficient the configuration of the SRAMs within the centralized memory block. However, the local interconnect structure disclosed in Wilton suffers performance problems due to excessive flexibility in the interconnect architecture.
Actel""s 3200 DX family of parts attempted an intermediate approach by including columns of dual ported SRAM blocks with 256 bits which are configurable as either 32xc3x978 or 64xc3x974. These blocks are distributed over several rows of logic modules to match the density of I/O signals to the SRAM block to that of the surrounding FPGA array. Polarity control circuits were added to the block enable signals to facilitate use as higher address bits. This architecture was designed to provide high performance and reasonable flexibility, with density approaching the inherent SRAM density of the semiconductor process, and routing density comparable to the rest of the logic array. Unfortunately, this approach required array routing resources to interconnect SRAM blocks into deeper and wider configurations.
One of the desirable attributes of user-assignable SRAM blocks in an FPGA architecture is the ability to connect the SRAM blocks to one another to form memories that are either wider (i.e. longer word length) or are deeper (i.e. more words). In connecting SRAM blocks into deeper and wider configurations it must be appreciated that the addresses have to go to each of the SRAM blocks, the write data has to go to each of the SRAM blocks, and the data must be able to be read from all of the SRAM blocks. In addition, the control signals used by the SRAM blocks to read and write data must also be routed to each of the SRAM blocks.
Since routing resources must be used to connect the dedicated SRAM blocks to one another to create either wider or deeper memories, and given that routing resources are not unlimited, preventing a degradation in the performance of the FPGA by efficiently forming deeper and wider memories is an important concern. In preventing a degradation of the FPGA performance, the connection to the user of SRAM blocks to provide deeper and wider memory configurations should not substantially impact the place and route algorithms of the FPGA, nor prevent the use of place and route algorithms for connecting the logic in the FPGA. Several approaches are known in the art for configuring dedicated SRAM blocks to provide deeper and wider memories.
The difficulty in creating deeper and wider SRAM block configurations in the prior art has been that array routing resources have been required to interconnect the SRAM blocks into these configurations. Part of the problem has been that the array routing resources have not been used very efficiently. In certain instances, this was due to the fact that the devices to which the SRAM blocks have been added were not originally designed with embedded SRAM blocks, rather the SRAM blocks have been inserted as an add-on piece.
These problems are better illustrated with reference to FIGS. 1 and 2. In FIG. 1, four 256xc3x978 SRAM blocks are connected into a deeper configuration or essentially a 1024xc3x978 memory. In this configuration it can be seen that the lower order write address bits must be supplied to each of the 256xc3x978 SRAM blocks along with the write data. Additionally, logic must be implemented to provide a 2 to 4 decode of the two higher order address bits used to select the one of four 256xc3x978 SRAM blocks to which the data will actually be written. To read data from the SRAM blocks in this deeper configuration, the lower order read address bits must be supplied to each of the 256xc3x978 SRAM blocks, and then additional logic must be implemented to provide a 4 to 1 multiplexer so that the correct data may be selected from the 1 of 4 SRAM blocks from which data is being output.
In FIG. 2, four 256xc3x978 SRAM blocks are configured in a wider configuration to provide a 256xc3x9732 SRAM block. In this configuration, the write address must be supplied to each of the 256xc3x978 blocks to perform a write operation, and to perform a read operation the read address must also be supplied to each of the 256xc3x978 blocks. The write data must be routed so that the first 8 bits of the data at a particular address location is supplied to a first 256xc3x978 SRAM block, the next 8 bits of the data at that particular address location is supplied to a second 256xc3x978 SRAM block, and the third and fourth 8 bits of data at the same address are supplied to a third and fourth SRAM block, respectively. For a data read, the output of the SRAM blocks must be connected so that the correct 8 bits are taken from each of the four 256xc3x978 SRAM blocks to form a single 32 bit word.
Clearly there is a need for a flexible SRAM bus architecture in an FPGA for embedding user-assignable SRAM blocks into the FPGA. The SRAM bus architecture of the present invention provides routing resources for efficiently using individual SRAM blocks or for connecting multiple blocks of user SRAM to make wider and/or deeper memory configurations. The SRAM bus architecture of the present invention is implemented with minimal use of the routing resources of the array, and with a minimal degradation in the performance of the FPGA.
According to the present invention, an SRAM bus architecture is disclosed that is suitable for use with a plurality of embedded SRAM blocks in an FPGA. The SRAM bus architecture is employed to connect the SRAM blocks in a group together into deeper and wider configurations without employing the general interconnect architecture resources of the FPGA, and to connect the SRAM blocks to the logic modules in an FPGA
The SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to the routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture. This aspect of the present invention, increases the efficiency of the place and route of the FPGA.
The SRAM blocks are dual ported (simultaneous read/write), and include an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core. Each SRAM block contains circuits in both the read port and the write port that together with the SRAM bus architecture permit the SRAM blocks to be connected into deeper and wider configurations by without any additional logic as required by the prior art.
In the preferred embodiment, there eight fully independent blocks of 2K bit SRAM blocks, wherein each SRAM block is organized as 256 words of 8 bits each. The eight SRAM blocks are further divided into two groups such that the SRAM blocks in each of the groups are substantially contiguous to the extent that the address busses, data busses, and control signal lines of each of the user-configurable SRAM blocks in a group can be commonly connected by user-programmable elements at their edges to facilitate directly combining the user-configurable SRAM blocks in a group into wider and/or deeper user-assignable memory configurations.

SRAM bus architecture and interconnect to an FPGA


The present invention relates to aqueous dispersions comprising multistage-prepared polymers of olefinically unsaturated compounds and to the preparation and use thereof, in particular in the field of automobile coating.

Known from the prior art are polymers which can be used as binders for automotive finishing. A binder of this kind is required to fulfill a multiplicity of properties. It must, for instance, be capable of being used in modern multicoat paint systems of the kind employed in the automobile industry.
The prior art (cf., e.g., German patent application DE 199 48 004 A1, page 17, line 37 to page 19, line 22, or German patent DE 100 43 405 C1, column 3, paragraph [0018], and column 8, paragraph [0052] to column 9, paragraph [0057], in conjunction with column 6, paragraph [0039] to column 8, paragraph [0050]) has disclosed the following process, in which
(1) a pigmented aqueous basecoat material is applied to a substrate,
(2) a polymer film is formed from the coating material applied in stage (1),
(3) a clearcoat material is applied to the resulting basecoat film, and subsequently
(4) the basecoat film is cured together with the clearcoat film,
to give a multicoat paint system.
This process is widely employed, for example, not only for the OEM (original) finishing of automobiles but also for the painting of ancillary components made from metal and plastic.
The resulting multicoat paint system is required to fulfill a multiplicity of properties.
Where coating defects occur, the vehicle bodies are coated a second time with the basecoat and clearcoat materials by the aforementioned process. In this coating procedure, in OEM automotive refinishing, the coating material used may be the same as for the first coating. Also possible, however, is the use of a clearcoat material which cures not at high temperatures (around 140° C.) but instead at much lower temperatures (about 80° C.). The resultant paint system must meet the high demands of the automobile industry for appearance and stability; the adhesion between the original finish and the basecoat material used in the refinishing operation may present particular difficulties.
A polymer which has been known in the prior art for many years, and which even now has retained high relevance as a binder in automotive OEM finishing, is a polyurethane which is known from WO 92/15405. This binder is used with the aim of improving the refinish adhesion, and can therefore serve as a reference for adhesion properties.
In Korea Polymer Journal (Korea Polym. J., vol. 7, no. 4, pp. 213-222) Hong, Kim, Kim and Park describe polymers of multistage construction for use as binders in metallic finishes. These polymers are produced via an operation in which the first stage of the polymer is prepared by a batch operation and the second and third stages are each carried out as starved feed polymerizations.

Aqueous dispersions containing polymerizates produced in multiple stages and coating agent compositions containing same


A system and method for vertical handoff between different types of wireless networks. A network allocation vector of a first wireless network is sampled for a period of time. The network allocation vector may include a transmission time advertised by a sender in the first wireless network. A network allocation vector occupation is calculated. The calculation of the network allocation vector may include calculating a ratio of an amount of time that the network allocation vector is busy during the time period to a total amount of time during the time period. A wireless network quality of service measure is calculated as a function of the network allocation vector occupation. A vertical handoff may be initiated from a second wireless network to the first wireless network based at least in part on the calculated wireless network quality of service measure.

Today, people use digital networks to communicate in many different ways. Speech, text, World Wide Web pages and streaming live video are just a few examples. The ability to connect to a digital network at a particular physical location is one thing. The ability to connect to a digital network while remaining mobile is quite another. Wireless digital networks are popular and becoming more so. People value the convenience and freedom offered by a wireless network.
Radio is the base technology underlying most wireless digital networks. Each wireless network base station or access point, and each mobile device capable of communicating with the access point, is able to both transmit and receive radio signals. The radio signals are encoded with wireless network data.
It is in the nature of radio signals that signal strength fades with increasing distance from a transmitter. Each wireless network is designed to operate in a certain range of signal strengths, so that when the signal strength drops below a certain point, the quality of service provided by the wireless network drops dramatically. The geographical area served by a single wireless network access point is a wireless network cell. A wireless network provides service to larger geographical areas by dividing the larger area into cells, each with an access point. As a mobile communications device moves through the cells, it communicates with each cell's access point in turn.
One of the traditional problems for wireless network designers is deciding when a mobile device should handoff communications from one wireless network access point to another. The decrease in the quality of service provided to a mobile device by a wireless network access point is nonlinear, particularly near cell boundaries, and the radio environment is dynamic, so that analysis of the problem is not trivial. In practice, most horizontal handoff algorithms rely on a comparison of the relative signal strengths from candidate access points. A horizontal handoff is a communications handoff that occurs between wireless network access points of the same type within a single type of wireless network.
There are many different types of wireless network, each designed to meet different goals. For example, wireless networks complying with standards such as the General Packet Radio Service (GPRS) and Code Division Multiple Access (CDMA) are designed to provide a relatively low level of digital communications bandwidth (e.g., 64 kbps) over a wide geographical area (e.g., a metropolitan area), whereas wireless networks complying with other standards, such as the Institute of Electrical and Electronics Engineers' (IEEE) 802.11 series of standards and the European Telecom Standards Institute's (ETSI) High Performance Radio Local Area Network (HIPERLAN) series of standards, are designed to provide a relatively high level of digital communications bandwidth (e.g., 10 Mbps) but over a much smaller geographical area (e.g., a building or campus). These examples illustrate one set of wireless network design tradeoffs, i.e., bandwidth versus cell size. Other design considerations include how the radio spectrum allocated to each network will be shared among its users as well as user authentication and privacy measures.
Many geographical locations are served by multiple wireless network types, for example, CDMA and IEEE 802.11b. It is desirable for a wireless network user to be able to take advantage of the best features of each network type, for example, to be able to take advantage of a CDMA wireless network's wide service area and also to be able to take advantage of an IEEE 802.11b wireless network's high bandwidth where service is available. It is possible for a wireless network user to manually switch between wireless network types but it is further desirable that vertical handoff, i.e., handoff between different types of wireless network, become as transparent to a wireless network user as horizontal handoff within a wireless network is today. A future is envisioned in which a wireless network user is able to roam seamlessly between network types according to the wireless network user's needs, but there are several problems that need to be solved in order for that future to be realized.
Wireless network standards such as CDMA and IEEE 802.11b, are generally incompatible and are not focused on supporting vertical handoffs. Signal strengths in different wireless networks are not directly comparable. A level of signal strength that provides a good quality of service in one wireless network may result in a poor quality of service in another. New handoff decision criteria are required. Some prior art (e.g., Optimization Scheme for Mobile Users Performing Vertical Handoffs between IEEE 802.11 and GPRS/EDGE networks, Ylianttila et al.) discusses the use of quality of service criteria, such as bandwidth, for making vertical handoff decisions but it is generally silent on how to obtain quality of service measures in practice. There is a need in the art for a practical system and method to implement seamless vertical handoffs between wireless network types.
The invention provides such a system and method. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.

This patent is subject to a terminal disclaimer.

Vertical roaming in wireless networks through improved quality of service measures


A wireless network may comprise a plurality of base stations and a plurality of access points, such as femtocells, which may be installed in homes and/or offices, as deemed necessary to provide improved signal quality and increased data throughput while off-loading capacity from one or more near-by base stations. A user device may be configured to detect proximity to an access point and establish communications preferentially with the access point while refraining from communicating with a base station even though the user device is within a service region of the base station and can communicate with that base station.

Wireless communications systems and methods are increasingly being used for voice, data and/or multimedia communications. As the use of such systems/methods continues to increase, available bandwidths may limit an ability to effectively transmit voice/data/multimedia content. Accordingly, access points other than base stations (e.g., femtocells) are increasingly being used to provide additional capacity and relieve base station load.

Systems/methods of preferential communications


A method for determining a gesture includes determining a change in a background of an image from a plurality of images, determining a object in the image, determining a trajectory of the object through the plurality of images, and classifying a gesture according to the trajectory of the object.

1. Field of the Invention
The present invention relates to computer interfaces, and more particularly to a real-time gesture interface for use in medical visualization workstations.
2. Discussion of the Prior Art
In many environments, traditional hands-on user interfaces, for example, a mouse and keyboard, for interacting with a computer are not practical. One example of such an environment is an operating theater (OT) where there is a need for strict sterility. A surgeon, and everything coming into contact with his/her hands must be sterile. Therefore, the mouse and keyboard may be excluded from consideration as an interface because they may not be sterilized.
A computer may be used in the OT for medical imaging. The interaction can include commands to display different images, scrolling through a set of two-dimensional (2D) images, changing imaging parameters (window/level), etc. With advances in technology, there is a growing demand for three-dimensional (3D) visualizations. The interaction and manipulation of 3D models is intrinsically more complicated than for 2D models even if a mouse and keyboard can be used, because the commands may not be intuitive when working in 3D. Examples of commands in a 3D medical data visualization environment include rotations and translations including zoom.
Areas of human-machine interaction in the OT include, for example, voice recognition and gesture recognition. There are several commercial voice recognition systems available. In the context of the OT, their advantage is that the surgeon can continue an activity, for example, a suture, while commanding the imaging system. However, the disadvantage is that the surgeon needs to mentally translate geometric information into language: e.g., "turn right", "zoom in", "stop". These commands need to include some type of qualitative information. Therefore, it can be complicated and tiresome to achieve a specific 3D orientation. Other problems related to voice recognition are that it may fail in a noisy environment, and the system may need to be trained to each user.
Researchers have attempted to develop systems that can provide a natural, intuitive human-machine interface. Efforts have been focused on the development of interfaces without mouse or device based interactions. In the OT, the need for sterility warrants the use of novel schemes for human-machine interfaces for the doctor to issue commands to a medical imaging workstation.
Gesture recognition includes two sequential tasks, feature detection/extraction and pattern recognition/classification. A review of visual interpretation of hand gestures can be found in V. I. Pavlovic, R. Sharma, and T. S. Huang, "Visual interpretation of hand gestures for human-computer interaction, A Review", IEEE Transactions on Pattern Analysis and Machine Intelligence, 19(7):677–695,July 1997.
For feature detection/extraction, applications may use color to detect human skin. An advantage of a color-based technique is real-time performance. However, the variability of skin color in varying lighting conditions can lead to false detection. Some applications use motion to localize the gesture. A drawback of a motion cue approach is that assumptions may be needed to make the system operable, e.g., a stationary background and one active gesturer. Other methods, such as using data-gloves/sensors to collect 3D data, may not be suitable for a human-machine interface because they are not natural.
For pattern recognition and classification, several techniques have been proposed. Hidden Markov Model (HMM) is one method. HMM can be used for, for example, the recognition of American Sign Language (ASL). One approach uses motion-energy images (MEI) and motion-history images (MHI) to recognize gestural actions. Computational simplicity is the main advantage of such a temporal template approach. However, motion of unrelated objects may be present in MHI.
Neural networks are another tool used for recognition. In particular, a time-delay neural network (TDNN) has demonstrated the capability to classify spatio-temporal signals. TDNN can also be used for hand gesture recognition. However, TDNN may not be suitable for some environments such as an OT, wherein the background can include elements contributing to clutter.
Therefore, a need exists for a system and method for a real-time interface for medical workstations.


The invention provides CVD-based methods for growing single-walled or multi-walled carbon nanotubes. In the methods of the invention, the nanotube growth environment is separated from the carbon-containing gas feed environment using a membrane which is substantially impermeable to gas flow but permits diffusion of carbon through the membrane. A catalyst for carbon nanotube growth is located on the growth side of the membrane while a catalyst for decomposition of carbon-containing gas is located on the feed side of the membrane. A path for diffusion of carbon through the membrane is provided between the growth and decomposition catalysts. Control of the size and shape of the carbon nanotube growth catalyst enables control over the nanotube structure formed.

This invention is in the field of carbon nanomaterials, in particular, methods for making carbon nanotubes and carbon nanotube fibers.
The term "carbon nanomaterials" is used generally herein to refer to any substantially carbon material containing six-membered rings that exhibits curving of the graphite planes, sometimes by including five-membered and/or seven membered rings amongst the hexagons formed by the positions of the carbon atoms, and has at least one dimension on the order of nanometers. Examples of carbon nanomaterials include, but are not limited to, fullerenes, single-walled carbon nanotubes (SWNTs), double-walled carbon nanotubes, multiple-walled carbon nanotubes (MWNTs), nanotubules, and nested carbon structures with dimensions on the order of nanometers.
Different carbon nanomaterials have different potential applications. Nanotube materials can exhibit extraordinary mechanical, thermal, electrical and/or chemical properties, which have stimulated substantial interest in developing applied technologies exploiting these properties. These technologies include, but are not limited to, advanced small-scale circuitry, body and vehicle armor, drug delivery, high-efficiency conductors, nanocomposite materials, medical applications, automobile and aircraft frames, heat transfer and large scale structures (such as very long single-span suspension bridges and the space elevator).
For example, nanotubes can have very high Young's modulus values. Multi-walled carbon nanotubes have been measured to have Young's modulus values between 0.1 and 1.33 TPa, with the Young's modulus being dependent upon the degree of order within the tube walls (Demczyk et al., 2002, Mater. Sci. and Engr. 1334, 173-178; Salvetat et al., 1999, Appl. Phys. A 69, 255-260). While the art recognizes significant potential for commercial application of carbon nanomaterials, the high cost and difficulty in obtaining these materials in the large amounts necessary for developing these applications has been a major impediment in practical application of these materials, although significant breakthroughs in manufacturing technique allow for kg quantities of short (<100 microns) multi-walled tubes to be made available in today's market.
Carbon nanotubes (CNTs) have been grown by chemical vapor deposition (CVD) methods. The carbon nanotube can be grown on a cluster containing metal atoms which serves as both a base and a catalyst for the high temperature decomposition of a carbon-containing material such as acetylene, ethylene, methane, carbon monoxide, etc. The clusters may be supported on a substrate such as alumina or silica or introduced into the feedstock to make vapor-grown carbon fibers. The clusters may be metal clusters or clusters which combine a metal with another element (e.g. oxides).
As described by Moisala et al. (Moisaal, A. et al., 2003, J. Phys. Condens. Matter 15 S3011-S3035), basic steps in the growth process for single walled nanotubes include catalytic decomposition of the carbon precursor molecules on the surface of the metal-containing catalyst particles followed by diffusion of the carbon atoms into the particles. Supersaturation of carbon in the metal results in solid carbon precipitation from the particles. The physical form of the precipitated carbon depends on several parameters, including catalyst particle size and precipitation rate. The growth mechanism is generally classified as either root growth (also called base growth) and tip growth. In base growth, the catalyst particle stays pinned at the support surface. The tip growth mechanism takes place when the catalyst is lifted off from the support surface due to weak support-catalyst interaction.
The size of the metal-containing cluster can influence the nanotube structure. U.S. Pat. No. 6,692,717 to Smalley et al. reports that metal clusters in the range of 0.5 to 3 nm will produce single-wall nanotubes while larger clusters tend to produce multi-wall nanotubes with outer diameters greater than about 3 nm. Molecular dynamics calculations show that larger metal clusters, which contain at least 20 iron atoms, nucleate SWNTS that have a far better tubular structure than SWNTs nucleated from smaller clusters (Feng D., A. Rosen, and K. Bolton, 2004, J. of Chem. Phys., 121, 2775-2779).
Aligned arrays of single-walled nanotubes have been reported in the scientific literature. Hata et al. report water-assisted catalytic growth of aligned single-walled nanotube "forests" (Hata, K., et al, 2004, Science, 306, 1362-1363). Millimeter-scale nanotube lengths were reported for a growth time of ten minutes. In such a dense nanotube forest, the rate at which the free carbons reach the catalyst may decrease due to mass transport limitations.
Aligned arrays of multi-walled carbon nanotubes have also been reported. Aligned arrays of multi-walled carbon nanotubes have been grown on nickel-coated glass (Zen, R. F. et al., 1998, Science, 282(5391), 1105-1107). For applications requiring good alignment, nanotube diameters greater than 50 nm were recommended. Lengths from 0.1 to 50 microns were reported. Aligned multi-walled carbon nanotubes have also been grown using iron nanoparticles embedded in mesoporous silica (Li, W. S. et al., 1996, Science, 274(5293), 1701-1703). The carbon nanotubes were reported to have diameters of about 30 nm, with spacing between the tubes of about 100 nm and lengths up to 50 microns. Furthermore, aligned multi-walled carbon nanotubes have been grown using oxidized patterned iron films on oxidized nanoporous silicon (Fan, S. et al., 1999, Science, 283(5401), 512-514). Typical nanotube diameters were reported as about 16 nm, with lengths between about 35 and 240 microns.
Furthermore, Japanese Patent Application Publication Number 2004-292310 describes growth of nanotubes by passage of synthesis gas through a nano-porous substrate, where the pore size of the substrate is not larger than the diameter of the nanotube. A catalyst metal is included within the pores or may be vapor-deposited on the substrate.
When carbon nanotubes are grown in an environment of carbon-containing materials, decomposition of the carbon-containing material can cause other carbon structures, such as turbostratic graphite and amorphous carbons, to grow. These other structures can cause inactivation of the catalyst (U.S. Pat. No. 6,692,717). A variety of techniques have been used to reduce the amount of the other structures formed. Hata et al. (ibid) report that including water vapor in the growth atmosphere leads to nanotubes free from amorphous carbon and metal particles. U.S. Patent Application Publication No. 2002/0172767, to Grigorian et al. reports that growth in the temperature range from about 760° C. to about 800° C. limits the formation of amorphous carbon.
A number of laboratories have reported "spinning" mixed-length carbon nanotubes into fibers in much the same way as cotton or wool fibers are spun into thread and yarn. Coagulation-based carbon nanotube spinning has been used to make fibers from single-walled nanotubes (Dalton, A. B. et al., 2003, Nature, 423, 703). The tensile strength of these composite fibers was reported as 1.8 GPa. Spinning by winding a nanotube aerogel onto a rotating rod was reported by Li et al. (Li, Y.-L., et al., 2004, Science, 304(5668), 276-278). The fibers were reported to have a range of strengths between 0.05 N/Tex and 0.5 N/Tex (estimated to be equivalent to about 0.10 and 1.0 GPa). Spinning has also been achieved by drawing carbon nanotubes from a multi-walled nanotube "forest" (Jian, K. et al., 2002, Nature, 419, 801; Zhang, M., et al., 2004, Science, 306, 1358-1361). Zhang et al. (ibid.) report formation of single ply, two-ply, four-ply, knitted, and knotted multi-walled nanotube yarns. Tensile strengths were reported as 150 and 300 MPa for the single ply yarns and between about 250 and 460 MPa for the two-ply yarns.
There remains a need for improved methods for producing long aligned nanotubes by catalytic decomposition of carbon-containing gases. These nanotubes can be used to make nanotube fibers, twine or braid. Because of their length, these nanotubes may also be used in applications that do not require that they be combined into such grouped strands.

Membrane separation of feed and growth environments in carbon nanostructure growth


The present invention prevents a moiré generated by the interference of two liquid crystal display panels in a display device capable of performing a three-dimensional display using two liquid crystal display panels. By arranging an upper lens array and a lower lens array between an upper liquid crystal display panel and a lower liquid crystal display panel, a moiré and smearing of an image can be prevented. Due to such a constitution, lowering of brightness and contrast can be suppressed.

1. Field of the Invention
The present invention relates to a display device, and more particularly to a device which acquires a three-dimensional image using two liquid crystal panels.
2. Description of the Related Art
As one of methods for displaying a three-dimensional image, there has been known a technique in which two transmissive display panels are arranged with a distance therebetween, similar images are formed on two transmissive display panels, and a depth feeling is generated by controlling brightnesses of two images thus forming a three-dimensional image. As a document which discloses such a method, "patent document 1 (JP-A-2001-54144)" may be named. A typical example of the transmissive display device is a liquid crystal display panel.
In the liquid crystal display panel, a large number of scanning lines and a large number of video signal lines are arranged in an intersecting manner. Further, pixels are formed at portions surrounded by the scanning lines and the video signal lines. Accordingly, to look at a screen in a microscopic manner, bright portions and dark portions are regularly generated. When images are formed by overlapping two liquid crystal display panels with a distance therebetween, the dark portions and the bright portions formed regularly on the respective liquid crystal display panels generate interference thus causing a so-called moiré. To cope with the moiré generated in the above-mentioned constitution, a technique which arranges a layer for diffusing light between two liquid crystal panels is described in "patent document 2 (Japanese Patent 3335998 (corresponding to U.S. Pat. No. 6,906,762))".


A DRAM cell structure having charge amplification is disclosed. The DRAM cell has a capacitor to store an electrical charge. The DRAM cell further has a MOS transistor. The gate of the MOS transistor is coupled to a word line control to activate and deactivate the MOS transistor. The drain MOS transistor is coupled to one plate of the capacitor. The DRAM cell has a bipolar transistor to amplify the electrical charge stored on the capacitor. The bipolar transistor has a base that is the source for the MOS transistor. The base of the bipolar transistors is formed by masking and implanting a material of the first conductivity type adjacent to the gate to form the base. The collector of the bipolar transistor is the semiconductor substrate. The bipolar transistor has an emitter coupled to a bit-lines control which when activated will sense the charge amplified by the bipolar transistor. The emitter is formed by masking and implanting a material of the second conductivity type within the material of the first conductivity type. The emitter is implanted to ensure a large overlap of the gate of the emitter. The overlap of the gate of the emitter will ensure generation of gate induced drain leakage current to discharge the storage capacitor during writing of a logical "0" to the storage capacitor.

1. Field of the Invention
This invention relates to the dynamic random access memories (DRAM) and more particularly to the structures and methods of fabrication of DRAM's with charge amplification.
2. Description of Related Art
The fabrication and structure of DRAM cells and DRAM array are well known in the art. Typical cell structures for high density DRAM in prior art is composed of one transistor M1 10 for switching charges and one storage capacitor C 15 for storing charges as illustrated in FIG. 1a. The transistor M1 10 will be an n-MOS transistor fabricated in a triple well as shown in FIG. 1b. A deep N-well 35 will be formed in a p-type substrate 30. The area for the deep n-well 35 will be formed as openings during the formation of the insulation are by the local oxidation of the silicon substrate (LOCOS) 45. Within the deep n-well 35 a shallower p-well well 40 will be formed. The gate 60 of the n-MOS transistor M1 10 will be formed as a conductive material such as polysilicon placed over an insulating gate oxide 55 to define the channel area that will between the drain 50 and source 80 of the n-MOS transistor M1 10.
The capacitor C 15 is formed by placing a conductive metal connected to the substrate biasing voltage source V.sub.ss 75 on a dielectric 70 placed over the N.sup.+ drain 80 of the transistor M1 10. The capacitor C 15 as shown is diagrammatic. The particular structure of the capacitor C 15 is well known and shown in "The Evolution Of DRAM Cell Technology" by B. El-Kareh et al., Solid State Technology, May 1997, pp. 89-101. In order to maintain the minimum storage capacitance of 30-40 fF of a cell, the structure of the DRAM cell results in complex semiconductor processing to develop these structures.
A corresponding DRAM cell using p-MOS transistor can certainly be used with polarity and operation bias reversed accordingly.
The deep n-well 35 is typically biased to the power supply voltage source V.sub.cc (i.e. the highest potential on chip) and the p-well is biased to substrate biasing voltage source V.sub.ss 75 (i.e. the lowest voltage on chip). The substrate biasing voltage source V.sub.ss 75 may be biased below ground (i.e. negative potential) so that the leakage current through the pass transistor M.sub.1 10 is reduced. The presence of charge in the storage capacitor C 15 indicates a logical "1" and its absence of charge indicates a logical "0". The storage capacitor C 15 is connected to n+drain 80 of the transistor M.sub.1 10, and the other n+ source 50 of the transistor M.sub.1 10 is connected to bit-line V.sub.bit 25 that controls the reading and writing of the DRAM cell. The gate of the MOS transistor M1 10 is connected to the word line V.sub.word to control the selection of the DRAM cell.
The DRAM cells Cell 11 200, Cell 12 205, Cell 21 210, Cell 22 215 are arranged in arrays of rows (word-lines WL0, WL1, WL2, and WL3,) and columns (bit-lines or BL0 and BL1) as shown in FIG. 2. One popular DRAM array is the folded bit-line architecture. Each pair of bit-lines BL0 and BL1 is connected to one sense amplifier 220 where one Bit-lines BL0 or BL1 serves as reference bias and the other BIT-LINES BL0 or BL1 serves as bit-line sensing during read operation. During write operation, the bit-line BL0 and BL1 is charged to either V.sub.cc to write a logical "1" or V.sub.ss to write a logical "0". The selected word-line WL0, WL1, WL2, or WL3 is charged to V.sub.cc so that all transistors connected to the same row turn on and the capacitor of each cell are charged to V.sub.cc or V.sub.ss representing information of "1" and "0" respectively. Before read operation starts, the bit-lines BL0 and BL1 are precharged to a voltage V.sub.cc /2. To start reading a cell, the selected word-line WL0, WL1, WL2, or WL3 is raised to V.sub.cc, turning on all transistors connected to the word-line WL0, WL1, WL2, or WL3. Each sense amplifier 220 detects the polarity of charge stored on capacitor C with respect to the reference Bit-lines BL0 and BL1 voltage (i.e. V.sub.cc /2).
The signal appearing at the input of sense amplifier 220 is very small (.about.100-200 mv), since the cell capacitance is small (<10%) compared to the bit-line capacitance. Throughout generations of DRAM, the minimum storage capacitance C needs to be 30-40 fF as described above in order to maintain read performance.
The requirement of large storage capacitance of conventional one-transistor cell results in high and multi-layered stack or deep trench capacitors, which is one of the major scaling limits in DRAM technology. Therefore, there is a need for innovations for reducing the requirement of storage capacitance in DRAM cell. One DRAM cell of the prior art adds a bipolar transistor to the DRAM cell for charge amplification as shown in FIG. 3a. DRAM cells with charge amplification are disclosed in U.S. Pat. No. 4,677,589 (Haskell et al.) and U.S. Pat. No. 5,363,325 (Sunouchi et al.) and shown in FIG. 3a and 3b. The structure of the cell is similar to that of FIGS. 1a and 1b. The n-MOS transistor M1 300 acts to switch the charges to and from the capacitor C 315. However, transistor Q1 310 acts to amplify the signal developed by the charges present on the capacitor to allow smaller charges to be present and still detect the logical "1" or the logical "0". The write of a logical "1" occurs when the bit-lines V.sub.bit 320 is brought to the voltage level V.sub.cc. This will allow the p/n junction formed by the emitter-base 350 of the bipolar transistor Q1 310 to conduct thus charging the capacitor C 305 to nearly the value of the power supply voltage source V.sub.cc.
When the cell is to be written to logical "0", the bipolar transistor Q1 310 will be nonconducting and any charge present on the capacitor C 305 will have to leak through parasitic paths from the capacitor C 315. This will cause the writing of a logical "0" to be very slow.
The structure of the bipolar transistor Q1 310 is formed by diffusing a p.sup.+ emitter 352 in the area that forms the N source of the n-MOS transistor M1 300. The bipolar transistor Q1 310 is thus formed as a merged transistor with the n-MOS transistor M1 300 by the p.sup.+ emitter 352, the N-base 350 (also the source of the n-MOS transistor M1 300), and the p-well 340 that acts as the collector.
"A Complementary Gain Cell Technology For Sub-1 v Supply Dram's", Shukuri et al., Digest of IEDM, p. 1006, 1992 and "Super-Low-Voltage Operation Of Semi-Static Complementary Gain DRAM Memory Cell", Shukuri et al., Digest of VLSI Technology Symposium, p. 23, 1993 describes a DRAM cell incorporating charge amplification. A complementary cell that has an n-MOS transistor and a p-MOS transistor with a floating gate structure acts as the storage node. The floating gate stores the charge representing the logical "1" or logical "0" and causes a shift in the threshold voltage of the pMOS transistor to allow reading of the logical "1" or logical "0" from the storage cell. "A Surrounding Gate Transistor (SGT) Gain Cell For Ultra High Density Dram's", M. Terauchi, et. al., Digest of VLSI Technology Symposium, p. 21, 1993 discloses a surrounding gate transistor gain cell. The surrounding gate transistor cell has an n-MOS transistor, a junction field effect transistor (FET), and a charge storage capacitor. The charge storage capacitor is formed as the gate of the junction FET.
"A Novel Merged Gain Cell For Logic Compatible High Density Dram's", M. Mukai, et. al., Digest of VLSI Technology Symposium, p. 155, 1997 discloses a merged DRAM cell that has a p-MOS transistor, an n-MOS transistor, a n-type junction FET, a second bit-line for write operation. The p-MOS transistor controls the charge transfer, the n-MOS transistor is used for charge storage and a read transistor, and the n-type junction FET is used to control the read out current. The charge storage occurs in the channel region of the n-MOS transistor.
The write and read operations of the DRAM cell of Shukuri et al., M. Terauchi, et. al., and M. Mukai, et. al., are handled by separate transistors and bit-lines to avoid the slow discharging as the bipolar/MOS transistor gain cell of FIGS. 3a and 3b as above described.
U.S. Pat. No. 5,066,607 (Banerjee) teaches a two transistor gain type DRAM cell. The two transistor DRAM cell has a high quality pass transistor and a large capacitance storage element. The gate of a gain transistor is coupled between the storage element and the pass transistor to amplify the charge at the storage element during a read operation.
U.S. Pat. No. 4,791,611 (Eldin et al.) discloses a memory cell that includes a bipolar transistor, a junction FET, and a capacitor. The capacitor comprises a MOSFET which is operated in the accumulation mode. The bipolar transistor controls the writing of the capacitor, while the junction FET controls the reading of the data from the capacitor.

Fabrication method and structure for a DRAM cell with bipolar charge amplification

Vanguard International Semiconductor Corporation


A cold cathode flat fluorescent lamp (CCFFL) comprising a flat lamp chamber, fluorescent substance, discharge gas, and a patterned electrode is provided. The discharge gas is disposed in the gas discharge chamber. The fluorescent substance is disposed over the inner wall of the gas discharge chamber. The patterned electrode is disposed over a surface of the flat lamp chamber. In an embodiment, the patterned electrode comprises anode pairs and cathode pairs which are alternately arranged. Each anode pair comprises a first meandering anode with first protrusions and a second meandering anode with second protrusions, wherein the first protrusions and the second protrusions are staggered. Each cathode pair comprises a first meandering cathode with third protrusions and a second meandering cathode with fourth protrusions, wherein each third protrusion aligns with each second protrusion, and each fourth protrusion aligns with each first protrusion.

1. Field of the Invention
The present invention relates to a cold cathode flat fluorescent lamp (CCFFL), and more particularly to a patterned electrode of a CCFFL.
2. Description of the Related Art
With the advance of technology, digital devices, such as mobile phones, digital cameras, digital video cameras, notebooks, and desktops are developed to have convenience, multiple functions and attractive designs. Display monitors of mobile phones, digital cameras, digital video cameras, notebooks, and desktops are essential interfaces between users and devices. Through the display monitors, users can conveniently use the devices. In recent years, display monitors of mobile phones, digital cameras, digital video cameras, notebooks, and desktops are liquid crystal display (LCD) panels, which, however, are not self-luminant. Therefore, a back-light module is disposed under a LCD panel to provide a light source to achieve the display purpose.
Having good luminance efficiency and uniformity, and the ability to provide a large-scale light source, the cold cathode flat fluorescent lamp (CCFFL) has been widely applied to the back-light module of LCD panels and other fields. A CCFFL is a plasma luminance device. By emitting electrons from a cathode to collide with inert gas between a cathode and an anode within a flat lamp chamber, the inert gas is ionized and excited to generate plasma. The excited atoms of the plasma return to the ground state by radiating ultra-violate (UV) light. The UV light then excites fluorescent substance in the CCFFL to generate visible light.
FIG. 1 is a schematic drawing showing a conventional CCFFL. Referring to FIG. 1, the conventional CCFFL comprises a flat lamp chamber 100, fluorescent substance 102, discharge gas 104, a patterned electrode 106, and a dielectric layer 108. Wherein, the flat lamp chamber 100 comprises flat substrates 100a and 100b, and edge stripes 100c. The edge stripes are disposed between the flat substrates 100a and 100b, and connect with the edges of the flat substrates 100a and 100b to form a sealed chamber.
Referring to FIG. 1, the material of the conventional patterned electrode 106 is usually silver, and the patterned electrode 106 is disposed over the flat substrate 100a. Usually, the dielectric layer 108 covers the patterned electrode 106 to protect the patterned electrode 106 from damage from ion collision. From FIG. 1, it is known that the patterned electrode 106 and the dielectric layer 108 thereon are on the inner wall of the flat lamp chamber 100. The discharge gas 104 is then injected in the flat lamp chamber 100. Usually, the discharge gas 104 is Xe, Ne, Ar, or other inert gas. In addition, the fluorescent substance 102 is disposed on the inner wall of the flat lamp chamber 100, for example, on the surface of the flat substrate 100b, the surface of the dielectric layer 108, and the surface of the flat substrate 100a, which is not covered by the dielectric layer 108, for example.
When the CCFFL is lit up, electrons emitted from the patterned electrode 106 collide with the discharge gas 104 in the flat lamp chamber 100 so that the discharge gas 104 is ionized to generate plasma. The excited atoms of the plasma return to the ground state by radiating UV light. The UV light then excites the fluorescent substance 102 on the inner wall of the flat lamp chamber 100 to generate visible light. In the luminance mechanism described above, however, the high-energy ions of the plasma would penetrate the dielectric layer 108 and damage the patterned electrode 106. As a result, the life time of the CCFFL is substantially reduced.
FIG. 2 is a schematic drawing showing a patterned electrode of a conventional CCFFL. Referring to FIG. 2, the patterned electrode of the conventional CCFFL comprises a plurality of meandering anodes 210, and a plurality of meandering cathodes 220. Because the meandering anodes 210 and the meandering cathodes 220 have sin-waveform designs, ideally, the meandering anodes 210 and the meandering cathodes 220 generate plasma in the luminance areas 230a and 230b. However, the luminance areas 230a and 230b are driven by the same meandering cathode 220 so that the luminance area 230a is lit up, but the luminance area 230b is not. In other words, sharing the same meandering cathode 220 or the same meandering anode 210 usually means only one of the two sides of the meandering cathode 220 or the meandering anode 210 is lit up. As a result, a dark-bright pattern would appear on the CCFFL, thus deteriorating the uniformity of the light source.

Cold cathode flat fluorescent lamp and patterned electrode thereof


A method for regulating a distance of a vehicle from a preceding vehicle (vehicle ahead) based on available information for the subject vehicle's speed, for the distance and for the speed of the vehicle ahead and on data regarding route information includes determining a fuel-saving situation for a fuel saving momentum utilization phase, and precomputing a consumption optimal speed profile for undisturbed travel. The method further precomputes an additional separation requirement to the vehicle ahead that is required to be able to fully implement the momentum utilization phase, and builds up the required additional separation prior to the fuel-saving situation, wherein the additional separation is built up, preferably substantially uniformly, over a separation build-up distance that is longer than the precomputed momentum utilization phase distance and/or is built up with a driver-acceptable, convoy-stabilizing, defined small speed reduction relative to the current speed of the vehicle. The momentum utilization phase on reaching the fuel-saving situation.

The invention relates to a method for regulating the distance of a vehicle from a preceding vehicle (vehicle ahead).
With vehicles, especially with commercial vehicles, the momentum of the vehicle can be advantageously used to reduce the fuel consumption. For this purpose, in suitable situations an increase in speed or a reduction in speed is carried out. The generally applicable background of said measure is to avoid braking and in return to reduce the length and intensity of a drive phase. Here the momentum of the vehicle is used in a road section lying at the end or start of a drive phase.
Such a utilization of momentum can take place individually by a corresponding driving style of a driver. An improved utilization of momentum is, however, achieved by automation using a driver assistance system in connection with a speed regulation system, e.g. as is known from DE 10 2008 023 135 A1. Relevant situations for a momentum utilization phase are determined in advance with road route information, which is provided in the vehicle by an extended navigation system. Such situations can arise from the topography, for example increasing downhill gradient, end of gradient, tight bend, etc. or from the knowledge of the road infrastructure, for example the start of a village, the start of a speed limit, etc. Furthermore, situations can be derived from the objective of operating the vehicle in relation to the topography and the road infrastructure at an optimal operating point for consumption and wear. Suitable optimizing measures for this purpose are known, for example from DE 10 2008 035 944 B4.
If the speed profile of vehicles that use a saving situation is compared with vehicles travelling at constant speed, depending on the saving situation there is a difference of the speed profiles and hence also a variation of the separation of the vehicles from each other. Therefore, for a full utilization of a saving situation by a vehicle it is necessary that there is sufficient distance to a vehicle ahead. For this purpose a method for the special situation of a build-up of momentum prior to a gradient is already known from DE 10 2006 003 625 A1, with which it is provided that there is such a large distance available ahead that an increased speed necessary for the utilization of momentum does not result in too short a distance to the vehicle ahead. Here an adjustment of the target distance to the vehicle ahead is carried out on the basis of topography information prior to gradients during distance regulation. Specific information, especially how large and how long in advance thereof an additional separation should be built up, is not given here. Particularly the type and manner of the build-up of the additional separation and its length are, however, essential for acceptance of an automated driving mode with a momentum utilization phase, especially in connection with the following traffic and the effects on behaviour in convoy traffic.

Method for regulating the distance of a vehicle from a preceding vehicle


A joint connector has a housing (10) with insertion spaces (11) for receiving terminal fittings (20). A joint terminal (30) is mounted in the housing (10) at a first position where the joint terminal (30) is retracted from the insertion spaces (11). The terminal fittings (20) then are inserted into the insertion spaces (11) of the housing (10). The joint terminal (30) then is displaced to a full locking position for contacting and shorting the terminal fittings (20). As a result, the joint terminal (30) does not hinder insertion of the terminal fittings (20). Furthermore, the joint terminal (30) is mounted directly in the housing (10) and does not require a separate holder. Thus, the number of parts is reduced.

1. Field of the Invention
The invention relates to a joint connector and to a method of assembling it.
2. Description of the Related Art
U.S. Pat. No. 6,878,017 discloses a joint connector that has a housing and a plurality of terminal fittings mounted in the housing. A joint terminal is mounted in a holder and has a plurality of contact portions. The contact portions can be brought into contact with the terminal fittings in the housing to short the terminal fittings.
The number of parts of the joint connector could be reduced by eliminating the holder and mounting the joint terminal in the housing. However, a connection resistance is produced between the joint terminal and the terminal fittings when the terminal fittings are inserted into the housing and creates a reaction force against the insertion. The terminal fittings often are inserted into the housing by gripping wires connected with the terminal fittings. However, the above-described connection resistance causes the wires to buckle, thereby making it impossible to insert the terminal fittings.
The invention was developed in view of the above problem and an object thereof is to reduce the number of parts without hindering the insertion of terminal fittings into a housing.

Joint connector and method of assembling it


An independent suspension system is provided for coupling a set of wheels to a vehicle body structure. The system includes independently pivotable swing arms, a shock absorber assembly, a joining arm and tie rods. The swing arms are attached to the vehicle body structure and to a respective wheel and the shock absorber assembly is mounted to the vehicle structure. The shock absorber assembly includes a biasing element and a linkage coupled to the joining arm and the biasing element. The suspension system further includes a tie rod connecting each swing arm to the joining arm. The joining arm is arranged to move in a lengthwise vehicle direction under control of the biasing element in response to road input to both wheels, and rotate about an attachment point without lengthwise movement to allow the tie rods to translate in opposite lengthwise direction in response to leaning of the vehicle.

Generally, motorcycles and all terrain vehicles, commonly referred to as ATV's, typically include two, three and four wheel configurations. In the three and four wheel configurations, adjacent wheels are typically spaced apart to span the width of the vehicle and also share a common axle. Spacing apart the wheels also provides the ability to mount suspension components to a common axle housing or to a wheel hub support structure located on an axle side of the wheel.
However, the aforementioned suspension configuration would not work well in a four wheel vehicle of narrow width where the wheels are spaced apart in a manner that does not allow enough space to mount suspension components between the wheels. For example, in a four wheel motorcycle arrangement, the motorcycle typically has a narrow width resulting in limited spaced between each set of spaced apart wheels. This limited space does not typically provide enough room to mount conventional suspension components, let alone an independent front and rear suspension system that would be required to accommodate a leaning condition of the four wheel motorcycle.
Thus, there is a need for a suspension system for a narrow width four wheel vehicle that overcomes the aforementioned and other disadvantages.


A method for manufacturing a semiconductor elemental device including an SOI structure in which an SOI layer is laminated, includes the steps of setting transistor forming regions and a device isolation region to the SOI layer, forming a pad oxide film over the SOI layer and forming an oxidation-resistant film over the pad oxide film; forming a resist mask in a region corresponding to each of the transistor forming regions, and etching the oxidation-resistant film and the pad oxide film with the resist mask as a mask to expose the SOI layer of the device isolation region; removing the resist mask and oxidizing the exposed SOI layer by a LOCOS method using the oxidation-resistant film to form a field oxide film; and implanting amorphization ions in an edge portion formed in the SOI layer upon formation of the field oxide film to amorphize the edge portion.

The present invention relates to a method for manufacturing a semiconductor elemental device wherein a device isolation layer is formed in an SOI layer of an SOI (Silicon On Insulator) substrate by a LOCOS (Local Oxidation of Silicon) method.
An SOI substrate is formed by sequentially laminating a support substrate, an insulating layer (so-called BOX oxide film) and a silicon thin film layer (called SOI layer) formed of monocrystalline silicon. Since a field oxide film electrically insulates and separates between elements of a semiconductor elemental device formed in an SOI layer of the SOI substrate to make it possible to suppress an soft error and latchup and reduce a junction capacitance of a source/drain section, such an SOI substrate has been used in the manufacture of a number of semiconductor devices as a technique that can contribute to speeding up and a reduction in power consumption.
A trench structure and a LOCOS method are used to form the field oxide film that separates between the elements. However, the trench structure has a disadvantage that since an SOI layer is etched to define trenches and an oxide film is embedded in the trenches, the number of processes increases and the cost of manufacturing thereof increases as compared with the LOCOS method.
On the other hand, the LOCOS method is advantageous to a reduction in manufacturing cost. It is however known that a thin silicon layer (called an edge portion) having a triangular section is formed at a boundary among an insulating layer, a field oxide film and an SOI layer upon formation of the field oxide film by the LOCOS method and constitutes a parasitic MOSFET (MOS (Metal Oxide Semiconductor) Field Effect Transistor), and this parasitic MOSFET exerts an adverse effect on current characteristics of an N channel MOS element (called an nMOS element) and is brought to a bump characteristic in which a bump occurs in current-voltage characteristics, thereby reducing a threshold voltage.
As the technique of preventing such a reduction in the threshold voltage, a simulation result has been reported that the bump characteristic can be suppressed by raising a boron concentration of the edge portion formed in the SOI layer (refer to, for example, a non-patent document 1 (J. W. Thomas and two more ones, "Characteristics of Submicrometer LOCOS Isolation", Proceedings 1995 IEEE International SOI Conference, IEEE, October 1995, p. 116-117)).
The inventors have actually prototyped an nMOS element using conditions shown in Table 1 of the non-patent document 1 and evaluated its current-voltage characteristics.
Process steps at this time are as follows: A pad oxide film is formed in its corresponding SOI layer of an SOI substrate. A silicon nitride film is deposited on the pad oxide film by a CVD (Chemical Vapor Deposition) method and thereafter patterned by photolithography and etching, thereby removing the pad oxide film and silicon nitride film in a device isolation region and forming a filed oxide film in the exposed SOI layer by a LOCOS method.
After the formation of the field oxide film, boron ions are implanted to raise the boron concentration of each edge portion, and thereafter the pad oxide film and silicon nitride film in the corresponding transistor forming region are removed.
Thereafter, the formation of a gate oxide film, the formation of a gate and the formation of a source/drain section are executed in a manner similar to the normal nMOS element manufacturing process, and the corresponding nMOS element used for evaluation was formed.
The result of measurement of current-voltage characteristics of the nMOS element prototyped in this way is shown in FIG. 10.
FIG. 10 shows a drain current per unit width, which flows between the source and drain with respect to each gate voltage. It is understood from the current-voltage characteristics of the nMOS element prototyped according to the above that as shown in FIG. 10, a bump occurs in a region enclosed with a circle and there is room for improvement in bump characteristic.
For the purpose of improving such a bump characteristic, the inventors have proposed that after the formation of a field oxide film, P type impurity ions such as boron are implanted in an SOI layer to form a high-concentration impurity region at an edge portion, and on such a heat-treatment condition that the impurity in the high-concentration impurity region is not diffused into a channel section before the removal of a pad oxide film and a silicon nitride film in a transistor forming region, the damage of the field oxide film due to ion implantation at the formation of the high-concentration impurity region is recovered and the amount of cutting of the field oxide film is reduced (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-124303 (paragraph numbers 0019-0021 in page 4, FIG. 2 and FIG. 3)).
It has been proposed by the specification disclosed in Japanese Patent Application No. 2003-328092 that a metal oxide film such as aluminum oxide is formed in a slope or inclined part of an edge portion or a device isolation region of an SOI layer before a field oxide film is formed in the SOI layer having exposed the device isolation region by a LOCOS method, and the field oxide film is formed on the metal oxide film to thereby reduce a bump characteristic through the use of a negative fixed electrical charge contained in a defect produced due to the reaction of an interface between the SOI layer and the metal oxide film.
However, the technique of the non-patent document 1 referred to above is accompanied by a problem that although the simulation result that the bump characteristic can be suppressed by enhancing the boron concentration of the edge portion formed in the SOI layer is obtained, the above-described bump characteristic appears in an actual nMOS element.
That is, the simulation result that the bump characteristic can be suppressed by enhancing the impurity concentration of boron or the like at the edge portion, is considered to be correct. However, it is considered to be proper because the impurity of the edge portion is diffused due to heat treatment executed in the subsequent process and eventually the impurity concentration of the edge portion is reduced so that the effect of suppressing the bump characteristic is degraded. This becomes a problem particularly important for an increase in the thermal processing process with multifunctioning of the recent semiconductor device.

Method for manufacturing a semiconductor elemental device


An electronic device is thin and includes heat-generating components that are cooled efficiently. The electronic device includes heat-transmitting sheets 72 and 47 being stuck to inside surfaces of a lower section and an upper section of the electronic device's case and in contact with heat-generating components, which are semiconductor components such as an image processor and a central processor mounted on both sides of a motherboard provided in the case, and elastic sheets, which are laid between the portions, contacting the heat-generating components, of the heat-transmitting sheets and the inside surfaces of the sections.

1. Field of the Invention
This invention relates to an electronic device whose heat-generating components are disposed in its case. More specifically, this invention relates to an electronic device whose cooling mechanism for heat-generating components is engineered so as not to prevent the device from being made thin and light.
2. Description of the Related Art
Notebook computers have been known for some time as an electronic device with a body and a display which can freely be opened away from the body and closed onto the body.
For example, patent document 1 discloses a notebook computer. A chassis is put in the case of the body, and an optical-disk device, a battery, etc. are housed in the chassis. Fitted to the bottom surface of the chassis is a motherboard on which a central processor, a hard-disk drive, and various connectors are mounted.
Heat generated by the central processor, etc. is transmitted to the chassis of die-cast magnesium and diffused through the chassis.
[Patent Document 1] Japanese Unexamined Patent Publication No. 2002-108505
The box-like chassis of the notebook computer of the patent literature 1 serves as a heat sink. As a result, no fan or separate heat sink is required. However, the chassis has a three-dimensional construction for strong rigidity against bending and twisting, preventing the computer from being made thin.


A light-emitting display device is disclosed. The display includes: a display panel having a plurality of light-emitting elements disposed on a substrate in a matrix; a deterioration amount difference calculation section; a correction amount calculation section; a deterioration amount difference correction section; a gamma conversion section; an actual deterioration amount calculation section; and an estimation error detection section.

1. Technical Field
An embodiment of the invention relates to a burn-in correction technology for a light-emitting display panel.
It should be noted that the invention proposed by the inventors includes aspects of a light-emitting display device, an electronic apparatus, a burn-in correction device, and a program.
2. Related Art
Flat panel displays are widely prevalent in products such as computer displays, mobile terminals, and television receivers. Although liquid crystal display panels are widely adopted now, narrow view angles and slow responses are still pointed out continuously.
On the other hand, organic EL displays composed of light-emitting elements are capable of achieving thin shapes without backlights, high luminance, and high contrast, in addition to overcoming the problems of view angles and responses. Therefore, organic EL displays are expected to be next generation display devices superseding liquid crystal displays.
Incidentally, organic EL devices or, other light-emitting devices have their characteristics deteriorated in accordance with the light-emitting amount or the amount of light-emitting period.
On the other hand, contents of images displayed on light-emitting display devices are not uniform. Therefore, deterioration of a part of the light-emitting elements is easily advanced. For example, deterioration in luminance advances faster in a time display area (a static display area) than in other display areas (moving image display areas).
The luminance of the light-emitting element with advanced deterioration is lowered in comparison with the luminance thereof in other display areas. This phenomenon is generally called "burn-in." Hereinafter, the deterioration of a part of the light-emitting elements is described as "burn-in."
Presently, there are various methods as measures for remediating the "burn-in" phenomenon.
As related art documents, there can be cited JP-A-2003-228329, JP-A-2000-132139, and JP-A-2001-175221.

Light-emitting display device, electronic apparatus, burn-in correction device, and program


An optical magnetic recording medium includes a first magnetic film for holding information in a status of either an upward or a downward magnetization, a second magnetic film closely adjacent to the first magnetic film and an in-plane magnetization film positioned between the first and second magnetic films, the in-plane magnetization film having such a characteristic that its magnetic characteristics are switched between a first temperature range and a second temperature range. The in-plane magnetization film is kept within the first temperature range at a room temperature and, at the time of an information reproduction, the in-plane magnetization film is locally heated to the second temperature range by an irradiation of an energy beam so that information on the recording layer is copied to the reproduction layer, and the copied information is observed.

The present invention relates to an optical magnetic recording medium for carrying out a recording, a reproducing and an erasing of information, and a method of reproducing information in an optical magnetic recording medium.
A reproduction of a record on an optical magnetic disk is carried out by using a laser beam. A spot diameter on a recording film can be expressed by .lambda./NA, where NA represents the numerical aperture (usually about 0.5) of an objective lens to be used and .lambda. represents a wavelength of a laser. When the wave-length is 680 nm and NA is equal to 0.55, the spot diameter becomes about 1.2 .mu.m. An existence of only one record magnetic domain (mark) in the spot diameter is a proper condition of reproduction. In other words, the shortest length of the record magnetic domain that can be reproduced is 1.2 .mu.m/=0.6 .mu.m.
As described above, the recording density is improved when the wavelength of a semiconductor laser is short. However, under current circumstances, it is not possible to expect the shortening of the wavelength of a semiconductor laser at a very early stage. Relating to this, a technique for improving a reproduction resolution by utilizing the magnetic characteristics of a recording film has been proposed in Japanese Patent laid-open Publication No. JP-A-3-93056, for example.
According to this technique, a recording film is structured by three kinds of magnetic film, and a part of information recorded on another magnetic layer is compulsively masked by a magnetic layer at a beam incident side to effectively improve the reproduction resolution. The recording film is structured by the three kinds of magnetic layer of a reproduction layer, an intermediate layer and a recording layer, from the beam incident side.
The above-described content is a magnetic super-resolution effect and this is called "magnetic super-resolution". A magnetic mask shape to be compulsively generated within a spot is determined by a temperature distribution on a recording film generated by a reproduction light.
There are the following three main types in the above-described magnetic super-resolution:
A first is FAD (Front Aperture Detection) as disclosed in the Japanese Patent laid-open Publication No. JP-A-3-93056 according to which a magnetic domain can be observed only at a low temperature section within a light spot. A second is RAD (Rear Aperture Detection, reference the Japanese Patent laid-open Publication No. JP-A-63-93058) according to which a magnetic domain can be observed only at a high temperature section within a light spot. A third is CAD (Center Aperture Detection, reference the Japanese Patent laid-open Publication No. JP-A-5-12731).
The first (FAD) is effective for improving the scanning density but it is not possible to increase the track density because a magnetic domain of a low temperature section, that is, the magnetic domain recorded on both sides of the adjacent tracks, is also leaked into a signal. Further, the FAD also has a handicap of an apparatus that a reproduction magnetic domain of several hundred Oe is necessary.
In the case of the second (RAD), only the information at a high temperature section, that is, the information near the center of the spot, can be observed. Therefore, there is no leakage of a magnetic domain of the surrounding low temperature section into a signal. Accordingly, the RAD is suitable for increasing both the track density and the scanning density. However, a magnetic domain copied to a reproduction layer deviated from the spot remains as it is, and therefore the magnetic super-resolution effect cannot be exhibited at the time of reading the information next time.
Accordingly, in the case of the RAD, it is necessary to erase in advance the magnetic domain copied to the reproduction layer at a sufficiently low temperature of the disk at the reproduction section. Thus, in the case of the RAD, it is also necessary to install a large permanent magnet of several kOe within the apparatus. This is a problem in providing a compact apparatus.
A magnetic field which is sufficiently large enough for preparing the magnetization of the reproduction layer in one direction is called an "initialization magnetic field" which is the magnetic field necessary for the initialization. This can be given by the following expression.
A minimum required initialization magnetic field=(coercive force of the reproduction layer)+(exchange-coupled magnetic field which is received by the reproduction layer from the adjacent magnetic layers)+(magneto-statically coupled magnetic field which is received by the reproduction layer from the adjacent magnetic layers) - - - (1)
In this case, the exchange-coupled magnetic field is a magnetic field which tries to cancel the torsion of a spin between the reproduction layer and the adjacent magnetic layers. The magneto-statically coupled magnetic field in this case refers to a portion of the magnetic field that extends from the inside of a magnetic domain recorded on a recording layer to the outside and affects the reproduction layer. Accordingly, in order to reduce the initialization magnetic field, it is necessary to make smaller the exchange-coupled magnetic field or the magneto-statically coupled magnetic field that is received by the reproduction layer from another magnetic layer. However, when the initialization magnetic field is reduced by making smaller the exchange-coupled magnetic field or the magneto-statically coupled magnetic field at ambient temperature, the magneto-statically coupled magnetic field and the exchange-coupled magnetic field are made further smaller at a high temperature, so that the information on the recording layer cannot be copied to the reproduction layer. Consequently, there is a limit to the reduction of the initialization magnetic field.
The third (CAD) does not require the initialization magnetic field. In the CAD, a magnetic layer having such characteristics that the magnetization faces within the plane at ambient temperature but faces a perpendicular direction when the temperature rises is used for the reproduction layer. In the case of the above-described RAD, there are only two types of magnetization status of the reproduction layer that the magnetization is either in the upward direction or in the downward direction and it is possible to achieve a contrast necessary for a super-resolution. However, in the case of the CAD, a super-resolution effect as obtained in the RAD cannot be achieved because there are various statuses of magnetization of the reproduction layer, ranging from the upward direction to the downward direction.
As explained above, each of the FAD, RAD and CAD has problems in practical application. In other words, according to the above-described prior-art techniques, an optical magnetic recording medium which can carry out a super-resolution reproduction at high contrast with both high track density and high scanning density and which does not require a reproduction magnetic field and an initialization magnetic field has not been obtained.
With a view to eliminating the above-described drawbacks, it is an object of the present invention to provide an optical magnetic recording medium which can satisfy all the above-described requirements, and a recording and reproducing method using the same. More particularly, it is an object of the present invention to provide an optical magnetic recording medium which does not require either an initialization magnetic field or a reproduction magnetic field and which can carry out a high-density reproduction with a magnetic super-resolution effect at 200 Oe or below that does not affect the structure of an apparatus, and a recording and reproducing method using the same.
In the abstract, the present invention includes a recording layer for holding information, a reproduction layer to which information on a recording film is copied and an intermediate layer positioned between the recording layer and the reproduction layer, wherein the intermediate layer has an in-plane magnetization component within a specific temperature range.
It is desirable that the recording layer has an easy magnetization axis perpendicular to the surface of the medium and holds information in either the upward or downward magnetization status. It is also desirable that the reproduction layer has an easy magnetization axis perpendicular to the surface of the medium and the information on the recording film is copied to this reproduction layer. It is further desirable that the recording layer and the reproduction layer are calibrated as vertical magnetization films. The intermediate layer has an in-plane magnetization component within a specific temperature range and plays the role of a switching layer by losing the magnetization component within a specific temperature range.
Further, the present invention includes a recording layer for holding information in the status of either an upward magnetization or a downward magnetization, a reproduction layer closely adjacent to a recording film and an intermediate layer located between the recording layer and the reproduction layer. Further, the present invention uses an optical magnetic recording medium in which the intermediate layer has an in-plane magnetization component within a first temperature range and loses the in-plane magnetization component within a second temperature range, and at the time of reproducing information, maintains the intermediate layer locally within the second temperature range by an irradiation of an energy beam so that the information on the recording layer is copied to the reproduction layer to enable observation of the copied information. Alternately, an in-plane magnetization film is used for the intermediate layer, and has a characteristic that the magnetic characteristics are switched between the first temperature range and the second temperature range. Normally, at the time of information reproduction, the in-plane magnetization film is locally heated by the irradiation of an energy beam so that the information on the recording layer is copied to the reproduction layer to enable observation of the copied information.
As a detailed structure of a medium, an optical magnetic recording medium is provided having a dielectric film formed on a substrate, a recording film including at least three layers of magnetic film formed by either a magneto-static coupling or an exchange-coupling on said dielectric film, and a recording film formed by a dielectric film and/or a metal film. Further, in between the reproduction layer and the recording layer of the above-described recording films, an intermediate layer in which a magnetization is faced in-plane within a temperature range from at least 50.degree. C. to the Curie temperature is inserted. Further, it is desirable that the sum of the coercive force of the reproduction layer and the magneto-statically coupled magnetic field and the exchange-coupled magnetic field received by the reproduction layer is smaller than 200.
This application relates to U.S. patent application Ser. No. 08/126,766 filed on Sep. 27, 1993 entitled Overwritable Optical Recording Medium and Recording Method of the Same, by Takeshi MAEDA et al. and assigned to HITACHI, LTD.

Optical magnetic recording medium and optical magnetic reproducing method