There is disclosed a method for the treatment of Extra Pyramidal syndrome (EPS) comprising the administration of an adenosine A2a receptor antagonist, alone or in combination with other agents useful for treating EPS.

Extra-Pyramidal Syndrome (EPS) is a collective term for a series of adverse neurological reactions associated with the use of antipsychotic drugs. There are six different categories of EPS-related neurological syndromes of which four, dystonia, akathisia, pseudoparkinsonism (parkinsonian syndrome), and tardive dyskinesia, are particularly prevalent in patients taking antipsychotic medication. Dystonia is a painful spasm of the muscle groups of, in particular, the neck, jaw, back, pharynx, and larynx. It is most common in young males being treated with antipsychotic drugs, but can also be associated with the use of cocaine, tricyclic antidepressants, lithium and anticonvulsants such as phenytoin and carbamazepine. Pseudoparkinsonism manifests itself as akinesia (rigidity, stiffness and slow voluntary motion, stooped, shuffling walk) and tremor and these symptoms develop within weeks or months after initiation of therapy. Akathisia manifests itself as strong, subjective inner feelings of distress or discomfort characterized by motor restlessness. Often mistaken for agitation or anxiety, this common syndrome is frequently under-diagnosed and is the least responsive to treatment. Tardive dyskinesia is a late-appearing syndrome associated with chronic use of neuroleptic drugs. It occurs more frequently in older patients and is characterized by stereotypical, repetitive, involuntary, quick choreiform movements of the face, eyelids, mouth, tongue, extremities and trunk.
EPS is more prevalent with the use of typical antipsychotic agents but has also been reported with the use of atypical agents. Typical antipsychotics include loxapine, haloperidol, chlorpromazine, prochlorperazine and thiothixene. Atypical antipsychotics include clozapine, olanzapine, loxapine, quetiapine, ziprasidone and risperidone.
Akathisia is also a characteristic of RLS and PLMS, as well as PLMD (periodic leg (or limb) movement disorder). RLS is a common disorder that causes patients to have an irresistible and unpleasant desire to move their legs; it usually manifests during periods of inactivity and/or at night, and can disturb sleep. Patients who do not have the typical RLS symptoms, but who do exhibit periodic leg movements that adversely impact sleep, are diagnosed with PLMS. Treatments for RLS and PLMS have included levodopa/carbidopa, levodopa/benserazide, dopamine agonists such as pramipexole and ropinerole, benzodiazepines, opioids, anticonvulsants and iron (ferrous sulfate). RLS and PLMS have been extensively described in the literature, for example by Saletu et al, Neuropsychobiology, 41, 4 (2000), p. 190-9.
The purine nucleotide, adenosine, is known to be an endogenous modulator of a number of physiological functions in the central (CNS) and peripheral nervous systems.
Adenosine exerts its biological actions through a class of membrane specific receptors which belong to the super family of receptors coupled with G proteins. Biochemical and pharmacological studies, together with advances in molecular biology, have allowed the identification of at least four subtypes of adenosine receptors: A1, A2a, A2b and A3. Analogs of adenosine able to interact as antagonists with the A1, A2a, A2b and A3 receptors have also been identified.
In the CNS, data has shown that A2a receptors are present in high density in the basal ganglia, known to be important in the control of fine motor movement. Moreover, selective antagonists for the A2a receptor are of pharmacological interest because of their demonstrated efficacy in reducing motor impairment thereby improving function in neurodegenerative diseases such as Parkinson's disease and related movement disorders (e.g. Huntington's Disease). A2a antagonists appear to demonstrate a reduced side-effect liability (e.g. no dyskinesia) compared to current dopaminergic therapies resulting in an improved therapeutic index. A2a antagonists may also have antidepressant properties and stimulate cognitive functions. Some xanthine-related compounds have been found to be A1 receptor selective antagonists, and xanthine and non-xanthine compounds have been found to have high A2a affinity with varying degrees of A2a vs. A1 selectivity. Adenosine A2a receptor antagonists have been disclosed previously, for example in WO 95/01356 and U.S. Pat. No. 6,630,475.


A technique for providing a control and management protocol for an Ethernet network in an Ethernet layer is disclosed. In one embodiment, the technique is realized by transporting a plurality of inter-nodal messages via Ethernet packets based on a type parameter; identifying at least one management packet from the Ethernet packets; and identifying a management function associated with the at least one management packet based on a management parameter. In addition, the management function may involve notification of physical link failure; monitoring congestion; monitoring packet errors; communicating with an External Management System; measuring signal quality of link; detecting loss of signal; assessing signal quality of nodes by a loop back packet comparison; and communicating user information in the form of voice, data, and video between nodes.

As a dominant Local Area Network (LAN) protocol, Ethernet is widely accepted and well understood. Its bandwidth evolution from Megabits per second (Mbps) to Gigabits per second (Gbps), as well as a competitive price per port, have attracted all types of service providers. Further, Ethernet can be used without a Synchronous Optical Network (SONET) protocol based network, thereby further reducing operating costs. On a business investment side, Regional Bell Operating Companies (RBOCs) have shown great interest in adopting Ethernet, and Gigabit Ethernet (GE) in particular, as a transport mechanism for voice, data and video in a network. This is economically attractive from a standpoint of operations and capital expenses.
However, there are concerns as to whether Service Level Agreements achieved by SONET can be sustained by Ethernet networks, as carriers of SONET tend to be more stringent in maintaining a high grade of service than normal IP service providers. For normal IP service, disruption of communications for a period up to tens of seconds may be tolerated by customers. However, for carriers of SONET, this period for restoration is regarded as unacceptable. In particular, link failures should be restored by a protection mechanism (e.g., a protection protocol and associated hardware) within a time period of approximately 50 milliseconds.
In a current deployment of GE services, a physical layer may include SONET or a photonic network, for example. Ethernet data frames are transported as payloads by physical layers of SONET or a photonic network. However, management of an Ethernet layer is limited and distinct from management capabilities of the physical layer of a network.
In SONET, detection of a fiber link failure between a first node and a second node is communicated via SONET overhead parameters. A protection link switch-over may be immediately initiated if a system is so configured. Generally, an Ethernet layer is oblivious of any management action taken in the physical layer.
External management of the Ethernet layer is mainly focused in a protocol domain (e.g. Management Information Base (MIB)). In particular, an External Network Management system only manages the Ethernet layer by manipulating MIB parameters at a management interface.
An Ethernet node (e.g., Ethernet switch) in a LAN network may rely on higher layer protocols to establish "keep alive" communication with peer nodes, where topology of the network may be reconfigured in case of link failure. Reconfiguration may take tens of seconds, for example. However, the Ethernet layer itself does not support any means to detect link failure or support a restoration scheme to recover from a failure situation. In current Ethernet networks, when network congestion is observed, a common approach involves enabling each Ethernet switch to discard Ethernet packets to alleviate the network congestion thereby resulting in inefficiencies.
Ethernet protocol does not currently support functions to facilitate management aspects of an Ethernet layer in a network. There is no channel dedicated to managing information exchange between nodes. If the Ethernet layer is to be utilized as a transport layer for various services, there is a need to have a set of management protocols for the Ethernet layer, similar to those of SONET, to enable the nodes (e.g., switches) of an Ethernet network to exchange management information. The introduction of these new protocols may enable the Ethernet layer to emulate management functions of a SONET network, where the management function of an Ethernet network may assume "SONET-like" characteristics.
In view of the foregoing, it would be desirable to provide a technique for providing a control and management protocol which overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for providing a control and management protocol for an Ethernet layer in an Ethernet network in an efficient and cost effective manner. A management function at the Ethernet layer at each node to utilize the control and management protocol to exchange information with peer nodes to perform network management would also be desirable.

Technique for providing a control and management protocol for an ethernet layer in an ethernet network


A method for a rechargeable battery is disclosed that includes applying a charge voltage to the rechargeable battery; monitoring a battery voltage and a battery current of the rechargeable battery; and identifying a top of charge condition when for a defined time period the battery voltage is within a voltage tolerance of the charge voltage and the battery current is within a current tolerance of a threshold current. Also disclosed is a rechargeable battery system.

1. Technical Field
Embodiments of the subject matter disclosed herein relate to rechargeable batteries and methods of recharging rechargeable batteries.
2. Dicussion of Art
In some situations, how a rechargeable battery is charged and discharged may result in undesired battery performance and premature deterioration of the electrochemical cells of the battery. For example, repeated over or under charging of a rechargeable battery may damage its electrochemical cells. Over charging batteries has also lead to battery failures. In prior systems, a battery has been recharged by applying a voltage to the battery and charging until the battery ceases to draw current from the charging source. Such systems have been susceptible to changes in the charge voltage that have led to over and under charging and reduced performance. In other systems, the total charge in the battery is monitored by integrating current to and from the battery. However such systems have required precise current measurement that substantially increases the cost of a rechargeable battery system. Moreover, the magnitude of errors in the monitored charge of the battery tends to increase over time through successive charge and discharge cycles resulting in reduced battery performance. Other systems have relied upon a correlation between a battery's open circuit voltage and state of charge to assess the total energy stored within the battery. However for some batteries, the open circuit voltage does not correlate well to the total energy stored. These prior systems have not provided a consistent indication of the useful power contained in the battery, which has adversely affected the efficiency of the charge and discharge operations.
It may therefore be desirable to have a rechargeable battery and/or a method for a rechargeable battery that differ from those that are currently available.

System and method for a rechargeable battery


The invention relates to an electrical distribution system for energizing a plurality of electric circuits in accordance with a predetermined delay pattern. The system as described comprises a control unit, a plurality of circuit delay arrangements each associated with an electrical circuit individual thereto and each circuit delay arrangement is identifiable by a circuit code individual thereto and includes a pulse counting arrangement. The control unit is arranged to transmit the circuit codes to the circuit delay arrangements and the pulse count individual to each circuit code, and each circuit delay arrangement identified by its circuit code is arranged to store the pulse count individual to that code. On receipt of a start signal from the control unit, transmitted simultaneously to all the circuit delay arrangements, each circuit delay arrangement starts its respective pulse counting arrangement and energizes its respective electrical circuit when the pulse count is completed.

It is well known in the art to provide an electrical distribution system for energizing a plurality of electric circuits in accordance with a predetermined delay pattern and one such system comprises a conventional street lighting system, particularly a sodium light system, and wherein a plurality of electrical circuits, each associated with a lamp, are activated successively in accordance with a predetermined delay pattern so that the lights are illuminated in the predetermined delay sequence to avoid an overload of the local electrical distribution system. In such, a system the predetermined delay pattern is predetermined by a clock, the clock is set to actuate the light circuits in accordance with the predetermined delay program, and in such a system the actual delay between successive lights being illuminated is not important, subject to the lights being illuminated in the desired order.
The present invention is not concerned with such clock controlled electrical delay systems and such clock controlled systems are disclaimed herefrom.
In other electrical systems, for example electrical systems for igniting detonators in an explosives firing circuit in accordance with a predetermined pattern, there are factors which require that the detonators be ignited in accordance with a relatively accurate delay pattern.
One arrangement for obtaining an accurate time delay sequence for a plurality of circuits is disclosed in the British Patent Publication No 2015791B and wherein an accurate pulse generating means is provided in a control unit and a relatively cheap, and relatively inaccurate, pulse generating means is provided in each of the delay circuits associated with the respective loads. The accurate pulse generator in the control unit sends relatively accurate timing interval signals and each electrical load circuit includes means for receiving the timing interval signals from the control unit, means for allowing the pulse generator of each delay circuit to run for the time interval defined by the control unit and for counting the number of pulses made by the pulse generator during the time interval signals means. The delay circuits are arranged to calculate a further time interval as a function of the said time interval and, on receipt of a fire signal, each pulse generating means is then arranged to run for said time interval and said function of the time interval before activation the relevant electrical load circuit.


A building block, comprises a plurality of basic units and a plurality of connectors. Each connector is used to connect each two basic units. The basic unit is a hexahedron. Each face is set with a plurality of connecting holes and a slot. The connector inserts into one connecting hole on one face of the basic unit, and comes out from another connecting hole on the opposing face through the slot to connect with another basic unit. The connecting design not only increases the ways of connecting each two basic units, but also ensures that one basic unit has at least one connecting hole for connecting with another basic unit. The present invention is help to cultivate children's ability of multiple perspectives thinking and ability of 3D space thinking.

Human brains develop fastest during infancy. And tactile manipulation of objects can promote the development of infant brains. At present, there is a few intelligence related toys on the market, such as puzzles, magic cubes, building blocks. Among these, children deeply love building blocks because children can assemble and disassemble building blocks as they wish with only their imagination as a limit.
In a Chinese patent published as CN 1035058874A, an atomic building block was disclosed. The atomic building block has a plurality of faces on which there are a plurality of interfaces. According to different types of interfaces, elements of the atomic building block can be categorized into two classes, elements with convex interfaces and elements with concave interfaces. By combining convex interfaces with concave interfaces of the atomic building block, 3-D assembly can be realized and children can build many forms and structures. However, because there are two kinds of atomic building blocks, children have to classify them. Many infants fail to conduct 3-D assembly because infants cannot distinguish between the two classes of the atomic building blocks.
In a Chinese patent published as CN 203208689U, a building block was disclosed. The building block comprises a base and a connector, wherein the base is a hexahedron whose top face is installed with fixing holes and whose bottom face, left face, right face, front face and back face are all installed with connecting holes matching the connector. This kind of building block enables children to assemble without classifying the building block. However, when the building block is used to build bottles and cans, the base has to reserve fixing holes to connect with bottles and cans. As a result, the base cannot extend to each side of the building block discretionally. Therefore, the extension of the base is limited. In addition, because the left face, the right, face, the front face, the back face and the bottom face are all installed with only one connecting holes, it's difficult to connect the five faces with the connector at the same time. Furthermore, when a connector is not inserted into its location deep enough, it results in a loose connection between the faces of the base, and the connector can easily move and separate from its location. If the connector is inserted into a connection hole too deep, the other connecting holes cannot be connected.

Building block system and building block units thereof


A data transmission method and apparatus, a computer device and a storage medium are provided. The method includes that: a terminal device selects, from at least two physical uplink shared channels (PUSCHs), a PUSCH satisfying a preset condition; and the terminal device multiplexes first uplink control information (UCI) into the selected PUSCH for transmission. The solution of the disclosure can realize the reasonable selection of a PUSCH, etc.

A 5th generation (5G) new radio (NR) system typically does not support simultaneous transmission of a physical uplink control channel (PUCCH) and a physical uplink shared channel (PUSCH). When a PUCCH and a PUSCH have a same start symbol and a same time-domain length, uplink control information (UCI) may be multiplexed into the PUSCH for transmission. However, other PUSCHs can also be employed to carry UCI. As for how to select a proper PUSCH to carry UCI, no effective solution has been proposed yet.

Data transmission method, apparatus, computer device and storage medium

GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.


A method and apparatus for substantially reducing and virtually eliminating direct current flow through the input transistor(s) of an input buffer circuit for an electret microphone is disclosed. An input transistor is provided and operably connected to an input and an output of the input buffer circuit. The input transistor has a first operating state wherein current flow occurs in a first direction and a second operating state wherein the a current flow occurs in a second direction—opposite that of the first direction. The input transistor is biased to alternately control operation between the first operating state and the second operating state. The alternating, opposing flows of current of the respective operating states cooperate to substantially reduce and virtually eliminate the flow of direct current through the input transistor(s) of the buffer circuit. A reduction in excess noise associated with the input transistor results from the substantially decreased direct current flow through the input transistor(s) of the buffer circuit.

Assisted-listening systems and/or devices, e.g., hearing aids, may utilize an electret microphone for converting sound energy to an electrical signal, signal processing circuitry for processing the electrical signal, and a receiver for converting the electrical signal to acoustical energy. Typically, the signal processing circuitry includes input buffer circuitry having an input impedance to match the output impedance of the electret microphone. The input buffer circuitry often includes a MOS transistor that is subject to undesirable 1/f noise, also called excess noise, or flicker noise.
The present invention is directed to solve these and other problems.


In a franking method and a mail transport system, a franking image is calculated before generation thereof on a mail piece. The franking image includes a franking image key, and for each new franking image, the franking image key therefor is derived from a predecessor franking image key according to a first crypto-algorithm. An integrity check code is also generated based on the new franking image key, a key generation number, an apparatus identifier of the franking device, and a second crypto-algorithm. The franking image includes at least the device identifier, the key generation number and the integrity check code. Upon transport of the mail piece to a sorting center, the franking image is scanned and fees for billing are generated based thereon.

1. Field of the Invention
The present invention concerns a franking method and mail transport system with central postage accounting. The mail transport system is of the type having a data center of the postal carrier, a data center of an operator and at least one franking device. The postal carrier transports the mail pieces franked by the franking device to the mail sorting center. The purpose of the invention is to achieve a secure mail transport system with franking devices of simple design.
2. Description of the Prior Art
A simple solution that assumes either a personal computer (PC) with printer at the sender or a special franking device that is very simple to operate but that thereby requires neither an online connection for every franking nor a security module has previously been missing. Such an offline solution without security module is possible if the mail carrier conducts the postage determination and billing in the framework of its service provision. This means that a suitable software collects the required postage for the posting while the postings are read in the mail sorting center of the mail carrier and the destination address is determined. The software transmits a data set composed of sender and postage amount to the customer account administration of the mail carrier, which bills a customer account of the sender. The billing with the customer (sender) can ensue temporally decoupled from the accounting entry.
This method is called "central postage accounting" because the required postage values are centrally collected in the mail sorting centers of the mail carrier and not, as in the conventional, "decentralized postage accounting", from the senders before commission to post offices or mail boxes.
Known from DE 38 40 041 A1 is an arrangement for franking of postal items with a franking device that prints a value imprint that is accounted by a computer of a central calculation point. This known franking device has a memory whose content is increased with each franking process and whose content can be read out by the user of the franking device. After a cover check, the computer is connected with a giro computer of the postal authority to bill the value imprint. The postal authority runs a mail giro account of the owner of the franking device. The giro computer releases every single value imprint after cover check and billing.
This means that the required postage for the posting is determined and paid before the postings are transported to the mail sorting center of the letter carrier and are read there along with the destination address. No retroactive payment of the service provided is provided in this mail transport system with central postage accounting.
In order to achieve the greatest possible security with regard to the postage accounting both for the mail carrier and for the user, the content of the memory (fashioned as units and sum memory) can be read out only by the user and by the computer of the charging location, and the connection of the computer of the charging location with the franking device is fashioned as a dedicated line (TEMEX) that is always in operation.
For small SOHOs (Small Office Home Office), no truly appropriate electronic franking solutions are yet on the market.
There are online solutions that assume a PC with printer at the sender and establish a data connection to the postage provider with every franking.
Furthermore, there are offline solutions that assume special franking devices with security module in which pre-paid postage values are administered in a manipulation-safe manner (Gerrit Bleumer: Electronic Postage Systems; Springer-Verlag, New York, 2007, Chapter 4.1 Basic Cryptographic Mechanisms, Page 91).
In postal markets worldwide it has been widespread to collect the postage fees decentrally at the input of the postal transport channel, for example via stamp sales or adoption of DV-cleared mailings in post offices and postal agents, via franking machines or franking service stations. For the sender, postage fees are due when the corresponding postage stamps are ordered or delivered, for example in the form of stamps, DV imprints and delivery lists, franking imprints in franking machines and PC franking solutions and franking services, etc.
To the extent that mail carriers transition to registering the processed mail entirely automatically for the purposes of address detection and additional services such as shipment tracking, the possibility results to also collect the due postage fees only upon processing in the mail sorting center. In this accounting model, customers do not have to pay any postage in advance; rather, they receive an invoice for their transported mailings at the end of the month, for example. If necessary, individual transport documentation can be ordered, similar to what is typical today for telecommunication invoices.
In the case of franking machines, this accounting model means that credit downloads are no longer necessary, rather the franking machine serves only to register the desired postal product and calculate and apply a corresponding franking imprint.
This accounting model is called "central postage accounting" in contrast to the previously typical "decentralized postage accounting". Central postage accounting leads to a delayed payment request to the sender. Nevertheless, the designation "postpay" or "pay later" is not characteristic because in conventional, decentralized postage accounting the effective charging of the customer account can also in fact ensue later (for example via debiting methods or credit card payment) than the postal service is provided.
A system and a method for authentication of a mail sender who signs a mailing are known from U.S. Pat. No. 7,110,576. A handwritten signature represents a biometric identity of the sender which the sender applies to a mailing in that he performs a handwritten signature with the aid of a digitizer pen. A mail carrier subsequently scans the signature and can check from a central remote service whether the read signature is valid. The digitizer pen has also originally been registered at the remote service by means of signature tests. In a special design, the digitizer pen writes information into a radio frequency identity device (RFID), wherein the RFID tag is attached to the mailing. As a result of the check of the biometric feature for sufficient similarity of a biometric reference feature performed by the asserted sender, the mail carrier receives a response and attaches the result to the mailing insofar as said result is positive. A biometric sender recognition disadvantageously does not allow a unique device detection. No integrity checksum about the sender recognition is provided whatsoever. Moreover, it would be complicated to ensure that particular technical features such as, for example, an RFID tag are present in the mailing.
A system for identification of mailings by means of RFID is known from U.S. Pat. No. 6,801,833 B2. The mailings are bundled into stacks that are in turn combined in containers that are themselves transported in delivery trucks. Each container is equipped with its own RFID tag that lists all contained containers or mailings, such that every container and every mail piece can be automatically detected and tracked by a central computer at defined points of the mail transport path. The RFID tag can carry the following information features: addressee, sender, shipment ID, integrity checksum of a shipment ID, shipment value or encrypted shipment value. It thereby results that mailings are marked with unique sender identifiers, but in a different form and together with different features than those of the present invention. The sender can deliver a larger quantity of mailings in that he simultaneously provides one delivery list (mailing manifest). In manifest mailing systems, the sender does not determine the required postage amount, rather the delivery post office does this based on the mailing manifest. Therefore only one feature that produces a reference to the associated mailing manifest (permit imprint) must be applied to the individual mailings. In an atypical manner, an RFID tag is provided for this. A mailing ID uniquely identifies the mail piece, wherein the mailing ID can consist of the following parts: sender account number, date, tray ID, piece ID in mail tray, e-mail address of the sender, shipment value, shipment category and mail carrier. An error correction code (CRC) or a digital signature or a message authentication code (MAC) can be used for the identifiers of the mailings and all containers. The integrity checks should prevent that mailings are added to a wrong mail tray or are associated with an incorrect mail tray of an incorrect palette etc. due to technical errors (error correction code) or fraudulent manipulation (digital signature or message authentication code). Therefore an RFID tag must be applied to the individual mailings; however, given the number of senders it is difficult to ensure that the same conditions prevail for all. This is hardly possible when the sender attaches the RFID tag to the mail piece. A wrong adhesive can lead to the signal that an RFID tag detaches. For the sender it is not possible without further measures to read information from the RFID tag. A use of special devices at the sender would be necessary in order to store this information in the RFID tag.
A mail processing system with unique mail piece authorization that is assigned before the entrance of a mail piece into the processing flow of a mail transport service is known from U.S. Pat. No. 5,612,889. A unique shipment ID that serves as an index in a mailing manifest that contains the service address of all committed mailings is stamped on mailings. An address correction of the basis of the mailing manifests is thereby enabled. A commission of mailings is electronically recorded in advance at the mail carrier. For this the sender generates an electronic mailing manifest that he transmits to the mail carrier with cryptographic security. The letter carrier evaluates the information about the expected mailings and their addresses for service, corrects addresses if necessary and determines the required postage fees and subsequently bills the sender. The mail carrier returns a list of shipment IDs to the sender, who prints these on his mailings. The sender subsequently commits his mailings to the letter carrier. The mailing manifest is already present at the mail carrier at this point in time. The shipment ID alone does not designate a sender; rather, it is merely an index in a mailing manifest. This shipment ID only receives a meaning in connection with the mailing manifest. However, the shipment ID is not a unique identifier that can be used on all of the mailings of a franking device and can identify the sender.
From EP 710 930 B1, corresponding to U.S. Pat. No. 5,612,889, it is known to use a unique shipment ID that serves as an index in a mailing manifest that contains the addresses of service or destination ZIP codes of all committed mailings is imprinted on the mailings.
A method for mail good processing and a mail good processing system with hierarchical mail good processing is known from EP 1 058 212 A1, corresponding to U.S. Pat. No. 7,219,084. Private mail carriers that are regionally established relay mailings to super-regional mail carriers for their distribution outside of their region of operation. An identification of the sender ensues by means of a chip card that the customer of the private mail carrier bears and inserts into a card reader of the mail infeed system (mail box) when the customer surrenders the mail. It is provided that the customer receives a receipt for the mail placed in a mail box and initially to be supplied to a first carrier/location. The chip card serves as a customer card that already exhibits an identification number. Each mail good is provided with a machine-readable marking that consists of a number and additional shipping data specific to each mail good. The first carrier transports the mail from the mail infeed station (mail box) to the first location and there franks the letter with a franking imprint and conducts a debit from the customer account at a customer bank and commits the franked letter to a mail distribution center of a second carrier, which transports the mail further. A conventional franking is thus implemented and a conventional mailing manifest is generated after the marking of the mail good. The due postage amount is determined and collected while the mail goods are committed. The corresponding markings are applied to the mail goods in the same process. The marking can contain date and time of the commission and moreover an identification of the customer that has previously been imported from his customer card into the infeed station. This method can be designated as a "semi-central postage accounting". Security checks in addition to the shipment identification and sender identification are not described.
Given decentralized postage accounting, pre-paid electronic money or credit is loaded into the franking device. If manipulation of these funds amount occurs, unpaid postal service can be accessed as a result. This can be difficult to detect by the harmed mail carrier and even more difficult to track back to the individual fraudulent party. The required expenditure via a hardware security module or an online data connection for franking which should prevent the fraudulent manipulations is disadvantageous.

Franking method and mail transport system with central postage accounting


A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.

Modern computer systems typically involve many components interacting with one another in a highly complex fashion. For example, a server installation may have multiple processors, configured either within individual (uniprocessor) machines, or combined into one or more multiprocessor machines. Such computer systems operate in conjunction with associated memory and disk drives for storage, video terminals and keyboards for input/output, plus interface facilities for data communications over one or more networks. The skilled person will appreciate that many additional components may also be present.
The pervasive use of such computer systems in modern day society places stringent requirements on their reliability. For example, it is especially important that the storage, manipulation and transmission of commercially significant information can all be performed correctly, without the introduction of errors. It is therefore of great importance that computer systems are correctly designed and built, and also that they continue to perform properly during their operational lifetime.
This in turn generates the need to be able to reliably test computer systems, especially during initial system design and construction. In addition it is also highly desirable to be able to test machines or components of machines in situ at customer premises, in a production environment. For example, the situation may arise where a processing error is suspected or detected in a customer system, but the source of the error is obscure. Since a typical server installation may be formed from multiple hardware and software components (each of which may potentially be supplied by a different vendor), tracing the error to its original source can be a difficult task. In such circumstances, the ability to show that at least certain components are properly functional can help to isolate the location of the fault. Indeed, even in situations where there is no particular evidence that a fault is present, it can still be desirable to be able to positively demonstrate at a customer location that a particular component (such as a newly installed device) is working properly.
One standard way of checking that hardware components are operating properly is by performing a functional test. In order to achieve this, a particular hardware unit is given some input data to process. It is then confirmed that the output from the unit represents the expected result for the given input data.
Unfortunately, the complexity of modern systems means that such functional testing can suffer from certain limitations. Thus the employment of multiprocessing cores within a single CPU, along with techniques such as register renaming, asynchronous IO, and out-of-order execution, make it difficult to determine in advance the exact processing sequence within a given hardware device. For example, microscopic timing variations from one program run to another may impact the precise execution strategy, such as which operations are performed in which particular processing core, and using which particular registers. (Of course, this will normally be transparent to programs running on the system).
As a result, it is difficult to be completely confident that all components in the system have been properly exercised when performing a functional test. For example, imagine that a particular register is potentially faulty, but that only some executions of a functional test program will actually utilise this register. In this situation, it is difficult to be certain that a positive result for a functional test is due to the fact that the register is indeed properly operational, rather than the register in question simply not being used for that particular execution.
One known alternative (or complement) to functional testing is scan testing, which can help address the above problem. Scan testing is typically applied to semiconductor devices, and is described, for example, in "Fault Diagnosis of Digital Circuits" by V Yarmolik, Wiley, 1990 (ISBN 0 471 92680 9).
FIG. 1 illustrates in simplified schematic form one stage of a generalised semiconductor processing device, in which combinational logic 15 is interposed between flip-flop 12 and flip-flop 14 (the flip-flops may also be replaced by registers and such like). At each clock signal (CLK), the contents of flip-flop 12 are output to combinational logic 15, and the contents of flip-flop 14 are output to the next stage (indicated by arrow C in FIG. 1). Flip-flop 12 then receives new contents from a preceding stage in the device (indicated by arrow A in FIG. 1), while the output of combinational logic 15 is loaded into flip-flop 14.
A complicated semiconductor device can then be regarded as formed from a large number of stages such as shown in FIG. 1. (Note that each stage comprises combinational logic plus a single flip-flop, so that, strictly speaking, FIG. 1 depicts one and a half stages, with flip-flop 12 and logic 15 forming a first stage, and flip-flop 14 then representing the input side of the next stage).
The various stages in a semiconductor device can be connected together in a highly complex manner (rather than just simply having a linear chain of one stage after another). For example, as shown in FIG. 1, combinational logic 15 may receive input for processing from more than one preceding stage (indicated schematically in FIG. 1 by arrows A and B). Similarly, the output from one stage may be split and directed to multiple other stages, including feedback loops and so on.
FIG. 2 illustrates a modification to the circuit of FIG. 1 in order to support scan testing. The components from FIG. 1 are supplemented in FIG. 2 by the addition of two multiplexers, MX 18 and MX 20, which are located in front of flip-flop 12 and flip-flop 14 respectively. Each multiplexer has two inputs, with the selection of the output from the multiplexers being controlled by a SCAN signal.
Considering the operation of multiplexer 20, when the SCAN signal is not set (i.e., has a value 0), then multiplexer 20 outputs to flip-flop 14 the signal that it receives from combinational logic 15. Thus in this mode, the presence of multiplexer 20 is, in effect, transparent, and the circuit operates in the same manner as described in relation to FIG. 1. However, when the SCAN signal is asserted (i.e., has a value 1), multiplexer 20 now outputs its second input, which is received from bypass line 25, which in turn is linked to the output of flip-flop 12. The consequence of this is that in scan mode (i.e., with the SCAN signal asserted), for each clock signal the contents of flip-flop 12 are simply shifted to flip-flop 14, as if combinational logic 15 were not present.
Multiplexer 18 operates in analogous fashion to multiplexer 20. Thus in normal mode, without the SCAN signal being asserted, its output corresponds to input A. However, in scan mode, its output now corresponds to input A′, which represents a direct connection to the output of a preceding flip-flop (not shown in FIG. 2), similar to bypass line 25.
To support full scan testing of a semiconductor device, the configuration of FIG. 2 is repeated for all relevant stages in the device. Thus a sequence of flip-flops is defined, with each flip-flop being preceded by a multiplexer. A first input to each of the multiplexers represents the normal operational input to the flip-flop, while the second input is connected by a bypass line to the preceding flip-flop in the sequence. In scan mode therefore, when the second input to the multiplexer is enforced, the sequence of flip-flops from all the different stages operates in effect as a long shift register, in which the contents of a flip-flop progress to the next flip-flop in the sequence at every clock signal.
The support of scan mode provides a mechanism both to read data into the flip-flops of a semiconductor device, and also to read data out of the flip-flops. One use of this is to verify that the device properly processes a predefined input sequence. The granularity of this testing can be as fine as one processing operation (i.e. one clock cycle).
This is illustrated schematically in FIGS. 3A–D, which each depict a sequence of flip-flops F1, F2, F3, and F4 respectively interlinked by combinational logic CL1, CL2, and CL3. Arrows A and C represent an external input and output facility respectively for the scan sequence, for example through appropriate pins on the semiconductor device. In FIG. 3A there is a binary data sequence of 110 to be input to the device (this is referred to as the input scan vector). Keeping the system in scan mode, after the first clock cycle, the 0 value is read into F1. After the second clock cycle, the 0 value is shifted into F2, while the 1 is read into F1. Next, after the third clock cycle, the 0 and 1 are shifted from F2 to F3 and from F1 to F2 respectively, while the last 1 of the input is read into F1. This leads to the position shown in FIG. 3B, in which the device has now been primed in effect to a predetermined starting state, as specified by the input scan vector.
We now suspend scan mode for a single processing cycle, which leads to the situation in FIG. 3C. This processing operation results in new data values being stored in F2, F3, and F4. The values stored are dependent on the input scan vector and the particular format of logic CL1, CL2, and CL3, and in FIG. 3C are assumed (for illustration) to be 1, 0, and 1. Re-asserting scan mode then allows the data values generated as a result of this processing to be read out in three clock cycles, as per FIG. 3D, to form an output scan vector.
It will be appreciated that analysis of the output scan vector for a given input scan vector provides a very powerful diagnostic tool for confirming that the various parts of a semiconductor device are properly operational. Consequently, scan testing is frequently employed in semiconductor fabrication plants, typically as part of the assembly line process.
Note that although in both FIG. 2 and FIGS. 3A–D, the sequence in which the flip-flops are connected up for scan testing corresponds to the normal operational flow of data through the flip-flops, this will not generally be the case. Indeed, this would actually be impossible for most devices, since as mentioned above, the normal data flow typically includes branches and such like, and so cannot be represented by a single chain or sequence of flip-flops.
As an example of this, although FIG. 2 shows bypass line 25 linking flip-flop 12 to flip-flop 14 in the same direction as data flow for standard processing, it would also be possible for the scan sequence to go in the opposite direction, i.e. a bypass line to go from the output of flip-flop 14 into multiplexer 18. In this case the bypass output of flip-flop 12 would go to some other multiplexer (not multiplexer 20), and likewise the bypass input of multiplexer 20 would come from some other flip-flop (not flip-flop 12).
In devices containing a large number of flip-flops, the bypass lines linking up the flip-flops into a single sequence for scan mode sometimes have to follow rather lengthy and indirect paths. This is primarily because priority in terms of layout is given to optimising the standard data flow of the device (i.e. through the combinational logic). Consequently, the clock rate for scan mode is usually significantly less than the normal clock rate of the device, to avoid any possible problems with signal timing on the relatively long bypass connections. Typically this reduced clock rate is achieved by providing a reduced (scan) rate clock signal to the clock line (CLK in FIG. 2).
As stated above, one of the advantages of scan testing is that it allows the flip-flops of the semiconductor device to be loaded with an arbitrary set of input data. Unfortunately however, this power and flexibility can also represent something of a hazard. An example of where such a problem can arise is illustrated in FIG. 4. (Note that for simplicity, the clock lines and scan mode circuitry have been omitted from FIG. 4).
As shown in FIG. 4, combinational logic 415 drives two flip-flops 412 and 414, each of which is respectively connected in turn to an AND gate 430, 432, and from there as the control input to a tri-state buffer (TSB 90 and 92). The outputs of the two tri-state buffers 90 and 92 are then connected to bus 450.
A tri-state buffer (or driver), as its name suggests, has three possible outputs. If the control input is 1, then the buffer is in an ON state, and simply outputs 0 or 1, mirroring its data input (shown schematically in FIG. 4 as A1 and A2 for TSB 90 and 92 respectively). However, if the control input is a 0, then the gate is in an OFF state and in effect disconnected from the circuit. Consequently, it can neither drive nor load another device.
Tri-state buffers are typically high output devices and can be used to drive a large number of gates. They are frequently employed in computer systems, for example for connecting registers to a common bus. However, the high power output can potentially cause problems. For example, in the circuit of FIG. 4, having both TSB 90 and TSB 92 simultaneously in an ON state may lead to excess current on bus 450, and potentially damage either the bus or devices attached to the bus. To avoid this, the combinational logic 415 of FIG. 4 can be designed to ensure that only one of the two TSBs 90 and 92 is ever in an ON state at any given time. As a further safeguard, an ENABLE signal is supplied to AND gates 430 and 432. When the ENABLE signal is absent, the outputs of the two AND gates are both held low, and so the two TSBs are both kept in a safe (OFF) state.
Considering now the application of a scan test to the circuitry of FIG. 4, the device can be maintained in safe mode, with the ENABLE signal absent, while initially loading the scan vector (corresponding to the transition from FIGS. 3A to 3B). The same also applies during the read out of the output scan vector (corresponding to the transition from FIG. 3C to FIG. 3D). However, the device must be taken out of safe mode, and the ENABLE signal asserted, in order to allow one or more normal processing steps to occur (corresponding to the transition from FIG. 3B to FIG. 3C). Otherwise, it is simply not possible to properly test the operation of the device.
Unfortunately, there is a danger that a particular scan vector may load 1 into both flip-flop 412 and also into flip-flop 414, since the combinational logic 415 that would normally ensure that this cannot happen is being bypassed in a scan test. This in turn may damage the chip, typically through causing excess current flow and the resultant overheating.
In a normal semiconductor fabrication facility it is relatively easy to ensure that the above problem does not arise, since the input scan vector applied on a given line for a given chip can be carefully controlled. However, as explained above, it is sometimes desirable for a field engineer or service operative to be able to perform testing at a customer location. This may include the use of scan testing via some portable electronic equipment to supply the input scan vector, and then to read and analyse the output scan vector.
In such circumstances, the risk of an inappropriate scan vector being used for testing a device is much higher. Thus one danger is that the scan vector becomes corrupted while being stored on the portable electronic equipment, or while transmitted to or from such equipment. A further possibility is that a typical engineer may have to deal with many different components in the field, including different versions or refinements of the same underlying product. Each such component may potentially have its own input scan vector or vectors stored on the portable electronic equipment, and there may be confusion about which particular one to use in a given situation.
If this leads to the wrong input scan vector being used to test a particular component (or possibly the right input scan vector being applied to the wrong component), then as mentioned above, this may result in damage to the device being tested. If such damage is readily noticeable, then the component concerned can be removed or disconnected, although the engineer may well not have a replacement part immediately to hand. A more insidious possibility is that the component suffers less apparent damage, which may cause problems with (intermittent) errors or degraded reliability in the future. In any event, the supplier or service organisation is likely to suffer poor customer satisfaction, and increased expense.
In addition to the risk of accidental damage, there is also a danger that someone may deliberately try to disable or at least degrade a device. One way of attempting such a malicious attack is potentially by inputting an inappropriate scan vector.

Semiconductor device and method and apparatus for testing such a device


A novel reverse-tone mask method which is capable of eliminating metal overburden humps in a metal layer electroplated onto a substrate, is disclosed. Typically, the method includes providing a masking layer on a metal layer such as copper previously electroplated onto a substrate; depositing a photoresist layer on the masking layer; patterning the photoresist layer according to the size and location of the largest metal overburden humps in the metal layer; exposing the overburden humps by etching the masking layer according to the patterned photoresist layer; stripping the photoresist layer from the masking layer; subjecting the metal overburden humps to a first CMP or reverse electroplating process; removing the masking layer from the metal layer; and subjecting the metal layer to a second CMP or reverse electroplating process.

In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers. Besides, single or dual damascene processes are applied to more advanced semiconductor manufacturing technologies. Since Copper is quite difficult to be removed by dry etching method, Cu CMP application is more suitable for both extra Cu removed and further planarization in damascene process.
Deposition of non-conductive layers on the wafer substrate can be carried out using any of a variety of techniques. These include oxidation, LPCVD (low-pressure chemical vapor deposition), APCVD (atmospheric-pressure chemical vapor deposition), and PECVD (plasma-enhanced chemical vapor deposition). In general, chemical vapor deposition involves reacting vapor-phase chemicals that contain the required deposition constituents with each other to form a nonvolatile film on the wafer substrate. Chemical vapor deposition is the most widely-used method of depositing films on wafer substrates in the fabrication of integrated circuits on the substrates.
Due to the ever-decreasing size of semiconductor components and the ever-increasing density of integrated circuits on a wafer, the complexity of interconnecting the components in the circuits requires that the fabrication processes used to define the metal conductor line interconnect patterns be subjected to precise dimensional control. Advances in lithography and masking techniques and dry etching processes, such as RIE (Reactive Ion Etching) and other plasma etching processes, allow production of conducting patterns with widths and spacings in the submicron range. Electrodeposition or electroplating of metals on wafer substrates has recently been identified as a promising technique for depositing conductive layers on the substrates in the manufacture of metal interconnect lines in integrated circuits and flat panel displays. Such electrodeposition processes have been used to achieve deposition of the copper or other metal layer with a smooth, level or uniform top surface. Consequently, much effort is currently focused on the design of electroplating hardware and chemistry to achieve high-quality films or layers which are uniform across the entire surface of the substrates and which are capable of filling or conforming to very small device features. Copper has been found to be particularly advantageous as an electroplating metal.
Electroplated copper provides several advantages over electroplated aluminum when used in integrated circuit (IC) applications. Copper is less electrically resistive than aluminum and is thus capable of higher frequencies of operation. Furthermore, copper is more resistant to electromigration (EM) than is aluminum. This provides an overall enhancement in the reliability of semiconductor devices because circuits which have higher current densities and/or lower resistance to EM have a tendency to develop voids or open circuits in their metallic interconnects. These voids or open circuits may cause device failure or burn-in.
A typical standard or conventional electroplating system for depositing a metal such as copper onto a semiconductor wafer includes a standard electroplating cell having an adjustable current source, a bath container which holds an electrolyte electroplating bath solution (typically acid copper sulfate solution), and a copper anode and a cathode immersed in the electrolyte solution. The cathode is the semiconductor wafer that is to be electroplated with metal. Both the anode and the semiconductor wafer/cathode are connected to the current source by means of suitable wiring. The electroplating bath solution may include an additive for filling of submicron features and leveling the surface of the copper electroplated on the wafer. An electrolyte holding tank may further be connected to the bath container for the addition of extra electrolyte solution to the bath container, as needed.
In operation of the electroplating system, the current source applies a selected voltage potential typically at room temperature between the anode and the cathode/wafer. This potential creates a magnetic field around the anode and the cathode/wafer, which magnetic field affects the distribution of the copper ions in the bath. In a typical copper electroplating application, a voltage potential of about 2 volts may be applied for about 2 minutes, and a current of about 4.5 amps flows between the anode and the cathode/wafer. Consequently, copper is oxidized at the anode as electrons from the copper anode and reduce the ionic copper in the copper sulfate solution bath to form a copper electroplate at the interface between the cathode/wafer and the copper sulfate bath.
The copper oxidation reaction which takes place at the anode is illustrated by the following reaction equation:Cu---->Cu+++2e−
The oxidized copper cation reaction product forms ionic copper sulfate in solution with the sulfate anion in the bath 20:Cu++SO4−−---->Cu++SO4−−
At the cathode/wafer, the electrons harvested from the anode flowed through the wiring reduce copper cations in solution in the copper sulfate bath to electroplate the reduced copper onto the cathode/wafer:Cu+++2e−---->Cu
After the copper is electroplated onto the wafer, the wafer is frequently subjected to a CMP (chemical mechanical polishing) process to remove excess copper (copper overburden) from the electroplated copper layer and smooth the surface of the layer to form the metal interconnect lines. Important components used in CMP processes include an automated rotating polishing platen and a wafer holder, which both exert a pressure on the wafer and rotate the wafer independently of the platen. The polishing or removal of surface layers is accomplished by a polishing slurry consisting mainly of colloidal silica suspended in deionixed water or KOH solution. The slurry is frequently fed by an automatic slurry feeding system in order to ensure uniform wetting of the polishing pad and proper delivery and recovery of the slurry. For a high-volume wafer fabrication process, automated wafer loading/unloading and a cassette handler are also included in a CMP apparatus.
In a typical ECP process, an acidic copper or other metal electroplating bath solution typically includes various additives such as suppressors, accelerators and levelers. In order to meet 65-nm technology gap fill requirements, the additive concentrations are selected to achieve rapid bottom-up fill optimization in high aspect ratio vias and trenches, as well as microscopic and macroscopic uniformity. Consequently, excessive post-ECP copper overburden is common, particularly in the fabrication of metal interconnect lines in dense circuit patterns on wafers.
In situations in which metal interconnect lines are densely-packed, defects such as dishing and erosion are often induced in the metal lines as a result of the post-ECP CMP process to remove overburden, particularly with regard to the use of low-k IMDs (intermetal dielectrics). Dishing is an unintended reduction in the thickness of a material toward the center of a feature. Erosion is the excessive thinning of the metal in the high-density patterned area.
One technique which has been used to reduce copper overburden prior to a post-electroplating CMP process includes subjecting the electroplated copper to reverse ECP, in which the substrate is the anode and loses excess metal from the metal overburden humps. However, while this reverse ECP process is capable of lowering the overburden humps prior to CMP, there is always a risk that gapfilling will be reduced through the process. Accordingly, a novel method is needed for the elimination of copper overburden generated during an ECP process, which method is capable of preventing or at least reducing dishing and erosion effects associated with the post-CMP or reverse-ECP treatment of metal interconnect lines in high-density circuit patterns.
An object of the present invention is to provide a novel method which is capable of eliminating copper overburden generated during an ECP process.
Another object of the present invention is to provide a novel reverse tone mask method which is capable of preventing or at least reducing dishing and erosion in an electroplated metal layer during post-ECP chemical mechanical planarization or reverse electrochemical plating.
Still another object of the present invention is to provide a novel reverse tone mask method which includes the use of a masking layer to expose areas of metal overburden, or "overburden humps", in a metal layer electroplated on a substrate to eliminate the metal overburden humps and planarize the metal layer by chemical mechanical planarization or reverse electrochemical plating.
Yet another object of the present invention is to provide a novel reverse tone mask method in which a mask layer is deposited on an electroplated metal as an isolation layer for the selective exposure and removal of metal overburden humps in the metal.

Reverse tone mask method for post-CMP elimination of copper overburden

Taiwan Semiconductor Manufacturing Co., Ltd.


There are provided bookbinding apparatuses that wrap a bundle of sheets with a cover and form back corners, and have a detecting unit for detecting a wave amount of a bundle of sheets. A type of such an apparatus includes a controller to control a time period to form back corners, based on a result of detection by the detecting unit. Another type of such an apparatus includes a controller to control a pressure applied to form back corners, based on a result of detection by the detecting unit. Still another type of such an apparatus includes a controller to control a time period and pressure applied to form back corners, based on a result of detection by the detecting unit.

As a bookbinding apparatus that binds a book by wrapping a bundle of sheets with a cover, there has been an apparatus wherein the back of a bundle of sheets and a cover are pasted together with a liquid state adhesive or an adhesive tape. For example, Unexamined Japanese Patent Application Publication No. H09-156249 discloses a means wherein the side edges of the bundle of sheets are lined up on a table, the bundle of sheets thus lined up is clamped at a sheet fixing portion, and the bundle of sheets thus clamped at a sheet fixing portion is caused by a sheet fixed portion moving means to reciprocate between a paste spreading roller that spreads paste on the back of the bundle of sheets and a dryer portion that dries the pasted portion forcibly. Further, Unexamined Japanese Patent Application Publication No. 2004-351726 discloses a means wherein adhesives are sufficiently solidified by measuring ambient temperature after coating adhesives on the back and thereby controlling interposing time for clamping.
However, in the apparatus that binds a book by wrapping a bundle of sheets with a cover, when bookbinding is performed by wrapping a bundle of sheets with a cover, if the bundle of sheets is sandwiched in a wavy form, there has been a problem that corners of the spine do not become straight lines and the spine does not become flat, even conducting folding formation (back corner forming) of the spine by pressing a cover against the bundle of sheets.
Means to solve the aforesaid problems is not described in any of the aforesaid Nos. H09-156249 or 2004-351726.

Konica Minolta Business Technologies, Inc.


A fuel injection system having at least two different, high system pressures for an internal combustion engine, includes a first central pressure reservoir for the lower system pressure and includes a second central pressure reservoir, supplied from a high-pressure pump, for the higher system pressure, both pressure reservoirs being connectable by line to the injector of each cylinder, and to increase the efficiency, a two-stage high-pressure pump, by whose lower stage the first pressure reservoir and by whose higher stage the second pressure reservoir are supplied.

This application is a 35 USC 371 application of PCT/DE 00/02550 filed on Aug. 2, 2000.
1. Field of the Invention
The invention is based on a fuel injection system for an internal combustion engine and particularly to such a fuel injection system having at least two high system pressures.
2. Description of the Prior Art
One fuel injection system of the type with which this invention is concerned has been disclosed by European Patent Disclosure EP 0 711 914 A1.
For better comprehension of the ensuing description, several terms will first be explained in further detail: In a pressure-controlled fuel injection system, a valve body (such as a nozzle needle) is opened counter to the action of a closing force by the fuel pressure prevailing in the nozzle chamber of an injector, and the injection opening is thus uncovered for an injection of the fuel. The pressure at which fuel emerges from the nozzle chamber into the cylinder is called the injection pressure, while system pressure is understood to mean the pressure at which fuel is available or is stored in the injection system. The term stroke-controlled fuel injection system is understood in the context of the invention to mean that the opening and closure of the injection opening of an injector are done with the aid of a displaceable valve member, on the basis of the hydraulic cooperation of the fuel pressures in a nozzle chamber and in a control chamber. In a combined fuel metering, a switch is made between various injection pressures, and only one common valve is used for metering the fuel; the switchover can be done either centrally, that is, prior to the fuel distribution to the individual cylinders, or locally, that is, individually for each cylinder.
In the pressure-controlled injection system known from EP 0 711 914 A1, fuel is compressed to a first, high system pressure of about 1200 bar with the aid of a high-pressure pump and is stored in a first pressure reservoir. The fuel at high pressure is also pumped into a second pressure reservoir, in which by regulation of its fuel delivery by means of a 2/2-way valve, a second, high system pressure of about 400 bar is maintained. Via a valve control unit, either the lower or the higher system pressure is directed into the nozzle chamber of an injector. There, by means of the pressure, a spring-loaded valve body is lifted from its valve seat, so that fuel can emerge from the nozzle opening.
In this known injection system, it is disadvantageous that all the fuel must first be compressed to the higher system pressure level so that then some of the fuel can be relieved again to the lower system pressure level.
The fuel injection system of the invention, which can be pressure-controlled or stroke-controlled, in order to increase its efficiency, it is proposed that only the fuel for one pressure reservoir be compressed to the higher system pressure level, while the fuel for the other pressure reservoir is compressed only to the lower system pressure level.
What according to the invention is the lesser fuel quantity at the higher system pressure leads not only to higher efficiency but also to a reduced load on the pump components, and since the higher system pressure need not be sealed off from normal pressure but only from the other high, yet lower, system pressure, this leads to improved sealing and thus less leakage.

Fuel injection system for an internal combustion engine


Dialysis systems and methods for operating dialysis machines (e.g., peritoneal dialysis machines) for conducting dialysis treatments are disclosed. The dialysis system may include a dialysis machine for transferring dialysate to a patient from a dialysate source. The dialysate may flow from the dialysate source through a cartridge or cassette (e.g., a disposable cartridge or cassette) positionable within the dialysis machine. The cassette includes a fluid flow channel. The dialysis machine includes a heating chamber for in-line heating of the dialysate in the fluid flow channel. The fluid flow channel is arranged and configured to provide turbulent flow of the dialysate through the fluid flow channel to provide increased heat transfer from the heating chamber to the dialysate.

Dialysis machines are known for use in the treatment of renal disease. The two principal dialysis methods are hemodialysis (HD) and peritoneal dialysis (PD). During HD, the patient's blood is passed through a dialyzer of an HD machine while also passing dialysate through the dialyzer. A semi-permeable membrane in the dialyzer separates the blood from the dialysate within the dialyzer and allows diffusion and osmosis exchanges to take place between the dialysate and the blood stream. During PD, the patient's peritoneal cavity is periodically infused with dialysate or dialysis solution. The membranous lining of the patient's peritoneum acts as a natural semi-permeable membrane that allows diffusion and osmosis exchanges to take place between the solution and the blood stream. Automated PD machines, called PD cyclers, are designed to control the entire PD process so that it can be performed at home, usually overnight, without clinical staff in attendance.
A dialysis machine, such as a PD machine, may include one or more containers (e.g., bags) containing a fluid (e.g., a dialysate) for patient infusion. In PD machines, for example, tubing as fluid lines are inserted into an abdomen of a patient for flowing fresh dialysate and removing used dialysate, waste, and excess fluid. In bags containing fresh dialysate, the dialysis needs to be heated to body temperature prior to being inserted into the patient.
Methods for heating dialysate include batch and in-line heating, With batch heating, a dialysis machine, such as, for example, a PD machine, may incorporate a heater tray positioned on, for example, the top of the dialysis machine. The heater tray may be sized and shaped to accommodate a heater bag of dialysate (e.g., a 5 L bag of dialysate) for batch heating. The heater tray includes a heating element for heating the dialysate prior to delivery into the patient. In use, dialysate bags may be suspended from hooks on the sides of a cart containing the dialysis machine. The heater bag may be positioned on the heater tray. Dialysate from the dialysate bags may be transferred to the heater bag in batches. For example, a batch of dialysate may be transferred from one or more of the dialysate bags to the heater bag, where the dialysate is heated by the heating element. When the batch of dialysate has reached a predetermined temperature (e.g., approximately 98°-100° F., 37° C.), the batch of dialysate may be flowed into the patient.
With in-line heating, a dialysis machine, such as, for example, a PD machine, may incorporate a heating chamber including one or more heating elements. During use, dialysate from one or more dialysate bags may be transferred directly to the patient through the heating chamber. The dialysate bags may be connected to a cassette, which may be insertable into the PD machine, typically into the heating chamber of the dialysis machine. The dialysate bags may be connected to the cassette via dialysate bag lines and the dialysate bag lines may be used to pass dialysate from dialysate bags to the cassette during use. That is, for example, a heating chamber may be disposed internal to the PD machine. The cassette may be insertable into an opening or cavity formed in the PD machine. The cassette may be configured so that dialysate may continually flow through the cassette, which may be surrounded by the heating chamber to achieve a predetermined temperature before flowing into the patient. For example, in one embodiment, one or more internal heating elements may be positioned above and/or below the opening or cavity, so that when the cassette is inserted into the opening or cavity formed in the PD machine, the one or more heating elements affect the temperature of the dialysate flowing through the cassette. Alternatively, in some embodiments, the heating chamber may be configured so that a portion of tubing in the system may be passed by, around, or otherwise configured with respect to, the one or more heating elements. Thus, in use, the dialysate continuously flows through the cassette "in-line" with the dialysis machine, reaching an acceptable temperature by the application of internal heating elements.
As described above, embodiments of PD machines incorporating in-line heaters may be susceptible to temperature variation of the dialysate. Thus, there is a need in dialysis to deliver dialysate accurately at specific temperatures, for example, at 37 degrees Celsius (e.g., body temperature). Additionally, it is desirable to heat the dialysate to the specified temperature as quickly as possible. By heating the dialysate to the specified temperature in a shorter period of time, the total treatment time can be reduced resulting in greater efficacies and reduced expense. Moreover, it would be advantageous to minimize the size of the cassette needed to heat the dialysate.
It is with respect to these and other considerations that the present improvements may be useful.


An apparatus for collecting failure data includes a failure data collector that initializes one or more test devices by establishing a secondary interface therewith in response to receiving a test device initialization command from a device tester, communicates one or more failure data collection requests to each test device corresponding to a failure data collection command received from the test device, and receives failure data from the test devices via the secondary interface in response to communicating the failure data collection request. In certain embodiments, the present invention includes a failure data storage repository for storing the collected failure data.

1. Field of the Invention
This invention relates to systems, apparatus, and methods for product testing and more particularly relates to systems, apparatus, and methods for collecting failure data.
2. Description of the Related Art
An important phase in the product development lifecycle is product testing. Through product testing, portions of a product that require correction and configuration can be identified. An important step in the product testing phase is failure data collection. Collecting failure data enables the analysis of a product's performance and the formation of additional product development strategies.
Though current failure data collection solutions collect failure data, there exist certain problems. For example, collecting failure data in a test system involving multiple devices often requires an individual to log into each device and collect the failure data logs there from. As the number of devices of a system increases, so does the time and resources required to collect failure data. The failure data collection process is further delayed as the failure data collected from each device often must be inputted or otherwise communicated to an additional device or system for analysis. As the time and resources required for failure data collection increases, the time and resource required to test and develop a product also increases.

Enhanced failure data collection system apparatus and method

International Business Machines Corporation


Various embodiments of the present invention provide a light emitting diode (LED) lighting fixture and methods of installing the same. In various embodiments, an LED lighting fixture may comprise: at least one socket comprising a socket opening; at least one LED positioned substantially within the socket opening; at least one shield member positioned adjacent the at least one socket such that the shield substantially encloses the socket opening; at least one decorative light shade; at least one cover comprising a neck portion having an internal surface, the internal surface defining a cover opening. The cover opening is configured to receive there-through at least a portion of a socket and substantially engage the socket. At least a portion of the cover is configured to substantially engage the decorative light shade. Also, at least a portion of the cover is configured to substantially enclose the LED and shield.

Incandescent bulbs are slowly being phased out in favor of more efficient lighting sources. This has led to an increased use of compact fluorescent bulbs which are more efficient than incandescent bulbs, but which tend to contain dangerous gasses, such as mercury. Additionally, many people find the color temperature of light emitted by compact fluorescents to not be aesthetically pleasing for many applications, such as household lighting in kitchens, bathrooms, and living rooms; some commercial applications; and the like.
Recent advances in manufacturing light emitting diodes (LEDs) combined with the efficiency and long lifetime of LEDs have led to an increase in the availability and affordability of LED lamps. LED lamps offer advantages over compact fluorescent bulbs including longer lifetime and the absence of dangerous gasses. Also, LED lamps may be configured to emit light at a wide variety of color temperatures.
Both incandescent bulbs and compact fluorescent bulbs must be designed to maintain a specific environment within the bulb (e.g., a vacuum or a specific mix of gasses). LEDs, by contrast, can function under regular atmospheric conditions. However, because LEDs are small, solid state devices, LED lamps generally utilize board mounted LEDs. Therefore, the electrical components of an LED lamp may be exposed, providing a possible safety hazard.
Thus, there is a need for LED lighting fixtures which are safe for household and commercial uses. Additionally, there is a need for aesthetically pleasing LED lighting fixtures.

This patent is subject to a terminal disclaimer.


An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

1. Technical Field
The present invention relates to an electronic structure having a wiring pattern and method of designing the wiring pattern so as to control the temperature distribution in a portion of the wiring pattern
2. Related Art
Electromigration due to an electric current in a conductive wire causes current-induced atomic diffusion due to momentum transfer from flowing electrons to host atoms, or a diffusion of electrons in electric fields set up in the wire while the circuit is in operation. Electromigration may cause connections at the end of the wire to degrade. For example, the interconnect may separate from an adjacent via, causing an opening or void in the circuit. In addition, metal at the end of the wire may form extrusions which may cause short-circuiting. Electromigration reliability is measured in terms of mean time to failure (MTF), which is defined as an increase in electrical resistance by a prescribed amount (e.g., 10%) for certain length and width interconnects at an assumed temperature with the application of a constant current density. The temperature may be in a range of 250° to 350° C., and the constant current density may be in a range of 20 to 30 mA/μm2.
Electromigration tests at the package-level are usually performed at a moderate current density (e.g., 20 to 30 mA/μm2) in an oven at a high temperature (e.g., 250 to 300° C.). Electronic structures in these package-level tests are stressed until they reach a certain failure criterion (e.g., 10 to 500 hours) such as a 10% increase in electrical resistance. In performing package-level tests, the time and cost to dice and package the wafers must also be taken into consideration. In these tests, the current density is small enough, so very little Joule heating occurs, eliminating the concern of temperature gradients. At the wafer level, however, Joule heating is used to raise the wire's temperature (e.g., 350–450° C.), which requires a very high current density (e.g., 400 mA/μm2). This method produces undesirable failure modes.
Accordingly, there is a need for an electronic structure having a multilayered substrate and a wiring pattern therein, together with an associated method of designing the wiring pattern, which avoids the undesirable failure modes for wires of the wiring pattern for an assumed current density.

Enhancement of performance of a conductive wire in a multilayered substrate


This invention named "the expanding bi-toothpick with dual controls for pushing and extracting" is mainly composed of the outer rod which is a thin rod designed to extract the food remains in the tooth gap directly and the inner stick which is a thin stick and can go deep into the tooth gap to clean the dregs directly. Besides there is a elastic device between these parts to provide the user dual controls for selecting pushing or picking the stick's end to reach the purpose of cleaning the teeth or the tooth gaps.

The traditional toothpick with a 2 mm diameter section is usually made of plastic as in FIG. 1 or of wood as in FIG. 2. One or both ends of the toothpick are pointed by gradually narrowing the diameter of the tip. The method of extracting food remains from the gaps between the teeth, using this kind of the toothpick, is to insert the toothpick in the gaps directly. This can result in the gap becoming wider because the deeper the toothpick is inserted into the gap, the wider the section of the toothpick would become when the toothpick is used for a period of time. Also the traditional toothpick can not be inserted into a narrow gap near the tooth surface due to different gap shape of everyone. If the tough food remains is picked out by force from the narrow gap, the gap would become wider, the pointed end of the toothpick might be broken and left in the gap, and the teeth or gum might also be injured.
Because the traditional toothpick has the said defects, the floss on a stick as in FIG. 3 was developed for improvement. It is made by a formed rod which has a proper length of a bow with floss tightened on both sides of the bow. However, it is not easy to use the formed rod when putting the floss into the tooth gap. Especially since the user would display unrefined manners by having to open his/her mouth wide to insert the rod. Besides, only the outside incisor can be cleaned by this kind of toothpick, as it is not convenient for cleaning the cheek teeth of the mouth due to the wrong inserting direction to put the floss into the tooth gap. It is furthermore difficult for the users without any tooth gap near the surface of teeth.
The following venders aiming at improving the said defects of the traditional toothpick are continuously developing new devices. For example as in FIG. 4 to form the end of the toothpick into a sheet, or as in FIG. 5 to connect any special device like a brush or a little salience on one side of the toothpick to clean the food remains better or to have the massage function. However, most of the said toothpick with a single rod grip only can pick the outside teeth easily, but not for the inner cheek teeth. If you wanted to extract the food remains from the inner cheek teeth, the toothpick would have to be held upside down, and the holding angle would not be easy to control. Furthermore, it is very ill mannered and also not healthy for the user to have to open his mouth widely to provide space for the toothpick Meanwhile the mouth or tongue could be also pricked by a too long toothpick. Therefore a kind of hook on the toothpick was developed as in FIG. 6. It is made by a bending rod with an adjustable angle function at the end of a toothpick and is able to clean the inner cheek teeth. But the angle between the straight rod and the bending hook could be very big that the toothpick need sufficient space to act. This means the user still has to open his mouth widely to provide enough space for controlling the toothpick. The pointed end of the hook is also the same as a normal toothpick's pointed end which is stretched from reducing gradually the section of the rod. The defects that make the user's tooth gap wider still exist. We can say that this kind of toothpick still can not improve the traditional structure effectively.

2F., No.4., Alley 1, Lane 564, Hsin Fu Rd., Hsinchuang


A backlight tile system is configured to be attached to a wall stud and to be surrounded by tile attached to drywall. The backlight tile system has a rear channel that is mechanically coupled to the wall stud and extending through the drywall. A first lighting strip is detachably coupled to the rear channel with a first adhesive strip. A front channel is detachably coupled to the rear channel with a first magnetic strip. A mosaic tile is directly attached to the front channel. The first lighting strip is configured to render light through the mosaic tile.

The embodiments herein relate generally to home construction.
Prior to embodiments of the disclosed invention, users sought new ways to illuminate kitchen or bathroom areas, without having to constantly change bulbs, or fixtures. Prior art LED tile solutions have difficult processes on how to install tile to be backlit, or by installing LEDs in the grout lines it's difficult to access the LEDs when they burn out. Embodiments of the present invention solve this problem.


A vial closure device, a sample vial incorporating such a vial closure device, and certain methods of using such a vial and closure device. The vial and closure device are intended to contain a gaseous sample or a headspace gas present above a liquid or solid material, so that the gaseous sample or headspace gas can be conveniently analyzed, typically by means of an autosampler connected to an analytical instrument such as a mass spectrometer. Mass spectrometric methods of determining the isotopic concentration of hydrogen and oxygen comprised in aqueous samples contained in vials fitted with such closure devices are disclosed. The vial closure device comprises a hollow body member locatable in the mouth of a vial, and a first seal for making a substantially gas-tight seal between the exterior of said hollow body member and said vial. The hollow body member comprises an aperture and an aperture closing means for closing said aperture when required, and a second seal, through which a gas sampling means may be inserted. The aperture closing means is operable to open the aperture by the insertion of a gas sampling means through the second seal and is operable to close the aperture when the gas sampling means is withdrawn.

Conventional sample vials for automatic samplers typically comprise a small glass vessel which may be closed by a rubber septum held in place by a cap attached to the vessel by a screw thread or by crimping. After sealing, a number of such vials may be loaded into an autosampler which extracts a sample from each vial in turn and sends it for analysis by any desired analytical instrument, for example a chromatograph or spectrometer. Both gaseous and liquid samples may be analysed in this way. In some cases, the vial may be partially filled with a liquid sample but only gas present in the space above the liquid (the headspace gas) may be sampled. Typically, the autosampler will comprise a syringe whose needle, under computer control, is caused to pierce the septum of a selected vial so that a sample of gas or liquid can be withdrawn through the needle and analysed. The septum maintains a gas-tight seal around the needle during this process to prevent contamination. Means are provided to align a second vial with the syringe after the first one has been sampled so that many vials may be sampled automatically in sequence. Means may also be provided for cleaning the syringe between samples.
For the majority of samples, silicone rubber septa may be used to close the vial, but where there is a possibility of reaction of the vial contents with a conventional septum, a septum lined with an inert material, such as PTFE or Teflon, may be employed. These are used with the PTFE lining in contact with the vial contents so that the contents are protected from contact with the rubber septum while the rubber portion still provides a good seal around the needle. A septum made from a solid material such as PTFE is generally incapable of providing an adequate seal around the needle. Unfortunately, lined septa of this type have a limited lifetime because the lining is usually damaged by insertion of the needle, leaving an area of silicone rubber in contact with the vial contents.
This problem has been addressed by the provision of sample vial closure devices which incorporate a shut-off valve as well as a septum. When the valve is opened, a syringe needle may be passed through it to allow the vial contents to be sampled. A silicone rubber septum or seal, through which the needle must also pass, is also provided to seal the vial while the needle is inserted because the valve itself is unable to seal to the needle. Vial closure devices of this type are disclosed in U.S. Pat. Nos. 3,757,981 and 3,603,471, and are commercially available (for example, "Mininert" valves available from Sigma-Aldrich Company Ltd.).
The vial closure device taught in U.S. Pat. No. 3,603,471 comprises a first tube fitted to the screw cap of a conventional glass vial, through which tube a syringe needle may be inserted. A valve stem comprising a second tube is disposed in a bore perpendicular to the axis of the first tube and may be rotated therein by means of an external handle. The second tube comprises a hole perpendicular to its axis which may be aligned with the bore of the first tube by rotation by the handle to open the valve and allow unobstructed passage of a syringe needle through the first tube into the vial. A plug type rubber septum is inserted into the bore of the second tube so that it is pierced by the syringe needle as it is inserted through the device when the valve is open. In this way the contents of the vial are exposed to the septum only for the short time that the valve is open, minimising contamination. U.S. Pat. No. 3,757,981 teaches a variation on this design in which the second tube is replaced by a rod having a bore perpendicular to its axis which may be aligned with the bore of the first tube by sliding the rod. In this device, the septum is placed in the entrance of the first tube. The currently available "Mininert" valves are of this general design.
In some analyses it is necessary to sample only the headspace gas from a vial. One example of this is the measurement of the isotopic composition of hydrogen and/or oxygen in samples of water. In this method a sample of water is placed in a vial which is then sealed. A quantity of carbon dioxide (for oxygen analysis) or hydrogen (for hydrogen analysis) of accurately known isotopic composition is then injected into the vial and allowed to equilibrate with the water. After a suitable time has elapsed, a sample of the headspace gas is withdrawn and its isotopic composition is determined by mass spectrometric analysis. The original isotopic composition of the hydrogen or oxygen present in the water can then be determined from the change in the isotopic composition of the headspace gas during equilibration. Unfortunately, prior attempts to automate this process have not been successful because of losses or contamination of the headspace gas arising from contact with the rubber septum (or a lined septum after it has been punctured to admit the equilibration gas) during the equilibration process. Prior types of valved vials have also proved unsatisfactory, firstly because they cannot easily be used with conventional autosamplers, requiring manual operation of the valve handle, and secondly because the surface area of the material from which the devices are made (PTFE) is so large that contamination or loss of the headspace gas can still occur.

Sample vial and vial closure device for use in gas analysis


A land block (100) has: a side surface (101) (which constitutes a lateral side surface section) forming a groove wall of a lateral groove (40A); and a side surface (102) (which constitutes a circumferential side surface section) forming a groove wall of a circumferential groove (20A). A protrusion (200) protruding from the side surface (101) in the circumferential direction (tc) of the tire and extending in the radial direction of the tire is formed in the region (101a) of the side surface (101) which is located at a position further toward one side of the side surface (101) in the width direction of the tread than the center of the side surface (101) in the width direction (tw) of the tread.

A rubber material having a viscous elasticity follows a hysteresis behavior and thus a tread portion of a tire generates a heat by repeating deformation and contraction due to rolling. If the rubber material constituting the tread portion increases, a hysteresis loss due to a bending deformation or a shear deformation at the time of tire rolling increases. Thus, a tire which is large in thickness of the tread portion is likely to increase in temperature.
In particular, a large-scaled tire employed in a large-scaled vehicle used in mine or construction site or the like is characterized in that the tire is not only large in amount of rubber material used, and but also is used in a heavy loading state, on a rough road surface, and under a severe traction condition, and the tire repeats deformation and contraction, and is thus likely to generate a heat. If the tire reaches a high temperature while in cruising, it causes delamination (separation) between the rubber material forming the tread portion and a belt layer or the like, thus leading to acceleration of an exchange cycle of the tire.
Incidentally, there is conventionally known a method of reducing an amount of rubber material that is a heat generation source by forming a subsidiary groove along a tread widthwise direction at a tread portion, and promoting heat radiation of the tread portion by increasing a surface area of the tread portion (for example, Patent Literature 1).