A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the invention relates to a quantum effect device and a method of manufacturing the quantum effect device, and a semiconductor device obtained by simplifying a binary decision diagram circuit including a single-electron tunneling transistor using semiconductor fine-lines, and a method of manufacturing the semiconductor device.
In these days, there is an increasing demand for decrease of power consumption of LSIs used in personal portable equipment. This is because the decrease of the power consumption of LSIs leads to decrease of power consumption of the entire portable equipment, resulting in elongating an operable time of the equipment driven by batteries. Therefore, the power consumption of a semiconductor device has definitely been decreased.
In a CMOS semiconductor device, which is recently mainly used as a semiconductor device, power consumption P is represented as P=f.multidot.C.multidot.V.sup.2, wherein f indicates an operational frequency of a circuit, C indicates an equivalent capacitance of the entire circuit, and V indicates an operational supply voltage. Therefore, when the operational frequency f is constant, the equivalent capacitance C of the entire circuit and the operational supply voltage V are required to be decreased for the purpose of decreasing the power consumption P. The decrease of the capacitance and the operational voltage corresponds to decrease of the number of carriers to be moved.
Accordingly, in order to decrease the power consumption of a semiconductor device, it is necessary to decrease the number of carriers for transferring a signal. A single-electron tunneling device, which transfers a signal with a single electron, is regarded as an ultimate form for this purpose (Nakazato et: al., IEDM Tech. Digest, p. 487 (1992)). Such a single-electron tunneling device attracts attentions as the most promising device of a post-Si-VLSI. In accordance with the recent development of a fine-line processing technique, it has become possible to form a fine-line structure to the same extent as a wavelength of an electron. Various attempts have been made to express bit information with a device using several electrons and to construct a single-electron tunneling device by extending the present concept of a semiconductor device.
Now, a conventional four-terminal single-electron tunneling device will be described with reference to the accompanying drawings.
FIG. 9(a) is a schematic circuit diagram of a four-terminal single-electron tunneling device to be used in a conventional pseudo CMOS single-electron tunneling circuit (Tucker JR; J. Appl. Phys. 72, 4399 (1992)). As is shown in FIG. 9(a), the conventional four-terminal single-electron tunneling device includes a first tunnel junction 103 connected with a common node 101 at its one electrode and connected with a drain terminal 102 at its another electrode, a second tunnel junction 105 connected with the common node 101 at its one electrode and connected with a source terminal 104 at its another electrode, a first capacitor 107 connected with the common node 101 at its one electrode and connected with a gate terminal 106 at its another electrode, and a second capacitor 109 connected with the common node 101 at its one electrode and connected with a power terminal 108 at its another electrode.
The four-terminal single-electron tunneling device works, for example, as an n-type device when the power terminal 108 is set at a supply voltage VDD and the gate terminal 106 is used as a gate electrode, and as a p-type device when the power terminal 108 is grounded and the gate terminal 106 is used as a gate electrode. Accordingly, a combination of such n-type and p-type four-terminal single-electron tunneling devices can constitute a circuit equivalent to a CMOS circuit. FIG. 9(b) shows simulation results of the operation of the conventional four-terminal single-electron tunneling device, and reveals that a characteristic similar to the Vd-Id characteristic of a MOSFET can be obtained by this single-electron tunneling device.
However, although the conventional single-electron tunneling device transfers a signal with one electron and is regarded as one of the ultimate devices from a view point of the power consumption decrease, it has the following two problems:
The first problem arises in a processing technique. In the case where the device as shown in FIG. 9(a) is realized by using silicon, which is superior in mass-production and material stability, it is necessary to suppress the capacitance of the tunnel junction to be several aF (atto-farad; 1 aF=10.sup.-18 F) as is shown in FIG. 9(b), and hence, a fine-line processing technique on a nm-level is indispensable. In the conventional manufacturing method for a quantum effect device using the electron beam lithography, a line width of approximately 10 nm is the minimum limit. Thus, it is disadvantageously difficult to form a device of several nm or smaller, which can exhibit a remarkable quantum effect. Also, when an electron beam is used, a process damage can be caused on the surface of a silicon substrate, which can disadvantageously degrade the characteristic of the device.
The second problem arises in a circuit technique. The single-electron tunneling device has a different operational mechanism from that of the CMOS technique, which is mainly used for conventional VLSIs, and theoretically has extremely small input and output voltages. Therefore, it is necessary to adopt, in the single-electron tunneling device, a different logical circuit technique from the conventional circuit technique. From this point of view, there is a proposal of forming a binary decision diagram circuit by using a single-electron tunneling transistor (Yoshihito Amamiya, et al., Oyo Butsuri, 64, No. 8, 765-768(1995)).

Quantum effect device, method of manufacturing the same

Matsushita Electric Industrial Co., Ltd.


Business forms are stacked using a cart having first and second portions pivotally movable with respect to each other from a substantially L-shaped configuration to a substantially in-line configuration with each portion having a conveyor associated with it, and a docking station. The cart with the first and second portions in the substantially L-shaped configuration is moved into operative association with the docking station. The cart is lifted and rotated in the docking station so that the second portion is substantially horizontal, and the first portion of the cart is pivoted with respect to the second portion so that the first portion is in the substantially in-line configuration with respect to the second portion. The conveyors are operated so that business forms are moved onto the first portion, and then onto the second portion, with the second conveyor operating at a speed of at least fifty percent greater than the first conveyor (e. g. about ten times as fast). An indicator automatically indicates when the frame is substantially full of forms and then the forms are moved off the first portion and operation of the conveyors stopped, and then the first portion is pivoted back to the substantially L-shaped configuration, the cart is lowered and rotated so that the second portion is substantially vertical, and the cart is manually rolled out of contact with the docking station.

There are many circumstances when it is highly desirable to be able to quickly, efficiently, inexpensively, and with relatively little and inexpensive equipment, stack and transport business forms. The invention fulfills all of these criteria at the same time, using some simple components, and simple operating techniques, by using a manual hand-truck, which is modified so that it can be used both as a conventional hand-truck and also as a conveying apparatus for stacking the forms, the number of components necessary to effectively and simply stack forms is minimized, and by using a docking station that is readily compatible with many conventional business forms handling devices (such as continuous spiral folders) a very practical arrangement may be provided.
According to one aspect of the present invention a cart assembly is provided comprising the following components: A frame having a first portion and a second portion pivotally connected to the first portion. A first conveyor mounted to the first portion, and a second conveyor mounted to the second portion. At least one power source which powers the conveyors. And, rolling supports attached to the frame which allow rolling movement of the frame.
The first and second conveyors are typically powered separately so that the second conveyor moves at least 50% slower than the first conveyor. A single motor with different gearing or pulley sizes can effect this differential powering, or two different motors may be used. First and second conveyors typically comprise conveyor belts, which may be interleaved from one conveyor to the other, although other conventional conveyor structures may be provided.
The first and second portions are pivotally connected so that they are movable from a first position in which the first and second portions are substantially perpendicular to each other (having a substantially L-shaped configuration), to a second position in which the first and second portion conveyors are substantially in-line with each other. First and second levers may each be pivotally connected at first and second ends thereof to the first and second portions respectively, with latches and slots for guiding the movement of one of the pivot pins when the portions are moved out of the substantially L-shaped configuration.
The rolling supports may comprise a first set of rolling supports (such as typical wheels connected to a common axle) on the second portion with a second set of rolling supports (such as casters) connected to the first portion. One or two pairs of shaft stubs may extend outwardly from the second frame portion substantially in-line with each other, for cooperation with a docking station. The second frame portion typically has first and second ends, and a handle is mounted adjacent the first end and the first portion is pivotally connected to the second portion adjacent the second end of the second portion.
According to another aspect of the present invention a material transport assembly is provided comprising the following components: A cart assembly having: a frame having a first portion and a second portion pivotally connected to the first portion, the first and second portions being movable from a first position in which the first and second portions are substantially perpendicular to each other, having a substantially L-shaped configuration, to a second position in which the first and second portion conveyors are substantially in-line with each other; a first conveyor mounted to the first portion, and a second conveyor mounted to the second portion; and rolling supports attached to the frame which allow rolling movement of the frame. And, a docking station dimensioned to receive the cart therein and for moving the cart from a position in which the second portion is generally upright to a position in which the cart second portion is substantially horizontal.
The cart assembly typically is as described above. The docking station preferably comprises means for automatically pivoting the cart frame about a substantially horizontal axis and means for moving the cart frame vertically. The automatic pivoting means may comprise any suitable conventional structure for that purpose, and the means for moving the cart frame vertically may comprise various hydraulic or pneumatic cylinders, motors with linearly moving elements powered thereby, or any other suitable conventional structure.
The material transport assembly may further comprise a stacking table having a horizontal surface, the means for moving the cart frame vertically and pivotally so that the stacking table horizontal surface is substantially horizontally aligned with the second conveyor portion. Also at least one power source is provided which powers the conveyors, mounted on the cart frame. The shaft stubs from the cart second frame portion may be engaged by the docking station for effecting vertical movement as well as automatic pivoting of the cart frame about a horizontal axis.
The invention also relates to a method of stacking business forms using a cart assembly having first and second portions pivotally movable with respect to each other from a substantially L-shaped configuration to a substantially in-line configuration, each portion having a conveyor associated with it, and a docking station. The method comprises the following steps: (a) Moving the cart assembly with the first and second portions in the substantially L-shaped configuration into operative association with the docking station. (b) Lifting and rotating the cart assembly in the docking station so that the second portion thereof is substantially horizontal. (c) Pivoting the first portion of the cart assembly with respect to the second portion so that the first portion is in the substantially in-line configuration with respect to the second portion. And, (d) operating the conveyors so that business forms are moved onto the first portion, and then onto the second portion from the first portion.
Step (d) is practiced so as to move the business forms with the first conveyor at a speed of at least 50% greater than the second conveyor, typically a speed of about ten times greater, thereby compacting the forms by a set ratio speed. There is also typically the further step of placing a backstop on the second portion against which forms are pushed by the first and second conveyors, primarily by the second conveyor. There are also typically the further steps of: (e) automatically indicating when the frame is substantially full of forms and then (f) moving the forms off the first portion and stopping operation of the conveyors, (g) pivoting the first portion back to the substantially L-shaped configuration, and (h) lowering and rotating the cart assembly in the docking station so that the second portion thereof is substantially vertical; and (i) manually rolling the cart assembly with forms thereon away from the docking station.
It is the primary object of the present invention to provide for the simple yet effective transport and stacking of business forms using a simple cart assembly, and/or docking station. This and other objects of the invention will become clear from an inspection of the detailed description of the invention and from the appended claims.


A disc clamping device with self lock elements particularly for DVD-ROM or CD-ROM fixedly maintained on a turntable when disc is rotating in high speed. The device comprises a turntable having a boss on the center for putting disc thereon, and a disc clamping member tightly sleeved on boss having protuberances on periphery wherein protuberances are deformed inwards when biased by disc such that disc can insert through disc clamping member, and then protuberances return to original forms by elastically energized force for clamping disc on turntable. By utilizing this, the purposes of decreasing the umber of parts, easy assembly, and high precision positioning of disc are achieved.

1. Field of Invention
The present invention relates to a slim size disc clamping device particularly for DVD-ROM or CD-ROM mounted in notebook computer being fixedly maintained on a turntable when disc is rotating in high speed.
2. Related Art
Conventionally, the mechanism of employing elastic O-ring or torsion spring to bias steel balls is adopted to clamp disc. This conventional disc clamping device is shown in a top view in FIG. 1A and a sectional view in FIG. 1B respectively. As shown, elastic O-ring 14 is inserted around an outer side of a cylindrical axis 12 projected to the upper surface of turntable 10. A plurality of steel balls 18 (e.g., 3) are equally distributed along the circumference of junction of guide member 16 and turntable 10. In mounting a disc (not shown) onto turntable 10, disc is pressed down to force steel balls 18 to bias O-ring 14 toward the inside by the guidance of guide member 16 until in place. At this time, the inner periphery of disc is fixedly maintained between guide member 16 and turntable 10 by the expansion of O-ring 14 which biases steel balls 18 to original positions. The drawbacks of such design are that O-ring 51 loses its elasticity as time passes, and O-ring 14 and steel balls 18 may not engage well due to poor manufacturing quality. As a result, a fix clamp of disc is not achievable.
Another prior art disc clamping device is shown in sectional views of FIGS. 2A and 2B. As shown in FIG. 2A, disc 20 is placed on top of insertion portion 22 of turntable 10a for clamping onto turntable 10a. In mounting, press down disc 20 to force it to contact with turntable 10a so as to clamp disc 20 between disc-clamping piece 24 and turntable 10a by the guidance of disc-clamping piece 24. Then turntable 10a immediately bounces up when disc 20 is not pressed for fixedly maintaining disc 20 between and by disc-clamping piece 24 and turntable 10a (see FIG. 2A). This design is without the problem of lacking elasticity of spring as time passes. But this is still unsatisfactory for the purpose for which the present invention is concerned because the radially positioning of disc is poor. It is known that not all central holes of discs have the same tolerance. However, above design does not provide a mechanism to compensate such tolerance for providing a precise positioning. As a result, such disc clamping device is not applicable to high precision positioning products such as DVDs.
It is thus an object of the present invention to provide a disc clamping device with self lock elements particularly for DVD-ROM or CD-ROM being fixedly maintained on a turntable when disc is rotating in high speed.
The advantages of the present invention are realized by providing a disc clamping device comprising a turntable having a boss on the center for putting disc thereon; and a disc clamping member tightly sleeved on boss of turntable having a diameter nearly the same as that of the center hole of disc, and disc clamping member having a plurality of protuberances on periphery wherein protuberances are deformed inwards when biased by disc such that disc can insert through disc clamping member, and then protuberances return to original forms by elastically energized force for clamping disc on turntable.
In one aspect of the invention, the number of protuberances is three. Protuberances are spaced apart by 120 degrees each other. Protuberances may be formed integrally with disc clamping member, or alternatively formed of copper separately. An annular pad is provided on the outer periphery of the top surface of turntable for providing a frictional force to disc when rotating. Disc clamping member includes a plurality of spaced cantilever members along its periphery wherein a protuberance is located on the outer surface of a corresponding cantilever member. Preferably, the line from protuberance to the center of disc clamping member is at an angle about 10 to 60 degrees with respect to the line from base of cantilever member to the center of disc clamping member. Also, the line from the point of protuberance contacting disc to the top of protuberance is at an angle about 10 to 80 degrees with respect to a downward vertical line originated from the top of protuberance.
In another aspect of the invention, turntable is a copper and disc clamping member is a plastic. In mounting disc on disc clamping member, press down disc to force circular protuberances to bias cantilever members to cause it to deform inwards. Then disc inserts through disc clamping member to pass protuberances until contacting with pad. At this time, protuberances immediately expand outward to return to original forms by elastically energized force of cantilever members. As such, disc is clamped by protuberances and pad. Thus, disc is secured on turntable.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Disc clamping device with self lock elements

Industrial Technology Research Institute


A fixing device includes a fixing rotator, a pressing rotator, an oil applicator, a first adjuster, a surface modifier, a second adjuster, and a processor. The fixing rotator contacts a recording medium bearing a toner image. The pressing rotator forms a fixing nip with the fixing rotator. The oil applicator is pressed against at least one of applied members of the fixing rotator and pressing rotator. The first adjuster adjusts contact/separation of the oil applicator with respect to the applied member. The surface modifier contacts the fixing rotator to modify a surface thereof. The second adjuster adjusts contact/separation of the surface modifier with respect to the fixing rotator. The processor allows the surface modifier to modify the fixing rotator surface after the oil applicator contacts the applied member, and the oil applicator to separate from the applied member after the surface modifier is separated from the fixing rotator.

Technical Field
Exemplary aspects of the present invention relate to a fixing device and an image forming apparatus incorporating the fixing device.
Related Art
Contemporary image forming apparatuses such as copiers, printers, facsimile machines, or multifunction peripherals having two or more copying, printing, and facsimile functions are expected to improve energy saving efficiency, accelerate operation speed, and enhance image quality. However, thermal efficiency of a fixing device used in the image forming apparatus needs to be improved, and heat of various rollers in the fixing device needs to be controlled with precision to meet such recent market demands.
The image forming apparatus, which employs an image transfer method or a direct method, performs an image forming process to form an unfixed toner image on a recording medium (also referred to as a recording material or paper) such as a recording material sheet, printing paper, photosensitized paper, or electrostatic recording paper. The image forming process includes electrophotographic recording, electrostatic recording, and magnetic recording. A fixing device that employs a contact heating method is widely used to fix the unfixed toner image on the recording medium. The contact heating method includes a heating roller method, a belt fixing method, a film heating method, and an electromagnetic induction method.
Herein, the fixing device employing the heating roller method includes a fixing roller and a pressing roller as a rotation roller pair as a basic configuration. The fixing roller includes a heat source such as a halogen lamp, the temperature of which is adjusted to a predetermined temperature. The pressing roller is pressed by the fixing roller. A recording medium is conveyed to a contact portion called a fixing nip (also referred to as a nip portion) between the rotation roller pair, so that an unfixed toner image is fixed with heat and pressure applied by the fixing roller and the pressing roller.
On the other hand, the fixing device employing the belt fixing method includes a fixing roller disposed opposite a pressing roller, and an endless fixing belt (a fixing rotator) looped around the fixing roller and a heating roller. In a fixing nip formed by contacting the pressing roller and the fixing belt, heat from the heating roller is applied to a recording medium via the fixing belt, and an unfixed toner image is pressed to the recording medium to fix the unfixed toner image on the recording medium.

Fixing device and image forming apparatus


An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

The field of the invention relates to systems and methods for shared access between an embedded controller and a host processor to modules including but not limited to input/output modules. Embedded controllers are designed for specific tasks and/or to control a particular system, as part of a larger device or system. Embedded controllers perform functions such as system monitoring and control, verification of correct system operation (health monitoring), and/or troubleshooting and error recovery, handled when the host processor is off or malfunctioning or as a background fail safe operation when the host is active. As embedded controllers and host processors increasingly function together in controlling a computer environment, sharing access between embedded controllers and host processors to different elements of the computer environment becomes increasingly important.
There follows a brief description of prior art input/output modules. Input/output ("I/O") modules allow the connection of peripheral devices to the computer (i.e., host processor and or embedded controller), typically through a bus interface. I/O modules commonly include one or more of the following: keyboard and mouse controller, floppy disk controller, serial ports, parallel ports, infrared ports, and general purpose input/output ports. It should be understood that the above list is not exhaustive and that I/O modules can include other modules which allow the connection of peripheral devices. The I/O modules are commonly but not necessarily integrated into one chip (i.e., an "input/output chip") on the motherboard of a computer. However, other connection configurations of certain or all of the modules, for example, through a bus extension, are also possible. It should be evident that input/output chips include other modules in addition to input/output modules to improve the functionality of the chip including but not limited to: clock modules, power management modules, configuration, bus extensions, interfaces, reset circuitry, etc.
A representative prior art I/O chip 10 PC87364 "128-Pin LPC Super I/O with Extended Wake-Up and Protection Support" of National Semiconductor Corporation of Santa Clara, Calif., is shown in FIG. 1. Data sheets for chip 10 are available on the World Wide Web at www.national.com. Modules typical to input/output chips which are included in chip 10 are a serial port 12, an infrared port 14, a plurality of general purpose I/O ports (GPIO ports) 16, a floppy disk controller 18, a parallel port 20, a configuration module 24, a keyboard and mouse controller 30, an access bus interface 36 and a system wake-up control (SWC) 38. Other components particular to chip 10 include an interrupt serializer 28, a fan speed control and monitor 32, and a watchdog timer 34. Power sources VDD (main) 40, VSB (standby) 44, and VBAT (battery backup) 42 supply power to chip 10. Part of GPIO ports 16, and optionally part of SWC 38 are powered by VSB 44. VBAT 42 provides backup (using a battery) to critical events and configurations in SWC 38 and to other parts of chip 10, while VSB is off. All other components of chip 10 are powered by VDD 40. A host processor 26 is connected to an internal bus 54 through a low pin count (LPC) interface 22, allowing host processor 26 to access modules 12 to 22 and modules 28 to 38, and configuration 24. Modules 12 to 22 and modules 28 to 38 are collectively noted as a typical module 45 in FIG. 2.
Although the description below for FIG. 2 and FIG. 3 refer to components of chip 10 for illustrative purposes, the schemes shown in FIG. 2 and FIG. 3 are common to many prior art chips.
Prior art FIG. 2 shows a system 46 whereby host processor 26 accesses typical module 45 through an LPC interface 22 that converts an LPC bus to a data bus 56, an address bus 55, and a control bus 53. Typical module 45 is enabled based on the value of module enable bits 52 within registers in configuration 24.
To access particular module 45, host processor 26 sends the address 55 of a specific register 47 within particular module 45. Address 55 includes high bits which are compared by a comparator 49 with the base addresses+size 48 for each module 45 that are stored (i.e., configured) in configuration 24. The size provides a boundary on the highest possible address for each module 45, and the base address provides the lower boundary of addresses for each module 45. If no configuring process takes place, the base address of typical module 45 is retained at default value. As a result of the comparison, a module select (or as sometimes called "chip select") 50 for particular module 45 is generated and placed on internal bus 54. Control signals 53 are converted to internal bus control 51 (i.e., in the format required by internal bus 54). In addition, address 55 includes lower bits which relate to the offset address. The offset address is specified with respect to the base address of particular module 45, and allows the identification of specific register 47 within particular module 45. The data 56 can then be read or written to specific register 47.
In certain modules 45, the approach to specific register 47 within particular module 45 is via a module-specific index register 59 (shown as optional in FIG. 2 using a broken line), and a module-specific data register 61 (also shown as optional in FIG. 2 using a broken line). Index register 59 and data register 61 are located at different offset addresses from the base address of module 45. For example, index register 59 can be located at offset zero ("0") and data register 61 at offset one ("1"). In this case, two transactions are necessary to read or write. First, address 55 of index register 59 is sent along with data 56 to be written to index register 59 (in this case the data 56 is the index value of specific register 47). Next, address 55 of data register 61 is sent and data 56 can then be written to or read from specific register 47 via data register 61 (as is well known in the art, data register 61 is a "dummy register" and contains a duplicate of the contents of specific register 47). Note that if the index is already set to the correct value, there is no need to re-write the address prior to the successive data access operation.
Prior art FIG. 3 shows the mechanism for setting the configuration of typical module 45. Device configuration 24, includes a configuration index register 73, a configuration data register 74, global configuration registers 64 and a logical device number (LDN) configuration register 66. Index register 73 is located at address 2Eh or 4Eh of input/output address space 58, and data register 74 is located at address 2Fh or 4Fh of input/output space 60. Configuration registers related to typical module 45 include logical device specific configuration registers 70 organized in banks 69. Therefore, to access logical device specific configuration registers 70, two-dimensional indexing is required. In order for host processor 26 to access one of logical device specific configuration registers 70 relating to one of modules 45, one of banks 69 (i.e., logical devices 45) is selected by first specifying the index of LDN configuration register 66 in configuration index register 73, and then specifying the logical device number of one of modules 45 in configuration data register 74. Host processor 26 next chooses a logical device specific configuration register 71 by writing the index of configuration register 71 in configuration index register 73. The configuration data is then written to register 71 through configuration data register 74.
Note that in the above description of chip 10, there is no interface for an embedded controller and specifically no means for an embedded controller to access typical module 45 and configuration 24.
Prior art FIG. 4 shows a schematic 80 of the host bus interface of PC87570 (chip 82) of National Semiconductor Corporation of Santa Clara, Calif. Data sheets for chip 82, a keyboard and power management controller are available on the World Wide Web at www.national.com. Chip 82 includes an embedded controller core 84, which accesses a host bus interface 86 through a core bus 85 to ISA bridge 87. An external flash memory 81 is accessible by core 84 through a core bus 85 and a bus interface unit 89. When a host processor 98 asserts certain signals, host bus interface. 86 identifies the signals and requests control over core bus 85 using a core bus master mechanism (not shown in FIG. 4), thereby allowing host processor 98 to access flash memory 81 through host bus interface 86, core bus 85 and bus interface unit 89. The host transaction is extended using a 'not ready' indication (not shown in FIG. 4) until the transaction is completed.
After reset, core 84 in chip 82 needs to finish various system configurations and therefore blocks access of host processor 98 to shared memory 81. After core 84 has completed various system configurations, core 84 removes the access block and enables host processor 98 to access shared memory 81. Until the configurations are complete, if host processor 98 attempts access to shared memory 81, host processor 98 is indicated to wait using a 'not-ready' indication, or optionally a signal is sent to reset host processor 98. Note that no indication is given to core 84 if host processor 98 attempts access to shared memory 81 when shared memory 81 is blocked. Note also that the blocking of shared memory 81 occurs only during an initialization process.
A core and host arbitrator 88 arbitrates between host processor 98 and core 84 the access to the shared a Real Time Clock (RTC) module 100 on a resident device bus 91. A host access 96 to RTC module 100 and a core access 94 to RTC module 100 are illustrated by broken lines having an arrow at each end. RTC module 100 includes an index register RTCCA 102 and a data register RTCCD 104, which are used to access all internal registers 103 of all RTC banks 105. Index register 102 and data register 104 are located at consecutive addresses. Index register 102 holds the index of particular RTC register 103 that is read or written to through data register 104. Bank 105 is selected using the CRA register 101. In chip 82, both host processor 98 and core 84 can access registers 102 and 104.
Assuming that bank 105 has already been indicated through CRA register 101, host processor 98 accesses particular internal register 103, by sending the host address of index register 102 on a host bus 92 along with data. The address is translated into a chip select and address offset as explained with reference to FIG. 2. The data (which in this case is the index value of internal register 103) is then written to index register 102. Host processor 98 then sends the host address of data register 104. The data of particular register 103 can then be written or read through data register 104. Similarly, core 84 can access particular internal register 103 through index register 102 and data register 104. Core 84 sends the core address of index register 102 on core bus 85 along with the data. The data (in this case the index value of internal register 103) is then written to index register 102. Core 84 then sends the core address of data register 104. The data of register 103, which corresponds to the index value, can then be written or read through data register 104.
Note that although the core address sent by core 84 and the host address sent by host processor 98 may not be identical, two decoders (not shown in FIG. 4), one for core 84 and one for host processor 98 decode the two addresses to the same register.
A register CTS1 90 is accessed by core 84 and used to control host bus interface 86 with respect to RTC module 100 access.
CTS1 90 is shown in more detail in prior art FIG. 5. A lock RTC host access (LKRTCHA) 106 arbitrates the usage of RTC module 100 between host processor 98 and core 84. When LKRTCHA 106 is reset to zero ("0"), core 84 can not access registers 102 and 104 (and therefore can not access all internal registers 103), and only host 98 can access registers 102 and 104. When LKRTCHA 106 is set to one ("1"), host processor 98 can not access registers 102 and 104 (and therefore can not access all internal registers 103), and only core 84 can access registers 102 and 104. An RTC lock violation (RTCLV) 108 is set as an indication to core 84 if host processor 98 attempts to access RTC module 100 when LKRTCHA 106 is set to one ("1"). In parallel, the host access is completed in the following way: read access return a fixed value of zero and write access is completed ignoring the data written.
Other components of CTS1 90 will be mentioned only in passing. An RTC master reset (RTCMR) 107 when set to one ("1"), allows core 84 to access RTC protected memory. A host power on (HPWRON) 109 allows core 84 to monitor host power on, and a host master reset active (HMRA) 110 enables core 84 to monitor the status of a host master reset.
It should be noted that the RTC sharing scheme of chip 82 provides only an access block option, i.e., either core 84 or host processor 98 have exclusive control of RTC module 100. Chip 82 therefore allows shared access (exclusively one at a time) of host processor 98 and core 84 to RTC module 100. In order to prevent conflicts, host processor 98 and core 84 can not access RTC module 100 concurrently.
An example of a possible conflict that could occur if concurrent access were allowed to RTC module 100 (i.e., if access by one of core 84 or host processor 98 were not blocked) is the following scenario: Recall from the discussion with reference to FIG. 2 that (assuming bank 105 has already been selected) two additional transactions are necessary for either core 84 or host processor 98 to read to or write from internal register 103 because of the index/data registers. In a first host transaction, host processor 98 writes the index of internal register 103 to index register 102. Then, in a first controller transaction, embedded controller core 84 writes the index of another internal register 99 to index register 102. Finally, in a second host transaction, host processor 98 sends or receives data supposedly for internal register 103 which is instead written to or read from register 99 (because the index value of register 99 is in index register 102).
In addition, shared access is only implemented for one specific pre-defined input/output module (i.e., RTC 100 of chip 82) on resident device bus 91, even though chip 82 also includes other modules such as a keyboard controller, and a power management device. Also, there is no indication to host processor 98 when host processor 98 attempts to access RTC module 100 while LKRTCHA 106 is set to one ("1"). Only one indication is provided (RTC lock violation RTCLV 108) and only to embedded controller core 84.
Chip 82 is powered by a single voltage source (VCC). In addition, there is a battery backup for RTC module 100.
FIG. 6 shows another example of prior art sharing of input/output functions between an embedded controller 113 and a host processor 114. Chip 115 FDC37N972, is a product of Standard Microsystems Corporation (SMsC) headquartered at Hauppauge, N.Y. Data sheets of chip 115 can be found on the World Wide Web at www.smsc.com. Embedded controller 113 can disconnect access of host processor 114 to parallel port connector 116 by writing a bit 112 in a parallel port controls register of controller 113. A multiplexer 117 controlled by bit 112 selects either host processor 114 or embedded controller 113 for access to parallel port connector 116. Embedded controller 113 has no access to any other input/output functions. Chip 115 is powered by one of two voltage sources (VCC1, VCC2). Chip 115 includes two separate buses, one for host processor 114, and the other for controller 113, with each bus powered by a different voltage source.
W83627HF is an input/output chip developed by Winbond Electronics Corporation of Taiwan whose World Wide Web site www.winbond.com includes data sheets for W83627HF. In addition to the traditional I/O functions, W83627HF has integrated into it a hardware monitor 119. Refer to FIG. 7 which shows the access scheme to hardware monitor 119. The functions of hardware monitor 119 are controlled by a host processor 118 through an LPC bus 126. An embedded controller core 120 also controls hardware monitor 119 through I2C bus 122.
FIG. 8 shows the access scheme through LPC bus 126. A hardware monitor index register 128 includes a bit 130 which is set to one ("1") by a write to index register 128. Bit 130 is cleared by a read or write from/to a data register 129. Bit 130 can be seen from both LPC bus 126 and I2C bus 122. Bit 130 should be checked prior to beginning an LPC bus 126 or I2C bus 122 transaction (see FIG. 7). For the scheme to work, either host processor 118 or embedded controller core 120 must perform the following sequence prior to any data access (read or write), without exception even for successive data accesses (i.e., the index even for successive data accesses must be rewritten each time). A read or write starts by reading index register 128 and checking that bit 130 is clear. If bit 130 is not clear, the operation is repeated until bit 130 is clear. Once bit 130 is found to be clear, the desired index is written to index register 128. Index register 128 and bit 130 are both read to check that the address is right and bit 130 is set. If bit 130 is not set, the process starts at the beginning. If bit 130 is set, one data item may be read or written from/to data register 129. Even using the above scheme, the mechanism will fail if both host processor 118 and embedded controller core 120 try to read and/or write locations with the same index value.
There is a need in the art for systems and methods for allowing shared access by an embedded controller and a host processor to modules both internal to chips and off bus extensions, including but not limited to modules within input/output ("I/O") chips or accessible through bus extensions off input/output chips. There is also a need in the art for systems and methods for allowing shared access by an embedded controller and a host processor to more than one module. There is also a need in the art for systems and methods for allowing concurrent access to certain modules by an embedded controller and a host processor. There is also a need in the art for a protocol which allows access by an embedded controller to more than one module.

Sharing of functions between an embedded controller and a host processor


A dictionary data structure is described. The data structure is made up of first, second, and third tables. The first table is comprised of entries each representing a natural language term, each entry of the first table containing a term ID identifying its term. The second table is comprised of entries each representing a definition, each entry of the second containing a definition ID identifying its definition. The third table is comprised of entries each representing correspondence between a terminate definition defining the term, each entry of the third table containing term ID identifying the defined term and a definition ID identifying the defining definition. The contents of the data structure are usable to identify any definitions corresponding to a term.

Many fields of business are subject to extensive, complex bodies of regulations. As one example, the field of Information Technology is subject to myriad international and local laws, administrative rules and guidelines, standards, and other forms of regulation relating to data security and privacy, export control, data formats, identity authentication and authorization of people and machines, among other subjects.

Unified Compliance Framework (Network Frontiers)


A fabrication method of a semiconductor device with the CMOS structure, which suppresses the sheet resistance of silicide layers of a refractory metal in an n-channel MOSFET at a satisfactorily low level while preventing the junction leakage current in a p-channel MOSFET from increasing. An n-type dopant is selectively ion-implanted into surface areas of a first pair of n-type source/drain regions and a surface area of a first gate electrode in an NMOS region at a first acceleration energy, thereby forming a first plurality of amorphous regions in the NMOS region. The n-type dopant is ion-implanted into surface areas of the second pair of p-type source/drain regions and a surface area of the second gate electrode in a PMOS region at a second acceleration energy lower than the first acceleration energy, thereby forming second plurality of amorphous regions in the PMOS region. The second acceleration energy is set in such a way that bottoms of the second pair of p-type source/drain regions in the PMOS region are not substantially shifted due to ion implantation of the n-type dopant for forming the second plurality of amorphous regions.

1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and more particularly, to a fabrication method of a semiconductor device with the Complementary Metal-Oxide-Semiconductor (CMOS) structure, in which silicide layers of a refractory metal are formed in self-alignment in the surface areas of gate electrodes and source/drain regions of n- and p-channel MOS Field-Effect Transistors (MOSFETs).
2. Description of the Prior Art
A conventional fabrication method of a semiconductor device of this sort is shown in FIGS. 1A to 1C, which is disclosed in the Japanese Non-Examined Patent Publication No. 8-78361 published in 1996.
This method employs the known Self-Aligned siLICIDE (SALICIDE) process and provides refractory-metal silicide layers with low electric resistance while preventing the short circuit between wiring lines.
In this method, amorphous silicon layers or regions are formed in the surface areas of impurity-doped silicon regions of a single-crystal silicon (Si) substrate. Next, a refractory metal such as titanium (Ti) is deposited on the amorphous silicon layers or regions while heating the substrate to a temperature at which no silicide of the deposited refractory metal is generated. Finally, the substrate is subjected to a heat treatment for silicidation reaction so that the amorphous silicon layers react with the deposited refractory metal to thereby form silicide layers of the deposited refractory metal.
First, as shown in FIG. 1A, a field oxide layer 104 with a thickness of 200 to 400 nm is selectively formed in the surface area of a p-type single-crystal silicon substrate 101 by the selective oxidation technique, thereby defining an NMOS region 121 where an n-channel MOSFET is formed and a PMOS region 122 where a p-channel MOSFET in the surface area of the substrate 101.
Next, a p-type well region 102 and an n-type well region 103 are formed in the NMOS and PMOS regions 121 and 122 by the ion-implantation technique, respectively.
Then, gate oxide layers 105 with a thickness of 3 to 6 nm are formed on the exposed surfaces of the NMOS and PMOS regions 121 and 122 by the thermal oxidation technique. Subsequently, polysilicon gate electrodes 106 with a thickness of 150 to 250 nm are formed on the gate oxide layers 105 in the NMOS and PMOS regions 121 and 122 by the Chemical Vapor Deposition (CVD), photolithography, and etching techniques.
Pairs of oxide sidewalls 107 with a width of 80 to 150 nm are then formed on the gate oxide layers 105 at each side of the corresponding gate electrodes 106 in the NMOS and PMOS regions 121 and 122 by using the CVD and anisotropic etching techniques.
An oxide layer 108 with a thickness of 5 to 10 nm is formed to entirely cover the NMOS and PMOS regions 121 and 122 by the CVD technique.
Further, a pair of n-type source/drain regions 109 and a pair of p-type source/drain regions 110 are formed in the NMOS and PMOS regions 121 and 122 through the oxide layer 108 by the ion-implantation technique and the annealing technique, respectively.
When the pair of n-type source/drain regions 109 are formed in the NMOS region 121, arsenic (As) ions as an n-type dopant are selectively implanted into the NMOS region 121 with a dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 at an acceleration energy of 20 to 50 keV while the PMOS region 122 is covered with a patterned photoresist film (not shown). When the pair of p-type source/drain regions 110 are formed in the PMOS region 122, boron difluoride (BF.sub.2) ions as a p-type dopant are selectively implanted into the PMOS region 122 with a dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 at an acceleration energy of 20 to 50 keV while the NMOS region 121 is covered with a patterned photoresist film (not shown).
The pair of n-type source/drain regions 109 and the pair of p-type source/drain regions 110 thus formed are then subjected to an annealing process for activating the implanted arsenic and boron atoms. This annealing process is typically carried out at a temperature of 1000 to 1050.degree. C. for 10 to 30 seconds.
The state at this stage is shown in FIG. 1A.
Following the annealing process, as shown in FIG. 1B, arsenic ions are implanted again into the pairs of the n- and p-type source/drain regions 109 and 110 and the gate electrodes 106 in the NMOS and PMOS regions 121 and 122 through the oxide layer 108, as indicated by vertical arrows 115. Thus, amorphous silicon regions 106a are formed by the surface areas of the gate electrodes 106 in the NMOS and PMOS regions 121 and 122 and at the same time, amorphous silicon regions 109a and 110a are formed by the surface areas of the pairs of n- and p-type source/drain regions 109 and 110 in the NMOS and PMOS regions 121 and 122, respectively.
The reason because arsenic is selected for the ion-implantation species in this process is that arsenic has a largest mass number within the popularly-used n-type dopants in the semiconductor device fabrication and therefore, arsenic is optimum for this purpose.
Further, the oxide layer 108 is removed to expose the amorphous silicon regions 106a of the gate electrodes 106 and the amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110 from the oxide layer 108. Then, a titanium (Ti) layer (not shown) with a thickness of 20 to 40 nm is deposited to cover the entire surface of the substrate 101 by the sputtering technique. The titanium layer is contacted with the exposed amorphous silicon regions 106a of the gate electrodes 106 and the exposed amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110.
The titanium layer and the entire substrate 101 are subjected to a heat treatment at a temperature of 650 to 750.degree. C. for 10 to 30 seconds, thereby reacting the titanium layer with the amorphous silicon regions 106a of the gate electrodes 106 and the amorphous silicon regions 109a and 110a of the pairs of source/drain regions 109 and 110. Through this heat treatment, the titanium silicide (TiSi.sub.2) layers 111 with a thickness of 30 to 60 nm are formed in self-alignment to the gate electrodes 106 and the pairs of source/drain regions 109 and 110 due to silicidation reaction, respectively.
The unreacted titanium layer is then removed. The state at this stage is shown in FIG. 1C.
Finally, the titanium silicide layers 111 are subjected to a heat-treatment at a temperature of 800 to 900.degree. C. for 10 to 30 seconds, thereby causing the phase transition in the layers 111 to decrease their electric resistivity.
With the conventional fabrication method of a semiconductor device shown in FIGS. 1A to 1C, however, the following problem will occur.
There is a tendency that the silicidation reaction of titanium (Ti) with silicon (Si) into which arsenic (As) ions have been implanted with the dose of 2 to 5.times.10.sup.15 atoms/cm.sup.2 is more difficult to progress than the case where boron difluoride (BF.sub.2) ions are implanted thereinto instead of arsenic. Therefore, when the acceleration energy of arsenic ions is low, the thickness of the titanium silicide layers 111 in the NMOS region 121 becomes small compared with the titanium silicide layers 111 in the PMOS region 122.
In this case, the titanium silicide layers 111 in the NMOS region 121 tend to have an unsatisfactory small thickness, even if the titanium silicide layers 111 in the PMOS region 122 have a satisfactory large thickness. As a result, agglomeration of titanium silicide tends to occur in the titanium silicide layers 111 during the subsequent heat-treatment process for activating the implanted arsenic atoms, thereby increasing conspicuously the sheet resistance of the titanium silicide layers 111 in the NMOS region 121.
To avoid such the sheet resistance increase of the titanium silicide layers 111 in the NMOS region 121 as described above, it is popular that the acceleration energy of arsenic ions is set as high as possible to thereby increase the resultant thickness of the amorphous silicon regions 106a, 109a, and 110a in the NMOS and PMOS regions 121 and 122. The increased thickness of the amorphous silicon regions 106a, 109a, and 110a accelerates the silicidation reaction of titanium with arsenic-implanted amorphous silicon and consequently, the above problem of the sheet resistance increase of the titanium silicide layers 111 in the NMOS region 121 can be prevented from occurring.
However, the increased thickness of the amorphous silicon regions 106a and 110a in the PMOS region 122 will cause another problem that the junction leakage current of the pair of p-type source/drain regions 110 in the PMOS region 122 becomes high.
The inventor found that this problem is due to the following reason.
FIG. 2 schematically shows the profile of the dopant concentration of the pairs of p-type source/drain regions 110 in the PMOS region 122 as a function of depth.
In FIG. 2, the curve A indicates the dopant concentration distribution due to the boron-difluoride-ion implantation for forming the pair of p-type source/drain regions 110. The straight line B indicates the dopant concentration distribution of the n-type well region 103. The curve C indicates the dopant concentration distribution due to the arsenic-ion implantation for forming the amorphous silicon regions 110a in the pair of p-type source/drain regions 110. The curve D indicates the resultant or overall dopant concentration distribution of the pair of p-type source/drain regions 110 after the arsenic-ion implantation for forming the amorphous silicon regions 110a.
As seen from FIG. 2, the depth X.sub.j0 of the p-n junctions of the pair of p-type source/drain regions 110 before the arsenic-ion implantation for forming the amorphous silicon regions 110a is given by the intersection of the curve A and the straight line B. On the other hand, the depth X.sub.j1 of the p-n junctions of the pair of p-type source/drain regions 110 after the arsenic-ion implantation for forming the amorphous silicon regions 110a is given by the intersection of the curve D and the straight line B.
It is clear that the depth X.sub.j1 is smaller than the depth X.sub.j0. This is caused by the fact that the p-type dopant (i.e., BF.sub.2) doped into the pair of p-type source/drain regions 110 is canceled or eliminated by the n-type dopant (i.e., As) at the tail or bottom of the distribution of the implanted p-type dopant (i.e., BF.sub.2), i.e., in the vicinity of the p-n junctions of the p-type source/drain regions 110. As a result, the tail or bottom of the distribution of the implanted p-type dopant is raised toward the surfaces of the regions 110. In other words, the p-n junctions of the pair of p-type source/drain regions 110 become shallow. These shallow p-n junctions increase the junction leakage current of the pair of p-type source/drain regions 110 in the PMOS region 122 due to spikes or crystal defects.
Concretely, to fabricate a p- or n-channel MOSFET having a gate length of approximately 0.15 .mu.m, the depth of the p-n junctions of a pair of source/drain regions with respect to their surfaces needs to be set as approximately 0.15 .mu.m or less from the viewpoint of suppression of the short channel effect.
On the other hand, to set the sheet resistance of a titanium silicide layer in a gate electrode of an n-channel MOSFET at 10 .OMEGA./.quadrature. or less, the acceleration energy of an n-type dopant (i.e., As ions) for forming an amorphous region in the gate electrode needs to be set as 60 keV or higher. However, if arsenic ions are implanted at an acceleration energy of 60 keV or higher with a dose of 2 to 5.times.10.sup.14 atoms/cm.sup.2, the tail or bottom of the implanted arsenic ions will have a depth of 0.1 .mu.m or larger.
Thus, the bottom or tail of the distribution of the implanted p-type dopant (i.e., BF.sub.2 ions) for forming the p-type source/drain regions 110 is canceled by the implanted n-type dopant (i.e., As ions) for forming the amorphous region, thereby decreasing the depth of the p-n junctions of the pair of p-type source/drain regions 110.

Fabrication method of semiconductor device with CMOS structure


In a random coding cipher system and method, a sender and receiver pair share a long string of random digits, the masking tape. To encrypt a plaintext message, the sender generates a random integer (with a random number generator, RNG) or a pseudo-random integer (using a pseudo-random number generator, PRNG). This is the initializing integer. The sender then selects an integer formed from a subset of the digits of the initializing integer. This is the starting integer for the message. The starting integer determines a starting, or indexing, position in the masking tape for extraction of a sequence of blocks of digits, of common length, to be put in one-to-one correspondence with the characters of the plaintext alphabet used for communication. The integer blocks comprise the numerical synonyms for the plaintext alphabet characters. By checking successive candidate digit blocks for prior association with plaintext alphabet characters, the one-to-one correspondence between numerical synonyms and alphabet characters is maintained. The concatenation of the numerical synonyms corresponding to successive message characters comprises the plaintext message string integer. A string of digits from the masking tape, beginning immediately after the last integer chosen for coding alphabet characters and of length equal to that of the plaintext message string, is added to the plaintext message string. This new random digit string is the masking tape string integer. The sum of the plaintext message string and the masking tape string is the ciphertext string integer which, preceded by the initializing integer, is sent as the cryptogram. To decrypt, the receiver uses the starting integer to determine the numerical synonyms and masking tape string, subtracts the masking tape string from the ciphertext string and recovers the plaintext message string and the plaintext message.

A common method of encrypting a plaintext message starts by substituting integers for plaintext characters according to some standard alphabet such as ITA2, ITA5, ASCII, or EBCDIC. These integers are then written in binary form to create a first string, or sequence, of 0's and 1's. The first string is modulo 2-added to another, second sequence of 0's and 1's to produce a third sequence of 0's and 1's. The third sequence of 0's and 1's is transmitted as the encrypted message. The sender's object is to make this third string of 0's and 1's appear to be a random sequence of digits in binary form. The intended receiver modulo 2-adds the second sequence to the third sequence to recover the first sequence. Thereafter, the original plaintext message is derived from the standard alphabet that was used, e.g., ITA2, ITA5, ASCII, or EBCDIC. If the second sequence is truly random, an interceptor-attacker will be unable to reproduce the first sequence. Thus, the plaintext message is preserved.
There are a number of problems with this scheme: First, random number strings are a relatively scarce commodity. Second, the receiver must have at hand exactly the same random number sequence the sender used or must be able to reproduce it. Having at hand exactly the same random number sequence the sender used requires the sharing of an enormous amount of key material. The sharing of an enormous amount of key material is impractical. Reproducing exactly the same random number sequence the sender used is impossible.
To avoid these two difficulties, a pseudo-random number generator is commonly employed by both sender and receiver. A pseudo-random number generator is a deterministic machine which, when initialized by a "seed" number, produces a string of digits which appears to be random (by passing various statistical tests). The output of a pseudo-random number generator is periodic, but the period can be made very long. When sender and receiver use pseudo-random number generators to produce the second, key, or encrypting sequence, they start with a common initializing "seed" and synchronize the outputs of their generators. Starting with a common initializing "seed" and synchronizing the outputs of the generators allows a knownplaintext attack in which an interceptor-attacker gains access to plaintext (hence to its binary digit string equivalent in terms of some standard numerical alphabet) and to the corresponding ciphertext. Knowing the digits of the binary plaintext string enables the attacker to reproduce the corresponding pseudo-random number sequence. This frequently allows the attacker to determine the algorithm, initializing "seed," and output sequence of the system's pseudo-random number generator, thus "breaking" the code.
In U.S. Pat. No. 5,113,444, entitled "Random Choice Cipher System and Method," issued to the same inventor as that of the present invention, a string of random digits is added to a string of integers numerically coding the plaintext characters of a message. The summed integer is the body of the cryptogram.
The numerical codings, "numerical synonyms," are randomly chosen from large, randomly dispersed collections of such integers corresponding to the plaintext alphabet characters. The collections of randomly distributed numerical synonyms and their matchings to the characters of a plaintext alphabet comprise a "thesaurus" which must be shared by a sender-receiver pair. So also must be shared a "masking tape," a long string of random digits from which the string of random digits, to be added to the numerical coding of the message, is selected.
The present invention dispenses with the thesaurus, using instead one-time numerical codings for message characters which are themselves extracted from the masking tape.


A system and method is provided for using an object-oriented interface for network management. An example system and method receives a management information base (MIB) including information related to one or more aspects of a network device, extracts a subset of information from the MIB describing at least one aspect of the network device, and generates a set of object-oriented classes and object-oriented methods corresponding to the subset of information in the MIB. In addition, this system and method interfaces with network management information on a network device, by providing a management information base (MIB) including information related to one or more aspects of a network device, and using a set of object-oriented classes and object-oriented methods that corresponds to the MIB and information related to one or more aspects of the network device.

Computer networks are becoming increasingly complex and difficult to manage. This is driven in part by the ever-increasing variety of network devices, computers, and software being combined together to integrate large enterprise-based intranets with the Internet. Network management tools have been produced to monitor these complex combinations of hardware and software and help troubleshoot network failures when they occurred.
Traditional network management tools use a protocol called simple network management protocol (SNMP) to monitor network devices such as routers, switches, hubs, remote access devices, or even computers in a network. The protocol used to interface with SNMP includes rudimentary commands to operate on data such as to "get" a variable, "set" a variable, or "test" a variable.
Having just a few simple commands make it difficult to perform network management tasks. Specifically, it can be difficult using these basic commands to develop sophisticated network management applications to monitor and troubleshoot a network. Each task may need to be customized to the parameters and capabilities of each network device. Further, a network management task sending combinations of these commands to one or more network devices connected to the network may wait a significant period of time for all the necessary results to be returned. Network delays can be caused by network congestion and the unique processing bottlenecks associated with each network device.

Object-oriented network management interface


A vehicle control apparatus includes an obstruction detection unit for measuring a headway distance until an obstruction existing ahead of the vehicle by means of a radar device, a unit for performing vehicle control or alarm control on the basis of the headway distance, a unit for detecting detection performance of the obstruction detection means in a vehicle in which the obstruction detection unit is used to perform two or more controls containing the vehicle control or alarm control, and a unit for controlling to stop operation of the vehicle control or alarm control in accordance with the detection performance individually.

The present invention relates to a radar apparatus for detecting an object on the periphery of a vehicle and a vehicle control apparatus for operating two or more traveling control apparatuses or alarm control apparatuses by means of the radar apparatus and stopping operation of traveling control or alarm control when detection performance of the radar apparatus is deteriorated.
Heretofore, in order to perform traveling control or alarm control of a vehicle, position information of a target detected by a radar apparatus mounted in a vehicle or relative speed information between the target and the vehicle is used. In such control, when detection performance of the radar apparatus is reduced due to a heavy rain or dirt attached to the surface of the radar apparatus, the traveling control or the alarm control cannot be performed in safety and accordingly avoidance measures for stopping all the controls are adopted.
On the other hand, U.S. Pat. No. 5,530,651 discloses a traveling safety device which changes a control logic so that traveling can be made in safety within the range that a radar apparatus can make detection when detection performance of the radar apparatus is reduced.
In the conventional method of stopping of all the controls, however, when the radar apparatus detects an obstruction short distance away, the traveling control or the alarm control cannot be performed and accordingly it is not desirable in safety.
Further, in the method of changing the control logic, a control range for a distance at which control is started is changed in accordance with detection performance of the radar apparatus and accordingly when judgment accuracy of detection performance deteriorates or when a strong reflection signal from a large obstruction is received, the obstruction is sometimes detected far from the maximum detecting distance of the detection performance of the radar apparatus. In such a case, alarm cannot be produced.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.


The present invention describes methods, systems, and data structures to create and search index records within a trace of a packet-based communications link that has been compressed by organizing the data packets according to which flow they belong. Index points are inserted within the compressed flow trace file to create frames and index records are created and saved for each index point. Consequently, searching for a particular data packet does not require sequentially reading the compressed flow trace file, but rather locating the appropriate index record and its corresponding frame in the compressed flow trace file.

Network monitoring is commonly used to measure traffic data across links connected to a particular router within a packet-based network. The traffic data can be useful for analyzing protocols, traffic engineering, and network anomaly detection. An interface within the router operates at a link speed indicating how much information can traverse the interface in a specified timeframe. For example, an OC-48 link can transfer data at a rate of up to 2,488 megabits per second. Passive monitoring involves copying data packets off a link in a manner that does not substantially affect the performance of the link. A data packet contains information regarding its source, its destination, its protocol type, its size, and its payload. This information, along with the time when the data packet crossed the link, can be helpful in reconstructing flows of related packets with the same sources and destinations. The packet information captured during the monitoring activity is commonly referred to as a trace.
Passive monitoring involves tapping the link on which data needs to be collected and recording to disk either complete packets or partial packets, such as packet headers and timestamps indicating their arrival time. In the case of fiber-based networks, an optical splitter may split the optical signal, therefore effectively copying all of the data on the link, which may be received by a packet capture card on a personal computer (PC). Timestamps recorded by the capture card may be synchronized to a global positioning system (GPS) signal. Packets are temporarily stored on the capture board and then sent to the PC main memory over the PC's PCI bus.
Collecting packet traces at higher than OC-48 link speeds can be difficult for several reasons:                PCI bus throughput is already challenged at OC-48. During passive monitoring, the PCI bus is crossed twice for any data transfer: once from the capture board to the main memory, and a second time from the main memory to the hard disk.        Collecting data at OC-48 results in possibly terabytes of trace information per day in a point of presence (POP). At OC-192, the storage capacity must increase by a factor of four, and the challenge of managing such an enormous data set increases greatly as well.        Memory access speeds have not increased as quickly as the link speed.        Disk array speed has not kept up with link bandwidth. At OC-192 speed, a packet-level trace would require a disk bandwidth of roughly 250 megabytes per second.
A passive monitoring infrastructure suitable for deployment for OC-192 links will benefit if it can perform some computation on-line so as to minimize the amount of data stored locally. But the computation must be simple—at OC-192 (10 Gbps) a new packet arrives every 240 ns on average (assuming 300-byte packets). This allows only 360 instructions per packet on the fastest processor currently available. Such a monitoring system may store the minimum amount of information necessary to simplify collection and storage. Sampling, such as copying every tenth packet rather than every packet, may be required in addition to compression.
One way to achieve these requirements is to store internet protocol (IP) packet data as flow traces instead of packet traces. A flow trace groups packets together that are from the same source and addressed to the same destination during a short time period. By collecting the related packets together, information that is common to all of the packets within a flow can be stored once for each flow, rather than with each packet. Since the common information can be removed from each data packet within the same flow, the resulting flow trace is compressed. With a compressed flow trace, less information is stored and processed, which reduces the resources required to collect data across higher speed links. Unfortunately, because the packets are no longer in chronological order, reconstructing the original arrival order of the packets from a flow-based trace requires sequentially reading the compressed flow trace file until the target packet is located.

Lightweight indexing for fast retrieval of data from a flow-level compressed packet trace


It is an object of the present invention to provide a highly reliable image database system capable of accessing image data at high speed regardless of the increase of the image data and capable of controlling the image data as a whole. A storage unit 1, a control unit 2, an image database server 3 and a DICOM gateway 4 are subjected with each other to network connection. The storage unit 1 stores medical image data. The control unit 2 controls the storage unit. The image database server 3 stores key information associated with the image data stored and applies relay processing between an externally connected viewer and the image database server. The DICOM gateway 4 applies relay processing via a DICOM protocol between a plurality of modality devices externally connected with the image database server and the DICOM gateway. A control unit group, an image database server group, and a DICOM gateway group are constituted by providing at least a plurality of control units, a plurality of image database servers and a plurality of DICOM gateways, and a load balancer for executing load distribution control of every group is provided for every group based on header information of a request.

1. Field of the Invention
The present invention relates to an image database system for storing a large quantity of medical image information photographed by a modality device such as a CT device and an MRI device as electronic information and for being useful for diagnosis.
2. Description of the Related Art
Japanese Patent Application Laid-Open (JP-A) No. 2002-245173discloses a medical image control system which subjects a plurality of image servers for storing medical image generated in a plurality of modality devices to network connection and controls a large quantity of medical images stored in the plurality of image servers. The medical image control system can detect and display a desired medical image at high speed from a plurality of medical image storage servers connected to the network. The medical image control system comprises an integrated control server containing detection means, data base means and control means. The detection means detects a first retrieval information concerning the medical image stored in a plurality of image servers regularly at prescribed time intervals. The data base means adds information concerning the image server to the first retrieval information detected by the detection means when the first retrieval information detected does not exist in a second retrieval information which has been already registered, and registers the information as the second retrieval information. The control means controls a large quantity of medical images stored in the plurality of image servers on the network based on the second retrieval information registered in the data base means. The medical image control system can rapidly access to a desired image server through the integrated control server.
For example, this type of the network is explained by using an OSI (Open Systems Interconnection) reference standard model. A physical layer and data link layer of the network are constituted by Ethernet (registered trade name), and a transport layer and a network layer are constituted by TCP/IP (Transmission Control Protocol/Internet Protocol). High order layers of a session layer or more are constituted by a DICOM (Digital Imaging and Communication for Medicine) protocol which is an image diagnostic standard in a medical field. The medical images are stored and controlled as a DICOM image comprising tag information and image data in each image server (DICOM server) through the network, and are interpreted and browsed by using an image viewer (DICOM viewer) for exclusive use.
However, according to the DICOM protocol in the conventional image database system as described above, the image data is essentially treated in a non-compression state. In addition, a communication procedure is complicated from the viewpoint of the protection of the tag information or the like, and it takes a time for data communication. Thereby, it is necessary to improve an image search response or the like. In particular, a lot of viewers are also set in a large-scale hospital, and the increase of network load causes the additional reduction of response.
In the above system, a large quantity of medical image data is respectively controlled by a plurality of different image servers for every modality device. The medical image data is backed up by a different system in a different media for every image server which is manufactured by a different manufacturer and is different model. Thereby, a problem exists in the control of the image data as a whole system is inadequate.
The image viewer connected to the above network may be set in an operating room, and may be used as an assistance of an operation. A request exists in that the reliability of the image viewer must be fully guaranteed.


A powertrain includes a continuously variable transmission having a starting mechanism, a continuously variable unit (CVU), and a pair of planetary gear arrangements. The continuously variable transmission also includes a plurality of torque transmitting mechanisms which are selectively engageable in combinations of two to establish a reverse mode of operation between the starting mechanism and a transmission output shaft, a low direct mode of operation, an intermediate split mode of operation, and a high split mode of operation.

Passenger vehicles in today's market incorporate a power transmission that has at least three forward ratios, and quite often, six forward ratios. These power transmissions are utilized to extend the operating range of the vehicle engine by reusing the engine speed range as the gear ratio is changed. In order to make more efficient use of the engine and its speed range, it has been proposed to employ a continuously variable type transmission wherein the ratio change within the transmission is continuous over during a drive range during which the engine speed might be held constant. For example, the continuously variable transmission ratios are changed from an underdrive of four to one (4:1) to an overdrive of point four to one (0.40:1). A step change transmission utilizing this same ratio spread would require five or six ratio steps depending upon the step ratio multiplier desired between the adjacent ratios.
The continuously variable type transmissions have been suggested as single mode and dual mode type power transmissions. Mostly, the transmissions for passenger vehicles have been proposed as geared neutral type transmission arrangements wherein the ratios in the transmission can be changed from forward to reverse without the interchange of friction devices. While these types of transmissions provide a simplified control system for forward and reverse, they do have the disadvantage in that a high portion of the power is recirculated through the continuously variable unit and the gearing during the vehicle launch operation. This reduces the transmission output torque, tractive effort, and the overall efficiency of the transmission during vehicle launch.

Three-mode continuously variable transmission with a direct low mode and two split path high modes


A brushless DC motor has a permanent magnet rotor comprising p magnetic poles and a stator having an integer multiple of 6*p*n slots containing windings, n being a positive, non-zero integer, and the poles and slots being skewed by one slot pitch with respect to each other. The windings in the slots are electrically connected in two separate groups of three-phase windings with each group having three phase terminals, the windings of each group being distributed in phase belts occupying alternate sectors of 30 electrical degrees and the windings of the first group alternating with the windings of the second group. Since the trapezoidal back EMF voltage curve has a wider top it exhibits less droop, compared with an equivalent three-phase brushless DC motor of the prior art, over the 60 electrical degree period centered on maximum back EMF in which torque producing current is applied. In addition, the maxima of back EMF voltage across pairs of terminals in the two groups of three phase windings are 30 electrical degrees out of phase with each other, so that variations in back EMF voltage in the two groups tend to cancel each other as torque producing current is applied to both groups. The result is significantly less torque ripple due to back EMF variation, compared with an equivalent three-phase brushless DC motor of the prior art, and less vibration coupled to the steering wheel of an electric power steering system in which the motor is used as a power assist actuator.

The technical field of this invention is brushless DC motors, and particularly such motors optimized for use in a vibration sensitive environment such as an electric power steering system for a vehicle.
In a conventional three-phase, trapezoidal back EMF, brushless DC motor, the three phase windings are distributed on the stator surface over 6 phase belts of 60 electrical degrees each. The conductors for each phase belt are placed in a single or multiple slots over this 60 degrees. FIG. 2 shows a prior art example of such a motor 1 having a four pole PM rotor 2 and a stator 3 with windings for phases A, B and C placed in 12 stator slots 4 of 60 electrical degrees (30 mechanical degrees) each. FIG. 3 shows a motor 5 which is a prior art variation of motor 1 in FIG. 2. Motor 5 has a similar four pole rotor 6 and a stator 7 having twenty-four stator slots 8, with each slot comprising only 30 electrical degrees (15 mechanical degrees) but with windings in pairs of adjacent slots connected in the same phase, so that the windings for phases A, B and C are still each distributed over phase belts of 60 electrical degrees.
In order to reduce cogging torque in such motors, either the stator slots or the rotor magnets are skewed to produce a skew of one slot pitch therebetween axially across the stator. Under such conditions, assuming an ideal square wave flux distribution in the air gap and a nearly closed slot structure, the line-to-line back EMF waveform generated by the rotating rotor across each pair of phase terminals has a trapezoidal shape with a flat top indicating a constant value over a range of 60 electrical degrees. In an ideal case wherein each phase is excited by a constant current over 120 degrees, a ripple free torque would be produced. However, in reality, the flux distribution in the air gap is not a square wave; and this results in a line-to-line back EMF wave form which droops at each end of the 60 degree "flat" area. In FIG. 9, the actual back EMF curves V.sub.cb, V.sub.ab and V.sub.ac of the motor of FIG. 3 are shown for a portion of a rotor rotation. The portions of the back EMF curves which produce motor torque, because current is provided through the indicated terminals, are shown as solid lines; and the remainder of the curves, which produce no torque, are shown as dashed lines. It can be seen that, from 60 to 120 electrical degrees, only curve V.sub.ab is active in generating torque. The solid line portion of curve V.sub.ab illustrates that the back EMF in this range is not constant: it achieves a maximum at 90 degrees and droops by about 12 percent of that maximum torque at 60 and 120 degrees. This occurs for each curve over the range of 60 electrical degrees of motor rotation in which it produces torque; and the result is a torque ripple which can be undesirable in some motor applications. In particular, such a motor used as a direct actuator in an electric power steering system for a motor vehicle will be mounted on and/or coupled to the vehicle steering column; and vibrations produced by the torque ripple may be conducted directly to the steering wheel, where they may be both apparent and annoying to the vehicle operator.

Brushless DC motor having reduced torque ripple for electric power steering


Apparatus is disclosed that efficiently projects electromagnetic radiation over a predetermined spherical sector with a tailored intensity distribution. The apparatus includes a base having a cavity and aperture that faces the spherical sector to be illuminated, with a flat, ring-shaped shoulder surrounding the aperture. The apparatus further includes a mask spaced over the aperture and a baffle projecting from the mask toward the aperture. The base, the mask, and the baffle are formed of a material having an outer surface with a significant diffuse, reflective characteristic. A source emits electromagnetic radiation (e.g., visible light) into the base cavity, and the base, mask and baffle are configured to redirect this radiation outwardly with the tailored intensity distribution (e.g., a uniform distribution) over the predetermined spherical sector (e.g., a hemisphere, or 2 .pi.steradians).

This invention relates generally to apparatus that project electromagnetic radiation over a predetermined spherical sector and, more particularly, to apparatus that project electromagnetic radiation with a tailored intensity distribution.
Apparatus of this particular kind are commonly used to project electromagnetic radiation, especially visible light, over a hemisphere, i.e., 2 .pi.steradians, for a variety of applications. Examples of such applications include use as a warning light on an emergency vehicle's light bar or as an aircraft warning light. In each case, the projected light has a predetermined intensity distribution, e.g., a uniform intensity profile over the hemisphere.
One type of apparatus of this kind is a translusive diffuser, which includes a sheet of translusive material disposed over a light source. Light from the light source passes through the translusive sheet and is diffused into the surrounding space. Suitable translusive materials include opal glass, acrylics, and Teflon. The translusive sheet sometimes is covered by a transparent protective dome or the sheet, itself, sometimes is formed into a dome shape. Although generally effective in projecting light substantially uniformly, translusive diffusers are considered to be unduly inefficient, projecting only about 20% to 25% of the available light when configured as a hemispherical light distributor.
Another type of apparatus of this kind is a beam redirector, which includes an optical device having a special refractive or reflective surface for redirecting light from a light source such as a laser into a hemisphere. Although such beam redirectors are relatively inexpensive to manufacture, they typically require a critical alignment between the light source and the optical device, and they typically require the use of a light source that provides a light beam having a known, stable intensity distribution. Moreover, the projected light often has a spatial intensity distribution that varies excessively.
It should, therefore, be appreciated that there is a need for an apparatus that projects electromagnetic radiation over a predetermined spherical sector, e.g., a hemisphere, with a tailored spatial intensity distribution, wherein the radiation is projected with greater efficiency and with less dependence on a critical alignment of optical components. The present invention fulfills this need.

Apparatus for projecting electromagnetic radiation with a tailored intensity distribution


A seamless women's upper body garment that functions to lift and enhance the bust line, slim and smooth the upper body and help to improve wearer's posture without creating unsightly visible back lines and bulging. The garment comprises a circumferential band below the bust line and dorsal and ventral vertical support panels.

The present invention relates to garments, particularly those that can be worn as women's undergarments or as day wear. In particular, the present invention relates to an improved seamless upper body garment of unitary construction.
No matter how slender a woman is or how much exercise a woman does, girdles and bras can create visible back lines and bulging. A wide variety of girdles and bras have been available for hundreds of years, all sacrificing a smooth, lineless back for full support in the front. In the past, full support could not be achieved without uncomfortable, unsightly back straps. Prior undergarments resulted in visible lines from supporting members such as bra straps and internal shelf bras, and from seams that formed the edges of bras and panties. In addition, prior undergarments caused a wearer's extra flesh to be forced into unsightly bulges.


A method of manufacturing an electrode for a secondary battery includes preparing an electrode current collector in which a plurality of through-holes are formed; applying a first slurry including an electrode active material, a binder, and a conductive material to at least one surface of the electrode current collector; and applying a second slurry including an electrode active material, a binder, and a conductive material on the first slurry. In manufacturing an electrode including an electrode current collector with a plurality of through-holes, processability may be secured by preventing leakage of a slurry, and thus, a uniform electrode mixture layer may be formed.

The present disclosure relates to a method of manufacturing an electrode for a secondary battery, and a secondary battery including the electrode, and more particularly, to a multilayer electrode formed by applying a slurry having different viscosity on an electrode current collector in which a plurality of through-holes are formed, and a method of manufacturing the same.
With the development of technology and demand for mobile devices, the demand for secondary batteries as an energy source has rapidly increased, and recently, the use of secondary batteries as a power source for electric vehicles (EV) and hybrid electric vehicles (HEV) has been realized. Among such secondary batteries, there is a high demand for lithium secondary batteries having high energy density, high discharge voltage, and output stability.
In general, a lithium secondary battery is manufactured by using a material capable of inserting and removing lithium ions as a negative electrode and a positive electrode and by charging an organic electrolyte or a polymer electrolyte between the positive electrode and the negative electrode, and electrical energy is generated by oxidation and reduction reactions when lithium ions are inserted and desorbed from the positive electrode and the negative electrode.
In this case, the negative electrode and the positive electrode include an electrode mixture layer on the current collector of each electrode. For example, a slurry is prepared by mixing and stirring a binder, a solvent, and a conductive material and a dispersant as needed, in the electrode active material, and then, electrodes may be prepared by applying the slurry to a current collector of a metallic material, followed by being compressed and dried.
In the process of manufacturing such an electrode, the development of a high-capacity battery has been required by expanding application of a lithium secondary battery to an electric vehicle, etc., thus increasing the load on the electrode mixture layer. However, the increased volume and weight of the electrode mixture layer lowers the energy density of the entire secondary battery, and there is a problem that causes non-uniformity of the electrochemical reaction inside the electrode mixture layer. Moreover, when a current or voltage is applied, a concentration gradient of lithium ions in the electrode occurs. In the thick electrode mixture layer, this phenomenon is further exacerbated, causing deterioration of rapid charging characteristics.
Therefore, a method of obtaining the capacity of a secondary battery having a thick electrode mixture layer by laminating several layers of thin electrodes rather than thickly applying an electrode mixture layer on one current collector has been proposed. However, in this case, to preserve the movement of lithium ions, a current collector having pores having a specific porosity or higher or openings having a specific aperture ratio or higher is used. In addition, the current collector in which the pores or openings are formed may significantly reduce the weight of the entire secondary battery, and thus, the use in future is further expected.
However, when the slurry is applied during the electrode manufacturing process, there is a problem in that the slurry leaks to the opposite side of the coated surface, resulting in surface irregularity of the electrode mixture layer, and failing to form a uniform electrode mixture layer, due to the high porosity or aperture ratio.

Method of preparing electrode for secondary battery, and secondary battery including the electrode


A semiconductor device comprises: a cell region that includes a semiconductor element; an outer peripheral region that surrounds an outer periphery of the cell region; a substrate that has a front surface and a back surface, and is made of a semiconductor of a first or second conductivity type; a first conductivity layer that is formed on the front surface of the substrate and made of the semiconductor of the first conductivity type having a lower impurity concentration than impurity concentration of the substrate; a first electrode that is provided on an opposite side of the substrate across the first conductivity layer, the first electrode being provided in the semiconductor element; and a second electrode that is placed toward the back surface of the substrate, the second electrode being provided in the semiconductor element.

In a semiconductor device having a cell region in which a semiconductor element such as a MOSFET is formed and an outer peripheral region surrounding the cell region, an outer peripheral withstand voltage structure for improving an element withstand voltage is provided in the outer peripheral region. As the outer peripheral withstand voltage structure, there is a guard ring structure. The guard ring structure is configured by forming a p-type guard ring so as to be in contact with a bottom surface of a recess portion provided around the cell region, and multiple p-type guard rings are concentrically arranged so as to surround the cell region.

Semiconductor device and manufacturing process therefor


Apparatuses, methods, and systems for calibrating of an antenna array that uses low-resolution phase shifters, are disclosed. On method includes generating a codebook of phase-shifter setting selections for each of a plurality of antenna elements of an antenna array including communicating a wireless signal between an external calibration antenna and the antenna array through a beam formed by a reference antenna element of the antenna array and an antenna element of the antenna array being calibrated, measuring a signal power of the communicated wireless signal for each of N settings of a digitally selected phase shifter associated with the antenna element of the antenna array being calibrated, and estimating a virtual signal power of each of M settings of the digitally selected phase shifter based on the signal power measurements of the N settings of the digitally selected phase shifter, wherein M is greater than N.

Wireless devices of a wireless network can communicate with each other using beamforming techniques. The wireless devices can include antenna arrays that form beams that facilities wireless communication between the wireless devices. Some wireless devices use low-resolution phase shifters for formation of the beams. However, low-resolution phase shifters can result in undesirable side lobes in the antenna response.
It is desirable to have methods, apparatuses, and systems for calibrating an antenna array that uses low-resolution phase shifters.

Calibration of an antenna array that uses low-resolution phase shifters