A check valve assembly mounted on an end surface of a projection of a valve body. The check valve assembly includes a valve having a sealing surface on one side and a stem on an opposite side, and the valve body includes a fluid inlet intersecting the end surface of the projection. A rigid mounting plate has a first locating element adapted to locate the mounting plate with respect to the end surface on the projection. The mounting plate has a second locating element adapted to receive a fastener for attaching the mounting plate to the end surface of the projection. A clearance hole in the mounting plate is sized to receive the stem of the valve. The stem of the valve moves freely within the first clearance hole thus permitting the valve to move freely between open and closed positions.

An inlet check valve for use with high pressure cylinders, for example, up to a 40,000 psi or greater, must be capable of operating reliably at such high pressures. One example of an inlet check valve assembly is described in U.S. Pat. No. 4,371,001 which discloses an inlet valve mounted on the end of a projecting portion of a generally cylindrical check valve body. The inlet check valve has a valve element that is mounted over an inlet passage. The inlet valve element tapers from a lower larger diameter to a thin shaft that is pressed into an opening on one end of a leaf spring. The opposite end of the leaf spring is secured to the projection of the valve body by a mounting screw extending through a spacer into a threaded hole in the valve body. The spacer has a height equal the height of the valve element such that the leaf spring is approximately perpendicular to the center lines of the mounting screw and the valve element. Such a check valve normally functions well in service, however, the design does have several disadvantages. First, the leaf spring is capable of rotation with respect to its mounting screw. Therefore, the valve element may be installed off-center with respect to the inlet passage, or the valve element may be moved off-center during operation of the cylinder pump. When the valve is off-center and misaligned with the inlet passage, the valve element is subjected to uneven wear and overheating. In addition, the leaf spring can bend or otherwise inhibit the valve from having the proper lift, thereby potentially causing overheating and reducing pump efficiency. Further, the assembly of the valve element and leaf spring must be replaced whenever the valve element itself must be replaced, thereby increasing the cost of valve replacement. Consequently, there is the need for an improved inlet check valve.


The present invention is directed to a method for forming glass articles containing internal enclosed channels. The method comprises the following steps: (a) delivering and depositing a first or channel-forming ribbon of molten glass to a surface of a mold assembly having a mold cavity possessing at least one channel-forming groove formed therewithin and a peripheral surface, wherein the channel-forming ribbon overlies the mold cavity and the peripheral surface of the mold assembly; (b) allowing the channel-forming ribbon of molten glass to substantially conform to the contour of the mold cavity resulting in the formation of at least one channel in the ribbon of the molten glass; (c) delivering and depositing a second or sealing ribbon of molten glass to the outer surface of the channel-forming ribbon of molten glass wherein the viscosity of the sealing ribbon is such that the sealing ribbon (i) bridges but does not sag into complete contact with the surfaces of at least one channel of the channel-forming ribbon and (ii) forms a hermetic seal wherever the sealing ribbon contacts the channel-forming ribbon to form a glass article possessing at least one enclosed channel; and, (d) removing the glass article from the mold.

Neon lighting devices are disclosed in U.S. Pat. No. 4,584,501(Cocks et al.), U.S. Pat. No. 4,990,826 (Cocks et al.), U.S. Pat. No. 5,036,243 (Cocks et al.). Generally, these patents disclose multifaceted lighting devices comprising glass or other vitreous plates which are hermetically sealed together to form a device with internal and enclosed channels. These enclosed and internal channels are thereafter evacuated and backfilled with an inert gas such as neon which is thereafter ionized through the provision of a series of electrodes.
Generally, the method for forming the glass component of these prior art neon lighting device involved cutting channels in a bottom glass plate followed by hermetically sealing, via the use of a glass frit, another glass top plate to this channeled glass bottom plate. Various methods were used to cut the channels into the bottom glass plate including grinding, etching and sand blasting through an adhesive rubberized mask exhibiting a pattern identical in shape to the desired channel pattern. The result of this cutting and subsequent fritting was that formation of the glass component of these lighting devices was an expensive and inefficient process and the resultant glass component was too heavy for use in those applications where weight was a concern, e.g., automotive applications.
Other more recent flat type lighting devices are disclosed in U.S. Pat. Nos. 5,041,762 (Hartai), 5,220,249 (Tsukada) and 5,223,262 (Lynn et al.). However, each of these references produces the glass body in generally the same manner; two glass plates fritted or sealed together. For example, Tsukada discloses a pair of transparent plates assembled and sealed together by a solder glass with a groove formed on the surface of one of the transparent glass plates thereby forming a discharge channel.
The principal objective of the present method is to provide for an improved method of forming the glass component for use in neon lighting devices; one which is simpler, more efficient and less costly than the prior art cutting or forming and fritting method, and which produces lightweight, sealant-free glass envelopes. In other words, the present method provides for a high volume, low cost method of producing lightweight glass articles possessing enclosed internal channels for use in light-emitting devices.

Method of making an internally channeled glass article


The present invention is a mounting structure for a power supply. The mounting structure of the present invention allows power to be coupled from a power supply to a predetermined area on a motherboard adjacent one or more high power demand components, such as an IC microprocessor chip. The mounting structure includes a frame; a plurality of legs attached to the frame for supporting the frame on the motherboard; the ends of the legs opposite the frame being attached to the motherboard; a fastener coupled to the frame for releasably fastening the power supply to the mounting structure such that the power supply is positioned a predefined distance above the upper surface of the motherboard; and a plurality of power buses interconnecting the power supply and the motherboard at predetermined area on the motherboard adjacent a high power demand IC chip. The high power demand IC chip is powered by the power supplied via the power buses such that resistive losses and inductive effects in delivering power to the IC chip are minimized, which among other things enables tight regulation of the voltage applied to IC chip(s). The mounting structure of the present invention also allows more efficient use of the motherboard area since it both minimizes the area needed on the motherboard for high power conductive traces and minimizes the area needed on the motherboard for the mechanical connection of the mounting structure thereto.

The present invention relates to power supply systems. More specifically, the present invention relates to a power supply mounting system for a high density printed circuit board.
All alternating current (AC) powered electronic equipment contain one or more power supplies to convert the AC input power to various lower direct current (DC) voltages needed by the circuits inside the equipment. In the prior art, a typical connection of power from the power supply to a printed circuit board on which various components such as integrated circuits (IC's) are mounted is by a wire harness. One or more printed circuit boards and peripheral devices have power coupled to them in this manner. In today's personal computers, a single large multilayer printed circuit board is usually included, a so called motherboard, and one or more IC's including the large microprocessor chip and various memory chips are mounted on this motherboard. Use of a wire harness to couple the power supply to a component on the motherboard has severe limitations as there are significant resistive losses and inductive effects in the wires of the wire harness and conductors in the multilayer printed circuit board (PCB). As is known in the art, resistive losses are determined by the amount of current squared multiplied by the resistance of the wire or conductor. Similarly, inductive effects are largely determined by the rate at which current through a wire changes and the length of the wire. Accordingly, the resistive losses and inductive effects are significant in a wire or conductor that delivers power to an IC chip or other component that has a high power demand, especially where the active component operates at a low voltage and has a wide ranging and rapidly changing current demand which can significantly affect the voltage regulation limits at the IC chip.
Unfortunately, from the perspective of worsening regulation limits due to resistive losses and inductive effects, most modern day microprocessors have an increasing power demand, lower operating voltages, and a wide ranging and rapidly changing current demand. For example, the Intel Pentium Pro microprocessor operates at 3.1 volts and has a current demand that can change from 0 to 11.2 amps in 350 nanoseconds. It is expected that future microprocessors will operate at lower voltages and significantly higher current demand. This will significantly increase resistive losses and inductive effects in wires and conductors connecting the power supply to the microprocessor. As a result of the resistive losses and the inductance of such power coupling wires or conductors, a power supply with a wire harness is not able to deliver an accurately regulated low voltage to components on the motherboard drawing large transient currents.
In addition to having resistive losses and inductive effects, wire harnesses have reliability problems in manufacturing and handling.
The above disadvantages of using wire harnesses are well known in the art and have resulted in the use of distributed power systems in some applications. In a distributed power system, a simple AC to DC power supply produces a single voltage output which is distributed around the system. Typically, the power supply produces a bus voltage of 48 volts. This voltage is preferred because it is low enough to ensure compliance with international safety standards, yet high enough to reduce distribution losses which are proportional to the square of the current. However, other bus voltages, such as 24 or 12 volts, are also possible. The distributed power system also includes one or more high density DC to DC converters (i.e., converters that have a high power output per cubic volume of space that they occupy). These high density DC to DC converters are powered by the bus voltage and are placed in close proximity to the high power demand components powered by the power source. The reduced distance between the high power demand components and the adjacent power converter significantly reduces the resistive losses and the inductive effects in the wires and conductors coupling the power converter to the component.
However, fully distributed power systems are not yet cost effective in high volume, low cost systems, such as personal computer systems. Nonetheless, some components in personal computers require a very fast response from the AC-DC or DC-DC converter to which they are coupled. For example, many high performance processor chips used in personal computers require a fast transient current response from a DC to DC converter providing a tightly regulated programmable output from 1.8 to 3.6 volts to the processor chip. The need for precise voltage regulation by such chips requires use of what is known in the art as a voltage regulator module (VRM). A VRM can be either a complete plug-in DC to DC converter or a circuit implemented on the motherboard. The addition of a VRM to a power system increases the cost of the power system by as much as 50%. Additionally, VRMs occupy valuable motherboard area. This is particularly significant when the "wasted" area under the power converter or VRM is, for example, a portion of a 12-14 layer high density high cost motherboard.
Therefore, it is desirable to tightly regulate the voltage applied to one or more IC chips mounted on a PCB. It is also desirable to reduce resistive losses and inductive effects in delivering power to components on a printed circuit board. It is also desirable to efficiently utilize the surface area of a printed circuit board.

Power supply system for high density printed circuit boards

G/F, No. 68 Po Sam Pai Village Ting Kok Road

Astec Custom Power (HK) Ltd. - ATC Blk H, 7/F., CDW Building 388 Castle Peak Road

Flat H, 24/F1. Block 8, Phase II Belvedere Garden


In order to improve the reliability and the accuracy of a position-finding method such as the GPS method, the quality of a radio link which is used for the position-finding method is determined by estimating a parameter, in particular the Rice factor of the amplitude distribution density, which is characteristic of the ratio of the strength of a signal transmitted via a line-of-sight path, with respect to the strength of the signals transmitted via non-line-of-sight paths.

It has been known for some time that position-finding can be carried out on the basis of radio links, for example within the satellite-assisted GPS system (Global Positioning System). The European Galileo satellite navigation system, as well as positioning methods based on terrestrial radio sources, offer further applications. Position-finding methods such as these and appropriate appliances allow the user to determine his position by measurement of the distance to a specific number of wire-free signal sources such as satellites or base stations. For example, each GPS and Galileo satellite transmits unique digital sequences, which include a time identification and the satellite position. The signals are normally modulated with long spread sequences. The spread sequences for the individual satellites are virtually orthogonal with respect to one another, so that the signals can be distinguished from one another at the receiver. By way of example, the spread sequences for the various GPS and Galileo satellites are synchronized to one another by means of high-precision atomic clocks that are installed in the satellites.
The receiver evaluates the relative delays (delay time offsets) between different radio sources (GPS satellites, Galileo satellites or terrestrial transmitters). Together with the data about the position and the time reference of the various radio sources, the delay time offsets can be used in order to locate the receiver exactly. The receiver calculates the so-called pseudo-ranges, which represent the distance to each radio source. Navigation software can then calculate the user position on the basis of the pseudo-range to each radio source and the position of the radio sources (GPS satellites, Galileo satellites or terrestrial transmitters) by solving a set of non-linear equations.
The delay time offset between the received signals from the radio sources is frequently measured by determining a correlation maximum in a receiver architecture and assuming that this maximum corresponds to the direct line-of-sight (LOS) path. The problem is that the individual signals do not always reach the receiver along a direct line-of-sight transmission, but often are reflected or scattered by a large number of obstructions such as buildings or hills. These reflected or scattered signals propagate along a greater distance, however, and are therefore delayed. If no line-of-sight path exists, the measured correlation maximum does not correspond to the path delay of a line-of-sight path, and thus leads to a greater pseudo-range. Determination of the user position on the basis of these reflected and delayed signals thus leads to a position error.
Particularly in urban environments and environments within buildings as well as rural environments, it is known that there are reasons why the signals are reflected, diffracted and scattered, thus leading to multipath signal propagation, in which various versions of the signal arrive at different times at the receiver. Depending on the phase offset, the signals are subject to constructive or destructive interference, which leads to multipath fading. This effect can attenuate the line-of-sight signal and can lead to the receiver detecting a delayed version as a supposed maximum, instead of this. Furthermore, obstructions such as buildings in urban environments can shadow the line-of-sight signal to such an extent that the receiver detects a non-line-of-sight signal as the maximum. Multipath fading often leads to line-of-sight signals which are weaker than the non-line-of-sight signals. The severe attenuation, such as that which occurs in environments within buildings, can completely mask the line-of-sight signal with environmental noise, so that the receiver detects a non-line-of-sight signal.
This problem is generally not so important for wire-free communication, since the useful data contained in the received signals can often be recovered from the delayed signals. However, for position-finding systems, the essential information is contained in the time relationship between the signals from the various signal sources. Reflected and delayed signals propagate over a longer distance. The position-finding receiver will in consequence detect a greater pseudo-range than the line of sight range. An incorrect pseudo-range measurement leads to an incorrect position being found. Multipath propagation scenarios normally occur in built-up or mountainous environments, and thus lead to position-finding errors by the position-finding appliances.
Position-finding receivers that are currently in use, in particular GPS receivers with increased sensitivity, determine positions on the basis of all of the detectable satellite signals. A number of position-finding processes are carried out over a predetermined interval. If the so-called "Dilution of Precision" (DOP) for these position-finding processes is below a specific threshold value, the position that has been found is accepted, otherwise the measurements are rejected.
There are also other multipath avoidance techniques which are implemented in the antenna in order to constantly attenuate signals from specific directions. However, this restricts the antenna coverage and requires the antenna to be oriented in a specific manner, thus resulting in problems for hand-held receivers.
A further alternative is to exclude false pseudo-areas by comparison of the calculated user position with a-priori information about the approximate user position. When determining new, unknown positions, this can be done only with considerably reduced accuracy. Furthermore, this means that the position calculation must be carried out before a decision can be made about incorrect pseudo-areas, and thus results in significant additional costs.

Reliability and the accuracy of position-finding methods by estimation of the Rice factor of a radio link


A strip light is disclosed. The light comprises an illuminating unit including a plurality of illuminators (e.g., LEDs) directly and electrically coupled in series, and a constant current stabilization unit with temperature compensating capability for supplying a constant current to each illuminator. A number of embodiments of the constant current stabilization unit are made possible. The invention further has advantages of energy saving, even brightness of the illuminators, less heat generation, and durability.

1. Field of the Invention
The present invention relates to strip lights and more particularly to such a strip light having an arrangement for supplying a constant current to each illuminator thereof.
2. Description of Related Art
A conventional LED (light-emitting diode) based strip light is disclosed in Taiwanese Patent Published No. 516,709 (the prior art). The prior art comprises a plurality of LEDs (light emitting diodes) mounted on a circuit board, a plurality of resistors coupled to each of the LEDs on the circuit board, two diodes at both ends of the circuit board, a positive terminal at one end of the circuit board for coupling to another LED based strip light or power source, a negative terminal at the other end of the circuit board for coupling a positive terminal of another LED based strip light or power source, upper insulation means for enclosing the LEDs, the resistors, the diodes, and the positive and the negative terminals on a top surface of the circuit board, and lower insulation means for enclosing pins, contacts, and circuits on a bottom surface of the circuit board.
The prior art is adapted to regulate current. However, the prior art suffered from several disadvantages. For example, high heat can be generated by a LED and its coupled resistor. Such heat may be excessively high if the number of LEDs and thus the number of resistors are large (i.e., many LEDs and resistors are coupled in series). Also, brightness of the LEDs can be lowered due to increased resistance. In other words, a considerable portion of electrical energy is consumed (i.e., wasted) by resistors rather than by LEDs. Further, brightness of one LED may be different from that of other LEDs due to uneven resistor in respective LEDs.
U.S. Pat. No. 4,717,868 entitled "Uniform Intensity led Driver Circuit" discloses the following characteristics. Voltage from a string of LEDs is fed to an output terminal 19. The voltage is decreased by a resistor R2 prior to turning on transistors Q3, Q4, and Q7. Further, high and low voltage levels are controlled by a node 13 for turning on transistor Q1 and for inputting signal through a NOR gate 17 and an inverter 16. Another signal through the NOR gate 17 is fed to a node 14 which is adapted to control high and low voltage levels for turning on transistor Q6. A comparison signal is generated by a comparator 15 in response to feeding two voltage signals from nodes 27 and 28 and comparing same. Further, the comparison signal is fed to the NOR gate 17 and high or low voltage level is fed to the NOR gate 17 via node 13 respectively for turning on transistor Q5 or not. As a result, the LEDs can maintain its constant current state. However, nodes 13 and 14 for high or low voltage level control, and NOR gate 17 for operation and output are required by the patent and thus the patent does not respond to temperature change. Also, no overload protection is provided. Further, PWM (pulse width modulation) for constant current control is not applicable to the patent. This is not desirable. Thus, the need for improvement still exists.


A zipper head assembly structure includes a fastening slider, a pulling piece, a horse-like hook, an elastic piece and a cap. The top of the fastening slider has a first fixing base and a second fixing base at two ends thereof, respectively. One end of the elastic piece is fixedly connected on the first fixing base of the fastening slider. The elastic piece abuts against the top portion of the horse-like hook. The cap covers the first and second fixing bases of the fastening slider, the end portion of the pulling piece, the horse-like hook and the elastic piece. The zipper head assembly structure of the present invention reduces efficiently the material cost, simplifies the manufacturing procedure much, and reduces the manufacturing cost. Further, the elastic piece is fixed on the fastening slider more firmly, so the elastic piece and the horse-like hook can abut to each other sufficiently.

1. Field of the Invention
The present invention relates to a zipper head assembly structure, and in particular to a zipper head assembly structure capable of fixing an elastic piece to a fastening slider.
2. Description of Prior Art
With reference to FIGS. 1 and 2, a conventional zipper head assembly structure is shown. The conventional zipper head assembly structure comprises a fastening slider 1, a pulling piece 2, a horse-like hook 3 and a cap 4. The above components of the conventional zipper head assembly structure are assembled in the following procedure. One end portion 22 of the pulling piece 2 is positioned into a recessed space 13 of the fastening slider 1. The pulling piece 2 is pushed toward one end of the fastening slider 1, so that a first fixing base 11 or a second fixing base 12 of the fastening slider 1 can be put around a hole 21 of the pulling piece 2. Then, the horse-like hook 3 is fixed to the first fixing base 11 and the second fixing base 12 of the fastening slider 1. The head portion 31 of the horse-like hook 3 is positioned in a groove 111 of the first fixing base 11, while the tail portion 32 of the horse-like hook 3 is positioned to abut against the bottom of the groove 121 of the second fixing base 12. The abdominal portion 33 of the horse-like hook 3 is supported on the end portion 22 of the pulling piece 2. The stop portion 34 of the horse-like hook 3 extends into a sliding groove 14 of the fastening slider 1 via a horse-like hook hole 15 between the first fixing base 11 and the second fixing base 12. Finally, the cap 4 is used to cover on the first fixing base 11 and the second fixing base 12 of the fastening slider 1. An elastic piece 41 is inserted into the interior of the cap 4 for abutting on the horse-like hook 3.
However, in the above assembling procedure, the elastic piece 41 should be firstly fixed in the cap 4. In order to insert the elastic piece 41 into the cap 4, the area of the elastic piece 41 should be made larger to mate with the interior of the cap 4. Since the elastic piece 41 is made of expensive material, the material cost is increased. Further, in the existing manufacturing procedure, the elastic piece 41 is firstly fixed within the cap 4 in one machine, and then the cap 4 provided with the elastic piece 41 is processed and mounted to the fastening slider 1 in another machine. Therefore, such manufacturing procedure becomes very troublesome, increasing the additional manufacturing cost. Further, since the elastic piece 41 inserted into the cap 4 is positioned slightly far from the horse-like hook 3, the elastic piece should be bent to project downward to abut against the horse-like hook 3. As a result, such bending step makes the manufacturing procedure more troublesome.
Further, since the elastic piece 41 is fixed within the cap 4 with four contacting points, such fixing is not stable. If the elastic piece 41 is subjected to an improper force, the projecting portion of the elastic piece 41 may be become flatter, causing weaker abutment between the elastic piece 41 and the horse-like hook 3.
Therefore, in view of the above drawbacks, the inventor proposes the present invention to overcome the above problems based on his deliberate researches and related principles.


A seal ring for sealing a space formed between a cylinder and a movable member inserted into the cylinder is essentially composed of a seal ring body which is fitted into a groove formed in the inner periphery of the cylinder. The seal ring body is formed of a resin material such as fluoride resin and a filler mixed with the resin material so that the seal ring body has a thermal expansion coefficient substantially equal to that of the cylinder. The filler is also mixed with the resin material so that the filler is oriented in a circumferential direction of the seal ring body. It is preferred to use a filler made of carbon fiber having an aspect ratio of about 5 to 400.

The present invention relates to a seal ring particularly utilized for a rotating, oscillating of reciprocating portion subjected to hydraulic control such as an automatic speed change gear or a power steering mechanism of an automobile, for example.
A seal ring particularly made of polytetrafluoro ethylene resin (to be called PTFE, hereunder) having improved low friction and wear-proof properties has been widely utilized in the prior art instead of cast iron for power steering mechanisms.
In such seal ring of the prior art, a seal ring body made of resin material is fitted into a groove formed in an inner peripheral surface of a cylinder to thereby seal a portion between the cylinder and a movable member disposed in the cylinder. The seal ring body is provided with a cut portion shaped in a straight cut, bias cut, step cut or the like. Seal rings provided with the bias cut have been widely utilized because of its stable sealing properties in a wide temperature range.
However, in the prior art described, the seal ring provided with the bias cut is apt to be influenced by its thermal expansion coefficient, resulting in the following problem.
Namely, because the seal ring body made of the resin material has a thermal expansion coefficient larger than the thermal expansion coefficient of the cylinder made of a metal material such as aluminium, even when the cut portion is adjusted to substantially reduce the amount of any leakage of oil, for example, at an ambient temperature, the size of the gap of the abutment portion of the cut ends of the seal ring body increases at a temperature higher than at the ambient temperature, resulting in the increasing of the leakage amount. On the other hand, even when the abutment portion is adjusted to substantially reduce the leakage at a high temperature, the size of the gap at the abutment portion also increases because the amount of shrinkage in the seal ring body is higher than that of the cylinder. This shrinkage results in the increasing of the leakage amount at the ambient temperature.
Furthermore, when the amount of leakage at the ambient temperature is reduced, the seal ring body has an interference fit with the cylinder at the high temperature, such that the minimum pressure, (i.e. minimum actuating pressure) of the seal ring body movable in the groove is adversely increased.
The above described problems result from the dimensional change of the gap at the abutment portion of the seal ring body due to the temperature change. In other words, the thermal expansion coefficient of the seal ring body is larger than that of the cylinder. In order to effectively reduce the dimensional change of the gap, it may be possible to reduce the range of the common difference of the outer diameter of the seal ring body (for example, to about 0.04 mm with respect to .phi. of 56 mm), but this working is troublesome and degraded products can often result.


A deep ocean gas storage system for storing compressed gas, the system comprising an inflexible thin walled storage vessel anchored to the sea floor having an axis located in water substantially perpendicular to and on a sea floor below sea level, a gas intake for admitting and discharging compressed natural gas to and from the vessel; a water port for admitting and discharging water to the vessel using hydrostatic pressure to discharge compressed gas from the vessel at a substantially constant discharge pressure as the volume of the gas in the storage vessel decreases when water content of the vessel increases; a conduit fluidly connected with the water port oriented substantially parallel to the axis having a discharge opening above the level of sea water in the vessel; and a valve disposed at the gas intake to the vessel for controlling compressed gas admission and discharge.

Oil at standard temperature and pressure conditions is a liquid and is reasonably dense and suitable for transportation. The market for oil is global in nature because it can be readily transported in tankers and stored in surface storage containers. Because of natural gases gaseous nature, natural gas is far more difficult to transport and store. Most natural gas is transported through pipelines, which means that sources of supply must be local. Gas is usually stored in underground natural caverns and the storage locations are therefore tied to the availability of these caverns.
A need has exists to link a subsea storage facility near the subsea pipelines in an economical manner, that is easy to monitor and with few moving parts for failure.
The main complication in development of a global gas industry is that at standard temperature and pressure (stp), gas is extremely diffuse and therefore has very little economic value for a given volume compared to oil (a difference of three orders of magnitude at $7/MCF for gas and $50/BBL for oil). Due to this difference in value per volume, combined with the gaseous state, transport of gas over long distances at stp is not economically feasible. Various methods for achieving more favorable ratios of gas value for a given volume are commonly used to make the transmission and storage more economically attractive, such as compressing or liquefying it. Compression is the most commonly used method for transportation because it is the preferred method of use in pipeline systems. Both methods can be used for marine transportation wherein liquefaction is used for Liquified Natural Gas (LNG) and compression is used for Compressed Natural Gas (CNG).
A measure of the economic feasibility for storing and transporting gas is the volume ratio, defined as volume of gas that can be stored in a given volume in its compressed condition divided by the volume of gas that could be stored in the same volume at standard temperature and pressure. LNG has a volume ratio of roughly 600, which means that its economic value per cubic meter is roughly a factor of two less than that of oil at the price conditions listed above. Although CNG has not been used to date, it has some applications where it may be a better method than LNG, depending on the gas conditions and the distance from the end user. CNG can achieve ratios of roughly 300, or roughly a factor of two less than that of LNG but has advantages because the facilities required at both source and destination are simpler than those required for LNG.
Both LNG and CNG require some means to get the gas back to standard pipeline conditions once the gas has reached its desired destination. Both LNG and CNG have severe complications storing gas after delivery. For LNG this is addressed by building either pressurized or cryogenic storage containment tanks onshore. Both methods are expensive and dangerous. CNG has not been used to date, but one of the main reasons could be the lack of availability of efficient storage means.
Various oil storage systems have been deployed on the seafloor, namely the Harding platform in the North Sea and the Dubai Oil Storage tanks in the Middle East. Additionally, oil over water storage systems have been deployed from Gravity Based Structures in the North Sea. Whereas oil has been stored on the seafloor for many years and mainly as a matter of convenience, storage of gas on the seafloor has never been done and yet has some very important technical advantages over gas storage through other methods. Additionally, gas storage on the seafloor can be an enabling technology for some of the CNG applications that are currently contemplated.
All presently available means for storing natural gas are dangerous with significant potential for both environmental damage and loss of life and property. Underground natural salt caverns are typically used for low pressure storage of natural gas. There have been many accidents related to these caverns, including both fires and explosions. LNG storage tanks have also had major accidents resulting in disastrous consequences. As both LNG demand and population along the shores increase, it has become increasingly difficult too locate LNG regassification units for permitting reasons despite the large market need.
The proposed gas storage invention can serve in several applications.
A need exists for a system for storing natural gas which is produced during a well testing operation offshore wherein the oil and gas operator does not want to commit to building a pipeline for gas export before the reservoir has been producing for long enough to evaluate its characteristics and condition.
A need exists for a system that can store significant volumes of gas and yet can be readily deployed and reused at the end of its initial service. This system has to be both portable for second and additional use applications and the design must also be capable of addressing all anticipated applications including a range of water depths and pressures.
A need exists for a gas storage system that can be built in a desired location close to a pipeline network and independent of the prior existence of naturally occurring caverns.
A need exists for a gas storage system which is remote from human life and property.
A need exists for a gas storage system that is not prone to catastrophic gas release and consequent fire or explosion.
A need exists for a gas storage system that can be used in conjunction with any of the proposed CNG or LNG systems in order to decouple the depressurization conditions from the immediate pipeline needs.
The present embodiments meet these needs.
The present embodiments are detailed below with reference to the listed Figures.


A solid electrolytic capacitor 1 includes a capacitor element 2 and a resin package 9 enclosing the capacitor element. The capacitor element includes a sintered body 3 of valve metal powder, an anode 4a provided by embedding an anode wire 4 in the sintered body, and a cathode 5 provided by forming a metal layer on the sintered body. A first lead member 6 in the form of a plate is connected to the anode wire 4. The end of the first lead member projects from a side surface 9a of the resin package 9 to provide an anode terminal T1. A second lead member 7 in the form of a plate is connected to the cathode 5. The end of the second lead member projects from a side surface 9b of the resin package 9 to provide a cathode terminal T2. By extending the first and the second lead members 6 and 7 generally horizontally at the substantially same height from the lower end of the resin package and making the portions projecting from the resin package 9 serve as the anode terminal T1 and the cathode terminal T2, the lead length between the anode 4a of the capacitor element 2 and the anode terminal T1 and the lead length between the cathode 5 and the cathode terminal T2 is made as short as possible, whereby ESL is reduced.

In a power supply circuit for an IC (Integrated Circuit) such as a CPU (Control Processing Unit) of a computer, high frequency noise is generated due to the high-speed processing of the IC. In light of this, a bypass capacitor for removing high-frequency noise from the power supply circuit is often provided in the power supply line for the IC. The bypass capacitor fulfills the decoupling function of preventing noise transmission from the power supply circuit to the IC and the stabilizing function of preventing the fluctuation of power supply voltage by temporarily supplementing or storing current when the load current changes largely. For such a bypass capacitor, use may be made of a ceramic capacitor or a tantalum capacitor.
Recently, with the speed increase of an IC, a bypass capacitor having a large capacitance, a low ESL (Equivalent Series Inductance) and a high responsibility is in demand. Also for a chip-type solid electrolytic capacitor using a sintered body of valve metal powder such as a tantalum capacitor, further decrease of the ESL is needed.
As compared with a chip ceramic capacitor, to increase the capacitance of a solid electrolytic capacitor is relatively easy. However, in a conventional chip-type solid electrolytic capacitor, the capacitor element, which substantially acts as a capacitor, is enclosed in a resin package, and this requires leads for connecting the anode and the cathode of the capacitor element to an anode terminal and a cathode terminal provided outside the resin package. These leads, however, result in an equivalent series inductance (ESL), thereby putting a limitation on the amount of decrease in the ESL of conventional chip-type solid electrolytic capacitors.
FIG. 19 is a sectional view showing a conventional solid electrolytic capacitor configured to be mounted on the surface of a printed board.
The illustrated solid electrolytic capacitor 100 includes a capacitor element 101 in a prismatic form enclosed in a resin package 107 in the form of a rectangular parallelepiped. The lower surface 107c of the resin package 107 is the mount surface to be mounted on a printed board. The resin package 107 may be about 2 to 3 mm in length (lateral dimension in FIG. 19), about 1 to 2 mm in width, and about 1 to 2 mm in height. The mounting electrode (the end 105c of an anode terminal 105 and the end 106c of a cathode terminal 106 in FIG. 19), which is formed on the lower surface 107c of the resin package 107, may be about 0.8 mm in length (lateral dimension in FIG. 19).
The capacitor element 101 comprises a prismatic porous sintered body 102 made of valve metal, an anode wire 103 of about 0.2 mm in diameter partially embedded at the substantial center of a side surface 102a of the porous sintered body 102, and a metal layer 104 serving as a cathode (hereinafter referred to as a cathode 104 when necessary) and formed on surfaces other than the side surface 102a. The region between the portion of the anode wire 103 which is located within the porous sintered body (hereinafter, this portion is referred to as an anode 103a) and the cathode 104 functions as a capacitor.
To the portion 103b of the anode wire 103 which projects from the porous sintered body 102, the anode terminal 105 made of a conductive material and channel-shaped in section is connected to guide the anode 103a to the lower surface 107c of the resin package 107. To the metal layer 104 on the upper surface of the capacitor element 101, the cathode terminal 106 made of a conductive material and channel-shaped in section is connected to guide the cathode (the entire metal layer 104) of the capacitor element 101 to the lower surface 107c of the resin package 107.
The base end 105a of the anode terminal 105 serves as a connecting portion for connection with the lead portion 103b of the anode wire 103, whereas the end 105c of the anode terminal 105 serves as a connecting portion (hereinafter referred to as mount portion) for connection with an electrode on the mount surface of the printed board by e.g. soldering. The intermediate portion 105b of the anode terminal 105 serves as a lead portion for guiding the anode 103a of the capacitor element 101 to the mount portion 105c on the lower surface 107c of the resin package 107.
Similarly, the base end 106a of the cathode terminal 106 serves as a connecting portion for connection with the cathode 104, whereas the end 106c of the cathode terminal 106 serves as a connecting portion (mount portion) for connection with an electrode on the mount surface of the printed board by e.g. soldering. The intermediate portion 106b of the cathode terminal 106 serves as a lead portion for guiding the cathode 104 of the capacitor element 101 to the mount portion 106c on the lower surface 107c of the resin package 107.
The lead portion 106b of the cathode terminal 106 is bent to be inclined at a region within the resin package 107. This is because, in forming the anode terminal 105 and the cathode terminal 106 using a lead frame, the position of the connecting portion 105a of the anode terminal 105 for connection with the anode wire 103 and the position of the connecting portion 106a of the cathode terminal 106 for connection with the cathode 104 are deviated from each other correspondingly to the height difference between the anode wire 103 and the cathode 104 of the capacitor element 101.
Each of the anode terminals 105 and the cathode terminal 106 is bent at the position exiting the resin package 107 to extend downward along the side surface 107a, 107b of the resin package 107 and bent at the lower end of the side surface toward the lower surface 107c. The end 105c of the anode terminal 105 and the end 106c of the cathode terminal 106, which extend along the lower surface 107c of the resin package 107, serve as mount portions.

Solid electrolytic capacitor and structure for mounting this solid electrolytic capacitor on board


A semiconductor substrate has a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a well contact region, a first dummy element, a second dummy element, a first transistor and a second transistor. The first and second memory cell regions are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is located over the well on a border between the first memory cell region and the second memory cell region. The well contact region is formed in the well in the border region and is electrically connected to a wiring layer for fixing the voltage of the well. The first and second dummy elements are formed in the border. The first transistor, that is a component of the memory cell, is formed in the first memory cell region and is located adjacent to the first dummy element. The second transistor, that is a component of the memory cell, is formed in the second memory cell region and is located adjacent to the second dummy element. The border region has a length that is equivalent to the sum of one half of the length between one of side sections of a gate electrode of the first transistor on the side of the first dummy element and one of side sections of the first dummy element on the side of the gate electrode of the first transistor, the length of the first dummy element, the length between one of the side sections of the first dummy element on the side of the second dummy element and one of side sections of the second dummy element on the side of the first dummy element, the length of the second dummy element, and one half of the length between one of side sections of a gate electrode of the second transistor on the side of the second dummy element and one of the side sections of the second dummy element on the side of the gate electrode of the second transistor.

1. Field of the Invention
The present invention relates to a semiconductor memory device such as an SRAM, and a method for manufacturing the same.
2. Description of Related Art
A semiconductor memory device has a structure in which peripheral circuits and memory cell arrays consisting of numerous memory cells are formed on a semiconductor substrate. To increase the capacity of a semiconductor memory device, a higher integration of the semiconductor memory device needs to be attained. In particular, an SRAM (Static Random Access Memory) has a large number of device elements that form each memory cell, and therefore a higher integration therefore is required.
The present invention has been made to solve the above-described problems. It is an object of the present invention to provide a semiconductor memory device having a structure that can achieve a higher integration of the semiconductor memory device and a method for manufacturing the semiconductor memory device.
In accordance with an embodiment of the present invention, a semiconductor memory device comprises a semiconductor substrate having a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a well contact region, a first dummy element, a second dummy element, a first transistor and a second transistor. The well is formed in the semiconductor substrate. The first and second memory cell regions are part of the main surface and are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is part of the main surface, and is located over the well on a border between the first memory cell region and the second memory cell region. The well contact region is formed in the well in the border region. The well contact region electrically connects to a wiring layer for fixing the voltage of the well. The first and second dummy elements are formed in the border region and do not function as device elements. The first transistor is a component of the memory cell. The first transistor is formed in the first memory cell region and is located adjacent to the first dummy element. The second transistor is a component of the memory cell. The second transistor is formed in the second memory cell region and is located adjacent to the second dummy element. The border region has a length that is equivalent to the total of one half of the length between one of side sections of a gate electrode of the first transistor on the side of the first dummy element and one of side sections of the first dummy element on the side of the gate electrode of the first transistor, the length of the first dummy element, the length between one of the side sections of the first dummy element on the side of the second dummy element and one of side sections of the second dummy element on the side of the first dummy element, the length of the second dummy element, and one half of the length between one of side sections of a gate electrode of the second transistor on the side of the second dummy element and one of the side sections of the second dummy element on the side of the gate electrode of the second transistor.
In the semiconductor memory device in accordance with the present invention, the border region has a length defined by the above-described values. As a result, while dummy elements are formed, a higher integration of a semiconductor memory device and the reduction of the chip size can be achieved. In other words, a higher integration of a semiconductor memory device can be achieved with the same chip size. On the other hand, the chip size can be reduced with the same number of element devices.
In a preferred embodiment, the border region is located between the first memory cell region and the second memory cell region. A predetermined number of memory cells are formed in each of the first and second memory cell regions. A well contact region is formed in the well in the border region. The well contact region electrically connects to a wiring layer for fixing the voltage of the well containing these memory cells.
Also, dummy elements are formed in the border region. The dummy elements are formed to prevent the optical proximity effect and the loading effect. In other words, if the dummy elements are not formed in the border region, the pattern density in the border region becomes different from the pattern density in the first and second memory cell regions. As a consequence, the optical proximity effect and the loading effect may occur near the border region. Accordingly, a designed memory cell pattern is not obtained near the border region. As a result, memory cells near the border region may become defective.
In a preferred embodiment, the well contact region may be formed in a self-alignment manner, using the first and second dummy elements as masks.
Preferably, the well contact region may be of a first conductivity type. Further, the semiconductor memory device may preferably have word lines wherein the word lines extends from the first memory cell region to the second memory cell region passing through the border region, and the word line are of a second conductivity type.
In accordance with one embodiment of the present invention, each of the memory cells may preferably include a first load transistor, a second load transistor, a first driver transistor and a second driver transistor that form a flip-flop.
The semiconductor memory device in accordance with one embodiment of the present invention may preferably further include a first conductive layer and a second conductive layer. The first and second conductive layers are respectively formed in the first and second memory cell regions. The first conductive layer serves as gate electrodes of the first load transistor and the first driver transistor. The second conductive layer servers as gate electrodes of the second load transistor and the second driver transistor. Preferably, the first conductive layer is generally in the shape of a letter xe2x80x9chxe2x80x9d and the second conductive layer is generally in the shape of the number xe2x80x9c7xe2x80x9d.
In accordance with one embodiment of the present invention, the semiconductor memory device may preferably form an SRAM.
In accordance with one embodiment of the present invention, each of the first and second dummy elements in the semiconductor memory device has a length equivalent to the length of a gate electrode of each of the memory cells.
In accordance with one embodiment of the present invention, one half of the length of each of the first and second dummy elements is greater than an alignment error that occurs when a mask member to be used for forming the well contact region is formed. One half of the length of a dummy element refers to one half of the gate length of the dummy gate when a side wall dielectric film is not formed on a side of the dummy element. When a side wall dielectric film is formed on the side of the dummy element, it refers to one half of the length of the dummy element plus the length of the side wall dielectric film.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate having a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a first source region, a second source region, a well contact region, a first dummy element and a second dummy element. The well is formed in the semiconductor substrate. The first and second memory cell regions are part of the main surface and are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is part of the main surface, and is located over the well on a border between the first memory cell region and the second memory cell region. The first source region is formed in the well, and extends over the border region and the first memory cell region. The second source region is formed in the well, and extends over the border region and the second memory cell region. The well contact region is formed in the well in the border region. The well contact region electrically connects to a wiring layer for fixing the voltage of the well. The first and second dummy elements are formed in the border region and do not function as device elements. The border region has a length that is equivalent to the total length of one half of the length of the first source region, the length of the first dummy element, the length of the well contact region, the length of the second dummy element and one half of the length between the second source region.
In the semiconductor memory device in accordance with the present invention, the border region has a length defined by the above-described values. As a result, while dummy elements are formed, a higher integration of a semiconductor memory device and the reduction of the chip size can be achieved. In other words, a higher integration of a semiconductor memory device can be achieved with the same chip size. The chip size can be reduced with the same number of element devices.
A semiconductor memory device in accordance with one embodiment of the present invention comprises a semiconductor substrate, a first conductivity type well region provided in the semiconductor substrate, a first memory cell region provided over the well region, a second memory cell region provided over the well region, and a border region provided over the well region and between the first memory cell region and the second memory cell region. The border region includes first and second dummy wirings disposed over the well region, a first impurity region of a second conductivity type shared by the first memory cell region and the border region and disposed adjacent to the first dummy wiring, a well contact region of a first conductivity type between the first dummy wiring and the second dummy wiring, and a second impurity region of the second conductivity type shared by the second memory cell region and the border region and disposed adjacent to the second dummy wiring.
A semiconductor memory device in accordance with one embodiment the present invention includes a semiconductor substrate having a main surface, a well, a plurality of memory cells, a first memory cell region, a second memory cell region, a border region, a well contact region, a first dummy element and a second dummy element. The well is formed in the semiconductor substrate. The first and second memory cell regions are part of the main surface and are located over the well. The memory cells are formed in the first and second memory cell regions. The border region is part of the main surface, and is located over the well on a border between the first memory cell region and the second memory cell region. The first and second dummy elements are formed in the border region and do not function as device elements. The well contact region is formed in the well in the border region, and is formed in a self-alignment manner using the first and second dummy elements as masks. The well contact region electrically connects to a wiring layer for fixing the voltage of the well.
In accordance with one embodiment of one embodiment of the present invention, a method is provided for manufacturing a semiconductor memory device having a semiconductor substrate defining a main surface that has a first memory cell region, a second memory cell region, and a border region between the first memory cell region and the second memory cell region. The method includes the step of forming wells in the semiconductor substrate below the first memory cell region, the second memory cell region and the border region, the step of forming gate electrodes in the first and second memory cell regions, the step of forming dummy gates of first and second dummy elements in the border region, the step of forming a first mask member that covers the border region and exposes the first and second memory cell regions, and the step of forming a first source/drain region of the first dummy element and a second source/drain region of the second dummy element by implanting ions of a second conductivity type in the well, using the first mask member as a mask.
The first source/drain region extends over the border region and the first memory cell region, and the second source/drain region extends over the border region and the second memory cell region. The method for manufacturing a semiconductor memory device further includes the step of forming a second mask member that covers the first and second memory cell regions and has an opening section in the border region, and the step of forming a well contact region between the first dummy element and the second dummy element by implanting ions of a first conductivity type in the well, using the second mask member, the first dummy element and the second dummy element as masks.
Preferably, the step of forming the gate electrodes in the first and second memory cell regions, and the step of forming the dummy gates of first and second dummy elements in the border region may be conducted in the same step. This reduces the number of manufacturing steps.
In the method for manufacturing a semiconductor memory device in accordance with the present invention, a positional alignment is conducted when forming the second mask member such that a side surface of the opening section is positioned over the first and second dummy elements, and one half of the length of each of the first and second dummy elements is greater than an alignment error value that may occur when forming the second mask member. This prevents the opening section from being positioned at the first and second source/drain regions. If the opening were positioned at the first and second source/drain regions, ions would be implanted in the first and second source/drain regions when the well contact region is formed. This may negatively affect the characteristics of the transistors when the xe2x80x9cfirst and second source/drain regionsxe2x80x9d means source regions.
It is noted that one half of the length of a dummy element refers to one half of the gate length of the dummy element when a side wall dielectric film is not formed on a side of the dummy element. When a side wall dielectric film is formed on the side of the dummy element, it refers to one half of the length of the dummy gate plus the length of the side wall dielectric film.
The method for manufacturing a semiconductor memory device in accordance with the present invention may preferably include the step of forming a word line that extends from the first memory cell region through the border region to the second memory cell region. Also, the step of forming the second mask member may not expose the word line through the opening section of the second mask member. This prevents the word line from being injected with ions of a first conductivity type. As a result, this would prevent p-n junctions from being formed in the word line.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, various features of embodiments of the invention.

Semiconductor memory device and method for manufacturing the same


The optical signal multiplexer/demultiplexer of the invention is characterized by incorporating a bidirectional optical transceiver which is capable of using individual channels working in a transmitting and receiving modes simultaneously. The device consists of a number of optical prisms combined into a single module and provided with appropriate dichroic mirrors and interferrometric filters located on the outer surfaces of the prisms. According to one embodiment of the invention, the module consists of two sequentially arranged parallelogram prisms, a single-channel signal input/output unit with an optical collimator/focusator on one side of the prism module and a two-channel signal output/input unit with a respective optical collimator/focusator on the other side of the prism module. The first prism, which is located on the single-channel side has a first antireflective coating transparent to all input/output signals (λ1, λ2, λ3) and a second coating located on the two-channel side of the first prism that reflects one optical signal (λ2) and passes the remaining two optical signals (λ1 and λ3). Thus, the input/output signals of several different wavelengths can be multiplexed/demultiplexed while passing in a multi-bounce zigzag expanded beam light paths in various combinations of signal-propagation directions. A pair of prism modules described above may be built-into a section of the main signal transmission/reception line and the output side of each prism module may be connected to a respective bidirectional optical signal transceiver.

One of main goals in optical communication and data transmission systems is the most optimal connection between the transmission and receiving sides. In modern systems this goal is achieved by efficient management of optical signals, i.e., by transmitting/receiving signals between communicating sides along the shortest paths and with involvement of the minimal possible quantity of indispensable optical network components.
There exists a great amount of different optical transmission/receiving systems, which are in practical commercial use for optical communication. Recently, an interest arose to possibility of incorporating specific local networks into existing commercial communication systems. Such incorporation must be fulfilled without interference with the signals transmitted through the main lines and without necessity of modification of the aforementioned existing systems, as well as without degradation of their performance characteristics.
For example, let us assume that a long-haul commercial communication line is used for transmitting and receiving data between two sides with optical signals having a wavelength 1550 nm and that a local network incorporated into the main line operates with optical signals having wavelength of 1480 nm and 1310 nm. It is understood that elements of local networks e incorporated a section of the main communication trunk should not interfere with the optical signals transmitted through the main line and should not impair the quality of the main signals.
Incorporation of local networks into main lines can be carried out through the use of optical signal multiplexers/demultiplexers, signal add/drop optical modules, etc.
An example of a multiplexing/demultiplexing module suitable for the above-mentioned purpose is described in U.S. Pat. No. 6,252,719 issued on Jan. 26, 2001 to B. R. Eichenbaum. This module is schematically shown in FIG. 1 in the form of a beam splitter/combiner unit 20 for multiplexing and/or demultiplexing a plurality of optical signals shown in FIG. 1 by arrows with appropriate wavelengths. In the embodiment shown in FIG. 1 the system has three input/output signals of respective wavelengths λ1 λ2 λ3. The module consists of an optical fiber 22 for transmitting and receiving optical signals of wavelengths λ1 λ2 λ3, a collimating lens 24 located in front of the input/output end of the optical fiber 22, a splitter/combiner 26 and three receiver/transmitters 28, 30, and 32 with respective collimating lenses 34, 36, and 38 between the splitter/combiner 26 and respective receiver/transmitters 28, 30, and 32.
The splitter/combiner 26 includes a first dichroic mirror 40 having low loss transmission over a first preselected range of wavelengths including λ1 λ2 so as to substantially transmit signals having wavelengths λ1 λ2 through the first mirror 40 and along an optical signal path P of the module 20. The first dichroic mirror 40 also has high reflectance over a second preselected range of wavelengths including λ3 so as to substantially reflect from the first mirror 40 signals having wavelength λ3. A second dichroic mirror 42, disposed along the optical signal path P for receiving from the first mirror 40 the signals transmitted through the first mirror 40, has low loss transmission over a third preselected range of wavelengths including λ1 so as to substantially transmit signals having wavelength λ1 through the second dichroic mirror 42. The second dichroic mirror 42 also has high reflectance over a third preselected range of wavelengths including λ2 so as to substantially reflect from the second mirror 42 signals having wavelength λ2.
Other embodiments of the multiplexing/demultiplexing systems disclosed in the aforementioned patent are based on the same principle and differs from each other by positions of transmitters/receivers relative to mirrors.
A disadvantage of the systems described in U.S. Pat. No. 6,252,719 consists in that the beam splitter/combiners used in these systems are not suitable for use in a bidirectional mode with simultaneous transmission and reception of the signals along the same fiber. This is because all channels used in the system are designed only for a single-operation function, e.g., only for transmitting or only for receiving. In the context of the present invention, the term "channel" means an individual optical fiber used for transmission/reception of optical signals. For example, in the system of FIG. 1, two channels, e.g., those corresponding to the transmitters/receivers 28 and 30, can be used only for reception of the signals, while the channel corresponding to one of the channels can work as a receiver and two channels can work as transmitters. It is understood that the aforementioned module cannot be incorporated into a main long haul communication line, e.g., for bidirectional optical fiber communications between the central telephone exchange side and a subscriber side, which utilizes bidirectional transceivers having individual channels working in a transceiving and receiving modes simultaneously.
Examples of aforementioned bidirectional optical signal transceivers are described in U.S. Pat. No. 6,075,635 issued on Jun. 13, 2000 to T. Butrie, et al., U.S. Pat. No. 5,485,538 issued on Jan. 16, 1996 to T. Bowen, et. Al, and in U.S. patent application Ser. No. 10/107,4346 filed on Feb. 12, 2002 by Igor Gurevich, et al. and relating to optical module for high-speed bidirectional transceiver. U.S. Pat. No. 5,005,935 issued on Apr. 9, 1991 to T. Kunikane, et al. discloses a wavelength-division multiplexing optical transmission system, which transmits light of wavelengths λ1, λ2, λ3 (λ1<λ2<λ3) by way of a single optical fiber. An optical multiplexer/demultiplexer of the filter type is used which includes a parallelogram prism, a first filter formed on a side face of the parallelogram prism, and second and third filters formed on the opposite side face of the parallelogram. Bidirectional optical fiber communications between the central telephone exchange side and a subscriber side can be achieved using such optical multiplexer/demultiplexer of the filter type. However, similar to the previously criticized module, the parallelogram prism module of U.S. Pat. No. 5,005,935 also cannot be used in optical fiber communications systems, which utilize bidirectional transceivers having individual channels working in a transceiving and receiving modes simultaneously.
U.S. Pat. No. 6,167,171 issued on Dec. 26, 2000 to M. Grasis, et al. and U.S. Pat. No. 6,198,857 issued on Mar. 6, 2000 to M. Grasis, et al. both relate to optical multiplexing devices based on the use of optical prisms with filters and mirrors formed on external surfaces of the prisms.
Thus, U.S. Pat. No. 6,167,171 describes an optical multiplexing device comprising multiple wavelength division multiplexers cascaded together. A first one of the wavelength division multiplexers has a common port and other optical ports, which are optically coupled to the common port. The common port may be optically coupled to a trunk line of a system employing wavelength division multiplexing, for example, a fiber-optic telecommunication system employing 4, 8, 16 or other number of multiplexed channels. The optical ports include multiple channel ports, each of which is transparent to a corresponding wavelength sub-range and reflective of other wavelengths. The second-wavelength division multiplexer has a common port optically coupled to one of the optical ports of the first-wavelength division multiplexer. The second-wavelength division multiplexer also has multiple optical ports, which are optically coupled to its common port and include multiple wavelength-selective channel ports. A waveguide, such as a fiber-optic line, can optically connect the common port of the second-wavelength division multiplexer to an optical port of the first-wavelength division multiplexer. The cascaded WDMs (wavelength division multiplexers) each may be optically coupled to the output of a passive coupler and a housing may be provided defining an enclosed space in which the optical multiplexing device is mounted. Optionally, additional WDMs may be cascaded with the first two WDMs in a parallel or branched formation, an in-line formation or some combination. Preferably, the channels are interleaved, such that they are removed from the multiplexed signal in certain non-sequential order. The optical multiplexing device also may employ compound interleaving wherein adjacent channels are multiplexed by different ones of the cascaded WDMs. The optical multiplexing devices can operate to add signals, remove signals or a combination of both.
In its form as described and shown in the specification of aforementioned U.S. Pat. No. 6,167,171, the module disclosed in this patent cannot be used in conjunction with an optical fiber communications system that utilizes bidirectional transceivers with individual channels working in a transceiving and receiving modes simultaneously.
The second patent, i.e., U.S. Pat. No. 6,198,857, also relates to an optical multiplexing device for multiplexing optical signals, for example, for a fiber-optic telecommunication system employing wavelength division multiplexing. This device is an add/drop type device, which has a filter assembly defining a light path, preferably a multi-bounce zigzag expanded beam light path, from a common port at least to a first channel port and then a second channel port and then a pass-through port. The first channel port has a first optical filter element, for example, a multi-cavity interference filter, which is transparent to a wavelength sub-range within the wavelength range passed by the common port and the pass-through port, and substantially reflective of other wavelengths within such wavelength range. The second channel port includes a second optical filter element having light transmittance and reflectance properties substantially the same as those of the first optical filter element. The optical multiplexing device can be used to extract or drop a selected wavelength sub-range, most typically a single channel signal, from the multiplexed light, and then to inject a new signal into the multiplexed light at that same wavelength sub-range. In accordance with preferred embodiments, the optical multiplexing device serves as an add/drop filter arrangement to extract the signal of a particular channel and then immediately use the available channel by injecting a new signal at that same wavelength sub-range. The device described in this patent possesses the same disadvantages as all the previously analyzed references.

Bidirectional optical signal multiplexer/demultiplexer


A game apparatus is provided for playing a game which tests the memories of game players. The apparatus includes a base, a rotatable disk mounted on the base, and a cover mounted on the base above the disk. A clutch mechanism is provided for rotating the disk, and a braking mechanism is provided for stopping rotation of the disk in one of a plurality of predetermined positions. The cover includes a plurality of spaced apertures and the disk includes a plurality of groups of matched pictures which are oriented so that a plurality of matched pairs of pictures are aligned with the apertures when the disk is stopped in one of the predetermined positions.

The instant invention relates to game apparatus and more particularly to game apparatus for use in playing a game which tests the memory of the players.
It is well known in the toy art that games which test the memories of the players have significant play value. It is also well known in the art that games of this type have significant educational value in that they are capable of strengthening the memories of children. In this regard, a variety of children's memory games have heretofore been known. For example, Milton Bradley Company currently manufactures and markets a line of 5 different memory games including ORIGINAL MEMORY.RTM., ANIMAL FAMILIES MEMORY.RTM., MICKEY MOUSE MEMORY.RTM., MAY I? MEMORY.RTM. and MATCH & MOVE MEMORY.RTM.. However, these games do not include game apparatus similar to the instant invention and therefore they are believed to be only of general interest. In addition, a variety of adult games have been available which test the memories of the game players.

Memory matching game with mechanically activated rotating disk


A system and method for improving the retrieval performance of a query engine in a visual information retrieval (VIR) system by encoding domain-specific knowledge into the VIR system through a visual dictionary or "victionary". The victionary is a dictionary-like information-mapping module that is used to retrieve visual information at a "semantic" level. A VIR system that performs generic image processing is enhanced by adding a query transformation unit and a query expansion unit, i.e., the victionary. With these additional components, a user may present a query either as a text term (such as a keyword or phrase), or as an image (with weights) and execute a "semantic query". During semantic query processing, the victionary-enhanced system transforms the user's original term (or image query) to a set of equivalent queries, and internally executes all the equivalent queries before presenting the results to the user. The victionary unit is responsible for taking the term (or image query) and finding the equivalent feature vectors (and weights). A result processor accumulates the score sheets of each equivalent query and presents a composite ranking that reflects a faithful representation of each equivalent query to the user. The architecture of the victionary-enhanced system is open and extensible, so that one or more domain-specific victionary modules can be plugged into the system. The plug-in architecture of the victionary module is effected through an application programming interface (API).

1. Field of the Invention
The present invention relates to database systems. More specifically, the invention is directed to a system for improving the performance of retrieving visual information from a database.
2. Description of the Related Technology
The emergent field of Visual Information Retrieval (VIR) has a purpose of developing techniques and systems to extract and access the content of visual media, which include images and videos. It is intended that the users of VIR systems are able to search through repositories of visual information just as in a textual database but without requiring that the visual media objects be pre-annotated with textual descriptors.
An important class of queries of query posed to a VIR system is a similarity query, where the user presents a clue to the system as a description of what he or she is looking for. The clue may be posited by:
a visual example, such as a similar picture; PA1 a sketch drawn to depict the search item; PA1 a set of keywords that describe the search item; PA1 a set of additional criteria, such as whether the user is more interested in the color of the visual media object, the relative sizes and spatial arrangements of interesting regions within the visual media object, and so on. PA1 two users may use the same clue with different intents; PA1 a user may use different clues with the same intent; PA1 the system cannot determine which aspect of the clue contains the real intent of the user. PA1 1. Current VIR Systems: There are several types of VIR systems currently available as research prototypes or commercial systems. FIG. 1 shows a block diagram of a computer-implemented system 100 with VIR capabilities. The system includes a computer, such as an Indy available from Silicon Graphics, Inc. Other computers, such as those based on the Alpha processor from Digital Equipment Corp., the Pentium family of processors from Intel, or the SPARC processor from Sun Microsystems, could be alternatively used. A visual display 104 is connected to the computer 102. User input 106 is received through any of a variety of input devices such as a keyboard, a mouse, or other pointing devices (not shown). A visual information retrieval system 110, a database management system (DBMS) 112 and an operating system (OS) 114 are also part of the computer-implemented system 100. A database 108 interfaces with the DBMS 112 and OS 114. The DBMS 112 is available from many vendors, such as the Universal Server marketed by Informix Software Inc., the Oracle8 Universal Data Server marketed by Oracle Corp., the DB2 system available from IBM, or the Sybase DBMS. The OS may be any of a variety of available operating systems, such as Unix, Microsoft Windows NT, or Solaris. PA1 2. Text Retrieval Systems: Many text retrieval systems use the notion of "query expansion", where an original query term is substituted by a list of other closely related terms. These close terms may be generated by adding suffixes using grammatical rules, by a set of synonyms found using a thesaurus lookup, by a relational knowledge representation structure like frame-networks, or by a natural language processing technique which helps the system disambiguate the word sense. Since these methods have been useful for complex queries in text retrieval systems, equivalent methods have been developed for use in VIR systems. However, because of the very different characteristics of text and visual information, any direct implementation of these methods for visual media is not meaningful. Explicit visual thesauri, although alluded to by some researchers such as D. Romer, Presentation at the seminar entitled "Towards a research agenda for cultural heritage in information networks", The Getty Art History Information Program, 1995, are not yet a reality, because the specification, implementation and use of such a mechanism has not been demonstrated. In fact, the only direct reference of a visual thesaurus in Romer, namely G. L. Lohse, K. Bilosi, N. Walker and H. H. Reuter "A Classification of Visual Representations", Communications of the ACM, Vol. 37(12), pp. 36-49, 1994, researches in a taxonomy of user perceptions of graphical entities like charts, graphs, icons, and pictures, and has no "synonym-" or "antonym-" like functionality that the notion of "thesaurus" implies. PA1 3. Current Computer Vision and Pattern Recognition Research: Recently researchers in computer vision and pattern recognition have approached the problem of visual information retrieval from a semantic object modeling and retrieval point of view. These research prototypes use one or more feature extraction techniques to model semantic concepts such as fire, people, and sky by user provided examples, and then use these models for retrieval. For example, some of the prototypes segment images, combine color, texture and shape information into composite groupings, and conduct a learning procedure from user-specified labels to one cluster per concept.
In all of these cases, the user expects that the system will locate those visual media instances that match the clue from a database. To the user, the performance of a VIR system is primarily judged by the degree to which the retrieved results correspond to the intent of the user-specified clue. However, it is very difficult to capture the intent of the user in a generic VIR system because of numerous reasons, such as:
It has been generally argued both in the database literature, e.g., S. Abad-Mota and C. A. Kulikowski, "Semantic queries on image databases: the IMTKAS model", Proc. Basque International Workshop on Info. Tech., San Sabastian, Spain, pp. 20-28, 1995, and in the information retrieval literature, e.g., W. B. Croft and R. H. Thompson, "IIIR: a new approach to the design of a document retrieval system", J. Amer. Soc. Info. Sci., vol. 38, pp. 308-404, 1987, that the retrieval performance improves if the system is knowledge-based. Knowledge here refers to a body of facts about the application domain, which is independent of media data. A VIR system is knowledge-based if some mechanism of the system utilizes this body of facts for extraction and/or retrieval of visual information. The addressed problem is: what form of knowledge is suitable for a VIR system and how to encode this knowledge into a generic VIR system in such a manner that the knowledge encoding module is flexible, customizable and can be easily changed if the user bias or application domain changes in a predictable manner. In this case, the reduction in search time as the criterion of performance as used by database researchers is not referred to, but to the quality of results as measured by precision (ratio of the number of correct results to total number of results retrieved by the system), recall (ratio of number of correct results retrieved by the system to the total number of correct results that should have been retrieved by the system) andfallout (fraction of false positives retrieved by the system) used by the Information Retrieval community. Current VIR systems (discussed further hereinbelow) until now do not have such a flexible knowledge-encoding module to improve an accepted effectiveness metric such as the well known Van Rijsbergen's formula F(X)=[(X.sup.2 +1) * P * R]/[X.sup.2 * P+R], where * indicates multiplication, P and R denote precision and recall respectively, and x is a free parameter to quantify the relative importance of precision and recall.
What is needed is a visual knowledge encoding mechanism that solves the above described problem. It would be desirable for such a mechanism to be utilized as a plug-in component in a VIR architecture.
There are three categories of work that are related to the current invention: current VIR systems, text retrieval systems, and computer vision and pattern recognition. The majority of this work relates to recently emerging technologies. These categories are described as follows:
FIG. 2 shows the general structure inside the VIR system 110. The VIR system 110 preferably includes a user interface 130, an insertion module 132, a database interface 134 and a query module 136. The user interface 130 receives user input and queries 106 (FIG. 1) by use of one or more input devices. The user interface 130 sends an image to be inserted into the DBMS 112 (FIG. 1) and metadata to the insertion module 132. Metadata is information about the image, particularly information that is useful for query purposes. Examples of metadata include the date a photographic image is created and the name of the photographer. The insertion module generates a feature vector for the image and sends the feature vector with the metadata to the database interface 134 for storage by the DBMS 112. The user interface also sends a user query to the query module 136. The query module 136 processes the query to generate a database query that is send through the database interface 134 to the DBMS 112. The database interface 134 receives results back from the DBMS 112 and sends the results to the user interface 130 through the query module 136. PA2 For the current VIR system category, there are four main types of systems: keywords only, generic image analysis, domain specific image analysis, and keywords together with image properties. These four system types are described as follows: PA2 Such a method has been used for video retrieval described by T-S. Chua and L-Q. Ruan, "A video retrieval and sequencing system", ACM Trans. Info. Syst., vol. 13(4), pp. 373-407, 1995. PA4 FIG. 3 shows a block diagram of a keyword-based image/video retrieval system 150. A query interface 152 receives keywords supplied by the user of the system 150. For this system 150, the query consists of a set of terms, i.e., keywords or phrases, which are connected together by operators, such as AND, OR, NOT and NEAR, as permitted by the underlying text database. The query is parsed by a query parser 154 to generate a query in text database format. The query is then "processed" by a text database 156, which returns the ranked list of asset identifiers (IDs) of those images that qualify the query conditions to a result processor 158. The result processor 158 then fetches the corresponding images (or their thumbnail representations) or video frames from an image repository 160 and presents the results to the user by use of a results interface 162. PA4 The problem with these keyword-only systems is that they are extremely dependent on the annotation. Hence, a user searching for "sunset" will never retrieve an image annotated with the keyword "San Francisco" even though the image may actually show a sunset in San Francisco. What is desired is to use keywords if available, but to retrieve a visual media instance if it matches the same concept as intended by the query keyword, although the instance retrieved may have different or no keywords associated with it. PA2 While these methods also attempt to capture user intent by associating features with concept, they are targeted at objectives different from the current invention. First, the mapping of one cluster to a concept is not a practical database solution to a VIR system. It is impossible to devise a clustering algorithm that will put a blue sky and a red sky of dusk in the same cluster, without misclassifying it with a lot of "non-sky" regions having smooth textures. Secondly, while the emphasis of these groups is in model building through application of suitable learning techniques for grouping features, what is desired is exemplar collection, and not model building. Although model building by learning is one way to create a victionary, the crucial point is to have a number of example cases, which would trigger a number of sufficiently diverse "expanded sub-queries" that form disjunctive descriptors of the user intent. Thirdly, the focus of this invention is in query processing in VIR systems, and on the functional requirement specification of the victionary that aids the query process, and not on any specific implementation that may yield the specifications covered herein. For the purpose of this invention therefore, the existing research ideas are potentially deployable tools, but not conceptual building blocks.
a) Systems that use keywords only: Many commercial systems associate keywords with images. The user places a search request by typing in some query words, and the system retrieves the images containing the same words. A variation of this is to use a text thesaurus. In this case, the system searches for the keywords and their synonyms. Hence a query for "car" will match an image record annotated as "automobile". PA3 b) Systems that perform generic image analysis: Many research systems, such as the projects at Columbia University, University of Chicago, University of Massachusetts and University of California-Santa Barbara, and a few commercial systems, such as the Virage VIR Engine, Excalibur Visual Retrievalware and IBM QBIC, use image processing techniques to extract some properties from the image. Among the most common properties are color, texture and shape of user-designated image regions. These abstracted properties are stored in a composite data structure called a feature vector. Applicant's VIR system for image analysis is described in copending application Ser. No. 08/829,791, filed Mar. 28, 1997, for "SIMILARITY ENGINE FOR CONTENT-BASED RETRIEVAL OF OBJECTS" to Jain, et al., which is herein incorporated by reference. PA4 FIG. 4 shows a block diagram that illustrates the structure and function of a typical VIR system 200 that performs image analysis. The database 112 (FIG. 1) stores a set of feature vectors of images that are stored therein. The user presents a query through an interface 202. The query specifies an example image, and a set of weights, which indicates the user's relative preferences of individual properties. A query parser 204 converts the user's query into an internal form (query structure) that a query processor 206 can recognize. This may involve analyzing the example image to extract its feature vector. The query processor executes the query by retrieving feature vectors from the database (using a database interface 208), comparing them against the example feature vector and creating a score sheet indicating the similarity of each retrieved image to the example image. A result processor 210 uses this score sheet and the user defined weights to compute a final ranked list. Images (or their thumbnail representations) corresponding to the ranked list are retrieved from the database interface 208 and presented to the user through the results interface 212. The VIR system 200 may include a query refinement interface 214 that sends refinement parameters based on user input to a query refinement processor 216 for modification of a query. The query refinement processor 216 may send a new query structure for refinement of the database query to the query processor 206 to produce a new set of query results and/or may send a refinement request to the result processor 210 to refine the prior set of query results. One type of query refinement is weight manipulation. PA4 Although these systems work well for query-by example cases, they are very dependent upon the properties of the example that is used as the clue. Hence, for these systems, if the query image shows a white bird flying in blue sky above some trees, the system may not ever retrieve (or rank high) an image of a bird silhouette flying against a dark red sunset over a sea, because the characteristics of these two images are very different. If the user's intent was to find a flying bird, the heavy dependence on the query example will lead to unsatisfactory performance. PA3 c) Systems that perform domain specific image analysis: Some very domain-specific systems, such as the face-recognition system of Pentland (U.S. Pat. No. 5,164,992), use prior training to enable the query engine to find similar images that are intuitively meaningful. However, these systems work only within the scope of the intended domain, are not easily extensible, and are not suitable for a database with a heterogeneous content. PA3 d) Systems using keywords and image properties: A few recent systems, such as the Photodisc system, have started using textual image descriptors together with computed image properties. These systems accept both textual query terms and an image example as input. Typically, they first issue a text query as in the keyword-only systems described above, and get back a set of image identifiers that satisfy the query. Next, they take this resulting set of images and perform an image similarity query, such as performed by the generic image analysis systems described above. These systems work very well for properly annotated databases, but suffer the same defects as the keyword-only systems and the generic image analysis systems. PA4 An interesting variant of this theme was used in the Japanese patent application to Akio Hamano (Kokai Patent Application No. HEI 2-51775 [1990]) of Nippon Telegram and Telephone Public Corporation. The Hamano patent starts with the assumption that each image shows a number of objects, and for each object, the name and spatial properties of the objects (size, position, and attitude) are stored by the system. Further, the system stores a "schematic diagram" for each image to depict the relative positions (e.g., "fore and aft relationship") of these objects. The user initiates a query by selecting an image, and inputting a keyword, such as "apple". The system retrieves a default property list for the object having the keyword. It also presents the schematic diagram data corresponding to this keyword for the current image. The user is allowed to interactively modify either the property list (e.g., make the apple bigger) and the relationships depicted in the schematic diagram (e.g., move it from the center of the desk to a corner"), through a graphical interface. When all objects pertaining to a desired image are thus modified, the system computes a "similarity criterion" from the edited image to search the database. For example, if the position of the apple was modified from p1 to p2, it creates a rectangular region around p2, to look for an apple in the database. It is important to note that the system is still looking for an apple using keyword annotations of the images in the database. The characteristic of the patent is that when it finds a candidate image in the database containing an apple by keyword search, it screens the image by comparing the similarity criteria set by the user with the schematic diagram and properties of the apple in the candidate image.