An ultrasonic sensor for measuring the level of liquid in a vessel has an elongated tubular probe, a tube within the probe, and a transducer that converts electrical energy to ultrasonic energy mounted at or near one end of the tube so as to transmit ultrasonic energy horizontally across the probe. An element having a surface that reflects ultrasonic energy is at an angle, preferably of about 45°, to the probe longitudinal axis opposite to an ultrasonic energy emitting part of the transducer to reflect ultrasonic energy received from the transducer upwardly in the probe to an air-liquid interface from which it is downwardly reflected to the angled reflector element that directs the energy reflected from the interface back to the transducer for conversion to an electrical signal that is used by an electronic module to measure the liquid level in the probe which is the liquid level in the vessel.

Ultrasonic sensors for continuously or intermittently measuring the level (height) of a liquid within a vessel are well known. The liquid can be of any type including different types of chemical and high purity liquids used in the manufacture of semiconductors. Such sensors have a transducer located close to the bottom of the vessel that transmits a beam of ultrasonic energy upwardly to the liquid surface. The sensor transducer is most often mounted at the bottom end of an elongated probe that extends within the vessel. The ultrasonic energy is transmitted from the bottom end of the probe and is reflected from the liquid surface and received back at the transducer. The round trip transit time of the beam of energy is measured and if the velocity of the ultrasonic energy in the liquid is known the vessel's liquid level can be determined.
FIG. 1 shows the construction of a typical prior art bottom-up contact type sensor of the type discussed above. There is a vessel 12 of a material that is compatible with the liquid 14 that it contains. The vessel 12 can be of any height as needed for the application that it serves and has a top wall 16 on which a header 19 of the ultrasonic sensor 20 is mounted. The mounting arrangement shown is illustrative and the sensor 20 can be suspended from the outer edge of the vessel. A probe 22 extends downward from the header 19 into the vessel. The probe 22 is most often a cylindrical tube of a material that is compatible with the liquid 14. Stainless steel is suitable probe material for many applications although probes of different types of plastic also are used. The probe 22 has a vent hole 23 near its upper end somewhat below the vessel top wall 16.
An inner tube 24 also is suspended from the header 19 and extends to or somewhat past the lower end of the probe 22. The tube 24 also can be of stainless steel or plastic. A housing 27, typically of stainless steel or plastic, is attached to the lower end of tube 24 that contains the transducer element 26. Transducer 26 usually is of a piezoelectric ceramic material such as PZT (lead-zirconate-titanate). There is a space 21 between the housing 27 and the lower end of probe 22 so that the vessel liquid 14 can enter the probe 22 and rise to the same level as the liquid in the vessel. Wires 30 extend from an electronic module 34 outside of the vessel, through the header 19 and within the tube 24 to the transducer 26. The electronic module 34, which also can be mounted on the header 19, contains the necessary conventional components and circuits to provide pulses or bursts of electrical energy to the transducer 26. The transducer converts the electrical energy into ultrasonic (electromechanical) energy and transmits this energy upwardly (vertically as shown in FIG. 1) in the probe 22 toward the header 19. The upwardly transmitted ultrasonic energy is reflected from the interface of the liquid 14 and air, or other gas, downwardly back to the transducer 26 which converts the received ultrasonic energy back into electrical energy signals that are supplied to the electronics module 34. The circuits in the electronics module 34 includes a microprocessor that controls production of periodic pulses or bursts of pulses of electrical energy by a power amplifier that are supplied to the transducer 26. The microprocessor also computes the round trip time of the transmitted and received reflected ultrasonic energy in the probe 22 and from this calculates the level of the liquid in the probe 22 which is the level of the liquid in the vessel 12. The electronics module also can have a display which reads out the level measured. The module 34 also can transmit measurement information to another device such as a control circuit that turns a supply of liquid to the vessel on and off.
While the prior art sensor 20 of FIG. 1 is operative it has several disadvantages. In a typical sensor the housing 27 requires a minimum height of ⅜″ to ½ to encapsulate the transducer 26. This means that the level of the liquid 14 in the vessel cannot be measured below the housing height. Sometimes the vessel is constructed with a well below its bottom wall into which the housing 27 can extend to eliminate the measuring problem caused by the housing height. But this adds expense in the construction of the vessel and can make its mounting more difficult. Also if liquid stays on the top portion of housing 27 which encapsulate the transducer 26 this may provide a false indication. Another disadvantage is that a characteristic of PZT material is such that it "rings" when an energy pulse or burst of pulses is applied to it. The ringing time is as long as 30/40 microseconds. Because of the ringing, as the transducer transmits energy in a direction vertically upward along the probe longitudinal axis a "dead zone", shown by the lines D-D, occurs between the upper end of the transducer housing 27 and a point within the probe 22. The duration of the transducer ringing does not allow level measurement in the "dead zone", which can of a height as large as ¾″ to 1″.
Because of the problems described above the prior art sensor 20 is unable to measure the liquid level to the bottom of the vessel. Accordingly, it would be desirable to provide a sensor that can overcome the disadvantages of the prior art bottom up type sensors so that a more accurate measurement of liquid closer to the bottom of the vessel can be made.

Bottom up contact type ultrasonic continuous level sensor


A mechanical-shock-mount assembly enables attachment of a mechanical-shock-sensitive electronic device to a support structure. Two identical shock-mount structures are attached and located on opposite sides of an electronic device. Each shock-mount structure has a pair of generally planar spring-like cantilever beams that have their free ends for attachment to the support structure. Damping material is located on the surfaces of the cantilever beams between the beams and clamping surfaces. At least one clamping surface is a plate that compresses the damping material between itself and the beam and/or compresses the damping material between the beam and a surface of the support structure when it is attached to the support structure. This shock-mount structure acts as a highly-damped nonlinear spring system that provides mechanical-shock resistance for the device in a direction perpendicular to the cantilevered beams and high stiffness in a direction in the plane of the beams. If desired, the shock-mounts can be first assembled to the support structure before attaching the device. The support structure can optionally have additional features for attaching other components of the device host.

1. Field of the Invention
This invention relates generally to mechanical-shock-mounts or shock absorbers for attachment of mechanical-shock-sensitive electronic devices to support structures.
2. Description of the Related Art
Many types of electronic devices, such as disk drives, including optical disk drives and magnetic recording hard disk drives (HDDs), are sensitive to mechanical shock, i.e., sudden acceleration or deceleration. Disk drives are especially sensitive to shock in a direction perpendicular or normal to the disks. Mechanical-shock-sensitive electronic devices are finding wide use in portable host systems, such as notebook computers, personal digital assistants (PDAs), cell phones, and MP3 music players, all of which experience mechanical shock in ordinary use.
What is needed is a shock-mount assembly for attachment of a mechanical-shock-sensitive electronic device to a support structure, wherein the support structure can be part of the host system or an independent structure that can in turn be attached to the host system.

Shock mount assembly for attachment of an electronic device to a support structure

Hitachi Global Storage Technologies Netherlands B.V.


A circuit configuration for reducing an injection of minority carriers into a substrate protects against malfunction due to injected minority carriers by providing a series circuit connected to an external terminal. The series circuit has a transistor and a diode disposed between a supply potential and the external terminal and fed back through a control loop from the external terminal to a control terminal of the transistor.

FIELD OF THE INVENTION
The invention relates to a circuit configuration for reducing injection of minority carriers into a substrate containing regions forming a pn junction, including a transistor connected to an external terminal of the circuit configuration.
Integrated semiconductor circuits contain a substrate, in which respective p-doped and n-doped regions are embedded with a predetermined structure. For example, n-doped wells which receive electrical components may be disposed on a p-type substrate. The pn junction with the substrate must always be reverse-biased so that no minority carriers are injected into the substrate. Such minority carriers spread by diffusion and, if they reach other circuit elements, cause malfunctions because of their parasitic properties. For that reason, on one hand the substrate is typically connected to the lowest potential of the circuit. On the other hand it is known that external connections to the integrated circuit entail problems with the circuit. The external terminals of the circuit, in particular the inputs and outputs of the circuit, therefore constitute particularly critical points.
If the current flowing through them is interrupted suddenly, loads which have an inductive component can produce a back-emf. Other problems are also possible, for example resulting from changes in the supply voltage. The effects result in a minority carrier current being injected into the substrate and being on the order of magnitude of the working current through a transistor. The back of the chip and the wells over the substrate act as sinks for the charge carriers. The motion of the minority carriers due to the concentration gradient causes so-called transverse currents. Only a fraction of the minority carriers combines in the substrate, since the crystalline quality of the substrate is generally so good that only low recombination rates, that is to say long carrier lifetimes, occur. The component wells of the circuit must therefore take up large transverse currents, which leads to undesired activation of parasitic bipolar transistors and therefore to malfunctions.
Published European Patent Application 0 284 979 A1 discloses a substrate which in each case is connected through a diode to the external terminal, or to a reference terminal for connection to a reference potential. In addition, German Published, Non-prosecuted Patent Application DE 44 11 869 A1, corresponding to allowed U.S. application Ser. No. 08/417,825, filed Apr. 6, 1995, discloses that a heavily doped substrate having an overlying weakly doped layer of the same conductivity is used, and that the wells are surrounded by a protective ring. Although that measure does not actually impede the injection of minority carriers, it greatly restricts the spreading of the charge carriers. Furthermore, a measure of that type is only of very limited effect in typical bipolar technologies, since substrates having epitaxial layers as in MOS technologies are not used.
Published European Patent Application 0 409 158 A1, corresponding to U.S. Pat. No. 3,058,428, discloses a circuit configuration for reducing injection of minority carriers into a substrate, in which a control loop, including a comparator and a transistor, is formed in conjunction with a working circuit.

Circuit configuration for reducing injection of minority carriers into a substrate


In a vector processing device, a data dependence detecting unit detects a data dependence relation between a preceding instruction and a succeeding instruction which are inputted from an instruction buffer, and an instruction issuance control unit controls issuance of an instruction based on a detection result thereof. When there is a data dependence relation between the preceding instruction and the succeeding instruction, the instruction issuance control unit generates a new instruction equivalent to processing related to a vector register including the data dependence relation with the succeeding instruction in processing executed by the preceding instruction and issues the new instruction between the preceding instruction and the succeeding instruction, and thereby a data hazard can be avoided between the preceding instruction and the succeeding instruction without making a stall occur.

A vector processing device (vector processor) performs calculation processing or the like in a pipelined manner according to an instruction on array-type data stored in a vector register file. The vector processing device has a plurality of execution pipelines as illustrated in FIG. 18, and the execution pipelines process the array data respectively.
FIG. 18 is a block diagram illustrating a structural example of the vector processing device. In FIG. 18, IF denotes an instruction fetch stage, ID denotes an instruction decoding stage, and EX denotes a calculation execution stage. The vector processing device has an instruction buffer 101, a data dependence detecting unit 102, an instruction issuance control unit 103, execution pipelines 104, a vector register file 105, and a multiplexer circuit 106. FIG. 18 illustrates a vector processing device having four execution pipelines 104, which are pipelines A, B, C, and D.
The instruction buffer 101 stores an instruction (vector instruction) read from a storage device. The data dependence detecting unit 102 determines whether or not a vector register specified by a preceding instruction which is executed precedingly overlaps with a vector register specified by a succeeding instruction which succeeds the preceding instruction, so as to detect a data dependence relation between the preceding instruction and the succeeding instruction. The instruction issuance control unit 103 issues an instruction to an execution pipeline 104 upon reception of an instruction stored in the instruction buffer 101 and a detection result in the data dependence detecting unit 102. The instruction issuance control unit 103 requests a next instruction from the instruction buffer 101 when there is a vacancy in the execution pipelines 104, determines which execution pipeline 104 an instruction is to be issued to according to the data dependence relation and vacant states of the execution pipelines 104, and issues the instruction.
The execution pipelines 104 execute processing on array data by complying with the instruction received from the instruction issuance control unit 103. Each of the execution pipelines 104 has a sequencer 107 and a calculating unit 108. The sequencer 107 performs control related to execution of the instruction received from the instruction issuance control unit 103. For example, the sequencer 107 instructs instruction execution or instructs execution of reading or writing of data from or to the vector register file 105. The calculating unit 108 has a plurality of calculators 109 and executes processing according to an instruction from the sequencer 107. Here, in this specification, for convenience of explanation, it is assumed that the calculating unit 108 has eight 16-bit calculators 109, and 32-bit data are processed using two calculators.
The vector register file 105 stores array data. The array data stored in the vector register file 105 are supplied to the execution pipelines 104 via the multiplexer circuit 106. Note that although not being written in the vector register file 105 yet, it is possible to supply array data generated already as a calculation result to the execution pipelines 104 via the multiplexer circuit 106.
The size of the array data, that is, the number of array elements are specified by a vector length (VL). The array elements whose number is specified by the vector length (VL) forms one array register, and one logical vector register number corresponds to one array register. The size of each array element is assigned according to a data word length handled by the vector processing device. A head value of the physical vector register number corresponding to the logical vector register number is a power of two. When the vector length (VL) is a power of two, a value obtained by multiplying the vector length (VL) by a logical vector register number is the start value of the physical vector register number corresponding to this logical vector register number. Further, when the vector length (VL) is not a power of two, a value obtained by multiplying the smallest value among powers of two equal to or larger than the vector length (VL) by a logical vector register number is the start value of the physical vector register number corresponding to this logical vector register number.
In the following description, using i, j as indexes, vri represents the register of a logical vector register number i, and vr[j] represents the register of a physical vector register number j. When the data word length handled by the vector processing device is Halfword (16 bits), one of registers vr[j] corresponds to one array element, and when the data word length is Word (32 bits), a pair of registers vr[j] corresponds to one array element.
For example, the correspondence of the logical vector register number and the physical vector register number of the vector register when the vector length (VL) is 32, which is a power of two, and the order of processing when calculation processing is executed are as illustrated in FIGS. 19A and 19B. Further, for example, the correspondence of the logical vector register number and the physical vector register number of the vector register when the vector length (VL) is 40, which is a power of two, and the order of processing when calculation processing is executed are as illustrated in FIGS. 20A and 20B.
As illustrated in FIG. 19A, when the data word length is Halfword, a vector register vr[32×i] to vr[32×i+31] with a physical number (32×i) to (32×i+31) corresponds to a vector register vri with a logical number i. Then, for example, when a vector register vr0 with a logical number 0 is specified by a Halfword calculation instruction, vector registers vr[0] to vr[7] with physical numbers 0 to 7 are targets of processing in a first cycle, and vector registers vr[8] to vr[15] with physical numbers 8 to 15 are targets of processing in a second cycle. Further, vector registers vr[16] to vr[23] with physical numbers 16 to 23 are targets of processing in a third cycle, and vector registers vr[24] to vr[31] with physical numbers 24 to 31 are targets of processing in a fourth cycle.
Further, as illustrated in FIG. 19B, when the data word length is Word, a vector register vr[32×i] to vr[32×i+63] with a physical number (32×i) to (32×i+63) corresponds to the vector register vri with the logical number i. Then, for example, when the vector register vr0 with the logical number 0 is specified by a Word calculation instruction, the vector registers vr[0] to vr[7] with the physical numbers 0 to 7 are targets of processing in the first cycle, and the vector registers vr[8] to vr[15] with the physical numbers 8 to 15 are targets of processing in the second cycle. The vector registers vr[16] to vr[23] with the physical numbers 16 to 23 are targets of processing in the third cycle, the vector registers vr[24] to vr[31] with the physical numbers 24 to 31 are targets of processing in the fourth cycle, and vector registers vr[32] to vr[39] with physical numbers 32 to 39 are targets of processing in a fifth cycle. Further, vector registers vr[40] to vr[47] with physical numbers 40 to 47 are targets of processing in a sixth cycle, and vector registers vr[48] to vr[55] with physical numbers 48 to 55 are targets of processing in a seventh cycle, and vector registers vr[56] to vr[63] with physical numbers 56 to 63 are targets of processing in an eighth cycle.
As illustrated in FIG. 20A, when the data word length is Halfword, a vector register vr[64×i] to vr[64×i+39] with a physical number (64×i) to (64×i+39) corresponds to the vector register vri with the logical number i. Then, for example, when the vector register vr0 with the logical number 0 is specified by the Halfword calculation instruction, registers to be targets of processing in the first cycle to the fourth cycle are the same as those when the vector length (VL) is 32. Moreover, the vector registers vr[32] to vr[39] with the physical numbers 32 to 39 are targets of processing in the fifth cycle.
Further, as illustrated in FIG. 20B, when the data word length is Word, a vector register vr[64×i] to vr[64×i+79] with a physical number (64×i) to (64×i+79) corresponds to the vector register vri with the logical number i. Then, for example, when the vector register vr0 with the logical number 0 is specified by the Word calculation instruction, registers to be targets of processing in the first cycle to the eighth cycle are the same as those when the vector length (VL) is 32. Moreover, vector registers vr[64] to vr[71] with physical numbers 64 to 71 are targets of processing in a ninth cycle, and vector registers vr[72] to vr[79] with physical numbers 72 to 79 are targets of processing in a tenth cycle.
Upon reception of an instruction "INS A, B, C", the vector processing device illustrated in FIG. 18 performs calculation processing corresponding to the instruction INS using corresponding data in a vector register with a logical vector register number A and a vector register with a logical vector register number B, and stores a calculation result in a vector register with a logical vector register number C.
For example, when a Halfword calculation instruction "vaddh vr1, vr6, vr7" is issued to a certain execution pipeline 104. The instruction "vaddh vr1, vr6, vr7" causes a result of adding data in the vector register vr1 with the logical number 1 and the vector register vr6 with the logical number 6 to be stored in the vector register vr7 with the logical number 7. The execution pipeline 104 which has received this instruction executes the following calculation processing in the first cycle.
            vr                    [        224        ]              =                  vr                          [          32          ]                    +              vr                          [          192          ]                                vr                    [        225        ]              =                  vr                          [          33          ]                    +              vr                          [          193          ]                      …            vr                    [        231        ]              =                  vr                          [          39          ]                    +              vr                          [          199          ]
Thereafter, when the vector length (VL) is 32, calculation processing is performed while changing the vector registers which are targets of processing in each cycle until the fourth cycle, and when the vector length (VL) is 40, calculation processing is performed while changing the vector registers which are targets of processing in each cycle until the fifth cycle.
Further, for example, when a Word calculation instruction "vadd vr2, vr4, vr0" is issued to a certain execution pipeline 104. The instruction "vadd vr2, vr4, vr0" causes a result of adding data in the vector register vr2 with the logical number 2 and the vector register vr4 with the logical number 4 to be stored in the vector register vr0 with the logical number 0. The execution pipeline 104 which has received this instruction executes the following calculation processing in the first cycle.vr[1−0]=vr[65−64]+vr[129−128]vr[3−2]=vr[67−66]+vr[131−130]vr[5−4]=vr[69−68]+vr[133−132]vr[7−6]=vr[71−70]+vr[135−134]
Thereafter, when the vector length (VL) is 32, calculation processing is performed while changing the vector registers which are targets of processing in each cycle until the eighth cycle, and when the vector length (VL) is 40, calculation processing is performed while changing the vector registers which are targets of processing in each cycle until a tenth cycle.
Thus, in the vector processing device, one instruction is executed across plural cycles in one execution pipeline. The execution pipeline is occupied across the plural cycles until processing is completed regarding the one instruction. Further, the respective execution pipelines included in the vector processing device are operable in parallel. Therefore, when the register specified by a preceding instruction overlaps with the register specified by a succeeding instruction, issuance timings of the instructions with each other is adjusted so that access to the overlapping register is performed properly and is reflected on the respective processing of the preceding instruction and the succeeding instruction. For this purpose, the vector processing device determines presence of the data dependence relation between the preceding instruction and the succeeding instruction when issuing the instructions.
Hazards related to the data dependence relation (data hazards) include a RAW (read after write) hazard and a WAR (write after read) hazard. The RAW hazard is a hazard such that after writing to a vector register is performed by the preceding instruction, in processing performed by the succeeding instruction using the vector register in which writing is performed by the preceding instruction, reading by the succeeding instruction is performed before the writing by the preceding instruction. Further, the WAR hazard is a hazard such that after reading from a vector register is performed by the preceding instruction, in processing performed by the succeeding instruction to write in the same vector register, writing by the succeeding instruction is performed before the reading by the preceding instruction.
When the data dependence relation is detected between the preceding instruction and the succeeding instruction, the vector processing device performs control to delay issuance of the succeeding instruction for a certain cycle until processing by the preceding instruction is performed, thereby avoiding the data hazard by a stall. FIGS. 21A and 21B are diagrams illustrating an operation example of avoiding the data hazard. Note that the vector length (VL) in the example illustrated in FIGS. 21A and 21B is 32.
FIG. 21A illustrates an example of an issuance timing of instruction related to avoidance of the RAW hazard. FIG. 21A illustrates an example in which "vadd vr2, vr4, vr0" is issued as the preceding instruction to a pipeline A, and as the succeeding instruction thereafter, "vaddh vr1, vr6, vr7" is issued to a pipeline B. The instruction "vadd vr2, vr4, vr0" is a Word calculation instruction for storing a result of adding data in the vector register vr2 with the logical number 2 and the vector register vr4 with the logical number 4 in the vector register vr0 with the logical number 0. Further, the instruction "vaddh vr1, vr6, vr7" is a Halfword calculation instruction for storing a result of adding data in the vector register vr1 with the logical number 1 and the vector register vr6 with the logical number 6 in the vector register vr7 with the logical number 7. In FIG. 21A, for the instruction "vadd vr2, vr4, vr0", the physical number (head value) of the vector register vr0 with the logical number 0 which is a destination register in which the calculation result is written is illustrated in every cycle. Further, for the instruction "vaddh vr1, vr6, vr7", the physical number (head value) of the vector register vr1 with the logical number 1 which is a source register from which data used in the calculation operation is read is illustrated in every cycle.
In processing by the preceding instruction "vadd vr2, vr4, vr0" and processing by the succeeding instruction "vaddh vr1, vr6, vr7", the vector registers vr[32] to vr[63] with the physical numbers 32 to 63 overlap. For example, in the vector registers vr[32] to vr[39] with the physical numbers 32 to 39, reading of data is performed in the beginning cycle in processing of the succeeding instruction "vaddh vr1, vr6, vr7", but writing of data is performed in the fifth cycle in processing of the preceding instruction "vadd vr2, vr4, vr0". In order to reflect a processing result of the preceding instruction on processing of the succeeding instruction, reading of data from the vector registers vr[32] to vr[39] with the physical numbers 32 to 39 by the succeeding instruction "vaddh vr1, vr6, vr7" needs to be performed after the cycle 5. Accordingly, in the cycle 2 to cycle 5, a stall due to the RAW hazard is made to occur, and the succeeding instruction "vaddh vr1, vr6, vr7" is issued in the cycle 6.
FIG. 21B illustrates an example of an issuance timing of instruction related to avoidance of the WAR hazard. FIG. 21B illustrates an example in which "vadd vr0, vr4, vr2" is issued as the preceding instruction to the pipeline A, and as the succeeding instruction thereafter, "vaddh vr6, vr7, vr1" is issued to the pipeline B. The instruction "vadd vr0, vr4, vr2" is a Word calculation instruction for storing a result of adding data in the vector register vr0 with the logical number 0 and the vector register vr4 with the logical number 4 in the vector register vr2 with the logical number 2. Further, the instruction "vaddh vr6, vr7, vr1" is a Halfword calculation instruction for storing a result of adding data in the vector register vr6 with the logical number 6 and the vector register vr7 with the logical number 7 in the vector register vr1 with the logical number 1. In FIG. 21B, for the instruction "vadd vr0, vr4, vr2", the physical number (head value) of the vector register vr0 with the logical number 0 which is a source register from which data used in the calculation operation is read is illustrated in every cycle. Further, for the instruction "vaddh vr6, vr7, vr1", the physical number (head value) of the vector register vr1 with the logical number 1 which is a destination register in which the calculation result is written is illustrated in every cycle.
In processing by the preceding instruction "vadd vr0, vr4, vr2" and processing by the succeeding instruction "vaddh vr6, vr7, vr1", the vector registers vr[32] to vr[63] with the physical numbers 32 to 63 overlap. For example, in the vector registers vr[32] to vr[39] with the physical numbers 32 to 39, writing of data is performed in the beginning cycle in processing of the succeeding instruction "vaddh vr6, vr7, vr1", but reading of data is performed in the fifth cycle in processing of the preceding instruction "vadd vr0, vr4, vr2". In order to perform processing of the preceding instruction before a processing result of the succeeding instruction is written, writing of data in the vector registers vr[32] to vr[39] with the physical numbers 32 to 39 by the succeeding instruction "vaddh vr6, vr7, vr1" may be performed after the cycle 5. Accordingly, in the cycle 2 to cycle 5, a stall due to the WAR hazard is made to occur, and the succeeding instruction "vaddh vr6, vr7, vr1" is issued in the cycle 6.
Further, in Patent Document 1 below, there is proposed a technique such that, when there is register interference (the data dependence relation exists between the preceding instruction and the succeeding instruction) and the preceding instruction needs a longer processing time than the succeeding instruction, the starting time of the succeeding instruction is set to eliminate the necessity to wait until execution of the preceding instruction is completed, so as to improve processing performance.    [Patent Document 1] Japanese Laid-open Patent Publication No. 60-178580
However, in the vector processing device, due to handling of array-type data, there is a problem that the stall period becomes long when the stall due to the data hazard is made to occur. For example, there is a problem that when a vector register storing a processing result from the middle of processing of the preceding Word instruction is used by the succeeding Halfword instruction, the succeeding instruction is stalled for a long period until writing by the preceding instruction in the vector register used in the succeeding instruction is completed.

Instruction control circuit, processor, and instruction control method


The present invention relates to a photosensitive resin composition excellent in pliability, ultraviolet sensitivity for development, developability with an aqueous alkali solution, and storage stability at room temperature and a circuit substrate employing the same. The photosensitive resin composition includes a siloxane-containing polyamic acid resin having structural units respectively represented by the following formulae (1), (2), and (3) and a photopolymerization initiator incorporated therein. The circuit substrate is coated with the photosensitive resin composition.

In recent years, ULTRAVIOLET-curable photosensitive resin compositions have been abundantly used in a wide variety of fields, such as coating materials, adhesives, and resists, because of various reasons including high productivity, low-pollution, and energy-saving properties. In the field of processing printed wiring boards, cover materials for various ink systems, such as solder resist ink, are being replaced from the conventional screen-printing system to ULTRAVIOLET-curable compositions. In addition, remarkable progresses in electron technologies allow the conventional rigid substrates to be substituted by flexible substrates because of advancing high-density and weight-saving technologies.
In general, in the case of using ink as a covering material, as the characteristics of the covering material after curing, the covering material used for a rigid substrate does not need pliability so much, but in the case of using a covering material for a flexible substrate, the cover material has been desired to be high in pliability in order to employ the characteristic features of the flexible substrate.
Further, JP 07-207211 A describes a curable photosensitive material including an epoxy resin, an unsaturated group-containing polycarboxylic acid resin provided as a reaction product of an unsaturated group-containing monocarboxylic acid and an carboxylic acid anhydride, and a photopolymerization-initiator. However, such a material has poor folding-endurance characteristics because of a lack in sufficient flexibility or pliability. Besides, a trouble such as the substrate warps after processing occurs. An improvement in such a trouble has been demanded in various fields. For this reason, as shown in JP 2004-294882 A, a composition containing a siloxane polyimide as a main component for expressing low elasticity has been proposed. In those compositions, warping of a substrate after processing may be decreased, but the compositions may cause problems of high price and poor storage stability of the composition at room temperature.    Patent Document 1: JP 07-207211 A    Patent Document 2: JP 2004-294882 A

Photosensitive resin composition and circuit substrate employing the same

Abstract: In the formulae, Ar represents a residue of an aromatic tetracarboxylic acid; R1 represents alkyl group having 1 to 6 carbon atoms or phenyl group; R2 represents alkylene group having 2 to 6 carbon atoms or phenylene group; l represents a number of 0 to 10; R3 represents a divalent group or a direct bond; R4 represents —CH2═CH—R6—, in which R6 represents a direct bond, alkylene group having 1 to 6 carbon atoms, or phenylene group; R5 represents a diamine residue; and m, n, and o, indicating the range of the abundant molar ratios of the respective structural units, are 0.3 to 0.95, 0.05 to 0.7, and 0 to 0.5, respectively.


An exhaust gas purifying apparatus includes a primary diesel particulate filter provided in an exhaust line of a diesel engine, a secondary exhaust line branched from the exhaust line at an upstream side of the primary diesel particulate filter, a secondary diesel particulate filter provided in the secondary exhaust line, and a low pressure part provided in the secondary exhaust line at a downstream side of said secondary diesel particulate filter. The secondary diesel particulate filter has a soot load capacity smaller than the soot load capacity of the primary diesel particulate filter. The low pressure part provides a pressure lower than a pressure of the branching point. The apparatus further includes a differential pressure measuring part for measuring a differential pressure between an inlet and an outlet of the secondary diesel particulate filter.

1. Field of the Invention
The present invention relates to exhaust gas purifying apparatuses.
2. Discussion of the Background
Conventionally, a diesel particulate filter (DPF) of porous ceramic has been used for collecting particulate matter (PM) primarily of C (carbon) emitted from a diesel engine. With such a diesel particulate filter, there occurs gradual deposition of particulate matter with continual use thereof, and thus, it has been practiced in the art of exhaust gas purifying apparatus that uses a diesel particulate filter to remove the deposited particulate matter by causing a burning process inside the diesel particulate filter periodically and regenerate the diesel particulate filter.
It is preferable that such regeneration of the diesel particulate filter is conducted during the operation of the diesel engine, without replacing or dismounting the filter, and thus, it is practiced in the art to carry out fuel injection in the state that the piston is moving down in the cylinder following combustion to form a high temperature gas (post injection process). Thereby, the deposited particulate matter is burned with the high temperature gas thus formed.
FIG. 1 shows the overall construction of a conventional exhaust gas purifying system of a diesel engine equipped with a diesel particulate filter according to a related art of the present invention.
With the conventional exhaust gas purifying system explained with reference to FIG. 1, it should be noted that such regeneration of filter is conducted each time the vehicle has traveled a predetermined mileage such as 500 km, over the duration of 10 minutes, for example.
In the case the filter regeneration by way of post injection has been conducted impartially, the regeneration is carried out irrespective of actual amount of collection of the particulate matter in the filter. Thus, in order to ensure that there occurs no excessive deposition of the particulate matter in the filter, there is a need to set the interval of filter regeneration to be shorter than what is actually needed for the sake of safety.
On the other hand, there is a known construction of carrying out regeneration of the diesel particulate filter 12B by way of posit injection as shown in FIG. 3, in which a differential pressure ΔP is measured between the upstream side and downstream side of the diesel particulate filter 12B and the posit injection is carried out when the foregoing differential pressure ΔP has reached a predetermined value. Reference should be made to the U.S. Pat. No. 6,952,920.
Further, U.S. Pat. No. 5,651,248 describes the construction that uses, in addition to the diesel particulate filter, a detection filter and evaluates the amount of the particulate matter collected in the detection filter by measuring the electric resistance. According to this technology, the particulate matter collected by the diesel particulate filter and the particulate matter collected by the detection filter are subjected to burning by using a heater when the detected resistance has decreased below a predetermined value. With this, regeneration of filter is achieved.
As shown in FIGS. 5A, 5B, and 5C, there can be a situation in which the thickness of the collected particulate matter changes in spite of the fact that the deposition amount thereof is the same. Now, when the thickness of the collected particulate matter is different, it becomes difficult to measure the electrical resistance precisely, and there tends to be caused error in the evaluation of the deposition amount.
Further, in the case there is caused a deposition of ash in the diesel particulate filter or detection filter after burning of the particulate matter, no precise measurement of electrical resistance is possible anymore and there tends to be caused a large error in the evaluation of the deposition amount.
Further, with the use of the detection filter, there is caused degradation in the filter or electrode with time or with use in the ambient of exhaust gas. Particularly, the electrode (terminal formed of a conductive metal) is formed by infiltrating a metal such as Cu, Cr, Ni, or the like, and thus, there is a tendency of causing problems of physical degradation, oxidation degradation and thermal degradation, such as oxidation, adhesion of impurities, cracking, corrosion, and the like.
When there is caused degradation in the filter or electrode, it is no longer possible to carry out precise measurement of the electric resistance and error is tend to be caused in the evaluation of the deposition amount of the particulate matter.
The contents of U.S. Pat. Nos. 6,952,920 and 5,651,248 are incorporated herein by reference in their entirety.


A nonvolatile semiconductor memory device includes a plurality of memory cell units and a memory cell array in which the memory cell units are arranged in matrix. Each of the memory cell units has a given number of electrically writable and erasable memory cell transistors that are connected in a column direction to form a memory cell column. One end of the memory cell column is connected to a bit line via a first select gate transistor, and the other end thereof is connected to a source line via a second select gate transistor. At least part of a gate electrode of one of the first and second select gate transistors is provided in a trench formed in the surface area of a substrate along a direction parallel to a word line.

1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device. More specifically, the invention relates to a nonvolatile semiconductor memory device including memory cell units each having a given number of memory cell transistors arranged in series in a column direction, such as a NAND flash memory (EEPROM: electrically erasable and programmable read only memory).
2. Description of the Related Art
As is known, a nonvolatile semiconductor memory device such as a NAND flash memory is useful in allowing data to be rewritten (written and erased) electrically though it is nonvolatile. Further, the memory device can increase in packing density and is decreasing in area (a transistor is decreasing in size) year by year.
Under the above circumstances, a nonvolatile semiconductor memory device has been proposed which is capable of greatly decreasing the size of a memory cell transistor whose gate electrode has a trench structure (refer to Jpn. Pat. Appln. KOKAI Publication No. 2001-274366, for example). In the proposed device, a memory cell transistor having a channel component in a vertical direction is formed to take measures against short-channel effects (SCE) due to the scaling of gate length.
However, the above prior art nonvolatile semiconductor memory device has the drawback that the scaling of gate length of a select gate transistor is more difficult than that of gate length of a memory cell transistor. The reason is as follows. A channel voltage that is cut off by a select gate transistor in write inhibit (or unwrite or unselect) mode does not drop due to the scaling. In other words, a boosted channel voltage cannot be cut off sufficiently if the gate length of a select gate transistor is decreased by scaling. The nonscaling of the select gate transistor is becoming a limiting factor in reducing the device in area.
In the future, the gate length of a select gate transistor needs to be decreased by scaling to meet a demand that a device should be reduced in area. A search for the best way to do so is being carried out.

Nonvolatile semiconductor memory device including memory cell units each having a given number of memory cell transistors


A piezoelectric element of a tuning fork resonator comprises a base portion and a plurality of leg portions. Drive electrodes are formed on top and bottom major surfaces and both side surfaces of each leg portion. The drive electrodes have polarities different between on the top and bottom major surfaces and the both side surfaces. The drive electrodes on the side surfaces are connected to each other. Further, metal film for frequency adjustment is formed on a tip portion of each leg portion of the piezoelectric element. The frequency adjustment is performed by removing the metal film formed on at least one surface of side surfaces and a tip surface of the tip portion by beam irradiation.

A production process of a tuning fork resonator (hereinafter referred to as a resonator) includes a step of adjusting an oscillation frequency. As a conventional resonator frequency adjusting method for this step, a method for adjusting the frequency of a resonator is disclosed in, for example, JP 2002-164759A.
A resonator disclosed in JP 2002-164759A is provided with a piezoelectric element (hereinafter referred to as an element) there within. The element includes a base portion and two leg portions. In addition, a metal film is provided on the top and bottom major surfaces of the two leg portions so as to adjust frequency.
In the resonator frequency adjusting method of JP2002-164759A, an oscillation frequency is adjusted by removing a portion of the top and bottom major surfaces of the metal film, which is provided as a weight for adjusting frequency on the top and bottom major surfaces of the leg portions of the element, by laser irradiation. Specifically, the metal film is irradiated with a laser to remove a portion of the metal film, thereby increasing the oscillation frequency of the resonator. The resultant oscillation frequency is measured. Laser irradiation and frequency measurement are repeatedly performed until the measured frequency value of the resonator reaches a target value. More specifically, when a YAG laser or the like is used, a portion of a metal film having a diameter of about 20 μm is removed by laser irradiation of a point on the metal film, resulting in a removal region (hereinafter referred to as a removal dot). Thus, the oscillation frequency of the resonator is increased by 2 to 3 ppm. Thus, each laser irradiation increases the oscillation frequency of the resonator by 2 to 3 ppm. The oscillation frequency is measured after each laser irradiation. When the measured frequency reaches a target value, the frequency adjustment procedure is ended.
In the above-described frequency adjusting method, the metal film on the top and bottom major surfaces of the leg portion is irradiated with a laser in a direction perpendicular thereto. Therefore, a plurality of removal dots are formed when rough adjustment is performed. Particularly when there is a relatively large difference between the oscillation frequency before adjustment and a target frequency, a large number of removal dots need to be formed. Unfortunately, in the above-described frequency adjusting method, the frequency adjustment procedure for the metal film on a limited region of the top and bottom major surfaces of the leg portion becomes unstable or the production efficiency of the resonator is decreased, in proportion to an increase in the number of removal dots.
Also, recently, there has been a demand for further miniaturization of resonators. In association with this, a smaller element is desired to be provided in a resonator. As the size of an element is reduced, the region of metal film for adjustment is also decreased. Therefore, it is difficult to use conventional resonator frequency adjusting methods to provide a large metal film frequency adjustment amount (rough adjustment) in a limited region of metal film for adjustment.
The present invention is provided to solve the above-described problems. It is an object of the present invention to stabilize the frequency adjustment procedure of the method for adjusting an oscillation frequency of a resonator by removing a portion of a metal film formed on the surface of an element, even if it is small, by beam irradiation, and to improve the production efficiency of the resonator.

Frequency regulating method for tuning fork type vibrator and tuning fork type vibrator frequency-regulated by the method


An airbag apparatus comprising an airbag module installed in a backrest of a vehicle seat is provided. The backrest has a side support on each side. Each side support has a base portion located at a position closer to a center of the backrest. The airbag module is installed in a side portion of the back rest that faces the exterior of the vehicle. The airbag module includes a gas generator that generates gas in response to impact from a side of the vehicle, and first and second airbag portions that are inflated and deployed by the gas generated by the gas generator. The airbag module is installed in the backrest in such a manner that, when the airbag is inflated and deployed, the first airbag portion pushes the base portion of the side support on the exterior side obliquely forward and further into the passenger compartment.

The present invention relates to an airbag apparatus for reducing impacts from a side of a vehicle.
Japanese Laid-Open Patent Publication Nos. 10-24793, 10-80590, and 10-81187 each disclose an airbag apparatus that protect an occupant of a vehicle when the impact is applied from a side of the vehicle. An airbag module of such an airbag apparatus is provided in an exterior side of a backrest of a vehicle seat. The airbag module includes an inflator, which generates gas in response to impact, and an airbag, which is inflated and deployed by the gas discharged from the inflator.
When impact is applied from a body side portion of a vehicle toward the passenger compartment, the inflator of the above airbag apparatus supplies gas into the airbag, so that the airbag is inflated and deployed forward with respect to the backrest. Since the airbag that has been inflated and deployed is located between the occupant and the body side portion that bulges into the passenger compartment, the impact applied to the occupant from the side via the body side portion is reduced.
It is predicted that, in the above shown airbag apparatus, the occupant protecting performance will be improved if the occupant is moved inward away from the body side portion before the body side portion bulges into the passenger compartment. In the above described airbag apparatus, although the inflated and deployed airbag can push the occupant further into the passenger compartment, the timing at which the airbag pushes the occupant is after the airbag breaks out of the backrest and is deployed to a certain degree. Thus, this type of airbag is still susceptible to improvement in terms of the occupant protecting performance.


A swinging toy for swinging a doll includes a sound producing unit comprising of a platter, a record, a tone arm assembly. The sound producing unit is a buzzer and driven by a motor drive to produce sounds. A clock may be provided which is controlled by a control unit to turn on the motor drive once per hour. And an actuator comprising a chuck carried on a revolving rod connected to a crank through a link and driven by the platter of the sound producing unit through a transmission gear to swing the doll as the sound producing unit produces sounds is also provided.

The present invention relates to a clock controlled swinging toy which is hourly controlled by a clock to swing and to produce sounds while swinging.
A variety of sound producing toys are known and widely accepted by children for the advantage of sound producing capability. For making a sound producing toy, an electronic sound producing system or a mechanical sound producing system may be used. An electronic sound producing system is generally comprised of a music IC controlled by a control circuit to produce sounds through a speaker. A mechanical sound producing system is generally comprised of a tone arm assembly moved along grooves on a record carried by a platter to produce sounds through a buzzer or speaker. In order to drive a sound producing toy to swing, an actuator is used. When an actuator is used in sound producing toy, two separate driving units are required for driving the actuator and the sound producing system. When two separate driving units are used, the structure of a toy becomes complicated.

Clock controlled swinging toy with sound producing means

2nd Fl., 6-1, Sublane 1, Lane 437 Pateh Road, Sec. 2


An apparatus and method for controlling the temperature profile of the surface of a medium such as a solid or a liquid. The surface is imaged onto an array of detectors which generate an electronic output indicative of the temperature profile of the surface. A heating beam provided by a laser is scanned across the surface, providing radiation which heats the surface locally in a pattern based upon the detected temperature profile and the desired temperature profile.

Modem semiconductor processing involves the precision growth of oxide layers across wafers of semiconductor material having diameters as large as 30 cm. During the growth of oxide layers, the entire wafer, or often a large number of wafers, is maintained at a regulated temperature within a furnace. Similarly, the composition of gases within the furnace is controlled. Standard procedure is either to maintain a nearly uniform temperature profile over the region of the furnace containing the wafer or wafers undergoing processing or to provide zonal radiative heating of the wafer. In some cases, the control of temperature may be critical for achieving chemical reaction at the requisite rate.
Other applications require the rapid and precision control of the temperature of a boundary or interface between one medium, which may be a solid or a liquid, and an ambient environment, which may be a second medium such as a liquid or a gas. One such application is microchemistry where precision control of chemical or biological processes is required in some instances.

Active thermal control of surfaces by steering heating beam in response to sensed thermal radiation


A method and apparatus for delivering conditioned air using short duty cycles during which a damper is fully open for a time and fully closed for the remaining time. Conditioned air is continuously supplied to a plenum at low pressure and is applied to the space when the damper is open and blocked when the damper is closed. The proportion of on to off time during each duty cycle is adjusted to meet the load. When several supply terminals serve a space, their duty cycles are staggered to avoid fan instability. A special motor is coupled directly to the damper shaft for fast opening and closing of the damper. A magnetic latch holds the damper open or closed until the motor moves it again.

Conventional systems for delivering air for the heating and cooling of buildings use one of three different techniques. A constant volume system continuously supplies a constant volume of air and varies the temperature of the air that is being supplied in order to achieve a temperature change in the space. Variable volume systems operate under simple on/off control or use analog throttling damper or fan modulation to vary the flow rate.
All of these conventional systems have serious shortcomings. A typical constant volume system uses a thermostat in the space that senses the ambient temperature and sends a feedback signal. If the air temperature is above the set point temperature, the air supply temperature is reduced. Conversely, the air supply temperature is increased if the sensed temperature is below the set point. Although constant volume systems are relatively simple and provide good ventilation, they have suffered a decline in popularity due primarily to their energy inefficiency. The problem is that when the load is low, a constant volume system delivers more air than is necessary to maintain the set point temperature. This results in a waste of fan energy which takes on increasingly adverse significance as energy costs increase.
Variable volume on/off systems are widely used because they are simple, economical to install and relatively inexpensive to operate. However, there are important disadvantages in that there is no ventilation during off cycles, the temperature in the space is non-uniform, there is considerable noise variation between on and off cycles, there is by necessity a significant dead band in the thermostat control, and they are not practical for use other than in single zone systems.
Variable volume systems that vary the flow using variable dampers or variable fans are advantageous in that they are able to closely track the load in the space and are efficient in fan energy use. However, they are also characterized by relatively high costs and complexity, noise variation caused by flow modulation, ineffective ventilation, and inadequate mixing at low air volumes and load.
Analog modulation techniques for varying the airflow are particularly disadvantageous when the air quantity is reduced under conditions of low loading. When the flow if reduced, there is also a reduction in the air momentum, velocity, air throw, air mixing and air induction. This results in poor comfort to the occupants of the space and a compromise in the thermal efficiencies of the system. These problems have been addressed by using air terminals in which the discharge area is restricted to maintain a relatively constant velocity as the flow rate is reduced. However, there is still a reduction of mass in the discharge air and associated limitations in the kinetic energy, momentum, mixing, induction and air throw. At low supply pressure, these problems are especially pronounced. For all of these reasons, the so-called constant velocity, variable area devices are deficient as to the range of loading conditions they can successfully handle.
Response rates have been another problem associated with variable damper mechanisms. Standard practice is to provide a slow opening and closing time for the damper in order to better match the dynamic response of the space to the response of the controls, the sensing elements and the damper mechanism. If the response is too rapid, unstable control of the damper can result and cause a "hunting" condition in which the damper is repeatedly repositioned without producing the correct air quantity. Conversely, if the damper opens and closes too slowly, the control of the temperature in the space suffers. This condition is referred to as "drift" and often results from efforts at avoiding the hunting effect at the expense of transient response. Reaching a compromise where the system is well tuned is always challenging and often labor intensive even if successful.
A further problem with prior art dampers is that they are subject to noise that results mainly when the air velocity changes. Air flowing through small areas at low flow rates can cause vibration of the hardware components and can also result in objectionable noise from the air itself. The result is that noise at objectionable levels can be produced, with varying noise at different flow rates making the situation even less acceptable.
Treating air in other ways such as for high or low humidity, oxygen depletion, or excessive carbon dioxide is subject to the same problems.

Method and apparatus for delivering conditioned air using pulse modulation


A shelter and a method of providing a shelter are provided. The shelter includes a roof structure supported by a plurality of wall structures. The wall structures are anchored securely into at least one foundation. A display panel extends adjacent to at least one of the wall structures but is structurally separate therefrom. The display panel includes advertising materials.

Transit shelters provide covered areas for passengers waiting for transportation, for example, a bus or a train. It is desirable to provide waiting passengers with protection from the elements, such as wind and precipitation, as well as to provide safety by providing a lighted area. Additionally, it is desirable to have transit shelters that blend into the urban setting and that may be placed at any location within a city without detracting from the surrounding area. Transit shelters that maintain their pleasing appearance over time and that do not require continual maintenance, such as painting or refinishing, are also advantageous.
In typical prior art shelters and the most secure and aesthetically pleasing structure has traditionally included a rear wall, one or two side walls and a partial front wall supporting a roof structure. This supplies shelter from wind and rain from nearly all sides. Shelters are typically scant structures, both for economic and aesthetic purposes. Often, in hurricane-prone or high-wind locations, structural damage may occur with prior art structures.
Transit shelters also may be used for advertising displays. In prior art structures, one of the walls of the shelter to attract the attention of waiting customers. Lighted advertising displays are especially advantageous for an income revenue stream for the shelter owner to defray the cost of the shelter. The displays also provide light for the shelter for increased safety and to deter theft and vandalism. However, providing conventional lighting in shelters in urban and rural areas is expensive because a permanent power supply must be linked to each shelter. Therefore, an alternative energy source, such as solar energy, to provide a self-contained lighted shelter is highly desirable.
Thus, a need exists to provide a transit shelter that also is hurricane wind resistant and maintains its integrity and appeal over time after repeated exposure to the elements and further provides a self-contained lighting source.


A radio transceiver including a PLL synthesizer and is adaptable to a TDMA system in which the frequency of a radio frequency carrier is switched frequently at high speed. When an unlock alarm of the PLL synthesizer is used as one of the device alarms, the unlock alarm to be generated in an initial unlock period which is usually provided every switching of an output frequency of the PLL synthesizer is not used as one of the device alarms. The prohibition of generation of this unlock alarm is started in synchronism with a frequency control signal supplied from a control portion of the radio transceiver to a frequency divider of the PLL synthesizer for switching the carrier frequency and is limited to an OFF period of the carrier transmitting/receiving period.

The present invention relates to a radio transmitter/receiver (referred to as "transceiver", hereinafter) having an unlock alarm of a frequency synthesizer including a PLL (phase locked loop) as one of the device alarms and, particularly, to such a transceiver suitable for use in a radio communication system such as a time division multiple access (TDMA) communications system which requires high-speed and frequent switching between a receiving state and a transmitting state.

Radio transceiver having PLL synthesizer


Provided is a polishing liquid including cerium oxide particles, an organic acid A, a polymer compound B having a carboxyl acid group or a carboxylate group, and water, wherein the organic acid A has at least one group selected from the group consisting of —COOM group, -Ph-OM group, —SO3M group and —PO3M2 group, pKa of the organic acid A is less than 9, a content of the organic acid A is 0.001 to 1 mass % with respect to the total mass of the polishing liquid, and a content of the polymer compound B is 0.01 to 0.50 mass % with respect to the total mass of the polishing liquid, and pH is in the range of 4.0 to 7.0.

In production of an ultra large scale integrated (ULSI) semiconductor device, a processing technique for achieving high density and miniaturization of a semiconductor device is currently being studied and developed. One of the processing techniques, a chemical mechanical polishing (CMP) technique becomes essential in production of semiconductor devices for the smoothening of an interlayer dielectric film, the formation of a shallow trench isolation (STI), and the formation of plugs and embedded metal wirings.
In a conventional production process of semiconductor devices, an inorganic insulation film such as a silicon oxide film is formed through plasma CVD (chemical vapor deposition), low-pressure CVD, etc. A fumed silica-based polishing liquid is commonly studied as a chemical mechanical polishing liquid for use in smoothening of the inorganic insulation film. The fumed silica-based polishing liquid is prepared by adjusting the pH of slurry in which particles obtained through grain growth using a method such as thermal decomposition of silicon tetrachloride are mixed. However, the fumed silica-based polishing liquid still has a technical problem that a polishing speed is low.
Also, in the generation of a design rule of 0.25 μm or later, STI has been used for isolation of devices in an integrated circuit. For STI, CMP technique is used for removal of an excessive silicon oxide film formed on a substrate. In this case, a stopper film with a low polishing speed is formed under the silicon oxide film so as to stop polishing at a given depth. A silicon nitride film or the like is used as the stopper film. Not only to effectively remove the excessive silicon oxide film but also to sufficiently prevent the progress of polishing thereafter, a polishing speed ratio between the silicon oxide film and the stopper film is preferably high. However, a conventional colloidal silica-based polishing liquid has a low polishing speed ratio of about 3 between the silicon oxide film and the stopper film, and thus does not have sufficient properties practically usable for STI.
As a polishing liquid for the surface of a glass such as a photomask and a lens, a cerium oxide polishing liquid containing cerium oxide particles is in use. Since the cerium oxide particles are lower in hardness than silica particles or alumina particles and are less likely to cause a polishing surface to be scratched during polishing, the cerium oxide particles are useful for finishing mirror-surface polishing. Furthermore, the cerium oxide polishing liquid has an advantage that the polishing speed is faster than that of a silica polishing liquid such as a fumed silica- or colloidal silica-based polishing liquid.
As the cerium oxide polishing liquid, Patent Literature 1 below discloses a chemical mechanical polishing liquid for semiconductors using high-purity cerium oxide abrasive particles. Also, Patent Literature 2 below discloses a technique for adding an additive in order to control a polishing speed of a cerium oxide polishing liquid and improve global smoothness.

Polishing liquid and method for polishing substrate using the polishing liquid


A method and system for providing a magnetoresistive structure is disclosed. The magnetoresistive structure includes a pinned layer, a nonmagnetic spacer layer, a free layer, a specular layer, a barrier layer, and a capping layer. The spacer layer resides between the pinned layer and the free layer. The free layer is electrically conductive and resides between the specular layer and the nonmagnetic spacer layer. The specular layer is adjacent to the free layer and includes at least one of titanium oxide, yttrium oxide, hafnium oxide, magnesium oxide, aluminum oxide, nickel oxide, iron oxide, zirconium oxide, niobium oxide, and tantalum oxide. The barrier layer resides between the specular layer and the capping layer. The barrier layer is nonmagnetic and includes a first material. The capping layer includes a second material different from the first material.

In the effort toward achieving higher data density on recording media, spin filters have become of interest for use in magnetoresistive (MR) read heads. FIG. 1 is a diagram of a conventional spin filter 10. In general, the conventional spin filter 10 would be incorporated into a MR read head (not explicitly shown), which would include leads electrically connected to other electronics to drive current through the conventional spin filter 10 during reading. In such an application, current is generally driven in the current perpendicular to the plane (CPP) configuration. The CPP configuration is in the z-direction depicted in FIG. 1.
The conventional spin filter 10 includes a seed layer 12, an antiferromagnetic (AFM) layer 14, a pinned layer 16, a nonmagnetic spacer layer 24, a free layer 26, a filter layer 28, a specular oxide layer 30, and a capping layer 32. The seed layer 12 is used to provide the appropriate surface for growing the AFM layer 14 with the desired crystal structure. The AFM layer 14 is used in pinning the magnetization of the pinned layer 16. The pinned layer 16 may be a synthetic pinned layer, including ferromagnetic layers 18 and 22 separated by an electrically conductive spacer layer 20 that is typically Ru. The electrically conductive spacer layer 20 has a thickness configured to ensure that the ferromagnetic layers 18 and 22 are antiferromagnetically coupled. Thus, the magnetization of the ferromagnetic layer 18 is pinned by the AFM layer 14. The magnetization of the ferromagnetic layer 22 is set because it is strongly antiferromagnetically coupled to the magnetization of the ferromagnetic layer 18. The nonmagnetic spacer layer 24 is typically electrically conductive, for example Cu. The free layer 26 is ferromagnetic and typically includes materials such as CoFe.
The filter layer 28 has a high electrical conductivity and typically includes materials such as Cu. The specular oxide layer 30 may be a nano-oxide and typically includes materials such as alumina. The combination of the filter layer 28 and the specular oxide layer 30 has been used to provide adequate specularity of scattering of electrons from the free layer 26 that are incident on the specular oxide layer 30. In particular, the filter layer 28 has been utilized in the conventional spin filter 10 to provide a region, or filter, for specular reflection between the free layer 26 and specular layer 30. Thus, the magnetoresistance of the conventional spin filter 10 is improved. Consequently, the magnetoresistance of the conventional spin filter 10 is adequate. The capping layer 32 is typically oxidized Ta.
Although the conventional spin filter 10 functions, there are drawbacks to the use of the conventional spin filter 10. Insertion of the specular oxide layer 30 can increase the coercivity of the free layer 26, which is undesirable. Furthermore, the specular oxide layer 30 is generally a nano-oxide that can continue to oxidize during processing. The signal may degrade during the lifetime of the conventional spin filter 10. The conventional spin filter 10 thus suffers thermal instabilities and may have reduced reliability.
Analogous conventional spin filters are described in U.S. Pat. No. 6,795,279 B2; U.S. Pat. No. 6,556,390 B1; U.S. Pat. No. 5,898,612; U.S. Pat. No. 6,407,890 B1; U.S. Pat. No. 6,764,778 B2; U.S. Pat. No. 6,700,753 B2; U.S. Pat. No. 6,775,111 B2; U.S. Pat. No. 6,591,481; U.S. Pat. No. 6,613,380 B1; U.S. Pat. No. 6,636,398 B2.
Accordingly, what is needed is a system and method for providing a spin filter having improved thermal stability, signal sensitivity, and/or reliability.

This patent is subject to a terminal disclaimer.

Magnetoresistive structure having a novel specular and barrier layer combination


A bicycle drive unit includes a crank axle, a motor, an output member and a torque combining mechanism. The crank axle is rotatable about a first rotational axis. The motor has an output shaft rotatable about a second rotational axis. The output member is rotatable about the first rotational axis in a first rotational direction as the crank axle rotates about the first rotational axis in the first rotational direction. The torque combining mechanism operatively couples the output shaft of the motor to the output member to transmit rotation of the output shaft of the motor to the output member. The torque combining mechanism operatively separates the output shaft of the motor from the output member for preventing rotation of the crank axle from being transmitted to the output shaft of the motor as the crank axle rotates about the first rotational axis in a second rotational direction.

1. Field of the Invention
The present invention generally relates to a bicycle drive unit. In particular, the present invention relates to a drive unit for an electrically assisted bicycle.
2. Background Information
A coaster brake is conventionally known that is disposed on a bicycle (see European Patent Application Publication No. 2 380 806 A2 (Patent Citation 1) and Japanese Patent No. 4959858 (Patent Citation 2), for example). Generally, a bicycle crank arm and a front gear are non-rotatably coupled to each other. The coaster brake is disposed on a bicycle rear hub, and is operatively coupled to the front gear. Thus, when the bicycle crank arm is rotated in a rearward rotational direction, the coaster brake is operated.
On the other hand, an electrically assisted bicycle is conventionally known that uses a motor output as assisting power (see Japanese Laid-Open Patent Application Publication No. H08-310478 (Patent Citation 3), for example). In the electrically assisted bicycle, after a pedaling force which is inputted by the pedals is transmitted and the transmitted drive force is combined with a drive force from the motor, the combined drive force is transmitted to the rear wheel, thereby causing the rear wheel to rotate.


A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected. As a result, if the instruction which gave rise to the exception is in a loop or the like, instead of the instruction being processed, the fix-up code will be processed, which will avoid the exception condition.

Digital computers process a variety of diverse types of programs, with each program including a series of instructions that enable the computer to perform specific operations in connection with specific elements of data. A variety of types of processors are available for use in digital computer systems, with each type of processor being constructed in accordance with an architecture which describes, inter alia, the set of instructions that a processor constructed in accordance with the architecture is expected to execute, the format(s) of the various instructions, the types and formats of data which may be processed, definitions for various registers that may be used during instruction processing, how information in the computer's memory will be accessed and how a processor constructed in accordance with the architecture is to handle exception conditions which may be detected during instruction processing.
It is often desirable to enable one type of processor, as an "emulated processor," to be emulated by another type of processor, as a "host processor." A host processor generally emulates an emulated processor by processing programs which have been written for the emulated processor, to generate an output that effectively corresponds to the output that would be generated by the emulated processor. Generally, emulation is accomplished by translating a program generated for execution by an emulated processor (an "original" program) into a program which may be processed by a host processor (a "translated" program). This translation process may include, for example, generating from instructions and other elements of the original program, instructions and other elements which are based on the host processor's architecture thereby to provide the translated program. The translation may be performed by, for example, the host processor itself, by another processor in the same computer system or by another computer system and made available to the host processor which is to process the program, under control of a translation program. In performing the translation, each instruction or sequences or various groups of instructions in the original program (that is, the program based on the emulated processor's architecture) may be translated into one or a series or group of instructions for processing by the host processor. The translation process is typically performed for all or selected portions of an original program when the processor begins processing the original program, although it will be appreciated that an instruction or group of instructions of the original program may be translated as the processing proceeds. In addition, if the emulated processor's data formats are not directly useable by the host processor, the data may be processed to convert it from the emulated processor's formats to formats usable by the host processor.
As noted above, an architectural definition includes a description of how a processor constructed in accordance with the architecture accesses information in the computer's memory. Normally, data is stored in a memory subsystem which includes a series of storage locations, each of which has the capacity to store an eight-bit byte of data, and which are associated with a corresponding series of successive address values. Typically, a processor can process items of data, each comprising, for example, one, two, four, eight and so forth, bytes (generally, quantities of 2.sup.n bytes, where "n" is an integer), and modern processor architectures typically require that the data items be stored in an "aligned" fashion. That is, the architectures require that two-byte data items be stored in memory locations that are accessed having addresses that are divisible by two, and that four-byte and eight-byte, data items be stored in memory locations that are accessed having addresses that are divisible by four. If a data item is not properly aligned, typically the memory subsystem or the processor would need to perform a series of operations, after the contents of one or more storage locations are retrieved during a retrieval operation, to reorganize the contents and extract the desired data item from the retrieved contents, or during a storage operation, to re-organize the data item and store it in one or more storage locations.
For processors constructed in accordance with such modem architectures, if a memory access were to make use of an address that is not properly aligned, typically an exception handler would be called to handle the operation. The exception handler may control the processor to perform a number of operations to enable the contents of a number of storage locations to be retrieved and the data item fabricated from portions of the retrieved contents, during a retrieval operation, or to disassemble various portions of the data item and store them in respective storage locations, in a storage operation. Alternatively, to avoid the significant amount of overhead which would be encountered in calling the exception handler, performing the remedial operations, and returning to the program, the exception handler may merely enable the processor to terminate the program which made use of the non-aligned address reference. To avoid either of these, typically compilers provide that data items are laid out in the memory to ensure that non-aligned references are avoided.
However, a number of older architectures, illustratively the Intel Corporation x86 family of microprocessors, which currently includes its 8086, 8088, 80286, 80386, 80486 and "Pentium.TM." lines of microprocessors, permit non-aligned references. A problem arises, however, if it is desired to enable a "host" processor, which is constructed according to one of the modern architectures which requires that memory accesses be aligned, to emulate an emulated processor which does not require such alignment, since a non-aligned reference may be encountered during such emulation.

System and method for facilitating avoidance of an exception of a predetermined type in a digital computer system by providing fix-up code for an instruction in response to detection of an exception condition resulting from execution thereof


A photo filmstrip includes two side portions extending in a longitudinal direction, and has a leader, a trailer, and a series of effective frame regions arranged between the leader and the trailer. A series of bar codes are recorded on one of the side portions optically in a predetermined exposing condition, i.e., with light of an intensity suitable for the film speed. The bar codes are associated with the series of the effective frame regions. A test dot is recorded optically in the predetermined exposing condition, disposed in each of the leader and the trailer, for inspection of the optical recording.

1. Field of the Invention
The present invention relates to a photo filmstrip and a side printing method for the same. More particularly, the present invention relates to a photo filmstrip and a side printing method for the same, in which results of a side printing operation can be inspected with convenience.
2. Description Related to the Prior Art
A photo filmstrip includes a series of bar codes or patterned codes recorded in one of its side portions. The photo filmstrip also includes a series of information signs, such as a manufacturer sign, a photo film type (photo film speed), a type sign, and the like. Those codes and signs are all recorded photographically in forms of latent images in a line for manufacturing the photo filmstrip. When the photo filmstrip is developed in a photo laboratory for the purpose of photofinishing, the codes and signs appear in forms of visible images. The bar codes or the patterned codes are read by a bar code reader incorporated in a photographic printer, in order to designate printing frame numbers and determine a printing condition.
If the bar codes or the patterned codes are erroneously read, the user and the photofinishing agent are involved with troubles. It is important to form the bar codes or the patterned codes under an exposing condition, i.e., light intensity suitable for the photo film speed, so that they have sufficient optical density after being developed. The photo filmstrip as produced is transferred to a subsequent line. In the course of transferring of the photo filmstrip, a predetermined number of samples of the photo filmstrip are separated from strips produced in each the lots of the line, and are transferred to an inspecting line. In the inspecting line, those samples of the photo filmstrip are developed, to visibilize the bar codes or the patterned codes. Then optical density of at least one of the bar codes or the patterned codes is measured, and evaluated to check acceptability of the exposing condition.
A single bar included in the bar codes or the patterned codes is defined to have only a width of 0.455.+-.0.075 mm, and thus have a considerably small area. It is excessively difficult to measure the density of a single bar with stability, because the measurement is influenced by low density of unexposed portions around each single bar.

Photo filmstrip and side printing method for the same


A scroll compressor including a non-orbiting and an orbiting scroll member having mating involute wraps extending therefrom. In one exemplary embodiment, at least one of the non-orbiting and orbiting scroll members includes an inner wall forming a groove in an end of the involute wrap and extending substantially entirely along the length thereof. Positioned within the groove is a tip seal having outwardly extending projections configured to engage the inner walls of the involute wrap along at least a portion thereof. In one exemplary embodiment, the tip seal has a length that is less than the length of the groove. As a result, a gap is formed at the innermost portion of the involute wrap between the end of the groove and the end of the tip seal.

1. Field of the Invention
The present invention relates to scroll compressors, and more particularly, to tipseals for use with the same.
2. Description of the Related Art
In a typical scroll compressor, a motor and a compression mechanism are mounted within a hermetic housing. The compression mechanism includes a non-orbiting scroll member and an orbiting scroll member each having involute wraps in mating engagement with one another. The orbiting scroll member is connected to and driven by the motor, resulting in orbital movement of the orbiting scroll member. This orbital movement relative to the fixed scroll member creates a plurality of variable-volume working pockets between the wraps of the non-orbiting and orbiting scroll members.
During operation of a scroll compressor, working fluid is received between the involute wraps of the non-orbiting and orbiting scroll members and moved through the plurality of variable-volume working pockets toward to the center of the scroll members, sequentially increasing the pressure of the working fluid. In order to ensure an effective seal between the working pockets and to prevent leakage of the compressed working fluid therebetween, tip seals may be utilized. Tip seals are received within a groove formed in the end of the involute wrap of the non-orbiting and/or orbiting scroll members. By positioning a tip seal in the end of the involute wrap of the non-orbiting and/or orbiting scroll members, the tip seal may contact an end plate of an opposing scroll member to effect a seal between the involute wrap and the opposing scroll member.
Additionally, in order to ensure that the tip seal remains in contact with the end plate of the opposing scroll member, the tip seal may be slightly undersized relative to the groove in which it is received. As a result, pressurized working fluid from opposing sides of the involute wrap of the scroll member is received within the groove, which, in turn, biases the tip seal upward against the end plate of the opposing scroll member. However, by utilizing working fluid from opposing sides of the scroll member to bias the tip seal, the efficiency of the compressor is reduced. Specifically, the working fluid may travel through the groove from a higher pressure working pocket on one side of a scroll member to a lower pressure working pocket on an opposing side of a scroll member.
What is needed in the art is an improvement over the foregoing.


A vehicle driving assist apparatus for guiding a vehicle to a target position is provided. A basic path that changes the deflection angle θ to 0 is determined, and is subjected to similarity transformation. On the basis of the similarity-transformed path, a path factoring in transition from the initial steering angle is set. Then, a correction is made such that the area in the running distance-curvature graph regarding this path becomes equal to a corresponding area regarding the basic path, thereby setting a corrected path. The corrected path is similarity-transformed, and then is re-corrected in accordance with transition from the initial steering angle. Thus, a final target path is obtained.

1. Field of the Invention
The invention relates to vehicular driving assist apparatus and method for determining a locus of run to a target position and assisting the driving of a vehicle so that the vehicle follows the locus of run.
2. Description of the Related Art
A related-art technology for guiding a vehicle to a target position through the use of the automatic steering, the steering command, etc., is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 5-297935. In this related technology, errors in position, azimuth angle and curvature are measured, and a predetermined locus of run (track pattern) in which the distance of run and the curvature are associated with each other is subjected to similarity transformation so as to determine an actual control locus, as a technique for compensating for the errors.
This technology reduces the track pattern by similarity transformation, so that the vehicle can be promptly returned to the locus from a deviation therefrom if any. As an application of this technology, the track pattern may also be enlarged by similarity transformation, so that it becomes possible to set a guide path that provides a good margin for steering.
However, in the above-described technology based on similarity transformation, if the initial steering state has been set at a position other than a neutral position, the actual curvature and the curvature of a set path disagree. Therefore, since there is an initial-stage difference between the curvature of a set guide path and the actual curvature, the target direction of vehicle run cannot bring the vehicle to the target position. Furthermore, there is a case where the curvature does not become neutral even if the steering wheel is at a neutral position. Still further, if the initial steering state is limited to the neutral position, the operability of the assist operation remarkably degrades.

Driving assist apparatus and method for vehicle


A copolymer, which comprises about 30 to about 70% by weight of perfluoroalkylethyl (meth)acrylate represented by the following general formula: EQU CH.sub.2 .dbd.CRCOOCH.sub.2 CH.sub.2 Rf. where R is a hydrogen atom or a methyl group, and Rf is a perfluoroalkyl group having 4 to 16 carbon atoms; about 25 to about 60% by weight of stearyl (meth)acrylate; about 1 to about 15% by weight of 2-chloroethyl vinyl ether; and (d) about 0.1 to about 5% by weight of N-methylol (meth)acrylamide, sum total being 100% by weight, is novel and can form a water- and oil-repellent agent having a good resistance to yellowing of textiles, etc. and capable of shorter curing and low temperature curing.

1. Field of the Invention
The present invention relates to a novel copolymer and a water- and oil-repellent agent containing the same, and more particularly to a novel copolymer having a distinguished water- and oil-repellence and a water- and oil-repellent agent containing the same.
2. Related Art
Generally, copolymers having a water- and oil-repellence are copolymers each comprising a (meth)acrylate monomer containing a perfluoroalkyl group capable of directly giving a water- and oil-repellence, a fluorine-free monomer capable of improving an adhesiveness to the surfaces of materials to be treated such as fibers, etc. through an affinity thereto, and a monomer capable of giving a durability through self-crosslinking or reaction with reactive groups on the surface of the materials to be treated, typical of which are copolymers having chlorine atoms combined with the main chain, such as copolymers of perfluoroalkyl group-containing (meth)acrylate and vinyl chloride (JP-B-49-45758; JP-B-50-3438; JP-B-50-4800; JP-A-58-59277, etc.) and vinylidene chloride-based copolymers (JP-A-50-49179; JP-A-51-133511, etc.).
However, water- and oil-repellent agents comprising these copolymers have such drawbacks that unsaturated bonds are formed on the main chains by dehydrochlorination to give rise to a yellowing phenomenon more or less, which is an adverse effect on the treatment of the materials, on treated materials such as fibers, etc.
As to the yellowing mechanism observed in vinyl chloride-based or vinylidene chloride-based copolymers whose main chains are substituted with chlorine atoms, it is known that unsaturated bonds, if concentratedly formed in the polymers by dehydrochlorination reaction, can serve as conjugation sites and form chromophores due to such polyene structures Plastic Zairyo Koza (Plstic Material Lectures), Vol. 18, Vinyl chloride resin, pages 112-118, published by Nikkan Kogyo K. K., Japan!. Actually, the mechanism seems to takes more complicated decomposition steps.
The dehydrochlorination reaction is accelerated by high temperature treatment during the curing process in the presence of a cationic surfactant of emulsion dispersion type used in the preparation a water- and oil-repellent agent and cationic components in the antistatic agent or the softening agent using at the same time. Furthermore, in case of application on materials treated with some fluorescent dyes, a yellowing phenomenon, i.e. so called chlorine hindrance, occurs.
Copolymers having chlorine atoms as combined to the side chains are known, for example, copolymers having 2-chloroethyl vinyl ether as copolymerized (JP-B-49-45758). Such copolymers, when used as a water- and oil-repellent agent, can give a better feeling without causing any serious yellowing phenomenon, but still fail to satisfy desired properties such as applicability to natural fibers, shorter curing, etc. Likewise, 2-hydroxy-3-chloropropyl (meth)acrylate-based copolymers, etc. having chlorine atoms on the side chains have been so far used as a water- and oil-repellent agent (JP-A-55-45756), but have such disadvantages that feeling of stiffness will be more remarkable with increasing amount of the coplymers.

Copolymer and water- and oil-repellent agent containing the same


An integrated circuit implements simple and efficient normal power to low power and low power to normal power transitions. Dedicated shadow latch circuits are added, each having a corresponding system latch. The state of the system latches is transferred to the shadow latches upon a transition from normal to low power mode and the stored information is transferred back to the system latches on the transition from low power to normal power operation. The shadow latches are optimized to minimize power usage during low power operation.

Volatile circuits have been and are the norm in digital technology. In order to maintain information, continuous power is necessary. Accordingly, in order to minimize the power consumed when there is no user activity, digital technologies, including custom and ASIC, applications typically feature some form of standby, sleep or low power mode in contrast to the normal or run mode. The standby or sleep mode exhibits greatly reduced power dissipation. Standby mode or sleep mode may be defined by interruption of the system clock or by disconnecting the power supply or by both. Power is most effectively minimized when all, or almost all, of the logic on a chip can be disconnected from the power supply. Modern logic technologies tend to be optimized for performance, and as a result the "off" currents of logic transistors can be substantial. This, of course, minimizes the advantages which might be gained from any sleep or standby mode in which power remains continuously applied.
Recovery from the standby mode in which power is interrupted usually requires returning the chip to the state it was in just prior to entering the standby mode. Typically this requires saving the state of the latches. In some systems, there may be provision for an elaborate powerdown sequence in which the content of latches and registers can be stored on a hard disk. Simple applications, on the other hand, cannot justify a hard disk for these features. In addition, the complexity of the power-down sequence may be undesirable. The present invention is directed at providing a simple and inexpensive solution which implements a power-down standby mode in an efficient and effective manner The simplicity and efficiency of the invention recommend it for use on devices as simple as a pocket calculator, as well as in more complex devices.

International Business Machines Corporation