A transpose memory circuit is provided which comprises a number of dual port memory blocks each having a plurality of storage cells each configured for storing one or more data word. The dual port memory blocks form a storage array for storing at least one input matrix and outputting the at least one input matrix in transposed form. A data input is provided to receive a plurality data words on each cycle and a data output is provided to output a plurality of data words on each cycle. A read address logic is provided to generate read addresses such that one cell of each dual port memory block can be read out on each cycle. A write address logic is provided to generate write addresses such that one cell k of each dual port memory block can be written on each cycle. In each cycle, one storage cell of each dual port memory block is addressed by the read address logic. The data words stored in the addressed storage cells are read out from one dual port memory block and outputted through the data output. In each cycle, one storage cell of each dual port memory block is addressed by the write address logic, where the addressed storage cells have been read out in a preceding cycle and into which storage cells data words received through the data input are written. The transpose memory circuit is provided to receive an input matrix in cycles and to output the transposed input matrix in next cycles without any dead cycles interposed between them.

Transpose memories are used to provide an efficient and specifically adapted processing component to transpose N×N matrices. Transposition of N×N matrices is for instance used in two dimensional transform processes such as Discrete Cosine Transform for image and video compression.
Transposition of matrices may be implemented on the basis of conventional single port memory. However, when using conventional single port memory, first all elements of the matrix to be transposed has to be written into the single port memory before the transposed matrix can be read out thereof. This means, the transpose operation requires N×N dead cycles, when assuming that each matrix element is written on each cycle.
In another approach, two conventional single port memories may be used, each for buffering another matrix to be transposed. The data elements of a first matrix may be written into both memories, after which the data elements of the first matrix can be read out in transposed form from one memory and new data elements of a next matrix is being written to the other memory. During the next matrix write/read matrix operation the roles of memories are swapped—such a memory configuration is also designated as ping-pong memory. Conventional single ported random access memories can be utilized for the aforementioned ping-pong memory configuration. Dead cycles are avoided but at the cost of doubled memory capacity requirement.
Hence, there is a need for an improved transpose memory, which operates at a minimized memory capacity requirement and avoids dead cycles undesired to ensure a maximized throughput.


A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of data signal outputs, a first PMOS transistor and a second PMOS transistor. A first switch is coupled between a power voltage, the power control signal and the logic cell. A latch circuit coupled between the power voltage and the data signal outputs preserves the voltage levels respectively of the complementary pair of data signal outputs when the logic cell operates in the standby mode.

1. Technical Field
The present disclosure relates in general to a circuit for power management of standard cell application. In particular, the present disclosure relates to a circuit for power management of differential cascode voltage switch (DCVS) logic cells and differential cascode voltage switch with pass-gate (DCVSPG).
2. Description of the Related Art
Differential cascode voltage switch (DCVS) logic is a dual-rail CMOS circuit technique with advantages over single-rail traditional logic circuit techniques in terms of circuit delay, layout area and logic flexibility. A further advantage to DCVS circuits is the fact that they can be readily designed for a complex Boolean logic function within single gate delay using straightforward procedures based on Karnaugh maps and tabular methods. The logic function may also be synthesized.
An application entitled "Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems" is disclosed on IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997. FIG. 1A and FIG. 1B are conventional circuits of DCVS AND logic cell and DCVSPG AND logic cell, respectively.
In FIG. 1A, the DCVS circuit comprises two cross-coupled PMOS transistors p11 and p12 forming the circuit load. Below the PMOS load, four NMOS transistors n11, n12, n13, and n14 form the n-channel logic evaluation tree. Transistors n11 and n12 are turned on when the input signals A and B swing from low to high. The node QN is then discharged to the ground. The node Q floats at the transition period when the complementary input signals AN and BN swing from high to low. Both of the NMOS transistors n13 and n14 are turned off. The cross-coupled PMOS transistor p12 is turned on by the ground level at the node QN. The output node will be charged to high. Thus, the AND logic function is realized.
The DCVSPG AND circuit shown in FIG. 1B also comprises two cross-coupled PMOS transistors p21 and p22 forming the circuit load. The cross-coupled PMOS device load is the same as in FIG. 1A. With the same previous state, when both input signals A and B swing from low to high, the NMOS transistors n22 and n24 are both turned on. The node QN is then discharged into ground when the complementary signals AN and BN swing from high to low.
However, the conventional circuits described suffer standby leakage problems when the circuits are in standby mode. Standby leakage problems are serious concerns in very deep submicron technology with device size reductions, causing output state of DCVS or DCVSPG logic cells changed. FIG. 2 shows current leakage sources in a transistor 10. The transistor 10 comprises a gate 12, a source 14, a drain 16 and a well 18. Current leakage is caused by junction leakage I1, weak inversion I2, drain induced barrier lowering I3, gate induced drain leakage I4, punchthrough I5, narrow width effect I6, gate oxide tunneling I7 and hot carrier injection I8. Thus, data stored in a logic cell of a chip can be lost in standby mode because of standby leakage.
Solutions to the standby leakage problem mentioned, especially subthreshold leakage and gate leakage, generally involve increased package costs and design difficulty in handling power distribution. In addition, excessive power consumption limits the usage of very deep submicron technology due to increased processing costs as well as extra costs to handle the unexpected power. Thus, power management has become a significant and challenging issue in recent chip design.
U.S. Pat. No. 6,287,920 to Chatterjee, et al. discloses a method for forming multiple threshold voltage integrated into circuit transistors. Angled pocket type implants are formed to create asymmetric regions. The source and drain regions are connected such that multiple threshold voltage transistors are formed. Several different threshold voltage libraries must be employed to implement the multiple threshold voltage method. In addition, power saving is typically limited and often insufficient. The multiple threshold voltage method requires extra masks for different threshold voltage and power.
U.S. Pat. No. 6,664,608 to Burr, et al. discloses a back-biased MOS device. A plurality of p-wells and n-wells are formed on a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side thereof and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected p-wells. However, disadvantages of the back-biased method include the need for additional charge pump or multiple power supplies to apply extra bias to the well and/or substrate, junction or gate oxide breakdown concerns, excessive time required to charge or discharge between different modes, deep N-well process required, wasted power and design difficulty.
U.S. Pat. No. 6,667,648 to Stout, et al. discloses a voltage island communications circuit. An integrated circuit comprises a first circuit powered by a first power supply. The first circuit sends a first signal referenced to the voltage of the first power supply to a second circuit powered by a second power supply. The second circuit receives the first signal and converts the first signal to a second signal of the same logical value as the first signal and is referenced to the voltage of the second power supply. However, complicated design and tools are required by the voltage island method. In addition, the voltage island method cannot solve leakage problems in most active circuit blocks.
The conventional methods described comprise use multiple Vt libraries, back-biased and voltage island methods to solve power consumption problems during standby mode. However, these cannot solve the gate leakage problem without changing the normal power supply voltage, creating design problems and delays in the systems resuming normal operation.

Taiwan Semiconductor Manufacturing Co, Ltd.


A method for making a carbon nanotube composite hollow structure is provided. The method includes: passing a linear structure through a hollow rotating shaft and fixing the linear structure on the collecting unit; drawing a carbon nanotube structure from a carbon nanotube array loaded on the face plate, and adhering one end of the carbon nanotube structure to part of the linear structure between the wrapping unit and the collecting unit; forming a first carbon nanotube composite wire collected by the collecting unit by rotating the face plate and pulling the linear structure along a fixed direction such that the carbon nanotube structure wraps around the linear structure; forming a second carbon nanotube composite structure by applying a polymer liquid to the first carbon nanotube composite structure; and forming the carbon nanotube composite hollow structure by removing the linear structure from the second carbon nanotube composite structure.

1. Technical Field
The present disclosure relates to a carbon nanotube composite hollow structure.
2. Discussion of Related Art
Carbon nanotubes have interesting and potentially useful electrical and mechanical properties. Due to these and other properties, carbon nanotubes have become a significant focus of research and development for use in electron emitting devices, sensors, transistors, and other devices.
It is becoming increasingly popular for carbon nanotubes to be used to make composite materials. Carbon nanotubes can be composed of a plurality of coaxial cylinders of graphite sheets. Carbon nanotubes composited with metals, semiconductors, or polymers result in a composite material with qualities of both materials. Generally, the composite has a solid linear structure or a sheet-shaped structure. However, macro-scale carbon nanotube hollow structures and methods for making the same are not provided.

This patent is subject to a terminal disclaimer.

Method for making carbon nanotube composite hollow structure


A membrane bag comprising a volume for permeate collection, wherein the volume is completely enclosed in seamless membrane substance; a filtration unit comprising at least one above-described seamless membrane bag; the use of at least one above-described seamless membrane bag in a membrane bioreactor; the use of at least one above-described seamless membrane bag in water filtration or waste water purification; and the use of at least one above-described seamless membrane bag for the filtration or separation of a mixture of fluids, vapors and particles.

There has been much interest in membrane bioreactors (MBRs) in the water-world in recent years. MBR is a combination of two basic processes—biological degradation and membrane separation—into a single process where suspended solids and microorganisms responsible for biodegradation are separated from the treated water by membrane filtration unit. To date research has concentrated on the applicability of MBRs for domestic, industrial and mixed domestic and industrial waste-water treatment plants, concentrated flows from industrial production processes, the treatment of percolate water from waste disposal sites and the dewatering of sludge. The success of membrane bioreactors for wastewater applications led to a study of the application of MBR concepts in the drinking water production process.
In wastewater MBR-applications biological treatment in a reactor is combined with physical treatment by membrane filtration. By using membrane filtration instead of a settling process, high sludge loads can be maintained in the reactor, which (theoretically) lead to high biological degradation rates with a low sludge production. Sludge concentrations of 15-20 g/l are mentioned in the MBR-literature. The high efficiency of the process would make it possible to process highly concentrated flows and to design systems with a small footprint. In practice, the footprint is reduced by the smaller area required for the membrane filtration due to a maximal maintainable sludge concentration of 8-12 g/l and dispensing with a settlement tank. In addition higher sludge production rates have been registered than in conventional settlement systems.
JP 2003-135939A discloses a separation membrane manufactured by forming the porous resin layer on the surface of the porous base material composed of an organic fiber, part of a resin forming the porous resin layer being infiltrated into at least the surface layer part of the porous base material to form a composite layer with the porous base material at least in the surface layer part.
JP 2003-144869A discloses a separation membrane having a porous resin layer formed on the surface of the porous base material and a combined layer formed by integrating a part of a resin forming the porous resin layer with the porous base material, the pores satisfying the relationship: 2 dB≦dA (wherein dA is the average pore diameter on the surface of the side of the liquid to be treated; dB is the average pore diameter on the surface of the side of the permeated liquid) are formed on both surfaces of the porous resin layer.
JP 2001-321645A discloses a filter membrane element in which flow path materials are arranged on both the surface of a support plate and liquid separation membranes for removing impurities in the liquid above the flow path materials, the filter member element having a gap for water collection penetrating both surfaces of the support plate on a portion of the support plate; and a gap for water collection being arranged in the direction of a takeout port of the permeated water and communicating with the exit port of the permeated water.
U.S. Pat. No. 4,871,456 discloses a flat-plate laminated filter cartridge, comprising at least one filtering unit, in which said filtering unit comprises: an inner rim; an outer member surrounding an outer periphery of and spaced apart from said inner rim; upper and lower filtering films extending between said inner rim and said outer member and each having an entire inner periphery which is bonded to said inner rim, and an entire outer periphery which is bonded to at least one of another said outer periphery and said outer member so as to form a space therebetween serving as a path of a solution to be filtered; and at least one film supporting member made of one of paper, unwoven cloth and net, disposed on at least one of both sides of said upper and lower filtering films, and between said upper and lower filtering films. U.S. Pat. No. 4,871,456 further discloses that the filtering film supporting member is not at all bonded to the upper and lower filtering films and it is provided only to support the filtering films from inside.
U.S. Pat. No. 5,482,625 discloses a filtration membrane module submerged with a processed liquid in a processing tank comprising: a plurality of flat, rigid membrane cartridges vertically placed in parallel to each other as properly spaced from the adjoining membrane cartridges; cleaning stream generating means for supplying a flow parallel to the membrane surfaces of the membrane cartridges which opposes to gaps defined between the membrane cartridges opposite to each other; and sucking means for sucking permeated liquid in each membrane cartridge which is communicated with the passage of permeated liquid in each membrane cartridge; each membrane cartridge having a membrane supporting plate and a filtration membrane covering the outer surface thereof; and the membrane supporting plate supporting the filtration membrane is being made hollow by using a rigid structural member, the inside of the plate forming a passage of permeated liquid, the membrane supporting plate having an opening formed on the surface opposite to the filtration membrane the opening communicating to the passage of permeated liquid. The membrane cartridges can be membrane bags as illustrated in FIG. 27.
WO 03/037489A discloses a filtration-module for the cleaning of waste-water with a multiplicity of filtration membrane pockets each having at least one opening for the dewatering of its interior space and which are disposed vertically, parallel to one another and preferably at the same spacing to one another in a rigid holder and so arranged that the intervening spaces lying between neigboring filter membrane pockets are intensively traversed by a liquid, characterized in that the filter membrane pockets are configured to be substantially flat and flexible and on opposite sides are fixedly connected with the holder which has at least one suction line for carrying off liquid drawn through the filter membrane pocket opening, and in that the filter membrane pockets have a flexible liquid permeable core and/or a plurality of flexible permeable core elements.
JP 11-244672A discloses an element with longitudinally long permeate flow passage materials which are relatively flexible and allow the passing of the permeate and flat members disposed along both sides thereof, sealing parts being formed by tightly adhering the peripherally marginal three sides at the top end and both right and left ends thereof to constitute the quadrilateral flat planar membrane formed as a bag form. JP 11-244672A further discloses that the one side at the unsealed peripheral edge of the flat planar membrane installed with the membrane supporting member is superposed by about 1.5 cm in height on the surface on both sides of the upper part of the membrane supporting member and is welded to the membrane supporting member to support the flat planar membrane; that the heads larger in thickness than the membrane supporting member are formed at both ends of the membrane supporting member; and that both of the heads are provided with the nozzles which are communicated with the flow passages of the membrane supporting member and are used to take out the permeate.
U.S. Pat. No. 5,275,725 discloses in a second embodiment the forming the flat membrane support by casting a solution of the membrane-forming polymer on the surfaces of a membrane support and immersing the support in a suspended solidifying bath to form the semipermeable membrane parts by the so-called phase inversion method, wherein the permselective membranes can be bonded to the support by the anchoring effect wherein the penetration of the membrane-forming polymer solution into the nonwoven fabric constituting the surface layer of the support is arrested by the fibers after the gelation.
The membrane plates (filter pockets, bag with four-sided flat planar membrane) of the above-mentioned prior art are formed by bringing together the separate constituents (two membranes, spacer and support) and the two membranes are placed with their membrane supports opposite one another and a spacer is placed between them creating a gap. The resulting weak points of these concepts including the large number of construction steps; poor adhesion of the membrane to the module support resulting in detachment and stripping of the membrane; and operational problems due to the impossibility of back-flushing the membranes with sufficient pressure, as a result of the poor adhesion of the membranes to their supports, were addressed in WO 2006/056159A and WO 2006/015461A.
WO 2006/056159A discloses a frameless plate-shaped filter element, particularly for filtering fluid media, comprising outer filter layers and at least one layer of membrane material wherein between the outer filter layers at least one inner layer is provided that comprises at least on one face a plurality of bumps that are distributed across the face and mounted at a spacing from each other, the end surfaces of which bumps form a contact surface for an outer fluid-permeable layer. The attachment of the membrane layer to the reinforcing structure is however poor resulting in low backflush pressures that can be used.
CA 2 552 533A1 discloses a filter medium with at least one filter membrane which has a fabric ply as the support and protective layer, characterized in that at least one other filter membrane with another fabric ply is present as the support and protective layer, that between the two adjacent filter membranes a third fabric ply extends, and that the two adjacent filter membranes are connected to one another via threads of the two other fabric plies which extend through the third fabric ply.
WO 2006/015461A discloses an integrated permeate channel (IPC) membrane, comprising a permeate channel consisting of a spacer fabric having an upper and a lower fabric surface tied together and spaced apart by monofilament threads at a predefined distance, said permeate channel being interposed between two membrane layers, wherein said membrane layers are linked at a multitude of points with said upper and lower fabric surfaces. IPC membrane cartridges have a high resistance to backflush pressures thereby increasing their efficiency and WO 2006/015461A further discloses that it is possible to obtain an asymmetric spacer fabric-reinforced membrane with different pore size characteristics at both sides by applying different conditions on both sides of the dope coated spacer fabric.
However, WO 2006/015461A discloses the following manufacturing steps:                Spacer fabric preparation step: spacer fabric (knitted, woven or non/woven) unwinding; spacer fabric guiding into vertical position and spacer fabric spreading to prevent fold formation (perpendicular to the fabrication direction);        Spacer fabric coating step: simultaneous double-side coating of dope with a double-sided coating system and automatic dope feeding on both sides of the spacer fabric (same level at both sides) to obtain a dope coated spacer fabric;        Surface pore formation step: contacting of the double-side coated spacer fabric with water vapour phase. It is also possible to obtain an asymmetric spacer fabric-reinforced membrane with different pore size characteristics at both sides by applying different conditions on both sides of the dope coated spacer fabric.        Bulk formation step: coagulation of product into a hot water bath;        Post-treatment step: washing out of chemicals in a water reservoir; and        Drying step: drying of the product.
WO 2006/015461A also discloses the preferred presence of a sealant at the perimeter of the planar membrane arranged to prevent direct fluid movement from or to the permeate channel without passing through a membrane layer. Moreover, in the single exemplification of the use of IPC-membranes disclosed in WO 2006/015461A (Application 1) a sealant such as epoxy/polyurethane, any rubber or a hot melt or even welding was deemed necessary to close at least two (preferably opposite) edges of the IPC-MBR membrane 1. Individual sealing of the IPC-membrane requires considerable manutention for a single IPC-membrane meaning high production costs. Moreover, the presence of a sealant reduces the efficiency of the filtration process by creating a blind area thereby reducing the filtration efficiency. Moreover, the sealing of membrane cartridges made from an IPC membrane can constitute a weak point, which places a limit on the allowable backflush pressure and also on the filtering capacity of the membrane cartidges.
It is therefore desirable to develop a membrane unit with an integrated permeate channel not requiring a sealant at the perimeter of the membrane arranged to prevent direct fluid movement from or to the permeate channel without passing through a membrane.

Membrane bags with seamless membrane substance, uses thereof and filtration units therewith

De Vlaamse Instelling voor Technologisch Onderrzoek (VITO) N.V.


The present invention relates to a method of manufacturing MOS components having lightly doped drains wherein the implanting type ion used is different than that used in the formation of the source/drain regions. The present invention also includes the use of a tilt implantation angle accompanied by substrate rotation during the implantation process to form lightly doped drain structures on two sides of the source/drain regions. The mask is the same for the formation of the source/drain regions as that for the formation of the lightly doped drain regions. The method of manufacturing MOS components having lightly doped drains according to this invention has fewer manufacturing processes for the formation of spacers than the conventional methods. Moreover, the reduction in spacer production results in an increased contact surface area for subsequent contact window formation, thereby lowering contact resistance.

1. Field of the Invention
The present invention relates to a method of manufacturing metal-oxide-semiconductor (MOS) components, and more particularly to a method of manufacturing MOS components having a lightly doped drain structure formed by using different ionic types in the implementation process.
2. Description of Related Art
MOS components are becoming smaller and smaller in order to increase the level of integration and speed of operation, therefore, the channel length of such components is being correspondingly reduced. As a consequence of the shortening of the channel length of a MOS transistor, detrimental short channel and hot electron effects have become dominant. To alleviate the problems caused by a reduction in channel length, it is common practice to add a group of impurity diffusion regions with dopant concentration level less than that of the original source/drain regions in areas surrounding the channel inside the original source/drain regions. This structural layout is known as a lightly doped drain (LDD).
FIGS. 1A through 1D show the manufacturing of an MOS component having a lightly doped drain structure. Referring to FIG. 1A, a substrate 10, such as a P-type silicon substrate, is provided having a plurality of gates 11 and field oxide layers 12 defined over it. Using the gates 11 and the field oxide layers 12 as masks, N-type ions, such as phosphorus ions, having a moderate concentration of about 10.sup.13 /cm.sup.2 are implanted into the substrate 10 forming lightly doped drain regions 13.
Referring next to FIG. 1B, spacers 14 are formed on the sidewalls of the gates 11. The spacers 14 can be made from material such as silicon dioxide or silicon nitride. The spacers 14, beside serving as partitions for separating adjacent gates 11, further function as masks with gates 11 when the source/drain regions are undergoing heavy doping.
Referring next to FIG. 1C, using the gates 11, the spacers 14, and the field oxide layers 12 as masks, N-type ions such as arsenic ions, having a concentration level of about 10.sup.15 /cm.sup.2 and deep implantation depth levels, are implanted into the substrate 10 forming the source drain regions 15.
Thereafter, referring to FIG. 1D, a planarized insulating layer 16 made from material such as borophosphosilicate glass (BPSG) is formed over the surfaces of the aforementioned layers. Next, a pattern is defined on the insulating layer 16 thereby forming contact window openings 17 that expose the source/drain regions 15. Finally, a conducting layer 18, such as an aluminum layer, is formed in the contact window openings 17 to form a plurality of contact windows 18.
In the above described conventional manufacturing process for forming a lightly doped drain structures of an MOS component, the spacers 14 are required to function as masks in the process of doping the source/drain regions 15 after the formation of the lightly doped drain regions 13. Moreover, because of the presence of spacers 14 on two sidewalls of the gate 11 and the thickness of the insulating layer 16, the available area for the contact window openings 17 is reduced, thereby lowering the contact surface area with the source/drain regions 15. This reduction in contact surface area results in increased resistance and a lowering the level of integration between the source/drain regions 15 and the conducting layer 18.

Method of manufacturing MOS components having lightly doped drain structures


An apparatus including an elongate handle, having a shaft coaxially aligned therewith, including positioning structure such as an "O" ring to maintain a plurality of weighted rings in adjacency to a remote end of the shaft in abutment with a head cap. A modification of the invention includes a plurality of shafts mounted to the head cap, each including further ring structure to provide for adjustable resistance in use of the organization.

1. Field of the Invention
The field of invention relates to exercise apparatus, and more particularly pertains to a new and improved forearm exercise apparatus wherein the same is arranged as a compact, readily adjustable organization.
2. Description of the Prior Art
Various exercise apparatus has been employed in the prior art, wherein U.S. Pat. No. 4,258,913 to Brentham sets forth a forearm exercise structure including a support frame having various manipulated handle members secured thereto. U.S. Pat. No. 4,840,370 sets forth a hand exercise apparatus forming a block of material for grasping by the palm of the hand, wherein U.S. Pat. No. 4,901,999 sets forth a hand, wrist, and forearm resistance structure employing a plurality of spherical balls attached to ends of a cylindrical ball mounting grip handles.
The instant invention attempts to overcome deficiencies of the prior art by providing for a forearm exercise apparatus arranged to focus and concentrate on the exercise of forearm muscles of an individual's arm and in this respect, the present invention substantially fulfills this need.


A low cost prefabricated fireplace is provided with an open-ended fireplace box which requires no outer sheet metal shroud or housing as employed in the prior art sheet metal fireplaces. The novel fireplace box has at least five walls which consist substantially of insulating reinforced ceramic fiber (RCF) material and a binder. A modular burner system is removably mounted on the bottom wall of the fireplace box and a floor panel is mounted on the modular burner system forming an air chamber below the floor panel in the fireplace box. A decorative surround trim is attached to the open end of the fireplace box which serves to support fixed or operable glass doors. A log set which may include a log burner is mounted above the floor panel which supports a decorative log set. Apertures are made in the sides or top of the fireplace box to accommodate an air supply and/or an exhaust stack. The fireplace box serves as a base unit to which other fireplace components are attached, connected or supported so that the need for conventional sheet metal is substantially eliminated. The resulting fireplace can be completed in many different configurations using a common fireplace box which needs no additional surrounding insulation for installation in a room.

1. Field of the Invention
The present invention relates to prefabricated fireplaces in general. More specifically, the present invention relates to low cost fireplaces that comprise an open-ended fiber insulation firebox and combustion chamber formed or molded in one piece from a slurry of refractory ceramic fibers.
2. Description of the Prior Art
It was known heretofore that flat panels of lightweight, low coefficient of heat transfer ceramic material could be made. Heat-N-Glow of Savage Minnesota has produced and incorporated thin panels of such insulating ceramic material into floors of their prefabricated fireplaces that are made of sheet metal.
In our co-pending application U.S. Ser .No. 08/588,866 there is shown and described an open-ended non-porous ceramic combustion chamber which may be assembled from panels in the field or made by forming a one piece open box on forming molds. Both type open boxes may be assembled into a fireplace by adding a burner and a log set, etc. The burner system illustrated employs the floor of the firebox as the floor of the combustion chamber. The referenced application also shows and describes how standard fireplace boxes may be assembled into different fireplace units by connecting a burner system to the open box and connecting different exhaust stacks and air supplies to the standard open box.
The present application shows and describes improvements in this co-pending application which may be universally applied to all types of fireplace configurations, thus, the present invention when applied to prefabricated fireplaces substantially reduces the manufacturing cost of the most expensive fireplaces and for the first time provides the technology to produce very low cost decorative gas fireplaces for custom installation and for stand alone unvented units.
Applicants are not aware of any prefabricated fireplace units which do not require an outer housing or separate outer insulation around the outside of the combustion chamber or firebox.
It would be desirable to provide a novel fireplace units that virtually eliminates sheet metal combustion chambers, outer sheet metal shrouds and expensive stamped sheet metal forms and also provide a low cost fireplace unit.

Low cost prefabricated fireplace with fiber insulation firebox


A technique for detecting and localizing vascular occlusions in the brain of a patient is presented. The technique uses volumetric angiographic data of the brain. A mid-sagittal plane and/or lines is/are identified within the set of angiographic data. Optionally, the asymmetry of the hemispheres is measured, thereby obtaining an initial indication of whether an occlusion might be present. The angiographic data is mapped to pre-existing atlas of blood supply territories, thereby obtaining the portion of the angiographic data corresponding to each of the blood supply territories. For each territory (including any sub-territories), the asymmetry of the corresponding portion of the angiographic data about the mid-sagittal plane/lines is measured, thereby detecting any of the blood supply territory including an occlusion. The angiographic data for any such territory is displayed by a three-dimensional imaging technique.

Determination whether a blood vessel is occluded (i.e. blocked) or patent (i.e. open), and, in the case of an occlusion being identified, localization of this occlusion, are important in the diagnosis and treatment of vascular diseases. This is also critical in acute stroke management. Imaging is a means to obtain this information. Volumetric angiographic data (that is, a set of data in which elements of the data correspond to respective points within a three-dimensional region) can be acquired with various imaging techniques, such as magnetic resonance angiography (MRA), computed tomography angiography (CTA) or X-ray rotation angiography. Present techniques for detecting occlusions involve a requirement to segment volumetric angiographic images (i.e. partition the images into regions which are the estimates of the positions of cerebral structures within the image). For this purpose, the Marching Cubes algorithm is typically used. The whole procedure of iso-surface segmentation and surface display is time consuming, particularly, in acute stroke management. Alternatively, the scan can be examined by using Maximum Intensity Projection (MIP) display. MIP, as a 2D projection of a 3D volume does not contain full information.

Detection and localization of vascular occlusion from angiography data

Agency for Science, Technology and Research


An interlocking paperboard carton blank (10) is disclosed. The carton blank has at least one flap (19) projecting from a side dge of a first base panel (14), the flap having a leading portion (20) which is folded about a scored waist section score line (23) back onto the remainder of the flap to double the thickness of the flap. The leading portion of the flap includes at least one, and preferably two laterally projecting portions (21). The flap is inserted folded end first into at least one correspondingly positioned opening (27) defined in a second base panel (15) of the carton blank. The flap is passed into the opening until the two lateral projections of the folded flap are passed through the opening in the second base panel, whereupon the laterally projecting portions are constructed and arranged to be urged upwardly from the remainder of the flap so as to prevent withdrawal of the flap from the opening while the leading portion of the flap remains folded against the remainder of the flap to ensure that the flap has a doubled thickness in the interlocked base panels of the carton blank.

According to the present invention an interlocking arrangement is provided for connecting the two end pieces of a paperboard carton blank having at least one flap projecting from a first one of the end pieces for cooperation with at least one respective opening defined in a end second end piece, of the paperboard carton blank the flap or flaps each having a leading portion spaced farthest from the remainder of the first end piece of the carton blank, behind which leading portion is a portion which projects laterally at least in one direction, the flap or flaps each being folded such that the leading portion and the laterally projecting portion are folded back on the rest of the flap, the flap is then inserted into its associated opening within the folded area or areas of the second piece first, so that when the laterally projecting portion of the flap passes through the opening it takes up a position clear of the edge of the opening, thereby preventing withdrawal of the flap while the leading portion thereof remains held by the opening. Such an interlocking arrangement can lie generally flat relative to the pieces of paperboard.
Preferably each flap has portions projecting laterally in both directions, the flap having a waisted section immediately behind the projecting portions, at which waist the flap is folded back along a straight line.
In preferred embodiments the opening comprises a single cut having two ends.
With chosen arrangements the laterally projecting portions are angled into the waist and into the leading portion. Also the maximum width across the laterally projecting portions of each flap is substantially the same as the maximum width of the associated opening. It is a preferred feature that the ends of the opening cut are angled in a manner corresponding to the angling, when folded back, of the laterally projecting portions towards the leading portion.
Preferably the flaps are dimensioned in such a way that during insertion of the leading portions do not clear the edges of the openings defined in the second end piece of the carton blank.
In certain embodiments the two pieces of paperboard are constituted by ends of a wraparound sleeve for containing one or more articles. Preferably two or more flaps are provided on one end of the sleeve and two or more corresponding openings are provided on the other end of the sleeve.
One preferred feature is that the ends of the openings are aligned on a fold line such that the free portion of the sleeve end hinges about the fold to in assist in the insertion of the flaps.
Another feature is that the fold comprises two end sections joined by a C-shaped cut extending away from the leading portion of the flap so that when folded back, a tab projects forwardly of the fold line.
Embodiments of the present invention will now be described in more detail in the accompanying drawings.


A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.

Capacitance enhancement is critical for continued scaling of trench embedded DRAM (eDRAM). In conventional trench eDRAM flow, trench capacitors are formed before CMOS logic processes. Although using high-k as the capacitor dielectric is known to enhance trench capacitance, the high thermal budget of CMOS process (e.g., STI anneal) poses constraints on the use of high-k materials that can be used in conventional trench eDRAM technology.
For example, forming a buried plate while protecting BOX is a challenge when a SOI substrate is used to manufacture eDRAM. Although the SOI substrate below the BOX can be pre-doped during SOI substrate fabrication, such an approach results in a nonconventional SOI substrate which, in turn, causes integration challenges when eDRAM and logic are formed on such a customized SOI substrate.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.

Metal trench capacitor and improved isolation and methods of manufacture

INTERNATIONAL BUSINESS MACHINES CORPORATION


A virtual source/virtual destination device including a BRM information extracting unit for extracting rate information and congestion information from a resource management cell transmitted in a closed loop control section on the destination side, a BRM information determining unit for determining rate information and congestion information to be notified to a closed loop control section on the source side based on the rate information and said congestion information at the closed loop control section on the destination side extracted by the BRM information extracting unit, and a VS module for writing the rate information and the congestion information determined by the BRM information determining unit to a resource management cell to be sent to the closed loop control section on the source side.

1. Field of the Invention
The present invention relates to a virtual source/virtual destination device in an asynchronous transfer mode (ATM) network and, more particularly, to a virtual source/virtual destination device which notifies a device located upstream on a signal flow of a rate and a congestion state, in an ATM network where available bit rate (ABR) service is provided for managing a band using a resource management cell (RM cell).
2. Description of the Related Art
As the service on an ATM network, ABR service has been recommended in these days. Such recommendation is recited, for example, in "ATM Forum Traffic Management Specification version 4.0" (The ATM Forum Technical Committee, April 1996). ABR service is the service intended to guarantee not transmission quality against a data transmission delay but quality against data abandonment. In other words, the service guarantees accurate transmission of data contents even when sacrificing an outgoing cell rate. In thus characterized ABR service, an allowable cell rate (ACR), which is an outgoing cell rate at an end-system, is controlled by closed loop control using a resource management cell (RM cell).
FIG. 5 is a block diagram showing concept of a conventional ATM network associated with the above-described ABR service. With reference to FIG. 5, connected to an ATM network 101 is a source 10 and a destination 20, in which an ATM switch 102 is disposed.
For the data transmission by the source 10 to the destination 20, the source 10 first sends out a forward resource management cell (FRM cell). Upon reception of the FRM cell which has sent from the source 10 and then passed through the ATM switch 102, the destination 20 returns the FRM cell as a backward resource management cell (BRM cell) to the source 10.
At the time when the FRM cell sent from the source 10 or the BRM cell sent from the destination 20 passes through the ATM switch 102, the switch writes to the FRM cell or the BRM cell, an explicit rate (ER), a congestion indication bit (CI bit) and a no increase bit (NI bit) which are information on a congestion state at that time. ER is a rate which indicates that no congestion occurs when the ATM switch is at a rate less than or equal to this rate. CI bit indicates congestion when its value is "1" and indicates non-congestion when it is "0". NI bit indicates no rate increase when its value is "1" and rate increase allowed when it is "0". The source 10 modifies an outgoing cell rate based on the ER, the CI bit and the NI bit written on the BRM cell sent from the destination 20.
ACR transmittable from the source 10 is controlled based on the rate information and the congestion information written on a turning-around RM cell. Large distance between the source 10 and the destination 20 and a long round trip time (RTT) therefore result in increase in a congestion control loop using an RM cell.
As a result, it will take a longer time for the congestion information written on the RM cell by the ATM switch 102 to arrive at the source 10, whereby rate control performance of the source 10 is degraded. In addition, since it is not before an FRM cell sent out first from the source 10 returns to the source 10 as a BRM cell that rate control by an RM cell starts operating, no improvement is made in data transfer efficiency at the start of data transmission.
For the purpose of solving the above problems, ABR service defines a virtual source/virtual destination (VS/VD) device as recited in the above-described literature, for example. VS/VD is provided halfway in the network to virtually assume a terminal behavior for conducting RM cell termination processing. Introduction of a VS/VD device into the ABR service network results in dividing a congestion control loop using an RM cell to shorten an arrival time of congestion information at the source 10, thereby improving rate control performance by the source 10. In the following description, a unit of such a divided congestion control loop is referred to as a segment.
FIG. 6 is a block diagram showing one example of an ATM network associated with ABR service in which a congestion control loop is divided into a plurality of segments by a conventional VS/VD device. In the illustrated example, the ABR service network has a congestion control loop divided into three segments 104a, 104b and 104c by VS/VDs 103a and 103b. In the following description, the side of a source 10 is referred to as being upstream and the side of a destination 20 as being downstream.
In FIG. 6, in data transmission from the source 10 to the destination 20, an FRM cell sent out by the source 10 is terminated by the VS/VD 103a and returned to the source 10 as an BRM cell. Also between the VS/VD 103a and the VS/VD 103b and between the VS/VD 103b and the destination 20, an RM cell similarly turns around within each segment. The VS/VD congestion indication system in the illustrated example is to indicate congestion, at the time when a cell buffer in the VS/VD congests, by applying the congestion indication to an RM cell turning around in an upstream segment.
The above-described conventional VS/VD device, however, has a shortcoming that rate information and congestion information written in an RM cell is neither received nor transmitted directly over divisional segments.
In FIG. 6, when congestion occurs at a switch in the downstream segment 104c, a BRM cell which stores the congestion information is terminated by the VS/VD 103b and therefore fails to arrive at the upstream segments 104b and 104a. While the VS/VD 103b reduces an ACR trasmittable to the destination 20 from the VS/VD 103b according to the contents of the BRM cell which stores the congestion information of the downstream segment 104c, an ACR from the upstream VS/VD 103a remains unchanged, so that a cell buffer of the VS/VD 103b congests. Therefore, the VS/VD 103b, upon occurrence of congestion of a cell buffer in its device, for the first time stores congestion information in the BRM cell to notify the VS/VD 103a, causing the VS/VD 103a to reduce the ACR to the VS/VD 103b.
Furthermore, reduction of an outgoing cell rate at the VS/VD 103a to the VS/VD 103b causes congestion at a cell buffer of the VS/VD 103a similarly to the generation of congestion in the cell buffer of the VS/VD 103b as mentioned above. Then, following the same procedure, a congestion indication arrives at the source 10.
As described in the foregoing, congestion control by a conventional VS/VD device has a shortcoming that when congestion occurs at any segment on a network, buffers of all the VS/VD devices existing halfway between connections congest before a congestion indication arrives at a source to reduce an outgoing cell rate at the source.
Another shortcoming is that since congestion indication and rate information indicative of a downstream congestion state do not arrive at the source until all the buffers of the VS/VDs existing halfway between connections congest, the congestion indication and notification of the rate information to the source takes much time to delay elimination of the congestion.
One of conventional ATM communication devices providing ABR service traffic is disclosed, for example, in Japanese Patent Laying-Open (Kokai) No. Heisei 7-297843, entitled "ATM Communication Device". The literature recites an ATM communication device with dynamic bandwidth allocation (DBA) comprising an accumulation device associated with DBA traffic including an accumulation device directed to ABR traffic, an device to which an ABR bandwidth request is allocated after all the remaining DBA bandwidth allocation is satisfied, and a device which interrupts, for the purpose of transmitting DBA traffic with higher priority than the others, said ABR transmission before band allocation including the ABR transmission is fully used. While the literature refers to an end-system and a switching system capable of handling traffic of ABR service, it refers nothing about a VS/VD device. It is therefore impossible to solve the problem concerning congestion indication at an ATM network into which the above-described VS/VD device is introduced.

Virtual source/virtual destination device of asynchronous transfer mode network


System and method for real-time on-line interactive forecasting of an element, the method comprising: receiving a user input for a forecast element; and capturing at least one forecast of an element or event, storing that at least one forecast of an element or event, and sending collective contributed forecast information back to the user who originally sent the input in response to the receipt of the user input for optional display. The method may optionally also include either or both of providing a minimal input forecast interface, and/or pre-queuing a list of elements for fast forecasting; receiving a user input for a forecast element. Computer program product for execution on a single computer or plurality of computers to implement the inventive method and system.

As described in co-pending U.S. Utility patent application Ser. No. 10/107,420 filed 26 Mar. 2002 and entitled System and Method for Forecasting Information Using Collective Intelligence from Diverse Sources (which application is incorporated by reference herein), it is possible to construct a real-time forecast system that includes: (a) means for gathering forecasts from a plurality of individuals or other entities within a defined period of time; (b) means of filtering and processing these individual forecasts to generate a collective forecast, and (c) means for communicating the collective forecast back to individuals very quickly.
However, even such a forecasting system generally operates with greater prediction or forecasting accuracy as greater numbers of forecasts are gathered from users (also referred to as contributors). Users, in turn, are more likely to provide a larger number of forecasts if one or more of and preferably all of the following are true of the system: (a) the system is very easy to use initially; (b) the system already has some forecasts or predictions at the time the user first uses the system; and (c) the system becomes even easier to use (or more useful with ease of use) upon repeated use.
Therefore, there remains a need for a system and method for forecasting that encourages new and previous users to continue to utilize such a forecasting system and method of forecasting by making it easier to use and contribute to such forecasts so that larger numbers of forecasts may be obtained and the forecasting accuracy may increase to the extent possible by the increased participation and number of contributions.


An antenna duplexer has a first filter and a second filter coupled to respective signal terminals and to a common node. The common node is coupled to an antenna terminal. The first filter has a higher-frequency passband than the second filter. A transmission-line circuit, inserted between the first filter and the common node, increases the impedance of the first filter in its lower stopband. The transmission-line circuit includes an internal node, a first transmission line coupling the internal node to the common node, a second transmission line coupling the internal node to the first filter, and a grounding circuit such as a capacitor coupling the internal node to ground. The grounding circuit further enhances the lower stopband impedance of the first filter.

The present invention relates to mobile communication equipment, more particularly to an antenna duplexer that can be used in the wireless interface of a device such as a mobile telephone.
The antenna duplexer of a mobile telephone or other mobile communication device must be small in size, and must combine low passband insertion loss with high stopband attenuation. As the density of mobile communications in the radio frequency spectrum increases, the antenna duplexer must also be able to deal with increasingly close spacing between transmit and receive channels, and there is a further trend toward increasing bandwidths of these channels.
Antenna duplexers employing surface-acoustic-wave (SAW) filters are particularly suitable for meeting these requirements. Examples of antenna duplexers of this type can be found in Japanese Unexamined Patent Applications 9-98046 and 5-167388. FIG. 7 of the latter document (5-167388) is reproduced here as FIG. 1.
The antenna duplexer shown in FIG. 1 has two SAW filters F1, F2 coupled in parallel via nodes xe2x80x98axe2x80x99 and xe2x80x98bxe2x80x99 to a pair of common signal terminals T0. SAW filter F1 leads to another pair of signal terminals T1; SAW filter F2 leads to still another pair of signal terminals T2. Each SAW filter F1, F2 has a ladder network configuration comprising a series resonator (denoted RS0 in F1 and RS in F2) and a shunt resonator (denoted RP in F1 and RP0 in F2). Each of these resonators has a single pair of interdigital transducers (not visible) flanked by a pair of reflectors (not visible). The interdigital transducers and reflectors are formed from, for example, an aluminum-copper (Al-2% Cu) electrode material disposed on a lithium-tantalate (LT) substrate. As seen from the common signal terminals T0, series resonator RS0 forms the first stage of filter F1, and shunt resonator RP0 forms the first stage of filter F2. If necessary, each filter F1, F2 may have additional series resonators and shunt resonators following one another in the same ladder pattern.
Filters F1 and F2 are bandpass filters with respective center frequencies f1 and f2, where f1 is less than f2. The passbands of the two filters F1, F2 must not overlap. Filter F2 must have a high characteristic impedance in the passband of filter F1, and filter F1 must have a high characteristic impedance in the passband of filter F2. In the antenna duplexer in FIG. 26, an extra length of signal line S is inserted in series with filter F2 to increase its lower stopband impedance by producing a phase rotation.
An f1 value of eight hundred eighty-seven megahertz (887 MHz) and an f2 value of nine hundred thirty-two megahertz (932 MHz) are given as examples in the above-mentioned document (5-167388); these are the transmit frequency (f1) and receive frequency (f2) of a type of cordless telephone. When the antenna duplexer is used in this type of cordless telephone, the common terminals T0 are coupled to the antenna, terminals T1 are coupled to a transmitting circuit, and terminals T2 are coupled to a receiving circuit. A cordless telephone has comparatively narrow transmit and receive bands, so the requirement that each filter must have a high stopband impedance in the other filter""s passband is readily met by the simple circuit configuration in FIG. 1.
When this antenna duplexer configuration is used in a mobile communication system such as the Japanese CDMA-One system, in which the transmit frequency is higher than the receive frequency, filter F1 becomes the receive filter and filter F2 becomes the transmit filter. The Japanese CDMA-One system, however, has comparatively wide transmit-band and receive-band specifications; the proportional bandwidth (the bandwidth divided by the center frequency) is equal to 0.042 for the transmit band and 0.045 for the receive band. Moreover, the spacing between the lowest transmit frequency and the highest receive frequency is less than half the passband width. The simple duplexer configuration in FIG. 1 fails to provide the desired combination of low passband insertion loss and high stopband impedance for this system, and for other mobile communication systems with wide, closely spaced transmit and receive bands.
An object of the present invention is to provide an antenna duplexer that combines low insertion loss in both the transmit and receive passbands with an adequately high characteristic impedance in the relevant stopbands (the transmit stopband in which the receive passband is located, and the receive stopband in which the transmit passband is located).
The invented antenna duplexer has a common node, first and second signal terminals, a first filter coupled between the common node and the first signal terminal, a second filter coupled between the common node and the second signal terminal, and an antenna signal terminal coupled to the common node. The first and second filters each have at least one series resonator and at least one shunt resonator coupled in a ladder configuration. The first filter has a higher passband than the second filter.
The antenna duplexer also has a transmission-line circuit with an internal node, a first transmission line coupling the internal node to the common node, a second transmission line coupling the internal node to the first filter, and a grounding circuit coupling the internal node to ground. The grounding circuit comprises, for example a capacitor coupled between the internal node and a ground node.
The grounding circuit increases the stopband impedance of the first filter in the region of the passband of the second filter, and improves impedance matching as seen from the antenna signal terminal.

Antenna duplexer with divided and grounded transmission line


A garbage fermenting apparatus is provided which can process a mixture of fermentative garbage and non-fermentative garbage. The fermentative garbage includes foodstuffs such as vegetables, meats, processed foods, etc. The non-fermentative garbage includes such things as the packages of packaged foods, plastic trays, vinyl, cellophane, chopsticks, etc. Once the fermentative and non-fermentative garbage are processed, the garbage fermenting apparatus automatically divides the processed matter into a fully-matured powder and a non-fermentative matter. The garbage fermenting apparatus includes: a full-maturation tank on the downstream side of the fermentation tank; a first heater attached to an outer face of the tank wall of the fermentation tank; a second heater attached to an outer face of the tank wall of the full-maturation tank; a first impeller which brakes and stirs the fermentative garbage and the non-fermentative garbage in the fermentation tank; a second impeller which stirs the fermentative garbage and the non-fermentative garbage in the full-maturation tank; and a sieve which divides fully-fermentation processed matter into fully-matured powder and non-fermentative matter.

1. Field of the Invention
The present invention generally relates to a garbage fermenting apparatus and more particularly, to a garbage fermenting apparatus which processes both fermentative garbage and non-fermentative garbage in a short period of time and then, divides the processed fermentative garbage and non-fermentative garbage into both a fully-matured powder and a non-fermentative component.
2. Description of the Related Art
In a conventional apparatus wherein excrement of livestock is fermented and discharged from a stock-breeding facility, (such as fish refuse discharged from fish markets and fish stores, vegetable refuse discharged from markets and restaurants, garbage discharged from households, hotels, and supermarkets, and other kinds of waste in a short period of time), the garbage fed into the apparatus is heated by hot air from either a blower or a hot air type heater, and the temperature of the garbage is controlled by changing the amount of air. Some known garbage fermenting apparatuses are also provided with a device for heating charged gas by heat exchange with exhaust gas heated by fermentation heat.
However, in the conventional garbage fermenting apparatuses described above, some items cannot be processed, such as, for example, cellophane, vinyl, plastic trays, food packed with synthetic or plastic materials, and caps of bottled beverages. These non-processable items comprise non-fermentative garbage, which must be removed by human hands prior to the fermentative garbage and non-fermentative garbage being fed into the garbage fermenting apparatuses, so that only fermentative garbage is fed into the apparatuses. The necessity for human labor to remove the non-fermentative garbage is inconvenient. In an apparatus which sends hot air directly into a fermentation tank, a necessary amount of air for heating is more than ten times the amount of air necessary for fermentative microorganisms. Furthermore, those apparatuses which sends hot air directly into a fermentation tank also require vaporization of water and large scale deodorization equipment for the exhaust gas. Although a hot air supply opening is provided at the downstream side of the fermentation tank to improve the heat conduction effect, the change of the amount of air for temperature control clogs the opening, and a stable operation over a long period of time is cannot be achieved.
It is therefore an object of the present invention to provide a garbage fermenting apparatus which processes a mixture of fermentative garbage and non-fermentative garbage, which divides the processed fermentative garbage and non-fermentative garbage into both a fully-matured powder and a non-fermentative matter, after the relatively short fermentation process.
It is also an object of the present invention to provide a garbage fermenting apparatus which has equipment of a relatively small scale and which has long and stable operation.


A method for plasma processing characterized by the steps of disposing a wafer proximate to a cathode within a process chamber, releasing a gas into the chamber, applying R.F. power in the VHF/UHF frequency range to the cathode to form a plasma within the chamber, developing a magnetic field within the chamber having flux lines substantially perpendicular to the surface of the wafer, and varying the strength of the magnetic field until a desired cathode sheath voltage is attained. The apparatus includes a chamber, a wafer-supporting cathode disposed within the chamber, a mechanism for introducing gas into the chamber, an R.F. power source coupled to the cathode operating in the frequency from about 50-800 megahertz, an electromagnetic coil disposed around the chamber adapted to develop a magnetic field within the chamber which is substantially perpendicular to the wafer and a variable output power supply coupled to the coil to vary the magnetic field strength and therefore the cathode sheath voltage within the chamber.

This invention relates generally to the plasma processing of semiconductor wafers and more particularly to methods and apparatus for plasma processing semiconductor wafers in a reactive ion etch mode.
Integrated circuits (ICs) are fabricated on semiconductor wafers by subjecting the wafers to a precise sequence of processes. These processes can include, but are not limited to, epitaxial deposition, lithographic patterning, chemical vapor deposition, sputter deposition, ion implantation and etch processes.
There is a seemingly inexorable trend in the IC industry to produce more powerful integrated circuits by packing ever greater numbers of active and passive devices into each integrated circuit. This is typically accomplished by both reducing the sizes of the devices within an IC and by arranging the devices more closely together.
As IC devices become smaller and more densely packed they also become more susceptible to damage during the aforementioned processing steps. For example, when the minimum feature size (such as a line width) of an IC reaches about 1 micron, the devices of the integrated circuit may be susceptible to damage if exposed to voltage levels over 200 volts. Since it is not unusual for conventional semiconductor processing equipment, such as a reactive ion etch (RIE) system, to develop considerable voltage levels during operation, steps must be taken to prevent damage to the devices of the integrated circuits.
In a reactive ion etch system a process gas is released into a process chamber and a radio-frequency (RF) power source is coupled to a cathode located within the chamber to create a plasma from the process gas. A semiconductor wafer can be supported by the cathode and positive ions formed within the plasma can be accelerated to the surface of the wafer to provide a very anisotropic etch of the wafer's surface. Conventional RIE systems have been operated at a number of frequencies including a low frequency range from about 10-400 kilohertz and a high frequency range from about 13-40 megahertz.
Both ions and electrons within a plasma are accelerated in systems operated in the low frequency range of 10-400 kilohertz creating the risk of potential damage to IC devices caused by the impact of heavy, high-energy ions against the surface of the wafer. In high frequency operation in the 13-40 megahertz range a steady state cathode sheath is formed near the cathode which typically develops a magnitude of over 1000 volts at 1 kilowatt of power. As mentioned previously, voltages of this magnitude can be very damaging to high-density IC circuitry. In contrast, systems operated in the microwave range of about 900 megahertz to 2.5 gigahertz, such as electron cyclotron resonance (ECR) systems, have sheath voltages so low that an auxiliary bias on the cathode is often required to provide commercially useful etch rates.
Of the frequency range choices, the high frequency range of 13-40 megahertz is most often employed in plasma etch systems. By far the most popular choice for an RIE system operating frequency is the ISM (industry, scientific, medical) standard frequency of 13.56 megahertz. However, the potentially damaging sheath voltages of such systems limits their usefulness in performing certain sensitive etch processes, such as a polysilicon over silicon dioxide ("oxide") etch.
The cathode sheath voltage can be reduced by the use of magnetic confinement techniques such as those disclosed in U.S. Pat. No. 4,842,683 entitled "Magnetic Field-Enhanced Plasma Etch Reactor" of Cheng et al. which teaches the use of a rotating magnetic field above the surface of a wafer having magnetic flux lines substantially parallel to the wafer surface. The magnetic field of Cheng et al. decreases the cathode sheath voltage 25-30 percent, i.e. to about 700 volts, while it increases the etch rate by as much as 50 percent.
A problem with a magnetic enhancement system as disclosed by Cheng et al. is that the electric (E) field created within the cathode sheath is substantially perpendicular to the wafer surface and is therefore at substantially perpendicular to the applied magnetic (B) field. The E.times.B force created by the interaction of these two fields causes the well-known electron/ion drift effect, which is a major source of etch non-uniformity in magnetically enhanced RIE systems. The aforementioned rotation of the magnetic field reduces, but does not eliminate, etch non-uniformity by averaging the effects of the electron/ion drift over the surface of the wafer.
Another problem encountered with the system of Cheng et al. is that, even with magnetic confinement, a cathode sheath voltage at about 700 volts is still too large to avoid damaging IC devices during certain types of processes. Unfortunately, since the electron/ion drift is caused by the E.times.B force, raising B to lower the cathode sheath voltage will increase the electron/ion drift effect a corresponding amount. In consequence, the system of Cheng et al. cannot reduce the cathode sheath voltage much below 700 volts by further increasing the B field strength without causing an unacceptably high etch non-uniformity over the surface of the wafer.
One approach to reducing the cathode sheath voltage to acceptably low levels is disclosed in parent application U.S. Ser. No. 07/559,947, filed Jul. 31, 1990, of Collins et al. and entitled "VHF/UHF Reactor System", the disclosure of which is incorporated herein by reference. It is known that the cathode sheath voltage is a function of the RF impedance (Z.sub.RF) of the plasma which is given by the following relationship: EQU Z.sub.RF =R-jx
where R is the resistive component of the plasma impedance and x is the reactive component of the plasma impedance. Therefore, an increase in RF frequency causes a decrease in Z.sub.RF and a consequent reduction in the cathode sheath voltage. Collins et al. teach that operating a RIE system at VHF/UHF frequencies from about 50 megahertz to about 800 megahertz will result in lower cathode sheath voltages resulting in a softer, less damaging etch processes.
While the system of Collins et al. performs very well, it suffers from the drawback that it requires a variable frequency R.F. power supply or multiple frequency R.F. sources which, for the required power and frequencies, are very large and very expensive. Also, their impedance matching network was, to some extent, a compromise over the range of operating frequencies, resulting in less than optimal impedance matching at any one frequency within the range.
In consequence, there was heretobefore an unsatisfied need for a plasma processing system in which the cathode sheath voltage could be controlled both inexpensively and effectively.

Method for plasma processing using magnetically enhanced plasma chemical vapor deposition


Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller is suitable for generating command signals and address signals. The semiconductor device is suitable for electrically disconnecting a first local line from a second local line in response to an input control signal enabled in a read mode. The read mode is set according to a logic combination of the command signals. Further, the semiconductor device is suitable for sensing and amplifying a data on the first local line or the second local line according to the address signals to output the amplified data through an input/output line.

1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices and semiconductor systems including the same.
2. Related Art
Currently known semiconductor devices may execute a write operation to store data therein and, likewise, may execute a read operation to output the data stored therein. To execute the write operation or the read operation, the semiconductor devices may selectively enable a word line using a row address signal to create a row path. Alternatively, the semiconductor devices may activate a switching element, coupled between a sense amplifier and an input/output (I/O) line, using a column selection signal generated by a column address signal. Upon activation of the switching element as described, the semiconductor devices may then create a column path.
Each of the semiconductor devices may be designed to include several input/output ("I/O") lines for outputting data. Further, the devices may also include sense amplifiers that may sense and amplify a voltage difference (ΔV) between a pair of I/O lines selected by a column address signal. The sense amplifiers may then output the data during the read operation.
During the read operation of the semiconductor device, at least one of the I/O lines may be selected by the column address signal while the remaining I/O lines may remain non-selected. In such an instance, a loading capacitance between the selected I/O line and the non-selected I/O lines adjacent thereto may degrade a function of the sense amplifier to increase a data access time of the semiconductor device.

Semiconductor devices and semiconductor systems including the same


A nonvolatile semiconductor memory serving as a semiconductor memory which is capable of erasing data in a batch comprises four banks constituting a storage circuit, a bank control circuit for instructing access to respective banks (writing, reading, etc.), and a status signal output circuit connected to the bank control circuit. The status signal output circuit outputs status signals for instructing access status of respective banks. The status signals are outputted to an external device through a data bus. With such a construction, the access status of respective banks can be easily grasped, so that the data access to the semiconductor memory can be enhanced with efficiency, thereby realizing high speed data processing.

1. Field of the Invention
The invention relates to a semiconductor memory, particularly to a semiconductor memory capable of writing and reading data in units of a predetermined plurality of memory cells.
2. Description of the Related Art
Semiconductor memories include random access memory in which data can be freely read and written, and read only memory which is dedicated for reading previously written data. The read only memory is generally composed of a nonvolatile semiconductor memory. As for the read only memory, there is a memory capable of electrically rewriting data (erasing written data and writing another data). The semiconductor memory includes a memory capable of erasing data in a batch.
As for a memory capable of electrically rewriting data, there is a memory capable of writing and reading data in unit of predetermined plural memory cells (predetermined plural memory cells are defined as banks) relative to a memory cell array composed of plural memory cells incorporated in the memory.
High speed access (reading and writing) has been recently required in a semiconductor memory. To realize a high speed access, a semiconductor memory capable of reading and writing in unit of bank requires access to every bank independently. Particularly, it is required to independently and efficiently access respective banks after confirming access status of respective banks. However, a semiconductor memory satisfying these requirement has not been developed hitherto.
A semiconductor memory has a tendency to include more pins as terminals through which signals are supplied. In a semiconductor memory capable of reading and writing data in unit of bank, it is preferable to avoid the provision of output terminals for signals to instruct access status in order to confirm the access status of respective banks. The reason is that if the number of terminals are increased, a scale of the semiconductor memory is increased, leading to the increase of cost.
It is therefore an object of the invention to provide a semiconductor memory capable of realizing the access to respective banks efficiently and independently upon confirmation of access status of respective banks.
It is another object of the invention to provide a semiconductor memory capable of realizing the access to respective banks efficiently independently without increasing the number of terminal for confirming access status of respective banks.

Semiconductor memory capable of writing and reading data


An organic light emitting display is capable of preventing or reducing a scratch and a short between the wire lines due to the scratch. The organic light emitting display includes a pixel substrate including an organic light emitting element formed on a pixel region and wire lines formed in a surrounding area of the pixel region; and a protrusion formed between the wire lines.

1. Field of the Invention
Aspects of the present invention relate to an organic light emitting display, and more particularly, to an organic light emitting display and a method of manufacturing the same to prevent or reduce a scratch on wire lines thereof.
2. Description of the Related Art
An organic light emitting display is a self-emitting display that uses a phenomenon in which electrons and holes injected into an organic material through an anode and a cathode, respectively, are recombined to form excitons. The excitons thereby generate a light beam with a specific wavelength by releasing energy. The organic light emitting display does not require a separate light source, such as a backlight, resulting in low or lower power consumption. Furthermore, since a wide viewing angle and a fast response time of the organic light emitting display can be easily ensured, the organic light emitting display is expected to be a next generation display.
In terms of a driving method, the organic light emitting display is classified into a passive matrix type and an active matrix type. In recent years, the active matrix type organic light emitting display has become more prevalent over the passive matrix type organic light emitting display. The active matrix type organic light emitting display enables realization of low power consumption, high definition, fast response time, wide viewing angle, and light thin film characteristics.
In an active matrix type organic light emitting display, a pixel region is formed on a pixel substrate so as to display an image. Also, wire lines, and data and scan drivers to operate the pixel region using signals input through pads of the wire lines, are formed in a surrounding area of the pixel region. Pixels in the pixel region, each of which is a basic unit for image display, are arranged in a matrix form, and an organic light emitting element is disposed for each pixel. The organic light emitting element includes a first pixel electrode of a positive polarity and a second pixel electrode of a negative polarity that are sequentially formed with an emitting layer interposed therebetween. The emitting layer includes a red (R), green (G), and/or blue (B) organic material. A thin film transistor (TFT) is in contact with the organic light emitting element so that the each pixel can be separately controlled.
The pixel substrate of the organic light emitting display is sealed by a sealing substrate to protect the pixels. Although the organic light emitting display is sealed, the wire lines and the pads are not sealed in order to be used to input external signals. Accordingly, the wire lines and the pads may be easily damaged by an external physical impact. In particular, a scratch may be produced on the wire lines as shown in FIGS. 5A to 5C to cause a short between the wire lines so that driving of the pixel deteriorates.

Organic light emitting display and method of manufacturing the same


In an embodiment, an image sensor includes an isolation layer disposed in a semiconductor substrate to define a first active region and a second active region extending from the first active region. A photodiode is disposed in a portion of the first active region. A floating diffusion region is provided in the second active region at a position spaced apart from the photodiode. A transfer gate electrode is disposed on the second active region between the photodiode and the floating diffusion region. The transfer gate electrode is disposed to cover both sidewalls and an upper portion of the second active region. The transfer gate electrode has a region extending onto the first active region and overlapping the photodiode. The photodiode has a protrusion into the second active region at the portion adjacent to the transfer gate electrode. A deep n-impurity region of the photodiode extends in the protrusion.

1. Technical Field
The present invention relates to an image sensor and a method of its manufacture, and more particularly, to an image sensor having a 3-dimensional transfer transistor and a method of its manufacture.
2. Discussion of the Related Art
An image sensor is a semiconductor device that converts an optical image into an electric signal. The image sensor can be classified into either a charge coupled device (CCD) type or a complementary metal oxide semiconductor (CMOS) type. The CMOS type image sensor will be referred to as CIS (CMOS image sensor). The CIS includes a plurality of 2-dimensional pixels. The pixels each employ a photodiode (PD), a floating diffusion region (FD), and a transfer transistor (TX). The photodiode PD serves to convert incident light into an electric signal. The transfer transistor TX serves to transfer photocharges collected at the photodiode PD to the floating diffusion region FD. If the photocharges collected at the photodiode PD are not completely transferred to the floating diffusion region FD, there may occur a problem of a degraded display resolution by a phenomenon called an image lag. Thus, it is important that the transfer transistor TX sufficiently transfer the photocharges collected at the photodiode PD to the floating diffusion region FD.
A method of manufacturing such an image sensor has been disclosed in U.S. Patent Publication No. 2003/0173585 A1, Kimura, et al., "Semiconductor device having solid-state image sensor with suppressed variation in impurity concentration distribution within semiconductor substrate and method of manufacturing the same."
FIG. 1 is a cross-sectional view of a pixel portion of the image sensor disclosed in U.S. Patent Publication No. 2003/0173585 A1.
Referring to FIG. 1, a P-well 11 is formed on the semiconductor substrate 10 at a certain depth. An isolation layer 12 is formed to define an active region. A transfer gate structure 15 is disposed across on the active region. The transfer gate structure 15 includes a gate dielectric 13 and a transfer gate electrode 14 on top. A photodiode 18 is disposed in the P well 11 at one side of the transfer gate structure 15. The photodiode 18 has a P-type impurity region 16 and an N-type impurity region 17. A floating diffusion region 19 is disposed in the P well 11 at the other side of the transfer gate structure 15.
For a high integration of the image sensor, the sizes of the photodiode 18 and the transfer gate structure 15 should be reduced as much as possible. However, a drivability of the transfer transistor TX is determined by the length and width of its effective channel. The width of the effective channel is defined by the transfer gate structure 15. That is, for securing the drivability, it is advantageous to enlarge the width of the effective channel defined by the transfer gate structure 15. However, in the publication by Kimura, et al., the transfer gate structure 15 is disposed on the plane on the semiconductor substrate 10. Accordingly, there is a trade-off between the drivability and the reduction of the size of the transfer structure 15.
Using a 3-dimensinal structure transfer transistor may be a solution of the above problem, as we now discuss.
FIG. 2 is a plan view illustrating a part of a pixel portion of an image sensor having a conventional 3-dimensional (3-D) transfer transistor, and FIG. 3 is a cross-sectional view taken along line I-I′ of FIG. 2.
Referring to FIGS. 2 and 3, the image sensor having the conventional 3-D transfer transistor includes, at a certain area of a semiconductor substrate 21, an isolation layer 23 defining a first active region 1 and a second active region 2. The second active region 2 is configured to extend from the first active region 1. A shallow p-impurity region 27 is in a portion of the first active region 1. A deep n-impurity region 25 is below the shallow p-impurity region 27. The shallow p-impurity region 27 and the deep n-impurity region 25 define a photodiode (PD) 29. A floating diffusion region (FD) 39 is in the second active region 2 at a position spaced apart from the photodiode 29. The floating diffusion region 39 is a high concentration n-impurity region. A transfer gate electrode 33 is disposed on the second active region 2 between the photodiode 29 and the floating diffusion region 39. The transfer gate electrode 33 is so disposed across the second active region 2 as to cover the sidewalls 37 of the second active region 2.
The transfer gate electrode 33 has a region that extends onto the first active region 1 and overlap the photodiode 29. In this case, a spaced region d is formed between the sidewalls 37 of the second active region 2 and the photodiode 29. Also, a gate dielectric 31 is interposed between the transfer gate electrode 33 and the active regions 1 and 2. The gate dielectric 31 may further extend to cover the photodiode 29 and the floating diffusion region 39. The deep n-impurity region 25, the transfer gate electrode 33 and the floating diffusion region 39 constitute a transfer transistor TX. In this case, the width of an effective channel of the transfer transistor TX is determined by the upper portion 35 and sidewalls 37 of the second active region 2. That is, the width of the effective channel is enlarged to the extent of a length of the sidewalls 37 of the second active region 2 covered by the transfer gate electrode 33.
If incident light is radiated onto the photodiode 29, the photocharges are concentrated in the deep n-impurity region 25. The quantity of the photocharges concentrated in the deep n-impurity region 25 is determined by the intensity of incident light. Subsequently, when a gate voltage higher than the threshold voltage is applied to the transfer gate electrode 33, an inversion region is formed at the upper portion 35 and sidewalls 37 in the active regions 1 and 2 covered with the transfer gate electrode 33, and the photocharges concentrated in the deep n-impurity region 25 are transferred to the floating diffusion region 39 via the inversion region.
However, if the spaced region d exists, the photocharges concentrated in the deep n-impurity region 25 have difficulty moving toward the sidewalls 37 of the second active region 2. That is, the transfer efficiency of the photocharges is degraded.

Image sensor having 3-dimensional transfer transistor and its method of manufacture


Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel region defined in the body between the first and second source/drain regions. Disposed in at least one of the first and second source/drain regions are a plurality of plugs each formed from a volume-expanded material that transfers compressive stress to the channel region. The compressively strained channel region may be useful, for example, for improving the operating performance of p-channel field effect transistors (PFET's).

Semiconductor devices, such as field effect transistors (FET's), are familiar building blocks of integrated circuits. Field effect transistors are formed from an electrically isolated body of semiconductor material, such as silicon, defined in a semiconductor substrate and include a channel region defined in the semiconductor body between a source region and a drain region. Carrier mobility in the channel region is an important consideration because of its direct influence on device performance. For example, transistor output current and switching performance may be improved by enhancing the carrier mobility in the channel region. One approach for enhancing the carrier mobility is to strain the crystal lattice of the semiconductor material by introducing either compressive stress or tensile stress. The strain resulting from the stress alters the electronic band structure of the constituent semiconductor material. As a result, the in-plane carrier mobility is significantly increased.
Biaxial tensile strain may be induced uniformly across an entire substrate by introducing, between the bodies of semiconductor material and the substrate, an intervening layer of a material having a lattice constant greater than that of the substrate. For example, a body of biaxially strained silicon may be produced by introducing a thin layer of silicon germanium between the substrate and the semiconductor bodies. The tensile strain increases the interatomic spacing of the bodies in the plane of the substrate, which enhances electron mobility in device channel regions of n-channel field effect transistors (NFET's).
Uniaxial compressive strain may be induced locally in a silicon layer by process optimizations. Small amounts of compressive stress may be introduced by manipulating the properties of existing device structures. For example, local strain caused by the thermal expansion mismatch of silicon and shallow-trench isolation has been demonstrated to produce amounts of strain sufficient to alter device characteristics. Greater amounts of compressive stress may be introduced by, for example, depositing a silicon germanium layer only in the source and drain regions of p-channel field effect transistors (PFET's). The local introduction of the silicon germanium layer has the effect of adding compressive strain to the PFET channel region, which locally increases hole mobility.
A limitation on this approach is that such strained devices are notoriously difficult to fabricate. In particular, the use of silicon germanium layers for forming strained silicon has certain disadvantages that prevent large scale integration. Silicon germanium layers tend to introduce defects into the overlying silicon bodies, which reduces device yields. Large scale integration is further limited because it is difficult to make strained NFET's and strained PFET's on a single substrate. For example, a layer of silicon germanium deposited across the wafer is not suitable for optimizing both NFET's and PFET's. Silicon germanium also has poor thermal conductivity. Some dopants diffuse more rapidly through silicon germanium, which may influence diffusion doping profiles in source and drain regions formed in the silicon bodies. Another practical limitation is that the silicon germanium layer contributes to increasing the overall thickness of the device structure, which is being scaled downwardly in modern device designs.
What is needed, therefore, is a method of selectively introducing compressive strain into the channel region of a semiconductor body, and structures, devices and integrated circuits having a compressively strained channel region fabricated by the method.

Strained semiconductor device structures

International Business Machines Corporation


A display apparatus includes a display panel and a backlight assembly including a lamp and an inverter. The inverter includes a main transformer, a main driver and a voltage controller. The main transformer applies a driving alternating current (AC) voltage to the lamp. The main driver generates an output signal controlling the main transformer based on a feedback signal from the main transformer. The voltage controller is electrically connected to a feedback terminal of the main driver to control a maximum level of a voltage applied to the feedback terminal.

1. Field of the Invention
The present invention relates to an inverter, a backlight assembly having the inverter and a display apparatus having the inverter. More particularly, the present invention relates to an inverter used for a display apparatus, a backlight assembly having the inverter and a display apparatus having the inverter.
2. Description of the Related Art
A liquid crystal display ("LCD") apparatus has various characteristics such as light weight, low power consumption and low driving voltage. Thus, the LCD apparatus has been used in various fields, such as in, monitors, notebook computers, mobile phones and large television receiver sets. The LCD apparatus includes an LCD panel displaying images by using optical transmittance of liquid crystals and a backlight assembly disposed under the LCD panel to provide the LCD panel with light.
The backlight assembly includes lamps disposed substantially parallel with each other and an inverter applying driving power to the lamps. The lamps may include cold cathode fluorescent lamps ("CCFLs") having a rod shape.
The CCFLs require excessive power to generate light during an initial driving period. That is, the inverter applies the excessive power to the CCFLs during the initial driving period. The CCFLs consume more power during the initial driving period than a normal driving period. The initial driving period is usually called a power overshoot period.
As a result, the power consumption of the initial driving period is excessively higher than that of the normal driving period, so that the amount of the power applied to the lamps using the inverter is restricted.

Inverter, backlight assembly having the same and display apparatus having the same