In accordance with the present invention there is provided a surgical device for joining a first and a second vessel together and creating a passageway therebetween. The device includes an implement which has proximal and distal ends and a longitudinal axis extending therebetween. The implement has a bottom member and a top member which are substantially coextensive. The top and bottom members are pivoted together at the proximal end so that a wall of each of the first and second vessels can be held between the top and bottom portions. The device includes a mechanism for joining the first and second vessels together along two joining lines which are substantially parallel to each other and to the longitudinal axis of the implement. The lines have distal and proximal ends. The device further includes a blade for severing the first and second vessels between the joining lines so as to create a passageway through the vessels. The blade operates such that it is able to cut the vessels along a cut line which has a proximal end that is distal to the proximal ends of the joining lines, and a distal end that is proximal to the distal ends of the joining lines.

Creating an anastomosis, or the surgical formation of a passage between two normally distinct vessels, is a critical step of many surgical procedures. This is particularly true for coronary artery bypass graft (CABG) procedures in which one or more graft vessels are joined to the coronary arteries distal to the diseased portion in order to improve the blood supply to the myocardium (heart muscle). The graft vessels typically used are the saphenous vein of the leg or the radial artery of the arm. Also, the internal mammary (IMA) artery is commonly rerouted from its original position and attached to the lower anterior descending coronary artery (LAD) to restore blood flow to the left ventricle of the heart. When using harvested vessels, an anastomosis must be performed on both the proximal and distal ends of the graft vessel. For the case using the IMA, the anastomosis is made only at the distal end, or pedicle, of the IMA.
Currently the method of hand suturing the vascular anastomosis during a CABG is preferred by surgeons. The suturing method, however, is very time consuming, requiring several minutes per anastomosis even for an experienced surgeon. In some cases the blood flow in the newly joined vessels may be poor or there may be leaks, and the surgeon must remove the stitches and repeat the suturing procedure. In surgical procedures involving multiple bypass grafts, the time accumulated for doing the suturing is very substantial, putting the patient at risk and increasing the cost of the surgical procedure. Hand suturing also requires a high level of skill and is not easily mastered by many surgeons. It is especially difficult to suture if the anastomosis site is not easily accessed or viewed.
In the CABG procedure, access to the heart is obtained via a median stemotomy in which the rib cage is split longitudinally on the midline of the chest, and the left and right rib cages are spread apart. This method allows very good access to the heart but is very traumatic to the patient, and a lengthy recovery time (1-2 weeks) in the hospital is required. More recently, a cardiac procedure known as MIDCAB (Minimally Invasive Direct Coronary Artery Bypass) using a small, left thoracotomy (incision between the ribs on the left chest) directly above the heart has become more widely used to reduce the patient's pain and recovery time. In this procedure, however, the surgical access to the heart and visibility of it are significantly reduced, and hand suturing may be more difficult than when using a median sternotomy.
A number of devices for augmentation of the suturing techniques for vascular anastomosis have been developed. These devices attempt, with varying degrees of success, to reduce the difficulty in repeatedly passing a needle and thread through the blood vessel walls. Recent examples are found in U.S. Pat. No. 5,571,090 issued to Sherts on Nov. 5, 1996, U.S. Pat. No. 4,803,984 issued to Narayanan on Feb. 14, 1989, and U.S. Pat. No. 5,545,148 issued to Wurster on Aug. 13, 1996. In Sherts and Narayanan, the individual stitches must still be made one at a time and, therefore, the procedure is still time consuming. In addition, the working ends of the Wurster and Sherts devices appear to obstruct the view of the needle tip, and so precise placement of the stitch might be difficult in some situations.
Devices incorporating rings or fittings have been tried for end-to-side anastomosis. Examples are U.S. Pat. No. 4,366,819 issued to Kaster on Jan. 4, 1983 and U.S. Pat. No. 4,657,019 issued to Walsh, et al, on Apr. 14, 1987. These devices have several disadvantages and, therefore, have not become widely used by surgeons. The devices incorporate small, separate parts which must be manipulated into the blood vessels using special tools and techniques. The steps for assembly of such devices to the blood vessels may become more difficult as less surgically invasive procedures are used. In addition, the necessary manipulation of the vessels traumatize the delicate vessel walls, thus jeopardizing the ability of the vessels to heal properly. The presence of a portion of a ring or fitting in the blood stream may also inhibit the formation of a smooth, endothelial lining on the inner wall of the vessels.
Surgical staplers have been widely used by surgeons for many surgical procedures. Circular staplers and linear stapling and cutting instruments are well known in the art for the anastomosis of bowel tissue, but have not yet been made available to surgeons in miniature versions suitable for vascular anastomosis. Circular staplers are used primarily for end-to-end anastomosis of bowel tissue. For coronary procedures, the end-to-end type of anastomosis is not preferred because it requires the coronary artery to be completely severed from its original blood supply to be joined to the graft vessel. This could only be used in relatively infrequent cases when the coronary artery is completely occluded proximal to the location for the anastomosis. Circular staplers also have been used for the end-to-side type of anastomosis on large organs such as bowel. A key disadvantage of a circular stapler for this application is that one hollow organ must be joined to the side of the other hollow organ at about a 90 degree angle. In vascular anastomosis, it is often desirable to join the graft vessel to the target vessel at an acute angle to facilitate laminar blood flow through the joined vessels, or to avoid kinking of the graft vessel. Also, the size of the passageway between the joined vessels is limited by the diameter of the graft vessel. For a side-to-side anastomosis, the passageway size can be made to very large relative to the vessel diameters by choosing the appropriate length of staple joining lines.
In the PCT application WO 97/16122 filed by Rygaard on Oct. 31, 1995, an instrument and method is shown for using a miniature, circular stapler in an end-to-side anastomosis of blood vessels. However, this device still requires substantial manipulation of the vessels as the device is assembled together and operated. This is often difficult to do with very limited access to the surgical site, and also could lead to the inability of the vessels to heal together properly. In addition, visualization of the vessels at the anastomosis while using this device is significantly obstructed by the distal end of the device.
Linear stapling and cutting instruments, usually referred to as linear cutters (see, for example, U.S. Pat. No. 5,465,895, issued to Knodel, et al, on Nov. 14, 1995 and which is hereby incorporated herein by reference) are primarily used to hemostatically transect tissues to be removed from the body, but may also be used to anastomose organs side-to-side. Such devices have proven to be time-saving, reliable, and relatively easy to use by surgeons. The current stapling devices, however, are not designed to be made into miniaturized versions that would allow them to be useful for vascular anastomosis, and, as is discussed below, there are difficulties in making miniaturized versions.
A linear cutter has two forks forming an implement on the distal end of the instrument. One fork is a metal channel adapted to receive a staple cartridge. The cartridge contains numerous surgical staples aligned longitudinally into a number (usually four or six) of rows. The other fork is a metallic anvil containing an equal number of pockets, one for each staple. When tissue is clamped between the two forks, a drive member actuated on the handle, pushes a number of wedges (usually 2) in the distal direction. The wedges bear against cam surfaces on a number of drivers within the staple cartridge, causing the drivers to push the staples out of the cartridge, through the tissue, and into the staple pockets on the anvil. As each staple is completely emitted from the cartridge, the staple forms in the anvil staple pocket, thus clinching the tissue held therebetween. As a drive member pushes the wedge in the distal direction, it also pushes a knife which is slightly proximal to the wedge. The knife cuts through all the tissue held in the forks except for at the distal most end where it stops at a location just proximal to the end of the staple lines. Then the wedges and knife are returned to their starting location either manually or by a spring return mechanism within the handle of the instrument.
When using a conventional linear cutter for creating a side-to-side anastomosis of large organs, the severed end of a first hollow organ (such as a portion of the small intestine) is placed over the anvil. Next the severed end of a second hollow organ (such as another portion of the small intestine) is placed over the staple cartridge channel. The tissue is clamped together, stapled and cut. This must then be followed by a second application of the device perpendicular to the first application in order to close the open ends of the two joined organs. The result is a passage between the two joined organs. In time, the tissues grow together, given an adequate blood supply. As the joined organs heal together, the passage between the organs straightens. More detailed descriptions along with illustrations showing the use of linear cutting staplers for side-to-side anastomosis of bowel, as well as other procedures, can be found in the Atlas of Abdominal Surgery, Braasch, et al, Chapter 10, published by W. B. Saunders Co., 1991.
Prior art linear cutters, however, are not practical for use on small blood vessels. In addition to the problems of attempting to manufacture components based on designs simply scaled down from the prior art linear cutters, there would be other difficulties with using prior art linear cutters for small vessel anastomosis. When a conventional linear cutter is used on tissue, the knife cuts through all the tissue clamped between the forks up to a location just proximal to the distal end of the staple line, severing the joined organs at their open ends where the forks are inserted. Therefore, instead of creating a closed loop passageway between the sides of the organs, an open, V-shaped passageway is created. This could cause a number of difficulties and problems when creating anastomosis in very delicate vessels such as the coronary artery.
Regardless of the above, linear cutters are simple, effective and easy to use surgical devices. Therefore there has been a desire for a linear cutter which can provide anastomosis of very small hollow organs such as blood vessels, but which overcomes the above mentioned problems. Such a device should allow the creation of a passage between the vessels in one step, after preparation of the vessels, and that the passage have an unbroken, flexible circumference. It is further desirable that the device require minimal manipulation of the blood vessels. It is also desirable to provide a device which creates the anastomosis without exposing blood flow to a significant amount of foreign material and allows rapid healing of the endothelial lining inside the blood vessels. Further, it is desirable to have such a device which is adapted to be used in traditional open cardiac procedures (CABG), minimally invasive procedures such as MIDCAB, and also adaptable to endoscopic procedures. The present invention provides such a device.


A retainer for constraining slidable movement of a sleeve along a shaft between open and closed positions. An end cap is fixed on the sleeve's rearward end, forming a recess between the sleeve's rearward end and the end cap. The retainer is slidable in and along the sleeve. A pair of flexible, transversely opposed ribs are provided at the retainer's rearward end. A lug projects outwardly from each rib's rearward end. A spring normally biases the ribs outwardly, biasing the lugs into the recess when the sleeve is closed to retain the sleeve in the closed position. When the sleeve is closed, application of a force to move the end cap rearwardly away from the shaft compresses the lugs inwardly, compressing the ribs against the spring and overcoming the spring's outward bias, such that the lugs circumscribe a reduced circumference permitting slidable movement of the lugs through the sleeve.

FIGS. 1, 2 and 3 depict a prior art battery-powered screwdriver 10 having a bit holding cartridge 12. Screwdriver 10 has a casing 14 within which a compartment 16 is formed for containing battery 17 (shown schematically only in FIGS. 2 and 3). Battery 17 powers motor 18 (shown schematically only in FIGS. 1 and 2) when rocker switch 20 is actuated, rotating shaft 22 about its longitudinal axis. Shaft 22 is drivingly coupled to motor 18 by a gearing mechanism (not shown) within forward compartment 24. A hexagonal cross-section tool bit holding chuck 26 is provided in the open forward end of shaft 22 for removably and lockably receiving any one of a number of different (preferably double-ended) screwdriver type tool bits 27 (FIGS. 1 and 3), or an assortment of drill type tool bits 27A (FIG. 2) removably stored on cartridge 12. The external surface of casing 14 defines a handle for grasping screwdriver 10.
The end of casing 14 opposite shaft 22 is extended rearwardly (i.e. to the right, as viewed in FIGS. 2 and 3) to define a bit holder storage compartment 28 rearwardly of battery storage compartment 16. A pair of opposed flanges 30, 32 are formed to extend circumferentially around the inner cylindrical surface of casing 14, rearwardly of battery storage compartment 16. Flanges 30, 32 are spaced apart to define a circumferential groove 34 for fixedly retaining the circular rim of base 36 of support shaft 38. As best seen in FIGS. 2 and 3, base 36 is flared radially inwardly and rearwardly to define an anchor flange portion 40 at the juncture of base 36 and shaft 38.
A cylindrically apertured sleeve 42 is formed on the central rearward face of support collar 44 and extends rearwardly therefrom. Stop shoulder 46 on support collar 44 circumferentially surrounds shaft 38 for slidable, longitudinal movement of sleeve 42 and collar 44 forwardly or rearwardly along shaft 38 between the closed and open positions respectively shown in FIGS. 2 and 3. The circumferential outward rim of collar 44 is flanged to bear against the inner cylindrical surface of compartment 28 thereby stabilizing cartridge 12 and preventing wobbling of sleeve 42 during slidable movement thereof along shaft 38.
An inwardly flexible retainer 47 is fixed on the rearward end 49 of shaft 38. This can be accomplished, as shown in FIG. 2, by providing external threading 48 on rearward end 49 of shaft 38 and screwing an internally threaded portion (not shown) of retainer 47 onto the threaded shaft end. Alternatively, as shown in FIG. 3, a spring-biased type clip 50 can be provided on the forward end of retainer 47 for snap-fit engagement within a mating flanged portion 51 formed within the rearward end of shaft 38.
Retainer 47 is formed with a plurality of flexible, radially spaced segments 52 separated by slots 54. When bit cartridge 12 is in the closed position shown in FIG. 2, segments 52 flex radially outwardly, forcing the outwardly protruding circumferential ridged portions 56 of segments 52 into snap-fit engagement within radially outwardly enlarged circumferential recess 58 provided between the rearward end of sleeve 42 and the central, forward face of end cap 60 to firmly retain cartridge 12 in the closed position. The forward end of retainer 47 protrudes radially outwardly around the rearward end of shaft 38, thereby serving as an end stop to limit rearward travel of sleeve 42 on shaft 38 when stop shoulder 46 contacts the forward end of retainer 47.
A cylindrically apertured collar 62 is formed around the central, forward face of cap 60. The circumferential inward surface of collar 62 is securely circumferentially bonded to the rearward end of sleeve 42. To move bit cartridge 12 into the open position shown in FIG. 3, the user grasps end cap 60 and draws it longitudinally away from screwdriver 10 (i.e. by pulling end cap 60 to the right, as viewed in FIG. 2). The force so exerted compresses segments 52 of retainer 47 radially inwardly within recess 58, such that ridges 56 circumscribe a reduced circumference capable of passage through the cylindrically apertured portion of sleeve 42, as sleeve 42 is slidably drawn along shaft 38 into the fully open position shown in FIG. 3.
A second collar 64 is formed around the central, forward face of cap 60 circumferentially surrounding collar 62. The forwardly protruding portion of collar 64 is received within the rearward circumferential end of casing 14 when bit cartridge 12 is in the closed position, as shown in FIG. 2.
A plurality of flexible bit holding clips 66 are spaced radially and fixed around the central outer circumference of sleeve 42. One bit can be press fitted and thus removably retained between each opposed pair of clips 66 to removably retain the bit. A plurality of different bits can be similarly removably retained by utilizing all of the available pairs of clips 66 on bit cartridge 12. When cartridge 12 is in the open position shown in FIG. 3, it can easily be rotated with respect to shaft 38, thereby allowing the user to easily inspect all of the bits removably stored on cartridge 12 and select a particular bit. The selected bit can be removed by pulling it outwardly away from the clips 66 which retain it. End cap 60 is then pressed toward screwdriver 10 to slidably replace cartridge 12 within bit storage compartment 28 in the closed position shown in FIG. 2.
Persons skilled in the art will understand that bit cartridge 12, retainer 47 and cap 60 are readily adapted to use with manually operated screwdrivers, for example as disclosed in U.S. Pat. No. 5,265,504.
Retainer 47 is typically formed of plastic or other suitable flexible material. It can be difficult to achieve uniform resilience in multiple batches of retainer 47 for high volume production of screwdriver 10. If different specimens of retainer 47 have different resilience then the operating characteristics of different screwdrivers incorporating those different retainers may be affected. For example, the snap-fit engagement of segments 52 within recess 58 may be relatively tight in one screwdriver, and relatively loose in another screwdriver. Extra effort may be required to move cartridge 12 between its open and closed positions in the case of relatively tight snap-fit engagement of segments 52 within recess 58, whereas cartridge 12 may be insufficiently retained in the closed position in the case of relatively loose snap-fit engagement of segments 52 within recess 58.
The resilience of retainer 47 may also vary over time. For example, when bit cartridge 12 is in the open position retainer 47's segments 52 are compressed within the cylindrically apertured portion of sleeve 42. If cartridge 12 is left open more than several hours, then the capability of segments 52 to flex radially outwardly into snap-fit engagement within recess 58 may be degraded, weakening such engagement and preventing retainer 47 from retaining cartridge 12 in its closed position, thus permitting undesirable slippage of cartridge 12 from the closed position toward the open position. Consequently, it is impractical to display screwdriver 10 for sale in transparent packaging with cartridge 12 in its open position. Such display is however desirable, because it lets prospective purchasers see cartridge 12 and any bits stored therein. The resilience of retainer 47 may also vary with temperature.
This disclosure addresses the shortcomings of retainer 47. The foregoing examples of the related art and limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.


Error-free data transfer between mesochronous clock domains can be accomplished by writing data to and reading data from a plurality of data storage elements in coordinated fashion. Write operations are controlled by execution of a state sequence synchronously with the source clock domain, and read operations are controlled by execution of the same state sequence synchronously with the destination clock domain. The states respectively correspond to the data storage elements, and the read and write executions of the state sequence do not simultaneously assume the same state.

Data is commonly transferred between mesochronous domains where the phase relationship between the synchronizing clocks of the two domains is arbitrary. This situation is illustrated in FIG. 1. The sending and receiving blocks (e.g., logic/data processing blocks) are said to be mesochronous if their synchronizing clocks have the same frequency but have an arbitrary phase relationship. This is typically the case if both clocks are generated from the same source such as an on-chip phase-locked loop (PLL).
The elements that actually transfer data are typically flip-flops, also known as registers. When data is transferred between two registers operating with the same synchronizing clock, it is fairly simple to comply with the set-up-and-hold time requirement for latching in data. This is due to the fact that data and clock propagation delays are typically known apriori and it is possible to compensate for these delays. On the other hand, when data is transferred between two mesochronous blocks as in FIG. 1, it is not possible to assume that the set-up-and-hold time requirement is satisfied. If the receiving block latches in the data without proper timing, error-free operation cannot be guaranteed.
In order to guarantee error-free data propagation, the incoming data must be transferred or "shifted" from the sending clock phase to the receiving clock phase. This point is illustrated in FIG. 2, wherein the synchronizing clock for the sending block is referred to as Pclk, and the synchronizing clock of the receiving block is referred to as Txclk. FIG. 2 shows a stream of random data, DataIn, which is synchronous with Pclk and is provided at the sending block output. On the other hand, DataIn has an arbitrary phase relationship to Txclk. This arbitrary phase relationship can result in bit errors as the data crosses the clock domain boundary between the sending and receiving blocks.
It is therefore desirable to provide for error-free data transfer across a clock domain boundary between first and second mesochronous clock domains.

Method and apparatus for data transfer between mesochronous clock domains


A solid-state image pickup device has a first substrate and a second substrate in which circuit elements constituting pixels are arranged. The pixel includes: a pixel section that includes a photoelectric conversion element; a ground potential controller that switches a potential to which a circuit element included in the pixel section is grounded; and a reading section that outputs a signal corresponding to the signal charge as a pixel signal output by the pixel. The pixel section includes: the photoelectric conversion element; an amplification transistor that outputs an amplification signal amplified according to the signal charge generated by the photoelectric conversion element; and a switch circuit that switches a ground of the amplification transistor according to a first output mode and a second output mode. The ground potential controller supplies a first potential in the first output mode and supplies a second potential in the second output mode.

Field of the Invention
The present invention relates to a solid-state image pickup device.
Description of the Related Art
In recent years, in an image pickup device for digital still cameras, digital video cameras, endoscopes, surveillance cameras, or vehicle-mounted cameras, a high quality image that is achieved through both of acquisition of a high-sensitivity image of a dark place or subject in a screen, and acquisition of an image in which pixel saturation of a bright place or subject is suppressed is required. Therefore, in a solid-state image pickup device mounted on an image pickup apparatus, realization of a high S/N (Signal/Noise) ratio and a wide dynamic range is required.
As the solid-state image pickup device mounted on the image pickup device, there is a CMOS (Complementary Metal Oxide Semiconductor) type solid-state image pickup device (hereinafter referred to as a "CMOS image sensor"). In general, in the CMOS image-sensor, a pixel configured of four transistors that includes an amplification circuit is used. A configuration of the pixel of the CMOS image sensor is a configuration for realizing reduction of noise in an image of a dark place or subject, that is, a high S/N ratio. FIGS. 11A and 11B illustrate an example of a schematic structure and a driving timing of a pixel included in a conventional CMOS image sensor. In the following description, the pixel configured of four transistors that includes an amplification circuit as illustrated in FIG. 11A is referred to as a "4-transistor APS pixel."
The 4-transistor APS pixel 7 illustrated in FIG. 11A includes a photodiode PD that is a photoelectric conversion element, a transfer transistor MTX that transfers signal charge generated by the photodiode PD, a floating diffusion layer FD that accumulates the transferred signal charge, a reset transistor MRST that resets the transferred signal charge, an amplification transistor MA that amplifies the transferred signal charge, and a pixel selection transistor MRS for selecting the 4-transistor APS pixel 7. While the floating diffusion layer FD is a capacitor associated with a node connected to a gate terminal of the amplification transistor MA, the floating diffusion layer FD is indicated by a symbol of a capacitor so as to clearly express the floating diffusion layer FD in the schematic configuration of the 4-transistor AFS pixel 7 illustrated in FIG. 11A.
The 4-transistor APS pixel 7 outputs a reset signal when reset, and a pixel signal corresponding to signal charge generated through photoelectric conversion of incident light by the photodiode PD to a pixel output signal terminal OUT. In this case, a signal amplified by a source follower circuit, which includes the amplification transistor MA and a constant current source ICOL provided in a vertical signal line COL, is output to the pixel output signal terminal OUT.
Here, the driving timing of the 4-transistor APS pixel 7 will be described with reference to FIG. 11B. First, at time t1, a pixel reset signal RST becomes at a "High" level such that a reset transistor MRST becomes in an ON state. Accordingly, the floating diffusion layer FD is reset, and a potential of the floating diffusion layer FD becomes at a potential that is reduced by a threshold voltage of the reset transistor MRST from a power supply VDD. Further, a pixel selection signal RS becomes at a "High" level such that the pixel selection transistor MRS becomes in an ON state. Accordingly, the potential of the pixel output signal terminal OUT becomes a potential close to the power supply VDD corresponding to the potential of the floating diffusion layer FD.
Subsequently, at time t2, the pixel reset signal RST becomes at a "Low" level such that the reset transistor MRST becomes in an OFF state, and an operation of resetting the floating diffusion layer FD to a potential of the power supply VDD ends. A period in which the potential of the pixel output signal terminal OUT is stabilized to the reset potential (a period to time t3 in FIG. 11B) starts. During the period in which the potential of the pixel output signal terminal OUT is stabilized to the reset potential, the potential of the pixel output signal terminal OUT decreases by a reset noise component of the 4-transistor APS pixel 7 and is stabilized to a potential of a reset potential VOUT(R7). The reset potential VOUT(R7) is a potential decreased by the amount of the noise generated by the 4-transistor APS pixel 7 in comparison with the potential of the power supply VDD.
Subsequently, at time t3, a pixel transfer signal TX becomes at a "High" level such that the transfer transistor MTX becomes in an ON state, and transfers the signal charge generated by the photodiode PD to the floating diffusion layer FD. Accordingly, the potential of the floating diffusion layer FD becomes at a potential corresponding to the signal charge generated by the photodiode PD due to exposure. In this case, since the pixel selection signal RS is at a "High" level, the potential of the pixel output signal terminal OUT decreases by the amount of charge corresponding to the signal charge transferred to the floating diffusion layer FD.
Subsequently, at time t4, the pixel transfer signal TX becomes at a "Low" level such that the transfer transistor MTX becomes in an OFF state, and an operation of transferring the signal charge generated by the photodiode FD to the floating diffusion layer FD ends. A period in which the potential of the pixel output signal terminal OUT is stabilized to the signal potential (a period, to time t5 in FIG. 11B) starts. During the period in which the potential of the pixel output signal terminal OUT is stabilized to a signal potential the potential of the pixel output signal terminal OUT decreases under an influence when the transfer transistor MTX is OFF, and is stabilized to the potential of the signal potential VOUT(S7). The signal potential VOUT(S7) is a potential that depends on parasitic capacitance or the like due to a transfer path for each signal.
Subsequently, at time t5, the pixel selection signal RS becomes at a "Low" level such that the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT becomes a potential which does not depend on the potential of the floating diffusion layer FD.
Thus, the 4-transistor APS pixel 7 outputs the reset signal at the reset potential VOUT(R7) when reset, and the pixel signal at the signal potential VOUT(S7) corresponding to the signal charge generated through photoelectric conversion of incident light by the photodiode PD to the pixel output signal terminal OUT.
Here, a conversion gain of the signal charge generated by the photodiode PD transferred to the floating diffusion layer FD at time t3 will be described. When the pixel transfer signal TX is set to a "High" level such that the transfer transistor MTX becomes in an ON state, the signal charge generated by the photodiode PD is transferred to the floating diffusion layer FD based on a slope of a potential provided in advance. As a result, the potential in the floating diffusion layer FD changes according to Equation (1) below.ΔVFD=QFD/CFD=qNph/CFD  (1)
In Equation (1) above, ΔVFD indicated the amount of variation in the potential in the floating diffusion layer FD. QPD indicates the signal charge generated by the photodiode PD, CFD indicates capacitance of the floating diffusion laser FD, q indicates elementary charge 1.6×10−19[C], and Nph indicates the number of signal charges generated by the photodiode PD.
From Equation (1) above, a conversion gain C. G. which can be defined as voltage variation with respect to one charge can be represented by Equation (2) below.C. G.=qNph/CFD·1/Nph=q/CFD×1/CFD  (2)
It can be seen from Equation (2) above that the conversion gain C. G. is inversely proportional to the capacitance CFD of the floating diffusion layer FD. Therefore, in the CMOS image sensor, it is possible to realize a high S/N ratio by fabricating the floating diffusion layer FD with small capacitance CFD, and to acquire a high-sensitivity image even in photographing a dark place or subject using the image pickup device.
However, the CMOS image sensor is different from a CCD (Charge Coupled Device) solid-state image pickup device that is one solid-state image pickup device mounted on an image pickup apparatus, and an operation at a low supply voltage also is one characteristic. In general, 3 to 3.3 [V] are used as a power supply voltage of the CMOS image sensor.
However, the power supply voltage of the CMOS image sensor of 3 to 3.3 [V] limits a voltage range that can be used for the floating diffusion layer FD. Further, in order to smoothly transfer the signal charge from the photodiode FD to the floating diffusion layer FD even in a short time, a certain potential difference is required between the potential of the photodiode PD and the potential of the floating diffusion layer FD, but since the supply voltage of the CMOS image sensor is low, an upper limit of the amount of variation ΔVFD in the potential in the floating diffusion layer FD is limited. Since the amount of variation ΔVFD of the potential in the floating diffusion layer FD is an element for determining a saturation characteristic of the pixel, the amount of variation affects the wide dynamic range of the CMOS image sensor.
Therefore, in the conventional CMOS image sensor, there is a trade-off relationship between the capacitance CFD of the floating diffusion layer FD and the number Nph of signal charges generated by the photodiode FD. For example, when the capacitance CFD of the floating diffusion layer FD decreases in order to realize a high S/N ratio of the CMOS image sensor, the conversion gain C. G is improved and high, sensitivity is achieved, but the number Nph of signal charges generated by the photodiode FD that can be stored in the floating diffusion layer FD is reduced in proportion to the capacitance CFD of the floating diffusion layer FD, and the pixel is saturated with a small number Nph of signal charges. Conversely when the capacitance CFD of the floating diffusion layer FD increases in order to realize a wide dynamic range of the CMOS image sensor, a large manner Nph of signal charges are used and the pixel is saturated, but since the conversion gain C. G. is reduced in inverse proportion to the capacitance CFD of the floating diffusion layer FD, the sensitivity is degraded.
Therefore, in the conventional CMOS image sensor including the 4-transistor APS pixel 7 having the configuration illustrated in FIG. 11A, it is not possible to achieve both of a high S/N ratio and a wide dynamic range and to realize an image pickup device in which both of acquisition of a high-sensitivity image in photography in a dark place and acquisition of a high-quality image in which the saturation of the pixel in photography in a bright place is suppressed are achieved. Therefore, in the conventional CMOS image sensor, performance compromised to some extent so as to balance the S/N ratio and the dynamic range is only obtained.
As a technology for solving such problems, for example, "A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor," by Jungwook Yang, et al., ISSCC Dig. Tech. Papers, February 2006 (hereinafter referred to as Non-Patent Literature 1) discloses a configuration of a pixel that can achieve both a high S/N ratio and a wide dynamic range, FIGS. 12A, 12B, and 12C are diagrams illustrating an example of a schematic configuration and a driving timing of the pixel included in a conventional CMOS image sensor, which is disclosed in Non-Patent literature 1. in the following description, the pixel having the configuration as illustrated in FIG. 12A is referred to as a "low-noise flexible pixel." In FIG. 12A, the same components as those of the 4-transistor APS pixel 7 illustrated in FIG. 11A are denoted with the same reference numerals.
The low-noise flexible pixel 8 illustrated in FIG. 12A includes a photodiode PD, a floating diffusion layer FD, a reset transistor MRST, an amplification transistor MA, a pixel selection transistor MRS, and a feedback capacitor CFB. While the floating diffusion layer FD is a capacitor associated with a node connected to agate terminal of the amplification transistor MA, the floating diffusion layer FD is indicated by a symbol of a capacitor so as to clearly express the floating diffusion layer FD in the schematic configuration of the low-noise flexible pixel 8 illustrated in FIG. 12A.
The low-noise flexible pixel 8 is a pixel that does not include the transfer transistor MTX included in the 4-transistor APS pixel 7 illustrated in FIG. 11A, that is, is based on a pixel including three transistors. Since the pixel including three transistors can deal with more signal charges, the pixel has a configuration For suppressing the saturation of the pixel, that is, realizing a wide dynamic range on the assumption that a bright place or subject is photographed by the image pickup device. However, since a conversion gain C. G. of the pixel including three transistors is inversely proportional to the capacitance of the photodiode PD that is generally greater than the capacitance of the floating diffusion layer FD, there is a problem in which the sensitivity is degraded. Therefore, in the low-noise flexible pixel 8, by including two types of amplification, modes (reading modes), both of a wide dynamic range and a high S/N ratio are achieved.
Here, driving timings in respective reading modes in a low-noise flexible pixel 8 will be described with reference to FIGS. 12B and 12C. Source follower reading (drain-grounded reading) for realizing a wide dynamic range illustrated in FIG. 12B will first be described. In the source follower reading, first, at time t1, the switch S1 is in an ON state (at a "High" level), the switch S2 becomes in an OFF state (at a "Low" level), the constant current source ICOL1 becomes in an OFF state, and the constant current source ICOL2 becomes in an ON state. Accordingly, the potential of the vertical signal line COL1 (the potential of the pixel output signal terminal OUT1) becomes a ground potential VOUT(V1) of the potential V1.
Subsequently at time t2, the pixel selection signal RS becomes at a "High" level, and accordingly, the pixel selection transistor MRS becomes in an ON state. Accordingly, a drain terminal of the amplification transistor MA is grounded to the ground potential VOUT1(V1), and the amplification transistor MA and the constant current source ICOL2 provided in the vertical signal line COL2 constitute a source follower circuit. A pixel signal of a signal potential VOUT2(S8) corresponding to the signal charge (potential of the Foaling diffusion layer FD) generated by the photodiode PD, which is input to the gate terminal of the amplification transistor MA, is output to a pixel output signal terminal OUT2.
Subsequently, at time t3, the pixel reset signal RST becomes at a "High" level and accordingly, the reset transistor MRST becomes in an ON state. Accordingly, the potential (potential of the floating diffusion layer FD) of the gate terminal of the amplification transistor MA is reset, and a reset signal of the reset potential VOUT2 (R8) when the low-noise flexible pixel 8 is reset is output to the pixel output signal terminal OUT2.
Subsequently, at time t4, the pixel reset signal RST becomes at a "Low" level, and accordingly, the reset transistor MRST becomes in an OFF state. The pixel selection signal RS becomes at a "Low" level, and the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT2 becomes a potential that does not depend on the potential (potential of the floating diffusion layer FD) of the gate terminal of the amplification transistor MA.
Subsequently, at time t5, the switch S1 becomes in an OFF state (at a "Low" level), and source follower reading in the low-noise flexible pixel 8 (drain-grounded reading) ends.
Next, common source reading (source-grounded reading) for realizing a high S/N ratio illustrated in FIG. 12C will be described. In the common source reading, first, at time t1, the switch S1 is in an OFF state (at a "Low" level), the switch S2 becomes in an ON state (at a "High" level), the constant current source ICOL1 becomes in an ON state, and the constant current source ICOL2 becomes in an OFF state. Accordingly, the potential of the vertical signal line COL2 (the potential of the pixel output signal terminal OUT2) becomes the ground potential VOUT2 (V2) of the potential V2.
Subsequently, at time t2, the pixel selection signal RS becomes at a "High" level, and accordingly, the pixel selection transistor MRS becomes in the ON state. Accordingly, the amplification transistor MA and the feedback capacitor CFB constitute a charge amplifier circuit. This charge amplifier circuit is an inversion amplification circuit having an amplification factor corresponding to a capacitance ratio between the feedback capacitor CFB and the capacitance CFD of the floating diffusion layer. The potential of the potential V2 is a potential required for operating the charge amplifier circuit and corresponds to a potential tor depleting the photodiode PD. A pixel signal of a signal potential VOUT1(S8) corresponding to the signal charge (potential of the floating diffusion layer FD) generated by the photodiode PD, which is amplified by the charge amplifier circuit, is output to the pixel output signal terminal OUT1.
Subsequently, at time t3, the pixel reset signal RST becomes at a "High" level, and accordingly, the reset transistor MRST becomes in the ON state. Accordingly, the signal charge generated by the photodiode PD (the potential of the floating diffusion layer FD) is reset, and a reset signal of a reset potential VOUT1(R8) when the low-noise flexible pixel 8 is reset is output to the pixel output signal terminal OUT1.
Subsequently, at time t4, the pixel reset signal RST becomes at a "Low" level, and accordingly, the reset transistor MRST becomes in an OFF state. The pixel selection signal RS becomes at a "Low" level, and accordingly, the pixel selection transistor MRS becomes in an OFF state. Accordingly, the potential of the pixel output signal terminal OUT1 becomes a potential that does not depend on the signal charge generated by the photodiode PD (the potential of the floating diffusion layer FD).
Subsequently, at time t5, the switch S2 becomes in an OFF state (at a "Low" level), and the common source reading in the low-noise flexible pixel 8 (source-grounded reading) ends.
Thus, in the low-noise flexible pixel 8 disclosed in Non-Patent Literature 1, two types of reading modes including the source follower reading (drain-grounded reading) and the common source reading (source-grounded reading) are included, and these reading modes are switched for each screen to achieve both of the wide dynamic range and the high S/N ratio.
Further, in a recent CMOS image sensor, in order to cope with mufti-functionality and miniaturization, a variety of functional circuits as well as pixels are incorporated to cope with a SOC (System On Chip) that realizes the multi-functionality. In the CMOS image sensor coping with the SOC, a chip-stacking technology in which the CMOS image sensor is physically divided into a first substrate in which pixels including photoelectric conversion elements are formed, and a second substrate in which a functional circuit is formed, which are separately fabricated, and the substrates are laminated to obtain one CMOS image sensor has also been used.
By physically dividing the pixel and the functional circuit of the CMOS image sensor, it is possible to fabricate respective substrates through a fabrication process most appropriate for required performance, and to greatly improve image pickup performance or functionality of the CMOS image sensor. Further, by physically dividing the pixel and the functional circuit of the CMOS image sensor, it is possible to reduce the respective substrate sizes, and thus, reduce a chip area (mounting area) of the CMOS image sensor, that is, to miniaturize the CMOS image sensor. Expansion into a new application use can also be realized.
In the chip-stacking technology, the first substrate and the second substrate that have been fabricated separately are electrically connected to each other by a connection electrode. In the CMOS image sensor corresponding to the SOC, the connection electrode is provided in each pixel formed in the first substrate and bonded to a corresponding connection electrode provided on the second substrate.
However, as can be seen from the configuration of the pixel illustrated in FIG. 12A, it is necessary for the low-noise flexible pixel 8 to include the two output terminals including the pixel output signal terminal OUT1 and the pixel output signal terminal OUT2 corresponding to the respective reading modes. That is, when the CMOS image sensor including the low-noise flexible pixel 8 is divided into the first substrate and the second substrate so as to cope with the SOC, two connection electrodes for connecting the respective substrates are required tor each pixel. In the chip-stacking technology, there are various technologies for a structure of the connection electrode or bonding portions for laminating the respective substrates, and a bonding method, but since previously fabricated substrates are laminated and bonded, reducing a size of the connection electrode or a distance between the connection electrodes is not easy in a recent miniaturization technology. Therefore, in the CMOS image sensor including the low-noise flexible pixel 8, it is difficult to cope with the SOC.
Therefore, for example, "A Rolling-Shutter Distortion-Free 3D Stacked Image Sensor with −160 dB Parasitic Light Sensitivity In-Pixel Storage Node," by J. Aoki, et al., ISSCC Dig. Tech. Papers, February 2013 (hereinafter referred to as Non-Patent Literature 2) discloses a technology for reducing the number of connection electrodes in a CMOS image sensor formed with a first substrate and a second substrate. FIG. 13 is a diagram illustrating a schematic configuration of a pixel configured with divided substrates in a conventional CMOS image sensor, which is disclosed in Non-Patent Literature 2. In the following description, a pixel having a configuration as illustrated in FIG. 13 is referred to as a "stacked low image distortion pixels." In FIG. 13, the same components as those of the pixels having the configurations illustrated in FIGS. 11A and 12A are denoted with the same reference numerals.
In the stacked low image distortion pixel 9 illustrated in FIG. 13, a pixel circuit 91 formed in a first substrate and a pixel signal reading circuit 92 formed in a second substrate are bonded by a connection electrode 93. In the stacked low image distortion pixel 9, one connection electrode is shared by four pixels, that is, the number of connection electrodes is ¼ of the number of pixels. In the stacked low image distortion pixel 9, by transferring signal charge generated by respective photodiodes PD-1 to PD-4 included in the pixel circuit 91 to corresponding analog memories CSH-1 to CSH-4, distortion of an image can be suppressed.


The process includes a treatment step during which a liquid containing a biocidal and/or plant-protection product or a mixture of biocidal and/or plant-protection products is evaporated and injected into the internal atmosphere of premises, the liquid being evaporates at a temperature of less than 50° C., the product vapour concentration in the internal atmosphere of the premises being kept at greater than 10% of a saturation concentration of the vapour of said product in said atmosphere at said temperature for a saturation duration of greater than 12 hours.

It is known that some synthetic volatile products or of natural origin e.g. essential oils have biocidal or plant-protection properties of interest. In particular, they are used to treat plant products to improve the preservation thereof.
The techniques used up until now to apply these products to plants are the following:                immersion of the plant products in a hot or cold aqueous dispersion containing the product;        spraying the premises e.g. plant storage chambers, for sanitization;        micro-misting when plant products enter the storage chambers.
The quantities of applied products are high and may lead to large concentrations in plant products.
Also, the grain sterilization processes currently used are based on spraying grain, on entry into silos, with highly toxic products; generally organophosphorus products. In the event of major insect attack during storage, the seeds are then treated with a gaseous product or fumigated volatile product. The products routinely used for this sterilization are phosphine, methyl bromide or ethyl formate. The treatment products used when entering storage or during storage are highly toxic and at times scarcely effective, notably on account of resistance-related problems.

This patent is subject to a terminal disclaimer.

Process for treatment by at least one moderately volatile biocidal and/or plant-protection product, corresponding treatment assembly and storage assembly


A field emission device is configured so as to suppress any deviation of the central axis of the distribution of emitted electrons from a conical cathode, with no electrode in addition to the gate electrode. A conductive layer is disposed over an insulating layer and has an electron emission window disposed over the conical cathode. Plural curved slits are formed in the conductive layer so as to expose the insulating layer and are arranged along a circle which is concentric with the tip of the conical cathode. The gate electrode is formed by the portion of conductive layer between the electron emission window and the curved slits. The portion of the conductive layer outside of the curved slits serves to distribute an applied potential to the gate electrodes of plural field emission devices arranged in a matrix. The portions of the conductive layer disposed between the curved slits serve to connect the gate electrode to the outer portion of the conductive layer. By selection of the physical geometry of the gate electrode, the field emission window, and the curved slits, and/or by selection of the relative doping concentrations of the gate electrode and the portions of the conductive layer disposed between the curved slits, any deviation in the emission direction of the electrons is automatically compensated for by a deviation in the voltage dropped by a portion of the gate electrode into which a disproportionate amount of electrons have been emitted.

1. Field of the Invention
The present invention relates to a field emission device and more particularly, to a field emission device capable of automatic compensation of the distribution deviation of emitted electrons from a cathode.
2. Description of the Prior Art
Conventionally, various types of field emission devices have been developed, typical examples of which were reported by C. A. Spindt et al. in the paper, Journal of Applied Physics, Vol. 47, No. 12, pp. 5248-5263, published in December 1976, and by H. F. Gray et al. in the paper, 1986 IEDM Technical Digest, pp. 776-779, published in 1986.
An example of the conventional field emission devices is shown in FIG. 1, which includes a semiconductor substrate 131. An insulating layer 132 is formed on the substrate 131. A conductive layer 133 is formed on the insulating layer 132. The conductive layer 133 serves as a gate electrode and has circular windows 134 uncovering the surface of the underlying insulating layer 132. The windows 134 are arranged in a matrix array. The insulating layer 132 has penetrating circular holes (not shown) formed at the locations corresponding to the windows 134, respectively, thereby exposing the surface of the substrate 131.
Conical cathodes 135, which are made of a conductive metal such as molybdenum (Mo), are formed on the exposed surface of the substrate 131 in the holes of the insulating layer 132, respectively. Each of the cathodes 135 has a shape of a sharp-pointed cone. The tips of the cathodes 135 are located in the vicinity of the interface of the gate electrode 133 and the insulating layer 132.
When a positive electric potential is applied to the gate electrode 133 with respect to the conical cathodes 135 in a vacuum atmosphere, electrons (not shown) are emitted or extracted from the vicinity of the tips of the cathodes 135 due to the "field emission" phenomenon. The emitted electrons move upward in the space near the gate electrode 133, traveling toward an anode (not shown).
The condition for the field emission phenomenon of the electrons is determined according to the shape of the cathodes 135 and the distances between the gate electrode 133 and the corresponding cathodes 135.
With the conventional field emission device shown in FIG. 1, the overall emission direction of the electrons is dependent upon (a) the electric-field distribution in the vicinity of the tips of the conical cathodes 135, (b) the surface state (for example, the work function and electron density) of the cathodes 135 in the vicinity of their tips, and (c) the surface configuration (for example, surface irregularities) of the cathodes 135 in the vicinity of their tips.
If the shape of each cathode 135 is accurately conical, the surface state and configuration of the cathode 135 are axially symmetric with respect to its central axis penetrating the tip, and the distance of the cathode 135 from the opposing inner edge of the gate electrode 133 is axially symmetric with respect to the central axis, the emitted electrons will travel from the tip through a conical region with a solid angle of approximately 40.degree..
However, if the above-described axial symmetry of either the shape, or the surface state, or and the surface configuration is collapsed, the central or symmetric axis of the distribution of the emitted electrons will deviate from its original position. This symmetric-axis deviation causes a problem that aberration tends to occur in the case where the emitted electrons are collected by an electron lens or lenses (not shown) or that deviation of the overall emission direction of the electrons from an intended direction tends to occur even for the case where no electron lens is used.
Further, the above symmetric-axis deviation causes another problem that the emitted electrons tend to stream into or enter the gate electrode 133, thereby consuming surplus electric power. This surplus power consumption heats the neighboring regions of the gate electrode 133 with the cathodes 135 to generate some gaseous material. The generated gaseous material leads to the insulation breakdown phenomenon. Therefore, a "discharge current" tends to flow between the gate electrode 133 and the cathodes 135, destroying or damaging the gate 133 and/or the cathodes 135.
At this stage, a part of the emitted electrons tend to directly or indirectly enter the insulating layer 132, thereby charging-up the insulating layer 132. Thus, there arises a problem that the insulating characteristic of the field emission device degrades. In other words, a leakage current tends to flow between the gate electrode 133 and the substrate 131. This results in an unstable potential difference between the gate electrode 133 and the substrate 131 (i.e., the cathodes 135).
A typical example of the above-described destruction of the gate electrode 133 and/or the cathodes 135 due to the discharge current is the short-circuit-induced destruction, where the gate electrode 133 and at least one of the cathodes 135 are electrically connected to be destroyed due to short-circuit.
To solve the problem of the short-circuit-induced destruction, the following improvement was developed as disclosed in the Japanese Non-Examined Patent Publication no. 4-284324 published in 1992.
In this improvement, a gate electrode is divided into a plurality of electrode elements; an unsoluble main element and soluble branch elements located at respective cathodes. When short-circuit occurs between the gate electrode and any one of the cathodes, the corresponding one of the branch elements of the gate electrode is solved or melted by heat due to the short-circuit, thereby being separated from the remainder. Thus, the normal operation of the remaining cathodes is surely kept even after the short-circuit.
However, the improvement disclosed in the Japanese Non-Examined Patent Publication no. 4-284324 cannot solve the previously-explained problem caused by the deviation of the symmetric axis of the emitted electron distribution.

Field emission device having configuration for correcting deviation of electron emission direction


A method of improving electrical contact to a thin film of a p-type tellurium-containing II-VI semiconductor comprising:. depositing a first undoped layer of ZnTe on a thin film of p-type tellurium containing II-VI semiconductor with material properties selected to limit the formation of potential barriers at the interface between the p-CdTe and the undoped layer, to a thickness sufficient to control diffusion of the metallic-doped ZnTe into the p-type tellurim-containing II-VI semiconductor, but thin enough to minimize affects of series resistance; PA1 depositing a second heavy doped p-type ZnTe layer to the first layer using an appropriate dopant; and PA1 depositing an appropriate metal onto the outer-most surface of the doped ZnTe layer for connecting an external electrical conductor to an ohmic contact.

A typical single-junction photovoltaic cell is comprised of a substrate on which to form the device, two ohmic contacts to conduct current to an external electrical circuit, and two or more semiconductor layers in series to form the semiconductor junction. At least one of these semiconductor layers (the absorber) is chosen so that its bandgap is of a value for near-optimum conversion of solar radiation. In the typical design, one semiconductor layer is doped n-type, and the adjacent layer is doped p-type. The intimate proximity of these layers forms a semiconductor p-n junction. The p-n junction provides an electric field that facilitates charge separation in the absorber layer(s) when the cell is illuminated, and charge collection at the ohmic contacts.
In general, the typical photovoltaic cell comprises a substrate to mount the cell and two ohmic contacts to conduct current to an external electrical circuit. In this arrangement, the cell may also include two or more semiconductor layers in series.
In the standard photovoltaic cell including the substrate for mounting the cell and two ohmic contacts for conducting current to an external electrical circuit, in addition to the n-type layer and the p-type layer of a p-n junction cell, a three layer cell can include an intrinsic (i-type) semiconductor layer disposed between the n-type layer and the p-type layer for absorption of light.
In the photovoltaic cell, the semiconductor layers may be formed from single crystalline materials, amorphous materials, or polycrystalline materials. However, single crystalline materials are preferred from an efficiency perspective, because efficiencies are available in excess of about 20% in specific single crystalline photovoltaic cells Nevertheless, the disadvantages associated with single crystalline materials is the high cost of the material as well as the difficulty in depositing the single crystalline materials.
On the other hand, in the case of amorphous materials, one must contend with low carrier mobility, low minority carrier lifetime, low efficiency, and issues of cell stability. Therefore, while single-crystalline and amorphous materials are utilized in some photovoltaic device applications, semiconductor layers composed of polycrystalline materials are viewed as the preferred alternative for the production of photovoltaic devices that would be economically viable for a wide range of applications.
Polycrystalline materials offer numerous advantages for the production of photovoltaic cells. However, there is a desire in the industry of the field of polycrystalline materials to increase the efficiency of the polycrystalline photovoltaic cells from the current efficiencies of about 5-10% range to about a range of about 10-15%, and ultimately to advance the efficiencies of polycrystalline photovoltaic cells closer to the 15-25% range of single-crystalline materials.
Cadmium telluride is a semiconductor with electrical properties recognized in the industry as well suited for conversion of sunlight into electrical energy.The material has a bandgap that is nearly optimum for conversion of terrestrial solar radiation, and the ability to be doped n-type and p-type, that permits the formation of a large range of junction structures.
Nevertheless, there is still extant a need for more efficient and less expensive photovoltaic cells, and in particular, for a more efficient cadmium telluride photovoltaic cell suitable for large scale production. While much of the earlier stages of research on cadmium telluride solar cells was confined to the use of a single crystal cadmium telluride, more recent work has included processes for improving the deposition of cadmium telluride on a substrate. For instance, some examples of deposition processes now available include chemical vapor deposition, electrodeposition, close spaced sublimation, solid-gas reaction, sputtering spray pyrolysis, molecular beam epitaxy, liquid phase epitaxy, and other processes known in the art.
One significant technological problem with CdTe-based devices is that it is difficult to form an ohmic contact to the p-type form of the material. This is observed for both single crystalline and polycrystalline p-type CdTe, and results from a combination of large semiconductor work function, and the inability of CdTe to sustain sufficiently high p-type carrier concentration to enable quantum-mechanical tunneling of charge carriers at the CdTe/metal contact interface. In addition to these fundamental problems, the polycrystalline p-type CdTe material used as the absorber in a CdS/CdTe photovoltaic device is typically treated with Cl-containing liquids or vapors just prior to the formation of ohmic contact. The Cl treatments improve junction performance, but also can produce a CdTe surface that is rich in Cl. Furthermore, the formation of oxide layers from atmospheric oxygen or other processes can alter the chemical properties of the p-type CdTe surface. These factors can effect the electrical transport at the contact interface, and alter the characteristics of the ohmic contact.
The outer surfaces of the p-type CdTe are typically preconditioned prior to application of contact layers by the use of various surface treatments that are known in art. In addition to removing unwanted contamination from the surface, these preconditioning treatments can result in a CdTe surface that is relatively stoichiometric, or a CdTe surface comprised of a Te-rich outer layer. Regardless of the processes used to precondition the CdTe surface, the materials and processes that are subsequently used to produce the outer contact layers must be optimized for the characteristics of the preconditioned CdTe surface so that all interfaces produce low resistance and interface stability.
Typically, the processes used to deposit the outer metallization layers are performed at relatively low temperature to avoid diffusion of the outer contact layers into the CdTe (i.e., less than about 150.degree. C.). This low-temperature processing is undesirable for in-line photovoltaic cell manufacturing processes because higher-temperature processes (greater than about 150.degree. C.) typically occur immediately prior to the contact fabrication. Additionally, it is difficult to attain optimum adhesion of the contact metallization at low temperature, and this can result in reduced contact stability.
Accordingly, there is a need in the art of preparing contacts to the back surface of CdS/CdTe thin-film photovoltaic devices to produce improved contacting processes. Desirable improvements to the contacting process would include: Inherent compatibility with in-line manufacturing processes (i.e., use of "dry processes"); allowance for incorporation of dry processes to precondition the CdTe surface prior to contact fabrication; ability to fabricate the contact at high processing temperatures (>150.degree. C.); ability to choose a variety of outer metallizations depending on industrial design considerations; ability to modify the contacting process to enhance contact stability; and provision to choose processes that minimize waste products.
The present invention encompasses the use of two separate ZnTe films deposited between the pre-conditioned p-CdTe surface and subsequent metallizations as interface layers to improve electrical contact to p-CdTe thin films. The first film deposited (on the p-CdTe) is undoped ZnTe, and the second film deposited is doped heavily p-type. The two separate films are used to avoid the drawbacks associated with using a single film to provide optimum device performance, and these layers may be used in photovoltaic and other devices to improve device performance by decreasing the losses associated with the back contact and by increasing back contact stability.
A heterojunction p-i-n photovoltaic cell having at least three different semiconductor layers formed of at least four different elements comprising a p-type wide band gap semiconductor layer, a high resistivity intrinsic semiconductor layer, used as an absorber of light radiation, and an n-type wide band gap semiconductor layer is disclosed in U.S. Pat. No. 4,710,589. The intrinsic layer is in electrically conductive contact on one side with the p-type layer and on an opposite side with the n-type layer. First and second ohmic contacts are in electrically conductive contact with the p-type layer and the n-type layer.
In U.S. Pat. No. 5,393,675, there is disclosed a process for dry fabrication of CdS/CdTe photovoltaic devices; however, this patent utilizes only a single ZnTe layer, discloses that the ZnTe functions only as the p-type layer of a p-i-n PV structure, and that the contact is provided by metal layers. Further, there is no indication or appreciation that the ZnTe can be doped, and that if a multilayer contact is used, both layers must be metals (e.g., Cu and Au).
Journal Paper, A. Mondal et al., Solar Energy Materials and Solar Cells 26, 181 (1992), discloses first use of electrochemistry to form ZnTe and ZnTe: Cu, and identifies the use of only a single-layer ZnTe: Cu interface.
The use of thin (1-5 nm) Cu layers to dope but not shunt the p-CdTe of a CdS/CdTe device is disclosed in U.S. Pat. No. 4,735,662, in which use of a barrier layer on top of a thin Cu layer is employed to afford selection of other conduction layers. In essence, this patent discloses the use of a metallic layer (.about.3 nm Cu) to provide the necessary p-type doping in the CdTe to produce a low resistance contact. On this layer is placed both a barrier layer and the thicker conduction layers.
U.S. Pat. No. 4,319,069 discloses chemical treatment of a p-CdTe surface prior to contacting to improve the contact characteristics. HNO.sub.3 (oxidizing acid) plus H.sub.3 PO.sub.4 (leveling agent) is employed to form the Te layer. In this patent, the use of .about.5% HNO.sub.3 +H.sub.3 PO.sub.4 chemical pretreatment is used to improve the contact characteristics, and is a subtractive process.
Chemical treatment of a p-CdTe surface prior to contacting to improve the contact characteristics, by use of an oxidizing acid plus a reducing agent (hydrazine or metal alkalide) is disclosed in U.S. Pat. No. 4,456,630. The use of the chemical pretreatment to improve contact characteristic is subtractive processing, and in such a process, generally, there is very limited control over characteristics such as removal rate, selective grain-boundary etching, and thickness of the resulting Te-layer formation.
In, Journal Paper A. Fahrenbruch., Solar Cells 21, 399 (1987), there is a review of technology used to contact polycrystaline p-CdTe up to approximately 1987; and, in Journal Paper, F. Debbagh et. al., Solar Energy Materials and Solar Cells 31, 1 (1993), there is a disclosure of interdiffusion of elemental Cu and Te layers on polycrystalline CdTe.
U.S. Pat. No. 4,568,792 discloses the production of CdS and CdTe ternaries (with Zn, Se, etc.) and makes photovoltaic devices that are better than the standard CdS/CdTe device.

Use of separate ZnTe interface layers to form OHMIC contacts to p-CdTe films


A structured sub-mount assembly is disclosed to support a hybrid assembly of tunable filters. The sub-mount assembly is constructed to provide a high thermal resistance path and high mechanical resonance frequency. Optionally, the structured sub-mount assembly includes a temperature-controlled phase adjust component disposed approximately midway between the two tunable filters. The structured sub-mount assembly may be part of a tunable laser or other application.

Tunable filters may be used for many different applications, such as tunable lasers, tunable add-drop multiplexers, tunable dispersion compensation, and tunable receivers. Where the filters are used in a tunable laser, for example, the filters select one of several wavelengths used by the laser. One implementation for a tunable laser monolithically integrates the tunable filter with thermal resistance and a mechanically stiff mounting, using a tensile-strained thin-film thermal resistor fashioned from silicon nitride. This implementation requires a relatively inefficient use of wafer area to accommodate the thermal resistance function. Further, the placing of the various fabrication steps in series results in yield and latency hits.
Another tunable laser uses a micro-hotplate as a sub-mount, but a sub-mount without structuring. A simple diced glass plate does not provide a sufficiently high thermal resistance for a given size so as to permit low power operation of the thin bulk etalon temperature tunable filters (˜150 microns Si) for standard telecom form factors and tuning ranges.
Thus, there is a continuing need for a structured sub-mount for a tunable filter that overcomes the shortcomings of the prior art.

Structured submount for tuner assembly with optional phase adjust


A blackbody radiation device (110) includes a planar filament emission element (102) and a planar detector (104) for respectively producing and detecting radiation having width dl/1 less than about 0.1 to test a sample gas, where 1 is the wavelength of the radiation; a reflector (108); a window (W); an electrical control (118); and a data output element (116).

Non-dispersive Infrared (NDIR) techniques utilizing the characteristic absorption bands of gases in the infrared have long been considered as one of the best methods for gas measurement. These techniques take advantage of the fact that various gases exhibit substantial absorption at specific wavelengths in the infrared radiation spectrum. The term "non-dispersive" refers to the type of apparatus incorporating the NDIR technique, typically including a narrow band pass interference filter (as opposed to a "dispersive" element such as a prism or a diffraction grating to isolate and pass radiation in a particular wavelength band from a spectrally broad band infrared source. The gas concentration is discerned from the detected intensity modulation of source radiation emanating from the source and passed by the filter coincident in wavelength with a strong absorption band of the gas to be measured.
A prior art NDIR gas analyzer typically includes an infrared source with a motor-driven mechanical chopper to modulate the source so that synchronous detection is used to discriminate spurious infrared radiation from surroundings; a pump to push gas through a sample chamber; a narrow band-pass interference filter; a sensitive infrared detector, inexpensive infrared optics and windows to focus the infrared energy from the source onto the detector. Despite the fact that the NDIR gas measurement technique is one of the best methodologies that had ever been devised, it has not enjoyed wide application because of its complexity and high cost of implementation.
Several components play essential roles in making the NDIR technique work for gas measurement. The radiation source is one such component; and in order for NDIR methodology to work efficaciously, this source must provide broad spectral output and give high power in the band of interest. A blackbody radiation source is generally used for this component because it can be heated to a temperature that provides high intensity radiation within any wavelength region. Because the blackbody output spectral distribution and intensity are uniquely determined by the temperature of the source, the spectral peak intensity can be adjusted by varying the temperature of the blackbody source. By the well-known Wien's Displacement Law the peak intensity of a blackbody radiation source of temperature T is at a wavelength λmax equivalent to 2.898×10−3/T where T is measured in degrees Kelvin (1° K) and λmax is measured in meters. By the process of T and the size of the blackbody radiator, a desired intensity of blackbody radiation selected wavelength λ can be attained.
The so-called "Nernst Glower," consisting of a heating element of a tungsten filament) embedded in a ceramic slab, has long been used for the blackbody source of most prior art NDIR gas detection systems. Despite the fact that the Nernst Glower gives off an amount of infrared energy with an emissivity close to unity, its power efficiency (i.e., efficiency from electrical to useable optical energy) is notoriously low. The large amount of unwanted heat is also a major drawback in the use of the Nernst Glower in any NDIR gas measurement systems. Furthermore, the large heat capacity of the Nernst Glower makes it a necessarily slow device in terms of intensity modulation. In many cases, it can only be used as a steady state or DC radiation source; and thus a mechanical chopper is needed to generate synchronous modulated signals, further adding to the complexity of NDIR gas measurement systems.
The prior art has attempted to replace the blackbody radiator with hot filament as an approximation to a blackbody. However, such a filament does not have high emission over all wavelengths because there is spatial temperature variation within the filament; it is not an ideal blackbody source. Optical radiation sources, such as a hot filament lamp, are thus often referred to as "quasi-blackbody" sources. In addition, hot filament radiators typically are used by a quartz bulb which is substantially opaque for wavelengths, longer than about 4.5 μm reducing its applicability to gas detection through longer wavelength absorption lines. Prior art hot filaments are thus not particularly good infrared radiation sources for use with NDIR gas sensors.
The prior art has attempted to improve NDIR sensors. In U.S. Pat. No. 4,876,413 (the '414 patent), published in April of 1975, Bridgham describes an infrared radiation source that includes a thin film resistor heater with highly emissive material Cr3Si on a substrate. The thin film heater is positioned between a pair of thin metal elements serving as sensing electrodes on a very thin (<0.005″ typical) insulating substrate. The entire thin film heater is packaged in a standard TO-5 heater equipped with a focusing reflector and pins supporting the heater structure.
While the source of the '413 patent advances infrared radiator sources in terms of higher emissivity and wider spectral emissions, it does not offer size or speed advance over the classic tungsten lamp. Furthermore, its construction is rather fragile and the heater cannot withstand temperatures above −700° C., severely limiting the maximum allowable output. Finally, its overall power efficiency is rather poor and the low cost and useable life of this radiator has not been satisfactorily proven. Consequently, the source of the '413 patent has not found wide application in NDIR gas measurement systems.
In U.S. Pat. No. 4,644,141 published in February of 1987, Hager et al. advances a heater structure first proposed in the '413 patent, except that a combination of silicon, silicon oxides and a platinum metal pattern are used as the heating element to optimize the performance of the overall heater structure. Nevertheless, other than a slight improvement in power efficiency over the device of '413 patent, there is no fundamental advancement over the prior art.
Over the past several years, significant technical progress has been made in the area of optical sources as set forth in the inventor's own prior application of U.S. Ser. No. 08/511,070, filed on Aug. 3, 1995. Such optical sources have greatly increased the reliability and cost-effectiveness of NDIR gas sensors.
The present invention has several objects in providing further improvements and advantages in source and sensor embodiments as compared to the prior art. One object of the invention is to provide sources which function as tuned waveband emitters that preferentially emit radiation into a wavelength band of interest as compared to blackbody or gray-body radiators. Another object of the invention provides in integrated circuit sensor include selectively tuned radiation source. Still another object of the invention provides methods and devices for sensing gas constituents without certain of the difficulties and problems of prior art NDIR devices.
These and other objects will become apparent in the description which follows.

Infrared radiation sources, sensors and source combinations, and methods of manufacture


A neural network capturing a minute pattern variation useful for recognition while maintaining robustness against a pattern variation unrelated to recognition is learned. A preprocessing unit performs, on a set of patterns being to be learned and including a specific pattern variation, a plurality of preprocesses causing different degrees of the specific pattern variation. A network structure determination unit determines, for each of the plurality of preprocesses, a network structure of a neural network having robustness according to a degree of the specific pattern variation after the preprocess. A network learning unit learns, for each of the plurality of preprocesses, the neural network with the network structure associated with the preprocess using the set of patterns after the preprocess.

A pattern recognition technique is a technique for estimating which class an input pattern belongs to. Specific examples of pattern recognition include object recognition which estimates an object appearing in an input image, voice recognition which estimates a speech content of an input voice, and the like.
Statistical machine learning is widely used as a pattern recognition technique. As statistical machine learning, a neural network in particular has been known in recent years as a learning method capable of recognition being robust against a pattern variation unrelated to recognition, because of development of a learning technique called deep learning.
In pattern recognition using a neural network, it is possible to perform recognition being robust against a pattern variation unrelated to recognition, but on the other hand, it is difficult to perform recognition capturing a minute pattern variation (minute characteristic difference) being useful for recognition. For example, in face authentication for identifying an individual from a face image, a pattern variation (a displacement of an image, and a difference of a position and a shape of a face resulting from a variation of facial expressions) unrelated to identification of an individual is larger than a characteristic difference (difference of positions and shapes of eyes and noses between individuals) useful for identification of an individual. Thus, when learning a neural network being robust against a pattern variation unrelated to recognition, it becomes difficult to capture a characteristic difference useful for identification of an individual.
Such a pattern variation unrelated to recognition is described with a positional variation (displacement) of an image as an example. Generally, in a neural network, a pooling layer, for example, as disclosed in PTL 1 is introduced in order to improve robustness against a positional variation. The pooling layer performs pooling which includes integrating pixel values for each local region and outputting a result. FIG. 5 is a diagram illustrating an example of pooling by a pooling layer. In FIG. 5, a rectangle represents a pixel, and a number in a rectangle represents a pixel value. In the example of FIG. 5, max pooling is performed as pooling. In the max pooling, a maximum value of pixel values in a local region (a region of 2×2 pixels in FIG. 5) is output as a pixel value after pooling. As a result of the pooling, substantially the same pixel value is output for a displacement whose size is equal to or less than a size of the local region. Therefore, it is possible to perform recognition being robust against a displacement by learning a neural network including a pooling layer.
FIG. 6 is a diagram illustrating an example of pooling for face recognition. Two images in FIG. 6 are face images of different persons. In these face images, minute characteristics in local regions are different, and it is therefore possible to distinguish the persons in the two images by capturing the minute characteristic difference. However, when a pooling layer is used, the minute characteristic difference is lost, and the same pixel value is output for each of the face images. Thus, while recognition being robust against a displacement can be performed, recognition capturing a minute characteristic difference cannot be performed.

Information processing device, information processing method, and recording medium


A vehicle body lower section structure comprises a rocker that extends in a vehicle body front-rear direction at a vehicle width direction outside of a floor panel; a first cross member that extends in the vehicle width direction at a lower side of a dashboard panel and includes an outside end portion in the vehicle width direction coupled to the rocker; a second cross member that extends in the vehicle width direction at the vehicle body front side of the first cross member; and a coupling member that couples the first cross member and the second cross member together, and configures a closed cross-section structure with the dashboard panel and/or the floor panel.

1. Technical Field
The present invention relates to a vehicle body lower section structure.
2. Related Art
As described in Japanese Patent No. 5041073, for example, a conventional vehicle body front section structure is proposed in which a dashboard cross member with a closed cross-section structure is provided to a dashboard panel, and the dashboard cross member is joined to a front pillar.


The invention relates to a process for preparing polyorganosiloxane-containing emulsions having a mean particle size of less than 0.3 .mu.m in which, in a first step,. (A) a concentrate is prepared by mixing a polyorganosiloxane with water and an emulsifier which is soluble in the polyorganosiloxane. PA1 (B) the concentrate thus obtained is diluted with water to the desired polyorganosiloxane concentration.. and, in a second step,. These emulsions can be used for impregnating fibres and fabrics.

Highly dispersed organopolysiloxane emulsions are disclosed, inter alia, in U.S. Pat. No. 4,620,878 (published on Nov. 4, 1986, R. P. Gee, Dow Corning Corp.). The emulsions prepared in accordance with this patent must contain at least one emulsifier which is insoluble in the organopolysiloxane. In a first step, an organopolysiloxane, an emulsifier and water are used to form an oil concentrate, which, in a second step, must be dispersed in water very rapidly and without any delay to give a sufficiently dispersed emulsion. Highly dispersed emulsions are also described in WO 88/08 436 (laid-open on Nov. 3, 1988, H. Chrobaczek et al., Chemische Fabrik Pfersee GmbH). These emulsions are prepared from an aminoalkyl-substituted polyorganosiloxane, a water-soluble emulsifier, acid and water while heating to at least 50.degree. C.
It is an object of the present invention to provide a process for preparing highly dispersed emulsions. Another object of the present invention is to provide a process for preparing such emulsions in which the concentrate obtained as an intermediate need not be rapidly and immediately dispersed in water. A further object of the present invention is to provide a process for preparing emulsions in which the reaction mixture need not be kept at a relatively high temperature during the preparation of the emulsions.


Two types of outline font data defining thin and thick line characters belonging to the same font category are stored in a character ROM. Intermediate line characters of the same font category are generated based on the data stored in the character ROM without need for fixedly determining an order of arrangement of a plurality of pieces of data making up the character.

1. Field of the Invention
The present invention relates generally to character/symbol generating devices, and more particularly to a character/symbol generating device capable of generating characters and symbols with a desired line thickness based on character/symbol data of the same font category but of different line thickness.
2. Description of the Related Art
Character/symbol generating devices encompass printers, display units and the like. As is well known in the art, characters of various kinds of font are generally usable in such devices. Typically, one font has several different families. Only line width or line thickness of segmental lines making up each character or symbol (for the sake of simplicity, referred to as "character" hereinafter) is different in the respective families of the same font. For example, a serif font like Times Roman and sans-serif font like Helvetica are of different kind. Times Roman can be classified into slender Times, normal Times and bold Times which are the families of Times Roman but the thickness of the line segments of the character in these families are different.
Conventionally, character/symbol generating devices are supplied with fonts of different families individually, so a large capacity memory is needed to load these font families. It is possible for the character/symbol generating devices to reduce the number of font families to be loaded by producing desired intermediate line thickness characters based on slender and bold characters using interpolation technique. Only the slender and bold character families suffice to load in the character/symbol generating devices, whereby characters of desired line thickness are generated.
However, there are problems in performing the interpolation technique in that arrangement order of pieces of data for the same character in slender and bold families must be fixedly determined in advance so that the corresponding points or parts of the two family characters can be identified from the order of the data arrangement. This is because different font families do not have intercommunicating information that identifies the corresponding points or parts of the different font family characters. Therefore, if it is attempted to produce additional fonts from the minimum number of family fonts, it is necessary to process separately developed family fonts and rearrange the order of pieces of data. If the arrangement order of the pieces of data provides an information when reconstructing the character, rearrangement of the order cannot be done.

Character/symbol generating device for generating character/symbol with a desired line thickness


A novel child's bicycle seat/rack assembly is provided. The seat is capable of slidable attachment to a touring rack of the type including a substantially rectangular frame formed from struts. The seat has integrally-formed channels for slidably engaging the struts and forward and rear integrally-formed, latches adapted to releasably engage the struts so as to lock the seat member against rearward movement relative to the rack. A locking wedge is provided to secure a latch against unintentional flexing and disengagement from the strut. A child's seat may have a seat portion and a back portion pivotably attached to one another by a pair of axially aligned, hub assemblies.

This invention relates to a child's bicycle seat of the type adapted to be supported on a bicycle rack attached to the frame of a bicycle and supported over a wheel.
Numerous child's bicycle seat and rack assemblies are known in the prior art. Nearly all involve seats which are bolted to rack elements, disengagement of the seat from the rack being troublesome and time consuming. Many of the existing assemblies do not even contemplate the use of the rack without the seat. One rack, that shown in U.S. Pat. No. 4,030,648, shows a seat adapted for sliding engagement with a rack, the seat being snap locked into engagement with the rack. The rack, however, is specially designed and requires a biased element integrally formed in its solid flat platform and an overhang of the platform relative to the side supports for interengagement with a channel in the seat.


Example implementations relate to flexible displays. For example, a flexible display system may comprise a plurality of display layers, an anti-reflective layer among the plurality of display layers to reduce reflection from an underlying light emitting layer, the anti-reflective layer including a wave plate and a polarizer, and a transistor layer among the plurality of display layers. Further, at least a portion of the plurality of display layers may include properties satisfying particular geometric and force balance constraints to enable the transistor layer to maintain a neutral force in response to compression or tension of the flexible display.

A flexible display may be convenient to carry, and may embody a relatively large-sized screen, and accordingly, the flexible display may be applied to not only mobile devices, such as cellular phones, portable multimedia players (PMPs), navigation devices, ultra mobile personal computers (UMPCs), e-books, e-newspapers, and the like, but also to other fields, such as TVs, monitors, and the like.

Hewlett-Packard Development Company, L.P.


Described herein are compositions for use in the brazing of metal substrates. Methods of making and using these compositions are also described herein.

Heat exchangers often have a distributor tube whose external surface is provided with cooling fins. The distributor tube is typically a steel tube coated with a metal having good heat conduction, such as aluminum. The cooling fins themselves also generally comprise aluminum because of its good heat conductivity and low weight.
The bond between the distributor tube and the cooling fins is generally created through a brazing process. Traditionally, the distributor tube was cladded with aluminum or an aluminum-silicon alloy. However, when producing an aluminum cladded tube, intermetallic layers form between the cladding and the base steel material. After forming the cladded tube, the tube must be cleaned for brazing. This cleaning typically involves water based cleaners which need to be dried before the brazing process. The cleaned and cladded tube is then subjected to a secondary heating such that the tube is bonded to the aluminum fins at a brazing temperature of approximately 600° C. Secondary heating increases the thickness of the brittle intermetallic layer which is subject to cracking. Also, during this secondary heating process, the aluminum layer can be thinned from capillary action during brazing to the point where it does not provide sufficient long term corrosion protection for the base steel material.
Accordingly, there is a need for brazing compositions which: (1) eliminate the need for aluminum cladding prior to the brazing process; (2) eliminate the need for a drying step in the brazing process; (3) eliminate the need for secondary heating in the brazing process; (4) reduce or eliminate the intermetallic layer between the cooling fin and the distributor tube; and (5) provide long term corrosion protection.
Embodiments of the present invention are designed to meet these ends.


To provide a transflective liquid crystal display device capable of obtaining a display with high brightness, high contrast, and wide viewing angle, a liquid crystal display device including a liquid crystal layer sandwiched between a pair of substrates, the liquid crystal layer having liquid crystal having negative dielectric anisotropy whose initial alignment state exhibits a vertical alignment; and a plurality of dot regions arranged in an image display region, each of the dot regions being provided with a transmissive display region to perform transmissive display and a reflective display region to perform reflective display therein, the transmissive display regions or the reflective display regions of two adjacent dot regions P1, P2 provided at positions facing edges of the respective dot regions and the liquid crystal aligned obliquely in reverse directions to each other by a transverse electric field which is generated at each edge when a voltage is applied.

1. Field of Invention
The present invention relates to a liquid crystal display device and an electronic apparatus, and more specifically, to a technology capable of obtaining a display with high brightness, high contrast and wide viewing angle, in a transflective liquid crystal display device where display is performed in both transmissive and reflective modes.
2. Description of Related Art
A liquid crystal display device has been proposed where external light is used in a bright place similar to a reflective liquid crystal display device and where an internal light source, such as a backlight, is used in a dark place to make the display visible. This liquid crystal display device adopts both reflective and transmissive display modes, and is configured to reduce power consumption by switching the display mode to either of the reflective and transmissive modes depending on the surrounding brightness. It can produce a clear display even in dark surroundings and is suitable for the display of a portable apparatus. Hereinafter, such a liquid crystal display device is referred to as a "transflective liquid crystal display device" in the present specification.
As such a transflective liquid crystal display device, a liquid crystal display device has been proposed in the related art in which a liquid crystal layer is sandwiched between an upper substrate and a lower substrate and a reflecting film in which an opening for light transmission is formed of a metal film, such as aluminum, is also provided on the inside of the lower substrate so as to function as a transflector. In the reflective mode, external light incident from the upper substrate side passes through a liquid crystal layer and then reflects on the reflecting film of the inside of the lower substrate and then passes through the liquid crystal layer again and emits from the upper substrate, thereby contributing to display. In the transmissive mode, light from the backlight incident to the lower substrate passes through a liquid crystal layer from the opening of the reflecting film and then emits from the upper substrate to the outside, thereby contributing to the display. Therefore, in the forming region of the reflecting film, the region in which an opening is formed is a transmissive display region, and the remaining region is a reflective display region.
However, a related art transflective liquid crystal display device has a problem in that the viewing angle is narrow in the transmissive display. This is because the reflective display uses only a single sheet of polarizer on the observers side since a transflector is provided on the inner plane of a liquid crystal cell so that parallax does not occur, thereby reducing the degree of freedom in the optical design. In order to address this problem, a transflective liquid crystal display device using a vertical alignment liquid crystal has been proposed in Japanese Unexamined Patent Application Publication No. 2002-350853. Its characteristics are as follows:
(1) A "VA (vertical alignment) mode" is employed where a liquid crystal having negative dielectric anisotropy is aligned vertically to a substrate and is inclined by the application of voltage.
(2) A "multigap structure" is employed where a transmissive display region and a reflective display region are different in liquid crystal layer thickness (cell gap) from each other.
(3) The transmissive display region is a regular octagon or a circle with a protrusion in the center of the transmissive display region on the counter substrate so that the liquid crystal is isotropically inclined within this region. In other words, an "alignment division structure" has been employed.
In a color liquid crystal display device of the transmissive type, there is a related art method known to realize a wide viewing angle as multi-domains are implemented by providing alignment control means such as various forms of electrode slits, protrusions, etc. employing a VA mode. See Japanese Unexamined Patent Application Publication No. 7-28063, Japanese Unexamined Patent Application Publication No. 11-258606 and Japanese Unexamined Patent Application Publication No. 2001-154200.

Liquid crystal display device and electronic apparatus having particular dot regions