A method and apparatus for routing calls for a subscriber based on the identification of the calling party or the originating line. Generally, the present invention operates to identify a calling party or originating line and then select a routing list based on this identification. Once a routing list has been selected, the call will be routed to the destination in the routing list. More specifically, when a call is received, an inquiry is made regarding the identity of the calling party or calling line. If the identification can be determined, then an attempt to retrieve a routing list associated with this identification is made. If a routing list has been provided for the identified party or line, the routing list will be retrieved. If a routing list has not been provided for the identified party or line, a default routing list will be selected for routing the call.

As technological advances are made in communication equipment, and computers are more highly integrated into the telecommunications networks and systems, the ultimate goal of communication service providers: obtaining "real-time", "seamless" access to all parties; is becoming an ascertainable target. "Real-time" access refers to the ability to contact a party instantaneously as opposed to paging the party or leaving a message. "Seamless" access includes the ability to reach a party regardless of the party's location, or the time of day. In achieving this goal, a party can always be contacted by callers regardless of the parties location. The task of maintaining real-time, seamless access is not trivial.
One solution presently in operation is the Personal Number System ("PNS"), which is described in commonly owned U.S. application Ser. No. 07/936,384. The PNS from BellSouth Wireless gives a subscriber the ability to be contacted by other callers regardless of the subscriber's location. This is accomplished by providing a single point of contact for each subscriber in the form of a personal number. In addition, each subscriber provides the system with communication routing information in the form of one or more "destination lists" or "routing lists". The routing list contains various directory numbers that identify phone lines where the subscriber may be accessed. Calls placed to the subscriber's personal number will be routed by the PNS to the various destination numbers until either the subscriber is located or the list of destination numbers has been exhausted.
In the PNS, the subscriber has the flexibility to change the routing lists or alter the manner in which they are utilized. Methods to alter the use of the routing lists include enabling an "override" feature. The override feature allows the subscriber to disable the use of the routing list for a particular caller or all callers, and force the incoming call to be routed to a particular alternate number. Upon disabling the override feature, the system will resume the use of the routing lists. Another feature of the personal number communication system is to allow the subscriber to provide different routing lists for different days of the week or specific time slots within the day. Thus, one routing list may be used on weekdays from 9:00 AM to 6:00 PM, another routing list on weekdays after 6:00 PM, and a third routing list on weekends.
The general operation of the PNS call routing feature can be described in the following steps:
(1) When a call is placed to a subscriber's personal number, the telephone system will intercept the call.
(2) The telephone system will then identify the called number as belonging to a subscriber of the personal number communication system and will then determine the type of service to be provided.
(3) Finally, if the call requires routing, a routing list will be retrieved and call attempts to the various destinations will be made until the subscriber is located; however, if the subscriber cannot be located, the incoming call will be routed to a default destination such as voice mail.
More specifically, when a call is received, the PNS determines if the called personal number requires facsimile services. If so, the system will determine whether the call attempt is a facsimile transmission. If the call is a facsimile transmission, then the call will be redirected to a device to store the facsimile data until the subscriber, at a later time, retrieves this information. If the call attempt is not a facsimile transmission, then the system will determine whether the call is an administration call. An administration call is initiated by the subscriber and allows the subscriber to modify his service options, retrieve any voice mail that might have previously been stored, or obtain download of prior facsimile transmissions.
Finally, if the call requires a routing service, the PNS will identify the calling party and prepare an identification announcement for the subscriber. The identity of the calling party may be determined in several ways. One method is by performing a reverse white pages database lookup using the phone number of the calling party as a search key. Alternatively, the identity can be obtained by prompting the calling party to provide identification information by keypad entries. Once the identity is determined, an identification announcement message is prepared based on the calling parties identification. The PNS also may provide the calling party with a personal greeting from the subscriber, or a standard greeting. The greeting requests the calling party to hold while an attempt to locate the subscriber is performed.
While the calling party is holding, the PNS continues by retrieving a routing list for the subscriber. The routing list can be selected from several routing lists based on the time of day, day of the week, or any other system established criteria. The numbers in the selected routing list will be sequentially accessed until either the call has been successfully routed, rejected, or the list has been exhausted. The routing operation is performed by selecting a first directory number from the routing list and redirecting the telephone call to that number.
If the call is answered, the identification announcement is delivered to the answering party. The answering party is prompted to provide disposition information indicating whether the call is formally accepted of formally rejected. A formal acceptance occurs when the call is answered and the answering party provides and indication that the call is accepted. This indication may take the form of pressing a key on the phone to transmit a particular dual tone multi-frequency (DTMF) signal or simply maintaining the phone in an "off-hook" state for a specific period of time. A formal rejected occurs when the call is answered and the answering party decides not to accept the call. Similar to a formal acceptance, a formal rejected can include pressing a key to transmit a DTMF signal. In addition, the party can return the receiver to an "on-hook" state within a specific period of time. A call is considered to be successfully routed when either a formal acceptance or formal rejection is received. If the call is not formally accepted or formally rejected, then the call is informally rejected. An informal rejected implies that the call was not successfully routing to the destination. This can occur when the call is (a) not answered, (b) a busy signal is received, or (c) the call is answered by an answering machine, recording or error message.
In response to the call being formally accepted, the PNS routes the communication to the successful destination. In response to the call being formally rejected, the PNS routes the communication to a default destination which can be specified by the subscriber. In response to the call being informally rejected, the system then attempts to route the call to the next destination in the routing list and again requests communication disposition information. The system continues to request communication disposition information from each sequential destination in the routing list until the communication is formally accepted, formally rejected or until the last destination on the routing list is reached. Once the destinations on the routing list have been exhausted, the communication is routed to a last or a default destination.
While the PNS has made substantial advances towards providing seamless access to a subscriber, there is a desire for achieving this level of service in a more efficient manner. One method to improve the efficiency of this service would be to include the ability to select a routing list for an incoming call based on the identity of the calling party or a calling line identification (CLID). The need for this capability exists in both the realms of business and personal calls. For instance, a sales representative visiting a first customer's office would not want to have calls from a competing customer routed to him at that location; however, it would be desirable to have calls from an expecting wife routed to that location. In addition, a subscriber may want to route calls differently based on the type of call (i.e., business, personal, solicitations). The ability to route calls based on the identification of the calling party or calling line is advantageous because a subscriber can (a) limit interruptions due to personal calls; (b) reduce the amount of hold time required for business calls by eliminating routing locations where the subscriber would not be found during business hours; (c) give priority service to important calls; and (d) give restrictive service to unwanted calls.
One way to implement this routing capability is to utilize separate routing lists that are selected based on the identification of the calling party, the type of call, or the originating line.
Therefore, there is a need in the art for a method that would route calls to a party based on the identity of the calling party.
Further, there is a need in the art for a method to route calls to a party based on the type or purpose of the call.
Furthermore, there is a need in the art for a method to route calls based on the identity of the originating line.

This patent is subject to a terminal disclaimer.

Method and apparatus for routing calls based on the identification of the calling party or calling line


A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.

The present disclosure relates, in general, to electronics, and more particularly, to semiconductor packages, structures thereof, and methods of forming semiconductor packages.
Prior semiconductor packages and methods for forming semiconductor packages are inadequate, for example resulting in excess cost, poor thermal performance, decreased reliability, relatively low performance, or package sizes that are too large. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure and reference to the drawings.
More particularly, some semiconductor packages include passive components in combination with one or more semiconductor die. In the past, the passive components, such as capacitors, were mounted on a package substrate laterally adjacent to the semiconductor die, which was also mounted to the package substrate. This conventional assembly approach consumed valuable substrate space and significantly increased the overall size of the semiconductor package. Next generation semiconductor packages will require a significant increase in total capacitance value per package, which will significantly grow the size of such packages formed using the conventional assembly approach.
Accordingly, it is desirable to have a package structure and a method that provides a packaged electronic device that overcomes the shortcomings of the prior art. It is also desirable for the structure and method to be easily incorporated into manufacturing flows, accommodate multiple die interconnect schemes, and to be cost effective.

Semiconductor device having a lid configured as an enclosure and a capacitive structure and method of manufacturing a semiconductor device

Amkor Technology Singapore Holding Pte. Ltd.


A device for protecting an electric component for a compressor is provided, where the device is equipped with a bracket formed with an insert portion and a locking part having a locking hole, facing each other; and a cover formed with a clamp for clamping the distal end of the insert portion, and a ratchet fastened to the locking hole, and where the insert portion is formed of a plurality of projections with different length of projected portions in insert direction. This makeup enables only one ratchet to fix the cover securely to the bracket, as well as makes the cover to be resistant to fracture owing to a small distortion of the cover when detaching.

Some conventional devices for protecting an electric component (referred to as "protecting device" hereinafter) with this type can be fixed with a single inserting operation. Such a protecting device is disclosed in Japanese Patent Unexamined Publication No. H02-33478.
Hereinafter a description is made for the above-mentioned conventional protecting device with reference to FIGS. 7 and 8. FIG. 7 is an exploded perspective view of the above-mentioned device and FIG. 8 is an enlarged side view of the above-mentioned device in a state of being mounted.
In FIGS. 7 and 8, electromotive compressor unit 10 containing its electromotive compressing element (not illustrated) is mounted thereon with glass terminal 15 for supplying the above-mentioned electromotive compressing element with electricity. Glass terminal 15 is connected with electric components 19a and 19b for protecting or starting the above-mentioned electromotive compressing element.
Bracket 20, made of a bend formed iron plate, such as a cold-rolled or hot-rolled steel plate, is fastened to electromotive compressor unit 10 so as to enclose glass terminal 15. Bracket 20 is attached thereon with cover 50 for covering electric components 19a and 19b. Bracket 20 has locking holes 45 on the right and left sides bend formed, facing each other across glass terminal 15.
Cover 50 is formed from synthetic resin material such as polypropylene (PP) or polycarbonate (PC), injection molded. Cover 50 has tapered ratchet 70 for engaging locking hole 45, on the inner wall surface at a position corresponding to locking hole 45 provided on bracket 20.
Hereinafter, a description is made for the actions of the protecting device composed as described above.
Electric component 19 is inserted and fixed in glass terminal 15.
When inserting cover 50 for covering electric component 19 into bracket 20, the following actions occur as a result that tapered ratchets 70 touch the right and left sides of bracket 20 having locking holes 45. That is, the right and left wall surfaces provided thereon with ratchets 70 of cover 50 are distorted outward from the right and left sides of bracket 20; tapered ratchets 70 are fastened to locking holes 45 of bracket 20; and cover 50 is fixed to bracket 20 with a single operation.
In the above-mentioned conventional makeup, however, in order to detach cover 50 from bracket 20, the right and left wall surfaces provided thereon with ratchets 70 of cover 50 need to be respectively distorted outward from the right and left sides of bracket 20, to detach ratchets 70 from locking holes 45 of bracket 20. Consequently, cover 50 formed from synthetic resin material may be largely distorted, resulting in fracture.

Device for protecting electric component

Matsushita Electric Industrial Co., Ltd.


An apparatus and method utilize compressed cache lines that incorporate embedded prefetch history data associated with such cache lines. In particular, by compressing at least a portion of the data in a cache line, additional space may be freed up in the cache line to embed prefetch history data associated with the data in the cache line. By doing so, long-lived prefetch history data may essentially be embedded in a cache line and retrieved in association with that cache line to initiate the prefetching of additional data that is likely to be accessed based upon historical data generated for that cache line, and often with no little or no additional storage overhead.

Computer technology continues to advance at a remarkable pace, with numerous improvements being made to the performance of both microprocessors—the "brains" of a computer—and the memory that stores the information processed by a computer.
In general, a microprocessor operates by executing a sequence of instructions that form a computer program. The instructions are typically stored in a memory system having a plurality of storage locations identified by unique memory addresses. The memory addresses collectively define a "memory address space," representing the addressable range of memory addresses that can be accessed by a microprocessor.
Both the instructions forming a computer program and the data operated upon by those instructions are often stored in a memory system and retrieved as necessary by the microprocessor when executing the computer program. The speed of microprocessors, however, has increased relative to that of memory devices to the extent that retrieving instructions and data from a memory can often become a significant bottleneck on performance. To decrease this bottleneck, it is desirable to use the fastest available memory devices possible. However, both memory speed and memory capacity are typically directly related to cost, and as a result, many computer designs must balance memory speed and capacity with cost.
A predominant manner of obtaining such a balance is to use multiple "levels" of memories in a memory architecture to attempt to decrease costs with minimal impact on system performance. Often, a computer relies on a relatively large, slow and inexpensive mass storage system such as a hard disk drive or other external storage device, an intermediate main storage memory that uses dynamic random access memory devices (DRAM's) or other volatile memory storage devices, and one or more high speed, limited capacity cache memories, or caches, implemented with static random access memory devices (SRAM's) or the like. Often multiple levels of cache memories are used, each with progressively faster and smaller memory devices. Also, depending upon the memory architecture used, cache memories may be shared by multiple microprocessors or dedicated to individual microprocessors, and may either be integrated onto the same integrated circuit as a microprocessor, or provided on a separate integrated circuit.
Moreover, some cache memories may be used to store both instructions, which comprise the actual programs that are being executed, and the data being processed by those programs. Other cache memories, often those closest to the microprocessors, may be dedicated to storing only instructions or data.
When multiple levels of memory are provided in a computer architecture, one or more memory controllers are typically relied upon to swap needed data from segments of memory addresses, often known as "cache lines", between the various memory levels to attempt to maximize the frequency that requested data is stored in the fastest cache memory accessible by the microprocessor. Whenever a memory access request attempts to access a memory address that is not cached in a cache memory, a "cache miss" occurs. As a result of a cache miss, the cache line for a memory address typically must be retrieved from a relatively slower, lower level memory, often with a significant performance penalty.
Caching depends upon both temporal and spatial locality to improve system performance. Put another way, when a particular cache line is retrieved into a cache memory, there is a good likelihood that data from that cache line will be needed again, so the next access to data in the same cache line will result in a "cache hit" and thus not incur a performance penalty.
One manner of increasing the performance benefits of caching involves the use of prefetching, which generally attempts to predict future program references, directed to program instructions and/or data accessed by program instructions, and fetch such information into a cache before the information is actually needed. As such, when the information is later requested, the likelihood increases that the information will already be present in the cache, thus averting the potential occurrence of a cache miss.
Prefetching can rely on a number of different algorithms. For example, prefetching may be history-based (also referred to as context-based), whereby access patterns in a program are monitored to attempt to detect repeating sequences of accesses, or even repeating sequences of cache misses. For example, history-based prefetching may be used to detect that whenever a reference to cache line X occurs, it is usually followed by references to cache lines Y and Z. As such, whenever a reference to cache line X occurs, a prefetch engine may be used to automatically initiate a prefetch of cache lines Y and Z so that when the references to those cache lines do occur, the fetches of those lines will be completed, or at least already underway.
One drawback to conventional history-based prefetching algorithms, however, is the requirement for relatively large hardware tables to store detected sequences of accesses. Large size hardware tables tend to occupy too much area on a hardware integrated circuit, and thus add to the cost and complexity of the hardware. Smaller size hardware tables often are incapable of storing enough prefetch history data to appreciably improve performance.
Therefore, a significant need has arisen in the art for a manner of improving the performance of and reducing the storage requirements for a history-based prefetching algorithm.

Compressed cache lines incorporating embedded prefetch history data

International Business Machines Corporation


A non-pneumatic tire with at least one annular band having an inner ring and a deformable outer ring, a plurality of generally flexible web-spokes connecting the inner ring to the outer ring and a ground contacting tread cap affixed to the annular band.

A pneumatic, or air-filled, tire is made of an airtight inner core filled with pressurized air or nitrogen. A tread, usually reinforced with steel belting or other materials, covers this inner core and provides the contact area with the traction surface. The pressure of the air inside the tire is greater than atmospheric air pressure, so that the tire remains inflated even with the weight of a machine resting on it. The air pressure within tires provides a cushioning effect and resistance, sometimes called "air springs", to radial, lateral, and torsion forces that try to deform the tire as the tire hits bumps and holes. A puncture of a pneumatic tire could result in loss of machine traction, control, and stability.
Pneumatic tires also undergo variances in air pressure and tire performance. The pressure inside the tires maintains the radial and lateral stiffness and effective spring rate of the tires. Lower tire pressure (lower spring rate) can create improved traction and increased comfort since the tires "flatten" slightly and increase the contact with the traction surface. A lower spring rate, however, can also reduce machine stability, reduce handling capability and increase rolling resistance due to added radial and lateral deflections. Higher tire pressures (higher spring rates) can reduce rolling resistance, but traction may be reduced creating a potential loss of control.
Many machine users do not set and maintain their tire pressure properly. This may result in improper machine orientation, and spatial attitude, thereby creating situations which could result in loss of control or stability.
Pneumatic tires are also susceptible to changes in temperature, which can change the tire's internal pressure and spring rate. Over-inflation may increase the potential for a tire or wheel rim rupture. In addition, pneumatic tires are inherently plagued with variations in loaded rolling radii, and this condition is typically amplified with increased tire pressures. This variation in rolling radii creates uneven instantaneous heights (single wheel/tire) and uneven side-to-side heights (multiple wheel/tires) leading to reduced implement performance. For example, uneven side-to-side heights in a riding mower may result in uneven cuts due to an out of level cutting deck as well as operator discomfort due to vibration and bounce.


Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.

For the design of digital circuits (e.g., on the scale of Very Large Scale Integration (VLSI) technology), designers often employ computer-aided techniques. Standard languages such as Hardware Description Languages (HDLs) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general-purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL) or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing an integrated circuit with an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes at some level the circuit elements, and the compiler produces an RTL netlist from this compilation. The RTL netlist is typically a technology independent netlist in that it is independent of the technology/architecture of a specific vendor's integrated circuit, such as field programmable gate arrays (FPGA) or an application-specific integrated circuit (ASIC). The RTL netlist corresponds to a schematic representation of circuit elements (as opposed to a behavioral representation). A mapping operation is then performed to convert from the technology independent RTL netlist to a technology specific netlist, which can be used to create circuits in the vendor's technology/architecture. It is well known that FPGA vendors utilize different technology/architecture to implement logic circuits within their integrated circuits. Thus, the technology independent RTL netlist is mapped to create a netlist, which is specific to a particular vendor's technology/architecture.
One operation, which is often desirable in this process, is to plan the layout of a particular integrated circuit and to control timing problems and to manage interconnections between regions of an integrated circuit. This is sometimes referred to as "floor planning". A typical floor planning operation divides the circuit area of an integrated circuit into regions, sometimes called "blocks," and then assigns logic to reside in a block. These regions may be rectangular or non-rectangular. This operation has two effects: the estimation error for the location of the logic is reduced from the size of the integrated circuit to the size of the block (which tends to reduce errors in timing estimates), and the placement and routing typically runs faster because as it has been reduced from one very large problem into a series of simpler problems.
After placement of components on the chip and routing of wires between components, timing analysis (e.g., timing simulation, or static timing analysis) can be performed to accurately determine the signal delays between logic elements. Back annotation can be performed to update a more-abstract design with information from later design stages. For example, back annotation reads wire delay information and placement information from the placement and route database to annotate the logic synthesis design. Back annotated delay information can be used to identify critical paths where the timing requirements are not satisfied; and logic synthesis may be improved to meet the timing requirements.
A typical software program for logic synthesis uses a delay estimator function based on the fanout of a net. Since all logic elements corresponding to a net with a certain fanout are assumed to have the same wire delay, the estimated delay information is not very accurate. In reality the wire delay depends on the length of the wire routed from one logic element to the next logic element. There is a higher correlation between placement distance and wire delay than between fanout and wire delay. Due to the error in the delay estimator in logic synthesis, a solution appears to be valid during logic synthesis may be found invalid after the placement and routing operation.
After the design layout (e.g., the placement and routing), only limited optimizations like resizing or buffering (known as in place optimizations) are typically performed. However, in place optimizations can provide only limited improvements. When the in place optimization cannot adjust the solution to meet the timing constraint, adjustment to the logic synthesis may be performed, leading to the expensive iteration between logic synthesis and placement and routing.
Synthesis and optimizations of logic circuits for reducing the delay of critical paths is an important step in designing and implementing a logic circuit. It is desirable to have accurate wire delay information to obtain optimization results of good qualities, since inaccurate delay estimation in the synthesis stage may lead to invalid design layout. If logic synthesis has to be improved to meet the timing requirement (e.g., slack requirement), expensive iterations between synthesis and design layout have to be performed. Note that slack is the difference between the desired delay and the actual (estimated or computed) delay. When the desired delay is larger than the actual delay, the slack is positive; otherwise, the slack is negative. Typically, it is necessary to make the slack positive (or close to zero) to meet the timing requirement (e.g., through reducing the wire delay to increase the slack). For example, during synthesis, a total negative slack algorithm (e.g., used in a circuit design compiler, Synplify, available from Synplicity, Inc., California) considers all instances whose slack is negative as candidates for improvement, since any one of the candidates with negative slack could become critical after physical design. It is typical to make the slack positive to ensure that the timing requirements are met.

Method and apparatus for automated circuit design


In a system for location estimation, information necessary for location estimation is acquired from a wireless signal. The first estimated location of each of target terminals is found out on the basis of the acquired information necessary for location estimation, and the locations of reference terminals. The second estimated location of each target terminal is found out on the basis of the information necessary for location estimation, the first estimated locations of the target terminals other than that target terminal of which the location estimation is being carried out, and on the locations of the reference terminals. Thus, the system for location estimation avoids the problem associated with an increased sphere of location estimation and with an increased communication traffic attendant on an increased number of target terminals, and achieves location estimation of high accuracy.

1. Field of the Invention
The present invention relates to a system for estimating the location of a wireless terminal on the basis of received wireless signals. More particularly, the present invention relates to such a system for high accuracy location estimation.
2. Description of the Background Art
A conventional system for location estimation includes a wireless terminal, the location of which is to be estimated, i.e. a target terminal, and three or more wireless terminals, the locations of which are known from the outset, i.e. reference terminals, which are adapted to transmit packets to respective neighboring terminals. The packets include identification codes proper to the respective terminals. On receipt of the packets, the respective terminals determine that the transmitting terminals stay within the range of possible signal delivery, and accordingly add the transmitting terminals to a list of neighboring terminals they have. When the transmissions between the totality of the terminals have come to an end, the lists of neighboring terminals are collected from those terminals to a location estimation device (sink terminal) and stored in the latter. The location estimation device progressively uses the obtained relationship of interconnection of the terminals and the locations of the reference terminals to narrow down the sphere of possible presence of the target terminals. More specifically, the system for location estimation deems that the distance between terminals, between which a packet has been transmitted with success, is less than the distance which allows for signal delivery, while deeming that the distance between terminals, between which a packet has not been transmitted with success, is not less than the distance which allows for signal delivery. The system for location estimation accordingly determines the distance between terminals in two stages, that is, a distance longer than the range of possible signal transmission and a distance not longer than the range of possible signal transmission, in order to effect location estimation. This is disclosed, for example, in N. Sundaram and P. Ramanathan, "Connectivity Based Location Estimation Scheme for Wireless Ad Hoc Networks", IEEE Globecom 2002, pp. 143-147.
It is also known to model the relationship between the distance between the terminals with the power of received signals with the fading occurring on a wireless transmission path taken into account, and to estimate the location of a target terminal from the location of a plural number of reference terminals and an estimated distance between the target terminal and the reference terminals. It is likewise known to effect signal reception a number of times to diminish the effect of fading to improve the accuracy in location estimation. Those are disclosed, for example, in U.S. Pat. No. 6,473,038 to Patwari, et al., and Kentaro Yanagihara, et al., "A Maximum Likelihood Estimation Method of Localization using RSSI in Wireless Sensor Networks", Technical report of IEICE, the Institute of Electronics, Information and Communication Engineers, IN2004-327. pp. 409-414.
However, with the conventional system for location estimation, if an area as the subject of location estimation becomes larger, then the more reference terminals have to be disposed. Moreover, if location estimation is to be improved in accuracy, it is necessary to install the reference terminals at a higher density to gather as much information as possible at the location estimation device. If the number of the target terminals is increased, the traffic of communication for location estimation is also increased. The amount of the information to be gathered is proportional to the product of the density of the reference terminals and the number of the target terminals. If the traffic of the communication for location estimation is increased, there is a possibility that the communication is deteriorated in quality. Hence, there is raised a demand for a system for location estimation may be moderated in which the problem associated with an increased communication traffic accompanying an increased sphere for location estimation and an increased number of target terminals, and at the same time high precision location estimation may be assured.
In addition, with the conventional system for location estimation, it is presupposed that the target terminals are immovable, so that, if target terminals are moving, location estimation accuracy may be lowered. Hence, there is raised a demand for a high precision system for location estimation capable of coping with a movable target terminal as a subject of location estimation.

Method and a system for location estimation using location estimated


A simulator includes a binary translator to translate target code into host instructions to be executed on a host processor. To identify target instructions which may be modified by self-modifying code, the simulator determines whether a target instruction to be translated resides in a writeable page, and if so, inserts a run-time check into a translation cache along with translated instructions corresponding to such target instructions.

Simulators may use binary translation to translate a target machine instruction into one or more host machine instructions. These translated instructions may enable the simulated program (after translation) to execute natively, e.g., directly on the host processor. The simulator may invoke the binary translator only for a part of the application actually executed by the processor.
Binary translation may be used to develop an instruction set architecture (ISA) for a new processor, since the ISA of the new processor may be different from the ISA of the host processor on which the simulator runs. Binary translation may also be used to port legacy code from a legacy ISA to a new architecture.

Binary translation of self-modifying code


The present invention is organized about the concept of providing an improved pawl brake assembly for use in electromechanical devices such as all electric motors or solenoids. For example, the improved pawl brake assembly may be used for braking the rotor assembly upon de-energization of the motor. The pawl brake assembly comprises a pawl arm and a brake portion. The pawl brake assembly employs electromagnetic principles to reduce the noise and metal fatigue caused by the undesired excess vibrational motion of a pawl arm wen a motor is energized. The novel use of a magnet disposed upon the pawl arm of a pawl brake assembly provides a single, elegant, and inexpensive solution to the identified noise and metal fatigue problems.

This invention relates in general to electric motors and solenoids, and in particular to an improved pawl brake assembly for any electric motor or solenoid.
Many electric motors manufactured today use a pawl brake assembly to stop the movement of the rotor assembly when the motor is de-energized. Typically, in prior art brake designs when a motor is de-energized, the magnetic field generated in the stator core diminishes causing a spring in cooperative contact with the pawl brake assembly to pull the pawl brake into frictional engagement with the rotor assembly.
A disadvantage with prior art pawl brake assembly designs is that when the motor is energized, the portion of the pawl arm proximate to the motor lamination stack has excess vibrational movement. This excess movement causes the pawl arm to rattle and bump against the motor lamination stack, resulting in undesirable noise levels. Thus, there is a need in the art for a solution to the noise and metal fatigue caused by the excessive movement of the pawl arm of a pawl brake assembly.
The present invention is organized about the concept of providing an improved pawl brake assembly for use in electromechanical devices such as all electric motors or solenoids. For example, the improved pawl brake assembly may be used for braking the rotor assembly upon de-energization of the motor. The pawl brake assembly employs electromagnetic principles to reduce the noise and metal fatigue caused by the undesired excess motion of a pawl arm when a motor is energized.
In an exemplary embodiment according to the invention, the pawl brake assembly comprises a pawl arm and a brake portion in pivotal engagement with one another. The pawl arm may be composed of any metal alloy subject to the influence of a magnetic field, and the brake portion may be composed of any material such as plastic. The pawl arm may comprise a first end, a second end, and an extending trigger portion radially disposed between the first end and the second end of the pawl arm. The movement of the first end of the pawl arm is governed by pivotal contact with a fastener used to secure a bearing retainer to the stator assembly of an electric motor. The radially extending trigger portion of the pawl arm is in pivotal contact with the brake portion of the pawl brake assembly, e.g. via a pivotal groove.
To reduce noise and metal fatigue caused by excess vibration of the pawl brake assembly, a permanent magnet, e.g. a magnetic strip, is disposed on the second end of the pawl arm. When the motor is energized, sufficient magnetic attraction is established between the stator assembly and the magnetic strip to force and hold the second end of the pawl brake arm against the motor lamination stack. Significantly, the vibration common to prior art is eliminated. The absence of excess vibrational movement on this portion of the pawl brake assembly results in quiet operation of the motor.

Pawl brake assembly for an electric motor


A user of a calendar application subscribes to a syndication feed corresponding to an event recorded at the calendar application in a calendar data format. The syndication feed commences sending feed data to the user upon occurrence of the event. The feed data indicates a status of the event. The syndication feed binds to a feed data entry in the calendar application that is associated with the calendar item. The feed data of the syndication feed is converted from a feed format to the calendar data format usable by the calendar application to produce converted feed data. The converted feed data is presented in the calendar application proximate to the calendar item. One or more of the subscribing, binding, converting, and presenting is performed by a computing device.

Embodiments of the present invention relate to the field of calendar data exchange technologies.
Internet Calendaring and Scheduling Core Object Specification (iCalendar) is a standard for calendar data exchange, which is defined by Request for Comments (RFC) 2445 of the Internet Engineering Task Force (IETF). This standard permits the exchange of meetings times, to-do entries, and other data among compliant applications. ICalendar data is typically exchanged using traditional email programs; however the standard is designed to be independent of any transport protocol. Currently, Web servers exist that distribute iCalendar data about an event and publish these event times to a group of interested people. Further, iCalendar data is presently being embedded in Web pages, typically using hCalendar, which is a microformat representation of iCalendar in semantic (X)HTML. Generally, users are able to publish and subscribe to iCalendar data.
A syndication feed, such as a Really Simple Syndication (RSS) or an ATOM feed, are used to provide items containing short descriptions of Web content together with a link to a full version of the content. Syndication feeds are used to publish frequently updated content, such as BLOG entries, news headlines, or podcasts. Feed content can be read using a feed reader or an aggregator. That is, users subscribe to a feed by entering the feed's link into the reader. The reader regularly checks subscribed feeds for new content and downloads any new content related to these feeds.
At present, syndication feeds and iCalendar data are disparate and incompatible mechanisms through which users can acquire time linked information. No current program or mechanism exists for binding syndication feeds to iCalendar entries.

Adding syndication feeds to calendar application items

INTERNATIONAL BUSINESS MACHINES CORPORATION


A method for identifying a protein as being able to bind a ligand comprising, providing a molecule composed of a methotrexate moiety that is covalently bonded to the ligand; introducing the molecule into a cell which a) expresses a first fusion protein comprising a dihydrofolate reductase capable of binding methotrexate, expresses b) a second fusion protein comprising the protein, wherein one of the first and second fusion proteins also comprises a transcription activator domain and the other comprises a DNA-binding domain, and c) has a reporter gene wherein expression of the reporter gene is conditioned on the proximity of the first fusion protein to the second fusion protein; permitting the molecule to bind to the first fusion protein and to the second fusion protein so as to activate the expression of the reporter gene; and selecting the cell if it expresses the reporter gene.

Initial efforts to design protein catalysts (enzymes) relied on the modification of individual proteins. (Kaiser 1984; Knowles 1987) Despite some successes, (Wharton 1985; Wilks 1988; Hilvert 1985, 1989, 1994; Imperiali 1994; Johnson 1993) protein engineering has proven to be difficult and has suggested that notions of how enzymes work may still be naive. Combinatorial techniques, which rely on generating and screening large pools of protein variants simultaneously, offer a promising new approach to enzyme design. (DeGrado 1997) Several straightforward methods exist for generating large libraries (>1012) of proteins rapidly. (Reidharr-Olson 1991; Eisenbeis 1985; Wells 1985; Zoller 1983; Leung 1989; Crameri 1998; Zhang 1997, 1999; Stemmer 1994(a); Stemmer 1994(b)) Methodologies for identifying protein catalysts from libraries of proteins primarily have been based not on catalysis, but on binding to a transition-state analog, (Wagner 1995, 1998; Shokat 1989) as in the case of catalytic antibodies (Schultz 1989; Schultz 1995; Hilvert 1985, 1989, 1994; Posner 1994) and phage-display (Baca 1997). While antibodies clearly can catalyze a broad range of reactions, there are few reports (Jacobsen 1992) that selections for binding can generate catalysts that rival natural enzymes. In vivo complementation of essential enzymes, such as chorismate mutase and triosephosphate isomerase, offers a direct selection for catalysis but is limited to existing reactions. (Hermes 1990; Kast 1996) General screens and selections for catalysis are beginning to be reported. (DeGrado 1997; Koltermann 1998; Pedersen 1998)
Combinatorial techniques allow structure-activity relationships of enzymes to be amassed quickly. With the aid of powerful selections it should be possible to create synthetically useful catalysts for pharmaceuticals and materials. However, as with proteins, it is difficult to design screens for non-protein catalysts.
Screens have been developed based on small-molecule inducible gene expression. Several systems for small-molecule inducible gene expression have been developed to the point that they are integral to basic research. The discovery that the lac operon is induced by binding of lactose to the lac repressor led to the widespread use of isopropyl-b-D-thiogalactoside (IPTG) to induce gene expression in bacteria. More recently it has been shown that by fusing the tet repressor to a eukaryotic transcription activation domain, gene expression in eukaryotes can be both negatively and positively regulated using tetracycline.(Gossen 1992, Gossen 1995). The demonstration that transgene expression can be regulated with tetracycline in transgenic mice highlights the utility of this system. In addition to the tetracycline-based system, ecdysone-, (No) estrogen-, (Braselman 1993) and progesterone-regulated systems (Wang 1994) have been reported.
An extension of these strategies resulted from studies of the mechanism of action of the immunosuppressants FK506 and rapamycin. (Rosen 1992) It was found that the biological activity of both compounds resulted from the fact that they each dimerize two proteins, FKBP12 and calcineurin or FKBP12 and FRAP, that otherwise do not interact. One portion of FK506 binds to FKBP12 and another to calcineurin. Based on this understanding, it was demonstrated that these molecules could be used to control protein oligomerization inside a cell.
Molecules such as FK506 are small molecule 'dimerizers' (sometimes referred to as chemical inducers of dimerization, CIDs) that activate the function of numerous proteins that regulate many important cellular processes. Dimerizers allow the functions of proteins to be explored even when small molecule ligands are unknown. A limited number of such reagents have been synthesized that control the function of a much larger number of proteins (expressed as fusions of proteins of interest linked to a small molecule-responsive dimerization domain). See, e.g. Austin 1994, Choi 1996, Crabtree 996, Diver 1997, Ho 1996, Holsinger 1995, Hung 1996, Klemm 1998, Liberles 1997, Pruschy 1994, Schreiber 1998, Spencer 1996, Spencer 1995, Spencer 1993, Stockwell 1998, and Yang 1998.
To generalize this approach, it was shown in 1993 that two FK506 molecules tethered via their C21-allyl groups could oligomerize proteins fused to FKBP12. Specifically, several FK506 dimers termed "FK1012s" were shown to oligomerize the cytoplasmic domain of T-cell receptors when these domains were fused to the FK506-binding protein FKBP12. Since this initial paper, there have been several important extensions of this work by Schreiber and coworkers. Belshaw et al. reported in 1996 that two different proteins could be dimerized by tethering FK506 to cyclosporin. In 1997 Diver and Schreiber demonstrated a two-step synthesis of an FK1012 molecule based on recent olefin metathesis chemistry.
While this work with FK506 establishes a powerful new approach for manipulating cellular function with small molecules, optimized chemical handles that are more convenient to work with than FK506 are critical for realizing the potential of this approach. FK506 (FIG. 5B) is cell permeable and has excellent pharmacokinetic properties—as evidenced by its widespread use as an immunosuppressant. FK506, however, is not an ideal chemical handle. FK506 is not available in large quantities, coupling via the C21 allyl group requires several chemical transformations including silyl protection of FK506, (Spencer 1993, 1995, 1996; Pruschy 1994) and FK506 is both acid and base sensitive.(Wagner 1998; Coleman 1989)
One very recent approach to replacing FK506 is to design synthetic ligands that also bind to FKBP12 with high affinity. In 1997 Amara at al. reported AP1510, a synthetic dimerizer that binds FKBP12 with high affinity and that can oligomerize proteins fused to FKBP12. Very recently a derivative of AP1510, "5S", was prepared that binds with high affinity to a FKBP12 mutant. (Clackson 1998) This derivative is particularly interesting because it does not bind with high affinity to wild type FKBP12.
Recently a system has been reported, named the yeast three-hybrid system, for detecting ligand-receptor interactions in vivo. (Licitra, represented in FIG. 2; U.S. Pat. No. 5,928,868) This system is based on the principle that small ligand-receptor interactions underlie many fundamental processes in biology and form the basis for pharmacological intervention of human diseases in medicine. This system is adapted from the yeast two-hybrid system by adding a third synthetic hybrid ligand. The feasibility of this system was demonstrated using as the hybrid ligand a dimer of covalently linked dexamethasone and FK506. The system used yeast expressing fusion proteins consisting of a) hormone binding domain of the rat glucocorticoid receptor fused to the LexA DNA-binding domain and b) FKBP12 fused to a transcriptional activation domain. When the yeast was plated on medium containing the dexamethasone-FK506 heterodimer, the reporter genes were activated. The reporter gene activation is completely abrogated in a competitive manner by the presence of excess FK506. Using this system, a screen was performed of a Jurkat cDNA library fused to the transcriptional activation domain in yeast in the presence of a methasone-FK506 heterodimer. The yeast in this system expressed the hormone binding domain of rat glucocorticoid receptor/DNA binding domain fusion protein. Overlapping clones of human FKBP12 were isolated. These results demonstrate that the three-hybrid system can be used to discover receptors for small ligands and to screen for new ligands to known receptors.
Other approaches, which do not rely on a readout based on alterations in genetic expression, have also been developed. WO 96/30540 (Tsien et al.) discloses a screen for β-lactamase activity that uses fluorescence resonance energy transfer as the indicator of β-lactamase activity. The degree of fluorescence in this screen depends on the level of β-lactamase activity. Detection of β-lactamase activity relies on detection of changes in the degree of fluorescence.
However, it has not heretofore been suggested to use small molecule induced protein dimerization to screen for catalysis in vivo, and specifically, it has not been suggested to use an enzyme cleavable moiety to link two molecules to dimerize proteins.
This invention provides proteins de novo with prescribed binding and catalytic properties and permits screening cDNA libraries based on biochemical function. Being able to understand and manipulate protein-small molecule interactions has broad implications for basic biomedical research and the pharmaceutical industry. Proteins engineered to have unique binding or catalytic properties have already proven useful as biomedical reagents, medical diagnostics, and even therapeutics. As with site-directed mutagenesis before it, randomization and screening techniques also offer an entirely new approach to understanding the molecular basis for recognition and catalysis. Technically, a high-throughput approach such as that disclosed here would speed-up the research because the activity of thousands of protein variants can be measured simultaneously. Practically, we believe that powerful screens in combination with existing randomization techniques will make it possible to take an existing protein fold and "evolve" it into an enzyme with a new function generating useful catalysts for the pharmaceutical and chemical industries. Intellectually, the ability to modify substrate specificity and catalytic activity offers a new standard for "understanding" how enzymes function. A powerful screen is also critical to the end goal of genome sequencing efforts-determining the function of each and every protein, bypassing decades of detailed biochemical and genetic experiments to unravel complex biochemical pathways. Since the screen is done in vivo and in both prokaryotes and eukaryotes, the methodology can be applied to functional genomics and drug discovery. A cDNA library can be screened for all enzymes that form or cleave a specific type of bond. A library of small molecules can be screened for its ability to inhibit a specific enzyme. The screen selects for cell permeability, compatibility with the cellular milieu, and inhibition of enzyme activity. The key to all of these applications is a robust screen for enzymatic activity such as that disclosed here.

Methods and assays for screening protein targets

The Trustees of Columbia University in the City of New York


A radio frequency energy radar system having a transmitting antenna system for transmitting and directing CW radio frequency energy toward a target. A receiving antenna system, adjacent to the transmitting antenna system, receives portions of the transmitted CW radio frequency energy reflected by the target. The receiving antenna system including a plurality of antenna elements disposed along a path and arranged to provide an antenna pattern having a main lobe antenna pattern directed toward the target and adjacent side lobe antenna pattern. A septum is positioned between the transmitting antenna and the receiving antenna, for shielding unwanted portions of the transmitted CW radio frequency energy from passing directly from the transmitting antenna to the antenna elements of the receiving antenna The shielding means terminates along an edge positioned in a region forward of the antenna elements. The distances between the antenna elements and points along the edge are selected to produce a non-uniform phase distribution of unwanted CW energy scattered by the edge and received by the antenna elements, such phase distribution being selected to enable the receiving antenna system to focus such unwanted scattered energy into the side lobe antenna pattern, thereby decreasing the amount of coupled energy from the transmit array to the receive array.

This invention relates generally to continuous wave (CW) radar systems and more particularly to the isolation between transmit and receive antennas used in such systems.
As is known in the art, continuous wave radar systems have a wide variety of applications. In one such system, the transmitting antenna and the receiving antenna are mounted adjacent one another on a common platform. Both the transmitting antenna and the receiving antenna have a plurality of horizontal rows of dipole antenna elements. The antenna elements of each row are coupled, in-phase, to a common feed port through a corporate feed network. Thus, each row of antenna elements produces an antenna pattern having a narrow main lobe, at the center of the row, directed into free space perpendicular to the row. A phase shifting network connects the feed ports of the transmitting antenna to the transmitter, and a phase shifting network connects the feed ports of the receiving antenna to the receiver. The relative phase shifts in the phase shifting networks enables the transmitting antenna and the receiving antenna to point their main lobe antenna patterns at the same desired elevation angle. Thus, the rotation of the transmitting and receiving antennas together as a unit about a vertical axis provides an azimuthal scan. Sequentially changing the relative phase shift provided by the phase shifting networks provides an elevation scan. During the scan, radio frequency energy is transmitted by the transmitting antenna and directed into free space. If the transmitted energy encounters a radar energy reflecting target, a portion of the reflected energy is received by the receiving antenna. The detection of such received energy indicates the presence, or acquisition of, a potential target. It is noted that during operation, the radar transmitter and receiver are on simultaneously for a continuous wave radar system.
For proper operation, it is highly desirable to prevent, or at least reduce to a minimum, the amount of transmitted energy passing directly from the transmitting antenna to the receiving antenna. Excessive power causes an increase in receiver noise above thermal noise and may require additional attenuation in the receiver, limiting the radar's receiver dynamic range. One technique used to provide this isolation is to insert a shield, or septum, between the two antennas. The septum is a planar conductive sheet, positioned in the horizontal plane between the transmitting and receiving antenna elements. Thus, if the sheet were of long enough, transmitted energy would be prevented from passing directly to the receiving antenna. However, as the length of the sheet is increased, the maximum elevation angle is correspondingly reduced. Thus, the system uses a shield of having a length limited by the maximum required elevation angle.

Antenna isolation for continuous wave radar systems


Disclosed are liquid crystalline polymer compositions, which are melt moldable, and which contain a perfluorinated polymer, and a particulate aramid, and optionally contain hollow glass or quartz spheres, and which usually have low dielectric constants. They are particularly useful as electrical connectors and substrates for other electronic applications which use high frequency signals.

Many types of materials are used as substrates for fabricating electrical connectors. One particular property of these materials, dielectric constant, is important when dealing with high frequency signals. If the dielectric constant of the substrate is too high, these signals may be attenuated to such a degree that the electronic apparatus does not function as designed. Therefore these substrates, particularly for this type of application, should have as low a dielectric constant as possible. However complicating this situation is the fact that other properties are also necessary and/or desirable in such substrates, such as good strength, resistance to high temperatures, good fire resistance, and good formability, etc. Making such compositions is a challenge, since improving one particular property often leads to deterioration of another (desired) property. Thus such compositions are constantly being sought.
U.S. Pat. No. 5,398,990 describes LCP compositions containing hollow glass spheres and polytetrafluoroethylene. The presence of aramids is not mentioned.
European Patent Application 512,401 describes certain laminates having low dielectric constants. The resin compositions contain molecularly porous aerogels, not hollow glass or quartz spheres.
Japanese Patent Application 0455437 describes a prepreg material which is made from a fluoroplastic, hollow glass spheres, and a cloth or paper-like material which can be an aramid. This material may be saturated with a thermosetting resin such as an epoxy resin, but LCPs aren't mentioned.

Liquid crystalline polymeric compositions


Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials to thereby form channel regions having enhanced mobility characteristics.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a 3-dimensional structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
Device designers have recently employed channel stress engineering techniques on FETs to improve the electrical performance of such devices, i.e., to improve the mobility of the charge carriers. More specifically, such stress engineering techniques generally involve creating a tensile stress in the channel region for an NMOS transistor and creating a compressive stress in the channel region for a PMOS transistor. Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of an NMOS transistor would only be formed above the NMOS transistors. Conversely, for PMOS transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PMOS transistor is formed above the PMOS transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art. Other techniques employed to induce the desired stress on a FET involves forming recesses or cavities in the substrate where source/drain regions will be formed and thereafter forming a stress-inducing material, such as an epitaxially formed silicon/germanium material, in the cavities to induce the desired stress in the channel region of the transistor.
In general, stress engineering techniques for FinFETs have generally involved forming stress-inducing layers of material over or within the source and drain regions of the FinFET. As noted above, a FinFET is a 3-dimensional device where stress engineering techniques may be very complex to implement. Therefore, there is a need for various methods and structures to improve carrier mobility in FinFETs.
The present disclosure is directed to various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials to thereby enhance the performance characteristics of such 3D devices by forming channel regions having enhanced mobility characteristics.

Methods of forming enhanced mobility channel regions on 3D semiconductor devices, and devices comprising same


A method of capturing the coordinates of a handwritten signature and compressing the coordinate data so obtained. The signature is captured in real time by a device such as a stylus-operated digitizer. Compression is performed by examining the location of the signature points relative to a series of guide lines extending in the strokewise direction. The data is stored in compressed form for use in subsequent transactions requiring authorization by the signature which has been so captured.

This invention relates to a method of recording a handwritten message such as a signature in digitized form. It has particular application to commercial transactions wherein a handwritten signature is captured at a point of sale and is stored for later use to authenticate the transaction, authorize an automatic account debit or the like. The invention is particularly well suited for use with merchandising systems of the type disclosed in Allgeier et al, application Ser. No. 575,096, filed Aug. 30, 1990 and in Kapp et al, application Ser. No. 640,199, filed Jan. 11, 1991, the disclosures of which are incorporated herein by reference.
Merchandising systems as described in the above-mentioned patent applications are equipped with a transparent glass screen having a resistive coating fused to its surface. A linearized voltage field is established on the surface of the screen. A human signature is captured by providing a hand-held stylus which is moved across the surface of the screen during writing of the signature. A digitizer senses the position of the stylus during writing of the signature and generates digital signals representing the X-Y coordinates of the stylus. The digitized coordinates are stored in a memory and are also used to drive a liquid crystal display positioned below the glass screen. This produces a visual display of the signature, as the handwriting progresses. Means are provided for maintaining the signature in registration with the movement of the stylus, as disclosed in detail in the above-mentioned patent applications. Preferably, a skew correction is employed in the signature registration as disclosed in Crooks et al, Ser. No. 640,321, filed Jan. 11, 1991, also incorporated herein by reference.
The system of the above applications preferably includes a work station such as an NCR 7052 Work Station equipped with a built-in microprocessor and a keyboard for entering transaction data. A printer may be provided for printing transaction data and a replica of the signature on a suitable paper receipt.

Method of recording a handwritten message


A transformation technique for nested loops. A virtual iteration space may be determined based on an unroll factor (UF). The virtual iteration space, which includes the actual iteration space, is fanned such that, the virtual iteration space may be evenly divided by a selected UF. Once the virtual iteration space has been calculated or determined, the virtual iteration space is “cut” into regular portions by one or more unroll factors. Portions of the actual iteration space which do not fill the cut portions of the virtual iteration space or which fall outside these cuts which have been evenly divided by the unroll factor form a residue which is calculated. The portions of the actual iteration space which remain arc also evenly divided by the unroll factor(s). An outer loop for this remaining portion of the actual iteration space is then unrolled. This unrolled portion forms a perfect nested loop.

Generating computer code that is efficiently processed (i.e., "optimized") is one of the most important goals in software design and execution. Computer code which performs the desired function accurately and reliably but too slowly (i.e., code which is not optimized) is often discarded or unused by the computer users.
As those of ordinary skill in the art are aware, most source code (i.e., that code which is a human readable form) is typically converted into object code, and thereafter an executable application by use of a compiler and a linker. The executable application is in a form and language that is machine readable (i.e., capable of being interpreted and executed by a computer). Other languages, such as Java available from Sun Microsystems, Inc. of California, USA, may be in source code form that is, on execution, transformed into a form understood by a computer system which then executes the transformed instructions. In any case, the source code, when transformed into a form capable of being understood and executed by a computer system, is frequently optimized. That is, a transformation is performed such that the instructions are performed more efficiently (i.e., optimized) and, hopefully, without any undue delay.
One common structure found in source code is a loop. Nested loops—a loop within another loop—are also common in the art. Loops are used to repeat one or more operations or instructions. For example, an array may be used to store the purchase price of individual articles (e.g., where the ith element in the array A is denoted, in Fortran, as A(i)—other similar notations are used in other languages generate a single instruction to add each of the purchase prices together (e.g., sum=A(1)+A(2)+ . . . +A(n)). This however would take the programmer some time to code and is not easily adapted to the situation where the computer programmer does not know, at development time, the number of articles in the array. That is, when the number of elements in the array can only be determined at run time (i.e., during execution). Accordingly, the loop was developed to repeat an operation (e.g., sum=sum+A(i))) where the induction variable, i, is changed for each iteration. Other forms of loops are known and are equally applicable. However, when the instructions of loop are transformed into machine readable code (e.g., executable code), the executed instructions may not be processed efficiently. For the example above, some computer systems may require that the processor fetch from memory, rather than from a register or cache memory, the various elements of the array "A". Fetching data from memory requires the processor to wait while the data is retrieved. Also, while loops may be an efficient way to write certain repetitive source code operations, a loop does insert additional operations that would not be present if the repetitive operations were replicated. These additional operations (e.g., branching operations) are considered to be the loop "overhead".
To address some of the inefficiencies in processing loops, various optimization techniques have been created and applied. For example, one optimization technique is to unroll portions of the loop (hereinafter "unrolling"), replicate the portions and then insert the replicated portions into the code (also known as "jamming"). Typically, when the unroll and jam loop transformation technique is applied to the outer loop of a nested loop pair, the outer loop's induction variable (e.g., "i") is advanced only a few times (the number of times being governed by a parameter referred to as the unroll factor—UF) rather than completely during the unrolling portion of this optimization technique. During the jamming portion of this technique, the inner loop would be replicated "UF" times. Persons of ordinary skill in the art will appreciate that the replicated loop bodies are not identical but only similar. In the replicated loop bodies, portions of the loop bodies which use the induction of the outer loop will be advanced as required (e.g., if the loop body included reference to array element A(i), where "i" is the outer loop induction variable, a replicated loop body would include reference to the next required array element—A(i+1)). The unroll and jam technique effectively reorders the calculations being performed in the nested loop.
The "unroll and jam" technique does offer some advantages but also has some disadvantages.
One disadvantage of the unroll and jam technique is that residues are created. Residues form the portion of a loop that is would not be executed when the loop is unrolled by a fixed factor—the unroll factor. That is, since the controlling induction variable of the unrolled outer loop is advanced a fixed number of times in every iteration, if the upper bound does not divide evenly by the unroll factor (i.e., when there is a remainder or, the modulus of the upper bound of the outer loop induction variable "i" and the unroll factor is not zero), then code must be generated to address this remaining portion —the residue. Code generated to handle these residues may add overhead and inefficiencies that can result in performance degradation.
The unroll and jam technique, as a result of the creation of code to address the residue problem, introduces some significant disadvantages. Notable amongst these disadvantages is that the creation of the residue causes perfect triangular nested loops (i.e., nested loops where the inner loop induction variable—"j"—is bounded on the upper end by the value of the outer loop induction variable "i") to no longer be "perfect". As a result, other optimization techniques which are only applicable to perfect loop nests cannot be additionally applied. Therefore, using the unroll and jam technique eliminates use of many further optimization techniques.
Other optimization techniques known to those skilled in the art do not scale well. That is, the optimization techniques may provide some benefit when applied to a nested loop pair (i.e., only two dimensions). However, such techniques are not known to the inventors of the present invention to be applicable or easily applicable to nest loops of three or greater dimensions.
Accordingly, an optimization technique which addresses at least some of these shortcomings would be desirable.

Unrolling transformation of nested loops


An air intake device offers simplified construction, reduced size, lowered cost, etc., while facilitating disposing of throttle body and driving part in intake air passage, allowing throttle body to be reliably held, and eliminating possible occurrence of intake air leakage, etc., thus positively securing the performance. The air intake device includes an actuator and an intake air manifold made of resin. In actuator, there are provided a throttle body, a throttle valve, a motor for opening/closing throttle valve, and a power transmission mechanism. Throttle valve and motor are positioned and held on one side of a support member, and power transmission mechanism is on the other side. In intake air manifold, a housing chamber is provided. When a fixing part of support member is jointed to a part to be fixed of intake air manifold, throttle body and motor are accommodated in a predetermined position in housing chamber.

With an electronic throttle device disclosed in the following Patent Document 1, a throttle body including a throttle valve is integrally molded with an intake air manifold, being made of resin material, and a driving part including a motor for rotating the throttle valve and a gear mechanism for transmitting power of the motor to the throttle valve is connected to the throttle body by welding. Further, with an air intake device disclosed in the following Patent Document 2, a connection pipe formed in a throttle body which integrally includes a motor for rotating a throttle valve is screwed to a connection pipe holding part formed in an intake air manifold, and a flange in the throttle body is fastened to that in the intake air manifold with a bolt, thereby the throttle body including a driving part being connected to the intake air manifold.
Patent document 1: Japanese Unexamined Patent Application Publication No. 2005-233146
Patent document 2: Japanese Unexamined Patent Application Publication No. 2010-116794


A wearing article such as a disposable diaper is provided in predetermined regions of the article with hook members. These predetermined regions are elastically stretchable at least in one direction. Each of the hook members includes a plurality of hook assemblies which are, in turn, attached to each of the predetermined regions so as to be spaced apart one from another in the one direction.

The present invention relates to wearing articles such as disposable diapers, disposable gowns used in medical field or bandages and particularly to such wearing articles utilizing a mechanical fastener.
Disposable wearing articles utilizing a mechanical fastener are well known in the art. For example, a disposable diaper disclosed in Japanese Patent Publication No. 2977501 utilizes a pair of Y-shaped tape fasteners extending outward from respective wings of a rear waist region in a transverse direction of the diaper. Each of these tape fasteners is provided on the inner surface at its distal end portion with a hook member of the tape fastener serving to cooperate with a loop member to form the entire tape fastener.
In the diaper disclosed in Japanese Patent Publication No. 2977501, respective proximal end portions of the Y-shaped tape fasteners are bonded to inner and outer surfaces of the respective wings. Such manner of bonding ensures that the tape fasteners can be permanently bonded to the wings, on one hand, but this locally stiffens the wings in zones thereof in which the tape fasteners are bonded thereto, on the other hand. For the diaper in which the wings should have elastic stretchability, this stretchability is deteriorated by the tape fasteners. In addition, the distal end portions of the tape fasteners already have a relatively high stiffness due to the presence of the hook member attached thereto and, in zones of the wings in which the respective hook members come in engagement with the loop member, the wings have a further higher stiffness which deteriorates stretchability and flexibility of the diaper.


In an assembly with a gas bag module at least one first detent element is designed for engagement into a second detent element, a load bearing fastening between the first and the second detent element fastening the gas bag module to a first vehicle-fixed component being closed by moving the gas bag module in an installation direction. An additional locking structure is provided which is separate from the first and second detent elements, and which connects the gas bag module with a second vehicle-fixed component. The additional locking structure exclusively determines in the installed state a final installation position of the gas bag module with respect to the second vehicle-fixed component, at least against the installation direction.

Gas bag modules often have at least one first detent element which is designed for engagement into a second detent element for load-bearing fastening of the gas bag module to a first vehicle-fixed component.
Such fastenings are frequently used for fixing a gas bag module in the hub of a steering wheel, because the actual installation process can thus be reduced to pushing the gas bag module into a recess of the steering wheel and, in particular, there are no longer any screw connections to be closed.
Another requirement is that the gas bag module is to be fitted as exactly as possible into the surface of a surrounding vehicle interior lining (such as, for example, a steering wheel covering), where cumulative tolerances may cause undesired inaccuracies.


The invention relates to antibacterial macrocycles with substituted biphenyl and processes for their preparation, their use for the treatment and/or prophylaxis of diseases, and their use for the production of medicaments for the treatment and/or prophylaxis of diseases, especially of bacterial infections.

The invention relates to antibacterial macrocycles with substituted biphenyl and processes for their preparation, their use for the treatment and/or prophylaxis of diseases, and their use for the production of medicaments for the treatment and/or prophylaxis of diseases, especially of bacterial infections.
In U.S. Pat. No. 3,452,136, thesis of R. U. Meyer, Stuttgart University, Germany 1991, thesis of V. Leitenberger, Stuttgart University, Germany 1991, Synthesis (1992), (10), 1025-30, J. Chem. Soc., Perkin Trans. 1 (1992), (1), 123-130, J. Chem. Soc., Chem. Commun. (1991), (10), 744, Synthesis (1991), (5), 409-13, J. Chem. Soc., Chem. Commun. (1991), (5), 275-7, J. Antibiot. (1985), 38(11), 1462-8, J. Antibiot. (1985), 38(11), 1453-61, the natural product biphenomycin B is described as having antibacterial activity. Some steps in the synthesis of biphenomycin B are described in Synlett (2003), 4, 522-526.
Chirality (1995), 7(4), 181-92, J. Antibiot. (1991), 44(6), 674-7, J. Am. Chem. Soc. (1989), 111(19), 7323-7, J. Am. Chem. Soc. (1989), 111(19), 7328-33, J. Org. Chem. (1987), 52(24), 5435-7, Anal. Biochem. (1987), 165(1), 108-13, J. Org. Chem. (1985), 50(8), 1341-2, J. Antibiot. (1993), 46(3), C-2, J. Antibiot. (1993), 46(1), 135-40, Synthesis (1992), (12), 1248-54, Appl. Environ. Microbiol. (1992), 58(12), 3879-8, J. Chem. Soc., Chem. Commun. (1992), (13), 951-3 describe a structurally related natural product, biphenomycin A, which has a further substitution with a hydroxy group on the macrocycle.
The natural products do not comply in terms of their properties with the requirements for antibacterial medicaments. Although structurally different agents with antibacterial activity are available on the market, the development of a resistance is a regular possibility. Novel agents for a good and more effective therapy are therefore desirable.

Antibacterial macrocycles with substituted biphenyl


A method for operating a computer system and an associated method for collecting information related to the operation of the computer system. An ECC count and a series of address/time/temperature entries is maintained in a memory of the computer system. The computer system is continuously monitored for occurrences of an SMM event. Upon detection of an SMM event, the computer system enters SMM mode where SMM handler code is executed until handling of the SMM event is complete. The SMM handler code includes special instructions which enable the collection of information related to the operation of the computer system. Specifically, a determination is made as to whether the SMM event was caused by an ECC event. If so, the address at which the ECC event occurred and the time and temperature when the ECC event occurred are acquired, the ECC count is incremented and the acquired address, time and temperature information is stored as an entry in the memory.

1. Field of the Invention
The present invention generally relates to a method for collecting information related to system errors which occur in a computer system and, more particularly, to a method of collecting error correction code event-related information while the computer system is executing system management mode handler code.
2. Description of Related Art
An error occurs whenever a computer system such as a personal computer (or "PC") produces an incorrect result. The cause of computer errors varies and may include malfunctions of physical components and coding errors in software. As a result, nearly all computer systems are equipped with error detecting and/or error correcting capabilities. Error detecting code commonly uses parity checks to determine if there is an error in a received message. More specifically, a parity bit is added to the end of a message block. Upon receipt, the message block is checked to see if it contains the correct number of ones. If there are not the correct number of ones in the message block, the message contains an odd number of errors. Upon detection of an error, the receiver can request that the message be retransmitted. In most cases, the retransmission will result in an error free message.
Error detection techniques are generally disfavored because of the additional time consumed by retransmissions of those messages containing errors. Additionally, error detection requires a two-way exchange in order to request and process the retransmission of a message. The aforementioned deficiencies associated with error detection techniques are overcome by the use of techniques which incorporate error correcting code (or "ECC"). Generally speaking, ECC techniques assign a parity check to those positions in a code that have a one in the rightmost position of their binary position, a second parity check for those positions that have a one in their second to right position, etc. When a single error occurs, exactly those parity checks will fail for which the binary expansion of the position of the error has ones.
Thus, the pattern of the parity-check failures points directly to the position of the error. Once identified, the erroneous bit may be changed to its opposite value, thereby correcting the error. Further details regarding error detecting and error correcting codes may be found by reference to Ralston et al., ed., Encyclopedia of Computer Science, 3rd ed., pgs. 531-532 (1992).
While message errors are often isolated and/or random occurrences, they may be symptomatic of a greater problem in need of rectification.
Unfortunately, ECC techniques are self-correcting.
Thus, after a message error has been corrected, no record of the error remains. It is clear, therefore, that information regarding ECC errors would be quite useful in the diagnosis and/or repair of a computer system, particularly if such information could be collected with minimal impact on the operations of the computer system.
As described in the Intel386.TM. Microprocessor SuperSet Programmer's Reference Manual, the Intel family of microprocessors (386 series or higher), as well as clones of these microprocessors, are provided with a hidden set of instructions commonly referred to as system management mode (or "SMM") code. SMM code was developed in order to provide a means of transparently managing system operations for a computer system. Generally, a computer system equipped with SMM code will operate normally until the occurrence of an SMM event, i.e., an event which will initiate execution of the SMM code. For example, a low battery condition in a laptop computer is an SMM event which will initiate execution of the SMM code. When an SMM event occurs, a system management interrupt (or "SMI") request is transmitted to the central processing unit (or "CPU"). Upon receipt of an SMI request, the highest priority non-maskable interrupt, the CPU saves its state in a specially allocated portion of main memory, exits the normal operating mode and enters SMM mode where the CPU begins to execute the SMM code. The CPU will stay in SMM mode until the SMI request is handled. At that time, the CPU will return to the normal operating mode.
Broadly speaking, SMM mode provides a process to transparently handle SMM events, a varied collection of types of events which includes the aforementioned ECC events. Once an event is handled and the CPU returns to normal operating mode, however, information related to the SMM event is not retained. Thus, the user is deprived of useful information which could later be reviewed, for example, while running a separate application or diagnostics on the computer system.
It can be readily seen from the foregoing that it would be desirable to a provide a method of operating a computer system such that information related to its operation is collected whenever the computer enters SMM mode in response to the occurrence of an event, for example, a system error, for which information is to be collected. It is, therefore, the object of this invention to provide such a method of operating a computer system.

Method for collecting ECC event-related information during SMM operations


A bus master (other than the CPU) sends a signal to a bus controller requesting use of the bus. After receiving the bus-use request signal from the bus master, the bus controller sends a hold signal to the CPU to separate the CPU from the bus. The CPU then outputs a hold response signal in response to the hold signal. Upon receiving the hold response signal from the CPU, the bus controller sends a signal to the bus master requesting use of the bus indicating that that bus master can use the bus. The bus controller also sends a signal to a clock signal generator, which lowers the clock speed below a certain threshold or switches it into a stop clock state. Once the bus controller senses that the bus master is finished using the bus, the bus controller stops the above-mentioned signal sent to the bus master indicating that the bus master can use the bus.

(1) Field of Invention
The present invention relates to a power consumption reducing apparatus for a computer bus system and an associated method for reducing power consumption. Particularly, the present invention relates to reducing power consumption during a CPU idle condition when a bus master other than the CPU, such as a Direct Memory Access (DMA) controller or a refresh controller, uses the bus system. Power consumption is reduced by lowering or stopping a clock signal supplied to the CPU.
(2) Description of Related Art
Recently, development of computer technology has taken into consideration functional aspects as well as power saving aspects. Therefore, a Power Management System (PMS) is used in a personal computer to maximize power savings in accordance with a current operational state of the computer.
As illustrated in FIG. 1, the Power Management System (PMS) is divided into a normal mode 10, a doze mode 12, a standby mode 14, a suspend mode 16, and an off mode 18 in accordance with the power supply.
The normal mode 10 refers to the normal operational state of the system.
The doze mode 12 reduces the clock speed of the CPU 1/2, 1/4, or 1/8 when the system is inactive, e.g., when a hard disk is not accessed via the serial input/output interface, or when the video display, the FDD, the keyboard, etc., are not active.
The standby mode 14 reduces the clock speed of the CPU when there is no system activity, shuts off the video display, and/or places the HDD in a standby mode.
The suspend mode 16 stops or shuts off the CPU clock, the HDD, the FDD, and the video display, but not the memory, in order to reduce power usage.
The PMS restores the system to its normal mode 10 from the doze and standby modes 12, 14 if system activity is sensed. The system is restored from the suspend mode 16 by, for example, pushing a suspend/resume button on the computer. The system is switched between the normal mode 10 and the off mode 18 by a conventional on/off switch.
In conventional PMS processes, however, the CPU is supplied with a full speed clock signal when the FDD is accessed, or when a bus master (for example, a DMA controller, a refresh controller, a Small Computer System Interface (SCSI), an Enhanced Small Device Interface HDD controller, a LAN card, a sound card, etc.) is allowed to use the bus system.
Therefore, power consumption associated with the clock signal supplied to the CPU is increased when a bus master, other than the CPU, uses the bus, because the CPU performs only an internal calculation.

Power consumption reducing apparatus in using no CPU bus system and method thereof