An improved cellular communication network which is divided into a plurality of cells is provided. Each of the cells including a base station has at least two directional antennae, each of which is operative to communicate with a plurality of units. Each of the antennae is directed in a different direction and operates in a different frequency band. A characterisitic of the cellular network is that antennae, in adjacent cells, operating in similar frequency bands are directed in different directions.

Cellular communication networks are well known in the art. An example of such a network is a cellular telephone network. Another example is the use of cellular communication in conventional telephone networks, i.e. for replacing physical (wire) connections between a central office and the subscribers units in dense urban areas where wiring is not practical or too costly.
Since a limited range of frequencies is allocated for each cellular telecommunication network, methods were developed to allow simultaneous use of frequency bands within the allocated range of frequencies. This enables an increased number of users per area to use the network at the same time.
One method for improving the use of an allocated range of frequencies includes reusing frequency bands within the allocated range of frequencies within the area covered by the network. This method which is known as the "cell method", is schematically shown in FIG. 1A to which reference is now made. The network of FIG. 1A covers an area indicated by reference numeral 12. The area 12 is divided into subareas, termed "cells", such as cell 14. Each cell includes a base station, such as base station 16, typically in its center. Each base station includes at least one non-directional antenna which communicates with any telephone or local station within the area covered by the cell.
Typically, two adjacent cells, such as cells 18 and 20 or cells 22 and 24, use different frequency bands within the range of frequencies allocated to the network. A typical width of a frequency band is on the order of 1 Mhz. In the network of FIG. 1, each cell operates in one of seven frequency bands within the range of frequencies allocated for the network. The bands are denoted F1, F2, F3, F4, F5, F6 and F7.
In a cellular network the reuse factor N, i.e. the number of distinct frequency bands required for covering the desired area, depends mainly on the capability of the antenna of a base station to cope with interference generated by the network users in other cells using the same frequency band. This capability is a function of the distance D between the interfering user unit and the signal carrier antenna. In a network, such as the network 10, which employs a reuse factor of 7, interference to an antennae in any cell, such as in cell 24, may come from any of the six closest cells which operate on the same frequency band, such as from users in cell 28.
The reuse factor also depends on the Carrier to Interference (C/I) ratio which measures the ratio between the carrier signal of an antennae and the interfering noise. For most modern networks, it is desired that the C/I ratio will be 7 dB-15 dB and preferably larger than 15 db to minimize interferences. Therefore, for a state of the art network which employs non-directional antennae, such as the network 10, a reuse factor of 7, as indicated by the notations F1-F7, is required in order to achieve a C/I ratio of 18.6 dB which meets the desired C/I value of 15 dB.
One way to reduce the reuse factor, in order to use a smaller range of frequencies, is to employ directional antennae in each one of the cells instead of the non-directional antennae of the network 10. A typical prior art cellular network which employs directional antennae is shown in FIG. 1B to which reference is now made.
In the network of FIG. 1B, referenced generally 50, three directional antennae are employed in each cell. Each antenna is directed to a different direction and is using a different frequency band of the three frequency bands denoted F1, F2 and F3.
In prior art networks which employ directional antennae in adjacent as well as in distant cells, antennae which are directed to the same direction employ a similar frequency band. For example, in the network 50, the antennae 52, 56 and 60 which employ the F2 band are directed in the same direction and cover the same area of the cells, 54, 58 and 62, respectively, i.e. the areas in the upper right side of each cell denoted 64, 66 and 68, respectively.
In the network 50, an improved C/I ratio relative to a similar network which employs non-directional antennae is achieved since interferences come to any antennae from two adjacent cells and not from six cells as in the network 10 as described in more detail with reference to FIG. 1C.
Reference is now made to FIG. 1C which is a schematic illustration of part of the network 50 in an operation mode. For clarity of presentation only, four cells in FIG. 3, cells 54, 58, 62 and 90 are shown in detail whereas the other cells are outlined only.
For each of the cells 54, 58, 62 and 90, there is shown a unit which communicates with one of the directional antennae in each cell, the antennae which employs the F3 frequency band. In the cell 54, unit 84 communicates with the antenna which covers the area 164, in the cell 58, unit 82 communicates with the antenna covering the area 66, in the cell 62, unit 86 communicates with the antenna covering the area 68 and in the cell 90 and unit 96 communicates with the antenna covering the area 92.
A characteristic of prior art networks, such as the network 50 is that interferences to any antennae come from two adjacent cell and also from more distant cells. For example, interferences to the antenna which employs the F3 frequency band in the cell 54 come from the units 82 and 86 of the cells 58 and 62, respectively, and to much less extent from the unit 90 of the cell 92. This is because all the antennae of the cells 53, 58, 62 and 92 which employ the F3 frequency band are directed in the same general direction as indicated by arrows 74, 82, 86 and 94, respectively.
For the network 50 the C/I ratio with comparable technology to that of the network 10 is 19.1 dB. For a network like network 50, with a reuse factor of 7, i.e. which employs altogether 21 frequency bands, three per each cell and with a reuse factor of 7, the C/I ratio is 23.4 dB.

Cellular network having cells which are in a specific circular orientation of sectors

Innowave Tadiran Telecommunictions Wireless Systems Ltd.


Provided are methods of preparing an article in which a microporous layer is coated on a temporary carrier substrate and a substrate is then laminated to the microporous layer, prior to removing the temporary carrier substrate from the microporous layer. The microporous layer may comprise one or more microporous xerogel layers. Optionally, the microporous layer assembly may comprise one or more non-microporous coating layers which are in contact with at least one of the microporous xerogel layers, and one of the non-microporous coating layers may be coated on the temporary carrier substrate prior to coating the microporous layer. Also provided are articles, such as electrochemical cells, capacitors, fuel cells, ink jet ink printing media, and filtration media, prepared by such methods.

The present invention relates generally to the field of articles comprising a microporous layer. More particularly, this invention pertains to methods of preparing an article comprising a microporous layer in which a microporous layer is coated on a temporary carrier substrate and a substrate is then laminated to the microporous layer, prior to removing the temporary carrier substrate from the microporous layer. The present invention also pertains to articles, such as electrochemical cells, capacitors, fuel cells, ink jet printing media, and filtration media, prepared by such methods.
Throughout this application, various publications, patents, and published patent applications are referred to by an identifying citation. The disclosures of the publications, patents, and published patent applications referenced in this application are hereby incorporated by reference into the present disclosure to more fully describe the state of the art to which this invention pertains.
U.S. patent application Ser. No. 08/995,089 titled xe2x80x9cSeparators for Electrochemical Cells,xe2x80x9d filed Dec. 19, 1997, to Carlson et al. of the common assignee, describes microporous layers as separators for use in electrochemical cells in which microporous layers comprise a microporous pseudo-boehmite layer prepared by coating and drying a boehmite sol. The microporous pseudo-boehmite separators and methods of preparing such separators are described for both free standing separators and as a separator layer coated directly onto an electrode or another layer of the cell.
When a microporous layer, such as a microporous separator layer, is coated directly onto an electrode, such as onto the cathode, the microporous separator coating may require a relatively smooth, uniform surface on the electrode and also may require a mechanically strong and flexible electrode layer. For example, for a microporous pseudo-boehmite layer having a xerogel structure, these specific electrode surface and layer properties may be required to prevent excessive stresses and subsequent cracking of the xerogel layer during drying of the pseudo-boehmite coating on the electrode surface and also during fabrication and use of electrochemical cells containing the pseudo-boehmite xerogel layer.
Besides separator-coated electrodes and electrochemical cells, a large variety of other articles comprising a microporous layer may require a relatively smooth, uniform surface on a substrate to which the microporous layer is to be applied. Also, the substrate may need to be mechanically strong and flexible. For example, for a microporous xerogel layer as used in ink jet printing media, such as described, for example,in U.S. Pat. No. 5,463,178 to Suzuki et al., such smooth, uniform, and other substrate properties may be useful in preventing excessive stresses and subsequent cracking of the xerogel layer, particularly when its thickness is above 20 microns, and also useful in providing excellent image quality. Some of the desired substrates in ink jet printing media, such as canvas, cloth, non-woven fiber substrates, and some grades of paper, have very rough and non-uniform surfaces and are difficult to coat with the microporous xerogel layers which typically provide the premium ink jet image quality. One approach to overcome the surface deficiencies of the substrate is to pre-coat the substrate with a coating layer. This approach may reduce the surface roughness and non-uniformities, but involves the expense and complexity of an additional coating step, usually does not fully eliminate the surface deficiencies, and may negatively affect the ink jet imaging, such as by interfering with the microporosity and transport of liquids between the xerogel layer and the rough but porous substrate.
In another approach that may overcome the surface deficiencies of the substrate, the ink jet ink-receptive layer may be coated on a temporary carrier layer to form an ink jet ink printing media for imaging on an ink jet printer, as, for example, described in U.S. Pat. Nos. 5,795,425 and 5,837,375, both to Brault et al. Then, as part of a two step imaging process, the ink jet media is imaged on the ink jet printer followed by lamination of the imaged ink jet ink-receptive layer to a desired substrate and removal of the temporary carrier layer from the ink jet ink-receptive layer. This approach has the disadvantage of being a two-step imaging proess where the user may obtain excellent quality in the first imaging step, but then, after the effort and expense of imaging, the quality of the second lamination step may be unacceptable. Also, this two step imaging process requires the user to have the equipment for the second lamination step. It would be advantageous to have a one step imaging process for ink jet printing on ink jet ink printing media having rough, non-uniform substrates.
A method for preparing articles, such as electrochemical cells and ink jet printing media, which can avoid the foregoing problems often encountered with preparing articles comprising a microporous layer, particularly those comprising a microporous xerogel layer, would be of great value.
The present invention pertains to methods of preparing an article comprising a microporous layer, which methods comprise the steps of (a) coating a microporous layer on a temporary carrier substrate to form a microporous layer assembly, wherein the microporous layer has a first surface in contact with the temporary carrier substrate and has a second surface on the side opposite from the temporary carrier substrate; (b) laminating the second surface of the microporous layer to a substrate to form a microporous layer/substrate assembly; and (c) removing the temporary carrier substrate from the first surface of the microporous layer to form the article. In a preferred embodiment, the microporous layer comprises one or more microporous xerogel layers. In one embodiment, the microporous layer assembly further comprises one or more non-microporous coating layers, wherein the one or more non-microporous coating layers are in contact with at least one of the one or more microporous xerogel layers of the microporous layer. In one embodiment, one of the one or more microporous xerogel layers of the microporous layer is coated directly on the temporary carrier substrate. In one embodiment, one of the one or more non-microporous coating layers of the microporous layer assembly is coated directly on the temporary carrier substrate prior to coating the microporous layer, and the microporous layer is then coated on a surface of the one of the one or more non-microporous coating layers, which surface is on the side of the one of the one or more non-microporous coating layers opposite from the temporary carrier substrate, and further wherein the temporary carrier substrate is removed in step (c) from asurface of the one of the one or more non-microporous coating layers, which surface is on the side of the one of the one or more non-microporous coating layers opposite from the microporous layer. In one embodiment, one of the one or more non-microporous coating layers of the microporous layer assembly is coated after step (a) directly on the surface of the microporous layer, which surface is on the side of the microporous layer opposite from the temporary carrier substrate layer, prior to laminating to the substrate in step (b).
In a preferred embodiment, at least one of the one or more microporous xerogel layers comprises a xerogel material selected from the group consisting of pseudo-boehmites, zirconium oxides, titanium oxides, aluminum oxides, silicon oxides, and tin oxides. In one embodiment, the microporous layer comprises a microporous material prepared by vesiculation of an organic polymer layer, and wherein said vesiculation comprises a step of photolyzing or heating a gas forming compound. In one embodiment, the gas forming compound is an aromatic diazonium compound.
In one embodiment of the methods of preparing an article comprising a microporous layer of the present invention, the temporary carrier substrate is a flexible web substrate. Suitable web substrates include, but are not limited to, papers, polymeric films, and metals. In one embodiment, the flexible web substrate is surface treated with a release agent.
In one embodiment, the microporous layer assembly is a cathode/separator assembly, the substrate is an anode assembly, and the article is an electrochemical cell. The electrochemical cell may be a primary cell or a secondary cell.
In one embodiment, the microporous layer assembly is an ink jet ink-receptive coating assembly, the substrate is a flexible web substrate, and the article is an ink jet ink printing media.
In one embodiment, the microporous layer assembly is an ultrafiltration layer assembly, the substrate is a flexible web substrate, and the article is a filtration media.
In one embodiment, the microporous layer assembly is a separator assembly, the substrate is a first electrode assembly, and the article is a first electrode/separator assembly. In one embodiment, the methods further comprise the step of combining the first electrode/separator assembly with a second electrode assembly to prepare an electrochemical cell, a capacitor, or a fuel cell.
Another aspect of the present invention pertains to an article prepared by the methods of this invention, as described herein. In a preferred embodiment, the article is an ink jet ink printing media.
As will be appreciated by one of skill in the art, features of one aspect or embodiment of the invention are also applicable to other aspects or embodiments of the invention.

Methods of preparing a microporous article


An antenna comprises a first antenna element, which has a first helix, and a second antenna element, which has a second helix. The first and the second antenna elements each have a feed point at an outer end of the corresponding helix and an open end at an inner end of the corresponding helix. A symmetrical helix antenna according to the invention can be integrated in a comparatively simple manner in an existing system, for example in a hearing aid. By integrating the antenna in a plastic housing, the antenna cannot be seen at all from the outside. The antenna is comparatively small in relation to conventional antennas.

There are presently numerous portable devices from which and to which data is to be transmitted by wireless means. One possibility which suggests itself here is to realize the data transmission by electromagnetic coupling. In doing this, particular difficulties arise if the devices used are very small, because in such a situation there are problems in integrating an antenna structure into the device concerned. An important example of a very small device for which wireless data transmission is required is a hearing aid.
In accordance with the prior art, the transmission of data to a hearing aid is often realized in practice by inductive transmission links. For this purpose, an induction loop is integrated into the hearing aid. However, this type of inductive transmission of speech or data, as applicable, to a hearing aid requires special installations in the area concerned, where the wireless transmission of speech or data is to take place.
In another form of embodiment of wireless radio transmission systems, magnetic antennas are used in the hearing aids. These essentially couple into the magnetic components of an electromagnetic field, and are generally designed as conductive loops. Radio transmission systems of this type generally work at frequencies which are significantly lower than the frequencies used in mobile radiocommunications, e.g. in the VHF band at 174 MHz.
European patent application EP 1 326 302 A2 describes a fractal antenna structure which is realized on an integrated circuit, and which can be used in a hearing aid. However, the fractal antennas described in the document cited can only be considered for significantly higher frequencies.


An example method includes receiving an indication of a selection of a first application environment that includes a first virtual environment associated with a first security domain and is configured to isolate execution of software applications within the first application environment, suspending execution of a second application environment that includes a second virtual environment associated with a second security domain different from the first security domain, initiating execution of the first application environment, identifying information associated with the first security domain and provided by the first application environment that is to be sent to an external computing device associated with the first security domain, selecting communication network(s) from one or more communication networks that are each available to the mobile computing device for data communication, encrypting, based on the first security domain and network(s), the information, and sending, to the external computing device via the network(s), the encrypted information.

Today, users increasingly rely on computing devices, such as mobile computing devices, for voice communication, information access, and application usage. However, untrustworthy applications and certain online behaviors can potentially compromise the security of such computing devices. The continuing adoption of mobile computing devices in various organizations has created a growing desire for technologies that enable device users to separate their data into different categories use, such as, for example, classified and unclassified data.

This patent is subject to a terminal disclaimer.

Fast reconfiguring environment for mobile computing devices


An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source stress experienced by transistors in that circuit that are in an off state. The auxiliary voltage generation circuit also generates a logic control signal that indicates to a high voltage discharge path to perform either a slow discharge operation or a fast discharge operation.

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include portable computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code, system data such as a basic input/output system (BIOS), and other firmware can typically be stored in flash memory devices. Most electronic devices are designed with a single flash memory device.
In order to increase the memory density of flash memories while making them smaller, the silicon is scaled. Associated with minimum length scaling is a reduction of the oxide thickness and the junctions become less graded. This results in a decrease of the maximum voltage that is tolerated between terminals of the transistors. For example, a high drain-to-source voltage (Vds) could exceed the breakdown limit of the transistor, eventually causing the transistor to fail.
An additional problem is experienced when the gate-to-source voltage (Vgs) goes high while Vds has a high value. This condition is referred to in the art as snapback. The high level of current associated with this phenomenon may damage the device and/or decrease its life.
Flash memory devices require a large negative voltage to erase the memory cells. The negative voltage is generated and regulated by an internal high voltage pump connected to control circuitry to control output of the high voltage.
FIG. 1 illustrates a block diagram of a typical prior art circuit for generating a high negative erase voltage. This circuit is connected to the wordlines of the memory array that are modeled here by a capacitor 101. REFN and REFH are analog values that are used to assign the target voltage values to VNEG and VHV rails, respectively. SELECT passes the high voltages to the sector/sectors that are to be erased. ENABLE activates the erase pulse.
The prior art system can have four different phases that are selected by the ENABLE signal and the VNEG and VHV values. These phases are an off state, ramp phase, pulse phase, and discharge phase.
The off state occurs when ENABLE=0, VNEG and VHV are shorted to ground by the discharge paths 103 and 104. The ramp phase is selected when ENABLE=1, VNEG and VHV are below their target values. The negative and HV pumps 107 and 108 are turned on during this phase. The pulse phase is selected when ENABLE=1, VNEG and VHV are at their target voltages. The negative and HV pumps 107 and 108 are turned off during this phase. The discharge phase is selected when ENABLE=0, VNEG and VHV are discharged to ground; each through its own path 104 and 103 respectively.
The circuit illustrated in FIG. 1 may cause snapback problems that increase the stress some transistors experience during their off state. This decreases the reliability of the transistors in the memory device. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a high voltage management circuit to improve the reliability of memory device transistors.

High voltage generation and regulation circuit in a memory device


A read and/or write head for a tape drive system has a tape bearing surface that includes relatively smooth areas surrounded by relatively rough areas. Read and/or write elements are located in the smooth areas.

1. Field of the Invention
The invention relates to reduced tape stick tape drive systems.
2. Discussion
Magnetic tape may stick to heads and other tape path components of tape drive systems. Whether a magnetic tape sticks may depend on the media formulation, the contact surface area, the smoothness of surfaces that tend to adhere to one another, and the spacing between head recording elements and recording media.


Certain exemplary embodiments can comprise a method comprising: receiving electrical energy from a braking system of a vehicle at a working coil, the vehicle comprising a first wheel drive comprising a first electric motor; and via the working coil, transferring the electrical energy to a mass related to the vehicle via Hall Effect, the transferred electrical energy converted to heat energy in the mass.

U.S. Pat. No. 2,633,541 (Justus), which is incorporated by reference herein in its entirety, allegedly cites "a novel method of dissipating the heat created in resistors for absorbing the electrical energy generated in dynamic braking, which method avoids the objections to the prior methods described above. One object of my invention is to provide a system for dissipating the heat created by conversion of the electrical energy generated in dynamic braking to heat energy in apparatus which is relatively compact and light in weight. Another object is to provide a system and method for dissipating the electrical energy created in dynamic braking which comprises converting the electrical energy into heat and transferring the heat to the liquid in the cooling circuit of an internal combustion engine. A further object is to provide a system for dissipating the energy created in dynamic braking as heat added to the cooling fluid of an unloaded internal combustion engine, thereby maintaining the engine at an elevated temperature. Still another object of my invention is to provide a system for dissipating the energy created in dynamic braking as heat added to the cooling fluid of an internal combustion engine which system includes, for cooling said fluid, a fan whose speed is automatically varied with the amount of energy to be dissipated. A still further object of my invention is to provide a system for dissipating the energy created in dynamic braking as heat added to the cooling fluid of an internal combustion engine, which system includes means for circulating said fluid in proportion to the amount of energy to be dissipated." See column 1, line 37 through column 2, line 9.
U.S. Pat. No. 4,173,732 (Anderson), which is incorporated by reference herein in its entirety, allegedly cites the "heat energy dissipation capacity of the provided dynamic braking resistors for a given transit vehicle is established and then the generated motor current supplied to those resistors by the regenerating propulsion motor of the vehicle during the brake mode of operation is controlled to limit as desired in accordance with that capacity the total energy dissipated by the dynamic braking resistors." See Abstract.

Enhanced system and method for controlling discharge of electric energy from machines


In a Digital Pressure Derivative Technique (DPDT) which uses convolution, an input signal including noise is convolved with a wavelet to produce an output signal which is a derivative of the input signal and which is substantially devoid of the noise. The DPDT can be used in many applications; however, in one such application, a pressure signal from a wellbore including noise is convolved with a special wavelet to produce an output signal which is the derivative of the input pressure signal, the output signal being substantially devoid of the noise. The wavelet is made from the unit sample response of a bandlimited, optimum linear phase Finite Impulse Response digital differentiator. The DPDT technique enables analysts to customize the differentiation based on the quality of the measured data without having to use traditional, subjective smoothing algorithms. The results presented here, in connection with the one such application mentioned above, bring significant improvements to the diagnosis and interpretation of pressure transient data, and interpretation techniques that utilize higher-order derivatives are now practical.

The subject matter of the present invention relates to a Digital Pressure Derivative software, adapted to be stored in a computer system, for receiving a measurement function including 'noise', such as a measurement of pressure in an oil or gas well, for convolving the measurement function with a wavelet, and for generating a high resolution and high accuracy output signal which is substantially devoid of the 'noise' and which will enable a customer to interpret the high resolution and high accuracy output signal in order to obtain more information about the measurement. When the measurement function represents a measurement of pressure in an oil or gas reservoir, the pressure measurement function including the 'noise' is convolved with a derivative wavelet thereby generating a much higher resolution 'derivative of the pressure measurement function' which is substantially devoid of the 'noise', the absence of the 'noise' in the higher resolution 'derivative of the pressure measurement function' generated by the convolution enabling a customer to interpret the 'derivative of the pressure measurement function' and obtain more information about the pressure measurement and the reservoir.
Reservoir characterization using well test data has made remarkable progress in the last decade. Significant advances in mathematical techniques have permitted the analytical solution to complex reservoir flow problems which were previously obtainable only by means of numerical methods. Notable contributions in this area include the work of Ozkan and Raghavan1-3 in which the Laplace transform and the method of sources and sinks were systematically combined to compute pressure distributions for various well and reservoir complexities. Utilizing the Laplace transform allows the addition of natural fractures,4 variable rate production5 (wellbore storage) and commingled production6 in a general and efficient manner. Combined with the Stehfest7 algorithm for numerically inverting the Laplace space solutions into the time domain we have, from a software implementation standpoint, a straightforward approach to developing efficient and extendible libraries of analytical solutions to the diffusivity equation. For situations in which analytical procedures are limited (e.g., complex geometries, multiphase flow) we may use recently developed software specifically designed to interactively model transient welltest data using finite-difference methods (e.g., GeoQuest's WellTest 200).
The advances made in the measurement of pressure transient data have complimented these new solution techniques by providing the stability and resolution required to perceive complexities of the well/reservoir system which may otherwise have gone unnoticed. Currently, we are able to measure pressures with a resolution of 0.001 psi with 10 second sampling and with a stability (drift) of less than three psi/year.8
The interpretation and measurement of well test data have, with a few recent exceptions, advanced separately. Notable exceptions include two studies presented by Veneruso et al.9,10 The first demonstrates how errors in pressure measurement affect well test analysis using a transfer function approach. Gauge effects, such as drift and resolution are incorporated into the analytical simulation of well tests in order to optimize testing performance with cost-effective instruments. The second discusses key data acquisition and data transmission techniques in addition to giving a good overview of the electronic processes involved in making pressure, flowrate and temperature measurements.
In this specification, we hope to further reduce the separation between advances in well test interpretation and advances in measurement technology by incorporating our knowledge of one within the other. Specifically, we utilize the firm mathematical foundation of Digital Signal Processing to combine the characteristics of the well test measurement process with our knowledge of reservoir physics to improve the pressure derivative technique of diagnosing and interpreting pressure transient data. The term derivative as used herein is intended to imply differentiation with respect to the time function plotted on the abscissa of the appropriate semi-log plot; for generality, this should be considered the superposition time function.
Arguably the most significant advance in well test interpretation the last decade, the pressure derivative, as described by Bourdet et al.,11-14 has become the primary tool for diagnosing well and reservoir behavior. It provides the basis for modern well test interpretation methodology15 and has become a customary and requisite feature in the myriad commercial well test interpretation software now available. In many situations however, the derivative of the measured data is uninterpretable or, worse, mis-interpreted by the analyst because of various artifacts of the measuring and differentiating process collectively termed "noise". A published article16 states "The main disadvantage of the pressure derivative is that one must construct derivative data by numerical differentiation of measured pressure data. The resulting pressure derivative data often are noisy and difficult to interpret. While various "smoothing" techniques have been used to reduce noise, some concern exists that the smoothing procedures may alter the basic character of the data." This opinion is respected by most engineers involved with the interpretation of well test data.
Various algorithms have been used in an effort to eliminate or reduce the inevitable noise associated with the numerical differentiation of measured data. For example, Bourdet, et al.14 considers polynomial fitting of the data and taking the analytical derivative of the polynomial. This procedure, in addition to being cumbersome, alters the shape of the original data. A second procedure given is to compute the third derivative of the data and subsequently integrating twice. This method tends to give false oscillations at late times and during infinite acting radial flow. The current practice is to use centuries-old techniques developed by Newton and Stirling for interpolating data tables (backward, forward, or central difference typically utilizing three points). When viewed in the frequency domain, these techniques are clearly highpass and bandpass filters, which exaggerate high frequency noise and distort the "true" dp/dt curve. The data is then typically smoothed by choosing the points used in the calculation a sufficient distance from the point of interest. This distance, given as L in Ref. 14, is expressed in terms of the appropriate time function. The idea of smoothing the derivative is considered suspect by some due to the subjective choosing of L. If L is chosen too large, the character of the actual signal will be distorted. Nevertheless, judging by the standard use of this method in commercial well testing software, it apparently has become the most popular. Akima17 suggests a slightly different approach whereby the slope of the point in question and two points on each side are used. A third degree polynomial representing a portion of the curve between a pair of given points is determined by the coordinates and the slopes at the two points. The derivative of the polynomial is then computed.
Regardless of which method of numerical differentiation is used and regardless of the chicanery employed to reduce the scatter in the resulting derivative data, the analyst is often left with data not entirely representative of the well/reservoir system (s)he is trying to identify.
In this specification, we describe a new technique for differentiating well test pressure data called the Digital Pressure Derivative Technique (DPDT). The DPDT produces the most accurate and representative dp/dt curve by incorporating knowledge of both reservoir and gauge physics. It is efficient and straightforward to implement and may be used on either real-time or recorded data. No modifications to gauges or surface hardware are necessary. Furthermore, error bounds and a quality control mechanism, indicating the end of a transient (i.e. a signal-to-noise ratio test) can be provided allowing the optimal use of recorder memory space. Additional DSP techniques such as oversampling may be utilized to further enhance the quality of the DPDT. The DPDT is generated by convolving the measured pressure samples with a special wavelet. This wavelet is made from the unit sample response of a bandlimited, optimum linear phase finite impulse response (FIR) differentiator. The DPDT is based on the firm mathematical foundation of Digital Signal Processing (DSP), reservoir physics and the characteristics of the pressure measurement system.

Digital pressure derivative method and program storage device


A switching power source, a method and a control chip for controlling the same are provided. The switching power source includes: a filtering and rectifying module, connected with an AC power source and configured to filter and rectify an alternating current outputted from the AC power source to obtain a direct current; a control module, connected with the filtering and rectifying module and configured to obtain an amplitude of the alternating current from the direct current, to adjust a frequency of a control signal according to the amplitude, in which the control module decreases the frequency of the control signal continuously or intermittently when the amplitude increases, and to output the control signal; and a primary constant current circuit, connected with the control module and the filtering and rectifying module respectively, and configured to receive the control signal and to output a constant current according to the control signal.

Currently, size of a flyback switching power source is mainly determined by size of the transformer and the input filtering capacitor in the power source, and a typical small switching power source adopts a relatively high switching frequency and a relatively low primary peak current, in which the relatively high switching frequency can ensure that the transformer has a relatively high power density, and the relatively low primary peak current can ensure that core saturation does not occur when a transformer having a small core area is used.
Currently, most flyback switching power sources work in a DCM (Discontinuous Inductor Current) mode, i.e., next charging is started only when a primary inductor is charged fully, as shown in FIG. 1, in which IP is the primary peak current and T is an operational period of the system. In order to ensure that the switching power source is working in the DCM mode and has an appropriate magnetic flux density, the inductance should be relatively small in high frequency applications. Thus, such a small switching power source generally has following defects.
1. The inductance is small, and a relatively large air gap exists between magnetic cores (in a condition of small core area), thus causing a large iron loss and being unfavorable for transformer manufacturing.
2. When a high alternating current is inputted, the high switching frequency causes a substantial switching loss, which greatly influences the efficiency of the switching power source.

Switching power source, method and control chip for controlling the same


An immunoassay comprises the steps of: (a) mixing a whole blood sample with sensitized insoluble carrier particles smaller than erythrocytes to cause an immune agglutination reaction; (b) introducing the resulting immune agglutination reaction mixture including agglutinated particles and unagglutinated particles to a flow cell, irradiating the particles passing through the flow cell with laser light, and detecting scattered lights generated thereby; (c) setting a threshold value for distinguishing unagglutinated particles from agglutinated particles and a threshold value for distinguishing the agglutinated particles from blood cells with regard to intensity of the scattered light; and (d) distinguishing and counting the unagglutinated particles, the agglutinated particles and the blood cells from the scattered lights detected in the step (b), in reference to the threshold values set in the step (c).

For immunoassays on infection disease-related test items, serum has been used as a sample to be tested. However, it takes about 30 minutes to separate serum from whole blood, including time for blood coagulation and time for subsequent centrifugation.
Typical examples of immunoassays include a radioimmunoassay (RIA), an enzyme immunoassay (EIA) a particle agglutination immunoassay and a counting immunoassay. However, RIA and EIA need B(Bound form)/F(Free form) separation after antigen-antibody reaction, and therefore, require time and labor before the results of the assays are obtained.
A particle agglutination immunoassay is advantageous in that it requires only the mixing of a sample to be tested with a suspension of insoluble carrier particles (e.g., latex) sensitized with an antibody or an antigen. Therefore it does not require the B/F separation and can be performed by simple operation.
Further, a counting immunoassay which is used serum or blood plasma and is known as an assay for measuring the degree of particle agglutination, antigen- or antibody-combined latex particles are reacted with an antibody or an antigen in a sample, so that they agglutinate according to the amount of the antigen or antibody. Agglutinated latex particles are distinguished by their size and counted. The count of unagglutinated latex particles is represented by M (monomer), the count of at least two agglutinated latex particles is represented by P (polymer), and the sum of M and P is represented by T (total). P/T is calculated as a degree of agglutination. If a calibration curve is determined beforehand by measuring the degree of agglutination of a known concentration of an antigen or antibody, the amount of the antigen or antibody in the sample can be found from the degree of agglutination of the sample (Sinkai Etsuro et al.: Principle of Measurement of PAMIA, Sysmex J. Vol. 20, No. 1, p.p. 77-78 (1997)). Since the agglutinated particles are directly counted, this assay is more accurate than the turbidimetric immunoassay which detects optical changes in the entire test sample.
In recent years, however, it has become necessary to judge rapidly whether or not a patient is infected with virus hepatitis, HIV or the like, for example, in the case of emergency operation. Accordingly, it is demanded that test time from collection of blood up to obtainment of test results be shortened. Also there is demanded a simple immunoassay that realizes the obtainment of highly accurate test results.
Taking the shortening of the test time into consideration, it is more desirable to use whole blood collected from a patient than to use serum, as a sample for immunoassays.
For example, Japanese Unexamined Patent Publication No. HEI 10(1998)-48214 proposes a whole blood assay using a conventional latex agglutination method. According to this assay, a whole blood sample is hemolyzed and the resulting sample is tested on its immune reaction by a latex turbidimetric immunoassay. This assay can provide test results simply and rapidly.
However, according to this assay, since the whole blood is hemolyzed, hemoglobin or fragments of hemolyzed blood cells interfere with the turbidimetric immunoassay using optical means and limit the accuracy of the assay. Therefore, the assay is not suitable for cases which require relatively high accuracy, for example, infection disease-related test items.
Whole blood usually contains about 40 to 50% of blood cell components in terms of hematocrit value. If whole blood is used in the same amount as in the case where serum is used, its measured values become lower than the values obtained by serum, reflecting the amount of blood cell components (a blood cell volume ratio content). In order to obtain measured values equivalent to those obtained by serum measurement, the values need to be corrected for the blood cell volume ratio content.
For this purpose, in Japanese Unexamined Patent Publication No. HEI 10 (1998)-48214, the hematocrit value is separately measured, and the measured values are corrected for the measured hematocrit value.
However, it is complicated to measure blood cells separately for correction. To avoid this, an inmmunoassay apparatus may be provided with a blood cell counting section and an immunoassay section, but such an apparatus becomes complicated and expensive. Therefore, there is a demand for a method for estimating or correcting influence by blood cells only by the immunoassay section.
Fully automated immunoassay apparatuses currently used are mostly designed for assaying serum (or blood plasma) samples, and therefore, do not have a stirrer which is necessary for assaying whole blood samples. If such apparatuses are used for immunoassays of whole blood samples, the blood cell components settle and only supernatant is used. The measured values are not affected seriously by the hematocrt value and may be not shifted apart to lower values.
In this case, if measured values are corrected for the hematocrit value separately measured by a blood cell counter for whole blood measurement as disclosed in Japanese Unexamined Patent Publication No. HEI 10 (1998)-48214, the measured values shift apart to higher values. As a result, precise measurement results cannot be obtained.
Alternatively, in an apparatus for both whole blood samples and serum samples which is already available commercially, a measuring sequence, an analysis program and the like are usually changed for measurement of a whole blood sample by designating the "whole blood measurement" on operation panel of the apparatus. However, where the number of samples is large, it is time- and labor-consuming to designate the "whole blood measurement" every time when a whole blood sample is used, and, where whole blood samples and serum samples are both used, it is also time- and labor-consuming to re-designate every time when the types of samples are changed. Furthermore, if the type of a sample is mis-designated, accurate measurement results are not obtained.


Disclosed is an object oriented netlist database that stores electrical circuit data parsed from a netlist text file that is formatted in HSPICE or Circuit Design Language (CDL) formats. To obtain the netlist text file, an electrical circuit schematic of an electrical circuit is created using a commercially available electrical schematic capture software tool. The electrical schematic capture software tool is then directed to create the netlist text file that is representative of the electrical circuit. A netlist text file parser program first creates the object oriented netlist database structure, then parses the netlist text file, and finally fills the netlist database with objects that represent the electrical circuit data contained in the netlist text file. Analysis software may be written to programmatically access the electrical data stored in the netlist database using netlist database access subroutines that are part of the netlist database objects. The analysis software may be used to locate topological circuit problems within the electrical circuit represented by the electrical circuit data. The analysis software may be run against the electrical circuit prior to laying out the electrical circuit for manufacture as an integrated circuit. This means topological circuit problems associated with manufacturing the electrical circuit as an integrated circuit may be found before time is taken to lay out, or manufacture, the electrical circuit as an integrated circuit.

a. Field of the Invention
The present invention pertains generally to integrated circuit design and manufacturing, and more specifically to software and database techniques that aid in analyzing an electrical circuit that is intended to be manufactured as an integrated circuit.
b. Description of the Background
The process of creating an integrated circuit begins by first designing an electrical schematic of an electrical circuit that will someday be created as an integrated circuit. Until the electrical circuit schematic is designed, the layout of the integrated circuit cannot begin. To make circuit design more efficient and less prone to error, software tools have been created to assist in creating the electrical circuit schematic drawing. The software tool, commonly called electrical schematic capture software, allows an electrical circuit designer to create an electrical circuit schematic in much the same manner as computer aided design (CAD) software tools assist a mechanical draftsperson in creating a mechanical drawing of a physical device. Some of the most common electrical schematic capture software tool vendors include: Mentor Graphics Corporation, Cadence Design Systems, and Synopsys, Inc. Many of the electrical schematic capture software tool vendors also supply electrical circuit analysis and simulation software tools, and integrated circuit layout and testing software tools. Mentor Graphics Corporation is located at 8005 SW Boeckman Road, Wilsonville, Oreg. 97070, and may be contacted at phone numbers 800-592-2210 and 503-685-7000 Cadence Design Systems is located at 2655 Seely Avenue, San Jose, Calif. 95134, and may be contacted at phone number 408-943-1234 Synopsys, Inc. is located at 700 East Middlefield Road, Mountain View, Calif. 94043, and may be contacted at phone numbers 650-584-5000 and 800-541-7737.
The electrical circuit designer typically lays out an electrical circuit schematic by placing primitive electrical devices onto an electrical schematic page. The electrical circuit designer then connects the primitive electrical devices with a line in a manner that creates the desired electrical circuit. The line represents an electrically connecting wire, or an electrical short, between the connected primitive electrical devices. A primitive electrical device is a basic electrical device that cannot be broken down into smaller devices within the electrical schematic capture software. The primitive electrical device is typically a device such as a resistor, capacitor, inductor, diode, transistor, and other similar basic electrical devices. The attributes, or properties, of each primitive electrical device are specified by the electrical circuit designer, and stored within the electrical schematic capture software. The device attributes determine the type and characteristics of each primitive electrical device within the system. For instance, a resistor might have attributes to define resistance, power ratings, and electrical connection points. Other primitive electrical devices would have similar, appropriate attributes to define the electrical characteristics for the primitive electrical device.
Many times, an electrical circuit designer may want to reuse a part of a circuit, sometimes called a sub-circuit, in other sections of the overall circuit. This is accomplished within the electrical schematic software tool by defining a sub-circuit as a macro. The macro has macro attributes similar to the primitive electrical device that define the external electrical connection points for the macro. The makeup of the internal electrical devices determine the electrical behavior of the macro. A macro can be made up of other macros defined within the electrical schematic capture software tool, as well as primitive electrical devices.
After the electrical circuit schematic is completed, the electrical circuit represented by the electrical circuit schematic is simulated to insure the electrical circuit functions as desired by the circuit designer. The simulation of the electrical circuit may be performed by the electrical schematic capture software tool, or by another analysis software tool. The choice of using the electrical schematic capture software tool simulation or an external simulation software tool depends on the complexity of the electrical circuit, and the complexity of the desired simulation. In order to allow an external software tool to analyze the electrical circuit, the electrical schematic software tool has the ability to create a netlist text file representing the electrical circuit in a text form. The netlist text file contains all of the data defining the primitive electrical devices, the electrical attributes of each primitive electrical device, the sub-circuit macros, the electrical attributes of each macro, the electrical connections for all of the primitive electrical devices and macros, and the attributes of each electrical connection including the connection point of each primitive electrical device and macro included in each electrical connection. HSPICE and Circuit Design Language (CDL) are considered two of the most common netlist text file formats, even though there are other netlist text file formats available. HSPICE is the most common netlist text file format, and is considered a defacto industry standard. HSPICE is a registered trademark of Synopsys, Inc., and information concerning the HSPICE netlist text file format may be obtained by contacting Synopsys, Inc. using the previously stated Synopsys, Inc. contact information. Circuit Design Language (CDL) netlist text file format is controlled by Cadence Design Systems, and information concerning the Circuit Design Language (CDL) netlist text file format may be obtained by contacting Cadence Design Systems using the previously stated Cadence Design Systems contact information. Another netlist text file format is SPECTRE for use with SPECTRE software produced by Cadence Design Systems. SPECTRE is a registered trademark of Cadence Design Systems, Inc., and information concerning the SPECTRE netlist text file format may be obtained by contacting Cadence Design Systems using the previously stated Cadence Design Systems contact information.
The netlist text file is imported by the external analysis software, and the electrical circuit is simulated. If errors in the electrical circuit are found, changes are made to the electrical circuit schematic in the electrical schematic software package. The netlist text file for the updated electrical circuit schematic is created and imported into the analysis software. The simulation and circuit schematic modification is repeated until the electrical circuit functions as desired on the simulator. Many of the analysis software tools allow the user to make modifications to the circuit being simulated so that the analysis process is not too cumbersome.
Once the electrical circuit functions properly within the simulator, the electrical circuit must then be created as an integrated circuit. The same netlist text file used to send electrical circuit data to external analysis and simulation software tools is used to export electrical circuit data to an integrated circuit layout software tool. The integrated circuit layout software tool imports the electrical circuit data in the netlist text file, and uses the electrical circuit data to layout the physical features of the integrated circuit that create the desired electrical circuit. After the integrated circuit layout is performed additional analysis and simulation of the integrated circuit is performed. The analysis and simulation of the integrated circuit allows the circuit designer to perform topological checks of the integrated circuit to find parasitics within the integrated circuit layout. A topological check may be configured to look for layout guidelines, known as Design Rule Checks (DRC's). For example, a topological check may look for a circuit element that has two MOSFET transistors connected together from the drain of one transistor to the gate of the other transistor, and where the source of each transistor is connected to a different ground plain. Since the ground plains may be at different electrical potentials there is a parasitic effect between the two transistors that may cause problems in the function of the circuit that would not be present in a simulation of the electrical circuit that does not include the physical integrated circuit layout. If problems are found during the analysis and simulation of the integrated circuit layout, the circuit changes are made using the electrical schematic capture software tool and the integrated circuit layout is performed again.
After a satisfactory analysis and simulation is performed on the integrated circuit layout, the integrated circuit is created and electrically tested for proper operation. If a problem is encountered, the electrical circuit schematic must be updated within the electrical schematic software tool, and the testing, simulation, layout, and manufacturing of the integrated circuit must be performed again to insure a properly functioning integrated circuit.
The present application is filed simultaneously with application Ser. No. 10/956,860, entitled "Netlist Query Language" by the present inventor, Eric Miller, filed Sep. 30, 2004, the full text of which is hereby specifically incorporated by reference for all it discloses and teaches.


An apparatus for growing a single crystal is disclosed which includes a double crucible assembly. The double crucible assembly has an outer crucible and an inner crucible disposed in the outer crucible. A support member is provided for supporting the inner crucible, and the support member is formed of an inorganic oxide non-reactive with silicon oxide. The upper end portion of the inner crucible may be formed of the same inorganic oxide. Alumina or mullite is suitable as the inorganic oxide. With the above construction, silicon single crystals obtained by the crystal growing apparatus will be free of contamination by carbon or heavy metals, and will exhibit excellent quality.

The present invention relates to an apparatus for growing single crystals, which can prevent semiconductor single crystals from being contaminated by carbon or heavy metals during a drawing operation, and which further reduces crystal defect density within the grown semiconductor single crystals.
Known as one of the methods for growing single crystals of a semiconductor material such as silicon (Si) or gallium arsenide (GaAs) is a continuous Czochralski method which is a modification of a conventional Czochralski method. The continuous Czochralski method involves growing semiconductor single crystals while introducing raw material continuously into an outer crucible of a double crucible assembly, and is regarded as being the most suitable for growing long single crystals of large diameter.
A crystal growing apparatus to be used for carrying out the aforesaid continuous Czochralski method comprises a hermetically sealed container which is filled with an inert gas at a low pressure, a double crucible assembly of quartz (SiO.sub.2) including inner and outer crucibles and placed in the container, a heat-resistant support member for releasing the inner crucible from the outer crucible and retaining the same above the outer crucible, and a heater for heating a semiconductor melt contained in the double crucible assembly.
In view of machinability and heat resistance, the aforesaid support member is suitably formed of a material having a high melting point such as molybdenum (Mo), tungsten (W), niobium (Nb), tantalum (Ta) or the like. Additionally, silicon nitride (Si.sub.3 N.sub.4) or silicon carbide (SiC) may be used as the material for the double crucible assembly, and in that case, the support member may be formed of amorphous carbon (graphite).
For growing semiconductor single crystals using the aforesaid double crucible assembly, a prescribed amount of a semiconductor raw material is first introduced in the double crucible assembly, and an inert gas such as argon gas is introduced into the hermetically sealed container. Thereafter, while rotating the double crucible assembly, the semiconductor raw material is heated above a temperature of growth of single crystals and melted completely. Then, a seed crystal is immersed in the semiconductor melt and pulled vertically upwards while rotating the crucible assembly, whereby a semiconductor single crystal is grown.
Furthermore, as the crystal grows, a new charge of the semiconductor material of a prescribed amount corresponding to the growth of the single crystal, i.e., pulled amount, is continuously furnished into and melted in the outer crucible and transferred to the inner crucible.
In the aforesaid apparatus of single crystal growth, however, it has recently been found that the semiconductor melt or grown single crystals may be contaminated by the substances from which the support member is formed. More specifically, when growing silicon single crystals, acidic silicon oxide (SiO) vapor is produced from the silicon melt and graphite reacts therewith to produce carbon monoxide (CO), and this carbon monoxide causes lattice defects within the silicon single crystals which are being pulled. Furthermore, the material with high melting point such as molybdenum or tungsten is oxidized by the acidic SiO vapor, and the resulting oxides are captured in the silicon single crystals and cause minute crystal defects which are referred to as stacking faults.
The aforesaid contaminations by carbon or heavy metals have not been previously taken into consideration. However, due to the recent demands towards higher purity and uniform quality, the adverse effects of the contaminations on the characteristics of the silicon single crystals have become crucial and nonnegligible.


A safety plate has a first, concave side for abutting a pipe, a second, convex side opposite the first, concave side, an arcuate portion interposed between a first linear portion and a second linear portion, a first edge on the first arcuate portion, and a second edge on the second arcuate portion; wherein the distance between the first and second edges is less than an exterior diameter of the pipe. A method of using a safety plate involves forcing the first side of the safety plate to abut the pipe, the safety plate extending around at least half of the circumference of the pipe.

In home and building construction, a safety plate (also known as a nail plate, stud guard, or notch plate) is typically secured to a stud to prevent a nail or screw from penetrating one or more pipes passing through the stud. In other words, nails and screws are used to secure drywall or other materials to the studs. Without a safety plate, the nail may enter the stud and puncture the pipe or wiring passing through the stud. To prevent this from occurring, safety plates have been used (and are required in many jurisdictions to pass an inspection) that are secured to the exterior of a stud. However, there are several scenarios for which the safety plates in the art are ineffective. For example, if the stud gap is larger than the safety plate, builders often attempt to combine multiple safety plates to protect the pipe. However, combining safety plates is not ideal, as it creates weak points and may not properly protect the pipe or wiring. Accordingly, there is a need for a safety plate that does not require attachment to the studs.
In other scenarios, the safety plate is often larger than the required coverage area, often resulting in portions of the safety plate that remain unsecured from a stud (i.e., overhanging edges). Therefore, despite the prior art's attempts, there still remains a need for a safety plate that can easily protect a pipe in a wall regardless of the number of studs present, and that can protect the pipe at issue without worrying about the size or distance of studs in the wall in relation to the pipe. The present disclosure seeks to solve these and other problems.


A disc clutch assembly is provided that includes first and second sets of generally annular plates spaced alternately with one another. The plates of the first set have a friction interface. The first and second sets of plates are selectively engagable with one another at the friction interface for transferring torque loads. Separating devices are in contact with the plates radially inward of the friction interface. The separating devices are configured to bias the respective ones of the first and second sets of plates apart from one another when not selectively engaged.

Disc clutches, such as rotating-type clutches and brake-type clutches used in transmissions, have sets of closely spaced plates that are selectively engagable with one another to transmit torque loads. The plates generate significant amounts of heat, and require cooling and lubrication. The lubricated plates tend to generate drag, causing considerable spin losses.

Disc clutch assembly with separating device


In accordance with an embodiment of the disclosed matter, a voltage regulator may supply power to a component within a computer system. A timer may be provided. The voltage regulator may operate synchronously, and when the timer expires the voltage regulator may operate non-synchronously. For one embodiment, the voltage regulator may operate non-synchronously when the timer expires and the component is in a sleep state.

Computer systems are becoming increasingly pervasive in our society, including everything from small handheld electronic devices, such as personal data assistants and cellular phones, to application-specific electronic devices, such as set-top boxes, digital cameras and other consumer electronics, to medium-sized mobile systems such as notebook and tablet computers, to desktop systems, workstations, and servers. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. To provide more powerful computer systems for consumers, processor designers strive to continually increase the operating speed of the processor. Unfortunately, as processor speed increases, the power consumed by the processor tends to increase as well.
Historically, the power consumed by a computer system has been limited by two factors. First, as power consumption increases, the computer tends to run hotter, leading to thermal dissipation problems. Second, the power consumed by a computer system may tax the limits of the power supply used to keep the system operational, reducing battery life in mobile systems and diminishing reliability while increasing cost in larger systems.
One method of reducing the amount of power consumed by a computer system is to design the system such that it is capable of operating in two different states. In a first state of operation, only the most vital functions of the system, such as those dedicated to monitoring for user input, may be active. This may be referred to as a "sleep state." During the sleep state, the computer system may consume very little power from a voltage regulator (alternatively referred to as a power supply, power source, voltage supply, voltage source, Vcc supply, or Vcc source). In a second state of operation, the computer system may be busy executing instructions to accomplish a particular task. This may be referred to as a "wake state." During the wake state, the computer system may consume a greater amount of power from the voltage regulator. Various components of the computer system similarly operate in sleep and wake states. The definition of these states, with respect to the individual components, may be particular to the design and function of the components.
Unfortunately, various components of a computer system, such as the voltage regulator, may be designed to operate more efficiently during one state than during another. This may result in poor average power consumption over an extended period of time.
One or more embodiments of the disclosed matter may address one or more of these issues.

Method and apparatus for operating a voltage regulator based on operation of a timer


A single focus lens is provided and includes: in order from an object side of the single focus lens, a first lens having positive power and having a convex surface on the object side; a second lens of a negative meniscus lens and having a concave surface of the object side on its paraxial axis; and a third lens of an aspherical lens having a convex surface on the object side on its paraxial axis. The single focus lens satisfies conditions specified in the specification.

1. Field of the Invention
The present invention relates to a single focus lens that is suitable for use in small apparatus having an imaging function such as cell phones with a camera, PDAs (personal digital assistants), and digital still cameras.
2. Description of Background Art
Imaging apparatus such as digital still cameras employ an imaging device such as a CCD (charge-coupled device) sensor or a CMOS (complementary metal oxide semiconductor) sensor. In recent years, such imaging devices have been miniaturized to a large extent. Accordingly, imaging apparatus main bodies and lenses mounted thereon have come to be required to be reduced in size and weight. On the other hand, in recent years, imaging devices having a large number of pixels have been developed to attain high image quality and, accordingly, lens systems have come to be required to be high in such performance as resolution and contrast.
An example of imaging lenses used in such imaging apparatus is one disclosed in JP-A-10-48516. JP-A-10-48516 discloses an imaging lens consisting of first to third lenses that are arranged in this order from the object side (three-lens system). In this imaging lens, the first lens is small in power and an aperture stop is disposed between the second lens and the third lens.
As described above, recent imaging devices have been miniaturized and increased in the number of pixels and, accordingly, imaging lenses have come to be required to exhibit a high resolution and be high in the degree of compactness. Although the imaging lens of JP-A-10-48516 attains certain levels of performance and compactness with a small number of lenses (three lens system), development of a more compact, higher-performance lens system is desired.


Disclosed are a driving circuit for a display panel, a display module, a compensation method of the display module, and a display device. According to the present disclosure, a TCON circuit board provided with a plurality of sets of reference voltage outputs is used to independently input a reference voltage to each driver chip through a corresponding set of reference voltage input lines, that is, each driver chip receives an independent reference voltage signal, in this way, the reference voltages output by the TCON circuit board corresponding to each driver chip can be adjusted, the reference voltages received by all driver chips are made to be the same voltages.

With the continuous development of a display technology, large-size display panels are more and more favored by people. With the continuous increase of display panels, the requirements for the driving ability are higher and higher. Therefore, a plurality of driver chips (source ICs) need to be spliced in the display panel to drive the display panel. Each driver chip is independent and is provided with its own gamma circuit, and each gamma circuit is configured to generate a gamma voltage to drive the display panel to display. In order to ensure that there is no split screen phenomenon during display of the large-size display panels, the gamma voltages output by each driver chip needs to be consistent.

Driving circuit for display panel, display module, compensation method of display module and display device

Chengdu BOE Optoelectronics Technology Co., Ltd.


Provided is a light emitting device in which deterioration of the substrate member can be reduced. The light emitting device includes a base member mainly made of a resin, a plurality of wiring portions and arranged on the base member via an adhesive agent, a groove portion defined between adjacent wiring portions, and at least one light emitting element which is disposed straddling at least a part of the groove portion. The adhesive agent is applied covering the base member from the groove portion, and contains a light-shielding member. The light-shielding member shields the base member from light, for example at a specific wavelength, emitted from the at least one light emitting element.

1. Technical Field
The present disclosure relates to a light emitting device.
2. Background Art
There has been proposed a light emitting device which includes a plurality of light emitting elements arranged on a flexible substrate member which uses a resin material (see Patent Literature 1: JP2005-322937A). In the light emitting device disclosed in JP2005-322937A, the light emitting elements are connected in a flip-chip configuration via bumps or the like to conductive regions formed on a polyimide substrate member.


A multi-part eccentric hinge assembly for a plumbing fixture has two hinge bodies, which when connected pivotally couple a movable part of the fixture to a fixed part, for example, a lid or cover to a bowl deck. One of the hinge bodies has a radial portion and an offset portion. The radial portion generally extends along a line intersecting a pivot axis from a connection for pivotally connecting the hinge assembly to the plumbing fixture. The offset portion intersects the radial portion at one side of the pivot axis and extends back toward an opposite side of the pivot axis to a free end that connects to the second hinge body by a connector. The single hinge body is integrally formed with the moveable part so that the follows an eccentric path when the hinge body is pivoted about the pivot axis.

The present invention relates to hinge structures for attaching movable parts to plumbing fixtures. More particularly it relates to a multi-part eccentric hinge assembly for connecting a seat, cover or the like to a plumbing fixture.
Plumbing fixtures such as bidets and toilets for cleaning and eliminating waste are well known. It is also well known for such fixtures to have a bowl holding plumbing water and a seat placed on the bowl for sitting on during use. The seat is typically pivotally attached to the bowl to allow it be moved out of the way, as when cleaning the bowl for example. To prevent objects from falling into the bowl, the seat is also often covered by a lid or seat cover that lies above the seat. Like the seat, the seat cover can be pivotally connected to the bowl.
Conventional seat and cover assemblies typically mount to the bowl by two bolts that fit through two openings in the rear deck of the bowl. A common hinge or two separate hinges connect the seat and cover to the mounts so that the cover or cover and seat can be pivoted up off of the bowl. In such conventional assemblies the hinges are exposed and somewhat unsightly. They also become a location where debris and urine can collect, thus making it more difficult to clean the fixture.
In certain fixtures, the location of the seat pivot axis is displaced from that of the cover. This can be to avoid the aesthetic and cleanliness problems associated with exposed hinges, or for other reasons, for example to accommodate raised rear deck areas of the bowl that contain washing controls and other features. Concealing the pivot axis presents other complications. Since the hinge must connect the seat cover, for example, to the bowl, the hinge arm must extend through an opening in the structure that conceals the pivot axis, usually a plastic housing mounted over the rear deck. If conventional straight hinges were used, the openings in the housings would have to be oversized, for example long slots, to permit the cover to pivot 90 degrees or slightly more as need to open and close the cover. Oversized openings like this create gaps into which object can fall and debris and liquids can collect. This problem has been overcome by using eccentric hinges, for example as taught in U.S. Pat. No. 5,450,633. As disclosed therein, such hinges can have a complex configuration, such as bent-back "U" or "C" shape, that allows the free ends of the hinges to follow a non-circular arc as the other ends pivot about the pivot axis. Such hinges can pivot 90 degrees or more through openings sized only slightly larger than the dimension of the hinge arm, thereby alleviating the aforesaid problem.
An additional complication with such concealed hinge arrangements pertains to manufacturing and assembly. To reduce assembly time and create a solid feeling connection at the seat cover, it is beneficial to form the hinge and seat cover as one piece, as in U.S. Pat. No. 5,450,633. However, assembling the hinges to a concealed pivot axis then becomes difficult. Either the pivot ends of the hinges have to be slid down through the narrow openings and somehow blindly connected to the pivots, or the openings in the housing must be open-ended, which again raises dirt collection issues.
Hence, a need exists to provide eccentric hinges for use in concealed pivot axis arrangements that can be more easily assembled to plumbing fixtures.


A combined data and power transmission arrangement has one or more power supplies and loads interconnected by a power transmission line, with transmitters and receivers for transmitting a digital data signal over the transmission line. The transmitter and receiver each include an inductor for providing a high impedance barrier to a data signal on the line, so as to isolate the data signal from the power supply and load. The receiver includes circuits for tracking the mid-point value of the data signal to produce a threshold value, and for comparing the threshold value with the data signal to produce an output signal. The threshold value is a controlled positive feedback signal derived from the output of the comparator by way of a positive feedback loop having a time constant approximately equal to the time constant of the transmitter.

This invention relates to combined data and power transmission arrangements.
A combined data and power transmission arrangement may be used, for example, to distribute electrical power to various components in a vehicle, and also to transmit digital data signals between those components.
A problem with combining data and power transmission on the same physical cable is that fluctuations in the power supply level, caused for example by variations in the power drawn by the load, can affect the data signal levels, and hence can result in corruption of the data. The data signal can be isolated from power voltage variations by capacitively coupling it to the line. However, a side effect of this is that the average level of the data will then depend on the data pattern, thus making the data pattern-sensitive. The object of the present invention is to provide a way of reducing or overcoming these problems.


An electronic file containing height field mapping data is output to a specialized printer and used to create one or more three dimensional molds. The molds, in turn, may be used to fabricate bas-relief tiles and similar three-dimensional objects from various materials. The process allows for rapid deployment of customized design elements in many construction applications and environments.

1. Technical Field
The present invention relates generally to manufacturing and more particularly to a process for the creation of certain three-dimensional building materials.
2. Background Art
The construction industry is a constantly evolving and rapidly growing industry, particularly with respect to the development of new and useful processes and materials to be used in the construction of new buildings. The creation and adoption of new processes and materials fuels the growth of the industry by allowing architects to exercise additional freedom in designing new structures that benefit from the inclusion of additional options based on the new processes and materials.
One popular option in many construction projects is the use of various three-dimensional tiles to create a "bas-relief" look and feel. In most cases where these three-dimensional tiles are manufactured by automated processes, the resulting three-dimensional tiles tend to be fairly pedestrian in nature, acknowledging the practical reality of appealing to a mass-market consumer base. Alternatively, where these three-dimensional tiles are laboriously manufactured by hand to create a more desirable custom look, the cost of the resultant three-dimensional tiles can be prohibitive for many applications. Accordingly, while the inclusion of custom three-dimensional tiles may be desirable in certain buildings, the cost may dictate the use of other, less desirable alternatives.
Another significant addition to the design repertoire of many architects is the constantly expanding palette of materials that may be used in various construction applications. For example, new types of glass, plastics and various polymers are being used in new and creative ways for creating bold and exciting design elements that can be incorporated into new buildings and structures.
Finally, new design and construction methodologies have also been enhanced by the development and deployment of certain computer-based technologies that can be used in the overall design and construction process. New software applications allow architects and builders to create sophisticated computer models of new buildings before a single construction worker lifts a hammer to pound a nail. Additionally, architects and designers can now use computers to experiment with materials, colors, and textures for new construction projects before committing to a final design. Finally, the continually accelerating growth and deployment of computer technology has provided significant advantages in the construction industry, even in mundane areas such as estimating, project management, etc.
While all of these various methods, materials and technologies have successfully added value to the construction industry, additional progress can be achieved. Specifically, many of the emerging technologies have yet to find their way to the ultimate destination where the greatest advantage may be realized. Disparate computer technologies and nascent understanding of the application for new materials have combined to slow the rapid adoption and deployment of these items in certain areas of the construction industry. Additionally, some new materials and technologies are still very expensive and difficult to deploy, making it difficult to integrate them into more traditional application environments.
Accordingly, without improved integration and deployment of the various methods, materials and technologies now emerging in the construction industry, the overall design and construction process will continue to be sub-optimal in at least some respects.

Apparatus and method for creating three dimensional relief tiles


The solid-state imaging device includes at least a silicon layer formed with a photo sensor portion and a wiring layer formed on the front-surface side of the silicon layer. Light enters from the rear-surface side opposite to the front-surface side of the silicon layer and the thickness of the silicon layer 4 is 10 μm or less. The photo sensor portion includes sensors configured to convert the light into signals representing an image. Each of the sensors includes a relatively highly doped first conductivity type region adjacent the front surface side of the silicon layer and serving as a charge storage region, a first relatively lightly doped second conductivity type region extending from the charge storage region toward the rear surface side of the silicon layer and serving as a photo sensitive region, a second relatively highly doped second conductivity type region extending from the front surface side of the silicon layer toward the rear surface side of the silicon layer and serving as a floating diffusion region, and a relatively lightly doped region of the first conductivity type between the floating diffusion region and the charge storage region and under one of the at least one read out gate electrode and serving as a charge read out region.

1. Field of the Invention
The present invention relates to a solid-state imaging device and a method for manufacturing the same, and particularly relates to what is called a solid-state imaging device of a back-illuminated type and a method for manufacturing the same.
2. Description of the Related Art
With a high density integration of a semiconductor device, a transistor and other semiconductor elements have been tried to be more miniaturized and to raise mounting density more than before.
Therefore, in a CMOS image sensor (CMOS type solid-state imaging device), it is required that a pixel is made minute and an element is made to be highly integrated.
However, in a conventional CMOS image sensor in which light detection is performed by irradiating a photo sensor portion with light from a lens formed on a wiring portion through the space between wiring layers, the photo sensor portion can not be irradiated with an enough amount of light, because an eclipse of incident light due to the obstacle such as a wiring layer occurs and an aperture ratio of the photo sensor portion is made small in accordance with the high density integration of device to make the pixel become minute. Accordingly, such problems as lower sensitivity and more shading may occur.
Therefore, the photo sensor portion is irradiated with light from the rear side (opposite side to the wiring portion), so that an effective 100% ratio of aperture can be achieved and sensitivity can be sufficiently raised without an influence of an obstacle such as a wiring layer.
Accordingly, a CMOS image sensor in which the photo sensor portion is irradiated with light from the rear-surface side (opposite side to the wiring portion), what is called a back-illuminated type CMOS image sensor, has been developed.
Then, in the back-illuminated type CMOS image sensor, it is considered that a silicon layer of the photo sensor portion is made thin to obtain higher sensitivity (refer to, for example, patent document 1 or patent document 2).
FIG. 1 is a vertically sectional view schematically showing a back-illuminated type CMOS image sensor to which the above described construction is applied.
In a MOS sensor 100, since a silicon substrate 101 including photo sensor portions 102 is made thin, sensitivity to incident light L can be raised.
Further, since the incident light L is not blocked even if wiring layers 104 are formed on the photo sensor portions 102, flexibility in layout of the wiring layers 104 can be obtained. Accordingly, the high density integration of an element can be obtained by forming the wiring layer 104 to be multi-layered and by minimizing an area of a pixel.
A method for manufacturing the back-illuminated type image sensor having such a thin silicon layer is considered, in which, for example, after a photo diode of a photo sensor portion is formed in a silicon substrate, the silicon substrate is ground from the back thereof to be thin.                Patent document 1: Japanese Published Patent Application No. H6-77461 (FIG. 3)        Patent document 2: Japanese Published Patent Application No. H6-283702 (FIG. 2)
However, in the above-described manufacturing method, an interface of the silicon substrate after grinding the back surface becomes electrically unstable. Also, a mechanical damage may affect the silicon substrate.
As a result, dark current is caused due to the above problems.
Hence, an image sensor of the back-illuminated type having the above-described structure has a limitation in use such as requiring a cooling process.
Furthermore, light absorption depends upon the thickness of a silicon layer; however, since the thickness is made thin by grinding, control for the thickness of the silicon layer (silicon substrate) of the photo sensor portion becomes deteriorated, so that the spectroscopic characteristic as the sensor tends to disperse.
As a result, the manufacturing yield ratio becomes deteriorated, and the cost may increase because of such a problem.
Therefore, the back-illuminated type structure has been used only for limited purposes, though the sensitivity of the photo sensor portion could be improved.
In addition, a conventional image sensor of the back-illuminated type structure has several ten micro-meter of the thickness of a silicon layer in which the photo sensor portion performing the photo-electric conversion is formed; and when a pixel is miniaturized, the electric-charge of a signal diffuses between adjacent pixels to generate mixed color.
Accordingly, it is difficult to realize a minute pixel.

Solid-state imaging device and method for manufacturing the same