A method for forming a field emitter structure. In one embodiment, the present invention creates a structure having a cavity formed into an insulating layer overlying a first electrically conductive layer. The present invention also creates a second electrically conductive layer with an opening formed above the cavity in the insulating layer. The present embodiment deposits a layer of electron emissive material directly onto the second electrically conductive layer without first depositing an underlying lift-off layer such that the electron emissive material covers the opening in the second electrically conductive layer and forms an electron emissive element within the cavity. The present invention applies a first potential to the first electrically conductive layer, such that the first potential is imparted to the electron emissive element formed within the cavity. The present invention also applies a second potential to the second electrically conductive layer, such that the second potential is imparted to the closure layer of electron emissive material. In the present embodiment, the second potential comprises an open circuit potential. The present invention then exposes the field emitter structure to an electrochemical etchant wherein the electrochemical etchant etches electron emissive material which is biased at the open circuit potential. In so doing, the layer of electron emissive material is removed from above the second electrically conductive layer without etching the electron emissive element formed within the cavity.

Field emission cathodes are electron emitting devices which are used, for example, in flat panel displays. A field emission cathode or "field emitter" emits electrons when subjected to an electric field of sufficient strength and appropriate polarity. A side sectional view depicting conventional steps used to manufacture a field emission cathode is shown in Prior Art FIG. 1A. More specifically, in Prior Art FIG. 1A, a first conductive layer or "row electrode" 102 has a resistive layer 104 disposed thereon. An inter-metal dielectric layer 106 disposed above resistive layer 104 has a cavity 108 formed therein. As shown in Prior Art FIG. 1A, a second conductive layer or gate electrode 110 resides above inter-metal dielectric layer 106. A hole or opening 112 is formed through gate electrode 110 directly above cavity 108. Opening 112 is used to form the field emitter which will reside within cavity 108. Typically, the formation of the field emitter is accomplished, in part, using a lift-off or "parting layer", and a closure layer. Unfortunately, conventional lift-off and closure layer deposition and removal methods have severe drawbacks associated therewith.
With reference next to Prior Art FIG. 1B, a side sectional view illustrating the deposition of a lift-off layer 114 is shown. Lift-off layer 114 is formed using an angled physical vapor deposition of, for example, aluminum. Arrows 118 illustrate the angled nature of the deposition of lift-off layer 114. The angled deposition of lift-off layer 114 is required to insure that no lift-off layer material, i.e. aluminum, is deposited into the bottom of cavity 108. As shown in Prior Art FIG. 1B, however, some lift-off layer material 115 may be deleteriously deposited along the sides defining cavity 108. In order to achieve an angled deposition, the entire field emitter structure must be rotated during the deposition of lift-off layer 114. As a result, considerable difficulty, expense, and complexity is introduced into the field emitter structure manufacturing process. Also, lift-off layer 114 must have uniform thickness across the surface of gate electrode 110. This additional requirement of uniformity further complicates the lift-off deposition process.
With reference still to Prior Art FIG. 1B, lift-off layer 114 has another substantial disadvantage associated therewith. Specifically, lift-off layer 114 reduces the opening above cavity 108. That is, lift-off layer 114 attaches to the inner diameter of opening 112 in gate electrode 110. As a result, the diameter of opening 112 is effectively reduced. Hence, the opening above cavity 108 is limited to the diameter of opening 116 in lift-off layer 114. Therefore, the diameter of opening 112 in gate electrode 110 must be increased to insure that the final diameter (i.e. the diameter of opening 116 in lift-off layer 114) is as large as is desired. It is well known, however, that increasing the diameter of opening 112 in gate electrode 110 can reduce the performance characteristics of the field emitter structure.
Referring next to Prior Art FIG. 1C, a side sectional view illustrating the initial formation of a closure layer 118 is shown. Closure layer 118 is comprised of electron emissive material such as, for example, molybdenum. The electron emissive material which forms closure layer 118 is also deposited into cavity 108 as shown by structure 120. Typically, the electron emissive material is deposited using, for example, an e-beam evaporative deposition method.
Referring now to Prior Art FIG. 1D, a side sectional view illustrating a completed deposition of electron emissive material is shown. As shown in Prior Art FIG. 1D, closure layer 118 completely seals cavity 108. Additionally, as the electron emissive material is deposited as shown in Prior Art FIGS. 1C and 1D, an electron emitting structure 120 commonly referred to as a "Spindt-type" emitter is formed within cavity 108 (Spindt-type emitters are described in detail in U.S. Pat. No. 3,665,241 to Spindt et al. which is incorporated herein by reference as background material). After Spindt-type emitter 120 is formed, closure layer 118 must be removed.
With reference now to Prior Art FIG. 1E, a side sectional view illustrating the removal of closure layer 118 is shown. When removing closure layer 118, care must be taken not to damage or otherwise adversely affect Spindt-type emitter 120. Such a removal process is further complicated by the fact that both closure layer 118 and Spindt-type emitter 120 are formed of the same electron emissive material. Prior art techniques remove closure layer 118 by etching lift-off layer 114 using an etchant which attacks the aluminum lift-off layer 114. As a result, lift-off layer 114 "lifts" from underlying gate electrode 110 and, consequently, removes closure layer 118, as illustrated in Prior Art FIG. 1E. Prior art lift-off layer etchants do not, however, attack the electron emissive material of either closure layer 118 or Spindt-type field emitter 120. Unfortunately, such a lift-off process results in the generation of flakes or contaminating chunks, typically shown as 122a-122c, which contaminate the etchant. Flakes or chunks 122a-122c can also redeposit within cavity 108, as shown by chunk 122c, and compromise the integrity of Spindt-type emitter 120 formed therein. As a result, the Spindt-type emitter can be severely damaged or even shorted to gate electrode 110. Hence, prior art "lift-off" closure layer removal methods include deleterious side effects.
Thus, a need exists for a closure layer deposition and removal method which eliminates the need for a complex and difficult to manufacture lift-off layer. A further need exists for a closure layer deposition and removal method which does not substantially limit gate electrode hole diameter. Yet another need exists for a closure layer deposition and removal method which reduces deleterious redeposition of portions of the closure layer within the emitter cavity.

Field emitter fabrication using open circuit electrochemical lift off


The present disclosure provides a photodiode, a display substrate, and manufacturing methods thereof, and a display device. The method for manufacturing the photodiode includes: forming a semiconductor material layer on a base substrate in a non-display region of a display substrate, the semiconductor material layer including a first contact area, a second contact area, and a semiconductor area sandwiched therebetween; processing the first contact area of the semiconductor material layer to form a first contact electrode; processing portions of the semiconductor material layer and the second contact area away from the base substrate in the semiconductor area, to form a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer being located on a side of the first semiconductor layer away from the base substrate; and processing the second semiconductor layer in the second contact area to form a second contact electrode.

With the continuous development of technology, smart devices have gradually entered people's life. For a smart device having a display function, if the display screen is kept in a high-brightness state for a long time, not only the power consumption will be increased, but also the display effect will be influenced and the visual experience of users will be degraded.

Photodiode for realizing automatic adjustment of display brightness, and display substrate and display device comprising said photodiode


A method and apparatus is provides for decontamination of soil from contaminates such as polychlorinated biphenyls. The method involves (a) admixing a short chain alcohol and a long chain alcohol to provide a solvent composition, (b) admixing the solvent composition with the contaminated soil to extract the contaminant from the soil into the solvent to form contaminated solvent, (c) separating the soil from the contaminated solvent, (d) washing of the decontaminated soil with water to remove residual solvent from the soil, and (e) distillation of the contaminated solvent to separate the reusable short chain alcohol as a light fraction from a heavy fraction containing the long chain alcohol and the contaminant. The apparatus includes (a) a mixer for mixing the soil and solvent, (b) a centrifuge for separating fines from decanted contaminated solvent, (c) a distillation unit for separating the solvent into a reusable light fraction and a waste heavy fraction, and (d) a water reclamation unit for removing residual solvent from the wash water. The method and apparatus are usable for reclaiming contaminated soils.

1. Field of the Invention
The present invention relates to processes and systems for decontamination of soils, and more particularly relates to methods and systems for decontamination of poly chlorinated biphenyl contaminated soils.
2. Description of the Related Art
The problem of poly chlorinated biphenyl (PCB) pollution of soils has been a major concern for some time. Accidental spills and improper land use have left numerous sites across the United States with PCB contaminated soil sites.
Various approaches have been used in efforts to decontaminate polychlorinated biphenyl laden soils. Efforts have included in-situ bio-destruction, thermal desorption, chemical declorination/destruction, and solvent extraction and soil washing. Solvent extraction processes have usually suffered from one or more of the following problems: environment impact of the solvent, lack of efficiency in movement of the contaminant from the soil to the solvent, difficulty of removal of solvent from the soil, solvent expense, and/or difficulty of separation of solvent from the contaminate. Specific decontamination methods are disclosed in Sivavec, Decontamination of Soil and Other Particulate Matter, U.S. Pat. No. 5,427,688 Jun. 27, 1995, and Szejtli et al. Method for the Extraction of Organic Pollutants from Contaminated Soils, U.S. Pat. No. 5,425,881 issued Jun. 20, 1995, which are both incorporated herein by reference.
Consequently, there is a need for a method and apparatus (system) that solves the above problems and provides for efficient removal of polychlorinated biphenyls from soil.

Method and apparatus for decontamination of poly chlorinated biphenyl contaminated soil


Disclosed is a device for use in machining an interior surface of a tubular object which comprises a pair of rails that can be longitudinally instad through the interior section of the tubular object. Braces join the rail for fixing the rails to the tubular object. A platform is movably mounted on the rails to allow longitudinal movement of the platform. A machine tool can be mounted on the platform.

(1) Field of the Invention
The present invention relates to work platform assemblies and more particularly to such assemblies which may be used to machine the interior surface of a tubular object.
(2) Description of the Prior Art
Various devices are disclosed in the prior art for providing access to cylindrical tubular recessed work surfaces. For example:
U.S. Pat. No. 3,058,543 to Prosser discloses a portable scaffold deployed in a vessel. This apparatus makes use of a radially extendable stabilizing arms and expandable width grating.
U.S. Pat. No. 3,870,122 to Faucheux discloses a catwalk that spans the circumference of a dome structure. The apparatus includes a roller track at the end of the catwalk on the side of the roller track which is movable thereon.
U.S. Pat. No. 3,960,242 to Saxonmeyer discloses an orbital service bridge for positioning a work platform at desired positions within an overlying dome shaped structure. Included in the apparatus is a polar crane which has parallel guide rails spanning a cylindrical vessel.
U.S. Pat. No. 5,067,589 to Bartnicki discloses an extendable platform in which two platform sections can be nested or moved apart from one another to increase platform length.
U.S. Pat. No. 5,301,770 to Regan et al. discloses an adjustable work platform assembly for the inside c)f a vessel. The platform is suspended from above and is extendable and collapsible to fit the various diameters of the vessel.
A need, however, exists for a device which can easily machine the interior surface of a tubular cylindrical recessed surface.

Device for machining an interior surface of a tubular object

The United States of America as represented by the Secretary of the Navy


In an exhaust gas purification system, including a catalyst unit carrying an NOx occlusion-reduction type catalyst, a first-stage rich control having a target air-fuel ratio lower than theoretical air-fuel ratio and which is conducted through addition of an amount of a reducing agent meeting an amount of oxygen emitted in the initial stage of regeneration control. In the first-stage rich control a completion of oxygen emission is judged on the basis of an oxygen concentration on the downstream side of the catalyst unit. Upon determination of the completion of the oxygen emission, a later-stage rich control close to the theoretical air-fuel ratio with the target air-fuel ratio increased over that of the first-stage rich control is conducted to thereby accomplish regeneration of the catalyst unit. As a result, there can be prevented not only any outflow of unpurified NOx occurring in the initial stage of regeneration but also any outflow of virgin reducing agents, such as HC and CO, occurring in the later stage of regeneration.

1. Field of the Invention
The present invention relates to a method of exhaust gas purification and an exhaust gas purification system having a catalyst unit carrying a NOx (nitrogen oxides) occlusion-reduction type catalyst that reduces and purifies NOx in exhaust gas from internal combustion engines.
2. Description of the Related Art
Various research and proposals have been made regarding NOx (nitrogen oxides) catalysts to reduce and remove NOx in exhaust gas from internal combustion engines such as diesel engines and certain types of gasoline engines and various combustion units. One of such catalysts is a NOx occlusion-reduction type catalyst, which is a catalyst for decreasing NOx from diesel engines. By using a catalyst unit carrying the NOx occlusion-reduction type catalyst, NOx in exhaust gas can be purified effectively.
This catalyst unit is constructed, having a monolith honeycomb 30M whose structure is as shown in FIG. 7. The monolith-honeycomb 30M, as shown in FIG. 8, is constructed by forming multiple of polygonal cells 30S on a support 31 that is a structural material made of cordierite or stainless steel. On the walls of the cells 30S, as shown in FIGS. 8 and 9, a porous catalyst coat layer 34, which is a catalyst carrying layer, made of alumina (Al2O3) or zeolite is provided. The catalyst coat layer 34 increases the contact surface area with exhaust gas. On the surface of the catalyst coat layer 34, there are carried precious metal (catalytically active metal) 32 and NOx occlusion material (NOx occlusion substance: NOx occlusion agent; NOx absorbent) 33. A catalytic function is provided by the construction described above.
FIGS. 10 and 11 show the configuration and occlusion-reduction mechanism of catalytic substances 32 and 33 on the surface of the carrying layer of the catalyst unit. In the catalyst unit, precious metal 32 having an oxidation function and NOx occlusion material 33 having a NOx occlusion function, are carried on the catalyst coat layer 34. The precious metal 32 is platinum (Pt) or the like. The NOx occlusion material 33 is made of some of alkaline metals such as potassium (K), sodium (Na), lithium (Li) and cesium (Cs), alkaline earth metals such as barium (Ba) and calcium (Ca) and rare-earth metals such as lanthanum (La) and yttrium (Y). Depending on the oxygen concentration in exhaust gas, the catalyst unit having the above described construction will perform the function of NOx occlusion or NOx release with purification of the released NOx.
As shown in FIG. 10, in normal diesel engines, lean-burn gasoline engines and the like, the exhaust gas contains oxygen (O2). In such cases where the air/fuel ratio of exhaust gas is in a lean air/fuel condition, nitrogen monoxide (NO) emitted from engines is oxidized into nitrogen dioxide (NO2) with oxygen contained in exhaust gas by the oxidation catalytic function of precious metal 32. Then, the nitrogen dioxide is occluded in the form of nitrate to the NOx occlusion material 33 such as barium having a NOx occlusion function, thus purifying NOx.
However, if the above reaction continues, the entire portion of the NOx occlusion material 33 having a NOx occlusion function will turn into nitrate, and will therefore lose the NOx occlusion function eventually. Therefore, exhaust gas with high fuel concentration (rich spike gas) is generated by changing the operating conditions of an engine or by injecting fuel into an exhaust passage, and then fed into the catalyst. The rich spike gas has no oxygen and a high carbon monoxide (CO) concentration with a high temperature.
Then, as shown in FIG. 11, in the rich air/fuel condition where there is no oxygen and a high concentration of carbon monoxide with a raised exhaust gas temperature, the nitrate formed after occluding NOx, releases nitrogen dioxide and returns to the original barium and the like. The released nitrogen dioxide, since no oxygen exists in the exhaust gas, is reduced by the oxidation function of carried precious metal 32, thus purifying the exhaust gas. That is, nitrogen dioxide is reduced into water (H2O), carbon dioxide (CO2) and nitrogen (N2) by using carbon monoxide, carbon hydride (HC) and hydrogen (H2) that are reductants in exhaust gas.
For the purpose described above, in an exhaust gas purification system having a catalyst unit carrying a NOx occlusion-reduction type catalyst, as described in Japanese Patent Application Kokai Publication No. 1994-336916, for example, the following regeneration operation is performed. When an estimated NOx occlusion amount reaches a NOx saturation amount, the air/fuel ratio in exhaust gas is made rich, thus decreasing the oxygen concentration in inflowing exhaust gas. That is, a rich control is performed for restoring a NOx occlusion capacity. The rich control causes occluded NOx to be released and the released NOx to be reduced with a precious metal catalyst.
However, in the conventional rich combustion control for regenerating the NOx occlusion capacity of the catalyst unit carrying a NOx occlusion-reduction type catalyst, the rich control is performed at the excess air ratio λ of 1.0 i.e. at the theoretical air/fuel ratio in the initial stage of rich combustion as shown in FIG. 12. At the beginning, the oxygen adsorbed onto the surface of the catalyst is released. The released oxygen consumes reductant in exhaust gas. Therefore, sufficient amount of reductant does not remain to reduce released NOx, so that the NOx reduction reaction is insufficiently activated. As a result, the NOx concentration at a catalyst outlet Cnoxex is remarkably higher compared to the NOx concentration at a catalyst inlet Cnoxin, and a large amount of unpurified NOx is released into the downstream of the catalyst unit. That is, the air/fuel ratio adjacent to the catalyst surface does not become rich because of the oxygen adsorbed on the catalyst surface. Therefore, NOx cannot be reduced and flows out. As a result, there is a problem that the overall performance of NOx purification is degraded.
In addition, in this regeneration control of the catalyst unit, the release of oxygen adsorbed onto the catalyst surface occurs more easily, compared to the release of NOx due to the decomposition of nitrate. As a result, in the initial stage of the regeneration control, NOx remain in a NOx occlusion agent at a high degree. This causes a problem that the restoration of a NOx occlusion capacity becomes insufficient, unless the regeneration control time is set, taking the above described issue into consideration.
In order to solve the problem, there is considered making the exhaust gas more fuel-rich. That can be attained by measuring the amount of oxygen adsorbed onto the catalyst unit in an experiment in advance and increasing the amount of reductant corresponding to the amount of oxygen released from the adsorbed oxygen.
An example close to this consideration is proposed in Japanese Patent Application Kokai Publication No. 2000-27677, which is an exhaust gas purification unit for a lean-burn internal combustion engine. In this exhaust gas purification unit, a catalyst unit having an oxygen (O2) storage function is placed in the upstream of a catalyst unit carrying a NOx occlusion-reduction type catalyst. The catalyst unit in the upstream works as a catalyst unit for startup time and its main purpose is to remove HC and CO components that are released in large amounts from an engine at startup. In this exhaust gas purification unit, the catalyst unit for startup time releases oxygen during a rich spike operation for regenerating the catalyst unit carrying a NOx occlusion-reduction type catalyst. By releasing oxygen, it is intended to solve the problem that unpurified NOx are flowed out toward the downstream of the catalyst unit in the initial stage of the regeneration.
This exhaust gas purification unit comprises a means for decreasing storage that makes an air/fuel ratio even richer than that during the rich spike operation for regenerating a NOx occlusion-reduction type catalyst by adding reductant to consume the entire amount of oxygen released from the catalyst unit in the upstream for startup time. The means for decreasing storage prevents the air/fuel ratio adjacent to a NOx occlusion-reduction type catalyst from becoming less rich than the theoretical air/fuel ratio in the initial stage of the rich spike operation, thus preventing NOx from being unpurified.
However, if the regeneration control of increasing the amount of reductant corresponding to the amount of released oxygen is employed, NOx continue to be released even after the completion of oxygen release. Because of this, the amounts of HC and CO that are reductant in exhaust gas become excessive, after oxygen that has been absorbed by an oxygen storage function, is released from the surface of a catalyst. As a result, there arises a problem that the exhaust gas is extremely deteriorated since HC and CO that have not been used for the reduction of NOx are flowed out in unpurified state toward the downstream of the catalyst unit carrying a NOx occlusion-reduction type catalyst.
That is, as shown in FIG. 13, when the more fuel-rich control whose excess air ratio λ is smaller than 1.0, i.e. whose air/fuel ratio is smaller than the theoretical air/fuel ratio is performed, the NOx concentration at a catalyst outlet Cnoxex in the initial stage becomes lower. However, the HC concentration at the catalyst outlet Chcex becomes extremely high since the consumption of reductant is decreased when oxygen is no longer released. As a result, after oxygen adsorbed on the surface of a catalyst is consumed, a large amount of HC flows out (or slips) unused toward the downstream of the catalyst unit.
Meanwhile, an exhaust gas purification unit for an internal combustion engine is proposed, for example, as described in Japanese Patent Application Kokai Publication No. 2002-188430. In this exhaust gas purification unit, the feedback control for the supply amount of reductant is performed by using an air/fuel ratio sensor placed in the downstream of a catalyst unit carrying a NOx occlusion-reduction type catalyst. In the initial stage of regeneration control, the feedback control is stopped during a predetermined period until the output value from the air/fuel ratio sensor reaches a certain predetermined value, i.e. during a period until oxygen (O2) storage effect converges. This prevents unnecessary supply of reductant caused by the oxygen occlusion function of a NOx occlusion material (NOx absorbent). At the same time, this prevents the deterioration of exhaust emissions caused by excessive supply of reductant and the useless consumption of reductant.
However, in this exhaust gas purification unit for an internal combustion engine, in the downstream of a catalyst unit, an air/fuel ratio is considered to exhibit a high apparent air/fuel ratio temporarily due to the release of oxygen caused by oxygen storage effect. Based on this consideration, the unit prevents the supply amount of reductant from exceeding the amount of reductant that should be supplied to the catalyst unit.
Accordingly, the consumption of reductant by released oxygen is not taken into consideration. As a result, there arises a problem that unpurified NOx cannot be prevented from flowing out toward the downstream of the catalyst unit in the initial stage of rich spike operation.

Method of exhaust gas purification and exhaust gas purification system


The present invention discloses a serially connected LED lamps control circuit device, which is applicable for an integrated circuit and has the following three features: using a buffer circuit to increase the DATA and Clock lines to extend the distance between a plurality of serially connected devices, delaying half cycle of the timing of the DATA line to enhance overall system stability, and adding an internal latch signal generate circuit to simplify the requirements for external connections.

The application of LED becomes popular, and the progress of LED brightness also promotes an extensive use of LEDs. Based on years of experience on research, development and selling of the LED products, the inventor of the present invention has developed a control device for improving system stability as well as greatly simplifying the system wiring.
The design of serially connected LED lamp control device is mainly applied for the occasion of connecting a series of LED lamps, and each LED lamp is controlled effectively and independently.
Three traditional methods for controlling the serially connected LED lamps are described as follows:
The first design uses a control box to control all lamps and an electric cable to connect each of the LED lamps. The cost for such method is lower; however, if the lamps are farther apart from each other or evenly distributed or arranged, then the cost of the electric cable is very high. Furthermore, since the length for each cable is not the same, which will cause tremendous difficulty for mass production and installation. Therefore, this design was adopted only at its early stage, but is seldom used thereafter because of its disadvantages.
The second design refers to a fixed address serial connection, of which a control circuit is installed in each lamp and a fixed address ID is assigned to each lamp, such that the system can operate as long as the power supply and the signal line are connected. Such system is simpler, but it has several drawbacks. Since each lamp requires a controller, therefore the cost is higher. In addition, each lamp requires a different ID, and thus making the manufacturing more difficult. Furthermore, it is necessary to change the ID of the spare parts for repair and maintenance purposes, thus causing some troubles.
The third design adopts a serially connected control circuit, which subdivides the controller as described in the abovementioned system and installs some part of the circuit in the lamp, and then all lamps are serially connected by an electric cable. Therefore, each time is seemingly identical and thus this design can simplify the level of difficulty for wiring, installing and maintaining the whole system.
Please refer to FIG. 7 for the block diagram of the foregoing third connection method. There are only 5 lamps 101a˜101e shown in the figure, and a minimal quantity of signal wires 102, 103 is required for the system, which includes a total of six lines such as a DAT, a Clock (CLK), a latch signal (STB), an output enable (OE) for controlling the brightness, a power supply (VDD) and a ground (GND) lines. Each lamp unit 101a˜101e uses the same line to connect the signal 103. Please refer to FIG. 8 for the internal structure of the lamp units 101a˜101e as depicted in FIG. 7, which comprises 4 sets of circuits for description. In actual practice, the number of circuits depends on the actual need. In FIG. 8, the signal group 210 is an input end, and the signal group 211 is an input end of another signal, and four sets of D-type latches 203a˜203d constitute a set of S-R shift registers and are driven by the external clock signal CLKI to save the external data DATI into the latches 203a˜203d in the proper order. In the meantime, the internal data are sent to the next lamp through another data line DATO. After the data is shifted to a fixed address, the external latch signal STB 1 will be outputted from four sets of D-type latches 203a˜203d to another set of D-type latches 203a˜202d and then sent to the LED driver circuit 201 to drive the external LEDs 213a˜213c. The buffers 204, 205, 206, 207 act as the buffers for the output of the CLK signal and data, the output of DATO latch signal, the output of STBO and the brightness output OEO respectively. The four connected signals DAT, CLK, STB and OE are the minimum requirement for such system. If there is an additional required function, the quantity of connecting wires will be increased. In view of the design that subdivides the central circuit to each lamp, the level of its originality is not high.
Since the method adopted by the foregoing method requires the connection of many circuits, and the lengths of the external connecting cables are different, and different lots of ICs have a slight difference such that the signal transmission error may occur easily (which will be illustrated by FIGS. 4 to 6), therefore the inventor of the present invention based on years of experience on designing and manufacturing similar system to invent and develop the control device in accordance with the invention to greatly improve the overall system stability as well as greatly reduce the required number of circuit connections.

Serially connected LED lamps control device


A lens plate integrator includes first and second lens plates which transmit light from a light source on an optical path to a projection plane. Each lens plate includes corresponding first and second groups of lens elements; light from the first group of the second plate is focused on a projection face in the projection plane, while light from the second group of the second plate is focused in front of or behind the projection plane and only partially illuminates the projection face.

The invention relates to an optical projection device comprising a light source and a lens plate integrator which comprises a first lens plate having a predeterminable number of lens elements and arranged in the optical path between the light source and a projection plane, and a second lens plate having a predeterminable number of lens elements and arranged in the optical path between the first lens plate and the projection plane. Light from the light source is imaged by means of the lens elements of the first lens plate on the lens elements of the second lens plate associated with the lens elements of the first lens plate, and the light beams of the lens elements of the second lens plate superimposed on the projection plane by means of a prismatic arrangement of the lens elements of the second lens plate or by means of a condenser lens.
In such optical projection devices, a very uniform illumination of a projection face in the projection plane is achieved by means of the lens plate integrator which comprises at least two lens plates each having a predeterminable number of lens elements. This means that the light on the projection face has a very homogeneous intensity distribution, i.e. particularly the light distribution in the center area and the peripheral areas of the projection face is substantially the same. Such optical projection devices including a lens plate integrator have the additional advantages that the light distribution on the projection plane or on the projection faces is quite insensitive to small variations of the position of the light source. Moreover, the device is insensitive to mechanical tolerances of the overall system. It is also insensitive to inhomogeneities of the light source itself, which may be caused, for example, by faults in the reflector, by electric wires, etc. Furthermore, the projection face is illuminated in homogeneous colors.
An optical projection device of this type is known, for example, from U.S. Pat. No. 5,418,583. In this device, the second lens plate of the lens plate integrator comprises additional lens elements of different sizes. The lens elements arranged at the periphery of the second lens plate are slightly smaller than those arranged in the center area so as to allow for the differently sized image of the light source on the lens elements of the second lens plate. In any case, this device also has for its object that each light beam passed through the lens elements of the second lens plate is imaged on the projection plane in a maximally uniform way and completely covers a projection face on this plane.

Optical projection devices including a lens plate integrator


The invention relates to a method for controlling at least two hydraulic actuators, to a monitoring valve and a rock drilling apparatus. The monitoring valve (10) is connected to the input channel of a first actuator through a sensing channel (9) and controls a load-sense circuit (6′) of a second actuator. The pressure of the load-sense circuit (6′) is set by a force of a spring element (12) and biased by a control element (42) of the monitoring valve with differential pressure sensing.

Load-sense circuits and valves are used more and more in hydraulic systems. Valves of this kind can be used in situations in which only one hydraulic pump provides the necessary flow and pressure to a hydraulic circuit having several actuators connected to it. With the load-sense valves, it is possible to control each of the actuators individually. The maximum pressure of the actuators can be controlled via pilot relief valves limiting the pressure of the load-sense lines.
In the case of two different actuators to be related by a pressure relation, a first actuator pressure can control a second actuator pressure in using a monitoring valve. The monitoring valve senses the pressure of first actuator and defines the load-sense pressure of the second actuator. Unfortunately, most monitoring valves induce unacceptable leaks from second circuit into the first circuit, and thus modify the first actuator's flow control. They also show high hysteresis, which is why their use in controlling pressures is difficult.

Monitoring valve, rock drilling apparatus and a method for controlling at least two hydraulic actuators to such a monitoring valve and rock drilling apparatus


A liquid discharging apparatus includes a head that is driven in response to a driving signal to discharge liquid, a controller that drives the head by generating the driving signal, an adjustment unit that adjusts the temperature of the liquid, and a supply path that supplies the head with the liquid having the temperature adjusted by the adjustment unit. The controller alters the driving signal in accordance with a flow amount of the liquid, which flows in the supply path.

1. Technical Field
The present invention relates to a liquid discharging apparatus, a liquid discharging method, and a program used therewith.
2. Related Art
Ink jet printers are known examples of liquid discharging apparatuses that discharge liquid. In a printer of this type, a head is supplied with ink, and the head is driven to discharge the ink.
A technology in which, when the ink is supplied to the head, the ink is heated by using a heater to heat a supply path for supplying the ink to the head has been proposed (see, for example, JP-A-2006-281454).
In a case in which the heater is installed at a position at a distance from the head, the ink heated by the heater naturally cools by the time it arrives at the head, and its temperature decreases. A manner in which the temperature of the ink decreases differs according to a natural cooling time. Thus, the temperature of the ink in the head differs according to a travel time (natural cooling time) from after the ink is heated by the heater until the ink arrives at the head. For example, in a case in which a flow amount of the ink in the supply path is large, the travel time is short. Thus, the ink in the head is warm. Alternatively, in a case in which the flow amount of the ink in the supply path is small, the travel time is long. Thus, the ink in the head is cool.
Such a change in temperature of the ink changes the viscosity of the ink. In addition, in a case where the head is similarly driven despite the change in viscosity of the ink, the amount of each ink droplet discharged from the head changes according to the viscosity of the ink. A problem of the change in the amount of the ink droplets discharged from the head is not limited to printers that discharge ink, and similarly occurs also in liquid discharging apparatuses that discharge liquid.

Liquid discharging apparatus, liquid discharging method, and program


The present invention relates to an electronic module, especially a storage module, having a strip on each of two opposite sides and a plastic substrate to accept and hold the electronic module in grooves in two U-shaped rails corresponding to the strips. The electronic module also has a plastic frame which accepts a fitted printed-circuit board and has at least one electrically conductive covering on either its upper and/or lower side and which extends as far as the strips and is connected to a reference potential. The electrical connection of the coverings to reference potential is ensured by contact components.

The present invention relates to an electronic module, especially a storage module, having a strip on each of two opposite sides and a plastic substrate to accept and hold the electronic module in grooves corresponding to the strips in the module substrate on a printed-circuit board.
By means of the electronic modules, which are accepted in a module substrate on a printed-circuit board, system components, like for example central controller modules or communications processors of programmable controllers, are realizable with a variable memory capacity. Depending on the requirement of the automation task, they can be provided with a memory of variable size. At the same time, the electronic module and the plastic substrate to accept the module on the printed-circuit board must meet the demands of industrial capability.

Electronic module and plastic substrate to accept and hold the electronic module


In one aspect, a MOS transistor includes a first diffusion region of a first doping type, a tap region of a second doping type configured to contact the first diffusion region, a channel region configured to substantially surround the first diffusion region and the tap region, and a second diffusion region of the first doping type configured to substantially surround the channel region. In another aspect, a method for manufacturing a MOS transistor includes, forming a first diffusion region of a first doping type, forming a tap region of a second doping type contacting the first diffusion region, forming a second diffusion region of the first doping type substantially surrounding the first diffusion region and the tap region, and forming a gate electrode substantially surrounding the first diffusion region and the tap region.

1. Field
The disclosure relates generally to semiconductor devices and, in particular, to metal-oxide-semiconductor (MOS) transistors.
2. Background
High-voltage MOS (HVMOS) transistors play an important role in wireless communication today. For example, a wireless device (e.g., a cellular phone or a smart phone) may transmit and receive data for two-way communication with a wireless communication system. The wireless device may include a transmitter for data transmission and a receiver for data reception. For data transmission, the transmitter may modulate a transmit local oscillator (LO) signal with data to obtain a modulated radio frequency (RF) signal, amplify the modulated RF signal to obtain an output RF signal having the desired output power level, and transmit the output RF signal via an antenna to a base station. For data reception, the receiver may obtain a received RF signal via the antenna, amplify and downconvert the received RF signal with a receive LO signal, and process the downconverted signal to recover data sent by the base station.
Typically, the RF functions operate at a higher voltage than the digital portions of the chipset within the wireless device. Because a higher breakdown voltage is needed, the HVMOS transistors may be utilized to provide power to the RF functions. However, those HVMOS transistors may not be integrated with the digital portions of the chipset within the wireless device. In one example, HVMOS transistors may require special steps and materials in the fabrication process. The HVMOS transistors would thus need to be fabricated separately from the digital components, adding to the manufacturing cost and consuming precious space within the wireless device.


A method is provided for preventing the formation of oxides in the process of creating a connection aperture through an insulating layer overlying a copper conductor having a connection surface region. The method deposits at least two insulation layers over the copper connection region including a nitride dielectric material adjacent the connection region, and a second insulating material adjacent the nitride layer. An area of the second insulator is selectively removed to partially form a connection aperture extending to the nitride layer. Next, an area of the nitride layer, and any layer overlying the nitride layer, is selectively removed to form an aperture in registration with the aperture formed in the second layer. The completed connection aperture extends through the entire insulating layer to the connection region. The nitride layer protects the copper from processes that cause oxidation as the layers overlying the nitride layer are removed. The present invention also provides an integrated circuit with at least two insulation layers overlying a copper connection region, with a nitride layer adjacent the connection region.

This invention relates generally to integrated circuits, and more particularly to a system and method of forming a via through dielectric material overlying a copper conductor in an integrated circuit.
Electrically conductive interconnects, used in the fabrication of integrated circuits and semiconductors, are an area of ongoing research. There is a need for interconnects and vias to have both low resistivity, and the ability to withstand volatile process environments. Aluminum and tungsten metals are often used in the production of integrated circuits for making interconnections or vias between electrically active areas. These metals are popular because they are easy to use in a production environment, unlike copper which requires special handling. Aluminum has a fairly good resistivity, approximately 2.65 .mu..OMEGA. cm. Aluminum oxides which are unintentionally formed in processing prevent good electrical connections, but are relatively easy to remove. Tungsten has a higher resistivity at approximately 6 .mu..OMEGA. cm, however, tungsten has advantages which makes its use desirable. These advantages include resistant to electromigration, or the ability maintain its electromechanical integrity, and also resistance to diffusion into surrounding materials. Further information about the relative merits of metals used in integrated circuits is found in, Mark J. Hampden-Smith and Tovia T. Kodas of University of New Mexico, "Copper Etching: New Chemical Approaches", MRS Bulletin, Feb. 23, 1993, pg. 2.
Copper has very good resistance to electromigration, approximately tens times better than aluminum. In addition, copper has extremely low resistivity at approximately 1.67 .mu..OMEGA. cm. One problem with copper is that it oxidizes easily, and the oxide is difficult to remove. Oxidized copper surfaces prevent reliable connections from being made with other conductors, and so oxidation interferes with electrical conductivity. As the complexity of integrated circuits (ICs) increases, so do the number of process steps, and the potential for unintentionally oxidizing connection surfaces. Therefore, despite copper's excellent electrical characteristics, it is infrequently used in the fabrication of integrated circuit interconnects.
The formation of multilayered, compact, integrated circuits with interconnecting vias requires anisotropic etching techniques. Anisotropic etching is directional so that the etching, or removal of material, is propagated in one direction, say the z axis, and not in the other directions, the x and y axes. Anisotropic etching allows for the formation of narrow, steep sided, wells and cylindrical vias between dielectric layers of an IC in a production environment. These vias are often used for interconnects between components at different layers of the IC.
One commercially prevalent form of anisotropic etching is the plasma etch. Plasma etching is performed in a chamber where an atmosphere of a relatively inert gas is introduced. The pressure of the gas and pump rates are controlled. A voltage across the chamber, at a predetermined frequency, is created to establish a flow of ions in a known direction. In addition, the temperature of the chamber, and the time of exposure to the ion flow, are controlled. As a consequence of the radio frequency voltage in the chamber, the relatively inert gas is transformed into a plasma consisting of ions and radicals. The ions and radicals react with the film layers on the IC wafer to form volatile etch products which perform the etching function on selected areas of the IC.
Oxygen is introduced in many plasma etch processes to help create the volatile etch product. One problem with the use of oxygen is that it promotes the oxidation of many metals. Tungsten is a popular interconnect material because it is relatively difficult to oxidize. Aluminum, although easily oxidized, is relatively easy to clean with standard solvents and etch techniques. Copper is also easily oxidized, and the oxides formed by copper are difficult to remove in an IC production environment. Therefore, even though copper's low resistivity makes it an attractive interconnect material, copper has been difficult to use in commercial integrated circuit fabrication where plasma etching, and other processes using oxygen, are common.
The development of smaller, and more densely constructed, integrated circuits necessitates the use of smaller interconnects and vias. The conductivity of the interconnects is reduced as the surface area of the interconnect is reduced, and the resulting increase in interconnect resistivity has become an obstacle in IC design. Conductors having high resistivity create conduction paths with high impedance and large propagation delays. These problems result in unreliable signal timing, unreliable voltage levels, and lengthy signal delays between components in the IC. Propagation discontinuities also result from intersecting conduction surfaces that are poorly connected, or from the joining of conductors having highly different resistivity characteristics. The size of interconnects can be halved by switching from aluminum to copper. Therefore, to meet he need for smaller interconnects, the search continues for a way to use metals, such as copper, in a way that promotes clean electrical connections.
It would be advantageous to employ a method of using copper as a low resistivity material in an interconnect or via between conductors on different layers of an integrated circuit.
It would also be advantageous if the formation of copper oxides could be prevented where copper is used in the fabrication of integrated circuits, and especially within integrated circuit via interconnects, where plasma etching, and other etching techniques using oxygen, are common.
It would also be advantageous if copper could be protected from oxidation with an insulator during processes that promote oxidation, with the insulator being easily removable at a later stage of IC processing. It would be advantageous if the copper insulator could be part of, or processed with, the dielectric films normally used to isolate electrically active sections in IC production.
Accordingly, in an integrated circuit, a method has been provided of connecting an electrical conductor to a connection surface of a copper conductor. The method comprises the step of depositing a multilayered dielectric material on the connection surface of the copper conductor, the multi-layered dielectric including first and second dielectric layers which are selectively etchable, with the first layer including nitride, the first layer located adjacent the connection surface, and the second layer extending over the first layer. The method also comprises the step of removing a portion of the second layer to form a via for an electrical conductor, the via extending to, but not through, the first layer. The method comprises the step of removing the remaining material in the via, including the first layer, to create a via, common to both the first and second layers, extending to the connection surface, whereby the connection surface is exposed to permit a connection to an electrical conductor through the via.
In a preferred form of the present invention, a method is provided for using an etchant to remove the second dielectric layer. A suitable etchant is an anisotropic plasma etch. The dielectric material of the second layer is selected, preferably, from a group consisting of tetraethyl orthosilicate (TEOS) oxide, silane, boron nitride (BN), and silicon dioxide.
An integrated circuit has also been provided comprising a copper conductor having a connection surface where an electrical connection is made to another conductor. The integrated circuit comprises a multilayered dielectric material deposited on the connection surface of the copper conductor, the multilayered dielectric including first and second dielectric layers having selective etchability, the first dielectric layer including nitride and located adjacent the connection surface, and the second dielectric layer extending over the first layer. The first and second layers have a common aperture therethrough to define a via extending to the connection surface for receiving the other conductor, whereby the nitride of the first layer protects the connection surface from oxidation during the creation of the via.
In a preferred form of the invention, the nitride layer is a thin film in the range of about 100 to 300 .ANG.. The nitride film is selected, preferably, from a group consisting of silicon nitride and boron nitride.

Method for preventing oxidation in the formation of a via in an integrated circuit


Tubing for use in gastrointestinal applications includes a hollow tube and a spring positioned inside the tube. The spring is corrosion resistant and helps to prevent kinking of the tubing when the tubing is bent. An encapsulant may be positioned over the spring. The spring may be co-extruded with the tubing.

Low profile gastrojejunostomy ("G-J") feeding tubes have been developed for use in smaller patients, such as pediatric patients, in small sizes such as 14 French. As the G-J feeding tubes are placed in younger and younger patients, the intestinal anatomy that the device is used in also becomes smaller. The jejunal portion of the small intestine in infants is very tight, compact and tortuous. The entire gastrointestinal tract fits in an abdominal cavity roughly the size of a softball. Each twist and turn of the jejunum must be navigated by the distal portion of the G-J device tube.
As the jejunal path becomes more tortuous, the probability of kinking of the G-J tube increases. If the tubing kinks, the device is rendered ineffective and must be replaced with a new device. Most patients that depend upon direct jejunal feedings for nutrition cannot tolerate a kinked tube for very long. Since most G-J device placements are performed by interventional radiology, the occurrence (or reoccurrence) of this expensive procedure, which is typically scheduled in advance, is something that hospitals and insurance companies would like to limit. Parents of pediatric patients would also like to reduce the time spent at the hospital, as well as the amount of radiation exposure to their children during fluoroscopy placements. Examples of kinked G-J tubing known in the prior art are shown in FIGS. 1 and 2. FIG. 1 depicts a kinked multi-lumen tube 2 and FIG. 2 depicts a kinked single lumen tube 4. As is evident, kinking involves restricting flow through the tubing either partially or entirely.


A robot system capable of performing automatic updating of data inherent to a robot mechanism section or a mechanical unit thereof when changing the robot mechanism section or the mechanical unit. After changing the robot mechanism section or the mechanical unit, data of identifiers are read by a robot control section from nonvolatile memories associated with encoders in the robot mechanism section or the mechanical unit automatically upon turning-on of a power supply on or a manual operation. If it is determined that a kind of the robot is changed, the data indicating the kind of robot is rewritten in the robot control section. If it is required to change an algorithm for forward/inverse transformation for calculation of a robot locus, the algorithm is changed. If a kind of the robot is not changed, it is determined whether individuality of the whole robot mechanism section or the mechanical unit is changed or not. If there is a change in the individuality, the data inherent to the individuality is read from the nonvolatile memories to update the corresponding data in the robot control section.

1. Field of the Invention
The present invention relates to a robot system for industrial use, and more particularly to a robot system comprising a mechanism section and a control section connected with each other, in which the whole or a part of the mechanism section is changeable.
2. Description of Related Art
In general, a robot system comprises a mechanism section (a robot mechanism including a base, arms and a wrist) and a control section (a robot controller) connected to the mechanism section, and the whole or a part of the mechanism section is required to be changed with another one because of failure, maintenance and other reasons. There is known to prepare a part of the mechanism section as a detachable mechanical unit.
In practice, after the whole mechanism section or a mechanical unit thereof is changed, if the robot is operated using data of an operation program used before the change, there is a case where a locus of an operational end of the robot is changed to fail in a proper operation of the robot. This is caused by a difference in individual dimensions and/or angular configurations of respective components of the mechanism section or the mechanical units even if a kind of the mechanical section (i.e. a kind of the robot) or a kind of mechanical unit (i.e. a design of the mechanical unit) is the same as that before the change.
Therefore, it has been necessary to perform calibration on the dimensions and/or the angular configuration of the mechanism section, or modification of taught data of the operation program in order to retain the same locus after the change of the whole mechanism section or the mechanical unit, requiring laborious works to lower efficiency of the robot system.


Techniques for profiling storage blocks in non-transitory memory (e.g., flash memory dies) to determine their retention capability, and assigning them with labels based on retention, are described. A superblock (SB) can be formed from physical blocks with the same labels located in different dies. The disclosed system and methods improve storage efficiency when the update frequency of stored data is non-uniform, as is typically the case. Moreover, the disclosed embodiments improve the reliability of solid state drives (SSDs), as well as reduce data refresh frequency and write amplification due to periodic refresh. A storage system can comprise a controller configured to obtain expected retention times for a plurality of storage blocks. The controller can partition the blocks into superblocks based on the retention times. A respective superblock is associated with a superblock retention time range, and contains blocks having expected retention times within the retention time range.

A solid state drive (SSD) can contain multiple flash memories, each of which typically contains thousands of physical flash memory blocks. Each flash block can retain data without loss even without a power source, for a relatively long period, such as a few days to a few years, depending on the age of the flash memory.
Due to process variations, each flash block can retain data for a different characteristic retention time. Likewise, different data files stored in flash memory may have different usage or update frequencies. Some data files may be updated in a shorter time, such as a few hours or a few days, while other data files may be updated in a longer time, e.g., a few months or even a few years. Existing SSD systems neglect the retention capability variation among different flash blocks, assigning data writes to blocks irrespective of the expected data update frequency.

Retention aware block mapping in flash-based solid state drives


A supporting structure applied in a display device is provided. The display device includes a casing and a display panel. The supporting structure comprises a fastening component and a sustaining component. The fastening component including a hook set is used for supporting the display panel. The sustaining component having a plurality of slot sets is disposed on the casing. The hook set separately presses against the slots for forming different distances between the display panel and the casing.

1. Field of the Invention
The invention relates in general to a supporting structure, and more particularly to a height-adjustable supporting structure applied in a display device.
2. Description of the Related Art
Liquid crystal display (LCD) device, having the features of light weight, slimness, small size, low power consumption, low radiation and low pollution, has gradually replaced conventional cathode ray tube (CRT) display device and become a standard item of equipment to a new generation computer.
Normally, a liquid crystal display device at least includes a casing and a panel. A plurality of supporting structures are disposed on the casing to support the panel. However, different panels manufactured by different manufacturers have different measures of thickness. In order to correspond to the panels with different measures of thickness, different sets of charge cores are developed to match the supporting structures with different measures of height, not only increasing the production cost but also reducing the production efficiency.

Supporting structure and display device using the same


A battery terminal shield comprises a base including a lower wall having an orifice for receiving a battery terminal and a cover including an upper wall and a peripheral wall extending downwardly from the periphery of the upper wall. Preferably, the cover includes an integral generally cylindrical hinge pin having opposite axial ends. The base preferably includes a pair of hinge sockets into which the hinge in snap fits to hingedly connect the cover to the base. Each of the hinge sockets comprises a locking finger flexing axially outwardly of the hinge pin upon insertion of the hinge pin.

This invention relates to a two-piece battery terminal shield having an improved hinge. Batteries on many current vehicles are provided with battery terminal shields which enclose the battery terminals and battery cable connectors. The battery shields protect the battery terminals and connections from corrosion and also prevent inadvertent contact with the terminals by a person working on the vehicle.
Current battery terminal shields comprise a generally planar base portion having a orifice for receiving the battery terminal. A cover generally comprises a generally planar upper wall and a peripheral wall extending downwardly from the periphery of the upper wall. The cover and base are molded together as a single piece and connected by a living hinge. A pair of latch windows extend upwardly from either side of the base portion. The peripheral wall of the cover includes a pair of latches which snap into the latch windows on the base. The peripheral wall of the cover is deformable inwardly to selectively release the latches from the latch windows to open the cover of the battery terminal shield.
Current designs of the battery terminal shields have several drawbacks. First, during manufacture, the living hinge must be opened and closed several times during or immediately after the molding of the base and cover in order to develop the living hinge. This additional step increases the manufacturing time and cost. Second, the living hinge becomes brittle in cold temperatures. This problem is exacerbated by the fact that access to battery terminals is often required during cold weather.

Battery terminal shield with improved hinge


A combined electrical and chemical stimulation lead is especially adapted for providing treatment to intervertebral discs. The combination lead may be placed proximate to intervertebral disc cellular matrix and nucleus pulposus tissue to promote tissue regeneration and repair, as well as nociceptor and neural tissue modulation. The stimulation lead includes electrodes that may be selectively positioned along various portions of the stimulation lead in order to precisely direct electrical energy to stimulate the target tissue. The lead also includes a central infusion passageway or lumen that communicates with various infusion ports spaced at selected locations along the lead to thereby direct the infusion of nutrients/chemicals to the target tissue.

It is known that immersing certain cell types within an electrical field will cause these cells to proliferate thus facilitating tissue repair. One known use of an electrical field for such repair is "in bone" stimulators that are implanted in fractures and/or spinal fusions. Another type of treatment has recently developed for spinal conditions wherein target tissue is stimulated by an electrical lead using radio-frequency energy to induce a thermal lesion in the target tissue. In this type of procedure, the therapeutic benefit is intended to derive from heating the target tissue and not from immersing the tissue in an electric field. Thus, the electrical lead in this treatment is strictly for use in heating the tissue, and there is no therapeutic electrical field generated. Chemical treatment of target tissues has also been developed by use of various types of infusion catheters.
For both electrical and thermal stimulation, an electrical current generator, commonly referred to as a pulse generator, may be used to transmit a pulse of electrical current to an implanted stimulation lead that has been precisely placed to transmit the electrical or thermal energy from the electrodes to the target tissue in order to treat the particular condition. For chemical stimulation, one or more drugs or nutrients are delivered by a pump that transfers a desired quantity and frequency of the drug/nutrient through an infusion port of the catheter to the target tissue. For chemical stimulation as well as electrical/thermal stimulation, implanted pumps and generators can be used to deliver the electrical and chemical stimulation as opposed to transdermal delivery devices. More particularly, implanted pulse generators (IPG) as well as implanted drug dispensers (IDP) are commonly used so that patients do not have to return to a medical facility each time treatment is to be conducted.
One relatively new procedure has been developed to treat discogenic back pain. As an alternative to other surgical procedures for patients who suffer from back pain caused by certain types of disc disorders, this new procedure is made possible by use of thermal stimulation leads that provide precise temperature control in the delivery of thermal energy to target tissue. This procedure, commonly referred to as intradiscal electrothermal annuloplasty (IDET) was initially believed to function by cauterizing nerve endings within the disc wall to assist in reduction of pain, and the heat produced by the stimulation leads would also thicken the collagen of the disc wall thereby promoting healing of the damaged disc. Due to age, injury or other conditions, cracks or fissures may develop in the wall of the invertebral disc causing a chronic source of pain in many patients. Additionally, the inner disc tissue (nucleus) will frequently cause the disc to bulge or herniate into the fissures in the outer region of the disc, thus causing nerve tissue therein to generate pain signals. IDET has proven in some cases to be a minimally invasive procedure to treat these types of disc ailments. However, recent research, and clinical experience has cast doubt on the reasons why the procedure results in a healing response of the target tissue. It is now believed that the thermal energy imparted to the disc creates an injury pattern that in some discs results in a repair response. The results of IDET are better characterized as inconsistent and this approach is a very inefficient and marginally effective means of producing a restorative response.
Combination electrical stimulators and chemical infusion catheters are known for purposes of treating various spine and brain ailments. One reference that discloses such a combination device is the invention in U.S. Publication No. US2004/0243206. This reference specifically discloses a combination electrical and stimulation lead for stimulation of a person's nerve tissue in the brain. One or more electrodes are located along the lead body and are adapted to be positioned proximate the target nerve tissue and to deliver electrical stimulation pulses transmitted through the lead to the target nerve tissue. One or more infusion ports located along the lead body are adapted for placement proximate the target nerve tissue and to deliver chemical stimulation pulses transmitted through the lead to the target nerve tissue.
While combination electrical and stimulation leads may be known, special considerations must be made for use of such devices for intervertebral disc treatment.
The intervertebral disc (IVD) provides separation, shock absorption, and controlled motion between vertebral bodies. The disc is comprised of a central nucleus of a semi-fluid mass of mucoid material, (nucleus pulposus), an outer more dense collagen ring (annulus fibrosis), and a thin, metabolically active cellular layer separating the nucleus and the outer collagen ring, referred to as the annular nuclear interface/transitional zone. Disc nutrition is tenuous at best and is provided by diffusion through the vertebral end plate in contact with the outer surface of the disc. As a result, a disc has limited ability to heal or regenerate.
Placement of a stimulation lead within a disc can be quite difficult. Because a disc does not have a uniform density, known stimulation leads can be quite difficult to place and may require the attending physician to make multiple attempts for proper placement or abandon the procedure. Of course, multiple placement attempts greatly increase the invasive nature of the procedure and therefore create unnecessary tissue damage and increased risk. Inability to perform the procedure denies the patient a therapeutic option. Improper placement of the stimulation lead can also result in the undesirable cauterization of nerve tissue that is not contributing to the chronic pain or other ailments. Because of the overall metabolically inactive nature of the disc, it is also important that chemical infusion be precisely targeted to contact the damaged area of the disc with the delivered chemicals/nutrients otherwise inaccurate delivery to non-damaged portions of the disc can reduce the effectiveness of the procedure. Thus, there is a need for a combination electrical and chemical stimulation lead that can be precisely placed with a high rate of success on a first attempt.
The IVD is also a motion segment of the body that is subjected to many flexion/extension/rotation cycles every day. In some procedures, it may be necessary to keep the stimulation lead emplaced for long periods of time, such as weeks or perhaps months. Thus, it is desirable to have a stimulation lead that maintains a small profile, yet is resilient enough to withstand the risk of permanent deformation or shearing during treatment and removal of the stimulation lead after treatment.

Combination electrical stimulating and infusion medical device


A semiconductor device includes a silicon substrate, a strain-inducing layer, a silicon layer, a FET, and an isolation region. On the silicon substrate, the strain-inducing layer is provided. On the strain-inducing layer, the silicon layer is provided. The strain-inducing layer induces lattice strain in a channel region of the FET in the silicon layer. The silicon layer includes the FET. The FET includes a source/drain region, an SD extension region, a gate electrode and a sidewall. The source/drain region and the strain-inducing layer are spaced from each other. Around the FET, the isolation region is provided. The isolation region penetrates the silicon layer so as to reach the strain-inducing layer.

1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
FIG. 7 is a cross-sectional view showing a conventional semiconductor device. In the semiconductor device 100, a SiGe epitaxial layer 102 and a silicon epitaxial layer 103 are sequentially stacked on a silicon substrate 101. The silicon epitaxial layer 103 includes a field effect transistor (hereinafter, FET) 110 constituted of a source/drain region 111, a gate electrode 112 and so forth. The FET 110 is isolated from other elements by a shallow trench isolation (hereinafter, STI) 104 formed around the FET 110.
Techniques related to the present invention are disclosed, for example, in Japanese Laid-open patent publication No. H10-284722 (patent document 1) and U.S. Pat. No. 6,121,100 Specification (patent document 2).

Semiconductor device and method of manufacturing the same


A positive resist composition comprising the components of: (A) a compound capable of generating an acid upon irradiation with one of an actinic ray and a radiation; (B) a resin that is insoluble or slightly soluble in alkalis, but becomes alkali-soluble under an action of an acid; (C) a basic compound; and (D) a compound comprising at least three hydroxyl groups or at least three substituted hydroxyl groups, and comprising at least one cyclic structure.

Chemical amplification positive resist compositions are materials that form patterns on substrates as follows. When irradiated with far ultraviolet radiation or the like, those resist compositions generate acids in the irradiated areas, and undergo reaction utilizing the acids as a catalyst to cause a difference in solubility in a developer between the areas unirradiated and irradiated with the actinic rays, thereby enabling pattern formation.
In the case where KrF excimer laser is an exposure light source, resins containing as their basic skeletons poly(hydroxystyrene) showing weak absorption in the region of 240 nm are used as a main component. Therefore, such resist compositions have high sensitivity and can form good-quality patterns at high resolution, compared with traditional resist compositions containing naphthoquinone-diazide/navolak resin combinations.
However, when light sources of shorter wavelengths, such as ArF exceimer laser (193 nm), are used for exposure, even the aforementioned resist compositions of chemical amplification type are not satisfactory, because compounds having aryl groups intrinsically show strong absorption at wavelengths around 193 nm.
On the other hand, utilization of poly(meth)acrylate as a polymer showing weak absorption in the region of 193 nm is described in J. Vac. Sci. Technol., B9, 3357 (1991). However, that polymer has a problem of being inferior to conventional phenol resins having aryl groups in resistance to dry etching generally carried out in the fabrication process for semiconductors.
In keeping with the recent trend toward finer patterning and higher throughput, it becomes increasingly important to reduce errors caused by exposure. The hitherto known resist compositions have narrow exposure margin and bad line edge roughness, which are impediments to heighten throughput.
Further, the recent finer patterning results in the aspect ratio being strict about the coating thickness also, and so the patterns formed have a tendency to topple easily. This tendency is observed noticeably in the cases of ArF resist, electron beam (EB) resist, vacuum ultraviolet (VUV) resist and extremely short ultraviolet (EUV) resist. Herein, the term "toppling of patterns" is intended to include all pattern-toppling phenomena regardless of what are their causes, e.g., whether the phenomenon is induced by lack of adhesion or coating strength.

This patent is subject to a terminal disclaimer.


A device for optical communication including a multilayer print circuit board in which a conductor circuit, an insulating layer, an optical circuit and an optical path for transmitting an optical signal are formed, and a package substrate having an optical element or an insulating layer and mounted on the multilayer print circuit board. An optical path converting member is disposed at the optical path to transmit an optical signal between the optical element and the optical circuit. The optical path converting member includes a lens and an optical path conversion mirror having an entrance surface, an exit surface and a reflection surface. The lens is provided at the entrance surface, the exit surface, or inside of the optical path conversion mirror.

1. Field of the Present Invention
The present invention relates to an optical path converting member, a multilayer print circuit board, and a device for optical communication.
2. Discussion of the Background
Recently, optical fibers are widely noticed especially in the field of communications. In particular, in the field of IT (information technology), communication technology using optical fibers is indispensable for building a high-speed network of the Internet.
In network communications such as the Internet, it is proposed to apply optical communication using optical fibers not only in communications of backbone networks, but also in communications between backbone network and terminal devices (personal computer, mobile unit, gaming machine, and the like), or communications between terminal devices.
As devices for optical communication usable in this kind of terminal devices of optical transmitting and receiving systems, the present inventors previously proposed a device for optical communication comprising a package substrate in which an optical path for transmitting an optical signal is formed, and an optical element is mounted on one side, and a substrate for a mother board provided at least with an optical waveguide (see, for example, JP-A 2004-004427).
On the other hand, when a light emitting element and a light receiving element are mounted on a circuit board in which an optical waveguide is formed to perform optical transmissions between the light emitting element and the emitting element, light from the light emitting element is irradiated to one end of the optical waveguide, and then emit from the other end of the optical waveguide to the light receiving element, and for this purpose, there has been proposed a method for reflecting the light by burying a optical path converting member at such as a prism at a predetermined position (see, for example, JP-A H07-159658).
Furthermore, there has been disclosed a photoelectric circuit board in which an optical waveguide film preliminarily provided with a mirror and a lens for optical path conversion is adhered to a substrate (see, for example, JP-A 2001-166167).
The contents of JP-A 2004-004427, JP-A H07-159658, and JP-A 2001-166167 are incorporated herein by reference in their entirety.

Optical path converting member, multilayer print circuit board, and device for optical communication


The present disclosure provides a control system of a buck converter, relating to the field of Internet of Things. The control system of a buck converter provided in an embodiment of the present disclosure includes a first control module, a second control module, and a mode selector. The first control module is turned on and the second control module is turned off through an analog current sensor in the mode selector when an IoT device switches from a transmission mode to a sleep mode or a standby mode, so that the first control module outputs a first voltage pulse to the driving and level shifter module, wherein a frequency of the first voltage pulse is determined by a frequency of a first clock in the first control module, and a width of the first voltage pulse is determined by a frequency of a second clock in the first control module.

With the development of science and technology, the applications of the Internet of Things (IoT) devices are becoming more and more extensive. It is estimated that in the near future, the IoT devices connected through the Internet will be more than 20 billion. The IoT devices are generally battery powered so as to be capable of continuously monitoring and collecting data in a physical environment during operation. Therefore, prolonging the service time of the battery is of important significance for improving the service life of the IoT.
The IoT devices generally use a power management unit to manage the battery, and a DC-DC (direct current-direct current) converter in the battery management unit can effectively output a fixed voltage after converting an input voltage, thus playing an important role in prolonging the service time of the battery. Generally, the range of load current of the IoT devices is large in different operation modes, such as sleep mode, standby mode, and transmission mode, and therefore, inductor-based DC-DC converters are more popular in such IoT device applications.
However, the existing inductor-based DC-DC converters will consume high quiescent current when the IoT devices are in the sleep mode or the standby mode, and cannot be adapted to a wide load current range or a wide input voltage range.


When reliability evaluation of the whole electronic package is performed, the time required for simulation is decreased, while solder connection parts, in particular, are accurately analyzed. The whole analysis model creating unit creates a solder connection part model which has the same volume, height, and connection area as the volume, height, and connection area of the solder connection part. By means of dividing the solder connection model into multiple meshes, the first mesh data for use in electronic package analysis is created.

Recently, electronic equipment such as personal computers and mobile telephones is highly integrated and greater packaging density is realized, and pitch fine design of an electronic package which is mounted for such electronic equipment has been developed at the same time. As the integration and downsizing of the electronic package proceed, concerns about reliability of packaging components, in particular, a solder connection part are increased.
Generally speaking, when a high density packaging is required for an electronic packaging, BGA (Ball Grid Array) or CSP (Chip Scale Package) is widely used. However, a solder connection part of such an electronic package is exposed to stress such as temperature change and fall impact force. Thus, in order to apply such electronic package to actual products, it is necessary to perform sufficient evaluation about strength reliability.
Previously, as a solder connection part strength (micro connection part strength) evaluation, there is an evaluation method with a CAE (Computer Aided Engineering) system based on the simulation technology such as a finite-element method. Today, evaluation with this CAE system is required in design and development of a new package.
However, in the evaluation with the CAE system, when the strength evaluation of the whole electronic package is performed, creation of simulation model and mesh data and simulation calculation need a significant amount of time, because the construction of the electronic package is complicated. Thus, it might take several days to obtain simulation result.
Hence, there is a following technique for evaluating an electronic package (see the following patent document 1). In the technique, to decrease the time necessary for simulation, the analysis model of the electronic package is subjected to rough element division to perform outline analysis of the whole electronic package. On the basis of the result of the outline analysis, a target solder bump is extracted, and the analysis model of the extracted solder bump is subjected to fine (dense) element division to perform detail analysis, thereby the electronic package is evaluated.
[Patent Document 1] Japanese Patent application Laid-open No. 2000-99550

Electronic package evaluation apparatus, electronic package optimizing apparatus, and computer-readable recording medium in which electronic package evaluation program is recorded


Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

Electronic systems are becoming a staple of modern life. These electronic systems may be very simple systems, such as individual logic gates that are used for simple control circuits, moderately complex systems, such as integrated logic circuits that are used for controllers and embedded processors, or much more complex systems utilized in powerful computing architectures.
Almost universally, the frequency and power requirements for these electronic systems have been increasing. This is especially true when referring to microprocessor based computing systems. Besides the display, the largest consumer of power in a computing system is the CPU microprocessor, and the higher the clock frequency of the microprocessor, the greater that microprocessor's power consumption (all other aspects being equal). As the power consumption and frequency of semiconductor devices grows so does the simultaneous switching noise (SSN) induced by the switching of the internal circuits of the semiconductor's core logic. This SSN is problematic, as it may cause interference with other aspects of the semiconductor's operation, with associated logic in other portions of the semiconductor, or with a device in which the semiconductor is utilized.
An effective way of suppressing this noise is to attach decoupling capacitors to the semiconductor, or a package containing the semiconductor. Because inductance and resistance between a semiconductor and its power source contributes significantly to the SSN, in most cases the closer decoupling capacitors are attached to a semiconductor device the smaller the SSN will be. FIG. 1 depicts a hierarchy of positions for the attachment of decoupling capacitors. Ideally, decoupling capacitors 110 will be coupled as closely to semiconductor 120 on package 130 as possible.
Additionally, the effectiveness of these decoupling capacitors is partially determined by how large the equivalent series inductance (ESL) and equivalent series resistance (ESR) are between the semiconductor and the decoupling capacitors. These factors are influenced, in main, by two variables: the type of decoupling capacitors used, and the path between these capacitors and the semiconductor in question.
To minimize the former variable, various low ESL and ESR decoupling capacitors are available from assorted vendors such as AVX, Murata and TDK. However, to minimize the latter variable is more difficult. Attaching the capacitors close to the semiconductor is one possible solution. To accomplish this, in many cases high-end microprocessors have decoupling capacitors coupled to the bottom side of the package with which they are utilized, usually just beneath the die to which the microprocessor is attached. FIG. 2 depicts one example of a method of attaching decoupling capacitors in close proximity to a semiconductor. Die 310 containing an integrated circuit, such as a microprocessor, is attached to substrate 220. BGA balls 230 serve to couple die 310 to a power source or other signal lines. Decoupling capacitors 380 may also be attached to the side of substrate 220 opposite die 310, placing them in close proximity to die 310.
Typically, substrate 220, with which microprocessors or semiconductors are packaged, is made of organic material (such as epoxy resin). Substrate 220 may be fabricated using build-up technology, which enables higher wiring capability by having fine-line build-up layer(s) on both sides of a coarser core substrate.
FIG. 3 illustrates a cross-sectional schematic of a package with an organic substrate 220. Package 300 consists of die 310 C4 bumps 320 build-up-layers 330, solder resist layers 340, microvias 350, core layer 360, plated through holes 370, and decoupling capacitors 380. Decoupling capacitors 380 are electrically coupled to the remainder of the package through pads in solder resist layer 330 of substrate 220. These pads are usually of a single polarity and are isolated from one another by solder resist. A terminal of decoupling capacitor 380 may be attached to one of these pads, usually by soldering. In package 300, therefore, the electrical path between operating device on die 310 and decoupling capacitors 380 flows through C4 bumps 320, microvias 350, plated through holes 360, microvias 350, pads in solder resist layer 340 to decoupling capacitors 380.
FIGS. 4A, 4B and 4C depict examples of decoupling capacitors for use with a semiconductor package like that pictured in FIG. 2. Decoupling capacitor 400 may have eight terminals 410–480 as pictured in FIG. 4A, and these terminals 410–480 may be of alternating polarity (i.e. interdigitated), as depicted in FIG. 4B. Two capacitors may have terminals with point symmetry to one another as depicted in FIGS. 4B and 4C. As can be seen, identical terminal 410-480 have opposite polarity in these capacitors. In one embodiment, capacitor 400 may be a four capacitor array. In other embodiments, capacitor 400 may be an interdigitated capacitor of the type manufactured by AVX, Murata and TDK.
FIG. 5A shows a typical pad opening layout for use in attaching decoupling capacitor 400 to a substrate. Pad openings 510–580 must be large enough for soldering one terminal 410–480 of decoupling capacitor 400. Recently, however, as the power consumption and frequency of semiconductors has increased, there has been a commensurate need for more decoupling capacitors 400 in a given package 300. Thus, to accommodate a higher density of decoupling capacitors 400, pad openings 510–580 have begun to shrink, as depicted in FIG. 5B. As a result of this shrinking pad opening 510–580 size, the number of microvias 350 contacting pad openings 510–580 has decreased. Not only does this decrease the mechanical reliability of pads and pad openings 510–580, but it also increases the ESR and ESL of the complete electrical path, the very problem trying to be avoided.
To help ameliorate these electrical and mechanical issues, a pad structure akin to the one depicted in FIG. 6 may be used. Pads 610–680 exist in solder resist layer 640. One pad opening 642 exists in each pad 640 for attaching terminals 410–480 of decoupling capacitor 400. One terminal 410–480 is attached to each soldering area of pad opening 612–682 within pad 610–680 having polarity matching terminal 410–480 being attached. Pad openings 612–682 may be defined on pad 610–680 by overlaying a solder mask layer on pads 610–680 during manufacturing of a package.
Using this pad structure, pads have been laid out in a solder resist layer of a substrate as depicted in FIG. 7. Pads 710, 720, 730 having alternating polarity, are laid out in solder resist 740. One pad opening 712, 722, 732 exists within each pad 710, 720, 730 for the coupling of a terminal 410–480 of decoupling capacitor 400 with corresponding polarity. Each pad 710, 720, 730 is separated from every other pad 710, 720, 730 by solder resist 740. Consequently, each pad 710, 720, 730 on substrate has only one pad opening 712, 722, 732.
Decoupling capacitor 400 of the type depicted in FIG. 4A may be attached on the back side of a substrate using this pattern of pads and pad openings with alternating polarity as shown in FIG. 8. Terminals 410–480 of capacitor 400 are attached to pad openings 812–882 of pads 810–880 with matching polarity. This solution, however, conflicts with the need for a high density of decoupling capacitors 400. Pads 810–880 are usually larger than pad openings 812–882 and must be isolated from one another by solder resist 890. Usually, 100–200 microns exists between individual pads 810–880. Consequently, in a given area, decoupling capacitors 400 may only be coupled to a substrate in as close a proximity to one another as the separation between individual pads 810–880 and their corresponding openings 812–882 allow.
Thus, a need exists for mechanically reliable methods and systems for attaching decoupling capacitors to a package which allow a high density of decoupling capacitors to be attached to a package while simultaneously decreasing both the ESL and ESR of the electrical path.

Method and system for a pad structure for use with a semiconductor package


A method of additive manufacturing of a three-dimensional object. The method comprises: sequentially dispensing and solidifying a plurality of layers comprising (i) a stack of model layers arranged in a configured pattern corresponding to the shape of the object and being made of a modeling material, (ii) a sacrificial structure having a stack of sacrificial layers made of an elastomeric material, and (iii) a stack of intermediate layers made of a support material having an elastic modulus less than the elastomeric material and being between the stack of model layers and the sacrificial structure; and applying a peeling force to the sacrificial structure (e.g., in dry environment) to remove the sacrificial structure, and to expose the stack of model layers and/or the stack of intermediate layers beneath the sacrificial structure.

The present invention, in some embodiments thereof, relates to additive manufacturing (AM), and, more particularly, but not exclusively, to method and system for additive manufacturing of peelable sacrificial structure.
Additive manufacturing (AM) is a technology enabling fabrication of arbitrarily shaped structures directly from computer data via additive formation steps. The basic operation of any AM system consists of slicing a three-dimensional computer model into thin cross sections, translating the result into two-dimensional position data and feeding the data to control equipment which fabricates a three-dimensional structure in a layerwise manner.
Additive manufacturing entails many different approaches to the method of fabrication, including three-dimensional (3D) printing such as 3D inkjet printing, electron beam melting, stereolithography, selective laser sintering, laminated object manufacturing, fused deposition modeling and others.
3D printing processes, for example, 3D inkjet printing, are being performed by a layer by layer inkjet deposition of building materials. Thus, a building material is dispensed from a dispensing head having a set of nozzles to deposit layers on a supporting structure. Depending on the building material, the layers may then be cured or solidified using a suitable device.
Various three-dimensional printing techniques exist and are disclosed in, e.g., U.S. Pat. Nos. 6,259,962, 6,569,373, 6,658,314, 6,850,334, 6,863,859, 7,183,335, 7,209,797, 7,225,045, 7,300,619, 7,500,846 and 9,031,680, all by the same Assignee, and being hereby incorporated by reference in their entirety.
The building material of a typical AM process, includes a model material (also referred to as "modeling material"), which is deposited to produce the desired object, and a support material (also referred to as "supporting material") which provides temporary support to specific regions of the object during building and for assuring adequate vertical placement of subsequent object layers. For example, in cases where objects include overhanging features or shapes, e.g., curved geometries, negative angles, voids, and the like, objects are typically constructed using adjacent support constructions, which are used during the printing and then subsequently removed in order to reveal the final shape of the fabricated object.
Known methods for removal of support materials include water-jet impact, chemical methods, such as dissolution in a solvent, oftentimes in combination with thermal treatment. For example, for water soluble support material, the fabricated object, including its support structure, is immersed in water capable of dissolving the support material.
Support materials for AM are described, for example, in U.S. Pat. Nos. 6,228,923, 7,255,825, 7,479,510, 7,183,335 and 6,569,373, all to the present Assignee and being incorporated by reference in their entirety.
U.S. Pat. No. 8,865,047, assigned to the present Assignee and being incorporated by reference in its entirety, discloses a method of constructing a support construction in which the support construction includes a strip that intersects the layers in a volume designed to be an empty space in the 3D object. The support construction is removed from the volume by application of a lifting force on the strip.

Method and system for additive manufacturing of peelable sacrificial structure